; -------------------------------------------------------------------------------- ; @Title: STM32N6 On-Chip Peripherals ; @Props: Released ; @Author: NEJ ; @Changelog: 2025-03-25 NEJ ; @Manufacturer: STM - ST Microelectronics N.V. ; @Doc: Generated (TRACE32, build: 178434.), based on: ; STM32N645.svd (Rev. 1.0), STM32N647.svd (Rev. 1.0), ; STM32N655.svd (Rev. 1.0), STM32N657.svd (Rev. 1.0) ; @Core: Cortex-M55 ; @Chip: STM32N645A0, STM32N645B0, STM32N645I0, STM32N645L0, ; STM32N645X0, STM32N645Z0, STM32N647A0, STM32N647B0, ; STM32N647I0, STM32N647L0, STM32N647X0, STM32N647Z0, ; STM32N655A0, STM32N655B0, STM32N655I0, STM32N655L0, ; STM32N655X0, STM32N655Z0, STM32N657A0, STM32N657B0, ; STM32N657I0, STM32N657L0, STM32N657X0, STM32N657Z0 ; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perstm32n6.per 19294 2025-03-26 15:35:28Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree.close "Core Registers (Cortex-M55)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 27. " EXTEXCLALL ,Disable critical AXI read under write" "No,Yes" bitfld.long 0x00 16.--17. " DISDI ,Disable dual-issue features" "None,Dual-issue,Swapping,Both" bitfld.long 0x00 15. " DISCRITAXIRUR ,Disable critical AXI read-under-read" "No,Yes" textline " " bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes" bitfld.long 0x00 11. " DISNWAMODE ,Disable no write allocate mode" "No,Yes" bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes" textline " " bitfld.long 0x00 7. " DISOLAP ,Disable overlapping of all instructions" "No,Yes" bitfld.long 0x00 6. " DISOLAPS ,Disable overlapping of scalar-only instructions" "No,Yes" bitfld.long 0x00 4. " DISLO ,Disable low overhead loops" "No,Yes" textline " " bitfld.long 0x00 3. " DISLOLEP ,Disable end of loop prediction in for low overhead loops" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes" group.long 0x0C++0x0F line.long 0x00 "CPPWR,Coprocessor Power Control Register" bitfld.long 0x00 21. " SUS10 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 15. " SUS7 ,State unknown secure only" "Both states,Secure only" textline " " bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 13. " SUS6 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted" textline " " bitfld.long 0x00 11. " SUS5 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 9. " SUS4 ,State unknown secure only" "Both states,Secure only" textline " " bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 7. " SUS3 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted" textline " " bitfld.long 0x00 5. " SUS2 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 3. " SUS1 ,State unknown secure only" "Both states,Secure only" textline " " bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 1. " SUS0 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted" line.long 0x04 "SYST_CSR,SysTick Control And Status Register" bitfld.long 0x04 16. " COUNTFLAG ,Counter flag" "Not counted,Counted" bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x04 1. " TICKINT ,Tick interrupt" "No SysTick,SysTick" textline " " bitfld.long 0x04 0. " ENABLE ,SysTick enable" "Disabled,Enabled" line.long 0x08 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x0C "SYST_CVR,SysTick Current Value Register" hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPUID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8.1-M w/ Main Extension" textline " " abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xD22=Cortex-M55" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control And State Register" setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes allows the PendSV exception for the selected security state to be set as pending on reads indicates whether the pendsv for the selected security state exception is pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes sets the SysTick exception as pending on reads indicates the current state of the exception" "Not pending,Pending" textline " " bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is secure or non-secure" "Secure,Non-secure" rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled" rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt generated by the NVIC is pending" "Not pending,Pending" textline " " hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt" rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent" hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address" line.long 0x08 "AIRCR,Application Interrupt And Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector key" rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian" bitfld.long 0x08 14. " PRIS ,Prioritize secure exceptions" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " BFHFNMINS ,BusFault HardFault and NMI non-secure enable" "Disabled,Enabled" bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping group priority field bits/subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" bitfld.long 0x08 5. " IESB ,Implicit ESB enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " DIT ,Data independent timing" "Not guaranteed,Guaranteed" bitfld.long 0x08 3. " SYSRESETREQS ,System reset request secure only" "Both states,Secure only" bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested" textline " " bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether on an exit from an ISR that returns to the base level of execution priority the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration And Control Register" bitfld.long 0x10 20. " TRD ,Enables checking for exception stack frame integrity signatures on SG instructions" "Disabled,Enabled" bitfld.long 0x10 19. " LOB ,Loop and branch info cache enable" "Disabled,Enabled" textline " " bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored" bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise bus faults on handlers running at a requested priority less than 0" "Not ignored,Ignored" bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled" line.long 0x14 "SHPR1,System Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7 SecureFault" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6 UsageFault" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5 BusFault" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4 MemManage" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11 SVCall" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15 SysTick" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14 PendSV" hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12 DebugMonitor" line.long 0x20 "SHCSR,System Handler Control And State Register" bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending" bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending" bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled" textline " " bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active" bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active" textline " " bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active" bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected security state" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active" group.byte 0xD28++0x01 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address valid flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,Stacking access violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking access violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data access violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction access violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address valid flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x01 line.word 0x00 "UFSR,Usage Fault Status Register" eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error" textline " " eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" eventfld.word 0x00 1. " INVSTATE ,Invalid combination of EPSR and instruction" "No error,Error" textline " " eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x0F line.long 0x00 "HFSR,HardFault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" eventfld.long 0x04 5. " PMU ,PMU event" "Not occurred,Occurred" eventfld.long 0x04 4. " EXTERNAL ,Eternal event" "Not occurred,Occurred" eventfld.long 0x04 3. " VCATCH ,Vector catch event" "Not occurred,Occurred" textline " " eventfld.long 0x04 2. " DWTTRAP ,Watchpoint event" "Not occurred,Occurred" eventfld.long 0x04 1. " BKPT ,Breakpoint event" "Not occurred,Occurred" eventfld.long 0x04 0. " HALTED ,Halt or step event" "Not occurred,Occurred" line.long 0x08 "MMFAR,MemManage Fault Address Register" line.long 0x0C "BFAR,BusFault Address Register" if ((per.b(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD29)&0x07)==0x07) rgroup.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred" bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR" bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred" bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred" bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred" textline " " bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred" bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR" bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred" bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred" bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred" bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR" bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred" bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred" elif ((per.b(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD29)&0x07)==0x06) rgroup.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred" bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred" textline " " bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR" bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred" bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred" bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred" bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred" bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR" bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred" bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred" bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred" elif ((per.b(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD29)&0x07)==0x05) rgroup.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred" bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR" bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred" bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred" bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred" bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR" bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred" bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred" bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred" elif ((per.b(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD29)&0x07)==0x04) rgroup.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred" bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred" bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR" textline " " bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred" bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred" elif ((per.b(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD29)&0x07)==0x03) rgroup.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred" bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR" bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred" bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred" bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred" textline " " bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred" bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR" bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred" bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred" elif ((per.b(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD29)&0x07)==0x02) rgroup.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred" bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred" textline " " bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR" bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred" bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred" bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred" elif ((per.b(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD29)&0x07)==0x01) rgroup.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred" bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR" bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred" bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred" else rgroup.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" endif group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,Reserved,Full" group.long 0xD8C++0x03 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 11. " CP11 ,Enables non-secure access to coprocessor CP11" "Disabled,Enabled" bitfld.long 0x00 10. " CP10 ,Enables non-secure access to coprocessor CP10" "Disabled,Enabled" bitfld.long 0x00 7. " CP7 ,Enables non-secure access to coprocessor CP7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CP6 ,Enables non-secure access to coprocessor CP6" "Disabled,Enabled" bitfld.long 0x00 5. " CP5 ,Enables non-secure access to coprocessor CP5" "Disabled,Enabled" bitfld.long 0x00 4. " CP4 ,Enables non-secure access to coprocessor CP4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CP3 ,Enables non-secure access to coprocessor CP3" "Disabled,Enabled" bitfld.long 0x00 2. " CP2 ,Enables non-secure access to coprocessor CP2" "Disabled,Enabled" bitfld.long 0x00 1. " CP1 ,Enables non-secure access to coprocessor CP1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CP0 ,Enables non-secure access to coprocessor CP0" "Disabled,Enabled" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Triggered Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended" wgroup.long 0x10700++0x03 line.long 0x00 "CFGINFOSEL,Processor Configuration Information Selection Register" rgroup.long 0x10704++0x03 line.long 0x00 "CFGINFORD,Processor Configuration Information Read Data Register" group.long 0x10004++0x03 line.long 0x00 "PFCR,Prefetcher Control Register" bitfld.long 0x00 0. " ENABLE ,Prefetcher enable" "Disabled,Enabled" tree "Memory System" width 10. rgroup.long 0xD78++0x03 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. " LOUU ,Level of unification uniprocessor" "Not implemented,Level 1,?..." bitfld.long 0x00 24.--26. " LOC ,Level of coherency" "Not implemented,Level 1,?..." textline " " bitfld.long 0x00 21.--23. " LOUIS ,Level of unification inner shareable" "Not implemented,Level 1,?..." bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000) rgroup.long 0xD7C++0x03 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,Reserved,Reserved,Reserved,Cache,?..." bitfld.long 0x00 24.--27. " CWG ,Cache write-back granule" "No Cache,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,?..." bitfld.long 0x00 20.--23. " ERG ,Exclusives reservation granule" "Not provided,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,?..." textline " " bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0xD7C++0x03 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,Reserved,Reserved,Reserved,Cache,?..." endif rgroup.long 0xD80++0x03 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Indicates support available for write-through" "Reserved,Supported" bitfld.long 0x00 30. " WB ,Indicates support available for write-back" "Reserved,Supported" bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Reserved,Supported" textline " " bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Reserved,Supported" hexmask.long.word 0x00 13.--27. 1. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1" hexmask.long.word 0x00 3.--12. 1. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "Reserved,32 bytes,?..." group.long 0xD84++0x03 line.long 0x00 "CSSELR,Cache Size Selection Register" rbitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..." bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction" wgroup.long 0xF50++0x03 line.long 0x00 "ICIALLU,I-Cache Invalidate All To PoU" wgroup.long 0xF58++0x1F line.long 0x00 "ICIMVAU,I-Cache Invalidate By MVA To PoU" line.long 0x04 "DCIMVAC,D-Cache Invalidate By MVA To PoC" line.long 0x08 "DCISW,D-Cache Invalidate By Set-Way" hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus 1" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x0C "DCCMVAU,D-Cache Clean By MVA To PoU" line.long 0x10 "DCCMVAC,D-Cache Clean By MVA To PoC" line.long 0x14 "DCCSW,D-Cache Clean By Set-Way" hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on minus" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x18 "DCCIMVAC,D-Cache Clean And Invalidate By MVA To PoC" line.long 0x1C "DCCISW,D-Cache Clean And Invalidate By Set-Way" hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on minus" "L1,L2,L3,L4,L5,L6,L7,L8" group.long 0x10010++0x0B line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register" bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register" bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x08 "PAHBCR,P-AHB Control Register" bitfld.long 0x08 1.--3. " SZ ,P-AHB size" "Disabled,64 MB,128 MB,256 MB,512 MB,?..." bitfld.long 0x08 0. " EN ,P-AHB enable" "Disabled,Enabled" group.long 0x10100++0x03 line.long 0x00 "IEBR0,Instruction Cache Error Bank Register 0" bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3" bitfld.long 0x00 16. " BANK ,Indicates which RAM bank to use" "Tag,Data" bitfld.long 0x00 15. " LOC_WAY ,Indicates the location in instruction cache RAM (way)" "0,1" hexmask.long.word 0x00 5.--14. 1. " LOC_INDEX ,Indicates the location in instruction cache RAM (index)" textline " " bitfld.long 0x00 2.--4. " LOC_OFFSET ,Indicates the location in instruction cache RAM (offset)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0x10104++0x03 line.long 0x00 "IEBR1,Instruction Cache Error Bank Register 1" bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3" bitfld.long 0x00 16. " BANK ,Indicates which RAM bank to use" "Tag,Data" bitfld.long 0x00 15. " LOC_WAY ,Indicates the location in instruction cache RAM (way)" "0,1" hexmask.long.word 0x00 5.--14. 1. " LOC_INDEX ,Indicates the location in instruction cache RAM (index)" textline " " bitfld.long 0x00 2.--4. " LOC_OFFSET ,Indicates the location in instruction cache RAM (offset)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0x10110++0x03 line.long 0x00 "DEBR0,Data Cache Error Bank Register 0" bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TYPE ,Indicates the error type" "Single-bit,Multi-bit" bitfld.long 0x00 16. " BANK ,Indicates which RAM bank to use" "Tag,Data" bitfld.long 0x00 14.--15. " LOC_WAY ,Indicates the location in instruction cache RAM (way)" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " LOC_INDEX ,Indicates the location in instruction cache RAM (index)" bitfld.long 0x00 2.--4. " LOC_OFFSET ,Indicates the location in instruction cache RAM (offset)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0x10114++0x03 line.long 0x00 "DEBR1,Data Cache Error Bank Register 1" bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TYPE ,Indicates the error type" "Single-bit,Multi-bit" bitfld.long 0x00 16. " BANK ,Indicates which RAM bank to use" "Tag,Data" bitfld.long 0x00 14.--15. " LOC_WAY ,Indicates the location in instruction cache RAM (way)" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " LOC_INDEX ,Indicates the location in instruction cache RAM (index)" bitfld.long 0x00 2.--4. " LOC_OFFSET ,Indicates the location in instruction cache RAM (offset)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0x10120++0x03 line.long 0x00 "TEBR0,TCM Error Bank Register 0" bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3" bitfld.long 0x00 28. " POISON ,Indicates whether a BusFault is generated or not" "Generated,Not generated" bitfld.long 0x00 27. " TYPE ,Indicates the error type" "Single-bit,Multi-bit" bitfld.long 0x00 24.--26. " BANK ,Indicates which RAM bank to use" "DTCM0,DTCM1,DTCM2,DTCM3,ITCM,?..." textline " " hexmask.long.tbyte 0x00 2.--23. 1. " LOCATION ,Indicates the location in data cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" rgroup.long (0x10120+0x04)++0x03 line.long 0x00 "TEBRDATA0,Data For TCU Error Bank Register 0" group.long 0x10128++0x03 line.long 0x00 "TEBR1,TCM Error Bank Register 1" bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3" bitfld.long 0x00 28. " POISON ,Indicates whether a BusFault is generated or not" "Generated,Not generated" bitfld.long 0x00 27. " TYPE ,Indicates the error type" "Single-bit,Multi-bit" bitfld.long 0x00 24.--26. " BANK ,Indicates which RAM bank to use" "DTCM0,DTCM1,DTCM2,DTCM3,ITCM,?..." textline " " hexmask.long.tbyte 0x00 2.--23. 1. " LOCATION ,Indicates the location in data cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" rgroup.long (0x10128+0x04)++0x03 line.long 0x00 "TEBRDATA1,Data For TCU Error Bank Register 1" group.long 0x10000++0x03 line.long 0x00 "MSCR,Memory System Control Register" bitfld.long 0x00 16. " DCCLEAN ,Data cache contains any dirty lines" "Contained,Not contained" bitfld.long 0x00 13. " ICACTIVE ,L1 instruction cache is active" "Not active,Active" bitfld.long 0x00 12. " DCACTIVE ,L1 data cache is active" "Not active,Active" textline " " bitfld.long 0x00 3. " EVECCFAULT ,Enables asynchronous BusFault exceptions when data is lost on evictions" "Disabled,Enabled" bitfld.long 0x00 2. " FORCEWT ,Enables forced write-through in the L1 data cache" "Disabled,Enabled" bitfld.long 0x00 1. " ECCEN ,Indicates whether error correcting code is present and enabled" "Disabled,Enabled" group.long 0x10200++0x07 line.long 0x00 "DCADCRR,Direct Cache Access Read Register" bitfld.long 0x00 23.--25. " STATUS ,Clean or dirty transient and outer attributes of the cache line" "0,1,2,3,4,5,6,7" bitfld.long 0x00 22. " VALID ,Valid state of the data cache line entry" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--21. 0x01 " TAG ,Tag address" line.long 0x04 "DCAICRR,Direct Cache Access Read Register" bitfld.long 0x04 21. " VALID ,Valid state of the instruction cache line" "Not valid,Valid" hexmask.long.tbyte 0x04 0.--20. 0x01 " TAG ,Tag address" rgroup.long 0x10210++0x07 line.long 0x00 "DCADCLR,Direct Cache Access Location Register" bitfld.long 0x00 30.--31. " WAY ,Cache way" "0,1,2,3" hexmask.long.word 0x00 5.--13. 1. " SET ,Set index" bitfld.long 0x00 2.--4. " OFFSET ,Data offset" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " RAMTYPE ,RAM type" "Tag,Data" line.long 0x04 "DCAICLR,Direct Cache Access Location Register" bitfld.long 0x04 30. " WAY ,Cache way" "0,1" hexmask.long.word 0x04 5.--14. 1. " SET ,Set index" bitfld.long 0x04 2.--4. " OFFSET ,Data offset" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " RAMTYPE ,RAM type" "Tag,Data" tree.end tree "Feature Registers" width 10. rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " RAS ,Identifies which version of the RAS architecture is implemented" "Reserved,Reserved,Version 1,?..." bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" "Reserved,Reserved,2-stack,?..." bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,Reserved,Implemented with state handling,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 28.--31. " UDE ,Unprivileged debug extension" "Not implemented,Implemented,?..." bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug indicates the supported M-profile debug architecture" "Not supported,Reserved,ARMv8-M Debug architecture,?..." rgroup.long 0xD4C++0x03 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for auxiliary registers" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,Indicates the support for tightly coupled memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Reserved,Reserved,Reserved,Reserved,PMSAv8,?..." rgroup.long 0xD54++0x03 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for wait for interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD5C++0x03 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..." rgroup.long 0xD60++0x03 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Reserved,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Reserved,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Reserved,CBNZ/CBZ,Reserved,CBNZ/CBZ with looping,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Reserved,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Reserved,CLZ supported,?..." rgroup.long 0xD64++0x03 line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported interworking instructions" "Reserved,Reserved,BX/BLX,?..." bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Reserved,Reserved,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Reserved,IT,?..." textline " " bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported extend instructions" "Reserved,Basic,Extended,?..." rgroup.long 0xD68++0x03 line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Reserved,Reserved,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Reserved,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Reserved,SMULL/SMLAL,Reserved,SMULL/SMLAL/DSP,?..." textline " " bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Reserved,Reserved,MUL/MLA/MLS,?..." bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Reserved,Reserved,Reserved,PLD/PLI,?..." textline " " bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Reserved,Reserved,Load-acquire/Store-release/Exclusive,?..." rgroup.long 0xD6C++0x03 line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " T32COPY ,Indicates the supported non flag-setting MOV instructions" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported table branch instructions" "Reserved,TBB/TBH,?..." textline " " bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported table branch instructions" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Reserved,SVC,?..." bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Reserved,Supported,Reserved,Extended,?..." textline " " bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..." rgroup.long 0xD70++0x03 line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Reserved,CPS/MRS/MSR,?..." bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicate the implemented synchronization primitive instructions" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported barrier instructions" "Reserved,CSDB/DMB/DSB/ISB/PSSBB/SSBB,?..." textline " " bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Reserved,Reserved,Supported,?..." rgroup.long 0xD74++0x03 line.long 0x00 "ID_ISAR5,Instruction Set Attributes Register 5" tree.end base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000) rgroup.long 0xFBC++0x03 line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "M-Profile V3.0,?..." textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "Reserved,Reserved,M-Profile V3.0,?..." hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" else rgroup.long 0xFBC++0x03 line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" endif rgroup.long 0xFCC++0x03 line.long 0x00 "DDEVTYPE,SCS Device Type Register" bitfld.long 0x00 4.--7. " SUB ,Component sub-type" "Other,?..." bitfld.long 0x00 0.--3. " MAJOR ,CoreSight major type" "Miscellaneous,?..." rgroup.long 0xCFC++0x03 line.long 0x00 "REVIDR,Revision ID Register" tree "Peripheral Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "DPIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]" line.long 0x04 "DPIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]" line.long 0x08 "DPIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "DPIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x0F line.long 0x00 "DPIDR4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" line.long 0x04 "DPIDR5,Peripheral Identification Register 5" line.long 0x08 "DPIDR6,Peripheral Identification Register 6" line.long 0x0C "DPIDR7,Peripheral Identification Register 7" rgroup.long 0xFF0++0x0F line.long 0x00 "DCIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "DCIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class preamble" line.long 0x08 "DCIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0C "DCIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end tree "Reliability, Availability, and Serviceability" base (CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))-0x9000) rgroup.long 0x00++0x03 line.long 0x00 "ERRFR0,RAS Error Record Feature Register" bitfld.long 0x00 8.--9. " UE ,Enable uncorrected error" "Reserved,Enabled,?..." bitfld.long 0x00 0.--1. " ED ,Error reporting and logging" "Reserved,Enabled,?..." rgroup.long 0x08++0x03 line.long 0x00 "ERRCTRL0,ERRCTRL0" group.long 0x10++0x03 line.long 0x00 "ERRSTATUS0,RAS Error Record Primary Status Register" eventfld.long 0x00 31. " AV ,Address valid" "Not valid,Valid" bitfld.long 0x00 30. " V ,Status valid" "Not valid,Valid" eventfld.long 0x00 29. " UE ,Uncorrected errors" "Not detected,Detected" eventfld.long 0x00 28. " ER ,BusFault caused by RAS" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " OF ,RAS event has occurred since the last time ERRSTATUS0.V was cleared" "At most one,At least two" eventfld.long 0x00 26. " MV ,Miscellaneous registers valid" "Not valid,Valid" bitfld.long 0x00 24.--25. " CE ,Corrected errors" "Not detected,Reserved,Detected,?..." eventfld.long 0x00 23. " DE ,Deferred errors" "No deferred,Deferred" textline " " bitfld.long 0x00 20.--21. " UET ,Uncorrectable error type" "Reserved,UC,Reserved,UER" bitfld.long 0x00 0.--7. " SERR ,Architecturally-defined primary error code" "No error,Reserved,TCM ECC,Reserved,Reserved,Reserved,Data RAM ECC,Tag RAM ECC,?..." rgroup.long 0x18++0x07 line.long 0x00 "ERRADDR0,RAS Error Record Address Register" line.long 0x04 "ERRADDR20,RAS Error Record Address Register" bitfld.long 0x04 30. " SI ,Security information incorrect" "Reserved,Not valid" bitfld.long 0x04 29. " AI ,Address incorrect" "Valid,Not valid" rgroup.long 0x20++0x1F line.long 0x00 "ERRMISC00,Error Record Miscellaneous Register 00" line.long 0x04 "ERRMISC10,Error Record Miscellaneous Register 10" bitfld.long 0x04 0.--1. " TYPE ,Indicates the type of RAS event logged" "L1 instruction,L1 data,By processor,S-AHB" line.long 0x08 "ERRMISC20,Error Record Miscellaneous Register 20" line.long 0x0C "ERRMISC30,Error Record Miscellaneous Register 30" line.long 0x10 "ERRMISC40,Error Record Miscellaneous Register 40" line.long 0x14 "ERRMISC50,Error Record Miscellaneous Register 50" line.long 0x18 "ERRMISC60,Error Record Miscellaneous Register 60" line.long 0x1C "ERRMISC70,Error Record Miscellaneous Register 70" rgroup.long 0xE00++0x03 line.long 0x00 "ERRGSR0,RAS Fault Group Status Register" bitfld.long 0x00 0. " ERR0 ,Error record 0 valid" "Not valid,Valid" rgroup.long 0xFC8++0x03 line.long 0x00 "ERRDEVID,RAS Error Record Device ID Register" hexmask.long.word 0x00 0.--15. 1. " NUM ,Maximum error record index+1" group.long 0x9F04++0x03 line.long 0x00 "RFSR,RAS Fault Status Register" bitfld.long 0x00 31. " VALID ,Indicates whether the register is valid" "Not valid,Valid" bitfld.long 0x00 16.--30. " IS ,Implementation-defined syndrome" "L1 instruction,L1 data,TCM ECC,?..." bitfld.long 0x00 0.--1. " UET ,Error type" "Uncontainable,Reserved,Reserved,Recoverable" tree.end tree "TCM security gate" base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) group.long 0x10500++0x03 line.long 0x00 "ITGU_CTRL,ITGU Control Register" bitfld.long 0x00 1. " DEREN ,Enable slave AHB error response for TGU fault" "Disabled,Enabled" bitfld.long 0x00 0. " DBFEN ,Enable data side BusFault for TGU fault" "Disabled,Enabled" rgroup.long 0x10504++0x03 line.long 0x00 "ITGU_CFG,ITGU Configuration Register" bitfld.long 0x00 31. " PRESENT ,This field determines if the TGU is present" "Not present,Present" bitfld.long 0x00 8.--11. " NUMBLKS ,Number of TCM blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " BLKSZ ,TGU block size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10510++0x03 line.long 0x00 "ITGU_LUT0,ITGU Look Up Table Register 0" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10514++0x03 line.long 0x00 "ITGU_LUT1,ITGU Look Up Table Register 1" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10518++0x03 line.long 0x00 "ITGU_LUT2,ITGU Look Up Table Register 2" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x1051C++0x03 line.long 0x00 "ITGU_LUT3,ITGU Look Up Table Register 3" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10520++0x03 line.long 0x00 "ITGU_LUT4,ITGU Look Up Table Register 4" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10524++0x03 line.long 0x00 "ITGU_LUT5,ITGU Look Up Table Register 5" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10528++0x03 line.long 0x00 "ITGU_LUT6,ITGU Look Up Table Register 6" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x1052C++0x03 line.long 0x00 "ITGU_LUT7,ITGU Look Up Table Register 7" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10530++0x03 line.long 0x00 "ITGU_LUT8,ITGU Look Up Table Register 8" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10534++0x03 line.long 0x00 "ITGU_LUT9,ITGU Look Up Table Register 9" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10538++0x03 line.long 0x00 "ITGU_LUT10,ITGU Look Up Table Register 10" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x1053C++0x03 line.long 0x00 "ITGU_LUT11,ITGU Look Up Table Register 11" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10540++0x03 line.long 0x00 "ITGU_LUT12,ITGU Look Up Table Register 12" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10544++0x03 line.long 0x00 "ITGU_LUT13,ITGU Look Up Table Register 13" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10548++0x03 line.long 0x00 "ITGU_LUT14,ITGU Look Up Table Register 14" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x1054C++0x03 line.long 0x00 "ITGU_LUT15,ITGU Look Up Table Register 15" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10600++0x03 line.long 0x00 "DTGU_CTRL,DTGU Control Register" bitfld.long 0x00 1. " DEREN ,Enable slave AHB error response for TGU fault" "Disabled,Enabled" bitfld.long 0x00 0. " DBFEN ,Enable data side BusFault for TGU fault" "Disabled,Enabled" rgroup.long 0x10604++0x03 line.long 0x00 "DTGU_CFG,DTGU Configuration Register" bitfld.long 0x00 31. " PRESENT ,This field determines if the TGU is present" "Not present,Present" bitfld.long 0x00 8.--11. " NUMBLKS ,Number of TCM blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " BLKSZ ,TGU block size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10610++0x03 line.long 0x00 "DTGU_LUT0,DTGU Look Up Table Register 0" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10614++0x03 line.long 0x00 "DTGU_LUT1,DTGU Look Up Table Register 1" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10618++0x03 line.long 0x00 "DTGU_LUT2,DTGU Look Up Table Register 2" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x1061C++0x03 line.long 0x00 "DTGU_LUT3,DTGU Look Up Table Register 3" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10620++0x03 line.long 0x00 "DTGU_LUT4,DTGU Look Up Table Register 4" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10624++0x03 line.long 0x00 "DTGU_LUT5,DTGU Look Up Table Register 5" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10628++0x03 line.long 0x00 "DTGU_LUT6,DTGU Look Up Table Register 6" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x1062C++0x03 line.long 0x00 "DTGU_LUT7,DTGU Look Up Table Register 7" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10630++0x03 line.long 0x00 "DTGU_LUT8,DTGU Look Up Table Register 8" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10634++0x03 line.long 0x00 "DTGU_LUT9,DTGU Look Up Table Register 9" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10638++0x03 line.long 0x00 "DTGU_LUT10,DTGU Look Up Table Register 10" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x1063C++0x03 line.long 0x00 "DTGU_LUT11,DTGU Look Up Table Register 11" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10640++0x03 line.long 0x00 "DTGU_LUT12,DTGU Look Up Table Register 12" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10644++0x03 line.long 0x00 "DTGU_LUT13,DTGU Look Up Table Register 13" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x10648++0x03 line.long 0x00 "DTGU_LUT14,DTGU Look Up Table Register 14" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" group.long 0x1064C++0x03 line.long 0x00 "DTGU_LUT15,DTGU Look Up Table Register 15" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" textline " " bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RLAR0,MPU Region Attribute And Size Register 0" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RLAR0,MPU Region Attribute And Size Register 0" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RLAR1,MPU Region Attribute And Size Register 1" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RLAR1,MPU Region Attribute And Size Register 1" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RLAR2,MPU Region Attribute And Size Register 2" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RLAR2,MPU Region Attribute And Size Register 2" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RLAR3,MPU Region Attribute And Size Register 3" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RLAR3,MPU Region Attribute And Size Register 3" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RLAR4,MPU Region Attribute And Size Register 4" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RLAR4,MPU Region Attribute And Size Register 4" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RLAR5,MPU Region Attribute And Size Register 5" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RLAR5,MPU Region Attribute And Size Register 5" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RLAR6,MPU Region Attribute And Size Register 6" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RLAR6,MPU Region Attribute And Size Register 6" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RLAR7,MPU Region Attribute And Size Register 7" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RLAR7,MPU Region Attribute And Size Register 7" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RLAR8,MPU Region Attribute And Size Register 8" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RLAR8,MPU Region Attribute And Size Register 8" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RLAR9,MPU Region Attribute And Size Register 9" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RLAR9,MPU Region Attribute And Size Register 9" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RLAR10,MPU Region Attribute And Size Register 10" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RLAR10,MPU Region Attribute And Size Register 10" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RLAR11,MPU Region Attribute And Size Register 11" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RLAR11,MPU Region Attribute And Size Register 11" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RLAR12,MPU Region Attribute And Size Register 12" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RLAR12,MPU Region Attribute And Size Register 12" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RLAR13,MPU Region Attribute And Size Register 13" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RLAR13,MPU Region Attribute And Size Register 13" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RLAR14,MPU Region Attribute And Size Register 14" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RLAR14,MPU Region Attribute And Size Register 14" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RLAR15,MPU Region Attribute And Size Register 15" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" newline hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RLAR15,MPU Region Attribute And Size Register 15" endif tree.end newline group.long 0xDA4++0x07 line.long 0x00 "MPU_RBAR_A1,MPU Region Base Address Register Alias 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR_A1,MPU Region Limit Address Register Alias 1" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" group.long 0xDAC++0x07 line.long 0x00 "MPU_RBAR_A2,MPU Region Base Address Register Alias 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR_A2,MPU Region Limit Address Register Alias 2" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" group.long 0xDB4++0x07 line.long 0x00 "MPU_RBAR_A3,MPU Region Base Address Register Alias 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR_A3,MPU Region Limit Address Register Alias 3" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" newline bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" newline group.long 0xDC0++0x07 line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1" bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Security Attribution Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. group.long 0xDD0++0x03 line.long 0x00 "SAU_CTRL,SAU Control Register" bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or secure" "Secure,Non-secure" bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled" rgroup.long 0xDD4++0x03 line.long 0x00 "SAU_TYPE,SAU Type Register" bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..." group.long 0xDD8++0x03 line.long 0x00 "SAU_RNR,SAU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR" tree.close "SAU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0 group.long 0xDDC++0x03 "Region 0" saveout 0xDD8 %l 0x0 line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x0 line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 0 (not implemented)" saveout 0xDD8 %l 0x0 hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x0 hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1 group.long 0xDDC++0x03 "Region 1" saveout 0xDD8 %l 0x1 line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x1 line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 1 (not implemented)" saveout 0xDD8 %l 0x1 hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x1 hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2 group.long 0xDDC++0x03 "Region 2" saveout 0xDD8 %l 0x2 line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x2 line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 2 (not implemented)" saveout 0xDD8 %l 0x2 hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x2 hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3 group.long 0xDDC++0x03 "Region 3" saveout 0xDD8 %l 0x3 line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x3 line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 3 (not implemented)" saveout 0xDD8 %l 0x3 hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x3 hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4 group.long 0xDDC++0x03 "Region 4" saveout 0xDD8 %l 0x4 line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x4 line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 4 (not implemented)" saveout 0xDD8 %l 0x4 hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x4 hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5 group.long 0xDDC++0x03 "Region 5" saveout 0xDD8 %l 0x5 line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x5 line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 5 (not implemented)" saveout 0xDD8 %l 0x5 hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x5 hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6 group.long 0xDDC++0x03 "Region 6" saveout 0xDD8 %l 0x6 line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x6 line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 6 (not implemented)" saveout 0xDD8 %l 0x6 hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x6 hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7 group.long 0xDDC++0x03 "Region 7" saveout 0xDD8 %l 0x7 line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x7 line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 7 (not implemented)" saveout 0xDD8 %l 0x7 hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x7 hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" endif tree.end newline group.long 0xDE4++0x03 line.long 0x00 "SFSR,Secure Fault Status Register" bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred" bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid" bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred" bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred" bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred" bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred" group.long 0xDE8++0x03 line.long 0x00 "SFAR,Secure Fault Address Register" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total number of interrupt" "0-31,0-63,0-95,0-127,0-159,0-191,0-223,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,?..." wgroup.long 0x10400++0x03 line.long 0x00 "EVENTSPR,Event Set Pending Register" bitfld.long 0x00 2. " EDBGREQ ,External debug request has occurred" "Not occurred,Occurred" bitfld.long 0x00 1. " NMI ,Non-maskable interrupt has occurred" "Not occurred,Occurred" bitfld.long 0x00 0. " EVENT ,RXEV event has occurred" "Not occurred,Occurred" rgroup.long 0x10480++0x03 line.long 0x00 "EVENTMASKA,Wake-Up Event Mask Register" bitfld.long 0x00 2. " EDBGREQ ,Mask for external debug request" "0,1" bitfld.long 0x00 1. " NMI ,Mask for non-maskable interrupt" "Not occurred,Occurred" rgroup.long 0x10484++0x03 line.long 0x00 "EVENTMASK0,Wake-up Event Mask Register 0" rgroup.long 0x10488++0x03 line.long 0x00 "EVENTMASK1,Wake-up Event Mask Register 1" rgroup.long 0x1048C++0x03 line.long 0x00 "EVENTMASK2,Wake-up Event Mask Register 2" rgroup.long 0x10490++0x03 line.long 0x00 "EVENTMASK3,Wake-up Event Mask Register 3" rgroup.long 0x10494++0x03 line.long 0x00 "EVENTMASK4,Wake-up Event Mask Register 4" rgroup.long 0x10498++0x03 line.long 0x00 "EVENTMASK5,Wake-up Event Mask Register 5" rgroup.long 0x1049C++0x03 line.long 0x00 "EVENTMASK6,Wake-up Event Mask Register 6" rgroup.long 0x104A0++0x03 line.long 0x00 "EVENTMASK7,Wake-up Event Mask Register 7" rgroup.long 0x104A4++0x03 line.long 0x00 "EVENTMASK8,Wake-up Event Mask Register 8" rgroup.long 0x104A8++0x03 line.long 0x00 "EVENTMASK9,Wake-up Event Mask Register 9" rgroup.long 0x104AC++0x03 line.long 0x00 "EVENTMASK10,Wake-up Event Mask Register 10" rgroup.long 0x104B0++0x03 line.long 0x00 "EVENTMASK11,Wake-up Event Mask Register 11" rgroup.long 0x104B4++0x03 line.long 0x00 "EVENTMASK12,Wake-up Event Mask Register 12" rgroup.long 0x104B8++0x03 line.long 0x00 "EVENTMASK13,Wake-up Event Mask Register 13" rgroup.long 0x104BC++0x03 line.long 0x00 "EVENTMASK14,Wake-up Event Mask Register 14" width 24. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt set/clear enable bit" "Disabled,Enabled" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x104++0x03 line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x104++0x03 hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x108++0x03 line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x108++0x03 hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x10C++0x03 line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x10C++0x03 hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x110++0x03 line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x110++0x03 hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x114++0x03 line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x114++0x03 hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x118++0x03 line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x118++0x03 hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x11C++0x03 line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x11C++0x03 hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x120++0x03 line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x120++0x03 hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x124++0x03 line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x124++0x03 hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x128++0x03 line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x128++0x03 hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x12C++0x03 line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x12C++0x03 hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x130++0x03 line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x130++0x03 hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x134++0x03 line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x134++0x03 hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x138++0x03 line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt set/clear enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x138++0x03 hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register" endif tree.end width 24. tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt set/clear pending" "Not pending,Pending" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x204++0x03 line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x204++0x03 hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x208++0x03 line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x208++0x03 hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x20C++0x03 line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x20C++0x03 hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x210++0x03 line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x210++0x03 hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x214++0x03 line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x214++0x03 hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x218++0x03 line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x218++0x03 hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x21C++0x03 line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x21C++0x03 hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x220++0x03 line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x220++0x03 hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x224++0x03 line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x224++0x03 hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x228++0x03 line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x228++0x03 hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x22C++0x03 line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x22C++0x03 hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x230++0x03 line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x230++0x03 hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x234++0x03 line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x234++0x03 hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x238++0x03 line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt set/clear pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x238++0x03 hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register" endif tree.end width 11. tree "Interrupt Active Bit Registers" rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE0,Active Bit Register 0" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt active flag" "Not active,Active" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) rgroup.long 0x304++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE63 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE62 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE61 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE60 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE59 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE58 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE57 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE56 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE55 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE54 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE53 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE52 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE51 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE50 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE49 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE48 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE47 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE46 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE45 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE44 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE43 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE42 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE41 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE40 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE39 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE38 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE37 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE36 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE35 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE34 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE33 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE32 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x304++0x03 hide.long 0x00 "ACTIVE1,Active Bit Register 1" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) rgroup.long 0x308++0x03 line.long 0x00 "ACTIVE2,Active Bit Register 2" bitfld.long 0x00 31. " ACTIVE95 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE94 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE93 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE92 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE91 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE90 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE89 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE88 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE87 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE86 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE85 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE84 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE83 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE82 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE81 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE80 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE79 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE78 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE77 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE76 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE75 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE74 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE73 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE72 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE71 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE70 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE69 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE68 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE67 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE66 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE65 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE64 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x308++0x03 hide.long 0x00 "ACTIVE2,Active Bit Register 2" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) rgroup.long 0x30C++0x03 line.long 0x00 "ACTIVE3,Active Bit Register 3" bitfld.long 0x00 31. " ACTIVE127 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE126 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE125 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE124 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE123 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE122 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE121 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE120 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE119 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE118 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE117 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE116 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE115 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE114 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE113 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE112 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE111 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE110 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE109 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE108 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE107 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE106 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE105 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE104 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE103 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE102 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE101 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE100 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE99 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE98 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE97 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE96 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x30C++0x03 hide.long 0x00 "ACTIVE3,Active Bit Register 3" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) rgroup.long 0x310++0x03 line.long 0x00 "ACTIVE4,Active Bit Register 4" bitfld.long 0x00 31. " ACTIVE159 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE158 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE157 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE156 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE155 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE154 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE153 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE152 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE151 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE150 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE149 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE148 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE147 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE146 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE145 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE144 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE143 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE142 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE141 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE140 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE139 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE138 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE137 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE136 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE135 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE134 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE133 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE132 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE131 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE130 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE129 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE128 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x310++0x03 hide.long 0x00 "ACTIVE4,Active Bit Register 4" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) rgroup.long 0x314++0x03 line.long 0x00 "ACTIVE5,Active Bit Register 5" bitfld.long 0x00 31. " ACTIVE191 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE190 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE189 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE188 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE187 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE186 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE185 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE184 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE183 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE182 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE181 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE180 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE179 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE178 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE177 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE176 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE175 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE174 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE173 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE172 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE171 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE170 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE169 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE168 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE167 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE166 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE165 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE164 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE163 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE162 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE161 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE160 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x314++0x03 hide.long 0x00 "ACTIVE5,Active Bit Register 5" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) rgroup.long 0x318++0x03 line.long 0x00 "ACTIVE6,Active Bit Register 6" bitfld.long 0x00 31. " ACTIVE223 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE222 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE221 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE220 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE219 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE218 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE217 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE216 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE215 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE214 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE213 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE212 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE211 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE210 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE209 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE208 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE207 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE206 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE205 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE204 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE203 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE202 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE201 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE200 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE199 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE198 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE197 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE196 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE195 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE194 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE193 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE192 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x318++0x03 hide.long 0x00 "ACTIVE6,Active Bit Register 6" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) rgroup.long 0x31C++0x03 line.long 0x00 "ACTIVE7,Active Bit Register 7" bitfld.long 0x00 31. " ACTIVE255 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE254 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE253 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE252 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE251 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE250 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE249 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE248 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE247 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE246 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE245 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE244 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE243 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE242 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE241 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE240 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE239 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE238 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE237 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE236 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE235 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE234 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE233 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE232 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE231 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE230 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE229 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE228 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE227 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE226 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE225 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE224 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x31C++0x03 hide.long 0x00 "ACTIVE7,Active Bit Register 7" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) rgroup.long 0x320++0x03 line.long 0x00 "ACTIVE8,Active Bit Register 8" bitfld.long 0x00 31. " ACTIVE287 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE286 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE285 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE284 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE283 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE282 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE281 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE280 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE279 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE278 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE277 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE276 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE275 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE274 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE273 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE272 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE271 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE270 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE269 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE268 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE267 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE266 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE265 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE264 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE263 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE262 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE261 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE260 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE259 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE258 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE257 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE256 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x320++0x03 hide.long 0x00 "ACTIVE8,Active Bit Register 8" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) rgroup.long 0x324++0x03 line.long 0x00 "ACTIVE9,Active Bit Register 9" bitfld.long 0x00 31. " ACTIVE319 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE318 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE317 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE316 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE315 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE314 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE313 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE312 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE311 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE310 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE309 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE308 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE307 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE306 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE305 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE304 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE303 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE302 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE301 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE300 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE299 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE298 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE297 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE296 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE295 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE294 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE293 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE292 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE291 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE290 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE289 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE288 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x324++0x03 hide.long 0x00 "ACTIVE9,Active Bit Register 9" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) rgroup.long 0x328++0x03 line.long 0x00 "ACTIVE10,Active Bit Register 10" bitfld.long 0x00 31. " ACTIVE351 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE350 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE349 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE348 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE347 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE346 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE345 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE344 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE343 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE342 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE341 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE340 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE339 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE338 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE337 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE336 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE335 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE334 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE333 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE332 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE331 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE330 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE329 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE328 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE327 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE326 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE325 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE324 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE323 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE322 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE321 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE320 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x328++0x03 hide.long 0x00 "ACTIVE10,Active Bit Register 10" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) rgroup.long 0x32C++0x03 line.long 0x00 "ACTIVE11,Active Bit Register 11" bitfld.long 0x00 31. " ACTIVE383 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE382 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE381 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE380 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE379 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE378 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE377 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE376 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE375 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE374 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE373 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE372 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE371 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE370 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE369 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE368 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE367 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE366 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE365 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE364 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE363 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE362 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE361 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE360 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE359 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE358 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE357 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE356 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE355 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE354 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE353 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE352 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x32C++0x03 hide.long 0x00 "ACTIVE11,Active Bit Register 11" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) rgroup.long 0x330++0x03 line.long 0x00 "ACTIVE12,Active Bit Register 12" bitfld.long 0x00 31. " ACTIVE415 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE414 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE413 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE412 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE411 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE410 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE409 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE408 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE407 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE406 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE405 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE404 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE403 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE402 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE401 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE400 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE399 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE398 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE397 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE396 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE395 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE394 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE393 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE392 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE391 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE390 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE389 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE388 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE387 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE386 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE385 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE384 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x330++0x03 hide.long 0x00 "ACTIVE12,Active Bit Register 12" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) rgroup.long 0x334++0x03 line.long 0x00 "ACTIVE13,Active Bit Register 13" bitfld.long 0x00 31. " ACTIVE447 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE446 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE445 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE444 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE443 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE442 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE441 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE440 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE439 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE438 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE437 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE436 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE435 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE434 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE433 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE432 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE431 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE430 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE429 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE428 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE427 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE426 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE425 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE424 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE423 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE422 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE421 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE420 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE419 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE418 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE417 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE416 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x334++0x03 hide.long 0x00 "ACTIVE13,Active Bit Register 13" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) rgroup.long 0x338++0x03 line.long 0x00 "ACTIVE14,Active Bit Register 14" bitfld.long 0x00 31. " ACTIVE479 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE478 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE477 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE476 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE475 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE474 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE473 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE472 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE471 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE470 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE469 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE468 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE467 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE466 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE465 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE464 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE463 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE462 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE461 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE460 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE459 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE458 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE457 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE456 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE455 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE454 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE453 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE452 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE451 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE450 ,Interrupt active flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE449 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE448 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x338++0x03 hide.long 0x00 "ACTIVE14,Active Bit Register 14" endif tree.end width 13. tree "Interrupt Target Non-Secure Registers" group.long 0x380++0x03 line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0" bitfld.long 0x00 31. " ITNS31 ,Interrupt targets non-secure 31" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS30 ,Interrupt targets non-secure 30" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS29 ,Interrupt targets non-secure 29" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS28 ,Interrupt targets non-secure 28" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS27 ,Interrupt targets non-secure 27" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS26 ,Interrupt targets non-secure 26" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS25 ,Interrupt targets non-secure 25" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS24 ,Interrupt targets non-secure 24" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS23 ,Interrupt targets non-secure 23" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS22 ,Interrupt targets non-secure 22" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS21 ,Interrupt targets non-secure 21" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS20 ,Interrupt targets non-secure 20" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS19 ,Interrupt targets non-secure 19" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS18 ,Interrupt targets non-secure 18" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS17 ,Interrupt targets non-secure 17" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS16 ,Interrupt targets non-secure 16" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS15 ,Interrupt targets non-secure 15" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS14 ,Interrupt targets non-secure 14" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS13 ,Interrupt targets non-secure 13" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS12 ,Interrupt targets non-secure 12" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS11 ,Interrupt targets non-secure 11" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS10 ,Interrupt targets non-secure 10" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS9 ,Interrupt targets non-secure 9" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS8 ,Interrupt targets non-secure 8" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS7 ,Interrupt targets non-secure 7" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS6 ,Interrupt targets non-secure 6" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS5 ,Interrupt targets non-secure 5" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS4 ,Interrupt targets non-secure 4" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS3 ,Interrupt targets non-secure 3" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS2 ,Interrupt targets non-secure 2" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS1 ,Interrupt targets non-secure 1" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS0 ,Interrupt targets non-secure 0" "Secure,Non-secure" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x384++0x03 line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1" bitfld.long 0x00 31. " ITNS63 ,Interrupt targets non-secure 63" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS62 ,Interrupt targets non-secure 62" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS61 ,Interrupt targets non-secure 61" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS60 ,Interrupt targets non-secure 60" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS59 ,Interrupt targets non-secure 59" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS58 ,Interrupt targets non-secure 58" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS57 ,Interrupt targets non-secure 57" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS56 ,Interrupt targets non-secure 56" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS55 ,Interrupt targets non-secure 55" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS54 ,Interrupt targets non-secure 54" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS53 ,Interrupt targets non-secure 53" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS52 ,Interrupt targets non-secure 52" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS51 ,Interrupt targets non-secure 51" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS50 ,Interrupt targets non-secure 50" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS49 ,Interrupt targets non-secure 49" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS48 ,Interrupt targets non-secure 48" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS47 ,Interrupt targets non-secure 47" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS46 ,Interrupt targets non-secure 46" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS45 ,Interrupt targets non-secure 45" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS44 ,Interrupt targets non-secure 44" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS43 ,Interrupt targets non-secure 43" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS42 ,Interrupt targets non-secure 42" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS41 ,Interrupt targets non-secure 41" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS40 ,Interrupt targets non-secure 40" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS39 ,Interrupt targets non-secure 39" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS38 ,Interrupt targets non-secure 38" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS37 ,Interrupt targets non-secure 37" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS36 ,Interrupt targets non-secure 36" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS35 ,Interrupt targets non-secure 35" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS34 ,Interrupt targets non-secure 34" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS33 ,Interrupt targets non-secure 33" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS32 ,Interrupt targets non-secure 32" "Secure,Non-secure" else hgroup.long 0x384++0x03 hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x388++0x03 line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2" bitfld.long 0x00 31. " ITNS95 ,Interrupt targets non-secure 95" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS94 ,Interrupt targets non-secure 94" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS93 ,Interrupt targets non-secure 93" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS92 ,Interrupt targets non-secure 92" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS91 ,Interrupt targets non-secure 91" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS90 ,Interrupt targets non-secure 90" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS89 ,Interrupt targets non-secure 89" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS88 ,Interrupt targets non-secure 88" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS87 ,Interrupt targets non-secure 87" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS86 ,Interrupt targets non-secure 86" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS85 ,Interrupt targets non-secure 85" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS84 ,Interrupt targets non-secure 84" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS83 ,Interrupt targets non-secure 83" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS82 ,Interrupt targets non-secure 82" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS81 ,Interrupt targets non-secure 81" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS80 ,Interrupt targets non-secure 80" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS79 ,Interrupt targets non-secure 79" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS78 ,Interrupt targets non-secure 78" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS77 ,Interrupt targets non-secure 77" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS76 ,Interrupt targets non-secure 76" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS75 ,Interrupt targets non-secure 75" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS74 ,Interrupt targets non-secure 74" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS73 ,Interrupt targets non-secure 73" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS72 ,Interrupt targets non-secure 72" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS71 ,Interrupt targets non-secure 71" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS70 ,Interrupt targets non-secure 70" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS69 ,Interrupt targets non-secure 69" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS68 ,Interrupt targets non-secure 68" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS67 ,Interrupt targets non-secure 67" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS66 ,Interrupt targets non-secure 66" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS65 ,Interrupt targets non-secure 65" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS64 ,Interrupt targets non-secure 64" "Secure,Non-secure" else hgroup.long 0x388++0x03 hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x38C++0x03 line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3" bitfld.long 0x00 31. " ITNS127 ,Interrupt targets non-secure 127" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS126 ,Interrupt targets non-secure 126" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS125 ,Interrupt targets non-secure 125" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS124 ,Interrupt targets non-secure 124" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS123 ,Interrupt targets non-secure 123" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS122 ,Interrupt targets non-secure 122" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS121 ,Interrupt targets non-secure 121" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS120 ,Interrupt targets non-secure 120" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS119 ,Interrupt targets non-secure 119" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS118 ,Interrupt targets non-secure 118" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS117 ,Interrupt targets non-secure 117" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS116 ,Interrupt targets non-secure 116" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS115 ,Interrupt targets non-secure 115" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS114 ,Interrupt targets non-secure 114" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS113 ,Interrupt targets non-secure 113" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS112 ,Interrupt targets non-secure 112" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS111 ,Interrupt targets non-secure 111" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS110 ,Interrupt targets non-secure 110" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS109 ,Interrupt targets non-secure 109" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS108 ,Interrupt targets non-secure 108" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS107 ,Interrupt targets non-secure 107" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS106 ,Interrupt targets non-secure 106" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS105 ,Interrupt targets non-secure 105" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS104 ,Interrupt targets non-secure 104" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS103 ,Interrupt targets non-secure 103" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS102 ,Interrupt targets non-secure 102" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS101 ,Interrupt targets non-secure 101" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS100 ,Interrupt targets non-secure 100" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS99 ,Interrupt targets non-secure 99" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS98 ,Interrupt targets non-secure 98" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS97 ,Interrupt targets non-secure 97" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS96 ,Interrupt targets non-secure 96" "Secure,Non-secure" else hgroup.long 0x38C++0x03 hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x390++0x03 line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4" bitfld.long 0x00 31. " ITNS159 ,Interrupt targets non-secure 159" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS158 ,Interrupt targets non-secure 158" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS157 ,Interrupt targets non-secure 157" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS156 ,Interrupt targets non-secure 156" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS155 ,Interrupt targets non-secure 155" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS154 ,Interrupt targets non-secure 154" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS153 ,Interrupt targets non-secure 153" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS152 ,Interrupt targets non-secure 152" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS151 ,Interrupt targets non-secure 151" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS150 ,Interrupt targets non-secure 150" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS149 ,Interrupt targets non-secure 149" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS148 ,Interrupt targets non-secure 148" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS147 ,Interrupt targets non-secure 147" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS146 ,Interrupt targets non-secure 146" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS145 ,Interrupt targets non-secure 145" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS144 ,Interrupt targets non-secure 144" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS143 ,Interrupt targets non-secure 143" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS142 ,Interrupt targets non-secure 142" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS141 ,Interrupt targets non-secure 141" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS140 ,Interrupt targets non-secure 140" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS139 ,Interrupt targets non-secure 139" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS138 ,Interrupt targets non-secure 138" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS137 ,Interrupt targets non-secure 137" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS136 ,Interrupt targets non-secure 136" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS135 ,Interrupt targets non-secure 135" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS134 ,Interrupt targets non-secure 134" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS133 ,Interrupt targets non-secure 133" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS132 ,Interrupt targets non-secure 132" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS131 ,Interrupt targets non-secure 131" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS130 ,Interrupt targets non-secure 130" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS129 ,Interrupt targets non-secure 129" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS128 ,Interrupt targets non-secure 128" "Secure,Non-secure" else hgroup.long 0x390++0x03 hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x394++0x03 line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5" bitfld.long 0x00 31. " ITNS191 ,Interrupt targets non-secure 191" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS190 ,Interrupt targets non-secure 190" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS189 ,Interrupt targets non-secure 189" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS188 ,Interrupt targets non-secure 188" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS187 ,Interrupt targets non-secure 187" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS186 ,Interrupt targets non-secure 186" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS185 ,Interrupt targets non-secure 185" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS184 ,Interrupt targets non-secure 184" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS183 ,Interrupt targets non-secure 183" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS182 ,Interrupt targets non-secure 182" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS181 ,Interrupt targets non-secure 181" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS180 ,Interrupt targets non-secure 180" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS179 ,Interrupt targets non-secure 179" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS178 ,Interrupt targets non-secure 178" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS177 ,Interrupt targets non-secure 177" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS176 ,Interrupt targets non-secure 176" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS175 ,Interrupt targets non-secure 175" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS174 ,Interrupt targets non-secure 174" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS173 ,Interrupt targets non-secure 173" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS172 ,Interrupt targets non-secure 172" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS171 ,Interrupt targets non-secure 171" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS170 ,Interrupt targets non-secure 170" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS169 ,Interrupt targets non-secure 169" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS168 ,Interrupt targets non-secure 168" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS167 ,Interrupt targets non-secure 167" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS166 ,Interrupt targets non-secure 166" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS165 ,Interrupt targets non-secure 165" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS164 ,Interrupt targets non-secure 164" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS163 ,Interrupt targets non-secure 163" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS162 ,Interrupt targets non-secure 162" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS161 ,Interrupt targets non-secure 161" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS160 ,Interrupt targets non-secure 160" "Secure,Non-secure" else hgroup.long 0x394++0x03 hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x398++0x03 line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6" bitfld.long 0x00 31. " ITNS223 ,Interrupt targets non-secure 223" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS222 ,Interrupt targets non-secure 222" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS221 ,Interrupt targets non-secure 221" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS220 ,Interrupt targets non-secure 220" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS219 ,Interrupt targets non-secure 219" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS218 ,Interrupt targets non-secure 218" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS217 ,Interrupt targets non-secure 217" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS216 ,Interrupt targets non-secure 216" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS215 ,Interrupt targets non-secure 215" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS214 ,Interrupt targets non-secure 214" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS213 ,Interrupt targets non-secure 213" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS212 ,Interrupt targets non-secure 212" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS211 ,Interrupt targets non-secure 211" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS210 ,Interrupt targets non-secure 210" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS209 ,Interrupt targets non-secure 209" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS208 ,Interrupt targets non-secure 208" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS207 ,Interrupt targets non-secure 207" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS206 ,Interrupt targets non-secure 206" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS205 ,Interrupt targets non-secure 205" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS204 ,Interrupt targets non-secure 204" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS203 ,Interrupt targets non-secure 203" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS202 ,Interrupt targets non-secure 202" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS201 ,Interrupt targets non-secure 201" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS200 ,Interrupt targets non-secure 200" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS199 ,Interrupt targets non-secure 199" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS198 ,Interrupt targets non-secure 198" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS197 ,Interrupt targets non-secure 197" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS196 ,Interrupt targets non-secure 196" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS195 ,Interrupt targets non-secure 195" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS194 ,Interrupt targets non-secure 194" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS193 ,Interrupt targets non-secure 193" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS192 ,Interrupt targets non-secure 192" "Secure,Non-secure" else hgroup.long 0x398++0x03 hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x39C++0x03 line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7" bitfld.long 0x00 31. " ITNS255 ,Interrupt targets non-secure 255" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS254 ,Interrupt targets non-secure 254" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS253 ,Interrupt targets non-secure 253" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS252 ,Interrupt targets non-secure 252" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS251 ,Interrupt targets non-secure 251" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS250 ,Interrupt targets non-secure 250" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS249 ,Interrupt targets non-secure 249" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS248 ,Interrupt targets non-secure 248" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS247 ,Interrupt targets non-secure 247" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS246 ,Interrupt targets non-secure 246" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS245 ,Interrupt targets non-secure 245" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS244 ,Interrupt targets non-secure 244" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS243 ,Interrupt targets non-secure 243" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS242 ,Interrupt targets non-secure 242" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS241 ,Interrupt targets non-secure 241" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS240 ,Interrupt targets non-secure 240" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS239 ,Interrupt targets non-secure 239" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS238 ,Interrupt targets non-secure 238" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS237 ,Interrupt targets non-secure 237" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS236 ,Interrupt targets non-secure 236" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS235 ,Interrupt targets non-secure 235" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS234 ,Interrupt targets non-secure 234" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS233 ,Interrupt targets non-secure 233" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS232 ,Interrupt targets non-secure 232" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS231 ,Interrupt targets non-secure 231" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS230 ,Interrupt targets non-secure 230" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS229 ,Interrupt targets non-secure 229" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS228 ,Interrupt targets non-secure 228" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS227 ,Interrupt targets non-secure 227" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS226 ,Interrupt targets non-secure 226" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS225 ,Interrupt targets non-secure 225" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS224 ,Interrupt targets non-secure 224" "Secure,Non-secure" else hgroup.long 0x39C++0x03 hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x3A0++0x03 line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8" bitfld.long 0x00 31. " ITNS287 ,Interrupt targets non-secure 287" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS286 ,Interrupt targets non-secure 286" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS285 ,Interrupt targets non-secure 285" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS284 ,Interrupt targets non-secure 284" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS283 ,Interrupt targets non-secure 283" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS282 ,Interrupt targets non-secure 282" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS281 ,Interrupt targets non-secure 281" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS280 ,Interrupt targets non-secure 280" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS279 ,Interrupt targets non-secure 279" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS278 ,Interrupt targets non-secure 278" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS277 ,Interrupt targets non-secure 277" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS276 ,Interrupt targets non-secure 276" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS275 ,Interrupt targets non-secure 275" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS274 ,Interrupt targets non-secure 274" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS273 ,Interrupt targets non-secure 273" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS272 ,Interrupt targets non-secure 272" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS271 ,Interrupt targets non-secure 271" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS270 ,Interrupt targets non-secure 270" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS269 ,Interrupt targets non-secure 269" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS268 ,Interrupt targets non-secure 268" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS267 ,Interrupt targets non-secure 267" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS266 ,Interrupt targets non-secure 266" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS265 ,Interrupt targets non-secure 265" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS264 ,Interrupt targets non-secure 264" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS263 ,Interrupt targets non-secure 263" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS262 ,Interrupt targets non-secure 262" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS261 ,Interrupt targets non-secure 261" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS260 ,Interrupt targets non-secure 260" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS259 ,Interrupt targets non-secure 259" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS258 ,Interrupt targets non-secure 258" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS257 ,Interrupt targets non-secure 257" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS256 ,Interrupt targets non-secure 256" "Secure,Non-secure" else hgroup.long 0x3A0++0x03 hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x3A4++0x03 line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9" bitfld.long 0x00 31. " ITNS319 ,Interrupt targets non-secure 319" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS318 ,Interrupt targets non-secure 318" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS317 ,Interrupt targets non-secure 317" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS316 ,Interrupt targets non-secure 316" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS315 ,Interrupt targets non-secure 315" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS314 ,Interrupt targets non-secure 314" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS313 ,Interrupt targets non-secure 313" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS312 ,Interrupt targets non-secure 312" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS311 ,Interrupt targets non-secure 311" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS310 ,Interrupt targets non-secure 310" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS309 ,Interrupt targets non-secure 309" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS308 ,Interrupt targets non-secure 308" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS307 ,Interrupt targets non-secure 307" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS306 ,Interrupt targets non-secure 306" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS305 ,Interrupt targets non-secure 305" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS304 ,Interrupt targets non-secure 304" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS303 ,Interrupt targets non-secure 303" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS302 ,Interrupt targets non-secure 302" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS301 ,Interrupt targets non-secure 301" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS300 ,Interrupt targets non-secure 300" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS299 ,Interrupt targets non-secure 299" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS298 ,Interrupt targets non-secure 298" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS297 ,Interrupt targets non-secure 297" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS296 ,Interrupt targets non-secure 296" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS295 ,Interrupt targets non-secure 295" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS294 ,Interrupt targets non-secure 294" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS293 ,Interrupt targets non-secure 293" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS292 ,Interrupt targets non-secure 292" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS291 ,Interrupt targets non-secure 291" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS290 ,Interrupt targets non-secure 290" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS289 ,Interrupt targets non-secure 289" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS288 ,Interrupt targets non-secure 288" "Secure,Non-secure" else hgroup.long 0x3A4++0x03 hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x3A8++0x03 line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10" bitfld.long 0x00 31. " ITNS351 ,Interrupt targets non-secure 351" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS350 ,Interrupt targets non-secure 350" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS349 ,Interrupt targets non-secure 349" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS348 ,Interrupt targets non-secure 348" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS347 ,Interrupt targets non-secure 347" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS346 ,Interrupt targets non-secure 346" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS345 ,Interrupt targets non-secure 345" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS344 ,Interrupt targets non-secure 344" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS343 ,Interrupt targets non-secure 343" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS342 ,Interrupt targets non-secure 342" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS341 ,Interrupt targets non-secure 341" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS340 ,Interrupt targets non-secure 340" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS339 ,Interrupt targets non-secure 339" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS338 ,Interrupt targets non-secure 338" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS337 ,Interrupt targets non-secure 337" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS336 ,Interrupt targets non-secure 336" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS335 ,Interrupt targets non-secure 335" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS334 ,Interrupt targets non-secure 334" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS333 ,Interrupt targets non-secure 333" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS332 ,Interrupt targets non-secure 332" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS331 ,Interrupt targets non-secure 331" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS330 ,Interrupt targets non-secure 330" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS329 ,Interrupt targets non-secure 329" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS328 ,Interrupt targets non-secure 328" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS327 ,Interrupt targets non-secure 327" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS326 ,Interrupt targets non-secure 326" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS325 ,Interrupt targets non-secure 325" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS324 ,Interrupt targets non-secure 324" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS323 ,Interrupt targets non-secure 323" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS322 ,Interrupt targets non-secure 322" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS321 ,Interrupt targets non-secure 321" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS320 ,Interrupt targets non-secure 320" "Secure,Non-secure" else hgroup.long 0x3A8++0x03 hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x3AC++0x03 line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11" bitfld.long 0x00 31. " ITNS383 ,Interrupt targets non-secure 383" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS382 ,Interrupt targets non-secure 382" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS381 ,Interrupt targets non-secure 381" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS380 ,Interrupt targets non-secure 380" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS379 ,Interrupt targets non-secure 379" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS378 ,Interrupt targets non-secure 378" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS377 ,Interrupt targets non-secure 377" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS376 ,Interrupt targets non-secure 376" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS375 ,Interrupt targets non-secure 375" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS374 ,Interrupt targets non-secure 374" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS373 ,Interrupt targets non-secure 373" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS372 ,Interrupt targets non-secure 372" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS371 ,Interrupt targets non-secure 371" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS370 ,Interrupt targets non-secure 370" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS369 ,Interrupt targets non-secure 369" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS368 ,Interrupt targets non-secure 368" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS367 ,Interrupt targets non-secure 367" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS366 ,Interrupt targets non-secure 366" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS365 ,Interrupt targets non-secure 365" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS364 ,Interrupt targets non-secure 364" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS363 ,Interrupt targets non-secure 363" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS362 ,Interrupt targets non-secure 362" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS361 ,Interrupt targets non-secure 361" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS360 ,Interrupt targets non-secure 360" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS359 ,Interrupt targets non-secure 359" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS358 ,Interrupt targets non-secure 358" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS357 ,Interrupt targets non-secure 357" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS356 ,Interrupt targets non-secure 356" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS355 ,Interrupt targets non-secure 355" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS354 ,Interrupt targets non-secure 354" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS353 ,Interrupt targets non-secure 353" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS352 ,Interrupt targets non-secure 352" "Secure,Non-secure" else hgroup.long 0x3AC++0x03 hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x3B0++0x03 line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12" bitfld.long 0x00 31. " ITNS415 ,Interrupt targets non-secure 415" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS414 ,Interrupt targets non-secure 414" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS413 ,Interrupt targets non-secure 413" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS412 ,Interrupt targets non-secure 412" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS411 ,Interrupt targets non-secure 411" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS410 ,Interrupt targets non-secure 410" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS409 ,Interrupt targets non-secure 409" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS408 ,Interrupt targets non-secure 408" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS407 ,Interrupt targets non-secure 407" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS406 ,Interrupt targets non-secure 406" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS405 ,Interrupt targets non-secure 405" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS404 ,Interrupt targets non-secure 404" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS403 ,Interrupt targets non-secure 403" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS402 ,Interrupt targets non-secure 402" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS401 ,Interrupt targets non-secure 401" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS400 ,Interrupt targets non-secure 400" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS399 ,Interrupt targets non-secure 399" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS398 ,Interrupt targets non-secure 398" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS397 ,Interrupt targets non-secure 397" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS396 ,Interrupt targets non-secure 396" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS395 ,Interrupt targets non-secure 395" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS394 ,Interrupt targets non-secure 394" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS393 ,Interrupt targets non-secure 393" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS392 ,Interrupt targets non-secure 392" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS391 ,Interrupt targets non-secure 391" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS390 ,Interrupt targets non-secure 390" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS389 ,Interrupt targets non-secure 389" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS388 ,Interrupt targets non-secure 388" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS387 ,Interrupt targets non-secure 387" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS386 ,Interrupt targets non-secure 386" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS385 ,Interrupt targets non-secure 385" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS384 ,Interrupt targets non-secure 384" "Secure,Non-secure" else hgroup.long 0x3B0++0x03 hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x3B4++0x03 line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13" bitfld.long 0x00 31. " ITNS447 ,Interrupt targets non-secure 447" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS446 ,Interrupt targets non-secure 446" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS445 ,Interrupt targets non-secure 445" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS444 ,Interrupt targets non-secure 444" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS443 ,Interrupt targets non-secure 443" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS442 ,Interrupt targets non-secure 442" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS441 ,Interrupt targets non-secure 441" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS440 ,Interrupt targets non-secure 440" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS439 ,Interrupt targets non-secure 439" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS438 ,Interrupt targets non-secure 438" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS437 ,Interrupt targets non-secure 437" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS436 ,Interrupt targets non-secure 436" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS435 ,Interrupt targets non-secure 435" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS434 ,Interrupt targets non-secure 434" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS433 ,Interrupt targets non-secure 433" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS432 ,Interrupt targets non-secure 432" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS431 ,Interrupt targets non-secure 431" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS430 ,Interrupt targets non-secure 430" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS429 ,Interrupt targets non-secure 429" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS428 ,Interrupt targets non-secure 428" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS427 ,Interrupt targets non-secure 427" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS426 ,Interrupt targets non-secure 426" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS425 ,Interrupt targets non-secure 425" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS424 ,Interrupt targets non-secure 424" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS423 ,Interrupt targets non-secure 423" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS422 ,Interrupt targets non-secure 422" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS421 ,Interrupt targets non-secure 421" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS420 ,Interrupt targets non-secure 420" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS419 ,Interrupt targets non-secure 419" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS418 ,Interrupt targets non-secure 418" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS417 ,Interrupt targets non-secure 417" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS416 ,Interrupt targets non-secure 416" "Secure,Non-secure" else hgroup.long 0x3B4++0x03 hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x3B8++0x03 line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14" bitfld.long 0x00 31. " ITNS479 ,Interrupt targets non-secure 479" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS478 ,Interrupt targets non-secure 478" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS477 ,Interrupt targets non-secure 477" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS476 ,Interrupt targets non-secure 476" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS475 ,Interrupt targets non-secure 475" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS474 ,Interrupt targets non-secure 474" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS473 ,Interrupt targets non-secure 473" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS472 ,Interrupt targets non-secure 472" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS471 ,Interrupt targets non-secure 471" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS470 ,Interrupt targets non-secure 470" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS469 ,Interrupt targets non-secure 469" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS468 ,Interrupt targets non-secure 468" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS467 ,Interrupt targets non-secure 467" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS466 ,Interrupt targets non-secure 466" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS465 ,Interrupt targets non-secure 465" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS464 ,Interrupt targets non-secure 464" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS463 ,Interrupt targets non-secure 463" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS462 ,Interrupt targets non-secure 462" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS461 ,Interrupt targets non-secure 461" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS460 ,Interrupt targets non-secure 460" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS459 ,Interrupt targets non-secure 459" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS458 ,Interrupt targets non-secure 458" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS457 ,Interrupt targets non-secure 457" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS456 ,Interrupt targets non-secure 456" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS455 ,Interrupt targets non-secure 455" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS454 ,Interrupt targets non-secure 454" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS453 ,Interrupt targets non-secure 453" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS452 ,Interrupt targets non-secure 452" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS451 ,Interrupt targets non-secure 451" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS450 ,Interrupt targets non-secure 450" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS449 ,Interrupt targets non-secure 449" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS448 ,Interrupt targets non-secure 448" "Secure,Non-secure" else hgroup.long 0x3B8++0x03 hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14" endif tree.end tree "Interrupt Priority Registers" group.long 0x400++0x03 line.long 0x00 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_3 ,Interrupt 3 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_2 ,Interrupt 2 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_1 ,Interrupt 1 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_0 ,Interrupt 0 priority" group.long 0x404++0x03 line.long 0x00 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Interrupt 7 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Interrupt 6 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Interrupt 5 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Interrupt 4 priority" group.long 0x408++0x03 line.long 0x00 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Interrupt 11 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_10 ,Interrupt 10 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_9 ,Interrupt 9 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_8 ,Interrupt 8 priority" group.long 0x40C++0x03 line.long 0x00 "IPR3,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_15 ,Interrupt 15 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_14 ,Interrupt 14 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_13 ,Interrupt 13 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_12 ,Interrupt 12 priority" group.long 0x410++0x03 line.long 0x00 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_19 ,Interrupt 19 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_18 ,Interrupt 18 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_17 ,Interrupt 17 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_16 ,Interrupt 16 priority" group.long 0x414++0x03 line.long 0x00 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_23 ,Interrupt 23 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_22 ,Interrupt 22 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_21 ,Interrupt 21 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_20 ,Interrupt 20 priority" group.long 0x418++0x03 line.long 0x00 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_27 ,Interrupt 27 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_26 ,Interrupt 26 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_25 ,Interrupt 25 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_24 ,Interrupt 24 priority" group.long 0x41C++0x03 line.long 0x00 "IPR7,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_31 ,Interrupt 31 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_30 ,Interrupt 30 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_29 ,Interrupt 29 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_28 ,Interrupt 28 priority" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x420++0x03 line.long 0x00 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_35 ,Interrupt 35 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_34 ,Interrupt 34 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_33 ,Interrupt 33 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_32 ,Interrupt 32 priority" group.long 0x424++0x03 line.long 0x00 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_39 ,Interrupt 39 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_38 ,Interrupt 38 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_37 ,Interrupt 37 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_36 ,Interrupt 36 priority" group.long 0x428++0x03 line.long 0x00 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_43 ,Interrupt 43 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_42 ,Interrupt 42 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_41 ,Interrupt 41 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_40 ,Interrupt 40 priority" group.long 0x42C++0x03 line.long 0x00 "IPR11,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_47 ,Interrupt 47 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_46 ,Interrupt 46 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_45 ,Interrupt 45 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_44 ,Interrupt 44 priority" group.long 0x430++0x03 line.long 0x00 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_51 ,Interrupt 51 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_50 ,Interrupt 50 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_49 ,Interrupt 49 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_48 ,Interrupt 48 priority" group.long 0x434++0x03 line.long 0x00 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_55 ,Interrupt 55 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_54 ,Interrupt 54 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_53 ,Interrupt 53 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_52 ,Interrupt 52 priority" group.long 0x438++0x03 line.long 0x00 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_59 ,Interrupt 59 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_58 ,Interrupt 58 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_57 ,Interrupt 57 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_56 ,Interrupt 56 priority" group.long 0x43C++0x03 line.long 0x00 "IPR15,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_63 ,Interrupt 63 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_62 ,Interrupt 62 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_61 ,Interrupt 61 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_60 ,Interrupt 60 priority" else hgroup.long 0x420++0x03 hide.long 0x00 "IPR8,Interrupt Priority Register" hgroup.long 0x420++0x03 hide.long 0x00 "IPR9,Interrupt Priority Register" hgroup.long 0x420++0x03 hide.long 0x00 "IPR10,Interrupt Priority Register" hgroup.long 0x420++0x03 hide.long 0x00 "IPR11,Interrupt Priority Register" hgroup.long 0x420++0x03 hide.long 0x00 "IPR12,Interrupt Priority Register" hgroup.long 0x420++0x03 hide.long 0x00 "IPR13,Interrupt Priority Register" hgroup.long 0x420++0x03 hide.long 0x00 "IPR14,Interrupt Priority Register" hgroup.long 0x420++0x03 hide.long 0x00 "IPR15,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x440++0x03 line.long 0x00 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_67 ,Interrupt 67 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_66 ,Interrupt 66 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_65 ,Interrupt 65 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_64 ,Interrupt 64 priority" group.long 0x444++0x03 line.long 0x00 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_71 ,Interrupt 71 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_70 ,Interrupt 70 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_69 ,Interrupt 69 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_68 ,Interrupt 68 priority" group.long 0x448++0x03 line.long 0x00 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_75 ,Interrupt 75 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_74 ,Interrupt 74 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_73 ,Interrupt 73 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_72 ,Interrupt 72 priority" group.long 0x44C++0x03 line.long 0x00 "IPR19,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_79 ,Interrupt 79 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_78 ,Interrupt 78 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_77 ,Interrupt 77 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_76 ,Interrupt 76 priority" group.long 0x450++0x03 line.long 0x00 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_83 ,Interrupt 83 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_82 ,Interrupt 82 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_81 ,Interrupt 81 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_80 ,Interrupt 80 priority" group.long 0x454++0x03 line.long 0x00 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_87 ,Interrupt 87 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_86 ,Interrupt 86 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_85 ,Interrupt 85 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_84 ,Interrupt 84 priority" group.long 0x458++0x03 line.long 0x00 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_91 ,Interrupt 91 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_90 ,Interrupt 90 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_89 ,Interrupt 89 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_88 ,Interrupt 88 priority" group.long 0x45C++0x03 line.long 0x00 "IPR23,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_95 ,Interrupt 95 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_94 ,Interrupt 94 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_93 ,Interrupt 93 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_92 ,Interrupt 92 priority" else hgroup.long 0x440++0x03 hide.long 0x00 "IPR16,Interrupt Priority Register" hgroup.long 0x444++0x03 hide.long 0x00 "IPR17,Interrupt Priority Register" hgroup.long 0x448++0x03 hide.long 0x00 "IPR18,Interrupt Priority Register" hgroup.long 0x44C++0x03 hide.long 0x00 "IPR19,Interrupt Priority Register" hgroup.long 0x450++0x03 hide.long 0x00 "IPR20,Interrupt Priority Register" hgroup.long 0x454++0x03 hide.long 0x00 "IPR21,Interrupt Priority Register" hgroup.long 0x458++0x03 hide.long 0x00 "IPR22,Interrupt Priority Register" hgroup.long 0x45C++0x03 hide.long 0x00 "IPR23,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x460++0x03 line.long 0x00 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_99 ,Interrupt 99 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_98 ,Interrupt 98 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_97 ,Interrupt 97 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_96 ,Interrupt 96 priority" group.long 0x464++0x03 line.long 0x00 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_103 ,Interrupt 103 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_102 ,Interrupt 102 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_101 ,Interrupt 101 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_100 ,Interrupt 100 priority" group.long 0x468++0x03 line.long 0x00 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_107 ,Interrupt 107 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_106 ,Interrupt 106 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_105 ,Interrupt 105 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_104 ,Interrupt 104 priority" group.long 0x46C++0x03 line.long 0x00 "IPR27,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_111 ,Interrupt 111 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_110 ,Interrupt 110 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_109 ,Interrupt 109 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_108 ,Interrupt 108 priority" group.long 0x470++0x03 line.long 0x00 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_115 ,Interrupt 115 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_114 ,Interrupt 114 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_113 ,Interrupt 113 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_112 ,Interrupt 112 priority" group.long 0x474++0x03 line.long 0x00 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_119 ,Interrupt 119 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_118 ,Interrupt 118 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_117 ,Interrupt 117 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_116 ,Interrupt 116 priority" group.long 0x478++0x03 line.long 0x00 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_123 ,Interrupt 123 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_122 ,Interrupt 122 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_121 ,Interrupt 121 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_120 ,Interrupt 120 priority" group.long 0x47C++0x03 line.long 0x00 "IPR31,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_127 ,Interrupt 127 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_126 ,Interrupt 126 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_125 ,Interrupt 125 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_124 ,Interrupt 124 priority" else hgroup.long 0x460++0x03 hide.long 0x00 "IPR24,Interrupt Priority Register" hgroup.long 0x464++0x03 hide.long 0x00 "IPR25,Interrupt Priority Register" hgroup.long 0x468++0x03 hide.long 0x00 "IPR26,Interrupt Priority Register" hgroup.long 0x46C++0x03 hide.long 0x00 "IPR27,Interrupt Priority Register" hgroup.long 0x470++0x03 hide.long 0x00 "IPR28,Interrupt Priority Register" hgroup.long 0x474++0x03 hide.long 0x00 "IPR29,Interrupt Priority Register" hgroup.long 0x478++0x03 hide.long 0x00 "IPR30,Interrupt Priority Register" hgroup.long 0x47C++0x03 hide.long 0x00 "IPR31,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x480++0x03 line.long 0x00 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_131 ,Interrupt 131 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_130 ,Interrupt 130 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_129 ,Interrupt 129 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_128 ,Interrupt 128 priority" group.long 0x484++0x03 line.long 0x00 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_135 ,Interrupt 135 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_134 ,Interrupt 134 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_133 ,Interrupt 133 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_132 ,Interrupt 132 priority" group.long 0x488++0x03 line.long 0x00 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_139 ,Interrupt 139 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_138 ,Interrupt 138 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_137 ,Interrupt 137 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_136 ,Interrupt 136 priority" group.long 0x48C++0x03 line.long 0x00 "IPR35,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_143 ,Interrupt 143 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_142 ,Interrupt 142 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_141 ,Interrupt 141 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_140 ,Interrupt 140 priority" group.long 0x490++0x03 line.long 0x00 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_147 ,Interrupt 147 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_146 ,Interrupt 146 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_145 ,Interrupt 145 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_144 ,Interrupt 144 priority" group.long 0x494++0x03 line.long 0x00 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_151 ,Interrupt 151 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_150 ,Interrupt 150 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_149 ,Interrupt 149 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_148 ,Interrupt 148 priority" group.long 0x498++0x03 line.long 0x00 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_155 ,Interrupt 155 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_154 ,Interrupt 154 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_153 ,Interrupt 153 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_152 ,Interrupt 152 priority" group.long 0x49C++0x03 line.long 0x00 "IPR39,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_159 ,Interrupt 159 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_158 ,Interrupt 158 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_157 ,Interrupt 157 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_156 ,Interrupt 156 priority" else hgroup.long 0x480++0x03 hide.long 0x00 "IPR32,Interrupt Priority Register" hgroup.long 0x484++0x03 hide.long 0x00 "IPR33,Interrupt Priority Register" hgroup.long 0x488++0x03 hide.long 0x00 "IPR34,Interrupt Priority Register" hgroup.long 0x48C++0x03 hide.long 0x00 "IPR35,Interrupt Priority Register" hgroup.long 0x490++0x03 hide.long 0x00 "IPR36,Interrupt Priority Register" hgroup.long 0x494++0x03 hide.long 0x00 "IPR37,Interrupt Priority Register" hgroup.long 0x498++0x03 hide.long 0x00 "IPR38,Interrupt Priority Register" hgroup.long 0x49C++0x03 hide.long 0x00 "IPR39,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "IPR40,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_163 ,Interrupt 163 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_162 ,Interrupt 162 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_161 ,Interrupt 161 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_160 ,Interrupt 160 priority" group.long 0x4A4++0x03 line.long 0x00 "IPR41,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_167 ,Interrupt 167 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_166 ,Interrupt 166 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_165 ,Interrupt 165 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_164 ,Interrupt 164 priority" group.long 0x4A8++0x03 line.long 0x00 "IPR42,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_171 ,Interrupt 171 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_170 ,Interrupt 170 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_169 ,Interrupt 169 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_168 ,Interrupt 168 priority" group.long 0x4AC++0x03 line.long 0x00 "IPR43,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_175 ,Interrupt 175 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_174 ,Interrupt 174 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_173 ,Interrupt 173 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_172 ,Interrupt 172 priority" group.long 0x4B0++0x03 line.long 0x00 "IPR44,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_179 ,Interrupt 179 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_178 ,Interrupt 178 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_177 ,Interrupt 177 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_176 ,Interrupt 176 priority" group.long 0x4B4++0x03 line.long 0x00 "IPR45,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_183 ,Interrupt 183 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_182 ,Interrupt 182 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_181 ,Interrupt 181 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_180 ,Interrupt 180 priority" group.long 0x4B8++0x03 line.long 0x00 "IPR46,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_187 ,Interrupt 187 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_186 ,Interrupt 186 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_185 ,Interrupt 185 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_184 ,Interrupt 184 priority" group.long 0x4BC++0x03 line.long 0x00 "IPR47,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_191 ,Interrupt 191 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_190 ,Interrupt 190 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_189 ,Interrupt 189 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_188 ,Interrupt 188 priority" else hgroup.long 0x4A0++0x03 hide.long 0x00 "IPR40,Interrupt Priority Register" hgroup.long 0x4A4++0x03 hide.long 0x00 "IPR41,Interrupt Priority Register" hgroup.long 0x4A8++0x03 hide.long 0x00 "IPR42,Interrupt Priority Register" hgroup.long 0x4AC++0x03 hide.long 0x00 "IPR43,Interrupt Priority Register" hgroup.long 0x4B0++0x03 hide.long 0x00 "IPR44,Interrupt Priority Register" hgroup.long 0x4B4++0x03 hide.long 0x00 "IPR45,Interrupt Priority Register" hgroup.long 0x4B8++0x03 hide.long 0x00 "IPR46,Interrupt Priority Register" hgroup.long 0x4BC++0x03 hide.long 0x00 "IPR47,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "IPR48,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_195 ,Interrupt 195 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_194 ,Interrupt 194 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_193 ,Interrupt 193 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_192 ,Interrupt 192 priority" group.long 0x4C4++0x03 line.long 0x00 "IPR49,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_199 ,Interrupt 199 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_198 ,Interrupt 198 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_197 ,Interrupt 197 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_196 ,Interrupt 196 priority" group.long 0x4C8++0x03 line.long 0x00 "IPR50,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_203 ,Interrupt 203 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_202 ,Interrupt 202 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_201 ,Interrupt 201 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_200 ,Interrupt 200 priority" group.long 0x4CC++0x03 line.long 0x00 "IPR51,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_207 ,Interrupt 207 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_206 ,Interrupt 206 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_205 ,Interrupt 205 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_204 ,Interrupt 204 priority" group.long 0x4D0++0x03 line.long 0x00 "IPR52,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_211 ,Interrupt 211 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_210 ,Interrupt 210 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_209 ,Interrupt 209 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_208 ,Interrupt 208 priority" group.long 0x4D4++0x03 line.long 0x00 "IPR53,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_215 ,Interrupt 215 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_214 ,Interrupt 214 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_213 ,Interrupt 213 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_212 ,Interrupt 212 priority" group.long 0x4D8++0x03 line.long 0x00 "IPR54,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_219 ,Interrupt 219 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_218 ,Interrupt 218 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_217 ,Interrupt 217 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_216 ,Interrupt 216 priority" group.long 0x4DC++0x03 line.long 0x00 "IPR55,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_223 ,Interrupt 223 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_222 ,Interrupt 222 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_221 ,Interrupt 221 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_220 ,Interrupt 220 priority" else hgroup.long 0x4C0++0x03 hide.long 0x00 "IPR48,Interrupt Priority Register" hgroup.long 0x4C4++0x03 hide.long 0x00 "IPR49,Interrupt Priority Register" hgroup.long 0x4C8++0x03 hide.long 0x00 "IPR50,Interrupt Priority Register" hgroup.long 0x4CC++0x03 hide.long 0x00 "IPR51,Interrupt Priority Register" hgroup.long 0x4D0++0x03 hide.long 0x00 "IPR52,Interrupt Priority Register" hgroup.long 0x4D4++0x03 hide.long 0x00 "IPR53,Interrupt Priority Register" hgroup.long 0x4D8++0x03 hide.long 0x00 "IPR54,Interrupt Priority Register" hgroup.long 0x4DC++0x03 hide.long 0x00 "IPR55,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "IPR56,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_227 ,Interrupt 227 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_226 ,Interrupt 226 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_225 ,Interrupt 225 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_224 ,Interrupt 224 priority" group.long 0x4E4++0x03 line.long 0x00 "IPR57,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_231 ,Interrupt 231 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_230 ,Interrupt 230 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_229 ,Interrupt 229 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_228 ,Interrupt 228 priority" group.long 0x4E8++0x03 line.long 0x00 "IPR58,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_235 ,Interrupt 235 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_234 ,Interrupt 234 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_233 ,Interrupt 233 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_232 ,Interrupt 232 priority" group.long 0x4EC++0x03 line.long 0x00 "IPR59,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_239 ,Interrupt 239 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_238 ,Interrupt 238 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_237 ,Interrupt 237 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_236 ,Interrupt 236 priority" group.long 0x4F0++0x03 line.long 0x00 "IPR60,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_243 ,Interrupt 243 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_242 ,Interrupt 242 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_241 ,Interrupt 241 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_240 ,Interrupt 240 priority" group.long 0x4F4++0x03 line.long 0x00 "IPR61,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_247 ,Interrupt 247 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_246 ,Interrupt 246 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_245 ,Interrupt 245 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_244 ,Interrupt 244 priority" group.long 0x4F8++0x03 line.long 0x00 "IPR62,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_251 ,Interrupt 251 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_250 ,Interrupt 250 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_249 ,Interrupt 249 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_248 ,Interrupt 248 priority" group.long 0x4FC++0x03 line.long 0x00 "IPR63,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_255 ,Interrupt 255 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_254 ,Interrupt 254 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_253 ,Interrupt 253 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_252 ,Interrupt 252 priority" else hgroup.long 0x4E0++0x03 hide.long 0x00 "IPR56,Interrupt Priority Register" hgroup.long 0x4E4++0x03 hide.long 0x00 "IPR57,Interrupt Priority Register" hgroup.long 0x4E8++0x03 hide.long 0x00 "IPR58,Interrupt Priority Register" hgroup.long 0x4EC++0x03 hide.long 0x00 "IPR59,Interrupt Priority Register" hgroup.long 0x4F0++0x03 hide.long 0x00 "IPR60,Interrupt Priority Register" hgroup.long 0x4F4++0x03 hide.long 0x00 "IPR61,Interrupt Priority Register" hgroup.long 0x4F8++0x03 hide.long 0x00 "IPR62,Interrupt Priority Register" hgroup.long 0x4FC++0x03 hide.long 0x00 "IPR63,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x500++0x03 line.long 0x00 "IPR64,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_259 ,Interrupt 259 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_258 ,Interrupt 258 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_257 ,Interrupt 257 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_256 ,Interrupt 256 priority" group.long 0x504++0x03 line.long 0x00 "IPR65,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_263 ,Interrupt 263 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_262 ,Interrupt 262 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_261 ,Interrupt 261 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_260 ,Interrupt 260 priority" group.long 0x508++0x03 line.long 0x00 "IPR66,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_267 ,Interrupt 267 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_266 ,Interrupt 266 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_265 ,Interrupt 265 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_264 ,Interrupt 264 priority" group.long 0x50C++0x03 line.long 0x00 "IPR67,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_271 ,Interrupt 271 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_270 ,Interrupt 270 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_269 ,Interrupt 269 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_268 ,Interrupt 268 priority" group.long 0x510++0x03 line.long 0x00 "IPR68,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_275 ,Interrupt 275 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_274 ,Interrupt 274 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_273 ,Interrupt 273 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_272 ,Interrupt 272 priority" group.long 0x514++0x03 line.long 0x00 "IPR69,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_279 ,Interrupt 279 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_278 ,Interrupt 278 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_277 ,Interrupt 277 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_276 ,Interrupt 276 priority" group.long 0x518++0x03 line.long 0x00 "IPR70,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_283 ,Interrupt 283 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_282 ,Interrupt 282 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_281 ,Interrupt 281 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_280 ,Interrupt 280 priority" group.long 0x51C++0x03 line.long 0x00 "IPR71,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_287 ,Interrupt 287 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_286 ,Interrupt 286 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_285 ,Interrupt 285 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_284 ,Interrupt 284 priority" else hgroup.long 0x500++0x03 hide.long 0x00 "IPR64,Interrupt Priority Register" hgroup.long 0x504++0x03 hide.long 0x00 "IPR65,Interrupt Priority Register" hgroup.long 0x508++0x03 hide.long 0x00 "IPR66,Interrupt Priority Register" hgroup.long 0x50C++0x03 hide.long 0x00 "IPR67,Interrupt Priority Register" hgroup.long 0x510++0x03 hide.long 0x00 "IPR68,Interrupt Priority Register" hgroup.long 0x514++0x03 hide.long 0x00 "IPR69,Interrupt Priority Register" hgroup.long 0x518++0x03 hide.long 0x00 "IPR70,Interrupt Priority Register" hgroup.long 0x51C++0x03 hide.long 0x00 "IPR71,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x520++0x03 line.long 0x00 "IPR72,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_291 ,Interrupt 291 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_290 ,Interrupt 290 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_289 ,Interrupt 289 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_288 ,Interrupt 288 priority" group.long 0x524++0x03 line.long 0x00 "IPR73,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_295 ,Interrupt 295 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_294 ,Interrupt 294 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_293 ,Interrupt 293 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_292 ,Interrupt 292 priority" group.long 0x528++0x03 line.long 0x00 "IPR74,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_299 ,Interrupt 299 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_298 ,Interrupt 298 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_297 ,Interrupt 297 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_296 ,Interrupt 296 priority" group.long 0x52C++0x03 line.long 0x00 "IPR75,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_303 ,Interrupt 303 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_302 ,Interrupt 302 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_301 ,Interrupt 301 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_300 ,Interrupt 300 priority" group.long 0x530++0x03 line.long 0x00 "IPR76,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_307 ,Interrupt 307 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_306 ,Interrupt 306 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_305 ,Interrupt 305 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_304 ,Interrupt 304 priority" group.long 0x534++0x03 line.long 0x00 "IPR77,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_311 ,Interrupt 311 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_310 ,Interrupt 310 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_309 ,Interrupt 309 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_308 ,Interrupt 308 priority" group.long 0x538++0x03 line.long 0x00 "IPR78,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_315 ,Interrupt 315 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_314 ,Interrupt 314 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_313 ,Interrupt 313 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_312 ,Interrupt 312 priority" group.long 0x53C++0x03 line.long 0x00 "IPR79,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_319 ,Interrupt 319 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_318 ,Interrupt 318 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_317 ,Interrupt 317 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_316 ,Interrupt 316 priority" else hgroup.long 0x520++0x03 hide.long 0x00 "IPR72,Interrupt Priority Register" hgroup.long 0x524++0x03 hide.long 0x00 "IPR73,Interrupt Priority Register" hgroup.long 0x528++0x03 hide.long 0x00 "IPR74,Interrupt Priority Register" hgroup.long 0x52C++0x03 hide.long 0x00 "IPR75,Interrupt Priority Register" hgroup.long 0x530++0x03 hide.long 0x00 "IPR76,Interrupt Priority Register" hgroup.long 0x534++0x03 hide.long 0x00 "IPR77,Interrupt Priority Register" hgroup.long 0x538++0x03 hide.long 0x00 "IPR78,Interrupt Priority Register" hgroup.long 0x53C++0x03 hide.long 0x00 "IPR79,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "IPR80,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_323 ,Interrupt 323 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_322 ,Interrupt 322 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_321 ,Interrupt 321 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_320 ,Interrupt 320 priority" group.long 0x544++0x03 line.long 0x00 "IPR81,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_327 ,Interrupt 327 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_326 ,Interrupt 326 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_325 ,Interrupt 325 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_324 ,Interrupt 324 priority" group.long 0x548++0x03 line.long 0x00 "IPR82,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_331 ,Interrupt 331 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_330 ,Interrupt 330 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_329 ,Interrupt 329 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_328 ,Interrupt 328 priority" group.long 0x54C++0x03 line.long 0x00 "IPR83,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_335 ,Interrupt 335 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_334 ,Interrupt 334 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_333 ,Interrupt 333 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_332 ,Interrupt 332 priority" group.long 0x550++0x03 line.long 0x00 "IPR84,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_339 ,Interrupt 339 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_338 ,Interrupt 338 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_337 ,Interrupt 337 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_336 ,Interrupt 336 priority" group.long 0x554++0x03 line.long 0x00 "IPR85,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_343 ,Interrupt 343 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_342 ,Interrupt 342 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_341 ,Interrupt 341 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_340 ,Interrupt 340 priority" group.long 0x558++0x03 line.long 0x00 "IPR86,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_347 ,Interrupt 347 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_346 ,Interrupt 346 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_345 ,Interrupt 345 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_344 ,Interrupt 344 priority" group.long 0x55C++0x03 line.long 0x00 "IPR87,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_351 ,Interrupt 351 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_350 ,Interrupt 350 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_349 ,Interrupt 349 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_348 ,Interrupt 348 priority" else hgroup.long 0x540++0x03 hide.long 0x00 "IPR80,Interrupt Priority Register" hgroup.long 0x544++0x03 hide.long 0x00 "IPR81,Interrupt Priority Register" hgroup.long 0x548++0x03 hide.long 0x00 "IPR82,Interrupt Priority Register" hgroup.long 0x54C++0x03 hide.long 0x00 "IPR83,Interrupt Priority Register" hgroup.long 0x550++0x03 hide.long 0x00 "IPR84,Interrupt Priority Register" hgroup.long 0x554++0x03 hide.long 0x00 "IPR85,Interrupt Priority Register" hgroup.long 0x558++0x03 hide.long 0x00 "IPR86,Interrupt Priority Register" hgroup.long 0x55C++0x03 hide.long 0x00 "IPR87,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "IPR88,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_355 ,Interrupt 355 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_354 ,Interrupt 354 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_353 ,Interrupt 353 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_352 ,Interrupt 352 priority" group.long 0x564++0x03 line.long 0x00 "IPR89,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_359 ,Interrupt 359 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_358 ,Interrupt 358 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_357 ,Interrupt 357 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_356 ,Interrupt 356 priority" group.long 0x568++0x03 line.long 0x00 "IPR90,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_363 ,Interrupt 363 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_362 ,Interrupt 362 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_361 ,Interrupt 361 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_360 ,Interrupt 360 priority" group.long 0x56C++0x03 line.long 0x00 "IPR91,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_367 ,Interrupt 367 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_366 ,Interrupt 366 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_365 ,Interrupt 365 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_364 ,Interrupt 364 priority" group.long 0x570++0x03 line.long 0x00 "IPR92,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_371 ,Interrupt 371 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_370 ,Interrupt 370 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_369 ,Interrupt 369 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_368 ,Interrupt 368 priority" group.long 0x574++0x03 line.long 0x00 "IPR93,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_375 ,Interrupt 375 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_374 ,Interrupt 374 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_373 ,Interrupt 373 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_372 ,Interrupt 372 priority" group.long 0x578++0x03 line.long 0x00 "IPR94,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_379 ,Interrupt 379 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_378 ,Interrupt 378 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_377 ,Interrupt 377 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_376 ,Interrupt 376 priority" group.long 0x57C++0x03 line.long 0x00 "IPR95,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_383 ,Interrupt 383 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_382 ,Interrupt 382 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_381 ,Interrupt 381 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_380 ,Interrupt 380 priority" else hgroup.long 0x560++0x03 hide.long 0x00 "IPR88,Interrupt Priority Register" hgroup.long 0x564++0x03 hide.long 0x00 "IPR89,Interrupt Priority Register" hgroup.long 0x568++0x03 hide.long 0x00 "IPR90,Interrupt Priority Register" hgroup.long 0x56C++0x03 hide.long 0x00 "IPR91,Interrupt Priority Register" hgroup.long 0x570++0x03 hide.long 0x00 "IPR92,Interrupt Priority Register" hgroup.long 0x574++0x03 hide.long 0x00 "IPR93,Interrupt Priority Register" hgroup.long 0x578++0x03 hide.long 0x00 "IPR94,Interrupt Priority Register" hgroup.long 0x57C++0x03 hide.long 0x00 "IPR95,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "IPR96,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_387 ,Interrupt 387 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_386 ,Interrupt 386 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_385 ,Interrupt 385 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_384 ,Interrupt 384 priority" group.long 0x584++0x03 line.long 0x00 "IPR97,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_391 ,Interrupt 391 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_390 ,Interrupt 390 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_389 ,Interrupt 389 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_388 ,Interrupt 388 priority" group.long 0x588++0x03 line.long 0x00 "IPR98,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_395 ,Interrupt 395 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_394 ,Interrupt 394 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_393 ,Interrupt 393 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_392 ,Interrupt 392 priority" group.long 0x58C++0x03 line.long 0x00 "IPR99,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_399 ,Interrupt 399 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_398 ,Interrupt 398 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_397 ,Interrupt 397 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_396 ,Interrupt 396 priority" group.long 0x590++0x03 line.long 0x00 "IPR100,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_403 ,Interrupt 403 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_402 ,Interrupt 402 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_401 ,Interrupt 401 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_400 ,Interrupt 400 priority" group.long 0x594++0x03 line.long 0x00 "IPR101,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_407 ,Interrupt 407 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_406 ,Interrupt 406 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_405 ,Interrupt 405 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_404 ,Interrupt 404 priority" group.long 0x598++0x03 line.long 0x00 "IPR102,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_411 ,Interrupt 411 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_410 ,Interrupt 410 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_409 ,Interrupt 409 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_408 ,Interrupt 408 priority" group.long 0x59C++0x03 line.long 0x00 "IPR103,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_415 ,Interrupt 415 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_414 ,Interrupt 414 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_413 ,Interrupt 413 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_412 ,Interrupt 412 priority" else hgroup.long 0x580++0x03 hide.long 0x00 "IPR96,Interrupt Priority Register" hgroup.long 0x584++0x03 hide.long 0x00 "IPR97,Interrupt Priority Register" hgroup.long 0x588++0x03 hide.long 0x00 "IPR98,Interrupt Priority Register" hgroup.long 0x58C++0x03 hide.long 0x00 "IPR99,Interrupt Priority Register" hgroup.long 0x590++0x03 hide.long 0x00 "IPR100,Interrupt Priority Register" hgroup.long 0x594++0x03 hide.long 0x00 "IPR101,Interrupt Priority Register" hgroup.long 0x598++0x03 hide.long 0x00 "IPR102,Interrupt Priority Register" hgroup.long 0x59C++0x03 hide.long 0x00 "IPR103,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "IPR104,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_419 ,Interrupt 419 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_418 ,Interrupt 418 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_417 ,Interrupt 417 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_416 ,Interrupt 416 priority" group.long 0x5A4++0x03 line.long 0x00 "IPR105,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_423 ,Interrupt 423 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_422 ,Interrupt 422 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_421 ,Interrupt 421 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_420 ,Interrupt 420 priority" group.long 0x5A8++0x03 line.long 0x00 "IPR106,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_427 ,Interrupt 427 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_426 ,Interrupt 426 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_425 ,Interrupt 425 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_424 ,Interrupt 424 priority" group.long 0x5AC++0x03 line.long 0x00 "IPR107,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_431 ,Interrupt 431 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_430 ,Interrupt 430 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_429 ,Interrupt 429 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_428 ,Interrupt 428 priority" group.long 0x5B0++0x03 line.long 0x00 "IPR108,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_435 ,Interrupt 435 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_434 ,Interrupt 434 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_433 ,Interrupt 433 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_432 ,Interrupt 432 priority" group.long 0x5B4++0x03 line.long 0x00 "IPR109,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_439 ,Interrupt 439 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_438 ,Interrupt 438 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_437 ,Interrupt 437 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_436 ,Interrupt 436 priority" group.long 0x5B8++0x03 line.long 0x00 "IPR110,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_443 ,Interrupt 443 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_442 ,Interrupt 442 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_441 ,Interrupt 441 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_440 ,Interrupt 440 priority" group.long 0x5BC++0x03 line.long 0x00 "IPR111,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_447 ,Interrupt 447 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_446 ,Interrupt 446 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_445 ,Interrupt 445 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_444 ,Interrupt 444 priority" else hgroup.long 0x5A0++0x03 hide.long 0x00 "IPR104,Interrupt Priority Register" hgroup.long 0x5A4++0x03 hide.long 0x00 "IPR105,Interrupt Priority Register" hgroup.long 0x5A8++0x03 hide.long 0x00 "IPR106,Interrupt Priority Register" hgroup.long 0x5AC++0x03 hide.long 0x00 "IPR107,Interrupt Priority Register" hgroup.long 0x5B0++0x03 hide.long 0x00 "IPR108,Interrupt Priority Register" hgroup.long 0x5B4++0x03 hide.long 0x00 "IPR109,Interrupt Priority Register" hgroup.long 0x5B8++0x03 hide.long 0x00 "IPR110,Interrupt Priority Register" hgroup.long 0x5BC++0x03 hide.long 0x00 "IPR111,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "IPR112,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_451 ,Interrupt 451 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_450 ,Interrupt 450 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_449 ,Interrupt 449 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_448 ,Interrupt 448 priority" group.long 0x5C4++0x03 line.long 0x00 "IPR113,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_455 ,Interrupt 455 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_454 ,Interrupt 454 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_453 ,Interrupt 453 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_452 ,Interrupt 452 priority" group.long 0x5C8++0x03 line.long 0x00 "IPR114,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_459 ,Interrupt 459 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_458 ,Interrupt 458 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_457 ,Interrupt 457 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_456 ,Interrupt 456 priority" group.long 0x5CC++0x03 line.long 0x00 "IPR115,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_463 ,Interrupt 463 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_462 ,Interrupt 462 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_461 ,Interrupt 461 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_460 ,Interrupt 460 priority" group.long 0x5D0++0x03 line.long 0x00 "IPR116,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_467 ,Interrupt 467 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_466 ,Interrupt 466 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_465 ,Interrupt 465 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_464 ,Interrupt 464 priority" group.long 0x5D4++0x03 line.long 0x00 "IPR117,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_471 ,Interrupt 471 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_470 ,Interrupt 470 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_469 ,Interrupt 469 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_468 ,Interrupt 468 priority" group.long 0x5D8++0x03 line.long 0x00 "IPR118,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_475 ,Interrupt 475 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_474 ,Interrupt 474 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_473 ,Interrupt 473 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_472 ,Interrupt 472 priority" group.long 0x5DC++0x03 line.long 0x00 "IPR119,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_479 ,Interrupt 479 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_478 ,Interrupt 478 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_477 ,Interrupt 477 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_476 ,Interrupt 476 priority" else hgroup.long 0x5C0++0x03 hide.long 0x00 "IPR112,Interrupt Priority Register" hgroup.long 0x5C4++0x03 hide.long 0x00 "IPR113,Interrupt Priority Register" hgroup.long 0x5C8++0x03 hide.long 0x00 "IPR114,Interrupt Priority Register" hgroup.long 0x5CC++0x03 hide.long 0x00 "IPR115,Interrupt Priority Register" hgroup.long 0x5D0++0x03 hide.long 0x00 "IPR116,Interrupt Priority Register" hgroup.long 0x5D4++0x03 hide.long 0x00 "IPR117,Interrupt Priority Register" hgroup.long 0x5D8++0x03 hide.long 0x00 "IPR118,Interrupt Priority Register" hgroup.long 0x5DC++0x03 hide.long 0x00 "IPR119,Interrupt Priority Register" endif tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writable from the non-secure state" "Writable,Write ignored" textline " " bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled" bitfld.long 0x00 27. " CLRONRETS ,Clear on return secure only" "Both states,Secure only" bitfld.long 0x00 26. " TS ,Treat as secure" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the usage fault exception to pending" "Not able,Able" bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the debug monitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the secure fault exception to pending" "Not able,Able" bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the bus fault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the mem manage exception to pending" "Not able,Able" textline " " bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the hard fault exception to pending" "Not able,Able" bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure" textline " " bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x08 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" bitfld.long 0x08 19. " FZ16 ,Flush-to-zero mode control bit on half-precision data-processing instructions" "Disabled,Enabled" bitfld.long 0x08 16.--18. " LTPSIZE ,Vector element size used when applying low-overhead-loop tail predication to vector instructions" "8-bit,16-bit,32-bit,64-bit,Not applied,?..." rgroup.long 0xF40++0x0B line.long 0x00 "MVFR0,Media And FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" "Not supported,All supported,?..." bitfld.long 0x00 20.--23. " FPSQRT ,Indicates the hardware support for FP square root operations" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" "Not supported,Supported,?..." textline " " bitfld.long 0x00 8.--11. " FPDP ,Indicates the hardware support for FP double precision operations" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " FPSP ,Indicates the hardware support for FP single-precision operations" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" "Reserved,Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media And FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" "Not supported,Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" "Not supported,Half-single,Half-single/double,?..." bitfld.long 0x04 20.--23. " FP16 ,Floating-point half-precision data processing" "Not supported,Supported,?..." textline " " bitfld.long 0x04 8.--11. " MVE ,Indicates support for M-profile vector extension" "Not supported,Supported no FP,Supported with FP,?..." bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the default NaN mode" "Not supported,NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the flush-to-zero mode of operation" "Not supported,Fully denormalized,?..." line.long 0x08 "MVFR2,Media And FP Feature Register 2" bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,Reserved,Reserved,Reserved,Supported,?..." width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 13. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 5. " PMU ,Indicates whether a PMU counter overflow event has occurred" "Not occurred,Occurred" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a vector catch" "Not triggered,Triggered" newline eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates that a halt request debug event or step debug event has occurred" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control And Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register special-purpose register or floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception And Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 23. " MONPRKEY ,Writes to the MON_PEND and MON_REQ fields are ignored" "Not ignored,Ignored" newline bitfld.long 0x00 21. " UMON_EN ,Unprivileged monitor enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the secure or the non-secure state" "Non-secure,Secure" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" newline bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a hard fault exception" "Disabled,Enabled" bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" newline bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a bus fault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a usage fault exception caused by a state information error" "Disabled,Enabled" bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a usage fault exception caused by a checking error" "Disabled,Enabled" newline bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a usage fault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a mem manage exception" "Disabled,Enabled" bitfld.long 0x00 0. " VC_CORERESET ,Enable reset vector catch" "Disabled,Enabled" newline group.long 0xE04++0x07 line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register" bitfld.long 0x00 10. " UIDEN ,Unprivileged invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 9. " UIDAPEN ,Unprivileged invasive dap access enable" "Disabled,Enabled" bitfld.long 0x00 8. " FSDMA ,Force secure debug monitor allowed" "Not allowed,Allowed" newline bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN" bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN" newline line.long 0x04 "DSCSR,Debug Security Control And Status Register" bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored" newline bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure" bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure" bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled" rgroup.long 0xFB8++0x03 line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 22.--23. " SUNID ,Secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 20.--21. " SUID ,Secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 18.--19. " NSUNID ,Non-secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" newline bitfld.long 0x00 16.--17. " NSUID ,Non-secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 6.--7. " SNID ,Secure non-invasive debug" "Not implemented,Reserved,Implemented/Disabled,Implemented/Enabled" bitfld.long 0x00 4.--5. " SID ,Secure invasive debug" "Not implemented,Reserved,Implemented/Disabled,Implemented/Enabled" newline bitfld.long 0x00 2.--3. " NSNID ,Non-secure non-invasive debug" "Reserved,Reserved,Prohibited,Allowed" bitfld.long 0x00 0.--1. " NSID ,Non-secure invasive debug" "Reserved,Reserved,Prohibited,Allowed" group.long 0x10300++0x07 line.long 0x00 "CPDLPSTATE,Core Power Domain Low Power State Register" bitfld.long 0x00 8.--9. " RLPSTATE ,Power-on state for PDRAMS power domain" "ON,Reserved,Reserved,OFF" bitfld.long 0x00 4.--5. " ELPSTATE ,Type of low-power state for PDEPU" "ON,ON clock off,RET,OFF" bitfld.long 0x00 0.--1. " CLPSTATE ,Type of low-power state for PDCORE" "ON,ON clock off,RET,OFF" line.long 0x04 "DPDLPSTATE,Debug Power Domain Low Power State Register" bitfld.long 0x04 0.--1. " DLPSTATE ,Type of low-power state for PDDEBUG" "ON,ON clock off,Reserved,OFF" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "BreakPoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 12. group.long 0x00++0x03 line.long 0x00 "FP_CTRL,Flash Patch Control Register" rbitfld.long 0x00 28.--31. " REV ,Flash patch breakpoint architecture revision" "Reserved,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "Not implemented,1,2,3,4,5,6,7,8,?..." rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1. " KEY ,FP_CTRL write-enable key" "Ignored,Permitted" bitfld.long 0x00 0. " ENABLE ,Flash patch unit enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "FP_REMAP,Flash Patch Remap Register" group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between remapping and breakpoint functionality" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between remapping and breakpoint functionality" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between remapping and breakpoint functionality" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between remapping and breakpoint functionality" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between remapping and breakpoint functionality" "Disabled,Enabled" group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between remapping and breakpoint functionality" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between remapping and breakpoint functionality" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between remapping and breakpoint functionality" "Disabled,Enabled" textline " " width 12. rgroup.long 0xFBC++0x03 line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Reserved,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "FPB v2,?..." textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "Reserved,FPB v2,?..." hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" tree "Peripheral Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "FP_PIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]" line.long 0x04 "FP_PIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]" line.long 0x08 "FP_PIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "FP_PIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "FP_CIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "FP_CIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0C "FP_CIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0B else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 16. group.long 0x00++0x03 line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "Not supported,1,2,3,4,5,6,7,8,?..." rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" textline " " rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in secure state" "No,Yes" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000) group.long 0x04++0x03 line.long 0x00 "DWT_CYCCNT,Cycle Count Register" else rgroup.long 0x04++0x03 line.long 0x00 "DWT_CYCCNT,Cycle Count Register" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000) group.long 0x08++0x13 line.long 0x00 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter" line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep counter" line.long 0x0C "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x0C 0.--7. 1. " LSUCNT ,Load-store overhead counter" line.long 0x10 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x10 0.--7. 1. " FOLDCNT ,Folded-instruction counter" else rgroup.long 0x08++0x13 line.long 0x00 "DWT_CPICNT,CPI Count Register" line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register" line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register" line.long 0x0C "DWT_LSUCNT,LSU Count Register" line.long 0x10 "DWT_FOLDCNT,Folded-instruction Count Register" endif rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample Register" textline " " if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0x0F)==0x01) group.long 0x20++0x03 "Comparator 0" line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0x0F)>=0x02&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0x0F)<0x04) group.long 0x20++0x03 "Comparator 0" line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0x0F)>=0x08&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0x0F)<0x0C) group.long 0x20++0x03 "Comparator 0" line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0x0F)>=0x04&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0x0F)<0x08||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0x0F)>=0x0C&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0x0F)<0x0F) group.long 0x20++0x03 "Comparator 0" line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else rgroup.long 0x20++0x03 "Comparator 0" line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" endif group.long (0x20+0x08)++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address with value,Cycle counter/data address/data address with value,Instruction address/data address/data address with value,Cycle counter/instruction address/data address/data address with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address limit/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data address with value,Reserved,Data address/data address limit/data value/linked data value/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data value/linked data value/data address with value,?..." textline " " rbitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" textline " " bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0F)==0x01) group.long 0x30++0x03 "Comparator 1" line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0F)>=0x02&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0F)<0x04) group.long 0x30++0x03 "Comparator 1" line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0F)>=0x08&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0F)<0x0C) group.long 0x30++0x03 "Comparator 1" line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0F)>=0x04&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0F)<0x08||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0F)>=0x0C&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0F)<0x0F) group.long 0x30++0x03 "Comparator 1" line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else rgroup.long 0x30++0x03 "Comparator 1" line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" endif group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address with value,Cycle counter/data address/data address with value,Instruction address/data address/data address with value,Cycle counter/instruction address/data address/data address with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address limit/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data address with value,Reserved,Data address/data address limit/data value/linked data value/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data value/linked data value/data address with value,?..." textline " " rbitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" textline " " bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0C)==(0x08||0x09||0x0A||0x0B)) group.long (0x30+0x0C)++0x03 line.long 0x00 "DWT_VMASK1,DWT Comparator Value Mask Register" bitfld.long 0x00 31. " VMASK[31] ,Data value mask 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Data value mask 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Data value mask 29" "Not masked,Masked" textline " " bitfld.long 0x00 28. " [28] ,Data value mask 28" "Not masked,Masked" bitfld.long 0x00 27. " [27] ,Data value mask 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Data value mask 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " [25] ,Data value mask 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Data value mask 24" "Not masked,Masked" bitfld.long 0x00 23. " [23] ,Data value mask 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " [22] ,Data value mask 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Data value mask 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Data value mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Data value mask 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Data value mask 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Data value mask 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " [16] ,Data value mask 16" "Not masked,Masked" bitfld.long 0x00 15. " [15] ,Data value mask 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Data value mask 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " [13] ,Data value mask 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Data value mask 12" "Not masked,Masked" bitfld.long 0x00 11. " [11] ,Data value mask 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " [10] ,Data value mask 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Data value mask 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Data value mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Data value mask 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Data value mask 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Data value mask 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " [4] ,Data value mask 4" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,Data value mask 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Data value mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " [1] ,Data value mask 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Data value mask 0" "Not masked,Masked" else rgroup.long (0x30+0x0C)++0x03 line.long 0x00 "DWT_VMASK1,DWT Comparator Value Mask Register" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0x0F)==0x01) group.long 0x40++0x03 "Comparator 2" line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0x0F)>=0x02&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0x0F)<0x04) group.long 0x40++0x03 "Comparator 2" line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0x0F)>=0x08&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0x0F)<0x0C) group.long 0x40++0x03 "Comparator 2" line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0x0F)>=0x04&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0x0F)<0x08||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0x0F)>=0x0C&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0x0F)<0x0F) group.long 0x40++0x03 "Comparator 2" line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else rgroup.long 0x40++0x03 "Comparator 2" line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" endif group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address with value,Cycle counter/data address/data address with value,Instruction address/data address/data address with value,Cycle counter/instruction address/data address/data address with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address limit/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data address with value,Reserved,Data address/data address limit/data value/linked data value/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data value/linked data value/data address with value,?..." textline " " rbitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" textline " " bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0F)==0x01) group.long 0x50++0x03 "Comparator 3" line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0F)>=0x02&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0F)<0x04) group.long 0x50++0x03 "Comparator 3" line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0F)>=0x08&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0F)<0x0C) group.long 0x50++0x03 "Comparator 3" line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0F)>=0x04&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0F)<0x08||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0F)>=0x0C&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0F)<0x0F) group.long 0x50++0x03 "Comparator 3" line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else rgroup.long 0x50++0x03 "Comparator 3" line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" endif group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address with value,Cycle counter/data address/data address with value,Instruction address/data address/data address with value,Cycle counter/instruction address/data address/data address with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address limit/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data address with value,Reserved,Data address/data address limit/data value/linked data value/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data value/linked data value/data address with value,?..." textline " " rbitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" textline " " bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0C)==(0x08||0x09||0x0A||0x0B)) group.long (0x50+0x0C)++0x03 line.long 0x00 "DWT_VMASK3,DWT Comparator Value Mask Register" bitfld.long 0x00 31. " VMASK[31] ,Data value mask 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Data value mask 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Data value mask 29" "Not masked,Masked" textline " " bitfld.long 0x00 28. " [28] ,Data value mask 28" "Not masked,Masked" bitfld.long 0x00 27. " [27] ,Data value mask 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Data value mask 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " [25] ,Data value mask 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Data value mask 24" "Not masked,Masked" bitfld.long 0x00 23. " [23] ,Data value mask 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " [22] ,Data value mask 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Data value mask 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Data value mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " [19] ,Data value mask 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Data value mask 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Data value mask 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " [16] ,Data value mask 16" "Not masked,Masked" bitfld.long 0x00 15. " [15] ,Data value mask 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Data value mask 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " [13] ,Data value mask 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Data value mask 12" "Not masked,Masked" bitfld.long 0x00 11. " [11] ,Data value mask 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " [10] ,Data value mask 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Data value mask 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Data value mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " [7] ,Data value mask 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Data value mask 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Data value mask 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " [4] ,Data value mask 4" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,Data value mask 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Data value mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " [1] ,Data value mask 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Data value mask 0" "Not masked,Masked" else rgroup.long (0x50+0x0C)++0x03 line.long 0x00 "DWT_VMASK3,DWT Comparator Value Mask Register" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0x0F)==0x01) group.long 0x60++0x03 "Comparator 4" line.long 0x00 "DWT_COMP4,DWT Comparator Register 4" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0x0F)>=0x02&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0x0F)<0x04) group.long 0x60++0x03 "Comparator 4" line.long 0x00 "DWT_COMP4,DWT Comparator Register 4" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0x0F)>=0x08&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0x0F)<0x0C) group.long 0x60++0x03 "Comparator 4" line.long 0x00 "DWT_COMP4,DWT Comparator Register 4" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0x0F)>=0x04&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0x0F)<0x08||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0x0F)>=0x0C&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0x0F)<0x0F) group.long 0x60++0x03 "Comparator 4" line.long 0x00 "DWT_COMP4,DWT Comparator Register 4" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else rgroup.long 0x60++0x03 "Comparator 4" line.long 0x00 "DWT_COMP4,DWT Comparator Register 4" endif group.long (0x60+0x08)++0x03 line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address with value,Cycle counter/data address/data address with value,Instruction address/data address/data address with value,Cycle counter/instruction address/data address/data address with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address limit/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data address with value,Reserved,Data address/data address limit/data value/linked data value/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data value/linked data value/data address with value,?..." textline " " rbitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" textline " " bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0x0F)==0x01) group.long 0x70++0x03 "Comparator 5" line.long 0x00 "DWT_COMP5,DWT Comparator Register 5" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0x0F)>=0x02&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0x0F)<0x04) group.long 0x70++0x03 "Comparator 5" line.long 0x00 "DWT_COMP5,DWT Comparator Register 5" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0x0F)>=0x08&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0x0F)<0x0C) group.long 0x70++0x03 "Comparator 5" line.long 0x00 "DWT_COMP5,DWT Comparator Register 5" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0x0F)>=0x04&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0x0F)<0x08||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0x0F)>=0x0C&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0x0F)<0x0F) group.long 0x70++0x03 "Comparator 5" line.long 0x00 "DWT_COMP5,DWT Comparator Register 5" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else rgroup.long 0x70++0x03 "Comparator 5" line.long 0x00 "DWT_COMP5,DWT Comparator Register 5" endif group.long (0x70+0x08)++0x03 line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address with value,Cycle counter/data address/data address with value,Instruction address/data address/data address with value,Cycle counter/instruction address/data address/data address with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address limit/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data address with value,Reserved,Data address/data address limit/data value/linked data value/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data value/linked data value/data address with value,?..." textline " " rbitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" textline " " bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0x0F)==0x01) group.long 0x80++0x03 "Comparator 6" line.long 0x00 "DWT_COMP6,DWT Comparator Register 6" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0x0F)>=0x02&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0x0F)<0x04) group.long 0x80++0x03 "Comparator 6" line.long 0x00 "DWT_COMP6,DWT Comparator Register 6" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0x0F)>=0x08&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0x0F)<0x0C) group.long 0x80++0x03 "Comparator 6" line.long 0x00 "DWT_COMP6,DWT Comparator Register 6" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0x0F)>=0x04&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0x0F)<0x08||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0x0F)>=0x0C&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0x0F)<0x0F) group.long 0x80++0x03 "Comparator 6" line.long 0x00 "DWT_COMP6,DWT Comparator Register 6" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else rgroup.long 0x80++0x03 "Comparator 6" line.long 0x00 "DWT_COMP6,DWT Comparator Register 6" endif group.long (0x80+0x08)++0x03 line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address with value,Cycle counter/data address/data address with value,Instruction address/data address/data address with value,Cycle counter/instruction address/data address/data address with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address limit/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data address with value,Reserved,Data address/data address limit/data value/linked data value/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data value/linked data value/data address with value,?..." textline " " rbitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" textline " " bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0x0F)==0x01) group.long 0x90++0x03 "Comparator 7" line.long 0x00 "DWT_COMP7,DWT Comparator Register 7" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0x0F)>=0x02&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0x0F)<0x04) group.long 0x90++0x03 "Comparator 7" line.long 0x00 "DWT_COMP7,DWT Comparator Register 7" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0x0F)>=0x08&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0x0F)<0x0C) group.long 0x90++0x03 "Comparator 7" line.long 0x00 "DWT_COMP7,DWT Comparator Register 7" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0x0F)>=0x04&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0x0F)<0x08||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0x0F)>=0x0C&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0x0F)<0x0F) group.long 0x90++0x03 "Comparator 7" line.long 0x00 "DWT_COMP7,DWT Comparator Register 7" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else rgroup.long 0x90++0x03 "Comparator 7" line.long 0x00 "DWT_COMP7,DWT Comparator Register 7" endif group.long (0x90+0x08)++0x03 line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address with value,Cycle counter/data address/data address with value,Instruction address/data address/data address with value,Cycle counter/instruction address/data address/data address with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data address/data address limit/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data address with value,Reserved,Data address/data address limit/data value/linked data value/data address with value,Reserved,Instruction address/instruction address limit/data address/data address limit/data value/linked data value/data address with value,?..." textline " " rbitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" textline " " bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." width 13. newline rgroup.long 0xFBC++0x03 line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "DWT v2.0,DWT v2.1,?..." textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "Reserved,DWT v2,?..." hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" rgroup.long 0xFCC++0x03 line.long 0x00 "DWT_DEVTYPE,Device Type Identifier Register" bitfld.long 0x00 4.--7. " SUB ,Sub-type" "Other,?..." bitfld.long 0x00 0.--3. " MAJOR ,Major type" "Miscellaneous,?..." tree "Peripheral Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "DWT_PIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]" line.long 0x04 "DWT_PIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]" line.long 0x08 "DWT_PIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "DWT_PIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x0F line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" line.long 0x04 "DWT_PIDR5,Peripheral Identification Register 5" line.long 0x08 "DWT_PIDR6,Peripheral Identification Register 6" line.long 0x0C "DWT_PIDR7,Peripheral Identification Register 7" rgroup.long 0xFF0++0x0F line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "DWT_CIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "DWT_CIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0C "DWT_CIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree "Performance Monitoring Unit Extension (PMU)" sif COMPonent.AVAILABLE("BMC") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1)) width 16. group.long 0x0++0x03 line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register 0" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x4++0x03 line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register 1" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x8++0x03 line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register 2" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0xC++0x03 line.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register 3" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x10++0x03 line.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register 4" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x14++0x03 line.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register 5" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x18++0x03 line.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register 6" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x1C++0x03 line.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register 7" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x7C++0x03 line.long 0x00 "PMU_CCNTR,Performance Monitoring Unit Cycle Counter Register" group.long 0x400++0x03 line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type And Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x404++0x03 line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type And Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x408++0x03 line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type And Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x40C++0x03 line.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type And Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x410++0x03 line.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type And Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x414++0x03 line.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type And Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x418++0x03 line.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type And Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x41C++0x03 line.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type And Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" rgroup.long 0x47C++0x03 line.long 0x00 "PMU_CCFILTR,Performance Monitoring Unit Cycle Counter Filter Register" group.long 0xC00++0x03 line.long 0x00 "PMU_CNTENSET,Performance Monitoring Unit Count Enable Set Register" bitfld.long 0x00 31. " C ,Cycle counter enable bit" "Disabled,Enabled" bitfld.long 0x00 7. " P7 ,Event counter PMN 7 enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,Event counter PMN 6 enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " P5 ,Event counter PMN 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event counter PMN 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,Event counter PMN 3 enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,Event counter PMN 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event counter PMN 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event counter PMN 0 enable bit" "Disabled,Enabled" group.long 0xC20++0x03 line.long 0x00 "PMU_CNTENCLR,Performance Monitoring Unit Count Enable Clear Register" bitfld.long 0x00 31. " C ,Cycle counter enable bit" "Disabled,Enabled" bitfld.long 0x00 7. " P7 ,Event counter PMN 7 enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,Event counter PMN 6 enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " P5 ,Event counter PMN 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event counter PMN 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,Event counter PMN 3 enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,Event counter PMN 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event counter PMN 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event counter PMN 0 enable bit" "Disabled,Enabled" group.long 0xC40++0x03 line.long 0x00 "PMU_INTENSET,Performance Monitoring Unit Interrupt Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " P7 ,PMCNT7 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,PMCNT6 overflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " P5 ,PMCNT5 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMCNT2 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 overflow interrupt enable" "Disabled,Enabled" group.long 0xC60++0x03 line.long 0x00 "PMU_INTENCLR,Performance Monitoring Unit Interrupt Enable Clear Register" bitfld.long 0x00 31. " C ,CCNT overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " P7 ,PMCNT7 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,PMCNT6 overflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " P5 ,PMCNT5 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 overflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMCNT2 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 overflow interrupt enable" "Disabled,Enabled" group.long 0xC80++0x03 line.long 0x00 "PMU_OVSCLR,Performance Monitoring Unit Overflow Flag Status Clear Register" bitfld.long 0x00 31. " C ,PMCCNTR overflow" "No overflow,Overflow" bitfld.long 0x00 7. " P7 ,PMN7 overflow" "No overflow,Overflow" bitfld.long 0x00 6. " P6 ,PMN6 overflow" "No overflow,Overflow" textline " " bitfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" bitfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow" bitfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow" textline " " bitfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" bitfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" bitfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" wgroup.long 0xCA0++0x03 line.long 0x00 "PMU_SWINC,Performance Monitoring Unit Software Increment Register" bitfld.long 0x00 7. " P7 ,PMN7 software increment" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,PMN6 software increment" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 software increment" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " P4 ,PMN4 software increment" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 software increment" "Disabled,Enabled" bitfld.long 0x00 2. " P2 ,PMN2 software increment" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " P1 ,PMN1 software increment" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 software increment" "Disabled,Enabled" group.long 0xCC0++0x03 line.long 0x00 "PMU_OVSSET,Performance Monitoring Unit Overflow Flag Status Set Register" bitfld.long 0x00 31. " C ,PMCCNTR overflow" "No overflow,Overflow" bitfld.long 0x00 7. " P7 ,PMN7 overflow" "No overflow,Overflow" bitfld.long 0x00 6. " P6 ,PMN6 overflow" "No overflow,Overflow" textline " " bitfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" bitfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow" bitfld.long 0x00 3. " P3 ,PMN3 Overflow" "No overflow,Overflow" textline " " bitfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" bitfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" bitfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" rgroup.long 0xE00++0x03 line.long 0x00 "PMU_TYPE,Performance Monitoring Unit Type Register" bitfld.long 0x00 23. " TRO ,Trace-on-overflow support" "Not supported,Supported" bitfld.long 0x00 21. " FZO ,Freeze-on-overflow support" "Not supported,Supported" textline " " bitfld.long 0x00 14. " CC ,Dedicated cycle counter" "Disabled,Enabled" bitfld.long 0x00 8.--13. " SIZE ,Size of counters" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" hexmask.long.byte 0x00 0.--7. 1. " N ,Number of event counters" group.long 0xE04++0x03 line.long 0x00 "PMU_CTRL,Performance Monitors Unit Control Register" bitfld.long 0x00 11. " TRO ,Trace-on-overflow" "Disabled,Enabled" bitfld.long 0x00 9. " FZO ,Freeze-on-overflow" "Disabled,Enabled" bitfld.long 0x00 5. " DP ,Disable cycle counter in prohibited regions" "No,Yes" textline " " bitfld.long 0x00 2. " C ,Clock counter reset" "No reset,Reset" bitfld.long 0x00 1. " P ,Event counter reset" "No reset,Reset" bitfld.long 0x00 0. " E ,Counters enable" "Disabled,Enabled" rgroup.long 0xFB8++0x03 line.long 0x00 "PMU_AUTHSTATUS,Performance Monitoring Unit Authentication Status Register" bitfld.long 0x00 22.--23. " SUNID ,Secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 20.--21. " SUID ,Secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 18.--19. " NSUNID ,Non-secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" textline " " bitfld.long 0x00 16.--17. " NSUID ,Non-secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 6.--7. " SNID ,Secure non-invasive debug" "Not implemented,Reserved,Implemented/Prohibited,Implemented/Allowed" bitfld.long 0x00 4.--5. " SID ,Secure invasive debug" "Not implemented,Reserved,Implemented/Prohibited,Implemented/Allowed" textline " " bitfld.long 0x00 2.--3. " NSNID ,Non-secure non-invasive debug" "Reserved,Reserved,Prohibited,Allowed" bitfld.long 0x00 0.--1. " NSID ,Non-secure invasive debug" "Reserved,Reserved,Prohibited,Allowed" rgroup.long 0xFBC++0x03 line.long 0x00 "PMU_DEVARCH,Performance Monitoring Unit Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Defines the architect of the component" bitfld.long 0x00 20. " PRESENT ,Defines that the DEVARCH register is present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Defines the architecture revision" "Armv8.1-M,?..." textline " " hexmask.long.word 0x00 0.--15. 1. " ARCHID ,Defines this part to be a ARMv8-M debug component" rgroup.long 0xFCC++0x03 line.long 0x00 "PMU_DEVTYPE,Device Type Register" bitfld.long 0x00 4.--7. " SUB ,Sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " MAJOR ,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree "Peripheral Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PMU_PIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]" line.long 0x04 "PMU_PIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]" line.long 0x08 "PMU_PIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PMU_PIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x0F line.long 0x00 "PMU_PIDR4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" line.long 0x04 "PMU_PIDR5,Peripheral Identification Register 5" line.long 0x08 "PMU_PIDR6,Peripheral Identification Register 6" line.long 0x0C "PMU_PIDR7,Peripheral Identification Register 7" rgroup.long 0xFF0++0x0F line.long 0x00 "PMU_CIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "PMU_CIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class preamble" line.long 0x08 "PMU_CIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0C "PMU_CIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0B else newline textline "BMC component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "ADC (Analog-to-Digital Converter)" base ad:0x0 tree "ADC1" base ad:0x40022000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 10. "JQOVF,Injected context queue overflow" "0: No injected context queue overflow occurred (or..,1: Injected context queue overflow has occurred" bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" newline bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" newline bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" newline bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" newline bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" newline bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,Injected context queue overflow interrupt enable" "0: Injected Context Queue Overflow interrupt disabled,1: Injected Context Queue Overflow interrupt.." bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" newline bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" newline bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." newline bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.." line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Normal mode,1: Calibration mode" bitfld.long 0x8 30. "ADCALDIF,Differential mode for calibration" "0: Single-ended input calibration mode.,1: Differential input calibration mode." newline bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in Deep-power down,1: ADC in Deep-power-down (default reset state)" bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." newline bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." newline bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." newline bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." line.long 0xC "ADC_CFGR1,ADC configuration register" bitfld.long 0xC 31. "JQDIS,Injected queue disable" "0: Injected queue enabled,1: Injected queue disabled" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" newline bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" newline bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" newline bitfld.long 0xC 21. "JQM,JSQR queue mode" "0: JSQR mode 0: The Queue is never empty and..,1: JSQR mode 1: The Queue can be empty and when.." bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" newline bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" newline bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" bitfld.long 0xC 13. "CONT,Single / Continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" newline bitfld.long 0xC 12. "OVRMOD,Overrun mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group" bitfld.long 0xC 2.--3. "RES,Data resolution" "0: 12-bit,1: 10-bit,2: 8-bit,3: 6-bit" newline bitfld.long 0xC 0.--1. "DMNGT,Data management configuration" "0: Regular conversion data stored in DR only,1: DMA One-shot mode selected,2: MDF mode detected,3: DMA Circular mode selected" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" newline bitfld.long 0x10 15. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled" bitfld.long 0x10 14. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.." newline bitfld.long 0x10 13. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.." bitfld.long 0x10 10. "ROVSM,Regular oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." newline bitfld.long 0x10 9. "TROVS,Triggered regular oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling shift" newline bitfld.long 0x10 1. "JOVSE,Injected oversampling enable" "0: Injected oversampling disabled,1: Injected oversampling enabled" bitfld.long 0x10 0. "ROVSE,Regular oversampling enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" hexmask.long.tbyte 0x1C 0.--19. 1. "PCSEL,Channel i (V less than sub>INP less than /sub>[i]) preselection" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence" hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence" hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence" newline hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence" hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence" hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence" hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence" hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence" hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular data register" hexmask.long 0x0 0.--31. 1. "RDATA,Regular data converted" group.long 0x4C++0x27 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence" newline bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External trigger selection for injected group" newline bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions" line.long 0x4 "ADC_OFCFGR1,ADC offset 1 configuration register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x4 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x4 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x4 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x8 "ADC_OFCFGR2,ADC offset 2 configuration register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x8 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x8 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x8 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0xC "ADC_OFCFGR3,ADC offset 3 configuration register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0xC 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0xC 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0xC 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x10 "ADC_OFCFGR4,ADC offset 4 configuration register" hexmask.long.byte 0x10 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x10 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x10 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x10 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x14 "ADC_OFR1,ADC offset 1 register" hexmask.long.tbyte 0x14 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x18 "ADC_OFR2,ADC offset 2 register" hexmask.long.tbyte 0x18 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x1C "ADC_OFR3,ADC offset 3 register" hexmask.long.tbyte 0x1C 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x20 "ADC_OFR4,ADC offset 4 register" hexmask.long.tbyte 0x20 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x24 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x24 31. "GCOMP,Gain compensation mode" "0: Regular ADC operation mode,1: Gain compensation enabled and applied on all.." hexmask.long.word 0x24 0.--13. 1. "GCOMPCOEFF,Gain compensation coefficient" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected channel 1 data register" hexmask.long 0x0 0.--31. 1. "JDATA,Injected data" line.long 0x4 "ADC_JDR2,ADC injected channel 2 data register" hexmask.long 0x4 0.--31. 1. "JDATA,Injected data" line.long 0x8 "ADC_JDR3,ADC injected channel 3 data register" hexmask.long 0x8 0.--31. 1. "JDATA,Injected data" line.long 0xC "ADC_JDR4,ADC injected channel 4 data register" hexmask.long 0xC 0.--31. 1. "JDATA,Injected data" group.long 0xA0++0x27 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration Register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,Analog watchdog 2 channel selection" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration Register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,Analog watchdog 3 channel selection" line.long 0x8 "ADC_AWD1LTR,ADC analog watchdog 1 lower threshold register" hexmask.long.tbyte 0x8 0.--22. 1. "LTR,Analog watchdog 1 lower threshold" line.long 0xC "ADC_AWD1HTR,ADC analog watchdog 1 higher threshold register" bitfld.long 0xC 29.--31. "AWDFILT,Analog watchdog filtering parameter" "0: No filtering one detection generates an AWDx..,1: two consecutive detections generate an AWDx flag..,?,?,?,?,?,7: Eight consecutive detections generate an AWDx.." hexmask.long.tbyte 0xC 0.--22. 1. "HTR,Analog watchdog 1 higher threshold" line.long 0x10 "ADC_AWD2LTR,ADC analog watchdog 2 lower threshold register" hexmask.long.tbyte 0x10 0.--22. 1. "LTR,Analog watchdog 2 lower threshold" line.long 0x14 "ADC_AWD2HTR,ADC analog watchdog 2 higher threshold register" hexmask.long.tbyte 0x14 0.--22. 1. "HTR,Analog watchdog 2 higher threshold" line.long 0x18 "ADC_AWD3LTR,ADC analog watchdog 3 lower threshold register" hexmask.long.tbyte 0x18 0.--22. 1. "LTR,Analog watchdog 3 lower threshold" line.long 0x1C "ADC_AWD3HTR,ADC analog watchdog 3 higher threshold register" hexmask.long.tbyte 0x1C 0.--22. 1. "HTR,Analog watchdog 3 higher threshold" line.long 0x20 "ADC_DIFSEL,ADC Differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,Differential mode for channels 19 to 0." line.long 0x24 "ADC_CALFACT,ADC calibration factors" bitfld.long 0x24 31. "CALADDOS,Calibration additional offset" "0: Calibration additional positive offset disabled,1: Calibration additional positive offset enabled" hexmask.long.word 0x24 16.--24. 1. "CALFACT_D,Calibration factors in Differential mode" newline hexmask.long.word 0x24 0.--8. 1. "CALFACT_S,Calibration factors In Single-ended mode" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 2. "VDDCOREEN,VDDCORE enable" "0: V less than sub>DDCORE less than /sub> channel..,1: V less than sub>DDCORE less than /sub> channel.." bitfld.long 0x0 1. "SELBG,Bandgap selection" "0: ADC internal bandgap disabled,1: ADC internal bandgap enabled" newline bitfld.long 0x0 0. "SELREF,Internal reference voltage selection" "0: ADC internal reference voltage buffer disabled,1: ADC internal reference voltage buffer enabled" tree.end tree "ADC1_S" base ad:0x50022000 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 10. "JQOVF,Injected context queue overflow" "0: No injected context queue overflow occurred (or..,1: Injected context queue overflow has occurred" bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" newline bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" newline bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" newline bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" newline bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" newline bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,Injected context queue overflow interrupt enable" "0: Injected Context Queue Overflow interrupt disabled,1: Injected Context Queue Overflow interrupt.." bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" newline bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" newline bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." newline bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.." line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Normal mode,1: Calibration mode" bitfld.long 0x8 30. "ADCALDIF,Differential mode for calibration" "0: Single-ended input calibration mode.,1: Differential input calibration mode." newline bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in Deep-power down,1: ADC in Deep-power-down (default reset state)" bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." newline bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." newline bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." newline bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." line.long 0xC "ADC_CFGR1,ADC configuration register" bitfld.long 0xC 31. "JQDIS,Injected queue disable" "0: Injected queue enabled,1: Injected queue disabled" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" newline bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" newline bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" newline bitfld.long 0xC 21. "JQM,JSQR queue mode" "0: JSQR mode 0: The Queue is never empty and..,1: JSQR mode 1: The Queue can be empty and when.." bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" newline bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" newline bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" bitfld.long 0xC 13. "CONT,Single / Continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" newline bitfld.long 0xC 12. "OVRMOD,Overrun mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group" bitfld.long 0xC 2.--3. "RES,Data resolution" "0: 12-bit,1: 10-bit,2: 8-bit,3: 6-bit" newline bitfld.long 0xC 0.--1. "DMNGT,Data management configuration" "0: Regular conversion data stored in DR only,1: DMA One-shot mode selected,2: MDF mode detected,3: DMA Circular mode selected" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" newline bitfld.long 0x10 15. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled" bitfld.long 0x10 14. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.." newline bitfld.long 0x10 13. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.." bitfld.long 0x10 10. "ROVSM,Regular oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." newline bitfld.long 0x10 9. "TROVS,Triggered regular oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling shift" newline bitfld.long 0x10 1. "JOVSE,Injected oversampling enable" "0: Injected oversampling disabled,1: Injected oversampling enabled" bitfld.long 0x10 0. "ROVSE,Regular oversampling enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" hexmask.long.tbyte 0x1C 0.--19. 1. "PCSEL,Channel i (V less than sub>INP less than /sub>[i]) preselection" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence" hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence" hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence" newline hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence" hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence" hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence" hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence" hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence" hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular data register" hexmask.long 0x0 0.--31. 1. "RDATA,Regular data converted" group.long 0x4C++0x27 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence" newline bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External trigger selection for injected group" newline bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions" line.long 0x4 "ADC_OFCFGR1,ADC offset 1 configuration register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x4 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x4 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x4 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x8 "ADC_OFCFGR2,ADC offset 2 configuration register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x8 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x8 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x8 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0xC "ADC_OFCFGR3,ADC offset 3 configuration register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0xC 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0xC 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0xC 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x10 "ADC_OFCFGR4,ADC offset 4 configuration register" hexmask.long.byte 0x10 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x10 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x10 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x10 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x14 "ADC_OFR1,ADC offset 1 register" hexmask.long.tbyte 0x14 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x18 "ADC_OFR2,ADC offset 2 register" hexmask.long.tbyte 0x18 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x1C "ADC_OFR3,ADC offset 3 register" hexmask.long.tbyte 0x1C 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x20 "ADC_OFR4,ADC offset 4 register" hexmask.long.tbyte 0x20 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x24 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x24 31. "GCOMP,Gain compensation mode" "0: Regular ADC operation mode,1: Gain compensation enabled and applied on all.." hexmask.long.word 0x24 0.--13. 1. "GCOMPCOEFF,Gain compensation coefficient" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected channel 1 data register" hexmask.long 0x0 0.--31. 1. "JDATA,Injected data" line.long 0x4 "ADC_JDR2,ADC injected channel 2 data register" hexmask.long 0x4 0.--31. 1. "JDATA,Injected data" line.long 0x8 "ADC_JDR3,ADC injected channel 3 data register" hexmask.long 0x8 0.--31. 1. "JDATA,Injected data" line.long 0xC "ADC_JDR4,ADC injected channel 4 data register" hexmask.long 0xC 0.--31. 1. "JDATA,Injected data" group.long 0xA0++0x27 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration Register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,Analog watchdog 2 channel selection" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration Register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,Analog watchdog 3 channel selection" line.long 0x8 "ADC_AWD1LTR,ADC analog watchdog 1 lower threshold register" hexmask.long.tbyte 0x8 0.--22. 1. "LTR,Analog watchdog 1 lower threshold" line.long 0xC "ADC_AWD1HTR,ADC analog watchdog 1 higher threshold register" bitfld.long 0xC 29.--31. "AWDFILT,Analog watchdog filtering parameter" "0: No filtering one detection generates an AWDx..,1: two consecutive detections generate an AWDx flag..,?,?,?,?,?,7: Eight consecutive detections generate an AWDx.." hexmask.long.tbyte 0xC 0.--22. 1. "HTR,Analog watchdog 1 higher threshold" line.long 0x10 "ADC_AWD2LTR,ADC analog watchdog 2 lower threshold register" hexmask.long.tbyte 0x10 0.--22. 1. "LTR,Analog watchdog 2 lower threshold" line.long 0x14 "ADC_AWD2HTR,ADC analog watchdog 2 higher threshold register" hexmask.long.tbyte 0x14 0.--22. 1. "HTR,Analog watchdog 2 higher threshold" line.long 0x18 "ADC_AWD3LTR,ADC analog watchdog 3 lower threshold register" hexmask.long.tbyte 0x18 0.--22. 1. "LTR,Analog watchdog 3 lower threshold" line.long 0x1C "ADC_AWD3HTR,ADC analog watchdog 3 higher threshold register" hexmask.long.tbyte 0x1C 0.--22. 1. "HTR,Analog watchdog 3 higher threshold" line.long 0x20 "ADC_DIFSEL,ADC Differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,Differential mode for channels 19 to 0." line.long 0x24 "ADC_CALFACT,ADC calibration factors" bitfld.long 0x24 31. "CALADDOS,Calibration additional offset" "0: Calibration additional positive offset disabled,1: Calibration additional positive offset enabled" hexmask.long.word 0x24 16.--24. 1. "CALFACT_D,Calibration factors in Differential mode" newline hexmask.long.word 0x24 0.--8. 1. "CALFACT_S,Calibration factors In Single-ended mode" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 2. "VDDCOREEN,VDDCORE enable" "0: V less than sub>DDCORE less than /sub> channel..,1: V less than sub>DDCORE less than /sub> channel.." bitfld.long 0x0 1. "SELBG,Bandgap selection" "0: ADC internal bandgap disabled,1: ADC internal bandgap enabled" newline bitfld.long 0x0 0. "SELREF,Internal reference voltage selection" "0: ADC internal reference voltage buffer disabled,1: ADC internal reference voltage buffer enabled" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 10. "JQOVF,Injected context queue overflow" "0: No injected context queue overflow occurred (or..,1: Injected context queue overflow has occurred" bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" newline bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" newline bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" newline bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" newline bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" newline bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,Injected context queue overflow interrupt enable" "0: Injected Context Queue Overflow interrupt disabled,1: Injected Context Queue Overflow interrupt.." bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" newline bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" newline bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." newline bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.." line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Normal mode,1: Calibration mode" bitfld.long 0x8 30. "ADCALDIF,Differential mode for calibration" "0: Single-ended input calibration mode.,1: Differential input calibration mode." newline bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in Deep-power down,1: ADC in Deep-power-down (default reset state)" bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." newline bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." newline bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." newline bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." line.long 0xC "ADC_CFGR1,ADC configuration register" bitfld.long 0xC 31. "JQDIS,Injected queue disable" "0: Injected queue enabled,1: Injected queue disabled" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" newline bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" newline bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" newline bitfld.long 0xC 21. "JQM,JSQR queue mode" "0: JSQR mode 0: The Queue is never empty and..,1: JSQR mode 1: The Queue can be empty and when.." bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" newline bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" newline bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" bitfld.long 0xC 13. "CONT,Single / Continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" newline bitfld.long 0xC 12. "OVRMOD,Overrun mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group" bitfld.long 0xC 2.--3. "RES,Data resolution" "0: 12-bit,1: 10-bit,2: 8-bit,3: 6-bit" newline bitfld.long 0xC 0.--1. "DMNGT,Data management configuration" "0: Regular conversion data stored in DR only,1: DMA One-shot mode selected,2: MDF mode detected,3: DMA Circular mode selected" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" newline bitfld.long 0x10 15. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled" bitfld.long 0x10 14. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.." newline bitfld.long 0x10 13. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.." bitfld.long 0x10 10. "ROVSM,Regular oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." newline bitfld.long 0x10 9. "TROVS,Triggered regular oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling shift" newline bitfld.long 0x10 1. "JOVSE,Injected oversampling enable" "0: Injected oversampling disabled,1: Injected oversampling enabled" bitfld.long 0x10 0. "ROVSE,Regular oversampling enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" hexmask.long.tbyte 0x1C 0.--19. 1. "PCSEL,Channel i (V less than sub>INP less than /sub>[i]) preselection" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence" hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence" hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence" newline hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence" hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence" hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence" hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence" hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence" hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular data register" hexmask.long 0x0 0.--31. 1. "RDATA,Regular data converted" group.long 0x4C++0x27 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence" newline bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External trigger selection for injected group" newline bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions" line.long 0x4 "ADC_OFCFGR1,ADC offset 1 configuration register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x4 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x4 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x4 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x8 "ADC_OFCFGR2,ADC offset 2 configuration register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x8 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x8 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x8 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0xC "ADC_OFCFGR3,ADC offset 3 configuration register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0xC 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0xC 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0xC 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x10 "ADC_OFCFGR4,ADC offset 4 configuration register" hexmask.long.byte 0x10 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x10 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x10 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x10 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x14 "ADC_OFR1,ADC offset 1 register" hexmask.long.tbyte 0x14 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x18 "ADC_OFR2,ADC offset 2 register" hexmask.long.tbyte 0x18 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x1C "ADC_OFR3,ADC offset 3 register" hexmask.long.tbyte 0x1C 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x20 "ADC_OFR4,ADC offset 4 register" hexmask.long.tbyte 0x20 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x24 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x24 31. "GCOMP,Gain compensation mode" "0: Regular ADC operation mode,1: Gain compensation enabled and applied on all.." hexmask.long.word 0x24 0.--13. 1. "GCOMPCOEFF,Gain compensation coefficient" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected channel 1 data register" hexmask.long 0x0 0.--31. 1. "JDATA,Injected data" line.long 0x4 "ADC_JDR2,ADC injected channel 2 data register" hexmask.long 0x4 0.--31. 1. "JDATA,Injected data" line.long 0x8 "ADC_JDR3,ADC injected channel 3 data register" hexmask.long 0x8 0.--31. 1. "JDATA,Injected data" line.long 0xC "ADC_JDR4,ADC injected channel 4 data register" hexmask.long 0xC 0.--31. 1. "JDATA,Injected data" group.long 0xA0++0x27 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration Register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,Analog watchdog 2 channel selection" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration Register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,Analog watchdog 3 channel selection" line.long 0x8 "ADC_AWD1LTR,ADC analog watchdog 1 lower threshold register" hexmask.long.tbyte 0x8 0.--22. 1. "LTR,Analog watchdog 1 lower threshold" line.long 0xC "ADC_AWD1HTR,ADC analog watchdog 1 higher threshold register" bitfld.long 0xC 29.--31. "AWDFILT,Analog watchdog filtering parameter" "0: No filtering one detection generates an AWDx..,1: two consecutive detections generate an AWDx flag..,?,?,?,?,?,7: Eight consecutive detections generate an AWDx.." hexmask.long.tbyte 0xC 0.--22. 1. "HTR,Analog watchdog 1 higher threshold" line.long 0x10 "ADC_AWD2LTR,ADC analog watchdog 2 lower threshold register" hexmask.long.tbyte 0x10 0.--22. 1. "LTR,Analog watchdog 2 lower threshold" line.long 0x14 "ADC_AWD2HTR,ADC analog watchdog 2 higher threshold register" hexmask.long.tbyte 0x14 0.--22. 1. "HTR,Analog watchdog 2 higher threshold" line.long 0x18 "ADC_AWD3LTR,ADC analog watchdog 3 lower threshold register" hexmask.long.tbyte 0x18 0.--22. 1. "LTR,Analog watchdog 3 lower threshold" line.long 0x1C "ADC_AWD3HTR,ADC analog watchdog 3 higher threshold register" hexmask.long.tbyte 0x1C 0.--22. 1. "HTR,Analog watchdog 3 higher threshold" line.long 0x20 "ADC_DIFSEL,ADC Differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,Differential mode for channels 19 to 0." line.long 0x24 "ADC_CALFACT,ADC calibration factors" bitfld.long 0x24 31. "CALADDOS,Calibration additional offset" "0: Calibration additional positive offset disabled,1: Calibration additional positive offset enabled" hexmask.long.word 0x24 16.--24. 1. "CALFACT_D,Calibration factors in Differential mode" newline hexmask.long.word 0x24 0.--8. 1. "CALFACT_S,Calibration factors In Single-ended mode" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 2. "VDDCOREEN,VDDCORE enable" "0: V less than sub>DDCORE less than /sub> channel..,1: V less than sub>DDCORE less than /sub> channel.." bitfld.long 0x0 1. "SELBG,Bandgap selection" "0: ADC internal bandgap disabled,1: ADC internal bandgap enabled" newline bitfld.long 0x0 0. "SELREF,Internal reference voltage selection" "0: ADC internal reference voltage buffer disabled,1: ADC internal reference voltage buffer enabled" tree.end tree "ADC2_S" base ad:0x50022100 group.long 0x0++0x1F line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 10. "JQOVF,Injected context queue overflow" "0: No injected context queue overflow occurred (or..,1: Injected context queue overflow has occurred" bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" newline bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" newline bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" newline bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" newline bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" newline bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,Injected context queue overflow interrupt enable" "0: Injected Context Queue Overflow interrupt disabled,1: Injected Context Queue Overflow interrupt.." bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" newline bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" newline bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." newline bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.." line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Normal mode,1: Calibration mode" bitfld.long 0x8 30. "ADCALDIF,Differential mode for calibration" "0: Single-ended input calibration mode.,1: Differential input calibration mode." newline bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in Deep-power down,1: ADC in Deep-power-down (default reset state)" bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." newline bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." newline bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." newline bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." line.long 0xC "ADC_CFGR1,ADC configuration register" bitfld.long 0xC 31. "JQDIS,Injected queue disable" "0: Injected queue enabled,1: Injected queue disabled" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" newline bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" newline bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" newline bitfld.long 0xC 21. "JQM,JSQR queue mode" "0: JSQR mode 0: The Queue is never empty and..,1: JSQR mode 1: The Queue can be empty and when.." bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" newline bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" newline bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" bitfld.long 0xC 13. "CONT,Single / Continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" newline bitfld.long 0xC 12. "OVRMOD,Overrun mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group" bitfld.long 0xC 2.--3. "RES,Data resolution" "0: 12-bit,1: 10-bit,2: 8-bit,3: 6-bit" newline bitfld.long 0xC 0.--1. "DMNGT,Data management configuration" "0: Regular conversion data stored in DR only,1: DMA One-shot mode selected,2: MDF mode detected,3: DMA Circular mode selected" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" newline bitfld.long 0x10 15. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled" bitfld.long 0x10 14. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.." newline bitfld.long 0x10 13. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.." bitfld.long 0x10 10. "ROVSM,Regular oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." newline bitfld.long 0x10 9. "TROVS,Triggered regular oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling shift" newline bitfld.long 0x10 1. "JOVSE,Injected oversampling enable" "0: Injected oversampling disabled,1: Injected oversampling enabled" bitfld.long 0x10 0. "ROVSE,Regular oversampling enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" newline bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 24.5 ADC clock cycles,5: 47.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 1501.5 ADC clock cycles" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" hexmask.long.tbyte 0x1C 0.--19. 1. "PCSEL,Channel i (V less than sub>INP less than /sub>[i]) preselection" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence" hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence" hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence" newline hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence" hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence" hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence" hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence" hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence" hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular data register" hexmask.long 0x0 0.--31. 1. "RDATA,Regular data converted" group.long 0x4C++0x27 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence" newline bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External trigger selection for injected group" newline bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions" line.long 0x4 "ADC_OFCFGR1,ADC offset 1 configuration register" hexmask.long.byte 0x4 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x4 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x4 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x4 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x8 "ADC_OFCFGR2,ADC offset 2 configuration register" hexmask.long.byte 0x8 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x8 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x8 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x8 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0xC "ADC_OFCFGR3,ADC offset 3 configuration register" hexmask.long.byte 0xC 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0xC 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0xC 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0xC 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x10 "ADC_OFCFGR4,ADC offset 4 configuration register" hexmask.long.byte 0x10 27.--31. 1. "OFFSET_CH,Channel selection for the data offset y" bitfld.long 0x10 26. "SSAT,Signed saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." newline bitfld.long 0x10 25. "USAT,Unsigned saturation enable" "0: Offset is subtracted maintaining the data..,1: Offset is subtracted and result is saturated to.." bitfld.long 0x10 24. "POSOFF,Positive offset enable" "0: Negative offset,1: Positive offset" line.long 0x14 "ADC_OFR1,ADC offset 1 register" hexmask.long.tbyte 0x14 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x18 "ADC_OFR2,ADC offset 2 register" hexmask.long.tbyte 0x18 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x1C "ADC_OFR3,ADC offset 3 register" hexmask.long.tbyte 0x1C 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x20 "ADC_OFR4,ADC offset 4 register" hexmask.long.tbyte 0x20 0.--21. 1. "OFFSET,Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" line.long 0x24 "ADC_GCOMP,ADC gain compensation register" bitfld.long 0x24 31. "GCOMP,Gain compensation mode" "0: Regular ADC operation mode,1: Gain compensation enabled and applied on all.." hexmask.long.word 0x24 0.--13. 1. "GCOMPCOEFF,Gain compensation coefficient" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected channel 1 data register" hexmask.long 0x0 0.--31. 1. "JDATA,Injected data" line.long 0x4 "ADC_JDR2,ADC injected channel 2 data register" hexmask.long 0x4 0.--31. 1. "JDATA,Injected data" line.long 0x8 "ADC_JDR3,ADC injected channel 3 data register" hexmask.long 0x8 0.--31. 1. "JDATA,Injected data" line.long 0xC "ADC_JDR4,ADC injected channel 4 data register" hexmask.long 0xC 0.--31. 1. "JDATA,Injected data" group.long 0xA0++0x27 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration Register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,Analog watchdog 2 channel selection" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration Register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,Analog watchdog 3 channel selection" line.long 0x8 "ADC_AWD1LTR,ADC analog watchdog 1 lower threshold register" hexmask.long.tbyte 0x8 0.--22. 1. "LTR,Analog watchdog 1 lower threshold" line.long 0xC "ADC_AWD1HTR,ADC analog watchdog 1 higher threshold register" bitfld.long 0xC 29.--31. "AWDFILT,Analog watchdog filtering parameter" "0: No filtering one detection generates an AWDx..,1: two consecutive detections generate an AWDx flag..,?,?,?,?,?,7: Eight consecutive detections generate an AWDx.." hexmask.long.tbyte 0xC 0.--22. 1. "HTR,Analog watchdog 1 higher threshold" line.long 0x10 "ADC_AWD2LTR,ADC analog watchdog 2 lower threshold register" hexmask.long.tbyte 0x10 0.--22. 1. "LTR,Analog watchdog 2 lower threshold" line.long 0x14 "ADC_AWD2HTR,ADC analog watchdog 2 higher threshold register" hexmask.long.tbyte 0x14 0.--22. 1. "HTR,Analog watchdog 2 higher threshold" line.long 0x18 "ADC_AWD3LTR,ADC analog watchdog 3 lower threshold register" hexmask.long.tbyte 0x18 0.--22. 1. "LTR,Analog watchdog 3 lower threshold" line.long 0x1C "ADC_AWD3HTR,ADC analog watchdog 3 higher threshold register" hexmask.long.tbyte 0x1C 0.--22. 1. "HTR,Analog watchdog 3 higher threshold" line.long 0x20 "ADC_DIFSEL,ADC Differential mode selection register" hexmask.long.tbyte 0x20 0.--19. 1. "DIFSEL,Differential mode for channels 19 to 0." line.long 0x24 "ADC_CALFACT,ADC calibration factors" bitfld.long 0x24 31. "CALADDOS,Calibration additional offset" "0: Calibration additional positive offset disabled,1: Calibration additional positive offset enabled" hexmask.long.word 0x24 16.--24. 1. "CALFACT_D,Calibration factors in Differential mode" newline hexmask.long.word 0x24 0.--8. 1. "CALFACT_S,Calibration factors In Single-ended mode" group.long 0xD0++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 2. "VDDCOREEN,VDDCORE enable" "0: V less than sub>DDCORE less than /sub> channel..,1: V less than sub>DDCORE less than /sub> channel.." bitfld.long 0x0 1. "SELBG,Bandgap selection" "0: ADC internal bandgap disabled,1: ADC internal bandgap enabled" newline bitfld.long 0x0 0. "SELREF,Internal reference voltage selection" "0: ADC internal reference voltage buffer disabled,1: ADC internal reference voltage buffer enabled" tree.end base ad:0x0 tree "ADC12" tree "ADC12 (ADC common registers)" base ad:0x40022300 rgroup.long 0x300++0x3 line.long 0x0 "ADC12_CSR,ADC12 common status register" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" newline bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" newline bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register." "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC12_CCR,ADC12 common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: V less than sub>BAT less than /sub> channel..,1: V less than sub>BAT less than /sub> channel.." bitfld.long 0x0 22. "VREFEN,V less than sub>REFINT less than /sub> enable" "0: V less than sub>REFINT less than /sub> channel..,1: V less than sub>REFINT less than /sub> channel.." newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC mode data format" "0: Dual ADC mode without data packing (ADCx_CDR and..,?,2: Data formatting mode for any data width..,3: Data formatting mode for data width lower that 8.." hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between two sampling phases" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0x30C++0x7 line.long 0x0 "ADC12_CDR,ADC12 common regular data register for Dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC12 common regular data register for Dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs." tree.end tree "ADC12_S (ADC common registers)" base ad:0x50022300 rgroup.long 0x300++0x3 line.long 0x0 "ADC12_CSR,ADC12 common status register" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1" newline bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1" newline bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1" newline bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register." "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC12_CCR,ADC12 common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: V less than sub>BAT less than /sub> channel..,1: V less than sub>BAT less than /sub> channel.." bitfld.long 0x0 22. "VREFEN,V less than sub>REFINT less than /sub> enable" "0: V less than sub>REFINT less than /sub> channel..,1: V less than sub>REFINT less than /sub> channel.." newline bitfld.long 0x0 14.--15. "DAMDF,Dual ADC mode data format" "0: Dual ADC mode without data packing (ADCx_CDR and..,?,2: Data formatting mode for any data width..,3: Data formatting mode for data width lower that 8.." hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between two sampling phases" newline hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0x30C++0x7 line.long 0x0 "ADC12_CDR,ADC12 common regular data register for Dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC." line.long 0x4 "ADC12_CDR2,ADC12 common regular data register for Dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave alternated ADCs." tree.end tree.end tree.end tree "ADF (Audio Digital Filter)" base ad:0x0 tree "ADF" base ad:0x42026000 group.long 0x0++0x7 line.long 0x0 "ADF_GCR,ADF global control register" bitfld.long 0x0 0. "TRGO,Trigger output control" "0: Write 0 has no effect. Read 0 means that the..,1: Write 1 generates a positive pulse on the.." line.long 0x4 "ADF_CKGCR,ADF clock generator control register" rbitfld.long 0x4 31. "CKGACTIVE,Clock generator active flag" "0: The clock generator is not active and can be..,1: The clock generator is active and protected.." hexmask.long.byte 0x4 24.--30. 1. "PROCDIV,Divider to control the serial interface clock" newline hexmask.long.byte 0x4 16.--19. 1. "CCKDIV,Divider to control the ADF_CCK clock" hexmask.long.byte 0x4 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" newline bitfld.long 0x4 8. "TRGSENS,CKGEN trigger sensitivity selection" "0: A rising edge event triggers the activation of..,1: A falling edge even triggers the activation of.." bitfld.long 0x4 6. "CCK1DIR,ADF_CCK1 direction" "0: The ADF_CCK1 pin direction is in input.,1: The ADF_CCK1 pin direction is in output." newline bitfld.long 0x4 5. "CCK0DIR,ADF_CCK0 direction" "0: The ADF_CCK0 pin direction is in input.,1: The ADF_CCK0 pin direction is in output." bitfld.long 0x4 4. "CKGMOD,Clock generator mode" "0: The kernel clock is provided to the dividers as..,1: The kernel clock is provided to the dividers.." newline bitfld.long 0x4 2. "CCK1EN,ADF_CCK1 clock enable" "0: Bitstream clock not generated,1: Bitstream clock generated on the ADF_CCK1 pin." bitfld.long 0x4 1. "CCK0EN,ADF_CCK0 clock enable" "0: Bitstream clock not generated,1: Bitstream clock generated on the ADF_CCK0 pin" newline bitfld.long 0x4 0. "CKGDEN,CKGEN dividers enable" "0: CKGEN dividers disabled,1: CKGEN dividers enabled" group.long 0x80++0x13 line.long 0x0 "ADF_SITF0CR,ADF serial interface control register 0" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is ADF_CCK0.,1: Serial clock source is ADF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "ADF_BSMX0CR,ADF bitstream matrix control register 0" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream selection" line.long 0x8 "ADF_DFLT0CR,ADF digital filter control register 0" rbitfld.long 0x8 31. "DFLTACTIVE,DFLT0 active flag" "0: DFLT0 not active (can be re-enabled again via..,1: DFLT0 active" rbitfld.long 0x8 30. "DFLTRUN,DFLT0 run status flag" "0: DFLT0 not running and ready to accept a new..,1: DFLT0running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,DFLT0 trigger signal selection" newline bitfld.long 0x8 8. "TRGSENS,DFLT0 trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." bitfld.long 0x8 4.--6. "ACQMOD,DFLT0 trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,?,?,?" newline bitfld.long 0x8 2. "FTH,RXFIFO threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." newline bitfld.long 0x8 0. "DFLTEN,DFLT0 enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "ADF_DFLT0CICR,ADF digital filer configuration register 0" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC order" "?,?,?,?,4: MCIC configured in single Sinc less than sup>4..,5: MCIC configured in single Sinc less than sup>5..,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "ADF_DFLT0RSFR,ADF reshape filter configuration register 0" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x FPCM,1: Cut-off frequency = 0.00125 x FPCM,2: Cut-off frequency = 0.00250 x FPCM,3: Cut-off frequency = 0.00950 x FPCM" bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" group.long 0xA4++0x3 line.long 0x0 "ADF_DLY0CR,ADF delay control register 0" rbitfld.long 0x0 31. "SKPBF,Skip busy flag" "0: ADF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under precessing" hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" group.long 0xAC++0x7 line.long 0x0 "ADF_DFLT0IER,ADF DFLT0 interrupt enable register" bitfld.long 0x0 13. "SDLVLIE,SAD sound-level value ready enable" "0: Sound-level-ready interrupt disabled,1: Sound-level-ready interrupt enabled" bitfld.long 0x0 12. "SDDETIE,Sound activity detection interrupt enable" "0: Sound-trigger interrupt disabled,1: Sound-trigger interrupt enabled" newline bitfld.long 0x0 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x4 "ADF_DFLT0ISR,ADF DFLT0 interrupt status register 0" bitfld.long 0x4 13. "SDLVLF,Sound level value ready flag" "0: Read 0 means that new sound level value is not..,1: Read 1 means that new sound level value is.." bitfld.long 0x4 12. "SDDETF,Sound activity detection flag" "0: Read 0 means that no sound activity is detected.,1: Read 1 means that sound activity is detected." newline bitfld.long 0x4 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x4 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x4 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." rbitfld.long 0x4 3. "RXNEF,RXFIFO not empty flag" "0: RXFIFO empty,1: RXFIFO not empty" newline bitfld.long 0x4 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x4 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" group.long 0xB8++0x7 line.long 0x0 "ADF_SADCR,ADF SAD control register" rbitfld.long 0x0 31. "SADACTIVE,SAD Active flag" "0: SAD not active and can be configured if needed,1: SAD active and protected fields cannot be.." bitfld.long 0x0 12.--13. "SADMOD,SAD working mode" "0: Threshold value computed according to the..,1: Threshold value equal to ANMIN[12:0] multiplied..,?,?" newline bitfld.long 0x0 8.--10. "FRSIZE,Frame size" "0: 8 PCM samples used to compute the short-term..,1: 16 PCM samples used to compute the short-term..,2: 32 PCM samples used to compute the short-term..,3: 64 PCM samples used to compute the short-term..,4: 128 PCM samples used to compute the short-term..,5: 256 PCM samples used to compute the short-term..,?,?" bitfld.long 0x0 7. "HYSTEN,Hysteresis enable" "0: Hysteresis function disabled. THR less than..,1: Hysteresis function enabled. THR less than sub>H.." newline rbitfld.long 0x0 4.--5. "SADST,SAD state" "0: SAD in LEARN state,1: SAD in MONITOR state,?,3: SAD in DETECT state" bitfld.long 0x0 3. "DETCFG,Sound trigger event configuration" "0: sddet_evt generated when SAD enters the MONITOR..,1: sddet_evt generated when SAD enters or exits the.." newline bitfld.long 0x0 1.--2. "DATCAP,Data capture mode" "0: Samples from DFLT0 not transfered into the memory,1: Samples from DFLT0 transfered into the memory..,?,?" bitfld.long 0x0 0. "SADEN,Sound activity detector enable" "0: SAD disabled and SAD state reset,1: SAD enabled" line.long 0x4 "ADF_SADCFGR,ADF SAD configuration register" hexmask.long.word 0x4 16.--28. 1. "ANMIN,Minimum noise level" bitfld.long 0x4 12.--14. "HGOVR,Hangover time window" "0: SAD back to MONITOR state if sound is below..,1: SAD back to MONITOR state if sound is below..,2: SAD back to MONITOR state if sound is below..,3: SAD back to MONITOR state if sound is below..,4: SAD back to MONITOR state if sound is below..,5: SAD back to MONITOR state if sound is below..,6: SAD back to MONITOR state if sound is below..,7: SAD back to MONITOR state if sound is below.." newline bitfld.long 0x4 8.--10. "LFRNB,Number of learning frames" "0: 2 frames used to compute the initial noise level,1: 4 frames used to compute the initial noise level,2: 8 frames used to compute the initial noise level,3: 16 frames used to compute the initial noise level,?,?,?,?" bitfld.long 0x4 4.--6. "ANSLP,Ambient noise slope control" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "SNTHR,Signal to noise threshold" rgroup.long 0xC0++0x7 line.long 0x0 "ADF_SADSDLVR,ADF SAD sound level register" hexmask.long.word 0x0 0.--14. 1. "SDLVL,Short term sound level" line.long 0x4 "ADF_SADANLVR,ADF SAD ambient noise level register" hexmask.long.word 0x4 0.--14. 1. "ANLVL,Ambient noise level estimation" rgroup.long 0xF0++0x3 line.long 0x0 "ADF_DFLT0DR,ADF digital filter data register 0" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by DFT0" tree.end tree "ADF_S" base ad:0x52026000 group.long 0x0++0x7 line.long 0x0 "ADF_GCR,ADF global control register" bitfld.long 0x0 0. "TRGO,Trigger output control" "0: Write 0 has no effect. Read 0 means that the..,1: Write 1 generates a positive pulse on the.." line.long 0x4 "ADF_CKGCR,ADF clock generator control register" rbitfld.long 0x4 31. "CKGACTIVE,Clock generator active flag" "0: The clock generator is not active and can be..,1: The clock generator is active and protected.." hexmask.long.byte 0x4 24.--30. 1. "PROCDIV,Divider to control the serial interface clock" newline hexmask.long.byte 0x4 16.--19. 1. "CCKDIV,Divider to control the ADF_CCK clock" hexmask.long.byte 0x4 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" newline bitfld.long 0x4 8. "TRGSENS,CKGEN trigger sensitivity selection" "0: A rising edge event triggers the activation of..,1: A falling edge even triggers the activation of.." bitfld.long 0x4 6. "CCK1DIR,ADF_CCK1 direction" "0: The ADF_CCK1 pin direction is in input.,1: The ADF_CCK1 pin direction is in output." newline bitfld.long 0x4 5. "CCK0DIR,ADF_CCK0 direction" "0: The ADF_CCK0 pin direction is in input.,1: The ADF_CCK0 pin direction is in output." bitfld.long 0x4 4. "CKGMOD,Clock generator mode" "0: The kernel clock is provided to the dividers as..,1: The kernel clock is provided to the dividers.." newline bitfld.long 0x4 2. "CCK1EN,ADF_CCK1 clock enable" "0: Bitstream clock not generated,1: Bitstream clock generated on the ADF_CCK1 pin." bitfld.long 0x4 1. "CCK0EN,ADF_CCK0 clock enable" "0: Bitstream clock not generated,1: Bitstream clock generated on the ADF_CCK0 pin" newline bitfld.long 0x4 0. "CKGDEN,CKGEN dividers enable" "0: CKGEN dividers disabled,1: CKGEN dividers enabled" group.long 0x80++0x13 line.long 0x0 "ADF_SITF0CR,ADF serial interface control register 0" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is ADF_CCK0.,1: Serial clock source is ADF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "ADF_BSMX0CR,ADF bitstream matrix control register 0" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream selection" line.long 0x8 "ADF_DFLT0CR,ADF digital filter control register 0" rbitfld.long 0x8 31. "DFLTACTIVE,DFLT0 active flag" "0: DFLT0 not active (can be re-enabled again via..,1: DFLT0 active" rbitfld.long 0x8 30. "DFLTRUN,DFLT0 run status flag" "0: DFLT0 not running and ready to accept a new..,1: DFLT0running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,DFLT0 trigger signal selection" newline bitfld.long 0x8 8. "TRGSENS,DFLT0 trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." bitfld.long 0x8 4.--6. "ACQMOD,DFLT0 trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,?,?,?" newline bitfld.long 0x8 2. "FTH,RXFIFO threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." newline bitfld.long 0x8 0. "DFLTEN,DFLT0 enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "ADF_DFLT0CICR,ADF digital filer configuration register 0" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC order" "?,?,?,?,4: MCIC configured in single Sinc less than sup>4..,5: MCIC configured in single Sinc less than sup>5..,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "ADF_DFLT0RSFR,ADF reshape filter configuration register 0" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x FPCM,1: Cut-off frequency = 0.00125 x FPCM,2: Cut-off frequency = 0.00250 x FPCM,3: Cut-off frequency = 0.00950 x FPCM" bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" group.long 0xA4++0x3 line.long 0x0 "ADF_DLY0CR,ADF delay control register 0" rbitfld.long 0x0 31. "SKPBF,Skip busy flag" "0: ADF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under precessing" hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" group.long 0xAC++0x7 line.long 0x0 "ADF_DFLT0IER,ADF DFLT0 interrupt enable register" bitfld.long 0x0 13. "SDLVLIE,SAD sound-level value ready enable" "0: Sound-level-ready interrupt disabled,1: Sound-level-ready interrupt enabled" bitfld.long 0x0 12. "SDDETIE,Sound activity detection interrupt enable" "0: Sound-trigger interrupt disabled,1: Sound-trigger interrupt enabled" newline bitfld.long 0x0 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x4 "ADF_DFLT0ISR,ADF DFLT0 interrupt status register 0" bitfld.long 0x4 13. "SDLVLF,Sound level value ready flag" "0: Read 0 means that new sound level value is not..,1: Read 1 means that new sound level value is.." bitfld.long 0x4 12. "SDDETF,Sound activity detection flag" "0: Read 0 means that no sound activity is detected.,1: Read 1 means that sound activity is detected." newline bitfld.long 0x4 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x4 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x4 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." rbitfld.long 0x4 3. "RXNEF,RXFIFO not empty flag" "0: RXFIFO empty,1: RXFIFO not empty" newline bitfld.long 0x4 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x4 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" group.long 0xB8++0x7 line.long 0x0 "ADF_SADCR,ADF SAD control register" rbitfld.long 0x0 31. "SADACTIVE,SAD Active flag" "0: SAD not active and can be configured if needed,1: SAD active and protected fields cannot be.." bitfld.long 0x0 12.--13. "SADMOD,SAD working mode" "0: Threshold value computed according to the..,1: Threshold value equal to ANMIN[12:0] multiplied..,?,?" newline bitfld.long 0x0 8.--10. "FRSIZE,Frame size" "0: 8 PCM samples used to compute the short-term..,1: 16 PCM samples used to compute the short-term..,2: 32 PCM samples used to compute the short-term..,3: 64 PCM samples used to compute the short-term..,4: 128 PCM samples used to compute the short-term..,5: 256 PCM samples used to compute the short-term..,?,?" bitfld.long 0x0 7. "HYSTEN,Hysteresis enable" "0: Hysteresis function disabled. THR less than..,1: Hysteresis function enabled. THR less than sub>H.." newline rbitfld.long 0x0 4.--5. "SADST,SAD state" "0: SAD in LEARN state,1: SAD in MONITOR state,?,3: SAD in DETECT state" bitfld.long 0x0 3. "DETCFG,Sound trigger event configuration" "0: sddet_evt generated when SAD enters the MONITOR..,1: sddet_evt generated when SAD enters or exits the.." newline bitfld.long 0x0 1.--2. "DATCAP,Data capture mode" "0: Samples from DFLT0 not transfered into the memory,1: Samples from DFLT0 transfered into the memory..,?,?" bitfld.long 0x0 0. "SADEN,Sound activity detector enable" "0: SAD disabled and SAD state reset,1: SAD enabled" line.long 0x4 "ADF_SADCFGR,ADF SAD configuration register" hexmask.long.word 0x4 16.--28. 1. "ANMIN,Minimum noise level" bitfld.long 0x4 12.--14. "HGOVR,Hangover time window" "0: SAD back to MONITOR state if sound is below..,1: SAD back to MONITOR state if sound is below..,2: SAD back to MONITOR state if sound is below..,3: SAD back to MONITOR state if sound is below..,4: SAD back to MONITOR state if sound is below..,5: SAD back to MONITOR state if sound is below..,6: SAD back to MONITOR state if sound is below..,7: SAD back to MONITOR state if sound is below.." newline bitfld.long 0x4 8.--10. "LFRNB,Number of learning frames" "0: 2 frames used to compute the initial noise level,1: 4 frames used to compute the initial noise level,2: 8 frames used to compute the initial noise level,3: 16 frames used to compute the initial noise level,?,?,?,?" bitfld.long 0x4 4.--6. "ANSLP,Ambient noise slope control" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "SNTHR,Signal to noise threshold" rgroup.long 0xC0++0x7 line.long 0x0 "ADF_SADSDLVR,ADF SAD sound level register" hexmask.long.word 0x0 0.--14. 1. "SDLVL,Short term sound level" line.long 0x4 "ADF_SADANLVR,ADF SAD ambient noise level register" hexmask.long.word 0x4 0.--14. 1. "ANLVL,Ambient noise level estimation" rgroup.long 0xF0++0x3 line.long 0x0 "ADF_DFLT0DR,ADF digital filter data register 0" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by DFT0" tree.end tree.end tree "BSEC (Boot and Security Control)" base ad:0x0 tree "BSEC" base ad:0x46009000 group.long 0x0++0x5DF line.long 0x0 "BSEC_FVR0,BSEC fuse word 0 value register" hexmask.long 0x0 0.--31. 1. "FV,fuse value" line.long 0x4 "BSEC_FVR1,BSEC fuse word 1 value register" hexmask.long 0x4 0.--31. 1. "FV,fuse value" line.long 0x8 "BSEC_FVR2,BSEC fuse word 2 value register" hexmask.long 0x8 0.--31. 1. "FV,fuse value" line.long 0xC "BSEC_FVR3,BSEC fuse word 3 value register" hexmask.long 0xC 0.--31. 1. "FV,fuse value" line.long 0x10 "BSEC_FVR4,BSEC fuse word 4 value register" hexmask.long 0x10 0.--31. 1. "FV,fuse value" line.long 0x14 "BSEC_FVR5,BSEC fuse word 5 value register" hexmask.long 0x14 0.--31. 1. "FV,fuse value" line.long 0x18 "BSEC_FVR6,BSEC fuse word 6 value register" hexmask.long 0x18 0.--31. 1. "FV,fuse value" line.long 0x1C "BSEC_FVR7,BSEC fuse word 7 value register" hexmask.long 0x1C 0.--31. 1. "FV,fuse value" line.long 0x20 "BSEC_FVR8,BSEC fuse word 8 value register" hexmask.long 0x20 0.--31. 1. "FV,fuse value" line.long 0x24 "BSEC_FVR9,BSEC fuse word 9 value register" hexmask.long 0x24 0.--31. 1. "FV,fuse value" line.long 0x28 "BSEC_FVR10,BSEC fuse word 10 value register" hexmask.long 0x28 0.--31. 1. "FV,fuse value" line.long 0x2C "BSEC_FVR11,BSEC fuse word 11 value register" hexmask.long 0x2C 0.--31. 1. "FV,fuse value" line.long 0x30 "BSEC_FVR12,BSEC fuse word 12 value register" hexmask.long 0x30 0.--31. 1. "FV,fuse value" line.long 0x34 "BSEC_FVR13,BSEC fuse word 13 value register" hexmask.long 0x34 0.--31. 1. "FV,fuse value" line.long 0x38 "BSEC_FVR14,BSEC fuse word 14 value register" hexmask.long 0x38 0.--31. 1. "FV,fuse value" line.long 0x3C "BSEC_FVR15,BSEC fuse word 15 value register" hexmask.long 0x3C 0.--31. 1. "FV,fuse value" line.long 0x40 "BSEC_FVR16,BSEC fuse word 16 value register" hexmask.long 0x40 0.--31. 1. "FV,fuse value" line.long 0x44 "BSEC_FVR17,BSEC fuse word 17 value register" hexmask.long 0x44 0.--31. 1. "FV,fuse value" line.long 0x48 "BSEC_FVR18,BSEC fuse word 18 value register" hexmask.long 0x48 0.--31. 1. "FV,fuse value" line.long 0x4C "BSEC_FVR19,BSEC fuse word 19 value register" hexmask.long 0x4C 0.--31. 1. "FV,fuse value" line.long 0x50 "BSEC_FVR20,BSEC fuse word 20 value register" hexmask.long 0x50 0.--31. 1. "FV,fuse value" line.long 0x54 "BSEC_FVR21,BSEC fuse word 21 value register" hexmask.long 0x54 0.--31. 1. "FV,fuse value" line.long 0x58 "BSEC_FVR22,BSEC fuse word 22 value register" hexmask.long 0x58 0.--31. 1. "FV,fuse value" line.long 0x5C "BSEC_FVR23,BSEC fuse word 23 value register" hexmask.long 0x5C 0.--31. 1. "FV,fuse value" line.long 0x60 "BSEC_FVR24,BSEC fuse word 24 value register" hexmask.long 0x60 0.--31. 1. "FV,fuse value" line.long 0x64 "BSEC_FVR25,BSEC fuse word 25 value register" hexmask.long 0x64 0.--31. 1. "FV,fuse value" line.long 0x68 "BSEC_FVR26,BSEC fuse word 26 value register" hexmask.long 0x68 0.--31. 1. "FV,fuse value" line.long 0x6C "BSEC_FVR27,BSEC fuse word 27 value register" hexmask.long 0x6C 0.--31. 1. "FV,fuse value" line.long 0x70 "BSEC_FVR28,BSEC fuse word 28 value register" hexmask.long 0x70 0.--31. 1. "FV,fuse value" line.long 0x74 "BSEC_FVR29,BSEC fuse word 29 value register" hexmask.long 0x74 0.--31. 1. "FV,fuse value" line.long 0x78 "BSEC_FVR30,BSEC fuse word 30 value register" hexmask.long 0x78 0.--31. 1. "FV,fuse value" line.long 0x7C "BSEC_FVR31,BSEC fuse word 31 value register" hexmask.long 0x7C 0.--31. 1. "FV,fuse value" line.long 0x80 "BSEC_FVR32,BSEC fuse word 32 value register" hexmask.long 0x80 0.--31. 1. "FV,fuse value" line.long 0x84 "BSEC_FVR33,BSEC fuse word 33 value register" hexmask.long 0x84 0.--31. 1. "FV,fuse value" line.long 0x88 "BSEC_FVR34,BSEC fuse word 34 value register" hexmask.long 0x88 0.--31. 1. "FV,fuse value" line.long 0x8C "BSEC_FVR35,BSEC fuse word 35 value register" hexmask.long 0x8C 0.--31. 1. "FV,fuse value" line.long 0x90 "BSEC_FVR36,BSEC fuse word 36 value register" hexmask.long 0x90 0.--31. 1. "FV,fuse value" line.long 0x94 "BSEC_FVR37,BSEC fuse word 37 value register" hexmask.long 0x94 0.--31. 1. "FV,fuse value" line.long 0x98 "BSEC_FVR38,BSEC fuse word 38 value register" hexmask.long 0x98 0.--31. 1. "FV,fuse value" line.long 0x9C "BSEC_FVR39,BSEC fuse word 39 value register" hexmask.long 0x9C 0.--31. 1. "FV,fuse value" line.long 0xA0 "BSEC_FVR40,BSEC fuse word 40 value register" hexmask.long 0xA0 0.--31. 1. "FV,fuse value" line.long 0xA4 "BSEC_FVR41,BSEC fuse word 41 value register" hexmask.long 0xA4 0.--31. 1. "FV,fuse value" line.long 0xA8 "BSEC_FVR42,BSEC fuse word 42 value register" hexmask.long 0xA8 0.--31. 1. "FV,fuse value" line.long 0xAC "BSEC_FVR43,BSEC fuse word 43 value register" hexmask.long 0xAC 0.--31. 1. "FV,fuse value" line.long 0xB0 "BSEC_FVR44,BSEC fuse word 44 value register" hexmask.long 0xB0 0.--31. 1. "FV,fuse value" line.long 0xB4 "BSEC_FVR45,BSEC fuse word 45 value register" hexmask.long 0xB4 0.--31. 1. "FV,fuse value" line.long 0xB8 "BSEC_FVR46,BSEC fuse word 46 value register" hexmask.long 0xB8 0.--31. 1. "FV,fuse value" line.long 0xBC "BSEC_FVR47,BSEC fuse word 47 value register" hexmask.long 0xBC 0.--31. 1. "FV,fuse value" line.long 0xC0 "BSEC_FVR48,BSEC fuse word 48 value register" hexmask.long 0xC0 0.--31. 1. "FV,fuse value" line.long 0xC4 "BSEC_FVR49,BSEC fuse word 49 value register" hexmask.long 0xC4 0.--31. 1. "FV,fuse value" line.long 0xC8 "BSEC_FVR50,BSEC fuse word 50 value register" hexmask.long 0xC8 0.--31. 1. "FV,fuse value" line.long 0xCC "BSEC_FVR51,BSEC fuse word 51 value register" hexmask.long 0xCC 0.--31. 1. "FV,fuse value" line.long 0xD0 "BSEC_FVR52,BSEC fuse word 52 value register" hexmask.long 0xD0 0.--31. 1. "FV,fuse value" line.long 0xD4 "BSEC_FVR53,BSEC fuse word 53 value register" hexmask.long 0xD4 0.--31. 1. "FV,fuse value" line.long 0xD8 "BSEC_FVR54,BSEC fuse word 54 value register" hexmask.long 0xD8 0.--31. 1. "FV,fuse value" line.long 0xDC "BSEC_FVR55,BSEC fuse word 55 value register" hexmask.long 0xDC 0.--31. 1. "FV,fuse value" line.long 0xE0 "BSEC_FVR56,BSEC fuse word 56 value register" hexmask.long 0xE0 0.--31. 1. "FV,fuse value" line.long 0xE4 "BSEC_FVR57,BSEC fuse word 57 value register" hexmask.long 0xE4 0.--31. 1. "FV,fuse value" line.long 0xE8 "BSEC_FVR58,BSEC fuse word 58 value register" hexmask.long 0xE8 0.--31. 1. "FV,fuse value" line.long 0xEC "BSEC_FVR59,BSEC fuse word 59 value register" hexmask.long 0xEC 0.--31. 1. "FV,fuse value" line.long 0xF0 "BSEC_FVR60,BSEC fuse word 60 value register" hexmask.long 0xF0 0.--31. 1. "FV,fuse value" line.long 0xF4 "BSEC_FVR61,BSEC fuse word 61 value register" hexmask.long 0xF4 0.--31. 1. "FV,fuse value" line.long 0xF8 "BSEC_FVR62,BSEC fuse word 62 value register" hexmask.long 0xF8 0.--31. 1. "FV,fuse value" line.long 0xFC "BSEC_FVR63,BSEC fuse word 63 value register" hexmask.long 0xFC 0.--31. 1. "FV,fuse value" line.long 0x100 "BSEC_FVR64,BSEC fuse word 64 value register" hexmask.long 0x100 0.--31. 1. "FV,fuse value" line.long 0x104 "BSEC_FVR65,BSEC fuse word 65 value register" hexmask.long 0x104 0.--31. 1. "FV,fuse value" line.long 0x108 "BSEC_FVR66,BSEC fuse word 66 value register" hexmask.long 0x108 0.--31. 1. "FV,fuse value" line.long 0x10C "BSEC_FVR67,BSEC fuse word 67 value register" hexmask.long 0x10C 0.--31. 1. "FV,fuse value" line.long 0x110 "BSEC_FVR68,BSEC fuse word 68 value register" hexmask.long 0x110 0.--31. 1. "FV,fuse value" line.long 0x114 "BSEC_FVR69,BSEC fuse word 69 value register" hexmask.long 0x114 0.--31. 1. "FV,fuse value" line.long 0x118 "BSEC_FVR70,BSEC fuse word 70 value register" hexmask.long 0x118 0.--31. 1. "FV,fuse value" line.long 0x11C "BSEC_FVR71,BSEC fuse word 71 value register" hexmask.long 0x11C 0.--31. 1. "FV,fuse value" line.long 0x120 "BSEC_FVR72,BSEC fuse word 72 value register" hexmask.long 0x120 0.--31. 1. "FV,fuse value" line.long 0x124 "BSEC_FVR73,BSEC fuse word 73 value register" hexmask.long 0x124 0.--31. 1. "FV,fuse value" line.long 0x128 "BSEC_FVR74,BSEC fuse word 74 value register" hexmask.long 0x128 0.--31. 1. "FV,fuse value" line.long 0x12C "BSEC_FVR75,BSEC fuse word 75 value register" hexmask.long 0x12C 0.--31. 1. "FV,fuse value" line.long 0x130 "BSEC_FVR76,BSEC fuse word 76 value register" hexmask.long 0x130 0.--31. 1. "FV,fuse value" line.long 0x134 "BSEC_FVR77,BSEC fuse word 77 value register" hexmask.long 0x134 0.--31. 1. "FV,fuse value" line.long 0x138 "BSEC_FVR78,BSEC fuse word 78 value register" hexmask.long 0x138 0.--31. 1. "FV,fuse value" line.long 0x13C "BSEC_FVR79,BSEC fuse word 79 value register" hexmask.long 0x13C 0.--31. 1. "FV,fuse value" line.long 0x140 "BSEC_FVR80,BSEC fuse word 80 value register" hexmask.long 0x140 0.--31. 1. "FV,fuse value" line.long 0x144 "BSEC_FVR81,BSEC fuse word 81 value register" hexmask.long 0x144 0.--31. 1. "FV,fuse value" line.long 0x148 "BSEC_FVR82,BSEC fuse word 82 value register" hexmask.long 0x148 0.--31. 1. "FV,fuse value" line.long 0x14C "BSEC_FVR83,BSEC fuse word 83 value register" hexmask.long 0x14C 0.--31. 1. "FV,fuse value" line.long 0x150 "BSEC_FVR84,BSEC fuse word 84 value register" hexmask.long 0x150 0.--31. 1. "FV,fuse value" line.long 0x154 "BSEC_FVR85,BSEC fuse word 85 value register" hexmask.long 0x154 0.--31. 1. "FV,fuse value" line.long 0x158 "BSEC_FVR86,BSEC fuse word 86 value register" hexmask.long 0x158 0.--31. 1. "FV,fuse value" line.long 0x15C "BSEC_FVR87,BSEC fuse word 87 value register" hexmask.long 0x15C 0.--31. 1. "FV,fuse value" line.long 0x160 "BSEC_FVR88,BSEC fuse word 88 value register" hexmask.long 0x160 0.--31. 1. "FV,fuse value" line.long 0x164 "BSEC_FVR89,BSEC fuse word 89 value register" hexmask.long 0x164 0.--31. 1. "FV,fuse value" line.long 0x168 "BSEC_FVR90,BSEC fuse word 90 value register" hexmask.long 0x168 0.--31. 1. "FV,fuse value" line.long 0x16C "BSEC_FVR91,BSEC fuse word 91 value register" hexmask.long 0x16C 0.--31. 1. "FV,fuse value" line.long 0x170 "BSEC_FVR92,BSEC fuse word 92 value register" hexmask.long 0x170 0.--31. 1. "FV,fuse value" line.long 0x174 "BSEC_FVR93,BSEC fuse word 93 value register" hexmask.long 0x174 0.--31. 1. "FV,fuse value" line.long 0x178 "BSEC_FVR94,BSEC fuse word 94 value register" hexmask.long 0x178 0.--31. 1. "FV,fuse value" line.long 0x17C "BSEC_FVR95,BSEC fuse word 95 value register" hexmask.long 0x17C 0.--31. 1. "FV,fuse value" line.long 0x180 "BSEC_FVR96,BSEC fuse word 96 value register" hexmask.long 0x180 0.--31. 1. "FV,fuse value" line.long 0x184 "BSEC_FVR97,BSEC fuse word 97 value register" hexmask.long 0x184 0.--31. 1. "FV,fuse value" line.long 0x188 "BSEC_FVR98,BSEC fuse word 98 value register" hexmask.long 0x188 0.--31. 1. "FV,fuse value" line.long 0x18C "BSEC_FVR99,BSEC fuse word 99 value register" hexmask.long 0x18C 0.--31. 1. "FV,fuse value" line.long 0x190 "BSEC_FVR100,BSEC fuse word 100 value register" hexmask.long 0x190 0.--31. 1. "FV,fuse value" line.long 0x194 "BSEC_FVR101,BSEC fuse word 101 value register" hexmask.long 0x194 0.--31. 1. "FV,fuse value" line.long 0x198 "BSEC_FVR102,BSEC fuse word 102 value register" hexmask.long 0x198 0.--31. 1. "FV,fuse value" line.long 0x19C "BSEC_FVR103,BSEC fuse word 103 value register" hexmask.long 0x19C 0.--31. 1. "FV,fuse value" line.long 0x1A0 "BSEC_FVR104,BSEC fuse word 104 value register" hexmask.long 0x1A0 0.--31. 1. "FV,fuse value" line.long 0x1A4 "BSEC_FVR105,BSEC fuse word 105 value register" hexmask.long 0x1A4 0.--31. 1. "FV,fuse value" line.long 0x1A8 "BSEC_FVR106,BSEC fuse word 106 value register" hexmask.long 0x1A8 0.--31. 1. "FV,fuse value" line.long 0x1AC "BSEC_FVR107,BSEC fuse word 107 value register" hexmask.long 0x1AC 0.--31. 1. "FV,fuse value" line.long 0x1B0 "BSEC_FVR108,BSEC fuse word 108 value register" hexmask.long 0x1B0 0.--31. 1. "FV,fuse value" line.long 0x1B4 "BSEC_FVR109,BSEC fuse word 109 value register" hexmask.long 0x1B4 0.--31. 1. "FV,fuse value" line.long 0x1B8 "BSEC_FVR110,BSEC fuse word 110 value register" hexmask.long 0x1B8 0.--31. 1. "FV,fuse value" line.long 0x1BC "BSEC_FVR111,BSEC fuse word 111 value register" hexmask.long 0x1BC 0.--31. 1. "FV,fuse value" line.long 0x1C0 "BSEC_FVR112,BSEC fuse word 112 value register" hexmask.long 0x1C0 0.--31. 1. "FV,fuse value" line.long 0x1C4 "BSEC_FVR113,BSEC fuse word 113 value register" hexmask.long 0x1C4 0.--31. 1. "FV,fuse value" line.long 0x1C8 "BSEC_FVR114,BSEC fuse word 114 value register" hexmask.long 0x1C8 0.--31. 1. "FV,fuse value" line.long 0x1CC "BSEC_FVR115,BSEC fuse word 115 value register" hexmask.long 0x1CC 0.--31. 1. "FV,fuse value" line.long 0x1D0 "BSEC_FVR116,BSEC fuse word 116 value register" hexmask.long 0x1D0 0.--31. 1. "FV,fuse value" line.long 0x1D4 "BSEC_FVR117,BSEC fuse word 117 value register" hexmask.long 0x1D4 0.--31. 1. "FV,fuse value" line.long 0x1D8 "BSEC_FVR118,BSEC fuse word 118 value register" hexmask.long 0x1D8 0.--31. 1. "FV,fuse value" line.long 0x1DC "BSEC_FVR119,BSEC fuse word 119 value register" hexmask.long 0x1DC 0.--31. 1. "FV,fuse value" line.long 0x1E0 "BSEC_FVR120,BSEC fuse word 120 value register" hexmask.long 0x1E0 0.--31. 1. "FV,fuse value" line.long 0x1E4 "BSEC_FVR121,BSEC fuse word 121 value register" hexmask.long 0x1E4 0.--31. 1. "FV,fuse value" line.long 0x1E8 "BSEC_FVR122,BSEC fuse word 122 value register" hexmask.long 0x1E8 0.--31. 1. "FV,fuse value" line.long 0x1EC "BSEC_FVR123,BSEC fuse word 123 value register" hexmask.long 0x1EC 0.--31. 1. "FV,fuse value" line.long 0x1F0 "BSEC_FVR124,BSEC fuse word 124 value register" hexmask.long 0x1F0 0.--31. 1. "FV,fuse value" line.long 0x1F4 "BSEC_FVR125,BSEC fuse word 125 value register" hexmask.long 0x1F4 0.--31. 1. "FV,fuse value" line.long 0x1F8 "BSEC_FVR126,BSEC fuse word 126 value register" hexmask.long 0x1F8 0.--31. 1. "FV,fuse value" line.long 0x1FC "BSEC_FVR127,BSEC fuse word 127 value register" hexmask.long 0x1FC 0.--31. 1. "FV,fuse value" line.long 0x200 "BSEC_FVR128,BSEC fuse word 128 value register" hexmask.long 0x200 0.--31. 1. "FV,fuse value" line.long 0x204 "BSEC_FVR129,BSEC fuse word 129 value register" hexmask.long 0x204 0.--31. 1. "FV,fuse value" line.long 0x208 "BSEC_FVR130,BSEC fuse word 130 value register" hexmask.long 0x208 0.--31. 1. "FV,fuse value" line.long 0x20C "BSEC_FVR131,BSEC fuse word 131 value register" hexmask.long 0x20C 0.--31. 1. "FV,fuse value" line.long 0x210 "BSEC_FVR132,BSEC fuse word 132 value register" hexmask.long 0x210 0.--31. 1. "FV,fuse value" line.long 0x214 "BSEC_FVR133,BSEC fuse word 133 value register" hexmask.long 0x214 0.--31. 1. "FV,fuse value" line.long 0x218 "BSEC_FVR134,BSEC fuse word 134 value register" hexmask.long 0x218 0.--31. 1. "FV,fuse value" line.long 0x21C "BSEC_FVR135,BSEC fuse word 135 value register" hexmask.long 0x21C 0.--31. 1. "FV,fuse value" line.long 0x220 "BSEC_FVR136,BSEC fuse word 136 value register" hexmask.long 0x220 0.--31. 1. "FV,fuse value" line.long 0x224 "BSEC_FVR137,BSEC fuse word 137 value register" hexmask.long 0x224 0.--31. 1. "FV,fuse value" line.long 0x228 "BSEC_FVR138,BSEC fuse word 138 value register" hexmask.long 0x228 0.--31. 1. "FV,fuse value" line.long 0x22C "BSEC_FVR139,BSEC fuse word 139 value register" hexmask.long 0x22C 0.--31. 1. "FV,fuse value" line.long 0x230 "BSEC_FVR140,BSEC fuse word 140 value register" hexmask.long 0x230 0.--31. 1. "FV,fuse value" line.long 0x234 "BSEC_FVR141,BSEC fuse word 141 value register" hexmask.long 0x234 0.--31. 1. "FV,fuse value" line.long 0x238 "BSEC_FVR142,BSEC fuse word 142 value register" hexmask.long 0x238 0.--31. 1. "FV,fuse value" line.long 0x23C "BSEC_FVR143,BSEC fuse word 143 value register" hexmask.long 0x23C 0.--31. 1. "FV,fuse value" line.long 0x240 "BSEC_FVR144,BSEC fuse word 144 value register" hexmask.long 0x240 0.--31. 1. "FV,fuse value" line.long 0x244 "BSEC_FVR145,BSEC fuse word 145 value register" hexmask.long 0x244 0.--31. 1. "FV,fuse value" line.long 0x248 "BSEC_FVR146,BSEC fuse word 146 value register" hexmask.long 0x248 0.--31. 1. "FV,fuse value" line.long 0x24C "BSEC_FVR147,BSEC fuse word 147 value register" hexmask.long 0x24C 0.--31. 1. "FV,fuse value" line.long 0x250 "BSEC_FVR148,BSEC fuse word 148 value register" hexmask.long 0x250 0.--31. 1. "FV,fuse value" line.long 0x254 "BSEC_FVR149,BSEC fuse word 149 value register" hexmask.long 0x254 0.--31. 1. "FV,fuse value" line.long 0x258 "BSEC_FVR150,BSEC fuse word 150 value register" hexmask.long 0x258 0.--31. 1. "FV,fuse value" line.long 0x25C "BSEC_FVR151,BSEC fuse word 151 value register" hexmask.long 0x25C 0.--31. 1. "FV,fuse value" line.long 0x260 "BSEC_FVR152,BSEC fuse word 152 value register" hexmask.long 0x260 0.--31. 1. "FV,fuse value" line.long 0x264 "BSEC_FVR153,BSEC fuse word 153 value register" hexmask.long 0x264 0.--31. 1. "FV,fuse value" line.long 0x268 "BSEC_FVR154,BSEC fuse word 154 value register" hexmask.long 0x268 0.--31. 1. "FV,fuse value" line.long 0x26C "BSEC_FVR155,BSEC fuse word 155 value register" hexmask.long 0x26C 0.--31. 1. "FV,fuse value" line.long 0x270 "BSEC_FVR156,BSEC fuse word 156 value register" hexmask.long 0x270 0.--31. 1. "FV,fuse value" line.long 0x274 "BSEC_FVR157,BSEC fuse word 157 value register" hexmask.long 0x274 0.--31. 1. "FV,fuse value" line.long 0x278 "BSEC_FVR158,BSEC fuse word 158 value register" hexmask.long 0x278 0.--31. 1. "FV,fuse value" line.long 0x27C "BSEC_FVR159,BSEC fuse word 159 value register" hexmask.long 0x27C 0.--31. 1. "FV,fuse value" line.long 0x280 "BSEC_FVR160,BSEC fuse word 160 value register" hexmask.long 0x280 0.--31. 1. "FV,fuse value" line.long 0x284 "BSEC_FVR161,BSEC fuse word 161 value register" hexmask.long 0x284 0.--31. 1. "FV,fuse value" line.long 0x288 "BSEC_FVR162,BSEC fuse word 162 value register" hexmask.long 0x288 0.--31. 1. "FV,fuse value" line.long 0x28C "BSEC_FVR163,BSEC fuse word 163 value register" hexmask.long 0x28C 0.--31. 1. "FV,fuse value" line.long 0x290 "BSEC_FVR164,BSEC fuse word 164 value register" hexmask.long 0x290 0.--31. 1. "FV,fuse value" line.long 0x294 "BSEC_FVR165,BSEC fuse word 165 value register" hexmask.long 0x294 0.--31. 1. "FV,fuse value" line.long 0x298 "BSEC_FVR166,BSEC fuse word 166 value register" hexmask.long 0x298 0.--31. 1. "FV,fuse value" line.long 0x29C "BSEC_FVR167,BSEC fuse word 167 value register" hexmask.long 0x29C 0.--31. 1. "FV,fuse value" line.long 0x2A0 "BSEC_FVR168,BSEC fuse word 168 value register" hexmask.long 0x2A0 0.--31. 1. "FV,fuse value" line.long 0x2A4 "BSEC_FVR169,BSEC fuse word 169 value register" hexmask.long 0x2A4 0.--31. 1. "FV,fuse value" line.long 0x2A8 "BSEC_FVR170,BSEC fuse word 170 value register" hexmask.long 0x2A8 0.--31. 1. "FV,fuse value" line.long 0x2AC "BSEC_FVR171,BSEC fuse word 171 value register" hexmask.long 0x2AC 0.--31. 1. "FV,fuse value" line.long 0x2B0 "BSEC_FVR172,BSEC fuse word 172 value register" hexmask.long 0x2B0 0.--31. 1. "FV,fuse value" line.long 0x2B4 "BSEC_FVR173,BSEC fuse word 173 value register" hexmask.long 0x2B4 0.--31. 1. "FV,fuse value" line.long 0x2B8 "BSEC_FVR174,BSEC fuse word 174 value register" hexmask.long 0x2B8 0.--31. 1. "FV,fuse value" line.long 0x2BC "BSEC_FVR175,BSEC fuse word 175 value register" hexmask.long 0x2BC 0.--31. 1. "FV,fuse value" line.long 0x2C0 "BSEC_FVR176,BSEC fuse word 176 value register" hexmask.long 0x2C0 0.--31. 1. "FV,fuse value" line.long 0x2C4 "BSEC_FVR177,BSEC fuse word 177 value register" hexmask.long 0x2C4 0.--31. 1. "FV,fuse value" line.long 0x2C8 "BSEC_FVR178,BSEC fuse word 178 value register" hexmask.long 0x2C8 0.--31. 1. "FV,fuse value" line.long 0x2CC "BSEC_FVR179,BSEC fuse word 179 value register" hexmask.long 0x2CC 0.--31. 1. "FV,fuse value" line.long 0x2D0 "BSEC_FVR180,BSEC fuse word 180 value register" hexmask.long 0x2D0 0.--31. 1. "FV,fuse value" line.long 0x2D4 "BSEC_FVR181,BSEC fuse word 181 value register" hexmask.long 0x2D4 0.--31. 1. "FV,fuse value" line.long 0x2D8 "BSEC_FVR182,BSEC fuse word 182 value register" hexmask.long 0x2D8 0.--31. 1. "FV,fuse value" line.long 0x2DC "BSEC_FVR183,BSEC fuse word 183 value register" hexmask.long 0x2DC 0.--31. 1. "FV,fuse value" line.long 0x2E0 "BSEC_FVR184,BSEC fuse word 184 value register" hexmask.long 0x2E0 0.--31. 1. "FV,fuse value" line.long 0x2E4 "BSEC_FVR185,BSEC fuse word 185 value register" hexmask.long 0x2E4 0.--31. 1. "FV,fuse value" line.long 0x2E8 "BSEC_FVR186,BSEC fuse word 186 value register" hexmask.long 0x2E8 0.--31. 1. "FV,fuse value" line.long 0x2EC "BSEC_FVR187,BSEC fuse word 187 value register" hexmask.long 0x2EC 0.--31. 1. "FV,fuse value" line.long 0x2F0 "BSEC_FVR188,BSEC fuse word 188 value register" hexmask.long 0x2F0 0.--31. 1. "FV,fuse value" line.long 0x2F4 "BSEC_FVR189,BSEC fuse word 189 value register" hexmask.long 0x2F4 0.--31. 1. "FV,fuse value" line.long 0x2F8 "BSEC_FVR190,BSEC fuse word 190 value register" hexmask.long 0x2F8 0.--31. 1. "FV,fuse value" line.long 0x2FC "BSEC_FVR191,BSEC fuse word 191 value register" hexmask.long 0x2FC 0.--31. 1. "FV,fuse value" line.long 0x300 "BSEC_FVR192,BSEC fuse word 192 value register" hexmask.long 0x300 0.--31. 1. "FV,fuse value" line.long 0x304 "BSEC_FVR193,BSEC fuse word 193 value register" hexmask.long 0x304 0.--31. 1. "FV,fuse value" line.long 0x308 "BSEC_FVR194,BSEC fuse word 194 value register" hexmask.long 0x308 0.--31. 1. "FV,fuse value" line.long 0x30C "BSEC_FVR195,BSEC fuse word 195 value register" hexmask.long 0x30C 0.--31. 1. "FV,fuse value" line.long 0x310 "BSEC_FVR196,BSEC fuse word 196 value register" hexmask.long 0x310 0.--31. 1. "FV,fuse value" line.long 0x314 "BSEC_FVR197,BSEC fuse word 197 value register" hexmask.long 0x314 0.--31. 1. "FV,fuse value" line.long 0x318 "BSEC_FVR198,BSEC fuse word 198 value register" hexmask.long 0x318 0.--31. 1. "FV,fuse value" line.long 0x31C "BSEC_FVR199,BSEC fuse word 199 value register" hexmask.long 0x31C 0.--31. 1. "FV,fuse value" line.long 0x320 "BSEC_FVR200,BSEC fuse word 200 value register" hexmask.long 0x320 0.--31. 1. "FV,fuse value" line.long 0x324 "BSEC_FVR201,BSEC fuse word 201 value register" hexmask.long 0x324 0.--31. 1. "FV,fuse value" line.long 0x328 "BSEC_FVR202,BSEC fuse word 202 value register" hexmask.long 0x328 0.--31. 1. "FV,fuse value" line.long 0x32C "BSEC_FVR203,BSEC fuse word 203 value register" hexmask.long 0x32C 0.--31. 1. "FV,fuse value" line.long 0x330 "BSEC_FVR204,BSEC fuse word 204 value register" hexmask.long 0x330 0.--31. 1. "FV,fuse value" line.long 0x334 "BSEC_FVR205,BSEC fuse word 205 value register" hexmask.long 0x334 0.--31. 1. "FV,fuse value" line.long 0x338 "BSEC_FVR206,BSEC fuse word 206 value register" hexmask.long 0x338 0.--31. 1. "FV,fuse value" line.long 0x33C "BSEC_FVR207,BSEC fuse word 207 value register" hexmask.long 0x33C 0.--31. 1. "FV,fuse value" line.long 0x340 "BSEC_FVR208,BSEC fuse word 208 value register" hexmask.long 0x340 0.--31. 1. "FV,fuse value" line.long 0x344 "BSEC_FVR209,BSEC fuse word 209 value register" hexmask.long 0x344 0.--31. 1. "FV,fuse value" line.long 0x348 "BSEC_FVR210,BSEC fuse word 210 value register" hexmask.long 0x348 0.--31. 1. "FV,fuse value" line.long 0x34C "BSEC_FVR211,BSEC fuse word 211 value register" hexmask.long 0x34C 0.--31. 1. "FV,fuse value" line.long 0x350 "BSEC_FVR212,BSEC fuse word 212 value register" hexmask.long 0x350 0.--31. 1. "FV,fuse value" line.long 0x354 "BSEC_FVR213,BSEC fuse word 213 value register" hexmask.long 0x354 0.--31. 1. "FV,fuse value" line.long 0x358 "BSEC_FVR214,BSEC fuse word 214 value register" hexmask.long 0x358 0.--31. 1. "FV,fuse value" line.long 0x35C "BSEC_FVR215,BSEC fuse word 215 value register" hexmask.long 0x35C 0.--31. 1. "FV,fuse value" line.long 0x360 "BSEC_FVR216,BSEC fuse word 216 value register" hexmask.long 0x360 0.--31. 1. "FV,fuse value" line.long 0x364 "BSEC_FVR217,BSEC fuse word 217 value register" hexmask.long 0x364 0.--31. 1. "FV,fuse value" line.long 0x368 "BSEC_FVR218,BSEC fuse word 218 value register" hexmask.long 0x368 0.--31. 1. "FV,fuse value" line.long 0x36C "BSEC_FVR219,BSEC fuse word 219 value register" hexmask.long 0x36C 0.--31. 1. "FV,fuse value" line.long 0x370 "BSEC_FVR220,BSEC fuse word 220 value register" hexmask.long 0x370 0.--31. 1. "FV,fuse value" line.long 0x374 "BSEC_FVR221,BSEC fuse word 221 value register" hexmask.long 0x374 0.--31. 1. "FV,fuse value" line.long 0x378 "BSEC_FVR222,BSEC fuse word 222 value register" hexmask.long 0x378 0.--31. 1. "FV,fuse value" line.long 0x37C "BSEC_FVR223,BSEC fuse word 223 value register" hexmask.long 0x37C 0.--31. 1. "FV,fuse value" line.long 0x380 "BSEC_FVR224,BSEC fuse word 224 value register" hexmask.long 0x380 0.--31. 1. "FV,fuse value" line.long 0x384 "BSEC_FVR225,BSEC fuse word 225 value register" hexmask.long 0x384 0.--31. 1. "FV,fuse value" line.long 0x388 "BSEC_FVR226,BSEC fuse word 226 value register" hexmask.long 0x388 0.--31. 1. "FV,fuse value" line.long 0x38C "BSEC_FVR227,BSEC fuse word 227 value register" hexmask.long 0x38C 0.--31. 1. "FV,fuse value" line.long 0x390 "BSEC_FVR228,BSEC fuse word 228 value register" hexmask.long 0x390 0.--31. 1. "FV,fuse value" line.long 0x394 "BSEC_FVR229,BSEC fuse word 229 value register" hexmask.long 0x394 0.--31. 1. "FV,fuse value" line.long 0x398 "BSEC_FVR230,BSEC fuse word 230 value register" hexmask.long 0x398 0.--31. 1. "FV,fuse value" line.long 0x39C "BSEC_FVR231,BSEC fuse word 231 value register" hexmask.long 0x39C 0.--31. 1. "FV,fuse value" line.long 0x3A0 "BSEC_FVR232,BSEC fuse word 232 value register" hexmask.long 0x3A0 0.--31. 1. "FV,fuse value" line.long 0x3A4 "BSEC_FVR233,BSEC fuse word 233 value register" hexmask.long 0x3A4 0.--31. 1. "FV,fuse value" line.long 0x3A8 "BSEC_FVR234,BSEC fuse word 234 value register" hexmask.long 0x3A8 0.--31. 1. "FV,fuse value" line.long 0x3AC "BSEC_FVR235,BSEC fuse word 235 value register" hexmask.long 0x3AC 0.--31. 1. "FV,fuse value" line.long 0x3B0 "BSEC_FVR236,BSEC fuse word 236 value register" hexmask.long 0x3B0 0.--31. 1. "FV,fuse value" line.long 0x3B4 "BSEC_FVR237,BSEC fuse word 237 value register" hexmask.long 0x3B4 0.--31. 1. "FV,fuse value" line.long 0x3B8 "BSEC_FVR238,BSEC fuse word 238 value register" hexmask.long 0x3B8 0.--31. 1. "FV,fuse value" line.long 0x3BC "BSEC_FVR239,BSEC fuse word 239 value register" hexmask.long 0x3BC 0.--31. 1. "FV,fuse value" line.long 0x3C0 "BSEC_FVR240,BSEC fuse word 240 value register" hexmask.long 0x3C0 0.--31. 1. "FV,fuse value" line.long 0x3C4 "BSEC_FVR241,BSEC fuse word 241 value register" hexmask.long 0x3C4 0.--31. 1. "FV,fuse value" line.long 0x3C8 "BSEC_FVR242,BSEC fuse word 242 value register" hexmask.long 0x3C8 0.--31. 1. "FV,fuse value" line.long 0x3CC "BSEC_FVR243,BSEC fuse word 243 value register" hexmask.long 0x3CC 0.--31. 1. "FV,fuse value" line.long 0x3D0 "BSEC_FVR244,BSEC fuse word 244 value register" hexmask.long 0x3D0 0.--31. 1. "FV,fuse value" line.long 0x3D4 "BSEC_FVR245,BSEC fuse word 245 value register" hexmask.long 0x3D4 0.--31. 1. "FV,fuse value" line.long 0x3D8 "BSEC_FVR246,BSEC fuse word 246 value register" hexmask.long 0x3D8 0.--31. 1. "FV,fuse value" line.long 0x3DC "BSEC_FVR247,BSEC fuse word 247 value register" hexmask.long 0x3DC 0.--31. 1. "FV,fuse value" line.long 0x3E0 "BSEC_FVR248,BSEC fuse word 248 value register" hexmask.long 0x3E0 0.--31. 1. "FV,fuse value" line.long 0x3E4 "BSEC_FVR249,BSEC fuse word 249 value register" hexmask.long 0x3E4 0.--31. 1. "FV,fuse value" line.long 0x3E8 "BSEC_FVR250,BSEC fuse word 250 value register" hexmask.long 0x3E8 0.--31. 1. "FV,fuse value" line.long 0x3EC "BSEC_FVR251,BSEC fuse word 251 value register" hexmask.long 0x3EC 0.--31. 1. "FV,fuse value" line.long 0x3F0 "BSEC_FVR252,BSEC fuse word 252 value register" hexmask.long 0x3F0 0.--31. 1. "FV,fuse value" line.long 0x3F4 "BSEC_FVR253,BSEC fuse word 253 value register" hexmask.long 0x3F4 0.--31. 1. "FV,fuse value" line.long 0x3F8 "BSEC_FVR254,BSEC fuse word 254 value register" hexmask.long 0x3F8 0.--31. 1. "FV,fuse value" line.long 0x3FC "BSEC_FVR255,BSEC fuse word 255 value register" hexmask.long 0x3FC 0.--31. 1. "FV,fuse value" line.long 0x400 "BSEC_FVR256,BSEC fuse word 256 value register" hexmask.long 0x400 0.--31. 1. "FV,fuse value" line.long 0x404 "BSEC_FVR257,BSEC fuse word 257 value register" hexmask.long 0x404 0.--31. 1. "FV,fuse value" line.long 0x408 "BSEC_FVR258,BSEC fuse word 258 value register" hexmask.long 0x408 0.--31. 1. "FV,fuse value" line.long 0x40C "BSEC_FVR259,BSEC fuse word 259 value register" hexmask.long 0x40C 0.--31. 1. "FV,fuse value" line.long 0x410 "BSEC_FVR260,BSEC fuse word 260 value register" hexmask.long 0x410 0.--31. 1. "FV,fuse value" line.long 0x414 "BSEC_FVR261,BSEC fuse word 261 value register" hexmask.long 0x414 0.--31. 1. "FV,fuse value" line.long 0x418 "BSEC_FVR262,BSEC fuse word 262 value register" hexmask.long 0x418 0.--31. 1. "FV,fuse value" line.long 0x41C "BSEC_FVR263,BSEC fuse word 263 value register" hexmask.long 0x41C 0.--31. 1. "FV,fuse value" line.long 0x420 "BSEC_FVR264,BSEC fuse word 264 value register" hexmask.long 0x420 0.--31. 1. "FV,fuse value" line.long 0x424 "BSEC_FVR265,BSEC fuse word 265 value register" hexmask.long 0x424 0.--31. 1. "FV,fuse value" line.long 0x428 "BSEC_FVR266,BSEC fuse word 266 value register" hexmask.long 0x428 0.--31. 1. "FV,fuse value" line.long 0x42C "BSEC_FVR267,BSEC fuse word 267 value register" hexmask.long 0x42C 0.--31. 1. "FV,fuse value" line.long 0x430 "BSEC_FVR268,BSEC fuse word 268 value register" hexmask.long 0x430 0.--31. 1. "FV,fuse value" line.long 0x434 "BSEC_FVR269,BSEC fuse word 269 value register" hexmask.long 0x434 0.--31. 1. "FV,fuse value" line.long 0x438 "BSEC_FVR270,BSEC fuse word 270 value register" hexmask.long 0x438 0.--31. 1. "FV,fuse value" line.long 0x43C "BSEC_FVR271,BSEC fuse word 271 value register" hexmask.long 0x43C 0.--31. 1. "FV,fuse value" line.long 0x440 "BSEC_FVR272,BSEC fuse word 272 value register" hexmask.long 0x440 0.--31. 1. "FV,fuse value" line.long 0x444 "BSEC_FVR273,BSEC fuse word 273 value register" hexmask.long 0x444 0.--31. 1. "FV,fuse value" line.long 0x448 "BSEC_FVR274,BSEC fuse word 274 value register" hexmask.long 0x448 0.--31. 1. "FV,fuse value" line.long 0x44C "BSEC_FVR275,BSEC fuse word 275 value register" hexmask.long 0x44C 0.--31. 1. "FV,fuse value" line.long 0x450 "BSEC_FVR276,BSEC fuse word 276 value register" hexmask.long 0x450 0.--31. 1. "FV,fuse value" line.long 0x454 "BSEC_FVR277,BSEC fuse word 277 value register" hexmask.long 0x454 0.--31. 1. "FV,fuse value" line.long 0x458 "BSEC_FVR278,BSEC fuse word 278 value register" hexmask.long 0x458 0.--31. 1. "FV,fuse value" line.long 0x45C "BSEC_FVR279,BSEC fuse word 279 value register" hexmask.long 0x45C 0.--31. 1. "FV,fuse value" line.long 0x460 "BSEC_FVR280,BSEC fuse word 280 value register" hexmask.long 0x460 0.--31. 1. "FV,fuse value" line.long 0x464 "BSEC_FVR281,BSEC fuse word 281 value register" hexmask.long 0x464 0.--31. 1. "FV,fuse value" line.long 0x468 "BSEC_FVR282,BSEC fuse word 282 value register" hexmask.long 0x468 0.--31. 1. "FV,fuse value" line.long 0x46C "BSEC_FVR283,BSEC fuse word 283 value register" hexmask.long 0x46C 0.--31. 1. "FV,fuse value" line.long 0x470 "BSEC_FVR284,BSEC fuse word 284 value register" hexmask.long 0x470 0.--31. 1. "FV,fuse value" line.long 0x474 "BSEC_FVR285,BSEC fuse word 285 value register" hexmask.long 0x474 0.--31. 1. "FV,fuse value" line.long 0x478 "BSEC_FVR286,BSEC fuse word 286 value register" hexmask.long 0x478 0.--31. 1. "FV,fuse value" line.long 0x47C "BSEC_FVR287,BSEC fuse word 287 value register" hexmask.long 0x47C 0.--31. 1. "FV,fuse value" line.long 0x480 "BSEC_FVR288,BSEC fuse word 288 value register" hexmask.long 0x480 0.--31. 1. "FV,fuse value" line.long 0x484 "BSEC_FVR289,BSEC fuse word 289 value register" hexmask.long 0x484 0.--31. 1. "FV,fuse value" line.long 0x488 "BSEC_FVR290,BSEC fuse word 290 value register" hexmask.long 0x488 0.--31. 1. "FV,fuse value" line.long 0x48C "BSEC_FVR291,BSEC fuse word 291 value register" hexmask.long 0x48C 0.--31. 1. "FV,fuse value" line.long 0x490 "BSEC_FVR292,BSEC fuse word 292 value register" hexmask.long 0x490 0.--31. 1. "FV,fuse value" line.long 0x494 "BSEC_FVR293,BSEC fuse word 293 value register" hexmask.long 0x494 0.--31. 1. "FV,fuse value" line.long 0x498 "BSEC_FVR294,BSEC fuse word 294 value register" hexmask.long 0x498 0.--31. 1. "FV,fuse value" line.long 0x49C "BSEC_FVR295,BSEC fuse word 295 value register" hexmask.long 0x49C 0.--31. 1. "FV,fuse value" line.long 0x4A0 "BSEC_FVR296,BSEC fuse word 296 value register" hexmask.long 0x4A0 0.--31. 1. "FV,fuse value" line.long 0x4A4 "BSEC_FVR297,BSEC fuse word 297 value register" hexmask.long 0x4A4 0.--31. 1. "FV,fuse value" line.long 0x4A8 "BSEC_FVR298,BSEC fuse word 298 value register" hexmask.long 0x4A8 0.--31. 1. "FV,fuse value" line.long 0x4AC "BSEC_FVR299,BSEC fuse word 299 value register" hexmask.long 0x4AC 0.--31. 1. "FV,fuse value" line.long 0x4B0 "BSEC_FVR300,BSEC fuse word 300 value register" hexmask.long 0x4B0 0.--31. 1. "FV,fuse value" line.long 0x4B4 "BSEC_FVR301,BSEC fuse word 301 value register" hexmask.long 0x4B4 0.--31. 1. "FV,fuse value" line.long 0x4B8 "BSEC_FVR302,BSEC fuse word 302 value register" hexmask.long 0x4B8 0.--31. 1. "FV,fuse value" line.long 0x4BC "BSEC_FVR303,BSEC fuse word 303 value register" hexmask.long 0x4BC 0.--31. 1. "FV,fuse value" line.long 0x4C0 "BSEC_FVR304,BSEC fuse word 304 value register" hexmask.long 0x4C0 0.--31. 1. "FV,fuse value" line.long 0x4C4 "BSEC_FVR305,BSEC fuse word 305 value register" hexmask.long 0x4C4 0.--31. 1. "FV,fuse value" line.long 0x4C8 "BSEC_FVR306,BSEC fuse word 306 value register" hexmask.long 0x4C8 0.--31. 1. "FV,fuse value" line.long 0x4CC "BSEC_FVR307,BSEC fuse word 307 value register" hexmask.long 0x4CC 0.--31. 1. "FV,fuse value" line.long 0x4D0 "BSEC_FVR308,BSEC fuse word 308 value register" hexmask.long 0x4D0 0.--31. 1. "FV,fuse value" line.long 0x4D4 "BSEC_FVR309,BSEC fuse word 309 value register" hexmask.long 0x4D4 0.--31. 1. "FV,fuse value" line.long 0x4D8 "BSEC_FVR310,BSEC fuse word 310 value register" hexmask.long 0x4D8 0.--31. 1. "FV,fuse value" line.long 0x4DC "BSEC_FVR311,BSEC fuse word 311 value register" hexmask.long 0x4DC 0.--31. 1. "FV,fuse value" line.long 0x4E0 "BSEC_FVR312,BSEC fuse word 312 value register" hexmask.long 0x4E0 0.--31. 1. "FV,fuse value" line.long 0x4E4 "BSEC_FVR313,BSEC fuse word 313 value register" hexmask.long 0x4E4 0.--31. 1. "FV,fuse value" line.long 0x4E8 "BSEC_FVR314,BSEC fuse word 314 value register" hexmask.long 0x4E8 0.--31. 1. "FV,fuse value" line.long 0x4EC "BSEC_FVR315,BSEC fuse word 315 value register" hexmask.long 0x4EC 0.--31. 1. "FV,fuse value" line.long 0x4F0 "BSEC_FVR316,BSEC fuse word 316 value register" hexmask.long 0x4F0 0.--31. 1. "FV,fuse value" line.long 0x4F4 "BSEC_FVR317,BSEC fuse word 317 value register" hexmask.long 0x4F4 0.--31. 1. "FV,fuse value" line.long 0x4F8 "BSEC_FVR318,BSEC fuse word 318 value register" hexmask.long 0x4F8 0.--31. 1. "FV,fuse value" line.long 0x4FC "BSEC_FVR319,BSEC fuse word 319 value register" hexmask.long 0x4FC 0.--31. 1. "FV,fuse value" line.long 0x500 "BSEC_FVR320,BSEC fuse word 320 value register" hexmask.long 0x500 0.--31. 1. "FV,fuse value" line.long 0x504 "BSEC_FVR321,BSEC fuse word 321 value register" hexmask.long 0x504 0.--31. 1. "FV,fuse value" line.long 0x508 "BSEC_FVR322,BSEC fuse word 322 value register" hexmask.long 0x508 0.--31. 1. "FV,fuse value" line.long 0x50C "BSEC_FVR323,BSEC fuse word 323 value register" hexmask.long 0x50C 0.--31. 1. "FV,fuse value" line.long 0x510 "BSEC_FVR324,BSEC fuse word 324 value register" hexmask.long 0x510 0.--31. 1. "FV,fuse value" line.long 0x514 "BSEC_FVR325,BSEC fuse word 325 value register" hexmask.long 0x514 0.--31. 1. "FV,fuse value" line.long 0x518 "BSEC_FVR326,BSEC fuse word 326 value register" hexmask.long 0x518 0.--31. 1. "FV,fuse value" line.long 0x51C "BSEC_FVR327,BSEC fuse word 327 value register" hexmask.long 0x51C 0.--31. 1. "FV,fuse value" line.long 0x520 "BSEC_FVR328,BSEC fuse word 328 value register" hexmask.long 0x520 0.--31. 1. "FV,fuse value" line.long 0x524 "BSEC_FVR329,BSEC fuse word 329 value register" hexmask.long 0x524 0.--31. 1. "FV,fuse value" line.long 0x528 "BSEC_FVR330,BSEC fuse word 330 value register" hexmask.long 0x528 0.--31. 1. "FV,fuse value" line.long 0x52C "BSEC_FVR331,BSEC fuse word 331 value register" hexmask.long 0x52C 0.--31. 1. "FV,fuse value" line.long 0x530 "BSEC_FVR332,BSEC fuse word 332 value register" hexmask.long 0x530 0.--31. 1. "FV,fuse value" line.long 0x534 "BSEC_FVR333,BSEC fuse word 333 value register" hexmask.long 0x534 0.--31. 1. "FV,fuse value" line.long 0x538 "BSEC_FVR334,BSEC fuse word 334 value register" hexmask.long 0x538 0.--31. 1. "FV,fuse value" line.long 0x53C "BSEC_FVR335,BSEC fuse word 335 value register" hexmask.long 0x53C 0.--31. 1. "FV,fuse value" line.long 0x540 "BSEC_FVR336,BSEC fuse word 336 value register" hexmask.long 0x540 0.--31. 1. "FV,fuse value" line.long 0x544 "BSEC_FVR337,BSEC fuse word 337 value register" hexmask.long 0x544 0.--31. 1. "FV,fuse value" line.long 0x548 "BSEC_FVR338,BSEC fuse word 338 value register" hexmask.long 0x548 0.--31. 1. "FV,fuse value" line.long 0x54C "BSEC_FVR339,BSEC fuse word 339 value register" hexmask.long 0x54C 0.--31. 1. "FV,fuse value" line.long 0x550 "BSEC_FVR340,BSEC fuse word 340 value register" hexmask.long 0x550 0.--31. 1. "FV,fuse value" line.long 0x554 "BSEC_FVR341,BSEC fuse word 341 value register" hexmask.long 0x554 0.--31. 1. "FV,fuse value" line.long 0x558 "BSEC_FVR342,BSEC fuse word 342 value register" hexmask.long 0x558 0.--31. 1. "FV,fuse value" line.long 0x55C "BSEC_FVR343,BSEC fuse word 343 value register" hexmask.long 0x55C 0.--31. 1. "FV,fuse value" line.long 0x560 "BSEC_FVR344,BSEC fuse word 344 value register" hexmask.long 0x560 0.--31. 1. "FV,fuse value" line.long 0x564 "BSEC_FVR345,BSEC fuse word 345 value register" hexmask.long 0x564 0.--31. 1. "FV,fuse value" line.long 0x568 "BSEC_FVR346,BSEC fuse word 346 value register" hexmask.long 0x568 0.--31. 1. "FV,fuse value" line.long 0x56C "BSEC_FVR347,BSEC fuse word 347 value register" hexmask.long 0x56C 0.--31. 1. "FV,fuse value" line.long 0x570 "BSEC_FVR348,BSEC fuse word 348 value register" hexmask.long 0x570 0.--31. 1. "FV,fuse value" line.long 0x574 "BSEC_FVR349,BSEC fuse word 349 value register" hexmask.long 0x574 0.--31. 1. "FV,fuse value" line.long 0x578 "BSEC_FVR350,BSEC fuse word 350 value register" hexmask.long 0x578 0.--31. 1. "FV,fuse value" line.long 0x57C "BSEC_FVR351,BSEC fuse word 351 value register" hexmask.long 0x57C 0.--31. 1. "FV,fuse value" line.long 0x580 "BSEC_FVR352,BSEC fuse word 352 value register" hexmask.long 0x580 0.--31. 1. "FV,fuse value" line.long 0x584 "BSEC_FVR353,BSEC fuse word 353 value register" hexmask.long 0x584 0.--31. 1. "FV,fuse value" line.long 0x588 "BSEC_FVR354,BSEC fuse word 354 value register" hexmask.long 0x588 0.--31. 1. "FV,fuse value" line.long 0x58C "BSEC_FVR355,BSEC fuse word 355 value register" hexmask.long 0x58C 0.--31. 1. "FV,fuse value" line.long 0x590 "BSEC_FVR356,BSEC fuse word 356 value register" hexmask.long 0x590 0.--31. 1. "FV,fuse value" line.long 0x594 "BSEC_FVR357,BSEC fuse word 357 value register" hexmask.long 0x594 0.--31. 1. "FV,fuse value" line.long 0x598 "BSEC_FVR358,BSEC fuse word 358 value register" hexmask.long 0x598 0.--31. 1. "FV,fuse value" line.long 0x59C "BSEC_FVR359,BSEC fuse word 359 value register" hexmask.long 0x59C 0.--31. 1. "FV,fuse value" line.long 0x5A0 "BSEC_FVR360,BSEC fuse word 360 value register" hexmask.long 0x5A0 0.--31. 1. "FV,fuse value" line.long 0x5A4 "BSEC_FVR361,BSEC fuse word 361 value register" hexmask.long 0x5A4 0.--31. 1. "FV,fuse value" line.long 0x5A8 "BSEC_FVR362,BSEC fuse word 362 value register" hexmask.long 0x5A8 0.--31. 1. "FV,fuse value" line.long 0x5AC "BSEC_FVR363,BSEC fuse word 363 value register" hexmask.long 0x5AC 0.--31. 1. "FV,fuse value" line.long 0x5B0 "BSEC_FVR364,BSEC fuse word 364 value register" hexmask.long 0x5B0 0.--31. 1. "FV,fuse value" line.long 0x5B4 "BSEC_FVR365,BSEC fuse word 365 value register" hexmask.long 0x5B4 0.--31. 1. "FV,fuse value" line.long 0x5B8 "BSEC_FVR366,BSEC fuse word 366 value register" hexmask.long 0x5B8 0.--31. 1. "FV,fuse value" line.long 0x5BC "BSEC_FVR367,BSEC fuse word 367 value register" hexmask.long 0x5BC 0.--31. 1. "FV,fuse value" line.long 0x5C0 "BSEC_FVR368,BSEC fuse word 368 value register" hexmask.long 0x5C0 0.--31. 1. "FV,fuse value" line.long 0x5C4 "BSEC_FVR369,BSEC fuse word 369 value register" hexmask.long 0x5C4 0.--31. 1. "FV,fuse value" line.long 0x5C8 "BSEC_FVR370,BSEC fuse word 370 value register" hexmask.long 0x5C8 0.--31. 1. "FV,fuse value" line.long 0x5CC "BSEC_FVR371,BSEC fuse word 371 value register" hexmask.long 0x5CC 0.--31. 1. "FV,fuse value" line.long 0x5D0 "BSEC_FVR372,BSEC fuse word 372 value register" hexmask.long 0x5D0 0.--31. 1. "FV,fuse value" line.long 0x5D4 "BSEC_FVR373,BSEC fuse word 373 value register" hexmask.long 0x5D4 0.--31. 1. "FV,fuse value" line.long 0x5D8 "BSEC_FVR374,BSEC fuse word 374 value register" hexmask.long 0x5D8 0.--31. 1. "FV,fuse value" line.long 0x5DC "BSEC_FVR375,BSEC fuse word 375 value register" hexmask.long 0x5DC 0.--31. 1. "FV,fuse value" group.long 0x800++0x2F line.long 0x0 "BSEC_SPLOCK0,BSEC sticky programming lock register 0" bitfld.long 0x0 31. "SPLOCK31,Sticky programming lock for word 31" "0: Fuse word 31 can be burnt in fuse memory array,1: Attempt to program fuse word 31 in OTP memory.." bitfld.long 0x0 30. "SPLOCK30,Sticky programming lock for word 30" "0: Fuse word 30 can be burnt in fuse memory array,1: Attempt to program fuse word 30 in OTP memory.." newline bitfld.long 0x0 29. "SPLOCK29,Sticky programming lock for word 29" "0: Fuse word 29 can be burnt in fuse memory array,1: Attempt to program fuse word 29 in OTP memory.." bitfld.long 0x0 28. "SPLOCK28,Sticky programming lock for word 28" "0: Fuse word 28 can be burnt in fuse memory array,1: Attempt to program fuse word 28 in OTP memory.." newline bitfld.long 0x0 27. "SPLOCK27,Sticky programming lock for word 27" "0: Fuse word 27 can be burnt in fuse memory array,1: Attempt to program fuse word 27 in OTP memory.." bitfld.long 0x0 26. "SPLOCK26,Sticky programming lock for word 26" "0: Fuse word 26 can be burnt in fuse memory array,1: Attempt to program fuse word 26 in OTP memory.." newline bitfld.long 0x0 25. "SPLOCK25,Sticky programming lock for word 25" "0: Fuse word 25 can be burnt in fuse memory array,1: Attempt to program fuse word 25 in OTP memory.." bitfld.long 0x0 24. "SPLOCK24,Sticky programming lock for word 24" "0: Fuse word 24 can be burnt in fuse memory array,1: Attempt to program fuse word 24 in OTP memory.." newline bitfld.long 0x0 23. "SPLOCK23,Sticky programming lock for word 23" "0: Fuse word 23 can be burnt in fuse memory array,1: Attempt to program fuse word 23 in OTP memory.." bitfld.long 0x0 22. "SPLOCK22,Sticky programming lock for word 22" "0: Fuse word 22 can be burnt in fuse memory array,1: Attempt to program fuse word 22 in OTP memory.." newline bitfld.long 0x0 21. "SPLOCK21,Sticky programming lock for word 21" "0: Fuse word 21 can be burnt in fuse memory array,1: Attempt to program fuse word 21 in OTP memory.." bitfld.long 0x0 20. "SPLOCK20,Sticky programming lock for word 20" "0: Fuse word 20 can be burnt in fuse memory array,1: Attempt to program fuse word 20 in OTP memory.." newline bitfld.long 0x0 19. "SPLOCK19,Sticky programming lock for word 19" "0: Fuse word 19 can be burnt in fuse memory array,1: Attempt to program fuse word 19 in OTP memory.." bitfld.long 0x0 18. "SPLOCK18,Sticky programming lock for word 18" "0: Fuse word 18 can be burnt in fuse memory array,1: Attempt to program fuse word 18 in OTP memory.." newline bitfld.long 0x0 17. "SPLOCK17,Sticky programming lock for word 17" "0: Fuse word 17 can be burnt in fuse memory array,1: Attempt to program fuse word 17 in OTP memory.." bitfld.long 0x0 16. "SPLOCK16,Sticky programming lock for word 16" "0: Fuse word 16 can be burnt in fuse memory array,1: Attempt to program fuse word 16 in OTP memory.." newline bitfld.long 0x0 15. "SPLOCK15,Sticky programming lock for word 15" "0: Fuse word 15 can be burnt in fuse memory array,1: Attempt to program fuse word 15 in OTP memory.." bitfld.long 0x0 14. "SPLOCK14,Sticky programming lock for word 14" "0: Fuse word 14 can be burnt in fuse memory array,1: Attempt to program fuse word 14 in OTP memory.." newline bitfld.long 0x0 13. "SPLOCK13,Sticky programming lock for word 13" "0: Fuse word 13 can be burnt in fuse memory array,1: Attempt to program fuse word 13 in OTP memory.." bitfld.long 0x0 12. "SPLOCK12,Sticky programming lock for word 12" "0: Fuse word 12 can be burnt in fuse memory array,1: Attempt to program fuse word 12 in OTP memory.." newline bitfld.long 0x0 11. "SPLOCK11,Sticky programming lock for word 11" "0: Fuse word 11 can be burnt in fuse memory array,1: Attempt to program fuse word 11 in OTP memory.." bitfld.long 0x0 10. "SPLOCK10,Sticky programming lock for word 10" "0: Fuse word 10 can be burnt in fuse memory array,1: Attempt to program fuse word 10 in OTP memory.." newline bitfld.long 0x0 9. "SPLOCK9,Sticky programming lock for word 9" "0: Fuse word 9 can be burnt in fuse memory array,1: Attempt to program fuse word 9 in OTP memory.." bitfld.long 0x0 8. "SPLOCK8,Sticky programming lock for word 8" "0: Fuse word 8 can be burnt in fuse memory array,1: Attempt to program fuse word 8 in OTP memory.." newline bitfld.long 0x0 7. "SPLOCK7,Sticky programming lock for word 7" "0: Fuse word 7 can be burnt in fuse memory array,1: Attempt to program fuse word 7 in OTP memory.." bitfld.long 0x0 6. "SPLOCK6,Sticky programming lock for word 6" "0: Fuse word 6 can be burnt in fuse memory array,1: Attempt to program fuse word 6 in OTP memory.." newline bitfld.long 0x0 5. "SPLOCK5,Sticky programming lock for word 5" "0: Fuse word 5 can be burnt in fuse memory array,1: Attempt to program fuse word 5 in OTP memory.." bitfld.long 0x0 4. "SPLOCK4,Sticky programming lock for word 4" "0: Fuse word 4 can be burnt in fuse memory array,1: Attempt to program fuse word 4 in OTP memory.." newline bitfld.long 0x0 3. "SPLOCK3,Sticky programming lock for word 3" "0: Fuse word 3 can be burnt in fuse memory array,1: Attempt to program fuse word 3 in OTP memory.." bitfld.long 0x0 2. "SPLOCK2,Sticky programming lock for word 2" "0: Fuse word 2 can be burnt in fuse memory array,1: Attempt to program fuse word 2 in OTP memory.." newline bitfld.long 0x0 1. "SPLOCK1,Sticky programming lock for word 1" "0: Fuse word 1 can be burnt in fuse memory array,1: Attempt to program fuse word 1 in OTP memory.." bitfld.long 0x0 0. "SPLOCK0,Sticky programming lock for word 0" "0: Fuse word 0 can be burnt in fuse memory array,1: Attempt to program fuse word 0 in OTP memory.." line.long 0x4 "BSEC_SPLOCK1,BSEC sticky programming lock register 1" bitfld.long 0x4 31. "SPLOCK63,Sticky programming lock for word 63" "0: Fuse word 63 can be burnt in fuse memory array,1: Attempt to program fuse word 63 in OTP memory.." bitfld.long 0x4 30. "SPLOCK62,Sticky programming lock for word 62" "0: Fuse word 62 can be burnt in fuse memory array,1: Attempt to program fuse word 62 in OTP memory.." newline bitfld.long 0x4 29. "SPLOCK61,Sticky programming lock for word 61" "0: Fuse word 61 can be burnt in fuse memory array,1: Attempt to program fuse word 61 in OTP memory.." bitfld.long 0x4 28. "SPLOCK60,Sticky programming lock for word 60" "0: Fuse word 60 can be burnt in fuse memory array,1: Attempt to program fuse word 60 in OTP memory.." newline bitfld.long 0x4 27. "SPLOCK59,Sticky programming lock for word 59" "0: Fuse word 59 can be burnt in fuse memory array,1: Attempt to program fuse word 59 in OTP memory.." bitfld.long 0x4 26. "SPLOCK58,Sticky programming lock for word 58" "0: Fuse word 58 can be burnt in fuse memory array,1: Attempt to program fuse word 58 in OTP memory.." newline bitfld.long 0x4 25. "SPLOCK57,Sticky programming lock for word 57" "0: Fuse word 57 can be burnt in fuse memory array,1: Attempt to program fuse word 57 in OTP memory.." bitfld.long 0x4 24. "SPLOCK56,Sticky programming lock for word 56" "0: Fuse word 56 can be burnt in fuse memory array,1: Attempt to program fuse word 56 in OTP memory.." newline bitfld.long 0x4 23. "SPLOCK55,Sticky programming lock for word 55" "0: Fuse word 55 can be burnt in fuse memory array,1: Attempt to program fuse word 55 in OTP memory.." bitfld.long 0x4 22. "SPLOCK54,Sticky programming lock for word 54" "0: Fuse word 54 can be burnt in fuse memory array,1: Attempt to program fuse word 54 in OTP memory.." newline bitfld.long 0x4 21. "SPLOCK53,Sticky programming lock for word 53" "0: Fuse word 53 can be burnt in fuse memory array,1: Attempt to program fuse word 53 in OTP memory.." bitfld.long 0x4 20. "SPLOCK52,Sticky programming lock for word 52" "0: Fuse word 52 can be burnt in fuse memory array,1: Attempt to program fuse word 52 in OTP memory.." newline bitfld.long 0x4 19. "SPLOCK51,Sticky programming lock for word 51" "0: Fuse word 51 can be burnt in fuse memory array,1: Attempt to program fuse word 51 in OTP memory.." bitfld.long 0x4 18. "SPLOCK50,Sticky programming lock for word 50" "0: Fuse word 50 can be burnt in fuse memory array,1: Attempt to program fuse word 50 in OTP memory.." newline bitfld.long 0x4 17. "SPLOCK49,Sticky programming lock for word 49" "0: Fuse word 49 can be burnt in fuse memory array,1: Attempt to program fuse word 49 in OTP memory.." bitfld.long 0x4 16. "SPLOCK48,Sticky programming lock for word 48" "0: Fuse word 48 can be burnt in fuse memory array,1: Attempt to program fuse word 48 in OTP memory.." newline bitfld.long 0x4 15. "SPLOCK47,Sticky programming lock for word 47" "0: Fuse word 47 can be burnt in fuse memory array,1: Attempt to program fuse word 47 in OTP memory.." bitfld.long 0x4 14. "SPLOCK46,Sticky programming lock for word 46" "0: Fuse word 46 can be burnt in fuse memory array,1: Attempt to program fuse word 46 in OTP memory.." newline bitfld.long 0x4 13. "SPLOCK45,Sticky programming lock for word 45" "0: Fuse word 45 can be burnt in fuse memory array,1: Attempt to program fuse word 45 in OTP memory.." bitfld.long 0x4 12. "SPLOCK44,Sticky programming lock for word 44" "0: Fuse word 44 can be burnt in fuse memory array,1: Attempt to program fuse word 44 in OTP memory.." newline bitfld.long 0x4 11. "SPLOCK43,Sticky programming lock for word 43" "0: Fuse word 43 can be burnt in fuse memory array,1: Attempt to program fuse word 43 in OTP memory.." bitfld.long 0x4 10. "SPLOCK42,Sticky programming lock for word 42" "0: Fuse word 42 can be burnt in fuse memory array,1: Attempt to program fuse word 42 in OTP memory.." newline bitfld.long 0x4 9. "SPLOCK41,Sticky programming lock for word 41" "0: Fuse word 41 can be burnt in fuse memory array,1: Attempt to program fuse word 41 in OTP memory.." bitfld.long 0x4 8. "SPLOCK40,Sticky programming lock for word 40" "0: Fuse word 40 can be burnt in fuse memory array,1: Attempt to program fuse word 40 in OTP memory.." newline bitfld.long 0x4 7. "SPLOCK39,Sticky programming lock for word 39" "0: Fuse word 39 can be burnt in fuse memory array,1: Attempt to program fuse word 39 in OTP memory.." bitfld.long 0x4 6. "SPLOCK38,Sticky programming lock for word 38" "0: Fuse word 38 can be burnt in fuse memory array,1: Attempt to program fuse word 38 in OTP memory.." newline bitfld.long 0x4 5. "SPLOCK37,Sticky programming lock for word 37" "0: Fuse word 37 can be burnt in fuse memory array,1: Attempt to program fuse word 37 in OTP memory.." bitfld.long 0x4 4. "SPLOCK36,Sticky programming lock for word 36" "0: Fuse word 36 can be burnt in fuse memory array,1: Attempt to program fuse word 36 in OTP memory.." newline bitfld.long 0x4 3. "SPLOCK35,Sticky programming lock for word 35" "0: Fuse word 35 can be burnt in fuse memory array,1: Attempt to program fuse word 35 in OTP memory.." bitfld.long 0x4 2. "SPLOCK34,Sticky programming lock for word 34" "0: Fuse word 34 can be burnt in fuse memory array,1: Attempt to program fuse word 34 in OTP memory.." newline bitfld.long 0x4 1. "SPLOCK33,Sticky programming lock for word 33" "0: Fuse word 33 can be burnt in fuse memory array,1: Attempt to program fuse word 33 in OTP memory.." bitfld.long 0x4 0. "SPLOCK32,Sticky programming lock for word 32" "0: Fuse word 32 can be burnt in fuse memory array,1: Attempt to program fuse word 32 in OTP memory.." line.long 0x8 "BSEC_SPLOCK2,BSEC sticky programming lock register 2" bitfld.long 0x8 31. "SPLOCK95,Sticky programming lock for word 95" "0: Fuse word 95 can be burnt in fuse memory array,1: Attempt to program fuse word 95 in OTP memory.." bitfld.long 0x8 30. "SPLOCK94,Sticky programming lock for word 94" "0: Fuse word 94 can be burnt in fuse memory array,1: Attempt to program fuse word 94 in OTP memory.." newline bitfld.long 0x8 29. "SPLOCK93,Sticky programming lock for word 93" "0: Fuse word 93 can be burnt in fuse memory array,1: Attempt to program fuse word 93 in OTP memory.." bitfld.long 0x8 28. "SPLOCK92,Sticky programming lock for word 92" "0: Fuse word 92 can be burnt in fuse memory array,1: Attempt to program fuse word 92 in OTP memory.." newline bitfld.long 0x8 27. "SPLOCK91,Sticky programming lock for word 91" "0: Fuse word 91 can be burnt in fuse memory array,1: Attempt to program fuse word 91 in OTP memory.." bitfld.long 0x8 26. "SPLOCK90,Sticky programming lock for word 90" "0: Fuse word 90 can be burnt in fuse memory array,1: Attempt to program fuse word 90 in OTP memory.." newline bitfld.long 0x8 25. "SPLOCK89,Sticky programming lock for word 89" "0: Fuse word 89 can be burnt in fuse memory array,1: Attempt to program fuse word 89 in OTP memory.." bitfld.long 0x8 24. "SPLOCK88,Sticky programming lock for word 88" "0: Fuse word 88 can be burnt in fuse memory array,1: Attempt to program fuse word 88 in OTP memory.." newline bitfld.long 0x8 23. "SPLOCK87,Sticky programming lock for word 87" "0: Fuse word 87 can be burnt in fuse memory array,1: Attempt to program fuse word 87 in OTP memory.." bitfld.long 0x8 22. "SPLOCK86,Sticky programming lock for word 86" "0: Fuse word 86 can be burnt in fuse memory array,1: Attempt to program fuse word 86 in OTP memory.." newline bitfld.long 0x8 21. "SPLOCK85,Sticky programming lock for word 85" "0: Fuse word 85 can be burnt in fuse memory array,1: Attempt to program fuse word 85 in OTP memory.." bitfld.long 0x8 20. "SPLOCK84,Sticky programming lock for word 84" "0: Fuse word 84 can be burnt in fuse memory array,1: Attempt to program fuse word 84 in OTP memory.." newline bitfld.long 0x8 19. "SPLOCK83,Sticky programming lock for word 83" "0: Fuse word 83 can be burnt in fuse memory array,1: Attempt to program fuse word 83 in OTP memory.." bitfld.long 0x8 18. "SPLOCK82,Sticky programming lock for word 82" "0: Fuse word 82 can be burnt in fuse memory array,1: Attempt to program fuse word 82 in OTP memory.." newline bitfld.long 0x8 17. "SPLOCK81,Sticky programming lock for word 81" "0: Fuse word 81 can be burnt in fuse memory array,1: Attempt to program fuse word 81 in OTP memory.." bitfld.long 0x8 16. "SPLOCK80,Sticky programming lock for word 80" "0: Fuse word 80 can be burnt in fuse memory array,1: Attempt to program fuse word 80 in OTP memory.." newline bitfld.long 0x8 15. "SPLOCK79,Sticky programming lock for word 79" "0: Fuse word 79 can be burnt in fuse memory array,1: Attempt to program fuse word 79 in OTP memory.." bitfld.long 0x8 14. "SPLOCK78,Sticky programming lock for word 78" "0: Fuse word 78 can be burnt in fuse memory array,1: Attempt to program fuse word 78 in OTP memory.." newline bitfld.long 0x8 13. "SPLOCK77,Sticky programming lock for word 77" "0: Fuse word 77 can be burnt in fuse memory array,1: Attempt to program fuse word 77 in OTP memory.." bitfld.long 0x8 12. "SPLOCK76,Sticky programming lock for word 76" "0: Fuse word 76 can be burnt in fuse memory array,1: Attempt to program fuse word 76 in OTP memory.." newline bitfld.long 0x8 11. "SPLOCK75,Sticky programming lock for word 75" "0: Fuse word 75 can be burnt in fuse memory array,1: Attempt to program fuse word 75 in OTP memory.." bitfld.long 0x8 10. "SPLOCK74,Sticky programming lock for word 74" "0: Fuse word 74 can be burnt in fuse memory array,1: Attempt to program fuse word 74 in OTP memory.." newline bitfld.long 0x8 9. "SPLOCK73,Sticky programming lock for word 73" "0: Fuse word 73 can be burnt in fuse memory array,1: Attempt to program fuse word 73 in OTP memory.." bitfld.long 0x8 8. "SPLOCK72,Sticky programming lock for word 72" "0: Fuse word 72 can be burnt in fuse memory array,1: Attempt to program fuse word 72 in OTP memory.." newline bitfld.long 0x8 7. "SPLOCK71,Sticky programming lock for word 71" "0: Fuse word 71 can be burnt in fuse memory array,1: Attempt to program fuse word 71 in OTP memory.." bitfld.long 0x8 6. "SPLOCK70,Sticky programming lock for word 70" "0: Fuse word 70 can be burnt in fuse memory array,1: Attempt to program fuse word 70 in OTP memory.." newline bitfld.long 0x8 5. "SPLOCK69,Sticky programming lock for word 69" "0: Fuse word 69 can be burnt in fuse memory array,1: Attempt to program fuse word 69 in OTP memory.." bitfld.long 0x8 4. "SPLOCK68,Sticky programming lock for word 68" "0: Fuse word 68 can be burnt in fuse memory array,1: Attempt to program fuse word 68 in OTP memory.." newline bitfld.long 0x8 3. "SPLOCK67,Sticky programming lock for word 67" "0: Fuse word 67 can be burnt in fuse memory array,1: Attempt to program fuse word 67 in OTP memory.." bitfld.long 0x8 2. "SPLOCK66,Sticky programming lock for word 66" "0: Fuse word 66 can be burnt in fuse memory array,1: Attempt to program fuse word 66 in OTP memory.." newline bitfld.long 0x8 1. "SPLOCK65,Sticky programming lock for word 65" "0: Fuse word 65 can be burnt in fuse memory array,1: Attempt to program fuse word 65 in OTP memory.." bitfld.long 0x8 0. "SPLOCK64,Sticky programming lock for word 64" "0: Fuse word 64 can be burnt in fuse memory array,1: Attempt to program fuse word 64 in OTP memory.." line.long 0xC "BSEC_SPLOCK3,BSEC sticky programming lock register 3" bitfld.long 0xC 31. "SPLOCK127,Sticky programming lock for word 127" "0: Fuse word 127 can be burnt in fuse memory array,1: Attempt to program fuse word 127 in OTP memory.." bitfld.long 0xC 30. "SPLOCK126,Sticky programming lock for word 126" "0: Fuse word 126 can be burnt in fuse memory array,1: Attempt to program fuse word 126 in OTP memory.." newline bitfld.long 0xC 29. "SPLOCK125,Sticky programming lock for word 125" "0: Fuse word 125 can be burnt in fuse memory array,1: Attempt to program fuse word 125 in OTP memory.." bitfld.long 0xC 28. "SPLOCK124,Sticky programming lock for word 124" "0: Fuse word 124 can be burnt in fuse memory array,1: Attempt to program fuse word 124 in OTP memory.." newline bitfld.long 0xC 27. "SPLOCK123,Sticky programming lock for word 123" "0: Fuse word 123 can be burnt in fuse memory array,1: Attempt to program fuse word 123 in OTP memory.." bitfld.long 0xC 26. "SPLOCK122,Sticky programming lock for word 122" "0: Fuse word 122 can be burnt in fuse memory array,1: Attempt to program fuse word 122 in OTP memory.." newline bitfld.long 0xC 25. "SPLOCK121,Sticky programming lock for word 121" "0: Fuse word 121 can be burnt in fuse memory array,1: Attempt to program fuse word 121 in OTP memory.." bitfld.long 0xC 24. "SPLOCK120,Sticky programming lock for word 120" "0: Fuse word 120 can be burnt in fuse memory array,1: Attempt to program fuse word 120 in OTP memory.." newline bitfld.long 0xC 23. "SPLOCK119,Sticky programming lock for word 119" "0: Fuse word 119 can be burnt in fuse memory array,1: Attempt to program fuse word 119 in OTP memory.." bitfld.long 0xC 22. "SPLOCK118,Sticky programming lock for word 118" "0: Fuse word 118 can be burnt in fuse memory array,1: Attempt to program fuse word 118 in OTP memory.." newline bitfld.long 0xC 21. "SPLOCK117,Sticky programming lock for word 117" "0: Fuse word 117 can be burnt in fuse memory array,1: Attempt to program fuse word 117 in OTP memory.." bitfld.long 0xC 20. "SPLOCK116,Sticky programming lock for word 116" "0: Fuse word 116 can be burnt in fuse memory array,1: Attempt to program fuse word 116 in OTP memory.." newline bitfld.long 0xC 19. "SPLOCK115,Sticky programming lock for word 115" "0: Fuse word 115 can be burnt in fuse memory array,1: Attempt to program fuse word 115 in OTP memory.." bitfld.long 0xC 18. "SPLOCK114,Sticky programming lock for word 114" "0: Fuse word 114 can be burnt in fuse memory array,1: Attempt to program fuse word 114 in OTP memory.." newline bitfld.long 0xC 17. "SPLOCK113,Sticky programming lock for word 113" "0: Fuse word 113 can be burnt in fuse memory array,1: Attempt to program fuse word 113 in OTP memory.." bitfld.long 0xC 16. "SPLOCK112,Sticky programming lock for word 112" "0: Fuse word 112 can be burnt in fuse memory array,1: Attempt to program fuse word 112 in OTP memory.." newline bitfld.long 0xC 15. "SPLOCK111,Sticky programming lock for word 111" "0: Fuse word 111 can be burnt in fuse memory array,1: Attempt to program fuse word 111 in OTP memory.." bitfld.long 0xC 14. "SPLOCK110,Sticky programming lock for word 110" "0: Fuse word 110 can be burnt in fuse memory array,1: Attempt to program fuse word 110 in OTP memory.." newline bitfld.long 0xC 13. "SPLOCK109,Sticky programming lock for word 109" "0: Fuse word 109 can be burnt in fuse memory array,1: Attempt to program fuse word 109 in OTP memory.." bitfld.long 0xC 12. "SPLOCK108,Sticky programming lock for word 108" "0: Fuse word 108 can be burnt in fuse memory array,1: Attempt to program fuse word 108 in OTP memory.." newline bitfld.long 0xC 11. "SPLOCK107,Sticky programming lock for word 107" "0: Fuse word 107 can be burnt in fuse memory array,1: Attempt to program fuse word 107 in OTP memory.." bitfld.long 0xC 10. "SPLOCK106,Sticky programming lock for word 106" "0: Fuse word 106 can be burnt in fuse memory array,1: Attempt to program fuse word 106 in OTP memory.." newline bitfld.long 0xC 9. "SPLOCK105,Sticky programming lock for word 105" "0: Fuse word 105 can be burnt in fuse memory array,1: Attempt to program fuse word 105 in OTP memory.." bitfld.long 0xC 8. "SPLOCK104,Sticky programming lock for word 104" "0: Fuse word 104 can be burnt in fuse memory array,1: Attempt to program fuse word 104 in OTP memory.." newline bitfld.long 0xC 7. "SPLOCK103,Sticky programming lock for word 103" "0: Fuse word 103 can be burnt in fuse memory array,1: Attempt to program fuse word 103 in OTP memory.." bitfld.long 0xC 6. "SPLOCK102,Sticky programming lock for word 102" "0: Fuse word 102 can be burnt in fuse memory array,1: Attempt to program fuse word 102 in OTP memory.." newline bitfld.long 0xC 5. "SPLOCK101,Sticky programming lock for word 101" "0: Fuse word 101 can be burnt in fuse memory array,1: Attempt to program fuse word 101 in OTP memory.." bitfld.long 0xC 4. "SPLOCK100,Sticky programming lock for word 100" "0: Fuse word 100 can be burnt in fuse memory array,1: Attempt to program fuse word 100 in OTP memory.." newline bitfld.long 0xC 3. "SPLOCK99,Sticky programming lock for word 99" "0: Fuse word 99 can be burnt in fuse memory array,1: Attempt to program fuse word 99 in OTP memory.." bitfld.long 0xC 2. "SPLOCK98,Sticky programming lock for word 98" "0: Fuse word 98 can be burnt in fuse memory array,1: Attempt to program fuse word 98 in OTP memory.." newline bitfld.long 0xC 1. "SPLOCK97,Sticky programming lock for word 97" "0: Fuse word 97 can be burnt in fuse memory array,1: Attempt to program fuse word 97 in OTP memory.." bitfld.long 0xC 0. "SPLOCK96,Sticky programming lock for word 96" "0: Fuse word 96 can be burnt in fuse memory array,1: Attempt to program fuse word 96 in OTP memory.." line.long 0x10 "BSEC_SPLOCK4,BSEC sticky programming lock register 4" bitfld.long 0x10 31. "SPLOCK159,Sticky programming lock for word 159" "0: Fuse word 159 can be burnt in fuse memory array,1: Attempt to program fuse word 159 in OTP memory.." bitfld.long 0x10 30. "SPLOCK158,Sticky programming lock for word 158" "0: Fuse word 158 can be burnt in fuse memory array,1: Attempt to program fuse word 158 in OTP memory.." newline bitfld.long 0x10 29. "SPLOCK157,Sticky programming lock for word 157" "0: Fuse word 157 can be burnt in fuse memory array,1: Attempt to program fuse word 157 in OTP memory.." bitfld.long 0x10 28. "SPLOCK156,Sticky programming lock for word 156" "0: Fuse word 156 can be burnt in fuse memory array,1: Attempt to program fuse word 156 in OTP memory.." newline bitfld.long 0x10 27. "SPLOCK155,Sticky programming lock for word 155" "0: Fuse word 155 can be burnt in fuse memory array,1: Attempt to program fuse word 155 in OTP memory.." bitfld.long 0x10 26. "SPLOCK154,Sticky programming lock for word 154" "0: Fuse word 154 can be burnt in fuse memory array,1: Attempt to program fuse word 154 in OTP memory.." newline bitfld.long 0x10 25. "SPLOCK153,Sticky programming lock for word 153" "0: Fuse word 153 can be burnt in fuse memory array,1: Attempt to program fuse word 153 in OTP memory.." bitfld.long 0x10 24. "SPLOCK152,Sticky programming lock for word 152" "0: Fuse word 152 can be burnt in fuse memory array,1: Attempt to program fuse word 152 in OTP memory.." newline bitfld.long 0x10 23. "SPLOCK151,Sticky programming lock for word 151" "0: Fuse word 151 can be burnt in fuse memory array,1: Attempt to program fuse word 151 in OTP memory.." bitfld.long 0x10 22. "SPLOCK150,Sticky programming lock for word 150" "0: Fuse word 150 can be burnt in fuse memory array,1: Attempt to program fuse word 150 in OTP memory.." newline bitfld.long 0x10 21. "SPLOCK149,Sticky programming lock for word 149" "0: Fuse word 149 can be burnt in fuse memory array,1: Attempt to program fuse word 149 in OTP memory.." bitfld.long 0x10 20. "SPLOCK148,Sticky programming lock for word 148" "0: Fuse word 148 can be burnt in fuse memory array,1: Attempt to program fuse word 148 in OTP memory.." newline bitfld.long 0x10 19. "SPLOCK147,Sticky programming lock for word 147" "0: Fuse word 147 can be burnt in fuse memory array,1: Attempt to program fuse word 147 in OTP memory.." bitfld.long 0x10 18. "SPLOCK146,Sticky programming lock for word 146" "0: Fuse word 146 can be burnt in fuse memory array,1: Attempt to program fuse word 146 in OTP memory.." newline bitfld.long 0x10 17. "SPLOCK145,Sticky programming lock for word 145" "0: Fuse word 145 can be burnt in fuse memory array,1: Attempt to program fuse word 145 in OTP memory.." bitfld.long 0x10 16. "SPLOCK144,Sticky programming lock for word 144" "0: Fuse word 144 can be burnt in fuse memory array,1: Attempt to program fuse word 144 in OTP memory.." newline bitfld.long 0x10 15. "SPLOCK143,Sticky programming lock for word 143" "0: Fuse word 143 can be burnt in fuse memory array,1: Attempt to program fuse word 143 in OTP memory.." bitfld.long 0x10 14. "SPLOCK142,Sticky programming lock for word 142" "0: Fuse word 142 can be burnt in fuse memory array,1: Attempt to program fuse word 142 in OTP memory.." newline bitfld.long 0x10 13. "SPLOCK141,Sticky programming lock for word 141" "0: Fuse word 141 can be burnt in fuse memory array,1: Attempt to program fuse word 141 in OTP memory.." bitfld.long 0x10 12. "SPLOCK140,Sticky programming lock for word 140" "0: Fuse word 140 can be burnt in fuse memory array,1: Attempt to program fuse word 140 in OTP memory.." newline bitfld.long 0x10 11. "SPLOCK139,Sticky programming lock for word 139" "0: Fuse word 139 can be burnt in fuse memory array,1: Attempt to program fuse word 139 in OTP memory.." bitfld.long 0x10 10. "SPLOCK138,Sticky programming lock for word 138" "0: Fuse word 138 can be burnt in fuse memory array,1: Attempt to program fuse word 138 in OTP memory.." newline bitfld.long 0x10 9. "SPLOCK137,Sticky programming lock for word 137" "0: Fuse word 137 can be burnt in fuse memory array,1: Attempt to program fuse word 137 in OTP memory.." bitfld.long 0x10 8. "SPLOCK136,Sticky programming lock for word 136" "0: Fuse word 136 can be burnt in fuse memory array,1: Attempt to program fuse word 136 in OTP memory.." newline bitfld.long 0x10 7. "SPLOCK135,Sticky programming lock for word 135" "0: Fuse word 135 can be burnt in fuse memory array,1: Attempt to program fuse word 135 in OTP memory.." bitfld.long 0x10 6. "SPLOCK134,Sticky programming lock for word 134" "0: Fuse word 134 can be burnt in fuse memory array,1: Attempt to program fuse word 134 in OTP memory.." newline bitfld.long 0x10 5. "SPLOCK133,Sticky programming lock for word 133" "0: Fuse word 133 can be burnt in fuse memory array,1: Attempt to program fuse word 133 in OTP memory.." bitfld.long 0x10 4. "SPLOCK132,Sticky programming lock for word 132" "0: Fuse word 132 can be burnt in fuse memory array,1: Attempt to program fuse word 132 in OTP memory.." newline bitfld.long 0x10 3. "SPLOCK131,Sticky programming lock for word 131" "0: Fuse word 131 can be burnt in fuse memory array,1: Attempt to program fuse word 131 in OTP memory.." bitfld.long 0x10 2. "SPLOCK130,Sticky programming lock for word 130" "0: Fuse word 130 can be burnt in fuse memory array,1: Attempt to program fuse word 130 in OTP memory.." newline bitfld.long 0x10 1. "SPLOCK129,Sticky programming lock for word 129" "0: Fuse word 129 can be burnt in fuse memory array,1: Attempt to program fuse word 129 in OTP memory.." bitfld.long 0x10 0. "SPLOCK128,Sticky programming lock for word 128" "0: Fuse word 128 can be burnt in fuse memory array,1: Attempt to program fuse word 128 in OTP memory.." line.long 0x14 "BSEC_SPLOCK5,BSEC sticky programming lock register 5" bitfld.long 0x14 31. "SPLOCK191,Sticky programming lock for word 191" "0: Fuse word 191 can be burnt in fuse memory array,1: Attempt to program fuse word 191 in OTP memory.." bitfld.long 0x14 30. "SPLOCK190,Sticky programming lock for word 190" "0: Fuse word 190 can be burnt in fuse memory array,1: Attempt to program fuse word 190 in OTP memory.." newline bitfld.long 0x14 29. "SPLOCK189,Sticky programming lock for word 189" "0: Fuse word 189 can be burnt in fuse memory array,1: Attempt to program fuse word 189 in OTP memory.." bitfld.long 0x14 28. "SPLOCK188,Sticky programming lock for word 188" "0: Fuse word 188 can be burnt in fuse memory array,1: Attempt to program fuse word 188 in OTP memory.." newline bitfld.long 0x14 27. "SPLOCK187,Sticky programming lock for word 187" "0: Fuse word 187 can be burnt in fuse memory array,1: Attempt to program fuse word 187 in OTP memory.." bitfld.long 0x14 26. "SPLOCK186,Sticky programming lock for word 186" "0: Fuse word 186 can be burnt in fuse memory array,1: Attempt to program fuse word 186 in OTP memory.." newline bitfld.long 0x14 25. "SPLOCK185,Sticky programming lock for word 185" "0: Fuse word 185 can be burnt in fuse memory array,1: Attempt to program fuse word 185 in OTP memory.." bitfld.long 0x14 24. "SPLOCK184,Sticky programming lock for word 184" "0: Fuse word 184 can be burnt in fuse memory array,1: Attempt to program fuse word 184 in OTP memory.." newline bitfld.long 0x14 23. "SPLOCK183,Sticky programming lock for word 183" "0: Fuse word 183 can be burnt in fuse memory array,1: Attempt to program fuse word 183 in OTP memory.." bitfld.long 0x14 22. "SPLOCK182,Sticky programming lock for word 182" "0: Fuse word 182 can be burnt in fuse memory array,1: Attempt to program fuse word 182 in OTP memory.." newline bitfld.long 0x14 21. "SPLOCK181,Sticky programming lock for word 181" "0: Fuse word 181 can be burnt in fuse memory array,1: Attempt to program fuse word 181 in OTP memory.." bitfld.long 0x14 20. "SPLOCK180,Sticky programming lock for word 180" "0: Fuse word 180 can be burnt in fuse memory array,1: Attempt to program fuse word 180 in OTP memory.." newline bitfld.long 0x14 19. "SPLOCK179,Sticky programming lock for word 179" "0: Fuse word 179 can be burnt in fuse memory array,1: Attempt to program fuse word 179 in OTP memory.." bitfld.long 0x14 18. "SPLOCK178,Sticky programming lock for word 178" "0: Fuse word 178 can be burnt in fuse memory array,1: Attempt to program fuse word 178 in OTP memory.." newline bitfld.long 0x14 17. "SPLOCK177,Sticky programming lock for word 177" "0: Fuse word 177 can be burnt in fuse memory array,1: Attempt to program fuse word 177 in OTP memory.." bitfld.long 0x14 16. "SPLOCK176,Sticky programming lock for word 176" "0: Fuse word 176 can be burnt in fuse memory array,1: Attempt to program fuse word 176 in OTP memory.." newline bitfld.long 0x14 15. "SPLOCK175,Sticky programming lock for word 175" "0: Fuse word 175 can be burnt in fuse memory array,1: Attempt to program fuse word 175 in OTP memory.." bitfld.long 0x14 14. "SPLOCK174,Sticky programming lock for word 174" "0: Fuse word 174 can be burnt in fuse memory array,1: Attempt to program fuse word 174 in OTP memory.." newline bitfld.long 0x14 13. "SPLOCK173,Sticky programming lock for word 173" "0: Fuse word 173 can be burnt in fuse memory array,1: Attempt to program fuse word 173 in OTP memory.." bitfld.long 0x14 12. "SPLOCK172,Sticky programming lock for word 172" "0: Fuse word 172 can be burnt in fuse memory array,1: Attempt to program fuse word 172 in OTP memory.." newline bitfld.long 0x14 11. "SPLOCK171,Sticky programming lock for word 171" "0: Fuse word 171 can be burnt in fuse memory array,1: Attempt to program fuse word 171 in OTP memory.." bitfld.long 0x14 10. "SPLOCK170,Sticky programming lock for word 170" "0: Fuse word 170 can be burnt in fuse memory array,1: Attempt to program fuse word 170 in OTP memory.." newline bitfld.long 0x14 9. "SPLOCK169,Sticky programming lock for word 169" "0: Fuse word 169 can be burnt in fuse memory array,1: Attempt to program fuse word 169 in OTP memory.." bitfld.long 0x14 8. "SPLOCK168,Sticky programming lock for word 168" "0: Fuse word 168 can be burnt in fuse memory array,1: Attempt to program fuse word 168 in OTP memory.." newline bitfld.long 0x14 7. "SPLOCK167,Sticky programming lock for word 167" "0: Fuse word 167 can be burnt in fuse memory array,1: Attempt to program fuse word 167 in OTP memory.." bitfld.long 0x14 6. "SPLOCK166,Sticky programming lock for word 166" "0: Fuse word 166 can be burnt in fuse memory array,1: Attempt to program fuse word 166 in OTP memory.." newline bitfld.long 0x14 5. "SPLOCK165,Sticky programming lock for word 165" "0: Fuse word 165 can be burnt in fuse memory array,1: Attempt to program fuse word 165 in OTP memory.." bitfld.long 0x14 4. "SPLOCK164,Sticky programming lock for word 164" "0: Fuse word 164 can be burnt in fuse memory array,1: Attempt to program fuse word 164 in OTP memory.." newline bitfld.long 0x14 3. "SPLOCK163,Sticky programming lock for word 163" "0: Fuse word 163 can be burnt in fuse memory array,1: Attempt to program fuse word 163 in OTP memory.." bitfld.long 0x14 2. "SPLOCK162,Sticky programming lock for word 162" "0: Fuse word 162 can be burnt in fuse memory array,1: Attempt to program fuse word 162 in OTP memory.." newline bitfld.long 0x14 1. "SPLOCK161,Sticky programming lock for word 161" "0: Fuse word 161 can be burnt in fuse memory array,1: Attempt to program fuse word 161 in OTP memory.." bitfld.long 0x14 0. "SPLOCK160,Sticky programming lock for word 160" "0: Fuse word 160 can be burnt in fuse memory array,1: Attempt to program fuse word 160 in OTP memory.." line.long 0x18 "BSEC_SPLOCK6,BSEC sticky programming lock register 6" bitfld.long 0x18 31. "SPLOCK223,Sticky programming lock for word 223" "0: Fuse word 223 can be burnt in fuse memory array,1: Attempt to program fuse word 223 in OTP memory.." bitfld.long 0x18 30. "SPLOCK222,Sticky programming lock for word 222" "0: Fuse word 222 can be burnt in fuse memory array,1: Attempt to program fuse word 222 in OTP memory.." newline bitfld.long 0x18 29. "SPLOCK221,Sticky programming lock for word 221" "0: Fuse word 221 can be burnt in fuse memory array,1: Attempt to program fuse word 221 in OTP memory.." bitfld.long 0x18 28. "SPLOCK220,Sticky programming lock for word 220" "0: Fuse word 220 can be burnt in fuse memory array,1: Attempt to program fuse word 220 in OTP memory.." newline bitfld.long 0x18 27. "SPLOCK219,Sticky programming lock for word 219" "0: Fuse word 219 can be burnt in fuse memory array,1: Attempt to program fuse word 219 in OTP memory.." bitfld.long 0x18 26. "SPLOCK218,Sticky programming lock for word 218" "0: Fuse word 218 can be burnt in fuse memory array,1: Attempt to program fuse word 218 in OTP memory.." newline bitfld.long 0x18 25. "SPLOCK217,Sticky programming lock for word 217" "0: Fuse word 217 can be burnt in fuse memory array,1: Attempt to program fuse word 217 in OTP memory.." bitfld.long 0x18 24. "SPLOCK216,Sticky programming lock for word 216" "0: Fuse word 216 can be burnt in fuse memory array,1: Attempt to program fuse word 216 in OTP memory.." newline bitfld.long 0x18 23. "SPLOCK215,Sticky programming lock for word 215" "0: Fuse word 215 can be burnt in fuse memory array,1: Attempt to program fuse word 215 in OTP memory.." bitfld.long 0x18 22. "SPLOCK214,Sticky programming lock for word 214" "0: Fuse word 214 can be burnt in fuse memory array,1: Attempt to program fuse word 214 in OTP memory.." newline bitfld.long 0x18 21. "SPLOCK213,Sticky programming lock for word 213" "0: Fuse word 213 can be burnt in fuse memory array,1: Attempt to program fuse word 213 in OTP memory.." bitfld.long 0x18 20. "SPLOCK212,Sticky programming lock for word 212" "0: Fuse word 212 can be burnt in fuse memory array,1: Attempt to program fuse word 212 in OTP memory.." newline bitfld.long 0x18 19. "SPLOCK211,Sticky programming lock for word 211" "0: Fuse word 211 can be burnt in fuse memory array,1: Attempt to program fuse word 211 in OTP memory.." bitfld.long 0x18 18. "SPLOCK210,Sticky programming lock for word 210" "0: Fuse word 210 can be burnt in fuse memory array,1: Attempt to program fuse word 210 in OTP memory.." newline bitfld.long 0x18 17. "SPLOCK209,Sticky programming lock for word 209" "0: Fuse word 209 can be burnt in fuse memory array,1: Attempt to program fuse word 209 in OTP memory.." bitfld.long 0x18 16. "SPLOCK208,Sticky programming lock for word 208" "0: Fuse word 208 can be burnt in fuse memory array,1: Attempt to program fuse word 208 in OTP memory.." newline bitfld.long 0x18 15. "SPLOCK207,Sticky programming lock for word 207" "0: Fuse word 207 can be burnt in fuse memory array,1: Attempt to program fuse word 207 in OTP memory.." bitfld.long 0x18 14. "SPLOCK206,Sticky programming lock for word 206" "0: Fuse word 206 can be burnt in fuse memory array,1: Attempt to program fuse word 206 in OTP memory.." newline bitfld.long 0x18 13. "SPLOCK205,Sticky programming lock for word 205" "0: Fuse word 205 can be burnt in fuse memory array,1: Attempt to program fuse word 205 in OTP memory.." bitfld.long 0x18 12. "SPLOCK204,Sticky programming lock for word 204" "0: Fuse word 204 can be burnt in fuse memory array,1: Attempt to program fuse word 204 in OTP memory.." newline bitfld.long 0x18 11. "SPLOCK203,Sticky programming lock for word 203" "0: Fuse word 203 can be burnt in fuse memory array,1: Attempt to program fuse word 203 in OTP memory.." bitfld.long 0x18 10. "SPLOCK202,Sticky programming lock for word 202" "0: Fuse word 202 can be burnt in fuse memory array,1: Attempt to program fuse word 202 in OTP memory.." newline bitfld.long 0x18 9. "SPLOCK201,Sticky programming lock for word 201" "0: Fuse word 201 can be burnt in fuse memory array,1: Attempt to program fuse word 201 in OTP memory.." bitfld.long 0x18 8. "SPLOCK200,Sticky programming lock for word 200" "0: Fuse word 200 can be burnt in fuse memory array,1: Attempt to program fuse word 200 in OTP memory.." newline bitfld.long 0x18 7. "SPLOCK199,Sticky programming lock for word 199" "0: Fuse word 199 can be burnt in fuse memory array,1: Attempt to program fuse word 199 in OTP memory.." bitfld.long 0x18 6. "SPLOCK198,Sticky programming lock for word 198" "0: Fuse word 198 can be burnt in fuse memory array,1: Attempt to program fuse word 198 in OTP memory.." newline bitfld.long 0x18 5. "SPLOCK197,Sticky programming lock for word 197" "0: Fuse word 197 can be burnt in fuse memory array,1: Attempt to program fuse word 197 in OTP memory.." bitfld.long 0x18 4. "SPLOCK196,Sticky programming lock for word 196" "0: Fuse word 196 can be burnt in fuse memory array,1: Attempt to program fuse word 196 in OTP memory.." newline bitfld.long 0x18 3. "SPLOCK195,Sticky programming lock for word 195" "0: Fuse word 195 can be burnt in fuse memory array,1: Attempt to program fuse word 195 in OTP memory.." bitfld.long 0x18 2. "SPLOCK194,Sticky programming lock for word 194" "0: Fuse word 194 can be burnt in fuse memory array,1: Attempt to program fuse word 194 in OTP memory.." newline bitfld.long 0x18 1. "SPLOCK193,Sticky programming lock for word 193" "0: Fuse word 193 can be burnt in fuse memory array,1: Attempt to program fuse word 193 in OTP memory.." bitfld.long 0x18 0. "SPLOCK192,Sticky programming lock for word 192" "0: Fuse word 192 can be burnt in fuse memory array,1: Attempt to program fuse word 192 in OTP memory.." line.long 0x1C "BSEC_SPLOCK7,BSEC sticky programming lock register 7" bitfld.long 0x1C 31. "SPLOCK255,Sticky programming lock for word 255" "0: Fuse word 255 can be burnt in fuse memory array,1: Attempt to program fuse word 255 in OTP memory.." bitfld.long 0x1C 30. "SPLOCK254,Sticky programming lock for word 254" "0: Fuse word 254 can be burnt in fuse memory array,1: Attempt to program fuse word 254 in OTP memory.." newline bitfld.long 0x1C 29. "SPLOCK253,Sticky programming lock for word 253" "0: Fuse word 253 can be burnt in fuse memory array,1: Attempt to program fuse word 253 in OTP memory.." bitfld.long 0x1C 28. "SPLOCK252,Sticky programming lock for word 252" "0: Fuse word 252 can be burnt in fuse memory array,1: Attempt to program fuse word 252 in OTP memory.." newline bitfld.long 0x1C 27. "SPLOCK251,Sticky programming lock for word 251" "0: Fuse word 251 can be burnt in fuse memory array,1: Attempt to program fuse word 251 in OTP memory.." bitfld.long 0x1C 26. "SPLOCK250,Sticky programming lock for word 250" "0: Fuse word 250 can be burnt in fuse memory array,1: Attempt to program fuse word 250 in OTP memory.." newline bitfld.long 0x1C 25. "SPLOCK249,Sticky programming lock for word 249" "0: Fuse word 249 can be burnt in fuse memory array,1: Attempt to program fuse word 249 in OTP memory.." bitfld.long 0x1C 24. "SPLOCK248,Sticky programming lock for word 248" "0: Fuse word 248 can be burnt in fuse memory array,1: Attempt to program fuse word 248 in OTP memory.." newline bitfld.long 0x1C 23. "SPLOCK247,Sticky programming lock for word 247" "0: Fuse word 247 can be burnt in fuse memory array,1: Attempt to program fuse word 247 in OTP memory.." bitfld.long 0x1C 22. "SPLOCK246,Sticky programming lock for word 246" "0: Fuse word 246 can be burnt in fuse memory array,1: Attempt to program fuse word 246 in OTP memory.." newline bitfld.long 0x1C 21. "SPLOCK245,Sticky programming lock for word 245" "0: Fuse word 245 can be burnt in fuse memory array,1: Attempt to program fuse word 245 in OTP memory.." bitfld.long 0x1C 20. "SPLOCK244,Sticky programming lock for word 244" "0: Fuse word 244 can be burnt in fuse memory array,1: Attempt to program fuse word 244 in OTP memory.." newline bitfld.long 0x1C 19. "SPLOCK243,Sticky programming lock for word 243" "0: Fuse word 243 can be burnt in fuse memory array,1: Attempt to program fuse word 243 in OTP memory.." bitfld.long 0x1C 18. "SPLOCK242,Sticky programming lock for word 242" "0: Fuse word 242 can be burnt in fuse memory array,1: Attempt to program fuse word 242 in OTP memory.." newline bitfld.long 0x1C 17. "SPLOCK241,Sticky programming lock for word 241" "0: Fuse word 241 can be burnt in fuse memory array,1: Attempt to program fuse word 241 in OTP memory.." bitfld.long 0x1C 16. "SPLOCK240,Sticky programming lock for word 240" "0: Fuse word 240 can be burnt in fuse memory array,1: Attempt to program fuse word 240 in OTP memory.." newline bitfld.long 0x1C 15. "SPLOCK239,Sticky programming lock for word 239" "0: Fuse word 239 can be burnt in fuse memory array,1: Attempt to program fuse word 239 in OTP memory.." bitfld.long 0x1C 14. "SPLOCK238,Sticky programming lock for word 238" "0: Fuse word 238 can be burnt in fuse memory array,1: Attempt to program fuse word 238 in OTP memory.." newline bitfld.long 0x1C 13. "SPLOCK237,Sticky programming lock for word 237" "0: Fuse word 237 can be burnt in fuse memory array,1: Attempt to program fuse word 237 in OTP memory.." bitfld.long 0x1C 12. "SPLOCK236,Sticky programming lock for word 236" "0: Fuse word 236 can be burnt in fuse memory array,1: Attempt to program fuse word 236 in OTP memory.." newline bitfld.long 0x1C 11. "SPLOCK235,Sticky programming lock for word 235" "0: Fuse word 235 can be burnt in fuse memory array,1: Attempt to program fuse word 235 in OTP memory.." bitfld.long 0x1C 10. "SPLOCK234,Sticky programming lock for word 234" "0: Fuse word 234 can be burnt in fuse memory array,1: Attempt to program fuse word 234 in OTP memory.." newline bitfld.long 0x1C 9. "SPLOCK233,Sticky programming lock for word 233" "0: Fuse word 233 can be burnt in fuse memory array,1: Attempt to program fuse word 233 in OTP memory.." bitfld.long 0x1C 8. "SPLOCK232,Sticky programming lock for word 232" "0: Fuse word 232 can be burnt in fuse memory array,1: Attempt to program fuse word 232 in OTP memory.." newline bitfld.long 0x1C 7. "SPLOCK231,Sticky programming lock for word 231" "0: Fuse word 231 can be burnt in fuse memory array,1: Attempt to program fuse word 231 in OTP memory.." bitfld.long 0x1C 6. "SPLOCK230,Sticky programming lock for word 230" "0: Fuse word 230 can be burnt in fuse memory array,1: Attempt to program fuse word 230 in OTP memory.." newline bitfld.long 0x1C 5. "SPLOCK229,Sticky programming lock for word 229" "0: Fuse word 229 can be burnt in fuse memory array,1: Attempt to program fuse word 229 in OTP memory.." bitfld.long 0x1C 4. "SPLOCK228,Sticky programming lock for word 228" "0: Fuse word 228 can be burnt in fuse memory array,1: Attempt to program fuse word 228 in OTP memory.." newline bitfld.long 0x1C 3. "SPLOCK227,Sticky programming lock for word 227" "0: Fuse word 227 can be burnt in fuse memory array,1: Attempt to program fuse word 227 in OTP memory.." bitfld.long 0x1C 2. "SPLOCK226,Sticky programming lock for word 226" "0: Fuse word 226 can be burnt in fuse memory array,1: Attempt to program fuse word 226 in OTP memory.." newline bitfld.long 0x1C 1. "SPLOCK225,Sticky programming lock for word 225" "0: Fuse word 225 can be burnt in fuse memory array,1: Attempt to program fuse word 225 in OTP memory.." bitfld.long 0x1C 0. "SPLOCK224,Sticky programming lock for word 224" "0: Fuse word 224 can be burnt in fuse memory array,1: Attempt to program fuse word 224 in OTP memory.." line.long 0x20 "BSEC_SPLOCK8,BSEC sticky programming lock register 8" bitfld.long 0x20 31. "SPLOCK287,Sticky programming lock for word 287" "0: Fuse word 287 can be burnt in fuse memory array,1: Attempt to program fuse word 287 in OTP memory.." bitfld.long 0x20 30. "SPLOCK286,Sticky programming lock for word 286" "0: Fuse word 286 can be burnt in fuse memory array,1: Attempt to program fuse word 286 in OTP memory.." newline bitfld.long 0x20 29. "SPLOCK285,Sticky programming lock for word 285" "0: Fuse word 285 can be burnt in fuse memory array,1: Attempt to program fuse word 285 in OTP memory.." bitfld.long 0x20 28. "SPLOCK284,Sticky programming lock for word 284" "0: Fuse word 284 can be burnt in fuse memory array,1: Attempt to program fuse word 284 in OTP memory.." newline bitfld.long 0x20 27. "SPLOCK283,Sticky programming lock for word 283" "0: Fuse word 283 can be burnt in fuse memory array,1: Attempt to program fuse word 283 in OTP memory.." bitfld.long 0x20 26. "SPLOCK282,Sticky programming lock for word 282" "0: Fuse word 282 can be burnt in fuse memory array,1: Attempt to program fuse word 282 in OTP memory.." newline bitfld.long 0x20 25. "SPLOCK281,Sticky programming lock for word 281" "0: Fuse word 281 can be burnt in fuse memory array,1: Attempt to program fuse word 281 in OTP memory.." bitfld.long 0x20 24. "SPLOCK280,Sticky programming lock for word 280" "0: Fuse word 280 can be burnt in fuse memory array,1: Attempt to program fuse word 280 in OTP memory.." newline bitfld.long 0x20 23. "SPLOCK279,Sticky programming lock for word 279" "0: Fuse word 279 can be burnt in fuse memory array,1: Attempt to program fuse word 279 in OTP memory.." bitfld.long 0x20 22. "SPLOCK278,Sticky programming lock for word 278" "0: Fuse word 278 can be burnt in fuse memory array,1: Attempt to program fuse word 278 in OTP memory.." newline bitfld.long 0x20 21. "SPLOCK277,Sticky programming lock for word 277" "0: Fuse word 277 can be burnt in fuse memory array,1: Attempt to program fuse word 277 in OTP memory.." bitfld.long 0x20 20. "SPLOCK276,Sticky programming lock for word 276" "0: Fuse word 276 can be burnt in fuse memory array,1: Attempt to program fuse word 276 in OTP memory.." newline bitfld.long 0x20 19. "SPLOCK275,Sticky programming lock for word 275" "0: Fuse word 275 can be burnt in fuse memory array,1: Attempt to program fuse word 275 in OTP memory.." bitfld.long 0x20 18. "SPLOCK274,Sticky programming lock for word 274" "0: Fuse word 274 can be burnt in fuse memory array,1: Attempt to program fuse word 274 in OTP memory.." newline bitfld.long 0x20 17. "SPLOCK273,Sticky programming lock for word 273" "0: Fuse word 273 can be burnt in fuse memory array,1: Attempt to program fuse word 273 in OTP memory.." bitfld.long 0x20 16. "SPLOCK272,Sticky programming lock for word 272" "0: Fuse word 272 can be burnt in fuse memory array,1: Attempt to program fuse word 272 in OTP memory.." newline bitfld.long 0x20 15. "SPLOCK271,Sticky programming lock for word 271" "0: Fuse word 271 can be burnt in fuse memory array,1: Attempt to program fuse word 271 in OTP memory.." bitfld.long 0x20 14. "SPLOCK270,Sticky programming lock for word 270" "0: Fuse word 270 can be burnt in fuse memory array,1: Attempt to program fuse word 270 in OTP memory.." newline bitfld.long 0x20 13. "SPLOCK269,Sticky programming lock for word 269" "0: Fuse word 269 can be burnt in fuse memory array,1: Attempt to program fuse word 269 in OTP memory.." bitfld.long 0x20 12. "SPLOCK268,Sticky programming lock for word 268" "0: Fuse word 268 can be burnt in fuse memory array,1: Attempt to program fuse word 268 in OTP memory.." newline bitfld.long 0x20 11. "SPLOCK267,Sticky programming lock for word 267" "0: Fuse word 267 can be burnt in fuse memory array,1: Attempt to program fuse word 267 in OTP memory.." bitfld.long 0x20 10. "SPLOCK266,Sticky programming lock for word 266" "0: Fuse word 266 can be burnt in fuse memory array,1: Attempt to program fuse word 266 in OTP memory.." newline bitfld.long 0x20 9. "SPLOCK265,Sticky programming lock for word 265" "0: Fuse word 265 can be burnt in fuse memory array,1: Attempt to program fuse word 265 in OTP memory.." bitfld.long 0x20 8. "SPLOCK264,Sticky programming lock for word 264" "0: Fuse word 264 can be burnt in fuse memory array,1: Attempt to program fuse word 264 in OTP memory.." newline bitfld.long 0x20 7. "SPLOCK263,Sticky programming lock for word 263" "0: Fuse word 263 can be burnt in fuse memory array,1: Attempt to program fuse word 263 in OTP memory.." bitfld.long 0x20 6. "SPLOCK262,Sticky programming lock for word 262" "0: Fuse word 262 can be burnt in fuse memory array,1: Attempt to program fuse word 262 in OTP memory.." newline bitfld.long 0x20 5. "SPLOCK261,Sticky programming lock for word 261" "0: Fuse word 261 can be burnt in fuse memory array,1: Attempt to program fuse word 261 in OTP memory.." bitfld.long 0x20 4. "SPLOCK260,Sticky programming lock for word 260" "0: Fuse word 260 can be burnt in fuse memory array,1: Attempt to program fuse word 260 in OTP memory.." newline bitfld.long 0x20 3. "SPLOCK259,Sticky programming lock for word 259" "0: Fuse word 259 can be burnt in fuse memory array,1: Attempt to program fuse word 259 in OTP memory.." bitfld.long 0x20 2. "SPLOCK258,Sticky programming lock for word 258" "0: Fuse word 258 can be burnt in fuse memory array,1: Attempt to program fuse word 258 in OTP memory.." newline bitfld.long 0x20 1. "SPLOCK257,Sticky programming lock for word 257" "0: Fuse word 257 can be burnt in fuse memory array,1: Attempt to program fuse word 257 in OTP memory.." bitfld.long 0x20 0. "SPLOCK256,Sticky programming lock for word 256" "0: Fuse word 256 can be burnt in fuse memory array,1: Attempt to program fuse word 256 in OTP memory.." line.long 0x24 "BSEC_SPLOCK9,BSEC sticky programming lock register 9" bitfld.long 0x24 31. "SPLOCK319,Sticky programming lock for word 319" "0: Fuse word 319 can be burnt in fuse memory array,1: Attempt to program fuse word 319 in OTP memory.." bitfld.long 0x24 30. "SPLOCK318,Sticky programming lock for word 318" "0: Fuse word 318 can be burnt in fuse memory array,1: Attempt to program fuse word 318 in OTP memory.." newline bitfld.long 0x24 29. "SPLOCK317,Sticky programming lock for word 317" "0: Fuse word 317 can be burnt in fuse memory array,1: Attempt to program fuse word 317 in OTP memory.." bitfld.long 0x24 28. "SPLOCK316,Sticky programming lock for word 316" "0: Fuse word 316 can be burnt in fuse memory array,1: Attempt to program fuse word 316 in OTP memory.." newline bitfld.long 0x24 27. "SPLOCK315,Sticky programming lock for word 315" "0: Fuse word 315 can be burnt in fuse memory array,1: Attempt to program fuse word 315 in OTP memory.." bitfld.long 0x24 26. "SPLOCK314,Sticky programming lock for word 314" "0: Fuse word 314 can be burnt in fuse memory array,1: Attempt to program fuse word 314 in OTP memory.." newline bitfld.long 0x24 25. "SPLOCK313,Sticky programming lock for word 313" "0: Fuse word 313 can be burnt in fuse memory array,1: Attempt to program fuse word 313 in OTP memory.." bitfld.long 0x24 24. "SPLOCK312,Sticky programming lock for word 312" "0: Fuse word 312 can be burnt in fuse memory array,1: Attempt to program fuse word 312 in OTP memory.." newline bitfld.long 0x24 23. "SPLOCK311,Sticky programming lock for word 311" "0: Fuse word 311 can be burnt in fuse memory array,1: Attempt to program fuse word 311 in OTP memory.." bitfld.long 0x24 22. "SPLOCK310,Sticky programming lock for word 310" "0: Fuse word 310 can be burnt in fuse memory array,1: Attempt to program fuse word 310 in OTP memory.." newline bitfld.long 0x24 21. "SPLOCK309,Sticky programming lock for word 309" "0: Fuse word 309 can be burnt in fuse memory array,1: Attempt to program fuse word 309 in OTP memory.." bitfld.long 0x24 20. "SPLOCK308,Sticky programming lock for word 308" "0: Fuse word 308 can be burnt in fuse memory array,1: Attempt to program fuse word 308 in OTP memory.." newline bitfld.long 0x24 19. "SPLOCK307,Sticky programming lock for word 307" "0: Fuse word 307 can be burnt in fuse memory array,1: Attempt to program fuse word 307 in OTP memory.." bitfld.long 0x24 18. "SPLOCK306,Sticky programming lock for word 306" "0: Fuse word 306 can be burnt in fuse memory array,1: Attempt to program fuse word 306 in OTP memory.." newline bitfld.long 0x24 17. "SPLOCK305,Sticky programming lock for word 305" "0: Fuse word 305 can be burnt in fuse memory array,1: Attempt to program fuse word 305 in OTP memory.." bitfld.long 0x24 16. "SPLOCK304,Sticky programming lock for word 304" "0: Fuse word 304 can be burnt in fuse memory array,1: Attempt to program fuse word 304 in OTP memory.." newline bitfld.long 0x24 15. "SPLOCK303,Sticky programming lock for word 303" "0: Fuse word 303 can be burnt in fuse memory array,1: Attempt to program fuse word 303 in OTP memory.." bitfld.long 0x24 14. "SPLOCK302,Sticky programming lock for word 302" "0: Fuse word 302 can be burnt in fuse memory array,1: Attempt to program fuse word 302 in OTP memory.." newline bitfld.long 0x24 13. "SPLOCK301,Sticky programming lock for word 301" "0: Fuse word 301 can be burnt in fuse memory array,1: Attempt to program fuse word 301 in OTP memory.." bitfld.long 0x24 12. "SPLOCK300,Sticky programming lock for word 300" "0: Fuse word 300 can be burnt in fuse memory array,1: Attempt to program fuse word 300 in OTP memory.." newline bitfld.long 0x24 11. "SPLOCK299,Sticky programming lock for word 299" "0: Fuse word 299 can be burnt in fuse memory array,1: Attempt to program fuse word 299 in OTP memory.." bitfld.long 0x24 10. "SPLOCK298,Sticky programming lock for word 298" "0: Fuse word 298 can be burnt in fuse memory array,1: Attempt to program fuse word 298 in OTP memory.." newline bitfld.long 0x24 9. "SPLOCK297,Sticky programming lock for word 297" "0: Fuse word 297 can be burnt in fuse memory array,1: Attempt to program fuse word 297 in OTP memory.." bitfld.long 0x24 8. "SPLOCK296,Sticky programming lock for word 296" "0: Fuse word 296 can be burnt in fuse memory array,1: Attempt to program fuse word 296 in OTP memory.." newline bitfld.long 0x24 7. "SPLOCK295,Sticky programming lock for word 295" "0: Fuse word 295 can be burnt in fuse memory array,1: Attempt to program fuse word 295 in OTP memory.." bitfld.long 0x24 6. "SPLOCK294,Sticky programming lock for word 294" "0: Fuse word 294 can be burnt in fuse memory array,1: Attempt to program fuse word 294 in OTP memory.." newline bitfld.long 0x24 5. "SPLOCK293,Sticky programming lock for word 293" "0: Fuse word 293 can be burnt in fuse memory array,1: Attempt to program fuse word 293 in OTP memory.." bitfld.long 0x24 4. "SPLOCK292,Sticky programming lock for word 292" "0: Fuse word 292 can be burnt in fuse memory array,1: Attempt to program fuse word 292 in OTP memory.." newline bitfld.long 0x24 3. "SPLOCK291,Sticky programming lock for word 291" "0: Fuse word 291 can be burnt in fuse memory array,1: Attempt to program fuse word 291 in OTP memory.." bitfld.long 0x24 2. "SPLOCK290,Sticky programming lock for word 290" "0: Fuse word 290 can be burnt in fuse memory array,1: Attempt to program fuse word 290 in OTP memory.." newline bitfld.long 0x24 1. "SPLOCK289,Sticky programming lock for word 289" "0: Fuse word 289 can be burnt in fuse memory array,1: Attempt to program fuse word 289 in OTP memory.." bitfld.long 0x24 0. "SPLOCK288,Sticky programming lock for word 288" "0: Fuse word 288 can be burnt in fuse memory array,1: Attempt to program fuse word 288 in OTP memory.." line.long 0x28 "BSEC_SPLOCK10,BSEC sticky programming lock register 10" bitfld.long 0x28 31. "SPLOCK351,Sticky programming lock for word 351" "0: Fuse word 351 can be burnt in fuse memory array,1: Attempt to program fuse word 351 in OTP memory.." bitfld.long 0x28 30. "SPLOCK350,Sticky programming lock for word 350" "0: Fuse word 350 can be burnt in fuse memory array,1: Attempt to program fuse word 350 in OTP memory.." newline bitfld.long 0x28 29. "SPLOCK349,Sticky programming lock for word 349" "0: Fuse word 349 can be burnt in fuse memory array,1: Attempt to program fuse word 349 in OTP memory.." bitfld.long 0x28 28. "SPLOCK348,Sticky programming lock for word 348" "0: Fuse word 348 can be burnt in fuse memory array,1: Attempt to program fuse word 348 in OTP memory.." newline bitfld.long 0x28 27. "SPLOCK347,Sticky programming lock for word 347" "0: Fuse word 347 can be burnt in fuse memory array,1: Attempt to program fuse word 347 in OTP memory.." bitfld.long 0x28 26. "SPLOCK346,Sticky programming lock for word 346" "0: Fuse word 346 can be burnt in fuse memory array,1: Attempt to program fuse word 346 in OTP memory.." newline bitfld.long 0x28 25. "SPLOCK345,Sticky programming lock for word 345" "0: Fuse word 345 can be burnt in fuse memory array,1: Attempt to program fuse word 345 in OTP memory.." bitfld.long 0x28 24. "SPLOCK344,Sticky programming lock for word 344" "0: Fuse word 344 can be burnt in fuse memory array,1: Attempt to program fuse word 344 in OTP memory.." newline bitfld.long 0x28 23. "SPLOCK343,Sticky programming lock for word 343" "0: Fuse word 343 can be burnt in fuse memory array,1: Attempt to program fuse word 343 in OTP memory.." bitfld.long 0x28 22. "SPLOCK342,Sticky programming lock for word 342" "0: Fuse word 342 can be burnt in fuse memory array,1: Attempt to program fuse word 342 in OTP memory.." newline bitfld.long 0x28 21. "SPLOCK341,Sticky programming lock for word 341" "0: Fuse word 341 can be burnt in fuse memory array,1: Attempt to program fuse word 341 in OTP memory.." bitfld.long 0x28 20. "SPLOCK340,Sticky programming lock for word 340" "0: Fuse word 340 can be burnt in fuse memory array,1: Attempt to program fuse word 340 in OTP memory.." newline bitfld.long 0x28 19. "SPLOCK339,Sticky programming lock for word 339" "0: Fuse word 339 can be burnt in fuse memory array,1: Attempt to program fuse word 339 in OTP memory.." bitfld.long 0x28 18. "SPLOCK338,Sticky programming lock for word 338" "0: Fuse word 338 can be burnt in fuse memory array,1: Attempt to program fuse word 338 in OTP memory.." newline bitfld.long 0x28 17. "SPLOCK337,Sticky programming lock for word 337" "0: Fuse word 337 can be burnt in fuse memory array,1: Attempt to program fuse word 337 in OTP memory.." bitfld.long 0x28 16. "SPLOCK336,Sticky programming lock for word 336" "0: Fuse word 336 can be burnt in fuse memory array,1: Attempt to program fuse word 336 in OTP memory.." newline bitfld.long 0x28 15. "SPLOCK335,Sticky programming lock for word 335" "0: Fuse word 335 can be burnt in fuse memory array,1: Attempt to program fuse word 335 in OTP memory.." bitfld.long 0x28 14. "SPLOCK334,Sticky programming lock for word 334" "0: Fuse word 334 can be burnt in fuse memory array,1: Attempt to program fuse word 334 in OTP memory.." newline bitfld.long 0x28 13. "SPLOCK333,Sticky programming lock for word 333" "0: Fuse word 333 can be burnt in fuse memory array,1: Attempt to program fuse word 333 in OTP memory.." bitfld.long 0x28 12. "SPLOCK332,Sticky programming lock for word 332" "0: Fuse word 332 can be burnt in fuse memory array,1: Attempt to program fuse word 332 in OTP memory.." newline bitfld.long 0x28 11. "SPLOCK331,Sticky programming lock for word 331" "0: Fuse word 331 can be burnt in fuse memory array,1: Attempt to program fuse word 331 in OTP memory.." bitfld.long 0x28 10. "SPLOCK330,Sticky programming lock for word 330" "0: Fuse word 330 can be burnt in fuse memory array,1: Attempt to program fuse word 330 in OTP memory.." newline bitfld.long 0x28 9. "SPLOCK329,Sticky programming lock for word 329" "0: Fuse word 329 can be burnt in fuse memory array,1: Attempt to program fuse word 329 in OTP memory.." bitfld.long 0x28 8. "SPLOCK328,Sticky programming lock for word 328" "0: Fuse word 328 can be burnt in fuse memory array,1: Attempt to program fuse word 328 in OTP memory.." newline bitfld.long 0x28 7. "SPLOCK327,Sticky programming lock for word 327" "0: Fuse word 327 can be burnt in fuse memory array,1: Attempt to program fuse word 327 in OTP memory.." bitfld.long 0x28 6. "SPLOCK326,Sticky programming lock for word 326" "0: Fuse word 326 can be burnt in fuse memory array,1: Attempt to program fuse word 326 in OTP memory.." newline bitfld.long 0x28 5. "SPLOCK325,Sticky programming lock for word 325" "0: Fuse word 325 can be burnt in fuse memory array,1: Attempt to program fuse word 325 in OTP memory.." bitfld.long 0x28 4. "SPLOCK324,Sticky programming lock for word 324" "0: Fuse word 324 can be burnt in fuse memory array,1: Attempt to program fuse word 324 in OTP memory.." newline bitfld.long 0x28 3. "SPLOCK323,Sticky programming lock for word 323" "0: Fuse word 323 can be burnt in fuse memory array,1: Attempt to program fuse word 323 in OTP memory.." bitfld.long 0x28 2. "SPLOCK322,Sticky programming lock for word 322" "0: Fuse word 322 can be burnt in fuse memory array,1: Attempt to program fuse word 322 in OTP memory.." newline bitfld.long 0x28 1. "SPLOCK321,Sticky programming lock for word 321" "0: Fuse word 321 can be burnt in fuse memory array,1: Attempt to program fuse word 321 in OTP memory.." bitfld.long 0x28 0. "SPLOCK320,Sticky programming lock for word 320" "0: Fuse word 320 can be burnt in fuse memory array,1: Attempt to program fuse word 320 in OTP memory.." line.long 0x2C "BSEC_SPLOCK11,BSEC sticky programming lock register 11" bitfld.long 0x2C 31. "SPLOCK383,Sticky programming lock for word 383" "0: Fuse word 383 can be burnt in fuse memory array,1: Attempt to program fuse word 383 in OTP memory.." bitfld.long 0x2C 30. "SPLOCK382,Sticky programming lock for word 382" "0: Fuse word 382 can be burnt in fuse memory array,1: Attempt to program fuse word 382 in OTP memory.." newline bitfld.long 0x2C 29. "SPLOCK381,Sticky programming lock for word 381" "0: Fuse word 381 can be burnt in fuse memory array,1: Attempt to program fuse word 381 in OTP memory.." bitfld.long 0x2C 28. "SPLOCK380,Sticky programming lock for word 380" "0: Fuse word 380 can be burnt in fuse memory array,1: Attempt to program fuse word 380 in OTP memory.." newline bitfld.long 0x2C 27. "SPLOCK379,Sticky programming lock for word 379" "0: Fuse word 379 can be burnt in fuse memory array,1: Attempt to program fuse word 379 in OTP memory.." bitfld.long 0x2C 26. "SPLOCK378,Sticky programming lock for word 378" "0: Fuse word 378 can be burnt in fuse memory array,1: Attempt to program fuse word 378 in OTP memory.." newline bitfld.long 0x2C 25. "SPLOCK377,Sticky programming lock for word 377" "0: Fuse word 377 can be burnt in fuse memory array,1: Attempt to program fuse word 377 in OTP memory.." bitfld.long 0x2C 24. "SPLOCK376,Sticky programming lock for word 376" "0: Fuse word 376 can be burnt in fuse memory array,1: Attempt to program fuse word 376 in OTP memory.." newline bitfld.long 0x2C 23. "SPLOCK375,Sticky programming lock for word 375" "0: Fuse word 375 can be burnt in fuse memory array,1: Attempt to program fuse word 375 in OTP memory.." bitfld.long 0x2C 22. "SPLOCK374,Sticky programming lock for word 374" "0: Fuse word 374 can be burnt in fuse memory array,1: Attempt to program fuse word 374 in OTP memory.." newline bitfld.long 0x2C 21. "SPLOCK373,Sticky programming lock for word 373" "0: Fuse word 373 can be burnt in fuse memory array,1: Attempt to program fuse word 373 in OTP memory.." bitfld.long 0x2C 20. "SPLOCK372,Sticky programming lock for word 372" "0: Fuse word 372 can be burnt in fuse memory array,1: Attempt to program fuse word 372 in OTP memory.." newline bitfld.long 0x2C 19. "SPLOCK371,Sticky programming lock for word 371" "0: Fuse word 371 can be burnt in fuse memory array,1: Attempt to program fuse word 371 in OTP memory.." bitfld.long 0x2C 18. "SPLOCK370,Sticky programming lock for word 370" "0: Fuse word 370 can be burnt in fuse memory array,1: Attempt to program fuse word 370 in OTP memory.." newline bitfld.long 0x2C 17. "SPLOCK369,Sticky programming lock for word 369" "0: Fuse word 369 can be burnt in fuse memory array,1: Attempt to program fuse word 369 in OTP memory.." bitfld.long 0x2C 16. "SPLOCK368,Sticky programming lock for word 368" "0: Fuse word 368 can be burnt in fuse memory array,1: Attempt to program fuse word 368 in OTP memory.." newline bitfld.long 0x2C 15. "SPLOCK367,Sticky programming lock for word 367" "0: Fuse word 367 can be burnt in fuse memory array,1: Attempt to program fuse word 367 in OTP memory.." bitfld.long 0x2C 14. "SPLOCK366,Sticky programming lock for word 366" "0: Fuse word 366 can be burnt in fuse memory array,1: Attempt to program fuse word 366 in OTP memory.." newline bitfld.long 0x2C 13. "SPLOCK365,Sticky programming lock for word 365" "0: Fuse word 365 can be burnt in fuse memory array,1: Attempt to program fuse word 365 in OTP memory.." bitfld.long 0x2C 12. "SPLOCK364,Sticky programming lock for word 364" "0: Fuse word 364 can be burnt in fuse memory array,1: Attempt to program fuse word 364 in OTP memory.." newline bitfld.long 0x2C 11. "SPLOCK363,Sticky programming lock for word 363" "0: Fuse word 363 can be burnt in fuse memory array,1: Attempt to program fuse word 363 in OTP memory.." bitfld.long 0x2C 10. "SPLOCK362,Sticky programming lock for word 362" "0: Fuse word 362 can be burnt in fuse memory array,1: Attempt to program fuse word 362 in OTP memory.." newline bitfld.long 0x2C 9. "SPLOCK361,Sticky programming lock for word 361" "0: Fuse word 361 can be burnt in fuse memory array,1: Attempt to program fuse word 361 in OTP memory.." bitfld.long 0x2C 8. "SPLOCK360,Sticky programming lock for word 360" "0: Fuse word 360 can be burnt in fuse memory array,1: Attempt to program fuse word 360 in OTP memory.." newline bitfld.long 0x2C 7. "SPLOCK359,Sticky programming lock for word 359" "0: Fuse word 359 can be burnt in fuse memory array,1: Attempt to program fuse word 359 in OTP memory.." bitfld.long 0x2C 6. "SPLOCK358,Sticky programming lock for word 358" "0: Fuse word 358 can be burnt in fuse memory array,1: Attempt to program fuse word 358 in OTP memory.." newline bitfld.long 0x2C 5. "SPLOCK357,Sticky programming lock for word 357" "0: Fuse word 357 can be burnt in fuse memory array,1: Attempt to program fuse word 357 in OTP memory.." bitfld.long 0x2C 4. "SPLOCK356,Sticky programming lock for word 356" "0: Fuse word 356 can be burnt in fuse memory array,1: Attempt to program fuse word 356 in OTP memory.." newline bitfld.long 0x2C 3. "SPLOCK355,Sticky programming lock for word 355" "0: Fuse word 355 can be burnt in fuse memory array,1: Attempt to program fuse word 355 in OTP memory.." bitfld.long 0x2C 2. "SPLOCK354,Sticky programming lock for word 354" "0: Fuse word 354 can be burnt in fuse memory array,1: Attempt to program fuse word 354 in OTP memory.." newline bitfld.long 0x2C 1. "SPLOCK353,Sticky programming lock for word 353" "0: Fuse word 353 can be burnt in fuse memory array,1: Attempt to program fuse word 353 in OTP memory.." bitfld.long 0x2C 0. "SPLOCK352,Sticky programming lock for word 352" "0: Fuse word 352 can be burnt in fuse memory array,1: Attempt to program fuse word 352 in OTP memory.." group.long 0x840++0x2F line.long 0x0 "BSEC_SWLOCK0,BSEC sticky write lock register 0" bitfld.long 0x0 31. "SWLOCK31,sticky write lock for shadow register 31" "0: Write to shadow register BSEC_FVR31 is allowed,1: Writes to shadow register BSEC_FVR31 are.." bitfld.long 0x0 30. "SWLOCK30,sticky write lock for shadow register 30" "0: Write to shadow register BSEC_FVR30 is allowed,1: Writes to shadow register BSEC_FVR30 are.." newline bitfld.long 0x0 29. "SWLOCK29,sticky write lock for shadow register 29" "0: Write to shadow register BSEC_FVR29 is allowed,1: Writes to shadow register BSEC_FVR29 are.." bitfld.long 0x0 28. "SWLOCK28,sticky write lock for shadow register 28" "0: Write to shadow register BSEC_FVR28 is allowed,1: Writes to shadow register BSEC_FVR28 are.." newline bitfld.long 0x0 27. "SWLOCK27,sticky write lock for shadow register 27" "0: Write to shadow register BSEC_FVR27 is allowed,1: Writes to shadow register BSEC_FVR27 are.." bitfld.long 0x0 26. "SWLOCK26,sticky write lock for shadow register 26" "0: Write to shadow register BSEC_FVR26 is allowed,1: Writes to shadow register BSEC_FVR26 are.." newline bitfld.long 0x0 25. "SWLOCK25,sticky write lock for shadow register 25" "0: Write to shadow register BSEC_FVR25 is allowed,1: Writes to shadow register BSEC_FVR25 are.." bitfld.long 0x0 24. "SWLOCK24,sticky write lock for shadow register 24" "0: Write to shadow register BSEC_FVR24 is allowed,1: Writes to shadow register BSEC_FVR24 are.." newline bitfld.long 0x0 23. "SWLOCK23,sticky write lock for shadow register 23" "0: Write to shadow register BSEC_FVR23 is allowed,1: Writes to shadow register BSEC_FVR23 are.." bitfld.long 0x0 22. "SWLOCK22,sticky write lock for shadow register 22" "0: Write to shadow register BSEC_FVR22 is allowed,1: Writes to shadow register BSEC_FVR22 are.." newline bitfld.long 0x0 21. "SWLOCK21,sticky write lock for shadow register 21" "0: Write to shadow register BSEC_FVR21 is allowed,1: Writes to shadow register BSEC_FVR21 are.." bitfld.long 0x0 20. "SWLOCK20,sticky write lock for shadow register 20" "0: Write to shadow register BSEC_FVR20 is allowed,1: Writes to shadow register BSEC_FVR20 are.." newline bitfld.long 0x0 19. "SWLOCK19,sticky write lock for shadow register 19" "0: Write to shadow register BSEC_FVR19 is allowed,1: Writes to shadow register BSEC_FVR19 are.." bitfld.long 0x0 18. "SWLOCK18,sticky write lock for shadow register 18" "0: Write to shadow register BSEC_FVR18 is allowed,1: Writes to shadow register BSEC_FVR18 are.." newline bitfld.long 0x0 17. "SWLOCK17,sticky write lock for shadow register 17" "0: Write to shadow register BSEC_FVR17 is allowed,1: Writes to shadow register BSEC_FVR17 are.." bitfld.long 0x0 16. "SWLOCK16,sticky write lock for shadow register 16" "0: Write to shadow register BSEC_FVR16 is allowed,1: Writes to shadow register BSEC_FVR16 are.." newline bitfld.long 0x0 15. "SWLOCK15,sticky write lock for shadow register 15" "0: Write to shadow register BSEC_FVR15 is allowed,1: Writes to shadow register BSEC_FVR15 are.." bitfld.long 0x0 14. "SWLOCK14,sticky write lock for shadow register 14" "0: Write to shadow register BSEC_FVR14 is allowed,1: Writes to shadow register BSEC_FVR14 are.." newline bitfld.long 0x0 13. "SWLOCK13,sticky write lock for shadow register 13" "0: Write to shadow register BSEC_FVR13 is allowed,1: Writes to shadow register BSEC_FVR13 are.." bitfld.long 0x0 12. "SWLOCK12,sticky write lock for shadow register 12" "0: Write to shadow register BSEC_FVR12 is allowed,1: Writes to shadow register BSEC_FVR12 are.." newline bitfld.long 0x0 11. "SWLOCK11,sticky write lock for shadow register 11" "0: Write to shadow register BSEC_FVR11 is allowed,1: Writes to shadow register BSEC_FVR11 are.." bitfld.long 0x0 10. "SWLOCK10,sticky write lock for shadow register 10" "0: Write to shadow register BSEC_FVR10 is allowed,1: Writes to shadow register BSEC_FVR10 are.." newline bitfld.long 0x0 9. "SWLOCK9,sticky write lock for shadow register 9" "0: Write to shadow register BSEC_FVR9 is allowed,1: Writes to shadow register BSEC_FVR9 are silently.." bitfld.long 0x0 8. "SWLOCK8,sticky write lock for shadow register 8" "0: Write to shadow register BSEC_FVR8 is allowed,1: Writes to shadow register BSEC_FVR8 are silently.." newline bitfld.long 0x0 7. "SWLOCK7,sticky write lock for shadow register 7" "0: Write to shadow register BSEC_FVR7 is allowed,1: Writes to shadow register BSEC_FVR7 are silently.." bitfld.long 0x0 6. "SWLOCK6,sticky write lock for shadow register 6" "0: Write to shadow register BSEC_FVR6 is allowed,1: Writes to shadow register BSEC_FVR6 are silently.." newline bitfld.long 0x0 5. "SWLOCK5,sticky write lock for shadow register 5" "0: Write to shadow register BSEC_FVR5 is allowed,1: Writes to shadow register BSEC_FVR5 are silently.." bitfld.long 0x0 4. "SWLOCK4,sticky write lock for shadow register 4" "0: Write to shadow register BSEC_FVR4 is allowed,1: Writes to shadow register BSEC_FVR4 are silently.." newline bitfld.long 0x0 3. "SWLOCK3,sticky write lock for shadow register 3" "0: Write to shadow register BSEC_FVR3 is allowed,1: Writes to shadow register BSEC_FVR3 are silently.." bitfld.long 0x0 2. "SWLOCK2,sticky write lock for shadow register 2" "0: Write to shadow register BSEC_FVR2 is allowed,1: Writes to shadow register BSEC_FVR2 are silently.." newline bitfld.long 0x0 1. "SWLOCK1,sticky write lock for shadow register 1" "0: Write to shadow register BSEC_FVR1 is allowed,1: Writes to shadow register BSEC_FVR1 are silently.." bitfld.long 0x0 0. "SWLOCK0,sticky write lock for shadow register 0" "0: Write to shadow register BSEC_FVR0 is allowed,1: Writes to shadow register BSEC_FVR0 are silently.." line.long 0x4 "BSEC_SWLOCK1,BSEC sticky write lock register 1" bitfld.long 0x4 31. "SWLOCK63,sticky write lock for shadow register 63" "0: Write to shadow register BSEC_FVR63 is allowed,1: Writes to shadow register BSEC_FVR63 are.." bitfld.long 0x4 30. "SWLOCK62,sticky write lock for shadow register 62" "0: Write to shadow register BSEC_FVR62 is allowed,1: Writes to shadow register BSEC_FVR62 are.." newline bitfld.long 0x4 29. "SWLOCK61,sticky write lock for shadow register 61" "0: Write to shadow register BSEC_FVR61 is allowed,1: Writes to shadow register BSEC_FVR61 are.." bitfld.long 0x4 28. "SWLOCK60,sticky write lock for shadow register 60" "0: Write to shadow register BSEC_FVR60 is allowed,1: Writes to shadow register BSEC_FVR60 are.." newline bitfld.long 0x4 27. "SWLOCK59,sticky write lock for shadow register 59" "0: Write to shadow register BSEC_FVR59 is allowed,1: Writes to shadow register BSEC_FVR59 are.." bitfld.long 0x4 26. "SWLOCK58,sticky write lock for shadow register 58" "0: Write to shadow register BSEC_FVR58 is allowed,1: Writes to shadow register BSEC_FVR58 are.." newline bitfld.long 0x4 25. "SWLOCK57,sticky write lock for shadow register 57" "0: Write to shadow register BSEC_FVR57 is allowed,1: Writes to shadow register BSEC_FVR57 are.." bitfld.long 0x4 24. "SWLOCK56,sticky write lock for shadow register 56" "0: Write to shadow register BSEC_FVR56 is allowed,1: Writes to shadow register BSEC_FVR56 are.." newline bitfld.long 0x4 23. "SWLOCK55,sticky write lock for shadow register 55" "0: Write to shadow register BSEC_FVR55 is allowed,1: Writes to shadow register BSEC_FVR55 are.." bitfld.long 0x4 22. "SWLOCK54,sticky write lock for shadow register 54" "0: Write to shadow register BSEC_FVR54 is allowed,1: Writes to shadow register BSEC_FVR54 are.." newline bitfld.long 0x4 21. "SWLOCK53,sticky write lock for shadow register 53" "0: Write to shadow register BSEC_FVR53 is allowed,1: Writes to shadow register BSEC_FVR53 are.." bitfld.long 0x4 20. "SWLOCK52,sticky write lock for shadow register 52" "0: Write to shadow register BSEC_FVR52 is allowed,1: Writes to shadow register BSEC_FVR52 are.." newline bitfld.long 0x4 19. "SWLOCK51,sticky write lock for shadow register 51" "0: Write to shadow register BSEC_FVR51 is allowed,1: Writes to shadow register BSEC_FVR51 are.." bitfld.long 0x4 18. "SWLOCK50,sticky write lock for shadow register 50" "0: Write to shadow register BSEC_FVR50 is allowed,1: Writes to shadow register BSEC_FVR50 are.." newline bitfld.long 0x4 17. "SWLOCK49,sticky write lock for shadow register 49" "0: Write to shadow register BSEC_FVR49 is allowed,1: Writes to shadow register BSEC_FVR49 are.." bitfld.long 0x4 16. "SWLOCK48,sticky write lock for shadow register 48" "0: Write to shadow register BSEC_FVR48 is allowed,1: Writes to shadow register BSEC_FVR48 are.." newline bitfld.long 0x4 15. "SWLOCK47,sticky write lock for shadow register 47" "0: Write to shadow register BSEC_FVR47 is allowed,1: Writes to shadow register BSEC_FVR47 are.." bitfld.long 0x4 14. "SWLOCK46,sticky write lock for shadow register 46" "0: Write to shadow register BSEC_FVR46 is allowed,1: Writes to shadow register BSEC_FVR46 are.." newline bitfld.long 0x4 13. "SWLOCK45,sticky write lock for shadow register 45" "0: Write to shadow register BSEC_FVR45 is allowed,1: Writes to shadow register BSEC_FVR45 are.." bitfld.long 0x4 12. "SWLOCK44,sticky write lock for shadow register 44" "0: Write to shadow register BSEC_FVR44 is allowed,1: Writes to shadow register BSEC_FVR44 are.." newline bitfld.long 0x4 11. "SWLOCK43,sticky write lock for shadow register 43" "0: Write to shadow register BSEC_FVR43 is allowed,1: Writes to shadow register BSEC_FVR43 are.." bitfld.long 0x4 10. "SWLOCK42,sticky write lock for shadow register 42" "0: Write to shadow register BSEC_FVR42 is allowed,1: Writes to shadow register BSEC_FVR42 are.." newline bitfld.long 0x4 9. "SWLOCK41,sticky write lock for shadow register 41" "0: Write to shadow register BSEC_FVR41 is allowed,1: Writes to shadow register BSEC_FVR41 are.." bitfld.long 0x4 8. "SWLOCK40,sticky write lock for shadow register 40" "0: Write to shadow register BSEC_FVR40 is allowed,1: Writes to shadow register BSEC_FVR40 are.." newline bitfld.long 0x4 7. "SWLOCK39,sticky write lock for shadow register 39" "0: Write to shadow register BSEC_FVR39 is allowed,1: Writes to shadow register BSEC_FVR39 are.." bitfld.long 0x4 6. "SWLOCK38,sticky write lock for shadow register 38" "0: Write to shadow register BSEC_FVR38 is allowed,1: Writes to shadow register BSEC_FVR38 are.." newline bitfld.long 0x4 5. "SWLOCK37,sticky write lock for shadow register 37" "0: Write to shadow register BSEC_FVR37 is allowed,1: Writes to shadow register BSEC_FVR37 are.." bitfld.long 0x4 4. "SWLOCK36,sticky write lock for shadow register 36" "0: Write to shadow register BSEC_FVR36 is allowed,1: Writes to shadow register BSEC_FVR36 are.." newline bitfld.long 0x4 3. "SWLOCK35,sticky write lock for shadow register 35" "0: Write to shadow register BSEC_FVR35 is allowed,1: Writes to shadow register BSEC_FVR35 are.." bitfld.long 0x4 2. "SWLOCK34,sticky write lock for shadow register 34" "0: Write to shadow register BSEC_FVR34 is allowed,1: Writes to shadow register BSEC_FVR34 are.." newline bitfld.long 0x4 1. "SWLOCK33,sticky write lock for shadow register 33" "0: Write to shadow register BSEC_FVR33 is allowed,1: Writes to shadow register BSEC_FVR33 are.." bitfld.long 0x4 0. "SWLOCK32,sticky write lock for shadow register 32" "0: Write to shadow register BSEC_FVR32 is allowed,1: Writes to shadow register BSEC_FVR32 are.." line.long 0x8 "BSEC_SWLOCK2,BSEC sticky write lock register 2" bitfld.long 0x8 31. "SWLOCK95,sticky write lock for shadow register 95" "0: Write to shadow register BSEC_FVR95 is allowed,1: Writes to shadow register BSEC_FVR95 are.." bitfld.long 0x8 30. "SWLOCK94,sticky write lock for shadow register 94" "0: Write to shadow register BSEC_FVR94 is allowed,1: Writes to shadow register BSEC_FVR94 are.." newline bitfld.long 0x8 29. "SWLOCK93,sticky write lock for shadow register 93" "0: Write to shadow register BSEC_FVR93 is allowed,1: Writes to shadow register BSEC_FVR93 are.." bitfld.long 0x8 28. "SWLOCK92,sticky write lock for shadow register 92" "0: Write to shadow register BSEC_FVR92 is allowed,1: Writes to shadow register BSEC_FVR92 are.." newline bitfld.long 0x8 27. "SWLOCK91,sticky write lock for shadow register 91" "0: Write to shadow register BSEC_FVR91 is allowed,1: Writes to shadow register BSEC_FVR91 are.." bitfld.long 0x8 26. "SWLOCK90,sticky write lock for shadow register 90" "0: Write to shadow register BSEC_FVR90 is allowed,1: Writes to shadow register BSEC_FVR90 are.." newline bitfld.long 0x8 25. "SWLOCK89,sticky write lock for shadow register 89" "0: Write to shadow register BSEC_FVR89 is allowed,1: Writes to shadow register BSEC_FVR89 are.." bitfld.long 0x8 24. "SWLOCK88,sticky write lock for shadow register 88" "0: Write to shadow register BSEC_FVR88 is allowed,1: Writes to shadow register BSEC_FVR88 are.." newline bitfld.long 0x8 23. "SWLOCK87,sticky write lock for shadow register 87" "0: Write to shadow register BSEC_FVR87 is allowed,1: Writes to shadow register BSEC_FVR87 are.." bitfld.long 0x8 22. "SWLOCK86,sticky write lock for shadow register 86" "0: Write to shadow register BSEC_FVR86 is allowed,1: Writes to shadow register BSEC_FVR86 are.." newline bitfld.long 0x8 21. "SWLOCK85,sticky write lock for shadow register 85" "0: Write to shadow register BSEC_FVR85 is allowed,1: Writes to shadow register BSEC_FVR85 are.." bitfld.long 0x8 20. "SWLOCK84,sticky write lock for shadow register 84" "0: Write to shadow register BSEC_FVR84 is allowed,1: Writes to shadow register BSEC_FVR84 are.." newline bitfld.long 0x8 19. "SWLOCK83,sticky write lock for shadow register 83" "0: Write to shadow register BSEC_FVR83 is allowed,1: Writes to shadow register BSEC_FVR83 are.." bitfld.long 0x8 18. "SWLOCK82,sticky write lock for shadow register 82" "0: Write to shadow register BSEC_FVR82 is allowed,1: Writes to shadow register BSEC_FVR82 are.." newline bitfld.long 0x8 17. "SWLOCK81,sticky write lock for shadow register 81" "0: Write to shadow register BSEC_FVR81 is allowed,1: Writes to shadow register BSEC_FVR81 are.." bitfld.long 0x8 16. "SWLOCK80,sticky write lock for shadow register 80" "0: Write to shadow register BSEC_FVR80 is allowed,1: Writes to shadow register BSEC_FVR80 are.." newline bitfld.long 0x8 15. "SWLOCK79,sticky write lock for shadow register 79" "0: Write to shadow register BSEC_FVR79 is allowed,1: Writes to shadow register BSEC_FVR79 are.." bitfld.long 0x8 14. "SWLOCK78,sticky write lock for shadow register 78" "0: Write to shadow register BSEC_FVR78 is allowed,1: Writes to shadow register BSEC_FVR78 are.." newline bitfld.long 0x8 13. "SWLOCK77,sticky write lock for shadow register 77" "0: Write to shadow register BSEC_FVR77 is allowed,1: Writes to shadow register BSEC_FVR77 are.." bitfld.long 0x8 12. "SWLOCK76,sticky write lock for shadow register 76" "0: Write to shadow register BSEC_FVR76 is allowed,1: Writes to shadow register BSEC_FVR76 are.." newline bitfld.long 0x8 11. "SWLOCK75,sticky write lock for shadow register 75" "0: Write to shadow register BSEC_FVR75 is allowed,1: Writes to shadow register BSEC_FVR75 are.." bitfld.long 0x8 10. "SWLOCK74,sticky write lock for shadow register 74" "0: Write to shadow register BSEC_FVR74 is allowed,1: Writes to shadow register BSEC_FVR74 are.." newline bitfld.long 0x8 9. "SWLOCK73,sticky write lock for shadow register 73" "0: Write to shadow register BSEC_FVR73 is allowed,1: Writes to shadow register BSEC_FVR73 are.." bitfld.long 0x8 8. "SWLOCK72,sticky write lock for shadow register 72" "0: Write to shadow register BSEC_FVR72 is allowed,1: Writes to shadow register BSEC_FVR72 are.." newline bitfld.long 0x8 7. "SWLOCK71,sticky write lock for shadow register 71" "0: Write to shadow register BSEC_FVR71 is allowed,1: Writes to shadow register BSEC_FVR71 are.." bitfld.long 0x8 6. "SWLOCK70,sticky write lock for shadow register 70" "0: Write to shadow register BSEC_FVR70 is allowed,1: Writes to shadow register BSEC_FVR70 are.." newline bitfld.long 0x8 5. "SWLOCK69,sticky write lock for shadow register 69" "0: Write to shadow register BSEC_FVR69 is allowed,1: Writes to shadow register BSEC_FVR69 are.." bitfld.long 0x8 4. "SWLOCK68,sticky write lock for shadow register 68" "0: Write to shadow register BSEC_FVR68 is allowed,1: Writes to shadow register BSEC_FVR68 are.." newline bitfld.long 0x8 3. "SWLOCK67,sticky write lock for shadow register 67" "0: Write to shadow register BSEC_FVR67 is allowed,1: Writes to shadow register BSEC_FVR67 are.." bitfld.long 0x8 2. "SWLOCK66,sticky write lock for shadow register 66" "0: Write to shadow register BSEC_FVR66 is allowed,1: Writes to shadow register BSEC_FVR66 are.." newline bitfld.long 0x8 1. "SWLOCK65,sticky write lock for shadow register 65" "0: Write to shadow register BSEC_FVR65 is allowed,1: Writes to shadow register BSEC_FVR65 are.." bitfld.long 0x8 0. "SWLOCK64,sticky write lock for shadow register 64" "0: Write to shadow register BSEC_FVR64 is allowed,1: Writes to shadow register BSEC_FVR64 are.." line.long 0xC "BSEC_SWLOCK3,BSEC sticky write lock register 3" bitfld.long 0xC 31. "SWLOCK127,sticky write lock for shadow register 127" "0: Write to shadow register BSEC_FVR127 is allowed,1: Writes to shadow register BSEC_FVR127 are.." bitfld.long 0xC 30. "SWLOCK126,sticky write lock for shadow register 126" "0: Write to shadow register BSEC_FVR126 is allowed,1: Writes to shadow register BSEC_FVR126 are.." newline bitfld.long 0xC 29. "SWLOCK125,sticky write lock for shadow register 125" "0: Write to shadow register BSEC_FVR125 is allowed,1: Writes to shadow register BSEC_FVR125 are.." bitfld.long 0xC 28. "SWLOCK124,sticky write lock for shadow register 124" "0: Write to shadow register BSEC_FVR124 is allowed,1: Writes to shadow register BSEC_FVR124 are.." newline bitfld.long 0xC 27. "SWLOCK123,sticky write lock for shadow register 123" "0: Write to shadow register BSEC_FVR123 is allowed,1: Writes to shadow register BSEC_FVR123 are.." bitfld.long 0xC 26. "SWLOCK122,sticky write lock for shadow register 122" "0: Write to shadow register BSEC_FVR122 is allowed,1: Writes to shadow register BSEC_FVR122 are.." newline bitfld.long 0xC 25. "SWLOCK121,sticky write lock for shadow register 121" "0: Write to shadow register BSEC_FVR121 is allowed,1: Writes to shadow register BSEC_FVR121 are.." bitfld.long 0xC 24. "SWLOCK120,sticky write lock for shadow register 120" "0: Write to shadow register BSEC_FVR120 is allowed,1: Writes to shadow register BSEC_FVR120 are.." newline bitfld.long 0xC 23. "SWLOCK119,sticky write lock for shadow register 119" "0: Write to shadow register BSEC_FVR119 is allowed,1: Writes to shadow register BSEC_FVR119 are.." bitfld.long 0xC 22. "SWLOCK118,sticky write lock for shadow register 118" "0: Write to shadow register BSEC_FVR118 is allowed,1: Writes to shadow register BSEC_FVR118 are.." newline bitfld.long 0xC 21. "SWLOCK117,sticky write lock for shadow register 117" "0: Write to shadow register BSEC_FVR117 is allowed,1: Writes to shadow register BSEC_FVR117 are.." bitfld.long 0xC 20. "SWLOCK116,sticky write lock for shadow register 116" "0: Write to shadow register BSEC_FVR116 is allowed,1: Writes to shadow register BSEC_FVR116 are.." newline bitfld.long 0xC 19. "SWLOCK115,sticky write lock for shadow register 115" "0: Write to shadow register BSEC_FVR115 is allowed,1: Writes to shadow register BSEC_FVR115 are.." bitfld.long 0xC 18. "SWLOCK114,sticky write lock for shadow register 114" "0: Write to shadow register BSEC_FVR114 is allowed,1: Writes to shadow register BSEC_FVR114 are.." newline bitfld.long 0xC 17. "SWLOCK113,sticky write lock for shadow register 113" "0: Write to shadow register BSEC_FVR113 is allowed,1: Writes to shadow register BSEC_FVR113 are.." bitfld.long 0xC 16. "SWLOCK112,sticky write lock for shadow register 112" "0: Write to shadow register BSEC_FVR112 is allowed,1: Writes to shadow register BSEC_FVR112 are.." newline bitfld.long 0xC 15. "SWLOCK111,sticky write lock for shadow register 111" "0: Write to shadow register BSEC_FVR111 is allowed,1: Writes to shadow register BSEC_FVR111 are.." bitfld.long 0xC 14. "SWLOCK110,sticky write lock for shadow register 110" "0: Write to shadow register BSEC_FVR110 is allowed,1: Writes to shadow register BSEC_FVR110 are.." newline bitfld.long 0xC 13. "SWLOCK109,sticky write lock for shadow register 109" "0: Write to shadow register BSEC_FVR109 is allowed,1: Writes to shadow register BSEC_FVR109 are.." bitfld.long 0xC 12. "SWLOCK108,sticky write lock for shadow register 108" "0: Write to shadow register BSEC_FVR108 is allowed,1: Writes to shadow register BSEC_FVR108 are.." newline bitfld.long 0xC 11. "SWLOCK107,sticky write lock for shadow register 107" "0: Write to shadow register BSEC_FVR107 is allowed,1: Writes to shadow register BSEC_FVR107 are.." bitfld.long 0xC 10. "SWLOCK106,sticky write lock for shadow register 106" "0: Write to shadow register BSEC_FVR106 is allowed,1: Writes to shadow register BSEC_FVR106 are.." newline bitfld.long 0xC 9. "SWLOCK105,sticky write lock for shadow register 105" "0: Write to shadow register BSEC_FVR105 is allowed,1: Writes to shadow register BSEC_FVR105 are.." bitfld.long 0xC 8. "SWLOCK104,sticky write lock for shadow register 104" "0: Write to shadow register BSEC_FVR104 is allowed,1: Writes to shadow register BSEC_FVR104 are.." newline bitfld.long 0xC 7. "SWLOCK103,sticky write lock for shadow register 103" "0: Write to shadow register BSEC_FVR103 is allowed,1: Writes to shadow register BSEC_FVR103 are.." bitfld.long 0xC 6. "SWLOCK102,sticky write lock for shadow register 102" "0: Write to shadow register BSEC_FVR102 is allowed,1: Writes to shadow register BSEC_FVR102 are.." newline bitfld.long 0xC 5. "SWLOCK101,sticky write lock for shadow register 101" "0: Write to shadow register BSEC_FVR101 is allowed,1: Writes to shadow register BSEC_FVR101 are.." bitfld.long 0xC 4. "SWLOCK100,sticky write lock for shadow register 100" "0: Write to shadow register BSEC_FVR100 is allowed,1: Writes to shadow register BSEC_FVR100 are.." newline bitfld.long 0xC 3. "SWLOCK99,sticky write lock for shadow register 99" "0: Write to shadow register BSEC_FVR99 is allowed,1: Writes to shadow register BSEC_FVR99 are.." bitfld.long 0xC 2. "SWLOCK98,sticky write lock for shadow register 98" "0: Write to shadow register BSEC_FVR98 is allowed,1: Writes to shadow register BSEC_FVR98 are.." newline bitfld.long 0xC 1. "SWLOCK97,sticky write lock for shadow register 97" "0: Write to shadow register BSEC_FVR97 is allowed,1: Writes to shadow register BSEC_FVR97 are.." bitfld.long 0xC 0. "SWLOCK96,sticky write lock for shadow register 96" "0: Write to shadow register BSEC_FVR96 is allowed,1: Writes to shadow register BSEC_FVR96 are.." line.long 0x10 "BSEC_SWLOCK4,BSEC sticky write lock register 4" bitfld.long 0x10 31. "SWLOCK159,sticky write lock for shadow register 159" "0: Write to shadow register BSEC_FVR159 is allowed,1: Writes to shadow register BSEC_FVR159 are.." bitfld.long 0x10 30. "SWLOCK158,sticky write lock for shadow register 158" "0: Write to shadow register BSEC_FVR158 is allowed,1: Writes to shadow register BSEC_FVR158 are.." newline bitfld.long 0x10 29. "SWLOCK157,sticky write lock for shadow register 157" "0: Write to shadow register BSEC_FVR157 is allowed,1: Writes to shadow register BSEC_FVR157 are.." bitfld.long 0x10 28. "SWLOCK156,sticky write lock for shadow register 156" "0: Write to shadow register BSEC_FVR156 is allowed,1: Writes to shadow register BSEC_FVR156 are.." newline bitfld.long 0x10 27. "SWLOCK155,sticky write lock for shadow register 155" "0: Write to shadow register BSEC_FVR155 is allowed,1: Writes to shadow register BSEC_FVR155 are.." bitfld.long 0x10 26. "SWLOCK154,sticky write lock for shadow register 154" "0: Write to shadow register BSEC_FVR154 is allowed,1: Writes to shadow register BSEC_FVR154 are.." newline bitfld.long 0x10 25. "SWLOCK153,sticky write lock for shadow register 153" "0: Write to shadow register BSEC_FVR153 is allowed,1: Writes to shadow register BSEC_FVR153 are.." bitfld.long 0x10 24. "SWLOCK152,sticky write lock for shadow register 152" "0: Write to shadow register BSEC_FVR152 is allowed,1: Writes to shadow register BSEC_FVR152 are.." newline bitfld.long 0x10 23. "SWLOCK151,sticky write lock for shadow register 151" "0: Write to shadow register BSEC_FVR151 is allowed,1: Writes to shadow register BSEC_FVR151 are.." bitfld.long 0x10 22. "SWLOCK150,sticky write lock for shadow register 150" "0: Write to shadow register BSEC_FVR150 is allowed,1: Writes to shadow register BSEC_FVR150 are.." newline bitfld.long 0x10 21. "SWLOCK149,sticky write lock for shadow register 149" "0: Write to shadow register BSEC_FVR149 is allowed,1: Writes to shadow register BSEC_FVR149 are.." bitfld.long 0x10 20. "SWLOCK148,sticky write lock for shadow register 148" "0: Write to shadow register BSEC_FVR148 is allowed,1: Writes to shadow register BSEC_FVR148 are.." newline bitfld.long 0x10 19. "SWLOCK147,sticky write lock for shadow register 147" "0: Write to shadow register BSEC_FVR147 is allowed,1: Writes to shadow register BSEC_FVR147 are.." bitfld.long 0x10 18. "SWLOCK146,sticky write lock for shadow register 146" "0: Write to shadow register BSEC_FVR146 is allowed,1: Writes to shadow register BSEC_FVR146 are.." newline bitfld.long 0x10 17. "SWLOCK145,sticky write lock for shadow register 145" "0: Write to shadow register BSEC_FVR145 is allowed,1: Writes to shadow register BSEC_FVR145 are.." bitfld.long 0x10 16. "SWLOCK144,sticky write lock for shadow register 144" "0: Write to shadow register BSEC_FVR144 is allowed,1: Writes to shadow register BSEC_FVR144 are.." newline bitfld.long 0x10 15. "SWLOCK143,sticky write lock for shadow register 143" "0: Write to shadow register BSEC_FVR143 is allowed,1: Writes to shadow register BSEC_FVR143 are.." bitfld.long 0x10 14. "SWLOCK142,sticky write lock for shadow register 142" "0: Write to shadow register BSEC_FVR142 is allowed,1: Writes to shadow register BSEC_FVR142 are.." newline bitfld.long 0x10 13. "SWLOCK141,sticky write lock for shadow register 141" "0: Write to shadow register BSEC_FVR141 is allowed,1: Writes to shadow register BSEC_FVR141 are.." bitfld.long 0x10 12. "SWLOCK140,sticky write lock for shadow register 140" "0: Write to shadow register BSEC_FVR140 is allowed,1: Writes to shadow register BSEC_FVR140 are.." newline bitfld.long 0x10 11. "SWLOCK139,sticky write lock for shadow register 139" "0: Write to shadow register BSEC_FVR139 is allowed,1: Writes to shadow register BSEC_FVR139 are.." bitfld.long 0x10 10. "SWLOCK138,sticky write lock for shadow register 138" "0: Write to shadow register BSEC_FVR138 is allowed,1: Writes to shadow register BSEC_FVR138 are.." newline bitfld.long 0x10 9. "SWLOCK137,sticky write lock for shadow register 137" "0: Write to shadow register BSEC_FVR137 is allowed,1: Writes to shadow register BSEC_FVR137 are.." bitfld.long 0x10 8. "SWLOCK136,sticky write lock for shadow register 136" "0: Write to shadow register BSEC_FVR136 is allowed,1: Writes to shadow register BSEC_FVR136 are.." newline bitfld.long 0x10 7. "SWLOCK135,sticky write lock for shadow register 135" "0: Write to shadow register BSEC_FVR135 is allowed,1: Writes to shadow register BSEC_FVR135 are.." bitfld.long 0x10 6. "SWLOCK134,sticky write lock for shadow register 134" "0: Write to shadow register BSEC_FVR134 is allowed,1: Writes to shadow register BSEC_FVR134 are.." newline bitfld.long 0x10 5. "SWLOCK133,sticky write lock for shadow register 133" "0: Write to shadow register BSEC_FVR133 is allowed,1: Writes to shadow register BSEC_FVR133 are.." bitfld.long 0x10 4. "SWLOCK132,sticky write lock for shadow register 132" "0: Write to shadow register BSEC_FVR132 is allowed,1: Writes to shadow register BSEC_FVR132 are.." newline bitfld.long 0x10 3. "SWLOCK131,sticky write lock for shadow register 131" "0: Write to shadow register BSEC_FVR131 is allowed,1: Writes to shadow register BSEC_FVR131 are.." bitfld.long 0x10 2. "SWLOCK130,sticky write lock for shadow register 130" "0: Write to shadow register BSEC_FVR130 is allowed,1: Writes to shadow register BSEC_FVR130 are.." newline bitfld.long 0x10 1. "SWLOCK129,sticky write lock for shadow register 129" "0: Write to shadow register BSEC_FVR129 is allowed,1: Writes to shadow register BSEC_FVR129 are.." bitfld.long 0x10 0. "SWLOCK128,sticky write lock for shadow register 128" "0: Write to shadow register BSEC_FVR128 is allowed,1: Writes to shadow register BSEC_FVR128 are.." line.long 0x14 "BSEC_SWLOCK5,BSEC sticky write lock register 5" bitfld.long 0x14 31. "SWLOCK191,sticky write lock for shadow register 191" "0: Write to shadow register BSEC_FVR191 is allowed,1: Writes to shadow register BSEC_FVR191 are.." bitfld.long 0x14 30. "SWLOCK190,sticky write lock for shadow register 190" "0: Write to shadow register BSEC_FVR190 is allowed,1: Writes to shadow register BSEC_FVR190 are.." newline bitfld.long 0x14 29. "SWLOCK189,sticky write lock for shadow register 189" "0: Write to shadow register BSEC_FVR189 is allowed,1: Writes to shadow register BSEC_FVR189 are.." bitfld.long 0x14 28. "SWLOCK188,sticky write lock for shadow register 188" "0: Write to shadow register BSEC_FVR188 is allowed,1: Writes to shadow register BSEC_FVR188 are.." newline bitfld.long 0x14 27. "SWLOCK187,sticky write lock for shadow register 187" "0: Write to shadow register BSEC_FVR187 is allowed,1: Writes to shadow register BSEC_FVR187 are.." bitfld.long 0x14 26. "SWLOCK186,sticky write lock for shadow register 186" "0: Write to shadow register BSEC_FVR186 is allowed,1: Writes to shadow register BSEC_FVR186 are.." newline bitfld.long 0x14 25. "SWLOCK185,sticky write lock for shadow register 185" "0: Write to shadow register BSEC_FVR185 is allowed,1: Writes to shadow register BSEC_FVR185 are.." bitfld.long 0x14 24. "SWLOCK184,sticky write lock for shadow register 184" "0: Write to shadow register BSEC_FVR184 is allowed,1: Writes to shadow register BSEC_FVR184 are.." newline bitfld.long 0x14 23. "SWLOCK183,sticky write lock for shadow register 183" "0: Write to shadow register BSEC_FVR183 is allowed,1: Writes to shadow register BSEC_FVR183 are.." bitfld.long 0x14 22. "SWLOCK182,sticky write lock for shadow register 182" "0: Write to shadow register BSEC_FVR182 is allowed,1: Writes to shadow register BSEC_FVR182 are.." newline bitfld.long 0x14 21. "SWLOCK181,sticky write lock for shadow register 181" "0: Write to shadow register BSEC_FVR181 is allowed,1: Writes to shadow register BSEC_FVR181 are.." bitfld.long 0x14 20. "SWLOCK180,sticky write lock for shadow register 180" "0: Write to shadow register BSEC_FVR180 is allowed,1: Writes to shadow register BSEC_FVR180 are.." newline bitfld.long 0x14 19. "SWLOCK179,sticky write lock for shadow register 179" "0: Write to shadow register BSEC_FVR179 is allowed,1: Writes to shadow register BSEC_FVR179 are.." bitfld.long 0x14 18. "SWLOCK178,sticky write lock for shadow register 178" "0: Write to shadow register BSEC_FVR178 is allowed,1: Writes to shadow register BSEC_FVR178 are.." newline bitfld.long 0x14 17. "SWLOCK177,sticky write lock for shadow register 177" "0: Write to shadow register BSEC_FVR177 is allowed,1: Writes to shadow register BSEC_FVR177 are.." bitfld.long 0x14 16. "SWLOCK176,sticky write lock for shadow register 176" "0: Write to shadow register BSEC_FVR176 is allowed,1: Writes to shadow register BSEC_FVR176 are.." newline bitfld.long 0x14 15. "SWLOCK175,sticky write lock for shadow register 175" "0: Write to shadow register BSEC_FVR175 is allowed,1: Writes to shadow register BSEC_FVR175 are.." bitfld.long 0x14 14. "SWLOCK174,sticky write lock for shadow register 174" "0: Write to shadow register BSEC_FVR174 is allowed,1: Writes to shadow register BSEC_FVR174 are.." newline bitfld.long 0x14 13. "SWLOCK173,sticky write lock for shadow register 173" "0: Write to shadow register BSEC_FVR173 is allowed,1: Writes to shadow register BSEC_FVR173 are.." bitfld.long 0x14 12. "SWLOCK172,sticky write lock for shadow register 172" "0: Write to shadow register BSEC_FVR172 is allowed,1: Writes to shadow register BSEC_FVR172 are.." newline bitfld.long 0x14 11. "SWLOCK171,sticky write lock for shadow register 171" "0: Write to shadow register BSEC_FVR171 is allowed,1: Writes to shadow register BSEC_FVR171 are.." bitfld.long 0x14 10. "SWLOCK170,sticky write lock for shadow register 170" "0: Write to shadow register BSEC_FVR170 is allowed,1: Writes to shadow register BSEC_FVR170 are.." newline bitfld.long 0x14 9. "SWLOCK169,sticky write lock for shadow register 169" "0: Write to shadow register BSEC_FVR169 is allowed,1: Writes to shadow register BSEC_FVR169 are.." bitfld.long 0x14 8. "SWLOCK168,sticky write lock for shadow register 168" "0: Write to shadow register BSEC_FVR168 is allowed,1: Writes to shadow register BSEC_FVR168 are.." newline bitfld.long 0x14 7. "SWLOCK167,sticky write lock for shadow register 167" "0: Write to shadow register BSEC_FVR167 is allowed,1: Writes to shadow register BSEC_FVR167 are.." bitfld.long 0x14 6. "SWLOCK166,sticky write lock for shadow register 166" "0: Write to shadow register BSEC_FVR166 is allowed,1: Writes to shadow register BSEC_FVR166 are.." newline bitfld.long 0x14 5. "SWLOCK165,sticky write lock for shadow register 165" "0: Write to shadow register BSEC_FVR165 is allowed,1: Writes to shadow register BSEC_FVR165 are.." bitfld.long 0x14 4. "SWLOCK164,sticky write lock for shadow register 164" "0: Write to shadow register BSEC_FVR164 is allowed,1: Writes to shadow register BSEC_FVR164 are.." newline bitfld.long 0x14 3. "SWLOCK163,sticky write lock for shadow register 163" "0: Write to shadow register BSEC_FVR163 is allowed,1: Writes to shadow register BSEC_FVR163 are.." bitfld.long 0x14 2. "SWLOCK162,sticky write lock for shadow register 162" "0: Write to shadow register BSEC_FVR162 is allowed,1: Writes to shadow register BSEC_FVR162 are.." newline bitfld.long 0x14 1. "SWLOCK161,sticky write lock for shadow register 161" "0: Write to shadow register BSEC_FVR161 is allowed,1: Writes to shadow register BSEC_FVR161 are.." bitfld.long 0x14 0. "SWLOCK160,sticky write lock for shadow register 160" "0: Write to shadow register BSEC_FVR160 is allowed,1: Writes to shadow register BSEC_FVR160 are.." line.long 0x18 "BSEC_SWLOCK6,BSEC sticky write lock register 6" bitfld.long 0x18 31. "SWLOCK223,sticky write lock for shadow register 223" "0: Write to shadow register BSEC_FVR223 is allowed,1: Writes to shadow register BSEC_FVR223 are.." bitfld.long 0x18 30. "SWLOCK222,sticky write lock for shadow register 222" "0: Write to shadow register BSEC_FVR222 is allowed,1: Writes to shadow register BSEC_FVR222 are.." newline bitfld.long 0x18 29. "SWLOCK221,sticky write lock for shadow register 221" "0: Write to shadow register BSEC_FVR221 is allowed,1: Writes to shadow register BSEC_FVR221 are.." bitfld.long 0x18 28. "SWLOCK220,sticky write lock for shadow register 220" "0: Write to shadow register BSEC_FVR220 is allowed,1: Writes to shadow register BSEC_FVR220 are.." newline bitfld.long 0x18 27. "SWLOCK219,sticky write lock for shadow register 219" "0: Write to shadow register BSEC_FVR219 is allowed,1: Writes to shadow register BSEC_FVR219 are.." bitfld.long 0x18 26. "SWLOCK218,sticky write lock for shadow register 218" "0: Write to shadow register BSEC_FVR218 is allowed,1: Writes to shadow register BSEC_FVR218 are.." newline bitfld.long 0x18 25. "SWLOCK217,sticky write lock for shadow register 217" "0: Write to shadow register BSEC_FVR217 is allowed,1: Writes to shadow register BSEC_FVR217 are.." bitfld.long 0x18 24. "SWLOCK216,sticky write lock for shadow register 216" "0: Write to shadow register BSEC_FVR216 is allowed,1: Writes to shadow register BSEC_FVR216 are.." newline bitfld.long 0x18 23. "SWLOCK215,sticky write lock for shadow register 215" "0: Write to shadow register BSEC_FVR215 is allowed,1: Writes to shadow register BSEC_FVR215 are.." bitfld.long 0x18 22. "SWLOCK214,sticky write lock for shadow register 214" "0: Write to shadow register BSEC_FVR214 is allowed,1: Writes to shadow register BSEC_FVR214 are.." newline bitfld.long 0x18 21. "SWLOCK213,sticky write lock for shadow register 213" "0: Write to shadow register BSEC_FVR213 is allowed,1: Writes to shadow register BSEC_FVR213 are.." bitfld.long 0x18 20. "SWLOCK212,sticky write lock for shadow register 212" "0: Write to shadow register BSEC_FVR212 is allowed,1: Writes to shadow register BSEC_FVR212 are.." newline bitfld.long 0x18 19. "SWLOCK211,sticky write lock for shadow register 211" "0: Write to shadow register BSEC_FVR211 is allowed,1: Writes to shadow register BSEC_FVR211 are.." bitfld.long 0x18 18. "SWLOCK210,sticky write lock for shadow register 210" "0: Write to shadow register BSEC_FVR210 is allowed,1: Writes to shadow register BSEC_FVR210 are.." newline bitfld.long 0x18 17. "SWLOCK209,sticky write lock for shadow register 209" "0: Write to shadow register BSEC_FVR209 is allowed,1: Writes to shadow register BSEC_FVR209 are.." bitfld.long 0x18 16. "SWLOCK208,sticky write lock for shadow register 208" "0: Write to shadow register BSEC_FVR208 is allowed,1: Writes to shadow register BSEC_FVR208 are.." newline bitfld.long 0x18 15. "SWLOCK207,sticky write lock for shadow register 207" "0: Write to shadow register BSEC_FVR207 is allowed,1: Writes to shadow register BSEC_FVR207 are.." bitfld.long 0x18 14. "SWLOCK206,sticky write lock for shadow register 206" "0: Write to shadow register BSEC_FVR206 is allowed,1: Writes to shadow register BSEC_FVR206 are.." newline bitfld.long 0x18 13. "SWLOCK205,sticky write lock for shadow register 205" "0: Write to shadow register BSEC_FVR205 is allowed,1: Writes to shadow register BSEC_FVR205 are.." bitfld.long 0x18 12. "SWLOCK204,sticky write lock for shadow register 204" "0: Write to shadow register BSEC_FVR204 is allowed,1: Writes to shadow register BSEC_FVR204 are.." newline bitfld.long 0x18 11. "SWLOCK203,sticky write lock for shadow register 203" "0: Write to shadow register BSEC_FVR203 is allowed,1: Writes to shadow register BSEC_FVR203 are.." bitfld.long 0x18 10. "SWLOCK202,sticky write lock for shadow register 202" "0: Write to shadow register BSEC_FVR202 is allowed,1: Writes to shadow register BSEC_FVR202 are.." newline bitfld.long 0x18 9. "SWLOCK201,sticky write lock for shadow register 201" "0: Write to shadow register BSEC_FVR201 is allowed,1: Writes to shadow register BSEC_FVR201 are.." bitfld.long 0x18 8. "SWLOCK200,sticky write lock for shadow register 200" "0: Write to shadow register BSEC_FVR200 is allowed,1: Writes to shadow register BSEC_FVR200 are.." newline bitfld.long 0x18 7. "SWLOCK199,sticky write lock for shadow register 199" "0: Write to shadow register BSEC_FVR199 is allowed,1: Writes to shadow register BSEC_FVR199 are.." bitfld.long 0x18 6. "SWLOCK198,sticky write lock for shadow register 198" "0: Write to shadow register BSEC_FVR198 is allowed,1: Writes to shadow register BSEC_FVR198 are.." newline bitfld.long 0x18 5. "SWLOCK197,sticky write lock for shadow register 197" "0: Write to shadow register BSEC_FVR197 is allowed,1: Writes to shadow register BSEC_FVR197 are.." bitfld.long 0x18 4. "SWLOCK196,sticky write lock for shadow register 196" "0: Write to shadow register BSEC_FVR196 is allowed,1: Writes to shadow register BSEC_FVR196 are.." newline bitfld.long 0x18 3. "SWLOCK195,sticky write lock for shadow register 195" "0: Write to shadow register BSEC_FVR195 is allowed,1: Writes to shadow register BSEC_FVR195 are.." bitfld.long 0x18 2. "SWLOCK194,sticky write lock for shadow register 194" "0: Write to shadow register BSEC_FVR194 is allowed,1: Writes to shadow register BSEC_FVR194 are.." newline bitfld.long 0x18 1. "SWLOCK193,sticky write lock for shadow register 193" "0: Write to shadow register BSEC_FVR193 is allowed,1: Writes to shadow register BSEC_FVR193 are.." bitfld.long 0x18 0. "SWLOCK192,sticky write lock for shadow register 192" "0: Write to shadow register BSEC_FVR192 is allowed,1: Writes to shadow register BSEC_FVR192 are.." line.long 0x1C "BSEC_SWLOCK7,BSEC sticky write lock register 7" bitfld.long 0x1C 31. "SWLOCK255,sticky write lock for shadow register 255" "0: Write to shadow register BSEC_FVR255 is allowed,1: Writes to shadow register BSEC_FVR255 are.." bitfld.long 0x1C 30. "SWLOCK254,sticky write lock for shadow register 254" "0: Write to shadow register BSEC_FVR254 is allowed,1: Writes to shadow register BSEC_FVR254 are.." newline bitfld.long 0x1C 29. "SWLOCK253,sticky write lock for shadow register 253" "0: Write to shadow register BSEC_FVR253 is allowed,1: Writes to shadow register BSEC_FVR253 are.." bitfld.long 0x1C 28. "SWLOCK252,sticky write lock for shadow register 252" "0: Write to shadow register BSEC_FVR252 is allowed,1: Writes to shadow register BSEC_FVR252 are.." newline bitfld.long 0x1C 27. "SWLOCK251,sticky write lock for shadow register 251" "0: Write to shadow register BSEC_FVR251 is allowed,1: Writes to shadow register BSEC_FVR251 are.." bitfld.long 0x1C 26. "SWLOCK250,sticky write lock for shadow register 250" "0: Write to shadow register BSEC_FVR250 is allowed,1: Writes to shadow register BSEC_FVR250 are.." newline bitfld.long 0x1C 25. "SWLOCK249,sticky write lock for shadow register 249" "0: Write to shadow register BSEC_FVR249 is allowed,1: Writes to shadow register BSEC_FVR249 are.." bitfld.long 0x1C 24. "SWLOCK248,sticky write lock for shadow register 248" "0: Write to shadow register BSEC_FVR248 is allowed,1: Writes to shadow register BSEC_FVR248 are.." newline bitfld.long 0x1C 23. "SWLOCK247,sticky write lock for shadow register 247" "0: Write to shadow register BSEC_FVR247 is allowed,1: Writes to shadow register BSEC_FVR247 are.." bitfld.long 0x1C 22. "SWLOCK246,sticky write lock for shadow register 246" "0: Write to shadow register BSEC_FVR246 is allowed,1: Writes to shadow register BSEC_FVR246 are.." newline bitfld.long 0x1C 21. "SWLOCK245,sticky write lock for shadow register 245" "0: Write to shadow register BSEC_FVR245 is allowed,1: Writes to shadow register BSEC_FVR245 are.." bitfld.long 0x1C 20. "SWLOCK244,sticky write lock for shadow register 244" "0: Write to shadow register BSEC_FVR244 is allowed,1: Writes to shadow register BSEC_FVR244 are.." newline bitfld.long 0x1C 19. "SWLOCK243,sticky write lock for shadow register 243" "0: Write to shadow register BSEC_FVR243 is allowed,1: Writes to shadow register BSEC_FVR243 are.." bitfld.long 0x1C 18. "SWLOCK242,sticky write lock for shadow register 242" "0: Write to shadow register BSEC_FVR242 is allowed,1: Writes to shadow register BSEC_FVR242 are.." newline bitfld.long 0x1C 17. "SWLOCK241,sticky write lock for shadow register 241" "0: Write to shadow register BSEC_FVR241 is allowed,1: Writes to shadow register BSEC_FVR241 are.." bitfld.long 0x1C 16. "SWLOCK240,sticky write lock for shadow register 240" "0: Write to shadow register BSEC_FVR240 is allowed,1: Writes to shadow register BSEC_FVR240 are.." newline bitfld.long 0x1C 15. "SWLOCK239,sticky write lock for shadow register 239" "0: Write to shadow register BSEC_FVR239 is allowed,1: Writes to shadow register BSEC_FVR239 are.." bitfld.long 0x1C 14. "SWLOCK238,sticky write lock for shadow register 238" "0: Write to shadow register BSEC_FVR238 is allowed,1: Writes to shadow register BSEC_FVR238 are.." newline bitfld.long 0x1C 13. "SWLOCK237,sticky write lock for shadow register 237" "0: Write to shadow register BSEC_FVR237 is allowed,1: Writes to shadow register BSEC_FVR237 are.." bitfld.long 0x1C 12. "SWLOCK236,sticky write lock for shadow register 236" "0: Write to shadow register BSEC_FVR236 is allowed,1: Writes to shadow register BSEC_FVR236 are.." newline bitfld.long 0x1C 11. "SWLOCK235,sticky write lock for shadow register 235" "0: Write to shadow register BSEC_FVR235 is allowed,1: Writes to shadow register BSEC_FVR235 are.." bitfld.long 0x1C 10. "SWLOCK234,sticky write lock for shadow register 234" "0: Write to shadow register BSEC_FVR234 is allowed,1: Writes to shadow register BSEC_FVR234 are.." newline bitfld.long 0x1C 9. "SWLOCK233,sticky write lock for shadow register 233" "0: Write to shadow register BSEC_FVR233 is allowed,1: Writes to shadow register BSEC_FVR233 are.." bitfld.long 0x1C 8. "SWLOCK232,sticky write lock for shadow register 232" "0: Write to shadow register BSEC_FVR232 is allowed,1: Writes to shadow register BSEC_FVR232 are.." newline bitfld.long 0x1C 7. "SWLOCK231,sticky write lock for shadow register 231" "0: Write to shadow register BSEC_FVR231 is allowed,1: Writes to shadow register BSEC_FVR231 are.." bitfld.long 0x1C 6. "SWLOCK230,sticky write lock for shadow register 230" "0: Write to shadow register BSEC_FVR230 is allowed,1: Writes to shadow register BSEC_FVR230 are.." newline bitfld.long 0x1C 5. "SWLOCK229,sticky write lock for shadow register 229" "0: Write to shadow register BSEC_FVR229 is allowed,1: Writes to shadow register BSEC_FVR229 are.." bitfld.long 0x1C 4. "SWLOCK228,sticky write lock for shadow register 228" "0: Write to shadow register BSEC_FVR228 is allowed,1: Writes to shadow register BSEC_FVR228 are.." newline bitfld.long 0x1C 3. "SWLOCK227,sticky write lock for shadow register 227" "0: Write to shadow register BSEC_FVR227 is allowed,1: Writes to shadow register BSEC_FVR227 are.." bitfld.long 0x1C 2. "SWLOCK226,sticky write lock for shadow register 226" "0: Write to shadow register BSEC_FVR226 is allowed,1: Writes to shadow register BSEC_FVR226 are.." newline bitfld.long 0x1C 1. "SWLOCK225,sticky write lock for shadow register 225" "0: Write to shadow register BSEC_FVR225 is allowed,1: Writes to shadow register BSEC_FVR225 are.." bitfld.long 0x1C 0. "SWLOCK224,sticky write lock for shadow register 224" "0: Write to shadow register BSEC_FVR224 is allowed,1: Writes to shadow register BSEC_FVR224 are.." line.long 0x20 "BSEC_SWLOCK8,BSEC sticky write lock register 8" bitfld.long 0x20 31. "SWLOCK287,sticky write lock for shadow register 287" "0: Write to shadow register BSEC_FVR287 is allowed,1: Writes to shadow register BSEC_FVR287 are.." bitfld.long 0x20 30. "SWLOCK286,sticky write lock for shadow register 286" "0: Write to shadow register BSEC_FVR286 is allowed,1: Writes to shadow register BSEC_FVR286 are.." newline bitfld.long 0x20 29. "SWLOCK285,sticky write lock for shadow register 285" "0: Write to shadow register BSEC_FVR285 is allowed,1: Writes to shadow register BSEC_FVR285 are.." bitfld.long 0x20 28. "SWLOCK284,sticky write lock for shadow register 284" "0: Write to shadow register BSEC_FVR284 is allowed,1: Writes to shadow register BSEC_FVR284 are.." newline bitfld.long 0x20 27. "SWLOCK283,sticky write lock for shadow register 283" "0: Write to shadow register BSEC_FVR283 is allowed,1: Writes to shadow register BSEC_FVR283 are.." bitfld.long 0x20 26. "SWLOCK282,sticky write lock for shadow register 282" "0: Write to shadow register BSEC_FVR282 is allowed,1: Writes to shadow register BSEC_FVR282 are.." newline bitfld.long 0x20 25. "SWLOCK281,sticky write lock for shadow register 281" "0: Write to shadow register BSEC_FVR281 is allowed,1: Writes to shadow register BSEC_FVR281 are.." bitfld.long 0x20 24. "SWLOCK280,sticky write lock for shadow register 280" "0: Write to shadow register BSEC_FVR280 is allowed,1: Writes to shadow register BSEC_FVR280 are.." newline bitfld.long 0x20 23. "SWLOCK279,sticky write lock for shadow register 279" "0: Write to shadow register BSEC_FVR279 is allowed,1: Writes to shadow register BSEC_FVR279 are.." bitfld.long 0x20 22. "SWLOCK278,sticky write lock for shadow register 278" "0: Write to shadow register BSEC_FVR278 is allowed,1: Writes to shadow register BSEC_FVR278 are.." newline bitfld.long 0x20 21. "SWLOCK277,sticky write lock for shadow register 277" "0: Write to shadow register BSEC_FVR277 is allowed,1: Writes to shadow register BSEC_FVR277 are.." bitfld.long 0x20 20. "SWLOCK276,sticky write lock for shadow register 276" "0: Write to shadow register BSEC_FVR276 is allowed,1: Writes to shadow register BSEC_FVR276 are.." newline bitfld.long 0x20 19. "SWLOCK275,sticky write lock for shadow register 275" "0: Write to shadow register BSEC_FVR275 is allowed,1: Writes to shadow register BSEC_FVR275 are.." bitfld.long 0x20 18. "SWLOCK274,sticky write lock for shadow register 274" "0: Write to shadow register BSEC_FVR274 is allowed,1: Writes to shadow register BSEC_FVR274 are.." newline bitfld.long 0x20 17. "SWLOCK273,sticky write lock for shadow register 273" "0: Write to shadow register BSEC_FVR273 is allowed,1: Writes to shadow register BSEC_FVR273 are.." bitfld.long 0x20 16. "SWLOCK272,sticky write lock for shadow register 272" "0: Write to shadow register BSEC_FVR272 is allowed,1: Writes to shadow register BSEC_FVR272 are.." newline bitfld.long 0x20 15. "SWLOCK271,sticky write lock for shadow register 271" "0: Write to shadow register BSEC_FVR271 is allowed,1: Writes to shadow register BSEC_FVR271 are.." bitfld.long 0x20 14. "SWLOCK270,sticky write lock for shadow register 270" "0: Write to shadow register BSEC_FVR270 is allowed,1: Writes to shadow register BSEC_FVR270 are.." newline bitfld.long 0x20 13. "SWLOCK269,sticky write lock for shadow register 269" "0: Write to shadow register BSEC_FVR269 is allowed,1: Writes to shadow register BSEC_FVR269 are.." bitfld.long 0x20 12. "SWLOCK268,sticky write lock for shadow register 268" "0: Write to shadow register BSEC_FVR268 is allowed,1: Writes to shadow register BSEC_FVR268 are.." newline bitfld.long 0x20 11. "SWLOCK267,sticky write lock for shadow register 267" "0: Write to shadow register BSEC_FVR267 is allowed,1: Writes to shadow register BSEC_FVR267 are.." bitfld.long 0x20 10. "SWLOCK266,sticky write lock for shadow register 266" "0: Write to shadow register BSEC_FVR266 is allowed,1: Writes to shadow register BSEC_FVR266 are.." newline bitfld.long 0x20 9. "SWLOCK265,sticky write lock for shadow register 265" "0: Write to shadow register BSEC_FVR265 is allowed,1: Writes to shadow register BSEC_FVR265 are.." bitfld.long 0x20 8. "SWLOCK264,sticky write lock for shadow register 264" "0: Write to shadow register BSEC_FVR264 is allowed,1: Writes to shadow register BSEC_FVR264 are.." newline bitfld.long 0x20 7. "SWLOCK263,sticky write lock for shadow register 263" "0: Write to shadow register BSEC_FVR263 is allowed,1: Writes to shadow register BSEC_FVR263 are.." bitfld.long 0x20 6. "SWLOCK262,sticky write lock for shadow register 262" "0: Write to shadow register BSEC_FVR262 is allowed,1: Writes to shadow register BSEC_FVR262 are.." newline bitfld.long 0x20 5. "SWLOCK261,sticky write lock for shadow register 261" "0: Write to shadow register BSEC_FVR261 is allowed,1: Writes to shadow register BSEC_FVR261 are.." bitfld.long 0x20 4. "SWLOCK260,sticky write lock for shadow register 260" "0: Write to shadow register BSEC_FVR260 is allowed,1: Writes to shadow register BSEC_FVR260 are.." newline bitfld.long 0x20 3. "SWLOCK259,sticky write lock for shadow register 259" "0: Write to shadow register BSEC_FVR259 is allowed,1: Writes to shadow register BSEC_FVR259 are.." bitfld.long 0x20 2. "SWLOCK258,sticky write lock for shadow register 258" "0: Write to shadow register BSEC_FVR258 is allowed,1: Writes to shadow register BSEC_FVR258 are.." newline bitfld.long 0x20 1. "SWLOCK257,sticky write lock for shadow register 257" "0: Write to shadow register BSEC_FVR257 is allowed,1: Writes to shadow register BSEC_FVR257 are.." bitfld.long 0x20 0. "SWLOCK256,sticky write lock for shadow register 256" "0: Write to shadow register BSEC_FVR256 is allowed,1: Writes to shadow register BSEC_FVR256 are.." line.long 0x24 "BSEC_SWLOCK9,BSEC sticky write lock register 9" bitfld.long 0x24 31. "SWLOCK319,sticky write lock for shadow register 319" "0: Write to shadow register BSEC_FVR319 is allowed,1: Writes to shadow register BSEC_FVR319 are.." bitfld.long 0x24 30. "SWLOCK318,sticky write lock for shadow register 318" "0: Write to shadow register BSEC_FVR318 is allowed,1: Writes to shadow register BSEC_FVR318 are.." newline bitfld.long 0x24 29. "SWLOCK317,sticky write lock for shadow register 317" "0: Write to shadow register BSEC_FVR317 is allowed,1: Writes to shadow register BSEC_FVR317 are.." bitfld.long 0x24 28. "SWLOCK316,sticky write lock for shadow register 316" "0: Write to shadow register BSEC_FVR316 is allowed,1: Writes to shadow register BSEC_FVR316 are.." newline bitfld.long 0x24 27. "SWLOCK315,sticky write lock for shadow register 315" "0: Write to shadow register BSEC_FVR315 is allowed,1: Writes to shadow register BSEC_FVR315 are.." bitfld.long 0x24 26. "SWLOCK314,sticky write lock for shadow register 314" "0: Write to shadow register BSEC_FVR314 is allowed,1: Writes to shadow register BSEC_FVR314 are.." newline bitfld.long 0x24 25. "SWLOCK313,sticky write lock for shadow register 313" "0: Write to shadow register BSEC_FVR313 is allowed,1: Writes to shadow register BSEC_FVR313 are.." bitfld.long 0x24 24. "SWLOCK312,sticky write lock for shadow register 312" "0: Write to shadow register BSEC_FVR312 is allowed,1: Writes to shadow register BSEC_FVR312 are.." newline bitfld.long 0x24 23. "SWLOCK311,sticky write lock for shadow register 311" "0: Write to shadow register BSEC_FVR311 is allowed,1: Writes to shadow register BSEC_FVR311 are.." bitfld.long 0x24 22. "SWLOCK310,sticky write lock for shadow register 310" "0: Write to shadow register BSEC_FVR310 is allowed,1: Writes to shadow register BSEC_FVR310 are.." newline bitfld.long 0x24 21. "SWLOCK309,sticky write lock for shadow register 309" "0: Write to shadow register BSEC_FVR309 is allowed,1: Writes to shadow register BSEC_FVR309 are.." bitfld.long 0x24 20. "SWLOCK308,sticky write lock for shadow register 308" "0: Write to shadow register BSEC_FVR308 is allowed,1: Writes to shadow register BSEC_FVR308 are.." newline bitfld.long 0x24 19. "SWLOCK307,sticky write lock for shadow register 307" "0: Write to shadow register BSEC_FVR307 is allowed,1: Writes to shadow register BSEC_FVR307 are.." bitfld.long 0x24 18. "SWLOCK306,sticky write lock for shadow register 306" "0: Write to shadow register BSEC_FVR306 is allowed,1: Writes to shadow register BSEC_FVR306 are.." newline bitfld.long 0x24 17. "SWLOCK305,sticky write lock for shadow register 305" "0: Write to shadow register BSEC_FVR305 is allowed,1: Writes to shadow register BSEC_FVR305 are.." bitfld.long 0x24 16. "SWLOCK304,sticky write lock for shadow register 304" "0: Write to shadow register BSEC_FVR304 is allowed,1: Writes to shadow register BSEC_FVR304 are.." newline bitfld.long 0x24 15. "SWLOCK303,sticky write lock for shadow register 303" "0: Write to shadow register BSEC_FVR303 is allowed,1: Writes to shadow register BSEC_FVR303 are.." bitfld.long 0x24 14. "SWLOCK302,sticky write lock for shadow register 302" "0: Write to shadow register BSEC_FVR302 is allowed,1: Writes to shadow register BSEC_FVR302 are.." newline bitfld.long 0x24 13. "SWLOCK301,sticky write lock for shadow register 301" "0: Write to shadow register BSEC_FVR301 is allowed,1: Writes to shadow register BSEC_FVR301 are.." bitfld.long 0x24 12. "SWLOCK300,sticky write lock for shadow register 300" "0: Write to shadow register BSEC_FVR300 is allowed,1: Writes to shadow register BSEC_FVR300 are.." newline bitfld.long 0x24 11. "SWLOCK299,sticky write lock for shadow register 299" "0: Write to shadow register BSEC_FVR299 is allowed,1: Writes to shadow register BSEC_FVR299 are.." bitfld.long 0x24 10. "SWLOCK298,sticky write lock for shadow register 298" "0: Write to shadow register BSEC_FVR298 is allowed,1: Writes to shadow register BSEC_FVR298 are.." newline bitfld.long 0x24 9. "SWLOCK297,sticky write lock for shadow register 297" "0: Write to shadow register BSEC_FVR297 is allowed,1: Writes to shadow register BSEC_FVR297 are.." bitfld.long 0x24 8. "SWLOCK296,sticky write lock for shadow register 296" "0: Write to shadow register BSEC_FVR296 is allowed,1: Writes to shadow register BSEC_FVR296 are.." newline bitfld.long 0x24 7. "SWLOCK295,sticky write lock for shadow register 295" "0: Write to shadow register BSEC_FVR295 is allowed,1: Writes to shadow register BSEC_FVR295 are.." bitfld.long 0x24 6. "SWLOCK294,sticky write lock for shadow register 294" "0: Write to shadow register BSEC_FVR294 is allowed,1: Writes to shadow register BSEC_FVR294 are.." newline bitfld.long 0x24 5. "SWLOCK293,sticky write lock for shadow register 293" "0: Write to shadow register BSEC_FVR293 is allowed,1: Writes to shadow register BSEC_FVR293 are.." bitfld.long 0x24 4. "SWLOCK292,sticky write lock for shadow register 292" "0: Write to shadow register BSEC_FVR292 is allowed,1: Writes to shadow register BSEC_FVR292 are.." newline bitfld.long 0x24 3. "SWLOCK291,sticky write lock for shadow register 291" "0: Write to shadow register BSEC_FVR291 is allowed,1: Writes to shadow register BSEC_FVR291 are.." bitfld.long 0x24 2. "SWLOCK290,sticky write lock for shadow register 290" "0: Write to shadow register BSEC_FVR290 is allowed,1: Writes to shadow register BSEC_FVR290 are.." newline bitfld.long 0x24 1. "SWLOCK289,sticky write lock for shadow register 289" "0: Write to shadow register BSEC_FVR289 is allowed,1: Writes to shadow register BSEC_FVR289 are.." bitfld.long 0x24 0. "SWLOCK288,sticky write lock for shadow register 288" "0: Write to shadow register BSEC_FVR288 is allowed,1: Writes to shadow register BSEC_FVR288 are.." line.long 0x28 "BSEC_SWLOCK10,BSEC sticky write lock register 10" bitfld.long 0x28 31. "SWLOCK351,sticky write lock for shadow register 351" "0: Write to shadow register BSEC_FVR351 is allowed,1: Writes to shadow register BSEC_FVR351 are.." bitfld.long 0x28 30. "SWLOCK350,sticky write lock for shadow register 350" "0: Write to shadow register BSEC_FVR350 is allowed,1: Writes to shadow register BSEC_FVR350 are.." newline bitfld.long 0x28 29. "SWLOCK349,sticky write lock for shadow register 349" "0: Write to shadow register BSEC_FVR349 is allowed,1: Writes to shadow register BSEC_FVR349 are.." bitfld.long 0x28 28. "SWLOCK348,sticky write lock for shadow register 348" "0: Write to shadow register BSEC_FVR348 is allowed,1: Writes to shadow register BSEC_FVR348 are.." newline bitfld.long 0x28 27. "SWLOCK347,sticky write lock for shadow register 347" "0: Write to shadow register BSEC_FVR347 is allowed,1: Writes to shadow register BSEC_FVR347 are.." bitfld.long 0x28 26. "SWLOCK346,sticky write lock for shadow register 346" "0: Write to shadow register BSEC_FVR346 is allowed,1: Writes to shadow register BSEC_FVR346 are.." newline bitfld.long 0x28 25. "SWLOCK345,sticky write lock for shadow register 345" "0: Write to shadow register BSEC_FVR345 is allowed,1: Writes to shadow register BSEC_FVR345 are.." bitfld.long 0x28 24. "SWLOCK344,sticky write lock for shadow register 344" "0: Write to shadow register BSEC_FVR344 is allowed,1: Writes to shadow register BSEC_FVR344 are.." newline bitfld.long 0x28 23. "SWLOCK343,sticky write lock for shadow register 343" "0: Write to shadow register BSEC_FVR343 is allowed,1: Writes to shadow register BSEC_FVR343 are.." bitfld.long 0x28 22. "SWLOCK342,sticky write lock for shadow register 342" "0: Write to shadow register BSEC_FVR342 is allowed,1: Writes to shadow register BSEC_FVR342 are.." newline bitfld.long 0x28 21. "SWLOCK341,sticky write lock for shadow register 341" "0: Write to shadow register BSEC_FVR341 is allowed,1: Writes to shadow register BSEC_FVR341 are.." bitfld.long 0x28 20. "SWLOCK340,sticky write lock for shadow register 340" "0: Write to shadow register BSEC_FVR340 is allowed,1: Writes to shadow register BSEC_FVR340 are.." newline bitfld.long 0x28 19. "SWLOCK339,sticky write lock for shadow register 339" "0: Write to shadow register BSEC_FVR339 is allowed,1: Writes to shadow register BSEC_FVR339 are.." bitfld.long 0x28 18. "SWLOCK338,sticky write lock for shadow register 338" "0: Write to shadow register BSEC_FVR338 is allowed,1: Writes to shadow register BSEC_FVR338 are.." newline bitfld.long 0x28 17. "SWLOCK337,sticky write lock for shadow register 337" "0: Write to shadow register BSEC_FVR337 is allowed,1: Writes to shadow register BSEC_FVR337 are.." bitfld.long 0x28 16. "SWLOCK336,sticky write lock for shadow register 336" "0: Write to shadow register BSEC_FVR336 is allowed,1: Writes to shadow register BSEC_FVR336 are.." newline bitfld.long 0x28 15. "SWLOCK335,sticky write lock for shadow register 335" "0: Write to shadow register BSEC_FVR335 is allowed,1: Writes to shadow register BSEC_FVR335 are.." bitfld.long 0x28 14. "SWLOCK334,sticky write lock for shadow register 334" "0: Write to shadow register BSEC_FVR334 is allowed,1: Writes to shadow register BSEC_FVR334 are.." newline bitfld.long 0x28 13. "SWLOCK333,sticky write lock for shadow register 333" "0: Write to shadow register BSEC_FVR333 is allowed,1: Writes to shadow register BSEC_FVR333 are.." bitfld.long 0x28 12. "SWLOCK332,sticky write lock for shadow register 332" "0: Write to shadow register BSEC_FVR332 is allowed,1: Writes to shadow register BSEC_FVR332 are.." newline bitfld.long 0x28 11. "SWLOCK331,sticky write lock for shadow register 331" "0: Write to shadow register BSEC_FVR331 is allowed,1: Writes to shadow register BSEC_FVR331 are.." bitfld.long 0x28 10. "SWLOCK330,sticky write lock for shadow register 330" "0: Write to shadow register BSEC_FVR330 is allowed,1: Writes to shadow register BSEC_FVR330 are.." newline bitfld.long 0x28 9. "SWLOCK329,sticky write lock for shadow register 329" "0: Write to shadow register BSEC_FVR329 is allowed,1: Writes to shadow register BSEC_FVR329 are.." bitfld.long 0x28 8. "SWLOCK328,sticky write lock for shadow register 328" "0: Write to shadow register BSEC_FVR328 is allowed,1: Writes to shadow register BSEC_FVR328 are.." newline bitfld.long 0x28 7. "SWLOCK327,sticky write lock for shadow register 327" "0: Write to shadow register BSEC_FVR327 is allowed,1: Writes to shadow register BSEC_FVR327 are.." bitfld.long 0x28 6. "SWLOCK326,sticky write lock for shadow register 326" "0: Write to shadow register BSEC_FVR326 is allowed,1: Writes to shadow register BSEC_FVR326 are.." newline bitfld.long 0x28 5. "SWLOCK325,sticky write lock for shadow register 325" "0: Write to shadow register BSEC_FVR325 is allowed,1: Writes to shadow register BSEC_FVR325 are.." bitfld.long 0x28 4. "SWLOCK324,sticky write lock for shadow register 324" "0: Write to shadow register BSEC_FVR324 is allowed,1: Writes to shadow register BSEC_FVR324 are.." newline bitfld.long 0x28 3. "SWLOCK323,sticky write lock for shadow register 323" "0: Write to shadow register BSEC_FVR323 is allowed,1: Writes to shadow register BSEC_FVR323 are.." bitfld.long 0x28 2. "SWLOCK322,sticky write lock for shadow register 322" "0: Write to shadow register BSEC_FVR322 is allowed,1: Writes to shadow register BSEC_FVR322 are.." newline bitfld.long 0x28 1. "SWLOCK321,sticky write lock for shadow register 321" "0: Write to shadow register BSEC_FVR321 is allowed,1: Writes to shadow register BSEC_FVR321 are.." bitfld.long 0x28 0. "SWLOCK320,sticky write lock for shadow register 320" "0: Write to shadow register BSEC_FVR320 is allowed,1: Writes to shadow register BSEC_FVR320 are.." line.long 0x2C "BSEC_SWLOCK11,BSEC sticky write lock register 11" bitfld.long 0x2C 31. "SWLOCK383,sticky write lock for shadow register 383" "0: Write to shadow register BSEC_FVR383 is allowed,1: Writes to shadow register BSEC_FVR383 are.." bitfld.long 0x2C 30. "SWLOCK382,sticky write lock for shadow register 382" "0: Write to shadow register BSEC_FVR382 is allowed,1: Writes to shadow register BSEC_FVR382 are.." newline bitfld.long 0x2C 29. "SWLOCK381,sticky write lock for shadow register 381" "0: Write to shadow register BSEC_FVR381 is allowed,1: Writes to shadow register BSEC_FVR381 are.." bitfld.long 0x2C 28. "SWLOCK380,sticky write lock for shadow register 380" "0: Write to shadow register BSEC_FVR380 is allowed,1: Writes to shadow register BSEC_FVR380 are.." newline bitfld.long 0x2C 27. "SWLOCK379,sticky write lock for shadow register 379" "0: Write to shadow register BSEC_FVR379 is allowed,1: Writes to shadow register BSEC_FVR379 are.." bitfld.long 0x2C 26. "SWLOCK378,sticky write lock for shadow register 378" "0: Write to shadow register BSEC_FVR378 is allowed,1: Writes to shadow register BSEC_FVR378 are.." newline bitfld.long 0x2C 25. "SWLOCK377,sticky write lock for shadow register 377" "0: Write to shadow register BSEC_FVR377 is allowed,1: Writes to shadow register BSEC_FVR377 are.." bitfld.long 0x2C 24. "SWLOCK376,sticky write lock for shadow register 376" "0: Write to shadow register BSEC_FVR376 is allowed,1: Writes to shadow register BSEC_FVR376 are.." newline bitfld.long 0x2C 23. "SWLOCK375,sticky write lock for shadow register 375" "0: Write to shadow register BSEC_FVR375 is allowed,1: Writes to shadow register BSEC_FVR375 are.." bitfld.long 0x2C 22. "SWLOCK374,sticky write lock for shadow register 374" "0: Write to shadow register BSEC_FVR374 is allowed,1: Writes to shadow register BSEC_FVR374 are.." newline bitfld.long 0x2C 21. "SWLOCK373,sticky write lock for shadow register 373" "0: Write to shadow register BSEC_FVR373 is allowed,1: Writes to shadow register BSEC_FVR373 are.." bitfld.long 0x2C 20. "SWLOCK372,sticky write lock for shadow register 372" "0: Write to shadow register BSEC_FVR372 is allowed,1: Writes to shadow register BSEC_FVR372 are.." newline bitfld.long 0x2C 19. "SWLOCK371,sticky write lock for shadow register 371" "0: Write to shadow register BSEC_FVR371 is allowed,1: Writes to shadow register BSEC_FVR371 are.." bitfld.long 0x2C 18. "SWLOCK370,sticky write lock for shadow register 370" "0: Write to shadow register BSEC_FVR370 is allowed,1: Writes to shadow register BSEC_FVR370 are.." newline bitfld.long 0x2C 17. "SWLOCK369,sticky write lock for shadow register 369" "0: Write to shadow register BSEC_FVR369 is allowed,1: Writes to shadow register BSEC_FVR369 are.." bitfld.long 0x2C 16. "SWLOCK368,sticky write lock for shadow register 368" "0: Write to shadow register BSEC_FVR368 is allowed,1: Writes to shadow register BSEC_FVR368 are.." newline bitfld.long 0x2C 15. "SWLOCK367,sticky write lock for shadow register 367" "0: Write to shadow register BSEC_FVR367 is allowed,1: Writes to shadow register BSEC_FVR367 are.." bitfld.long 0x2C 14. "SWLOCK366,sticky write lock for shadow register 366" "0: Write to shadow register BSEC_FVR366 is allowed,1: Writes to shadow register BSEC_FVR366 are.." newline bitfld.long 0x2C 13. "SWLOCK365,sticky write lock for shadow register 365" "0: Write to shadow register BSEC_FVR365 is allowed,1: Writes to shadow register BSEC_FVR365 are.." bitfld.long 0x2C 12. "SWLOCK364,sticky write lock for shadow register 364" "0: Write to shadow register BSEC_FVR364 is allowed,1: Writes to shadow register BSEC_FVR364 are.." newline bitfld.long 0x2C 11. "SWLOCK363,sticky write lock for shadow register 363" "0: Write to shadow register BSEC_FVR363 is allowed,1: Writes to shadow register BSEC_FVR363 are.." bitfld.long 0x2C 10. "SWLOCK362,sticky write lock for shadow register 362" "0: Write to shadow register BSEC_FVR362 is allowed,1: Writes to shadow register BSEC_FVR362 are.." newline bitfld.long 0x2C 9. "SWLOCK361,sticky write lock for shadow register 361" "0: Write to shadow register BSEC_FVR361 is allowed,1: Writes to shadow register BSEC_FVR361 are.." bitfld.long 0x2C 8. "SWLOCK360,sticky write lock for shadow register 360" "0: Write to shadow register BSEC_FVR360 is allowed,1: Writes to shadow register BSEC_FVR360 are.." newline bitfld.long 0x2C 7. "SWLOCK359,sticky write lock for shadow register 359" "0: Write to shadow register BSEC_FVR359 is allowed,1: Writes to shadow register BSEC_FVR359 are.." bitfld.long 0x2C 6. "SWLOCK358,sticky write lock for shadow register 358" "0: Write to shadow register BSEC_FVR358 is allowed,1: Writes to shadow register BSEC_FVR358 are.." newline bitfld.long 0x2C 5. "SWLOCK357,sticky write lock for shadow register 357" "0: Write to shadow register BSEC_FVR357 is allowed,1: Writes to shadow register BSEC_FVR357 are.." bitfld.long 0x2C 4. "SWLOCK356,sticky write lock for shadow register 356" "0: Write to shadow register BSEC_FVR356 is allowed,1: Writes to shadow register BSEC_FVR356 are.." newline bitfld.long 0x2C 3. "SWLOCK355,sticky write lock for shadow register 355" "0: Write to shadow register BSEC_FVR355 is allowed,1: Writes to shadow register BSEC_FVR355 are.." bitfld.long 0x2C 2. "SWLOCK354,sticky write lock for shadow register 354" "0: Write to shadow register BSEC_FVR354 is allowed,1: Writes to shadow register BSEC_FVR354 are.." newline bitfld.long 0x2C 1. "SWLOCK353,sticky write lock for shadow register 353" "0: Write to shadow register BSEC_FVR353 is allowed,1: Writes to shadow register BSEC_FVR353 are.." bitfld.long 0x2C 0. "SWLOCK352,sticky write lock for shadow register 352" "0: Write to shadow register BSEC_FVR352 is allowed,1: Writes to shadow register BSEC_FVR352 are.." group.long 0x880++0x2F line.long 0x0 "BSEC_SRLOCK0,BSEC sticky reload lock register 0" bitfld.long 0x0 31. "SRLOCK31,sticky reload lock for fuse word 31" "0: Fuse word 31 loading through BSEC_OTPCR is..,1: Fuse word 31 loading through BSEC_OTPCR is.." bitfld.long 0x0 30. "SRLOCK30,sticky reload lock for fuse word 30" "0: Fuse word 30 loading through BSEC_OTPCR is..,1: Fuse word 30 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 29. "SRLOCK29,sticky reload lock for fuse word 29" "0: Fuse word 29 loading through BSEC_OTPCR is..,1: Fuse word 29 loading through BSEC_OTPCR is.." bitfld.long 0x0 28. "SRLOCK28,sticky reload lock for fuse word 28" "0: Fuse word 28 loading through BSEC_OTPCR is..,1: Fuse word 28 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 27. "SRLOCK27,sticky reload lock for fuse word 27" "0: Fuse word 27 loading through BSEC_OTPCR is..,1: Fuse word 27 loading through BSEC_OTPCR is.." bitfld.long 0x0 26. "SRLOCK26,sticky reload lock for fuse word 26" "0: Fuse word 26 loading through BSEC_OTPCR is..,1: Fuse word 26 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 25. "SRLOCK25,sticky reload lock for fuse word 25" "0: Fuse word 25 loading through BSEC_OTPCR is..,1: Fuse word 25 loading through BSEC_OTPCR is.." bitfld.long 0x0 24. "SRLOCK24,sticky reload lock for fuse word 24" "0: Fuse word 24 loading through BSEC_OTPCR is..,1: Fuse word 24 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 23. "SRLOCK23,sticky reload lock for fuse word 23" "0: Fuse word 23 loading through BSEC_OTPCR is..,1: Fuse word 23 loading through BSEC_OTPCR is.." bitfld.long 0x0 22. "SRLOCK22,sticky reload lock for fuse word 22" "0: Fuse word 22 loading through BSEC_OTPCR is..,1: Fuse word 22 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 21. "SRLOCK21,sticky reload lock for fuse word 21" "0: Fuse word 21 loading through BSEC_OTPCR is..,1: Fuse word 21 loading through BSEC_OTPCR is.." bitfld.long 0x0 20. "SRLOCK20,sticky reload lock for fuse word 20" "0: Fuse word 20 loading through BSEC_OTPCR is..,1: Fuse word 20 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 19. "SRLOCK19,sticky reload lock for fuse word 19" "0: Fuse word 19 loading through BSEC_OTPCR is..,1: Fuse word 19 loading through BSEC_OTPCR is.." bitfld.long 0x0 18. "SRLOCK18,sticky reload lock for fuse word 18" "0: Fuse word 18 loading through BSEC_OTPCR is..,1: Fuse word 18 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 17. "SRLOCK17,sticky reload lock for fuse word 17" "0: Fuse word 17 loading through BSEC_OTPCR is..,1: Fuse word 17 loading through BSEC_OTPCR is.." bitfld.long 0x0 16. "SRLOCK16,sticky reload lock for fuse word 16" "0: Fuse word 16 loading through BSEC_OTPCR is..,1: Fuse word 16 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 15. "SRLOCK15,sticky reload lock for fuse word 15" "0: Fuse word 15 loading through BSEC_OTPCR is..,1: Fuse word 15 loading through BSEC_OTPCR is.." bitfld.long 0x0 14. "SRLOCK14,sticky reload lock for fuse word 14" "0: Fuse word 14 loading through BSEC_OTPCR is..,1: Fuse word 14 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 13. "SRLOCK13,sticky reload lock for fuse word 13" "0: Fuse word 13 loading through BSEC_OTPCR is..,1: Fuse word 13 loading through BSEC_OTPCR is.." bitfld.long 0x0 12. "SRLOCK12,sticky reload lock for fuse word 12" "0: Fuse word 12 loading through BSEC_OTPCR is..,1: Fuse word 12 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 11. "SRLOCK11,sticky reload lock for fuse word 11" "0: Fuse word 11 loading through BSEC_OTPCR is..,1: Fuse word 11 loading through BSEC_OTPCR is.." bitfld.long 0x0 10. "SRLOCK10,sticky reload lock for fuse word 10" "0: Fuse word 10 loading through BSEC_OTPCR is..,1: Fuse word 10 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 9. "SRLOCK9,sticky reload lock for fuse word 9" "0: Fuse word 9 loading through BSEC_OTPCR is..,1: Fuse word 9 loading through BSEC_OTPCR is denied.." bitfld.long 0x0 8. "SRLOCK8,sticky reload lock for fuse word 8" "0: Fuse word 8 loading through BSEC_OTPCR is..,1: Fuse word 8 loading through BSEC_OTPCR is denied.." newline bitfld.long 0x0 7. "SRLOCK7,sticky reload lock for fuse word 7" "0: Fuse word 7 loading through BSEC_OTPCR is..,1: Fuse word 7 loading through BSEC_OTPCR is denied.." bitfld.long 0x0 6. "SRLOCK6,sticky reload lock for fuse word 6" "0: Fuse word 6 loading through BSEC_OTPCR is..,1: Fuse word 6 loading through BSEC_OTPCR is denied.." newline bitfld.long 0x0 5. "SRLOCK5,sticky reload lock for fuse word 5" "0: Fuse word 5 loading through BSEC_OTPCR is..,1: Fuse word 5 loading through BSEC_OTPCR is denied.." bitfld.long 0x0 4. "SRLOCK4,sticky reload lock for fuse word 4" "0: Fuse word 4 loading through BSEC_OTPCR is..,1: Fuse word 4 loading through BSEC_OTPCR is denied.." newline bitfld.long 0x0 3. "SRLOCK3,sticky reload lock for fuse word 3" "0: Fuse word 3 loading through BSEC_OTPCR is..,1: Fuse word 3 loading through BSEC_OTPCR is denied.." bitfld.long 0x0 2. "SRLOCK2,sticky reload lock for fuse word 2" "0: Fuse word 2 loading through BSEC_OTPCR is..,1: Fuse word 2 loading through BSEC_OTPCR is denied.." newline bitfld.long 0x0 1. "SRLOCK1,sticky reload lock for fuse word 1" "0: Fuse word 1 loading through BSEC_OTPCR is..,1: Fuse word 1 loading through BSEC_OTPCR is denied.." bitfld.long 0x0 0. "SRLOCK0,sticky reload lock for fuse word 0" "0: Fuse word 0 loading through BSEC_OTPCR is..,1: Fuse word 0 loading through BSEC_OTPCR is denied.." line.long 0x4 "BSEC_SRLOCK1,BSEC sticky reload lock register 1" bitfld.long 0x4 31. "SRLOCK63,sticky reload lock for fuse word 63" "0: Fuse word 63 loading through BSEC_OTPCR is..,1: Fuse word 63 loading through BSEC_OTPCR is.." bitfld.long 0x4 30. "SRLOCK62,sticky reload lock for fuse word 62" "0: Fuse word 62 loading through BSEC_OTPCR is..,1: Fuse word 62 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 29. "SRLOCK61,sticky reload lock for fuse word 61" "0: Fuse word 61 loading through BSEC_OTPCR is..,1: Fuse word 61 loading through BSEC_OTPCR is.." bitfld.long 0x4 28. "SRLOCK60,sticky reload lock for fuse word 60" "0: Fuse word 60 loading through BSEC_OTPCR is..,1: Fuse word 60 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 27. "SRLOCK59,sticky reload lock for fuse word 59" "0: Fuse word 59 loading through BSEC_OTPCR is..,1: Fuse word 59 loading through BSEC_OTPCR is.." bitfld.long 0x4 26. "SRLOCK58,sticky reload lock for fuse word 58" "0: Fuse word 58 loading through BSEC_OTPCR is..,1: Fuse word 58 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 25. "SRLOCK57,sticky reload lock for fuse word 57" "0: Fuse word 57 loading through BSEC_OTPCR is..,1: Fuse word 57 loading through BSEC_OTPCR is.." bitfld.long 0x4 24. "SRLOCK56,sticky reload lock for fuse word 56" "0: Fuse word 56 loading through BSEC_OTPCR is..,1: Fuse word 56 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 23. "SRLOCK55,sticky reload lock for fuse word 55" "0: Fuse word 55 loading through BSEC_OTPCR is..,1: Fuse word 55 loading through BSEC_OTPCR is.." bitfld.long 0x4 22. "SRLOCK54,sticky reload lock for fuse word 54" "0: Fuse word 54 loading through BSEC_OTPCR is..,1: Fuse word 54 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 21. "SRLOCK53,sticky reload lock for fuse word 53" "0: Fuse word 53 loading through BSEC_OTPCR is..,1: Fuse word 53 loading through BSEC_OTPCR is.." bitfld.long 0x4 20. "SRLOCK52,sticky reload lock for fuse word 52" "0: Fuse word 52 loading through BSEC_OTPCR is..,1: Fuse word 52 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 19. "SRLOCK51,sticky reload lock for fuse word 51" "0: Fuse word 51 loading through BSEC_OTPCR is..,1: Fuse word 51 loading through BSEC_OTPCR is.." bitfld.long 0x4 18. "SRLOCK50,sticky reload lock for fuse word 50" "0: Fuse word 50 loading through BSEC_OTPCR is..,1: Fuse word 50 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 17. "SRLOCK49,sticky reload lock for fuse word 49" "0: Fuse word 49 loading through BSEC_OTPCR is..,1: Fuse word 49 loading through BSEC_OTPCR is.." bitfld.long 0x4 16. "SRLOCK48,sticky reload lock for fuse word 48" "0: Fuse word 48 loading through BSEC_OTPCR is..,1: Fuse word 48 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 15. "SRLOCK47,sticky reload lock for fuse word 47" "0: Fuse word 47 loading through BSEC_OTPCR is..,1: Fuse word 47 loading through BSEC_OTPCR is.." bitfld.long 0x4 14. "SRLOCK46,sticky reload lock for fuse word 46" "0: Fuse word 46 loading through BSEC_OTPCR is..,1: Fuse word 46 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 13. "SRLOCK45,sticky reload lock for fuse word 45" "0: Fuse word 45 loading through BSEC_OTPCR is..,1: Fuse word 45 loading through BSEC_OTPCR is.." bitfld.long 0x4 12. "SRLOCK44,sticky reload lock for fuse word 44" "0: Fuse word 44 loading through BSEC_OTPCR is..,1: Fuse word 44 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 11. "SRLOCK43,sticky reload lock for fuse word 43" "0: Fuse word 43 loading through BSEC_OTPCR is..,1: Fuse word 43 loading through BSEC_OTPCR is.." bitfld.long 0x4 10. "SRLOCK42,sticky reload lock for fuse word 42" "0: Fuse word 42 loading through BSEC_OTPCR is..,1: Fuse word 42 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 9. "SRLOCK41,sticky reload lock for fuse word 41" "0: Fuse word 41 loading through BSEC_OTPCR is..,1: Fuse word 41 loading through BSEC_OTPCR is.." bitfld.long 0x4 8. "SRLOCK40,sticky reload lock for fuse word 40" "0: Fuse word 40 loading through BSEC_OTPCR is..,1: Fuse word 40 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 7. "SRLOCK39,sticky reload lock for fuse word 39" "0: Fuse word 39 loading through BSEC_OTPCR is..,1: Fuse word 39 loading through BSEC_OTPCR is.." bitfld.long 0x4 6. "SRLOCK38,sticky reload lock for fuse word 38" "0: Fuse word 38 loading through BSEC_OTPCR is..,1: Fuse word 38 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 5. "SRLOCK37,sticky reload lock for fuse word 37" "0: Fuse word 37 loading through BSEC_OTPCR is..,1: Fuse word 37 loading through BSEC_OTPCR is.." bitfld.long 0x4 4. "SRLOCK36,sticky reload lock for fuse word 36" "0: Fuse word 36 loading through BSEC_OTPCR is..,1: Fuse word 36 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 3. "SRLOCK35,sticky reload lock for fuse word 35" "0: Fuse word 35 loading through BSEC_OTPCR is..,1: Fuse word 35 loading through BSEC_OTPCR is.." bitfld.long 0x4 2. "SRLOCK34,sticky reload lock for fuse word 34" "0: Fuse word 34 loading through BSEC_OTPCR is..,1: Fuse word 34 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 1. "SRLOCK33,sticky reload lock for fuse word 33" "0: Fuse word 33 loading through BSEC_OTPCR is..,1: Fuse word 33 loading through BSEC_OTPCR is.." bitfld.long 0x4 0. "SRLOCK32,sticky reload lock for fuse word 32" "0: Fuse word 32 loading through BSEC_OTPCR is..,1: Fuse word 32 loading through BSEC_OTPCR is.." line.long 0x8 "BSEC_SRLOCK2,BSEC sticky reload lock register 2" bitfld.long 0x8 31. "SRLOCK95,sticky reload lock for fuse word 95" "0: Fuse word 95 loading through BSEC_OTPCR is..,1: Fuse word 95 loading through BSEC_OTPCR is.." bitfld.long 0x8 30. "SRLOCK94,sticky reload lock for fuse word 94" "0: Fuse word 94 loading through BSEC_OTPCR is..,1: Fuse word 94 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 29. "SRLOCK93,sticky reload lock for fuse word 93" "0: Fuse word 93 loading through BSEC_OTPCR is..,1: Fuse word 93 loading through BSEC_OTPCR is.." bitfld.long 0x8 28. "SRLOCK92,sticky reload lock for fuse word 92" "0: Fuse word 92 loading through BSEC_OTPCR is..,1: Fuse word 92 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 27. "SRLOCK91,sticky reload lock for fuse word 91" "0: Fuse word 91 loading through BSEC_OTPCR is..,1: Fuse word 91 loading through BSEC_OTPCR is.." bitfld.long 0x8 26. "SRLOCK90,sticky reload lock for fuse word 90" "0: Fuse word 90 loading through BSEC_OTPCR is..,1: Fuse word 90 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 25. "SRLOCK89,sticky reload lock for fuse word 89" "0: Fuse word 89 loading through BSEC_OTPCR is..,1: Fuse word 89 loading through BSEC_OTPCR is.." bitfld.long 0x8 24. "SRLOCK88,sticky reload lock for fuse word 88" "0: Fuse word 88 loading through BSEC_OTPCR is..,1: Fuse word 88 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 23. "SRLOCK87,sticky reload lock for fuse word 87" "0: Fuse word 87 loading through BSEC_OTPCR is..,1: Fuse word 87 loading through BSEC_OTPCR is.." bitfld.long 0x8 22. "SRLOCK86,sticky reload lock for fuse word 86" "0: Fuse word 86 loading through BSEC_OTPCR is..,1: Fuse word 86 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 21. "SRLOCK85,sticky reload lock for fuse word 85" "0: Fuse word 85 loading through BSEC_OTPCR is..,1: Fuse word 85 loading through BSEC_OTPCR is.." bitfld.long 0x8 20. "SRLOCK84,sticky reload lock for fuse word 84" "0: Fuse word 84 loading through BSEC_OTPCR is..,1: Fuse word 84 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 19. "SRLOCK83,sticky reload lock for fuse word 83" "0: Fuse word 83 loading through BSEC_OTPCR is..,1: Fuse word 83 loading through BSEC_OTPCR is.." bitfld.long 0x8 18. "SRLOCK82,sticky reload lock for fuse word 82" "0: Fuse word 82 loading through BSEC_OTPCR is..,1: Fuse word 82 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 17. "SRLOCK81,sticky reload lock for fuse word 81" "0: Fuse word 81 loading through BSEC_OTPCR is..,1: Fuse word 81 loading through BSEC_OTPCR is.." bitfld.long 0x8 16. "SRLOCK80,sticky reload lock for fuse word 80" "0: Fuse word 80 loading through BSEC_OTPCR is..,1: Fuse word 80 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 15. "SRLOCK79,sticky reload lock for fuse word 79" "0: Fuse word 79 loading through BSEC_OTPCR is..,1: Fuse word 79 loading through BSEC_OTPCR is.." bitfld.long 0x8 14. "SRLOCK78,sticky reload lock for fuse word 78" "0: Fuse word 78 loading through BSEC_OTPCR is..,1: Fuse word 78 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 13. "SRLOCK77,sticky reload lock for fuse word 77" "0: Fuse word 77 loading through BSEC_OTPCR is..,1: Fuse word 77 loading through BSEC_OTPCR is.." bitfld.long 0x8 12. "SRLOCK76,sticky reload lock for fuse word 76" "0: Fuse word 76 loading through BSEC_OTPCR is..,1: Fuse word 76 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 11. "SRLOCK75,sticky reload lock for fuse word 75" "0: Fuse word 75 loading through BSEC_OTPCR is..,1: Fuse word 75 loading through BSEC_OTPCR is.." bitfld.long 0x8 10. "SRLOCK74,sticky reload lock for fuse word 74" "0: Fuse word 74 loading through BSEC_OTPCR is..,1: Fuse word 74 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 9. "SRLOCK73,sticky reload lock for fuse word 73" "0: Fuse word 73 loading through BSEC_OTPCR is..,1: Fuse word 73 loading through BSEC_OTPCR is.." bitfld.long 0x8 8. "SRLOCK72,sticky reload lock for fuse word 72" "0: Fuse word 72 loading through BSEC_OTPCR is..,1: Fuse word 72 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 7. "SRLOCK71,sticky reload lock for fuse word 71" "0: Fuse word 71 loading through BSEC_OTPCR is..,1: Fuse word 71 loading through BSEC_OTPCR is.." bitfld.long 0x8 6. "SRLOCK70,sticky reload lock for fuse word 70" "0: Fuse word 70 loading through BSEC_OTPCR is..,1: Fuse word 70 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 5. "SRLOCK69,sticky reload lock for fuse word 69" "0: Fuse word 69 loading through BSEC_OTPCR is..,1: Fuse word 69 loading through BSEC_OTPCR is.." bitfld.long 0x8 4. "SRLOCK68,sticky reload lock for fuse word 68" "0: Fuse word 68 loading through BSEC_OTPCR is..,1: Fuse word 68 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 3. "SRLOCK67,sticky reload lock for fuse word 67" "0: Fuse word 67 loading through BSEC_OTPCR is..,1: Fuse word 67 loading through BSEC_OTPCR is.." bitfld.long 0x8 2. "SRLOCK66,sticky reload lock for fuse word 66" "0: Fuse word 66 loading through BSEC_OTPCR is..,1: Fuse word 66 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 1. "SRLOCK65,sticky reload lock for fuse word 65" "0: Fuse word 65 loading through BSEC_OTPCR is..,1: Fuse word 65 loading through BSEC_OTPCR is.." bitfld.long 0x8 0. "SRLOCK64,sticky reload lock for fuse word 64" "0: Fuse word 64 loading through BSEC_OTPCR is..,1: Fuse word 64 loading through BSEC_OTPCR is.." line.long 0xC "BSEC_SRLOCK3,BSEC sticky reload lock register 3" bitfld.long 0xC 31. "SRLOCK127,sticky reload lock for fuse word 127" "0: Fuse word 127 loading through BSEC_OTPCR is..,1: Fuse word 127 loading through BSEC_OTPCR is.." bitfld.long 0xC 30. "SRLOCK126,sticky reload lock for fuse word 126" "0: Fuse word 126 loading through BSEC_OTPCR is..,1: Fuse word 126 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 29. "SRLOCK125,sticky reload lock for fuse word 125" "0: Fuse word 125 loading through BSEC_OTPCR is..,1: Fuse word 125 loading through BSEC_OTPCR is.." bitfld.long 0xC 28. "SRLOCK124,sticky reload lock for fuse word 124" "0: Fuse word 124 loading through BSEC_OTPCR is..,1: Fuse word 124 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 27. "SRLOCK123,sticky reload lock for fuse word 123" "0: Fuse word 123 loading through BSEC_OTPCR is..,1: Fuse word 123 loading through BSEC_OTPCR is.." bitfld.long 0xC 26. "SRLOCK122,sticky reload lock for fuse word 122" "0: Fuse word 122 loading through BSEC_OTPCR is..,1: Fuse word 122 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 25. "SRLOCK121,sticky reload lock for fuse word 121" "0: Fuse word 121 loading through BSEC_OTPCR is..,1: Fuse word 121 loading through BSEC_OTPCR is.." bitfld.long 0xC 24. "SRLOCK120,sticky reload lock for fuse word 120" "0: Fuse word 120 loading through BSEC_OTPCR is..,1: Fuse word 120 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 23. "SRLOCK119,sticky reload lock for fuse word 119" "0: Fuse word 119 loading through BSEC_OTPCR is..,1: Fuse word 119 loading through BSEC_OTPCR is.." bitfld.long 0xC 22. "SRLOCK118,sticky reload lock for fuse word 118" "0: Fuse word 118 loading through BSEC_OTPCR is..,1: Fuse word 118 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 21. "SRLOCK117,sticky reload lock for fuse word 117" "0: Fuse word 117 loading through BSEC_OTPCR is..,1: Fuse word 117 loading through BSEC_OTPCR is.." bitfld.long 0xC 20. "SRLOCK116,sticky reload lock for fuse word 116" "0: Fuse word 116 loading through BSEC_OTPCR is..,1: Fuse word 116 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 19. "SRLOCK115,sticky reload lock for fuse word 115" "0: Fuse word 115 loading through BSEC_OTPCR is..,1: Fuse word 115 loading through BSEC_OTPCR is.." bitfld.long 0xC 18. "SRLOCK114,sticky reload lock for fuse word 114" "0: Fuse word 114 loading through BSEC_OTPCR is..,1: Fuse word 114 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 17. "SRLOCK113,sticky reload lock for fuse word 113" "0: Fuse word 113 loading through BSEC_OTPCR is..,1: Fuse word 113 loading through BSEC_OTPCR is.." bitfld.long 0xC 16. "SRLOCK112,sticky reload lock for fuse word 112" "0: Fuse word 112 loading through BSEC_OTPCR is..,1: Fuse word 112 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 15. "SRLOCK111,sticky reload lock for fuse word 111" "0: Fuse word 111 loading through BSEC_OTPCR is..,1: Fuse word 111 loading through BSEC_OTPCR is.." bitfld.long 0xC 14. "SRLOCK110,sticky reload lock for fuse word 110" "0: Fuse word 110 loading through BSEC_OTPCR is..,1: Fuse word 110 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 13. "SRLOCK109,sticky reload lock for fuse word 109" "0: Fuse word 109 loading through BSEC_OTPCR is..,1: Fuse word 109 loading through BSEC_OTPCR is.." bitfld.long 0xC 12. "SRLOCK108,sticky reload lock for fuse word 108" "0: Fuse word 108 loading through BSEC_OTPCR is..,1: Fuse word 108 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 11. "SRLOCK107,sticky reload lock for fuse word 107" "0: Fuse word 107 loading through BSEC_OTPCR is..,1: Fuse word 107 loading through BSEC_OTPCR is.." bitfld.long 0xC 10. "SRLOCK106,sticky reload lock for fuse word 106" "0: Fuse word 106 loading through BSEC_OTPCR is..,1: Fuse word 106 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 9. "SRLOCK105,sticky reload lock for fuse word 105" "0: Fuse word 105 loading through BSEC_OTPCR is..,1: Fuse word 105 loading through BSEC_OTPCR is.." bitfld.long 0xC 8. "SRLOCK104,sticky reload lock for fuse word 104" "0: Fuse word 104 loading through BSEC_OTPCR is..,1: Fuse word 104 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 7. "SRLOCK103,sticky reload lock for fuse word 103" "0: Fuse word 103 loading through BSEC_OTPCR is..,1: Fuse word 103 loading through BSEC_OTPCR is.." bitfld.long 0xC 6. "SRLOCK102,sticky reload lock for fuse word 102" "0: Fuse word 102 loading through BSEC_OTPCR is..,1: Fuse word 102 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 5. "SRLOCK101,sticky reload lock for fuse word 101" "0: Fuse word 101 loading through BSEC_OTPCR is..,1: Fuse word 101 loading through BSEC_OTPCR is.." bitfld.long 0xC 4. "SRLOCK100,sticky reload lock for fuse word 100" "0: Fuse word 100 loading through BSEC_OTPCR is..,1: Fuse word 100 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 3. "SRLOCK99,sticky reload lock for fuse word 99" "0: Fuse word 99 loading through BSEC_OTPCR is..,1: Fuse word 99 loading through BSEC_OTPCR is.." bitfld.long 0xC 2. "SRLOCK98,sticky reload lock for fuse word 98" "0: Fuse word 98 loading through BSEC_OTPCR is..,1: Fuse word 98 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 1. "SRLOCK97,sticky reload lock for fuse word 97" "0: Fuse word 97 loading through BSEC_OTPCR is..,1: Fuse word 97 loading through BSEC_OTPCR is.." bitfld.long 0xC 0. "SRLOCK96,sticky reload lock for fuse word 96" "0: Fuse word 96 loading through BSEC_OTPCR is..,1: Fuse word 96 loading through BSEC_OTPCR is.." line.long 0x10 "BSEC_SRLOCK4,BSEC sticky reload lock register 4" bitfld.long 0x10 31. "SRLOCK159,sticky reload lock for fuse word 159" "0: Fuse word 159 loading through BSEC_OTPCR is..,1: Fuse word 159 loading through BSEC_OTPCR is.." bitfld.long 0x10 30. "SRLOCK158,sticky reload lock for fuse word 158" "0: Fuse word 158 loading through BSEC_OTPCR is..,1: Fuse word 158 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 29. "SRLOCK157,sticky reload lock for fuse word 157" "0: Fuse word 157 loading through BSEC_OTPCR is..,1: Fuse word 157 loading through BSEC_OTPCR is.." bitfld.long 0x10 28. "SRLOCK156,sticky reload lock for fuse word 156" "0: Fuse word 156 loading through BSEC_OTPCR is..,1: Fuse word 156 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 27. "SRLOCK155,sticky reload lock for fuse word 155" "0: Fuse word 155 loading through BSEC_OTPCR is..,1: Fuse word 155 loading through BSEC_OTPCR is.." bitfld.long 0x10 26. "SRLOCK154,sticky reload lock for fuse word 154" "0: Fuse word 154 loading through BSEC_OTPCR is..,1: Fuse word 154 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 25. "SRLOCK153,sticky reload lock for fuse word 153" "0: Fuse word 153 loading through BSEC_OTPCR is..,1: Fuse word 153 loading through BSEC_OTPCR is.." bitfld.long 0x10 24. "SRLOCK152,sticky reload lock for fuse word 152" "0: Fuse word 152 loading through BSEC_OTPCR is..,1: Fuse word 152 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 23. "SRLOCK151,sticky reload lock for fuse word 151" "0: Fuse word 151 loading through BSEC_OTPCR is..,1: Fuse word 151 loading through BSEC_OTPCR is.." bitfld.long 0x10 22. "SRLOCK150,sticky reload lock for fuse word 150" "0: Fuse word 150 loading through BSEC_OTPCR is..,1: Fuse word 150 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 21. "SRLOCK149,sticky reload lock for fuse word 149" "0: Fuse word 149 loading through BSEC_OTPCR is..,1: Fuse word 149 loading through BSEC_OTPCR is.." bitfld.long 0x10 20. "SRLOCK148,sticky reload lock for fuse word 148" "0: Fuse word 148 loading through BSEC_OTPCR is..,1: Fuse word 148 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 19. "SRLOCK147,sticky reload lock for fuse word 147" "0: Fuse word 147 loading through BSEC_OTPCR is..,1: Fuse word 147 loading through BSEC_OTPCR is.." bitfld.long 0x10 18. "SRLOCK146,sticky reload lock for fuse word 146" "0: Fuse word 146 loading through BSEC_OTPCR is..,1: Fuse word 146 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 17. "SRLOCK145,sticky reload lock for fuse word 145" "0: Fuse word 145 loading through BSEC_OTPCR is..,1: Fuse word 145 loading through BSEC_OTPCR is.." bitfld.long 0x10 16. "SRLOCK144,sticky reload lock for fuse word 144" "0: Fuse word 144 loading through BSEC_OTPCR is..,1: Fuse word 144 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 15. "SRLOCK143,sticky reload lock for fuse word 143" "0: Fuse word 143 loading through BSEC_OTPCR is..,1: Fuse word 143 loading through BSEC_OTPCR is.." bitfld.long 0x10 14. "SRLOCK142,sticky reload lock for fuse word 142" "0: Fuse word 142 loading through BSEC_OTPCR is..,1: Fuse word 142 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 13. "SRLOCK141,sticky reload lock for fuse word 141" "0: Fuse word 141 loading through BSEC_OTPCR is..,1: Fuse word 141 loading through BSEC_OTPCR is.." bitfld.long 0x10 12. "SRLOCK140,sticky reload lock for fuse word 140" "0: Fuse word 140 loading through BSEC_OTPCR is..,1: Fuse word 140 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 11. "SRLOCK139,sticky reload lock for fuse word 139" "0: Fuse word 139 loading through BSEC_OTPCR is..,1: Fuse word 139 loading through BSEC_OTPCR is.." bitfld.long 0x10 10. "SRLOCK138,sticky reload lock for fuse word 138" "0: Fuse word 138 loading through BSEC_OTPCR is..,1: Fuse word 138 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 9. "SRLOCK137,sticky reload lock for fuse word 137" "0: Fuse word 137 loading through BSEC_OTPCR is..,1: Fuse word 137 loading through BSEC_OTPCR is.." bitfld.long 0x10 8. "SRLOCK136,sticky reload lock for fuse word 136" "0: Fuse word 136 loading through BSEC_OTPCR is..,1: Fuse word 136 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 7. "SRLOCK135,sticky reload lock for fuse word 135" "0: Fuse word 135 loading through BSEC_OTPCR is..,1: Fuse word 135 loading through BSEC_OTPCR is.." bitfld.long 0x10 6. "SRLOCK134,sticky reload lock for fuse word 134" "0: Fuse word 134 loading through BSEC_OTPCR is..,1: Fuse word 134 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 5. "SRLOCK133,sticky reload lock for fuse word 133" "0: Fuse word 133 loading through BSEC_OTPCR is..,1: Fuse word 133 loading through BSEC_OTPCR is.." bitfld.long 0x10 4. "SRLOCK132,sticky reload lock for fuse word 132" "0: Fuse word 132 loading through BSEC_OTPCR is..,1: Fuse word 132 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 3. "SRLOCK131,sticky reload lock for fuse word 131" "0: Fuse word 131 loading through BSEC_OTPCR is..,1: Fuse word 131 loading through BSEC_OTPCR is.." bitfld.long 0x10 2. "SRLOCK130,sticky reload lock for fuse word 130" "0: Fuse word 130 loading through BSEC_OTPCR is..,1: Fuse word 130 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 1. "SRLOCK129,sticky reload lock for fuse word 129" "0: Fuse word 129 loading through BSEC_OTPCR is..,1: Fuse word 129 loading through BSEC_OTPCR is.." bitfld.long 0x10 0. "SRLOCK128,sticky reload lock for fuse word 128" "0: Fuse word 128 loading through BSEC_OTPCR is..,1: Fuse word 128 loading through BSEC_OTPCR is.." line.long 0x14 "BSEC_SRLOCK5,BSEC sticky reload lock register 5" bitfld.long 0x14 31. "SRLOCK191,sticky reload lock for fuse word 191" "0: Fuse word 191 loading through BSEC_OTPCR is..,1: Fuse word 191 loading through BSEC_OTPCR is.." bitfld.long 0x14 30. "SRLOCK190,sticky reload lock for fuse word 190" "0: Fuse word 190 loading through BSEC_OTPCR is..,1: Fuse word 190 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 29. "SRLOCK189,sticky reload lock for fuse word 189" "0: Fuse word 189 loading through BSEC_OTPCR is..,1: Fuse word 189 loading through BSEC_OTPCR is.." bitfld.long 0x14 28. "SRLOCK188,sticky reload lock for fuse word 188" "0: Fuse word 188 loading through BSEC_OTPCR is..,1: Fuse word 188 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 27. "SRLOCK187,sticky reload lock for fuse word 187" "0: Fuse word 187 loading through BSEC_OTPCR is..,1: Fuse word 187 loading through BSEC_OTPCR is.." bitfld.long 0x14 26. "SRLOCK186,sticky reload lock for fuse word 186" "0: Fuse word 186 loading through BSEC_OTPCR is..,1: Fuse word 186 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 25. "SRLOCK185,sticky reload lock for fuse word 185" "0: Fuse word 185 loading through BSEC_OTPCR is..,1: Fuse word 185 loading through BSEC_OTPCR is.." bitfld.long 0x14 24. "SRLOCK184,sticky reload lock for fuse word 184" "0: Fuse word 184 loading through BSEC_OTPCR is..,1: Fuse word 184 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 23. "SRLOCK183,sticky reload lock for fuse word 183" "0: Fuse word 183 loading through BSEC_OTPCR is..,1: Fuse word 183 loading through BSEC_OTPCR is.." bitfld.long 0x14 22. "SRLOCK182,sticky reload lock for fuse word 182" "0: Fuse word 182 loading through BSEC_OTPCR is..,1: Fuse word 182 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 21. "SRLOCK181,sticky reload lock for fuse word 181" "0: Fuse word 181 loading through BSEC_OTPCR is..,1: Fuse word 181 loading through BSEC_OTPCR is.." bitfld.long 0x14 20. "SRLOCK180,sticky reload lock for fuse word 180" "0: Fuse word 180 loading through BSEC_OTPCR is..,1: Fuse word 180 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 19. "SRLOCK179,sticky reload lock for fuse word 179" "0: Fuse word 179 loading through BSEC_OTPCR is..,1: Fuse word 179 loading through BSEC_OTPCR is.." bitfld.long 0x14 18. "SRLOCK178,sticky reload lock for fuse word 178" "0: Fuse word 178 loading through BSEC_OTPCR is..,1: Fuse word 178 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 17. "SRLOCK177,sticky reload lock for fuse word 177" "0: Fuse word 177 loading through BSEC_OTPCR is..,1: Fuse word 177 loading through BSEC_OTPCR is.." bitfld.long 0x14 16. "SRLOCK176,sticky reload lock for fuse word 176" "0: Fuse word 176 loading through BSEC_OTPCR is..,1: Fuse word 176 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 15. "SRLOCK175,sticky reload lock for fuse word 175" "0: Fuse word 175 loading through BSEC_OTPCR is..,1: Fuse word 175 loading through BSEC_OTPCR is.." bitfld.long 0x14 14. "SRLOCK174,sticky reload lock for fuse word 174" "0: Fuse word 174 loading through BSEC_OTPCR is..,1: Fuse word 174 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 13. "SRLOCK173,sticky reload lock for fuse word 173" "0: Fuse word 173 loading through BSEC_OTPCR is..,1: Fuse word 173 loading through BSEC_OTPCR is.." bitfld.long 0x14 12. "SRLOCK172,sticky reload lock for fuse word 172" "0: Fuse word 172 loading through BSEC_OTPCR is..,1: Fuse word 172 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 11. "SRLOCK171,sticky reload lock for fuse word 171" "0: Fuse word 171 loading through BSEC_OTPCR is..,1: Fuse word 171 loading through BSEC_OTPCR is.." bitfld.long 0x14 10. "SRLOCK170,sticky reload lock for fuse word 170" "0: Fuse word 170 loading through BSEC_OTPCR is..,1: Fuse word 170 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 9. "SRLOCK169,sticky reload lock for fuse word 169" "0: Fuse word 169 loading through BSEC_OTPCR is..,1: Fuse word 169 loading through BSEC_OTPCR is.." bitfld.long 0x14 8. "SRLOCK168,sticky reload lock for fuse word 168" "0: Fuse word 168 loading through BSEC_OTPCR is..,1: Fuse word 168 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 7. "SRLOCK167,sticky reload lock for fuse word 167" "0: Fuse word 167 loading through BSEC_OTPCR is..,1: Fuse word 167 loading through BSEC_OTPCR is.." bitfld.long 0x14 6. "SRLOCK166,sticky reload lock for fuse word 166" "0: Fuse word 166 loading through BSEC_OTPCR is..,1: Fuse word 166 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 5. "SRLOCK165,sticky reload lock for fuse word 165" "0: Fuse word 165 loading through BSEC_OTPCR is..,1: Fuse word 165 loading through BSEC_OTPCR is.." bitfld.long 0x14 4. "SRLOCK164,sticky reload lock for fuse word 164" "0: Fuse word 164 loading through BSEC_OTPCR is..,1: Fuse word 164 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 3. "SRLOCK163,sticky reload lock for fuse word 163" "0: Fuse word 163 loading through BSEC_OTPCR is..,1: Fuse word 163 loading through BSEC_OTPCR is.." bitfld.long 0x14 2. "SRLOCK162,sticky reload lock for fuse word 162" "0: Fuse word 162 loading through BSEC_OTPCR is..,1: Fuse word 162 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 1. "SRLOCK161,sticky reload lock for fuse word 161" "0: Fuse word 161 loading through BSEC_OTPCR is..,1: Fuse word 161 loading through BSEC_OTPCR is.." bitfld.long 0x14 0. "SRLOCK160,sticky reload lock for fuse word 160" "0: Fuse word 160 loading through BSEC_OTPCR is..,1: Fuse word 160 loading through BSEC_OTPCR is.." line.long 0x18 "BSEC_SRLOCK6,BSEC sticky reload lock register 6" bitfld.long 0x18 31. "SRLOCK223,sticky reload lock for fuse word 223" "0: Fuse word 223 loading through BSEC_OTPCR is..,1: Fuse word 223 loading through BSEC_OTPCR is.." bitfld.long 0x18 30. "SRLOCK222,sticky reload lock for fuse word 222" "0: Fuse word 222 loading through BSEC_OTPCR is..,1: Fuse word 222 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 29. "SRLOCK221,sticky reload lock for fuse word 221" "0: Fuse word 221 loading through BSEC_OTPCR is..,1: Fuse word 221 loading through BSEC_OTPCR is.." bitfld.long 0x18 28. "SRLOCK220,sticky reload lock for fuse word 220" "0: Fuse word 220 loading through BSEC_OTPCR is..,1: Fuse word 220 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 27. "SRLOCK219,sticky reload lock for fuse word 219" "0: Fuse word 219 loading through BSEC_OTPCR is..,1: Fuse word 219 loading through BSEC_OTPCR is.." bitfld.long 0x18 26. "SRLOCK218,sticky reload lock for fuse word 218" "0: Fuse word 218 loading through BSEC_OTPCR is..,1: Fuse word 218 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 25. "SRLOCK217,sticky reload lock for fuse word 217" "0: Fuse word 217 loading through BSEC_OTPCR is..,1: Fuse word 217 loading through BSEC_OTPCR is.." bitfld.long 0x18 24. "SRLOCK216,sticky reload lock for fuse word 216" "0: Fuse word 216 loading through BSEC_OTPCR is..,1: Fuse word 216 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 23. "SRLOCK215,sticky reload lock for fuse word 215" "0: Fuse word 215 loading through BSEC_OTPCR is..,1: Fuse word 215 loading through BSEC_OTPCR is.." bitfld.long 0x18 22. "SRLOCK214,sticky reload lock for fuse word 214" "0: Fuse word 214 loading through BSEC_OTPCR is..,1: Fuse word 214 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 21. "SRLOCK213,sticky reload lock for fuse word 213" "0: Fuse word 213 loading through BSEC_OTPCR is..,1: Fuse word 213 loading through BSEC_OTPCR is.." bitfld.long 0x18 20. "SRLOCK212,sticky reload lock for fuse word 212" "0: Fuse word 212 loading through BSEC_OTPCR is..,1: Fuse word 212 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 19. "SRLOCK211,sticky reload lock for fuse word 211" "0: Fuse word 211 loading through BSEC_OTPCR is..,1: Fuse word 211 loading through BSEC_OTPCR is.." bitfld.long 0x18 18. "SRLOCK210,sticky reload lock for fuse word 210" "0: Fuse word 210 loading through BSEC_OTPCR is..,1: Fuse word 210 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 17. "SRLOCK209,sticky reload lock for fuse word 209" "0: Fuse word 209 loading through BSEC_OTPCR is..,1: Fuse word 209 loading through BSEC_OTPCR is.." bitfld.long 0x18 16. "SRLOCK208,sticky reload lock for fuse word 208" "0: Fuse word 208 loading through BSEC_OTPCR is..,1: Fuse word 208 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 15. "SRLOCK207,sticky reload lock for fuse word 207" "0: Fuse word 207 loading through BSEC_OTPCR is..,1: Fuse word 207 loading through BSEC_OTPCR is.." bitfld.long 0x18 14. "SRLOCK206,sticky reload lock for fuse word 206" "0: Fuse word 206 loading through BSEC_OTPCR is..,1: Fuse word 206 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 13. "SRLOCK205,sticky reload lock for fuse word 205" "0: Fuse word 205 loading through BSEC_OTPCR is..,1: Fuse word 205 loading through BSEC_OTPCR is.." bitfld.long 0x18 12. "SRLOCK204,sticky reload lock for fuse word 204" "0: Fuse word 204 loading through BSEC_OTPCR is..,1: Fuse word 204 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 11. "SRLOCK203,sticky reload lock for fuse word 203" "0: Fuse word 203 loading through BSEC_OTPCR is..,1: Fuse word 203 loading through BSEC_OTPCR is.." bitfld.long 0x18 10. "SRLOCK202,sticky reload lock for fuse word 202" "0: Fuse word 202 loading through BSEC_OTPCR is..,1: Fuse word 202 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 9. "SRLOCK201,sticky reload lock for fuse word 201" "0: Fuse word 201 loading through BSEC_OTPCR is..,1: Fuse word 201 loading through BSEC_OTPCR is.." bitfld.long 0x18 8. "SRLOCK200,sticky reload lock for fuse word 200" "0: Fuse word 200 loading through BSEC_OTPCR is..,1: Fuse word 200 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 7. "SRLOCK199,sticky reload lock for fuse word 199" "0: Fuse word 199 loading through BSEC_OTPCR is..,1: Fuse word 199 loading through BSEC_OTPCR is.." bitfld.long 0x18 6. "SRLOCK198,sticky reload lock for fuse word 198" "0: Fuse word 198 loading through BSEC_OTPCR is..,1: Fuse word 198 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 5. "SRLOCK197,sticky reload lock for fuse word 197" "0: Fuse word 197 loading through BSEC_OTPCR is..,1: Fuse word 197 loading through BSEC_OTPCR is.." bitfld.long 0x18 4. "SRLOCK196,sticky reload lock for fuse word 196" "0: Fuse word 196 loading through BSEC_OTPCR is..,1: Fuse word 196 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 3. "SRLOCK195,sticky reload lock for fuse word 195" "0: Fuse word 195 loading through BSEC_OTPCR is..,1: Fuse word 195 loading through BSEC_OTPCR is.." bitfld.long 0x18 2. "SRLOCK194,sticky reload lock for fuse word 194" "0: Fuse word 194 loading through BSEC_OTPCR is..,1: Fuse word 194 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 1. "SRLOCK193,sticky reload lock for fuse word 193" "0: Fuse word 193 loading through BSEC_OTPCR is..,1: Fuse word 193 loading through BSEC_OTPCR is.." bitfld.long 0x18 0. "SRLOCK192,sticky reload lock for fuse word 192" "0: Fuse word 192 loading through BSEC_OTPCR is..,1: Fuse word 192 loading through BSEC_OTPCR is.." line.long 0x1C "BSEC_SRLOCK7,BSEC sticky reload lock register 7" bitfld.long 0x1C 31. "SRLOCK255,sticky reload lock for fuse word 255" "0: Fuse word 255 loading through BSEC_OTPCR is..,1: Fuse word 255 loading through BSEC_OTPCR is.." bitfld.long 0x1C 30. "SRLOCK254,sticky reload lock for fuse word 254" "0: Fuse word 254 loading through BSEC_OTPCR is..,1: Fuse word 254 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 29. "SRLOCK253,sticky reload lock for fuse word 253" "0: Fuse word 253 loading through BSEC_OTPCR is..,1: Fuse word 253 loading through BSEC_OTPCR is.." bitfld.long 0x1C 28. "SRLOCK252,sticky reload lock for fuse word 252" "0: Fuse word 252 loading through BSEC_OTPCR is..,1: Fuse word 252 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 27. "SRLOCK251,sticky reload lock for fuse word 251" "0: Fuse word 251 loading through BSEC_OTPCR is..,1: Fuse word 251 loading through BSEC_OTPCR is.." bitfld.long 0x1C 26. "SRLOCK250,sticky reload lock for fuse word 250" "0: Fuse word 250 loading through BSEC_OTPCR is..,1: Fuse word 250 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 25. "SRLOCK249,sticky reload lock for fuse word 249" "0: Fuse word 249 loading through BSEC_OTPCR is..,1: Fuse word 249 loading through BSEC_OTPCR is.." bitfld.long 0x1C 24. "SRLOCK248,sticky reload lock for fuse word 248" "0: Fuse word 248 loading through BSEC_OTPCR is..,1: Fuse word 248 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 23. "SRLOCK247,sticky reload lock for fuse word 247" "0: Fuse word 247 loading through BSEC_OTPCR is..,1: Fuse word 247 loading through BSEC_OTPCR is.." bitfld.long 0x1C 22. "SRLOCK246,sticky reload lock for fuse word 246" "0: Fuse word 246 loading through BSEC_OTPCR is..,1: Fuse word 246 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 21. "SRLOCK245,sticky reload lock for fuse word 245" "0: Fuse word 245 loading through BSEC_OTPCR is..,1: Fuse word 245 loading through BSEC_OTPCR is.." bitfld.long 0x1C 20. "SRLOCK244,sticky reload lock for fuse word 244" "0: Fuse word 244 loading through BSEC_OTPCR is..,1: Fuse word 244 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 19. "SRLOCK243,sticky reload lock for fuse word 243" "0: Fuse word 243 loading through BSEC_OTPCR is..,1: Fuse word 243 loading through BSEC_OTPCR is.." bitfld.long 0x1C 18. "SRLOCK242,sticky reload lock for fuse word 242" "0: Fuse word 242 loading through BSEC_OTPCR is..,1: Fuse word 242 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 17. "SRLOCK241,sticky reload lock for fuse word 241" "0: Fuse word 241 loading through BSEC_OTPCR is..,1: Fuse word 241 loading through BSEC_OTPCR is.." bitfld.long 0x1C 16. "SRLOCK240,sticky reload lock for fuse word 240" "0: Fuse word 240 loading through BSEC_OTPCR is..,1: Fuse word 240 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 15. "SRLOCK239,sticky reload lock for fuse word 239" "0: Fuse word 239 loading through BSEC_OTPCR is..,1: Fuse word 239 loading through BSEC_OTPCR is.." bitfld.long 0x1C 14. "SRLOCK238,sticky reload lock for fuse word 238" "0: Fuse word 238 loading through BSEC_OTPCR is..,1: Fuse word 238 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 13. "SRLOCK237,sticky reload lock for fuse word 237" "0: Fuse word 237 loading through BSEC_OTPCR is..,1: Fuse word 237 loading through BSEC_OTPCR is.." bitfld.long 0x1C 12. "SRLOCK236,sticky reload lock for fuse word 236" "0: Fuse word 236 loading through BSEC_OTPCR is..,1: Fuse word 236 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 11. "SRLOCK235,sticky reload lock for fuse word 235" "0: Fuse word 235 loading through BSEC_OTPCR is..,1: Fuse word 235 loading through BSEC_OTPCR is.." bitfld.long 0x1C 10. "SRLOCK234,sticky reload lock for fuse word 234" "0: Fuse word 234 loading through BSEC_OTPCR is..,1: Fuse word 234 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 9. "SRLOCK233,sticky reload lock for fuse word 233" "0: Fuse word 233 loading through BSEC_OTPCR is..,1: Fuse word 233 loading through BSEC_OTPCR is.." bitfld.long 0x1C 8. "SRLOCK232,sticky reload lock for fuse word 232" "0: Fuse word 232 loading through BSEC_OTPCR is..,1: Fuse word 232 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 7. "SRLOCK231,sticky reload lock for fuse word 231" "0: Fuse word 231 loading through BSEC_OTPCR is..,1: Fuse word 231 loading through BSEC_OTPCR is.." bitfld.long 0x1C 6. "SRLOCK230,sticky reload lock for fuse word 230" "0: Fuse word 230 loading through BSEC_OTPCR is..,1: Fuse word 230 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 5. "SRLOCK229,sticky reload lock for fuse word 229" "0: Fuse word 229 loading through BSEC_OTPCR is..,1: Fuse word 229 loading through BSEC_OTPCR is.." bitfld.long 0x1C 4. "SRLOCK228,sticky reload lock for fuse word 228" "0: Fuse word 228 loading through BSEC_OTPCR is..,1: Fuse word 228 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 3. "SRLOCK227,sticky reload lock for fuse word 227" "0: Fuse word 227 loading through BSEC_OTPCR is..,1: Fuse word 227 loading through BSEC_OTPCR is.." bitfld.long 0x1C 2. "SRLOCK226,sticky reload lock for fuse word 226" "0: Fuse word 226 loading through BSEC_OTPCR is..,1: Fuse word 226 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 1. "SRLOCK225,sticky reload lock for fuse word 225" "0: Fuse word 225 loading through BSEC_OTPCR is..,1: Fuse word 225 loading through BSEC_OTPCR is.." bitfld.long 0x1C 0. "SRLOCK224,sticky reload lock for fuse word 224" "0: Fuse word 224 loading through BSEC_OTPCR is..,1: Fuse word 224 loading through BSEC_OTPCR is.." line.long 0x20 "BSEC_SRLOCK8,BSEC sticky reload lock register 8" bitfld.long 0x20 31. "SRLOCK287,sticky reload lock for fuse word 287" "0: Fuse word 287 loading through BSEC_OTPCR is..,1: Fuse word 287 loading through BSEC_OTPCR is.." bitfld.long 0x20 30. "SRLOCK286,sticky reload lock for fuse word 286" "0: Fuse word 286 loading through BSEC_OTPCR is..,1: Fuse word 286 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 29. "SRLOCK285,sticky reload lock for fuse word 285" "0: Fuse word 285 loading through BSEC_OTPCR is..,1: Fuse word 285 loading through BSEC_OTPCR is.." bitfld.long 0x20 28. "SRLOCK284,sticky reload lock for fuse word 284" "0: Fuse word 284 loading through BSEC_OTPCR is..,1: Fuse word 284 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 27. "SRLOCK283,sticky reload lock for fuse word 283" "0: Fuse word 283 loading through BSEC_OTPCR is..,1: Fuse word 283 loading through BSEC_OTPCR is.." bitfld.long 0x20 26. "SRLOCK282,sticky reload lock for fuse word 282" "0: Fuse word 282 loading through BSEC_OTPCR is..,1: Fuse word 282 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 25. "SRLOCK281,sticky reload lock for fuse word 281" "0: Fuse word 281 loading through BSEC_OTPCR is..,1: Fuse word 281 loading through BSEC_OTPCR is.." bitfld.long 0x20 24. "SRLOCK280,sticky reload lock for fuse word 280" "0: Fuse word 280 loading through BSEC_OTPCR is..,1: Fuse word 280 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 23. "SRLOCK279,sticky reload lock for fuse word 279" "0: Fuse word 279 loading through BSEC_OTPCR is..,1: Fuse word 279 loading through BSEC_OTPCR is.." bitfld.long 0x20 22. "SRLOCK278,sticky reload lock for fuse word 278" "0: Fuse word 278 loading through BSEC_OTPCR is..,1: Fuse word 278 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 21. "SRLOCK277,sticky reload lock for fuse word 277" "0: Fuse word 277 loading through BSEC_OTPCR is..,1: Fuse word 277 loading through BSEC_OTPCR is.." bitfld.long 0x20 20. "SRLOCK276,sticky reload lock for fuse word 276" "0: Fuse word 276 loading through BSEC_OTPCR is..,1: Fuse word 276 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 19. "SRLOCK275,sticky reload lock for fuse word 275" "0: Fuse word 275 loading through BSEC_OTPCR is..,1: Fuse word 275 loading through BSEC_OTPCR is.." bitfld.long 0x20 18. "SRLOCK274,sticky reload lock for fuse word 274" "0: Fuse word 274 loading through BSEC_OTPCR is..,1: Fuse word 274 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 17. "SRLOCK273,sticky reload lock for fuse word 273" "0: Fuse word 273 loading through BSEC_OTPCR is..,1: Fuse word 273 loading through BSEC_OTPCR is.." bitfld.long 0x20 16. "SRLOCK272,sticky reload lock for fuse word 272" "0: Fuse word 272 loading through BSEC_OTPCR is..,1: Fuse word 272 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 15. "SRLOCK271,sticky reload lock for fuse word 271" "0: Fuse word 271 loading through BSEC_OTPCR is..,1: Fuse word 271 loading through BSEC_OTPCR is.." bitfld.long 0x20 14. "SRLOCK270,sticky reload lock for fuse word 270" "0: Fuse word 270 loading through BSEC_OTPCR is..,1: Fuse word 270 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 13. "SRLOCK269,sticky reload lock for fuse word 269" "0: Fuse word 269 loading through BSEC_OTPCR is..,1: Fuse word 269 loading through BSEC_OTPCR is.." bitfld.long 0x20 12. "SRLOCK268,sticky reload lock for fuse word 268" "0: Fuse word 268 loading through BSEC_OTPCR is..,1: Fuse word 268 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 11. "SRLOCK267,sticky reload lock for fuse word 267" "0: Fuse word 267 loading through BSEC_OTPCR is..,1: Fuse word 267 loading through BSEC_OTPCR is.." bitfld.long 0x20 10. "SRLOCK266,sticky reload lock for fuse word 266" "0: Fuse word 266 loading through BSEC_OTPCR is..,1: Fuse word 266 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 9. "SRLOCK265,sticky reload lock for fuse word 265" "0: Fuse word 265 loading through BSEC_OTPCR is..,1: Fuse word 265 loading through BSEC_OTPCR is.." bitfld.long 0x20 8. "SRLOCK264,sticky reload lock for fuse word 264" "0: Fuse word 264 loading through BSEC_OTPCR is..,1: Fuse word 264 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 7. "SRLOCK263,sticky reload lock for fuse word 263" "0: Fuse word 263 loading through BSEC_OTPCR is..,1: Fuse word 263 loading through BSEC_OTPCR is.." bitfld.long 0x20 6. "SRLOCK262,sticky reload lock for fuse word 262" "0: Fuse word 262 loading through BSEC_OTPCR is..,1: Fuse word 262 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 5. "SRLOCK261,sticky reload lock for fuse word 261" "0: Fuse word 261 loading through BSEC_OTPCR is..,1: Fuse word 261 loading through BSEC_OTPCR is.." bitfld.long 0x20 4. "SRLOCK260,sticky reload lock for fuse word 260" "0: Fuse word 260 loading through BSEC_OTPCR is..,1: Fuse word 260 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 3. "SRLOCK259,sticky reload lock for fuse word 259" "0: Fuse word 259 loading through BSEC_OTPCR is..,1: Fuse word 259 loading through BSEC_OTPCR is.." bitfld.long 0x20 2. "SRLOCK258,sticky reload lock for fuse word 258" "0: Fuse word 258 loading through BSEC_OTPCR is..,1: Fuse word 258 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 1. "SRLOCK257,sticky reload lock for fuse word 257" "0: Fuse word 257 loading through BSEC_OTPCR is..,1: Fuse word 257 loading through BSEC_OTPCR is.." bitfld.long 0x20 0. "SRLOCK256,sticky reload lock for fuse word 256" "0: Fuse word 256 loading through BSEC_OTPCR is..,1: Fuse word 256 loading through BSEC_OTPCR is.." line.long 0x24 "BSEC_SRLOCK9,BSEC sticky reload lock register 9" bitfld.long 0x24 31. "SRLOCK319,sticky reload lock for fuse word 319" "0: Fuse word 319 loading through BSEC_OTPCR is..,1: Fuse word 319 loading through BSEC_OTPCR is.." bitfld.long 0x24 30. "SRLOCK318,sticky reload lock for fuse word 318" "0: Fuse word 318 loading through BSEC_OTPCR is..,1: Fuse word 318 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 29. "SRLOCK317,sticky reload lock for fuse word 317" "0: Fuse word 317 loading through BSEC_OTPCR is..,1: Fuse word 317 loading through BSEC_OTPCR is.." bitfld.long 0x24 28. "SRLOCK316,sticky reload lock for fuse word 316" "0: Fuse word 316 loading through BSEC_OTPCR is..,1: Fuse word 316 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 27. "SRLOCK315,sticky reload lock for fuse word 315" "0: Fuse word 315 loading through BSEC_OTPCR is..,1: Fuse word 315 loading through BSEC_OTPCR is.." bitfld.long 0x24 26. "SRLOCK314,sticky reload lock for fuse word 314" "0: Fuse word 314 loading through BSEC_OTPCR is..,1: Fuse word 314 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 25. "SRLOCK313,sticky reload lock for fuse word 313" "0: Fuse word 313 loading through BSEC_OTPCR is..,1: Fuse word 313 loading through BSEC_OTPCR is.." bitfld.long 0x24 24. "SRLOCK312,sticky reload lock for fuse word 312" "0: Fuse word 312 loading through BSEC_OTPCR is..,1: Fuse word 312 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 23. "SRLOCK311,sticky reload lock for fuse word 311" "0: Fuse word 311 loading through BSEC_OTPCR is..,1: Fuse word 311 loading through BSEC_OTPCR is.." bitfld.long 0x24 22. "SRLOCK310,sticky reload lock for fuse word 310" "0: Fuse word 310 loading through BSEC_OTPCR is..,1: Fuse word 310 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 21. "SRLOCK309,sticky reload lock for fuse word 309" "0: Fuse word 309 loading through BSEC_OTPCR is..,1: Fuse word 309 loading through BSEC_OTPCR is.." bitfld.long 0x24 20. "SRLOCK308,sticky reload lock for fuse word 308" "0: Fuse word 308 loading through BSEC_OTPCR is..,1: Fuse word 308 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 19. "SRLOCK307,sticky reload lock for fuse word 307" "0: Fuse word 307 loading through BSEC_OTPCR is..,1: Fuse word 307 loading through BSEC_OTPCR is.." bitfld.long 0x24 18. "SRLOCK306,sticky reload lock for fuse word 306" "0: Fuse word 306 loading through BSEC_OTPCR is..,1: Fuse word 306 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 17. "SRLOCK305,sticky reload lock for fuse word 305" "0: Fuse word 305 loading through BSEC_OTPCR is..,1: Fuse word 305 loading through BSEC_OTPCR is.." bitfld.long 0x24 16. "SRLOCK304,sticky reload lock for fuse word 304" "0: Fuse word 304 loading through BSEC_OTPCR is..,1: Fuse word 304 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 15. "SRLOCK303,sticky reload lock for fuse word 303" "0: Fuse word 303 loading through BSEC_OTPCR is..,1: Fuse word 303 loading through BSEC_OTPCR is.." bitfld.long 0x24 14. "SRLOCK302,sticky reload lock for fuse word 302" "0: Fuse word 302 loading through BSEC_OTPCR is..,1: Fuse word 302 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 13. "SRLOCK301,sticky reload lock for fuse word 301" "0: Fuse word 301 loading through BSEC_OTPCR is..,1: Fuse word 301 loading through BSEC_OTPCR is.." bitfld.long 0x24 12. "SRLOCK300,sticky reload lock for fuse word 300" "0: Fuse word 300 loading through BSEC_OTPCR is..,1: Fuse word 300 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 11. "SRLOCK299,sticky reload lock for fuse word 299" "0: Fuse word 299 loading through BSEC_OTPCR is..,1: Fuse word 299 loading through BSEC_OTPCR is.." bitfld.long 0x24 10. "SRLOCK298,sticky reload lock for fuse word 298" "0: Fuse word 298 loading through BSEC_OTPCR is..,1: Fuse word 298 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 9. "SRLOCK297,sticky reload lock for fuse word 297" "0: Fuse word 297 loading through BSEC_OTPCR is..,1: Fuse word 297 loading through BSEC_OTPCR is.." bitfld.long 0x24 8. "SRLOCK296,sticky reload lock for fuse word 296" "0: Fuse word 296 loading through BSEC_OTPCR is..,1: Fuse word 296 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 7. "SRLOCK295,sticky reload lock for fuse word 295" "0: Fuse word 295 loading through BSEC_OTPCR is..,1: Fuse word 295 loading through BSEC_OTPCR is.." bitfld.long 0x24 6. "SRLOCK294,sticky reload lock for fuse word 294" "0: Fuse word 294 loading through BSEC_OTPCR is..,1: Fuse word 294 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 5. "SRLOCK293,sticky reload lock for fuse word 293" "0: Fuse word 293 loading through BSEC_OTPCR is..,1: Fuse word 293 loading through BSEC_OTPCR is.." bitfld.long 0x24 4. "SRLOCK292,sticky reload lock for fuse word 292" "0: Fuse word 292 loading through BSEC_OTPCR is..,1: Fuse word 292 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 3. "SRLOCK291,sticky reload lock for fuse word 291" "0: Fuse word 291 loading through BSEC_OTPCR is..,1: Fuse word 291 loading through BSEC_OTPCR is.." bitfld.long 0x24 2. "SRLOCK290,sticky reload lock for fuse word 290" "0: Fuse word 290 loading through BSEC_OTPCR is..,1: Fuse word 290 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 1. "SRLOCK289,sticky reload lock for fuse word 289" "0: Fuse word 289 loading through BSEC_OTPCR is..,1: Fuse word 289 loading through BSEC_OTPCR is.." bitfld.long 0x24 0. "SRLOCK288,sticky reload lock for fuse word 288" "0: Fuse word 288 loading through BSEC_OTPCR is..,1: Fuse word 288 loading through BSEC_OTPCR is.." line.long 0x28 "BSEC_SRLOCK10,BSEC sticky reload lock register 10" bitfld.long 0x28 31. "SRLOCK351,sticky reload lock for fuse word 351" "0: Fuse word 351 loading through BSEC_OTPCR is..,1: Fuse word 351 loading through BSEC_OTPCR is.." bitfld.long 0x28 30. "SRLOCK350,sticky reload lock for fuse word 350" "0: Fuse word 350 loading through BSEC_OTPCR is..,1: Fuse word 350 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 29. "SRLOCK349,sticky reload lock for fuse word 349" "0: Fuse word 349 loading through BSEC_OTPCR is..,1: Fuse word 349 loading through BSEC_OTPCR is.." bitfld.long 0x28 28. "SRLOCK348,sticky reload lock for fuse word 348" "0: Fuse word 348 loading through BSEC_OTPCR is..,1: Fuse word 348 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 27. "SRLOCK347,sticky reload lock for fuse word 347" "0: Fuse word 347 loading through BSEC_OTPCR is..,1: Fuse word 347 loading through BSEC_OTPCR is.." bitfld.long 0x28 26. "SRLOCK346,sticky reload lock for fuse word 346" "0: Fuse word 346 loading through BSEC_OTPCR is..,1: Fuse word 346 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 25. "SRLOCK345,sticky reload lock for fuse word 345" "0: Fuse word 345 loading through BSEC_OTPCR is..,1: Fuse word 345 loading through BSEC_OTPCR is.." bitfld.long 0x28 24. "SRLOCK344,sticky reload lock for fuse word 344" "0: Fuse word 344 loading through BSEC_OTPCR is..,1: Fuse word 344 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 23. "SRLOCK343,sticky reload lock for fuse word 343" "0: Fuse word 343 loading through BSEC_OTPCR is..,1: Fuse word 343 loading through BSEC_OTPCR is.." bitfld.long 0x28 22. "SRLOCK342,sticky reload lock for fuse word 342" "0: Fuse word 342 loading through BSEC_OTPCR is..,1: Fuse word 342 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 21. "SRLOCK341,sticky reload lock for fuse word 341" "0: Fuse word 341 loading through BSEC_OTPCR is..,1: Fuse word 341 loading through BSEC_OTPCR is.." bitfld.long 0x28 20. "SRLOCK340,sticky reload lock for fuse word 340" "0: Fuse word 340 loading through BSEC_OTPCR is..,1: Fuse word 340 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 19. "SRLOCK339,sticky reload lock for fuse word 339" "0: Fuse word 339 loading through BSEC_OTPCR is..,1: Fuse word 339 loading through BSEC_OTPCR is.." bitfld.long 0x28 18. "SRLOCK338,sticky reload lock for fuse word 338" "0: Fuse word 338 loading through BSEC_OTPCR is..,1: Fuse word 338 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 17. "SRLOCK337,sticky reload lock for fuse word 337" "0: Fuse word 337 loading through BSEC_OTPCR is..,1: Fuse word 337 loading through BSEC_OTPCR is.." bitfld.long 0x28 16. "SRLOCK336,sticky reload lock for fuse word 336" "0: Fuse word 336 loading through BSEC_OTPCR is..,1: Fuse word 336 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 15. "SRLOCK335,sticky reload lock for fuse word 335" "0: Fuse word 335 loading through BSEC_OTPCR is..,1: Fuse word 335 loading through BSEC_OTPCR is.." bitfld.long 0x28 14. "SRLOCK334,sticky reload lock for fuse word 334" "0: Fuse word 334 loading through BSEC_OTPCR is..,1: Fuse word 334 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 13. "SRLOCK333,sticky reload lock for fuse word 333" "0: Fuse word 333 loading through BSEC_OTPCR is..,1: Fuse word 333 loading through BSEC_OTPCR is.." bitfld.long 0x28 12. "SRLOCK332,sticky reload lock for fuse word 332" "0: Fuse word 332 loading through BSEC_OTPCR is..,1: Fuse word 332 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 11. "SRLOCK331,sticky reload lock for fuse word 331" "0: Fuse word 331 loading through BSEC_OTPCR is..,1: Fuse word 331 loading through BSEC_OTPCR is.." bitfld.long 0x28 10. "SRLOCK330,sticky reload lock for fuse word 330" "0: Fuse word 330 loading through BSEC_OTPCR is..,1: Fuse word 330 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 9. "SRLOCK329,sticky reload lock for fuse word 329" "0: Fuse word 329 loading through BSEC_OTPCR is..,1: Fuse word 329 loading through BSEC_OTPCR is.." bitfld.long 0x28 8. "SRLOCK328,sticky reload lock for fuse word 328" "0: Fuse word 328 loading through BSEC_OTPCR is..,1: Fuse word 328 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 7. "SRLOCK327,sticky reload lock for fuse word 327" "0: Fuse word 327 loading through BSEC_OTPCR is..,1: Fuse word 327 loading through BSEC_OTPCR is.." bitfld.long 0x28 6. "SRLOCK326,sticky reload lock for fuse word 326" "0: Fuse word 326 loading through BSEC_OTPCR is..,1: Fuse word 326 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 5. "SRLOCK325,sticky reload lock for fuse word 325" "0: Fuse word 325 loading through BSEC_OTPCR is..,1: Fuse word 325 loading through BSEC_OTPCR is.." bitfld.long 0x28 4. "SRLOCK324,sticky reload lock for fuse word 324" "0: Fuse word 324 loading through BSEC_OTPCR is..,1: Fuse word 324 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 3. "SRLOCK323,sticky reload lock for fuse word 323" "0: Fuse word 323 loading through BSEC_OTPCR is..,1: Fuse word 323 loading through BSEC_OTPCR is.." bitfld.long 0x28 2. "SRLOCK322,sticky reload lock for fuse word 322" "0: Fuse word 322 loading through BSEC_OTPCR is..,1: Fuse word 322 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 1. "SRLOCK321,sticky reload lock for fuse word 321" "0: Fuse word 321 loading through BSEC_OTPCR is..,1: Fuse word 321 loading through BSEC_OTPCR is.." bitfld.long 0x28 0. "SRLOCK320,sticky reload lock for fuse word 320" "0: Fuse word 320 loading through BSEC_OTPCR is..,1: Fuse word 320 loading through BSEC_OTPCR is.." line.long 0x2C "BSEC_SRLOCK11,BSEC sticky reload lock register 11" bitfld.long 0x2C 31. "SRLOCK383,sticky reload lock for fuse word 383" "0: Fuse word 383 loading through BSEC_OTPCR is..,1: Fuse word 383 loading through BSEC_OTPCR is.." bitfld.long 0x2C 30. "SRLOCK382,sticky reload lock for fuse word 382" "0: Fuse word 382 loading through BSEC_OTPCR is..,1: Fuse word 382 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 29. "SRLOCK381,sticky reload lock for fuse word 381" "0: Fuse word 381 loading through BSEC_OTPCR is..,1: Fuse word 381 loading through BSEC_OTPCR is.." bitfld.long 0x2C 28. "SRLOCK380,sticky reload lock for fuse word 380" "0: Fuse word 380 loading through BSEC_OTPCR is..,1: Fuse word 380 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 27. "SRLOCK379,sticky reload lock for fuse word 379" "0: Fuse word 379 loading through BSEC_OTPCR is..,1: Fuse word 379 loading through BSEC_OTPCR is.." bitfld.long 0x2C 26. "SRLOCK378,sticky reload lock for fuse word 378" "0: Fuse word 378 loading through BSEC_OTPCR is..,1: Fuse word 378 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 25. "SRLOCK377,sticky reload lock for fuse word 377" "0: Fuse word 377 loading through BSEC_OTPCR is..,1: Fuse word 377 loading through BSEC_OTPCR is.." bitfld.long 0x2C 24. "SRLOCK376,sticky reload lock for fuse word 376" "0: Fuse word 376 loading through BSEC_OTPCR is..,1: Fuse word 376 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 23. "SRLOCK375,sticky reload lock for fuse word 375" "0: Fuse word 375 loading through BSEC_OTPCR is..,1: Fuse word 375 loading through BSEC_OTPCR is.." bitfld.long 0x2C 22. "SRLOCK374,sticky reload lock for fuse word 374" "0: Fuse word 374 loading through BSEC_OTPCR is..,1: Fuse word 374 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 21. "SRLOCK373,sticky reload lock for fuse word 373" "0: Fuse word 373 loading through BSEC_OTPCR is..,1: Fuse word 373 loading through BSEC_OTPCR is.." bitfld.long 0x2C 20. "SRLOCK372,sticky reload lock for fuse word 372" "0: Fuse word 372 loading through BSEC_OTPCR is..,1: Fuse word 372 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 19. "SRLOCK371,sticky reload lock for fuse word 371" "0: Fuse word 371 loading through BSEC_OTPCR is..,1: Fuse word 371 loading through BSEC_OTPCR is.." bitfld.long 0x2C 18. "SRLOCK370,sticky reload lock for fuse word 370" "0: Fuse word 370 loading through BSEC_OTPCR is..,1: Fuse word 370 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 17. "SRLOCK369,sticky reload lock for fuse word 369" "0: Fuse word 369 loading through BSEC_OTPCR is..,1: Fuse word 369 loading through BSEC_OTPCR is.." bitfld.long 0x2C 16. "SRLOCK368,sticky reload lock for fuse word 368" "0: Fuse word 368 loading through BSEC_OTPCR is..,1: Fuse word 368 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 15. "SRLOCK367,sticky reload lock for fuse word 367" "0: Fuse word 367 loading through BSEC_OTPCR is..,1: Fuse word 367 loading through BSEC_OTPCR is.." bitfld.long 0x2C 14. "SRLOCK366,sticky reload lock for fuse word 366" "0: Fuse word 366 loading through BSEC_OTPCR is..,1: Fuse word 366 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 13. "SRLOCK365,sticky reload lock for fuse word 365" "0: Fuse word 365 loading through BSEC_OTPCR is..,1: Fuse word 365 loading through BSEC_OTPCR is.." bitfld.long 0x2C 12. "SRLOCK364,sticky reload lock for fuse word 364" "0: Fuse word 364 loading through BSEC_OTPCR is..,1: Fuse word 364 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 11. "SRLOCK363,sticky reload lock for fuse word 363" "0: Fuse word 363 loading through BSEC_OTPCR is..,1: Fuse word 363 loading through BSEC_OTPCR is.." bitfld.long 0x2C 10. "SRLOCK362,sticky reload lock for fuse word 362" "0: Fuse word 362 loading through BSEC_OTPCR is..,1: Fuse word 362 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 9. "SRLOCK361,sticky reload lock for fuse word 361" "0: Fuse word 361 loading through BSEC_OTPCR is..,1: Fuse word 361 loading through BSEC_OTPCR is.." bitfld.long 0x2C 8. "SRLOCK360,sticky reload lock for fuse word 360" "0: Fuse word 360 loading through BSEC_OTPCR is..,1: Fuse word 360 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 7. "SRLOCK359,sticky reload lock for fuse word 359" "0: Fuse word 359 loading through BSEC_OTPCR is..,1: Fuse word 359 loading through BSEC_OTPCR is.." bitfld.long 0x2C 6. "SRLOCK358,sticky reload lock for fuse word 358" "0: Fuse word 358 loading through BSEC_OTPCR is..,1: Fuse word 358 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 5. "SRLOCK357,sticky reload lock for fuse word 357" "0: Fuse word 357 loading through BSEC_OTPCR is..,1: Fuse word 357 loading through BSEC_OTPCR is.." bitfld.long 0x2C 4. "SRLOCK356,sticky reload lock for fuse word 356" "0: Fuse word 356 loading through BSEC_OTPCR is..,1: Fuse word 356 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 3. "SRLOCK355,sticky reload lock for fuse word 355" "0: Fuse word 355 loading through BSEC_OTPCR is..,1: Fuse word 355 loading through BSEC_OTPCR is.." bitfld.long 0x2C 2. "SRLOCK354,sticky reload lock for fuse word 354" "0: Fuse word 354 loading through BSEC_OTPCR is..,1: Fuse word 354 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 1. "SRLOCK353,sticky reload lock for fuse word 353" "0: Fuse word 353 loading through BSEC_OTPCR is..,1: Fuse word 353 loading through BSEC_OTPCR is.." bitfld.long 0x2C 0. "SRLOCK352,sticky reload lock for fuse word 352" "0: Fuse word 352 loading through BSEC_OTPCR is..,1: Fuse word 352 loading through BSEC_OTPCR is.." rgroup.long 0x8C0++0x2F line.long 0x0 "BSEC_OTPVLDR0,BSEC OTP valid register 0" bitfld.long 0x0 31. "VLDF31,Valid flag for shadow register 31" "0: An error occurred while fuse word 31 was last..,1: Last reload of fuse word 31 was done without.." bitfld.long 0x0 30. "VLDF30,Valid flag for shadow register 30" "0: An error occurred while fuse word 30 was last..,1: Last reload of fuse word 30 was done without.." newline bitfld.long 0x0 29. "VLDF29,Valid flag for shadow register 29" "0: An error occurred while fuse word 29 was last..,1: Last reload of fuse word 29 was done without.." bitfld.long 0x0 28. "VLDF28,Valid flag for shadow register 28" "0: An error occurred while fuse word 28 was last..,1: Last reload of fuse word 28 was done without.." newline bitfld.long 0x0 27. "VLDF27,Valid flag for shadow register 27" "0: An error occurred while fuse word 27 was last..,1: Last reload of fuse word 27 was done without.." bitfld.long 0x0 26. "VLDF26,Valid flag for shadow register 26" "0: An error occurred while fuse word 26 was last..,1: Last reload of fuse word 26 was done without.." newline bitfld.long 0x0 25. "VLDF25,Valid flag for shadow register 25" "0: An error occurred while fuse word 25 was last..,1: Last reload of fuse word 25 was done without.." bitfld.long 0x0 24. "VLDF24,Valid flag for shadow register 24" "0: An error occurred while fuse word 24 was last..,1: Last reload of fuse word 24 was done without.." newline bitfld.long 0x0 23. "VLDF23,Valid flag for shadow register 23" "0: An error occurred while fuse word 23 was last..,1: Last reload of fuse word 23 was done without.." bitfld.long 0x0 22. "VLDF22,Valid flag for shadow register 22" "0: An error occurred while fuse word 22 was last..,1: Last reload of fuse word 22 was done without.." newline bitfld.long 0x0 21. "VLDF21,Valid flag for shadow register 21" "0: An error occurred while fuse word 21 was last..,1: Last reload of fuse word 21 was done without.." bitfld.long 0x0 20. "VLDF20,Valid flag for shadow register 20" "0: An error occurred while fuse word 20 was last..,1: Last reload of fuse word 20 was done without.." newline bitfld.long 0x0 19. "VLDF19,Valid flag for shadow register 19" "0: An error occurred while fuse word 19 was last..,1: Last reload of fuse word 19 was done without.." bitfld.long 0x0 18. "VLDF18,Valid flag for shadow register 18" "0: An error occurred while fuse word 18 was last..,1: Last reload of fuse word 18 was done without.." newline bitfld.long 0x0 17. "VLDF17,Valid flag for shadow register 17" "0: An error occurred while fuse word 17 was last..,1: Last reload of fuse word 17 was done without.." bitfld.long 0x0 16. "VLDF16,Valid flag for shadow register 16" "0: An error occurred while fuse word 16 was last..,1: Last reload of fuse word 16 was done without.." newline bitfld.long 0x0 15. "VLDF15,Valid flag for shadow register 15" "0: An error occurred while fuse word 15 was last..,1: Last reload of fuse word 15 was done without.." bitfld.long 0x0 14. "VLDF14,Valid flag for shadow register 14" "0: An error occurred while fuse word 14 was last..,1: Last reload of fuse word 14 was done without.." newline bitfld.long 0x0 13. "VLDF13,Valid flag for shadow register 13" "0: An error occurred while fuse word 13 was last..,1: Last reload of fuse word 13 was done without.." bitfld.long 0x0 12. "VLDF12,Valid flag for shadow register 12" "0: An error occurred while fuse word 12 was last..,1: Last reload of fuse word 12 was done without.." newline bitfld.long 0x0 11. "VLDF11,Valid flag for shadow register 11" "0: An error occurred while fuse word 11 was last..,1: Last reload of fuse word 11 was done without.." bitfld.long 0x0 10. "VLDF10,Valid flag for shadow register 10" "0: An error occurred while fuse word 10 was last..,1: Last reload of fuse word 10 was done without.." newline bitfld.long 0x0 9. "VLDF9,Valid flag for shadow register 9" "0: An error occurred while fuse word 9 was last..,1: Last reload of fuse word 9 was done without error." bitfld.long 0x0 8. "VLDF8,Valid flag for shadow register 8" "0: An error occurred while fuse word 8 was last..,1: Last reload of fuse word 8 was done without error." newline bitfld.long 0x0 7. "VLDF7,Valid flag for shadow register 7" "0: An error occurred while fuse word 7 was last..,1: Last reload of fuse word 7 was done without error." bitfld.long 0x0 6. "VLDF6,Valid flag for shadow register 6" "0: An error occurred while fuse word 6 was last..,1: Last reload of fuse word 6 was done without error." newline bitfld.long 0x0 5. "VLDF5,Valid flag for shadow register 5" "0: An error occurred while fuse word 5 was last..,1: Last reload of fuse word 5 was done without error." bitfld.long 0x0 4. "VLDF4,Valid flag for shadow register 4" "0: An error occurred while fuse word 4 was last..,1: Last reload of fuse word 4 was done without error." newline bitfld.long 0x0 3. "VLDF3,Valid flag for shadow register 3" "0: An error occurred while fuse word 3 was last..,1: Last reload of fuse word 3 was done without error." bitfld.long 0x0 2. "VLDF2,Valid flag for shadow register 2" "0: An error occurred while fuse word 2 was last..,1: Last reload of fuse word 2 was done without error." newline bitfld.long 0x0 1. "VLDF1,Valid flag for shadow register 1" "0: An error occurred while fuse word 1 was last..,1: Last reload of fuse word 1 was done without error." bitfld.long 0x0 0. "VLDF0,Valid flag for shadow register 0" "0: An error occurred while fuse word 0 was last..,1: Last reload of fuse word 0 was done without error." line.long 0x4 "BSEC_OTPVLDR1,BSEC OTP valid register 1" bitfld.long 0x4 31. "VLDF63,Valid flag for shadow register 63" "0: An error occurred while fuse word 63 was last..,1: Last reload of fuse word 63 was done without.." bitfld.long 0x4 30. "VLDF62,Valid flag for shadow register 62" "0: An error occurred while fuse word 62 was last..,1: Last reload of fuse word 62 was done without.." newline bitfld.long 0x4 29. "VLDF61,Valid flag for shadow register 61" "0: An error occurred while fuse word 61 was last..,1: Last reload of fuse word 61 was done without.." bitfld.long 0x4 28. "VLDF60,Valid flag for shadow register 60" "0: An error occurred while fuse word 60 was last..,1: Last reload of fuse word 60 was done without.." newline bitfld.long 0x4 27. "VLDF59,Valid flag for shadow register 59" "0: An error occurred while fuse word 59 was last..,1: Last reload of fuse word 59 was done without.." bitfld.long 0x4 26. "VLDF58,Valid flag for shadow register 58" "0: An error occurred while fuse word 58 was last..,1: Last reload of fuse word 58 was done without.." newline bitfld.long 0x4 25. "VLDF57,Valid flag for shadow register 57" "0: An error occurred while fuse word 57 was last..,1: Last reload of fuse word 57 was done without.." bitfld.long 0x4 24. "VLDF56,Valid flag for shadow register 56" "0: An error occurred while fuse word 56 was last..,1: Last reload of fuse word 56 was done without.." newline bitfld.long 0x4 23. "VLDF55,Valid flag for shadow register 55" "0: An error occurred while fuse word 55 was last..,1: Last reload of fuse word 55 was done without.." bitfld.long 0x4 22. "VLDF54,Valid flag for shadow register 54" "0: An error occurred while fuse word 54 was last..,1: Last reload of fuse word 54 was done without.." newline bitfld.long 0x4 21. "VLDF53,Valid flag for shadow register 53" "0: An error occurred while fuse word 53 was last..,1: Last reload of fuse word 53 was done without.." bitfld.long 0x4 20. "VLDF52,Valid flag for shadow register 52" "0: An error occurred while fuse word 52 was last..,1: Last reload of fuse word 52 was done without.." newline bitfld.long 0x4 19. "VLDF51,Valid flag for shadow register 51" "0: An error occurred while fuse word 51 was last..,1: Last reload of fuse word 51 was done without.." bitfld.long 0x4 18. "VLDF50,Valid flag for shadow register 50" "0: An error occurred while fuse word 50 was last..,1: Last reload of fuse word 50 was done without.." newline bitfld.long 0x4 17. "VLDF49,Valid flag for shadow register 49" "0: An error occurred while fuse word 49 was last..,1: Last reload of fuse word 49 was done without.." bitfld.long 0x4 16. "VLDF48,Valid flag for shadow register 48" "0: An error occurred while fuse word 48 was last..,1: Last reload of fuse word 48 was done without.." newline bitfld.long 0x4 15. "VLDF47,Valid flag for shadow register 47" "0: An error occurred while fuse word 47 was last..,1: Last reload of fuse word 47 was done without.." bitfld.long 0x4 14. "VLDF46,Valid flag for shadow register 46" "0: An error occurred while fuse word 46 was last..,1: Last reload of fuse word 46 was done without.." newline bitfld.long 0x4 13. "VLDF45,Valid flag for shadow register 45" "0: An error occurred while fuse word 45 was last..,1: Last reload of fuse word 45 was done without.." bitfld.long 0x4 12. "VLDF44,Valid flag for shadow register 44" "0: An error occurred while fuse word 44 was last..,1: Last reload of fuse word 44 was done without.." newline bitfld.long 0x4 11. "VLDF43,Valid flag for shadow register 43" "0: An error occurred while fuse word 43 was last..,1: Last reload of fuse word 43 was done without.." bitfld.long 0x4 10. "VLDF42,Valid flag for shadow register 42" "0: An error occurred while fuse word 42 was last..,1: Last reload of fuse word 42 was done without.." newline bitfld.long 0x4 9. "VLDF41,Valid flag for shadow register 41" "0: An error occurred while fuse word 41 was last..,1: Last reload of fuse word 41 was done without.." bitfld.long 0x4 8. "VLDF40,Valid flag for shadow register 40" "0: An error occurred while fuse word 40 was last..,1: Last reload of fuse word 40 was done without.." newline bitfld.long 0x4 7. "VLDF39,Valid flag for shadow register 39" "0: An error occurred while fuse word 39 was last..,1: Last reload of fuse word 39 was done without.." bitfld.long 0x4 6. "VLDF38,Valid flag for shadow register 38" "0: An error occurred while fuse word 38 was last..,1: Last reload of fuse word 38 was done without.." newline bitfld.long 0x4 5. "VLDF37,Valid flag for shadow register 37" "0: An error occurred while fuse word 37 was last..,1: Last reload of fuse word 37 was done without.." bitfld.long 0x4 4. "VLDF36,Valid flag for shadow register 36" "0: An error occurred while fuse word 36 was last..,1: Last reload of fuse word 36 was done without.." newline bitfld.long 0x4 3. "VLDF35,Valid flag for shadow register 35" "0: An error occurred while fuse word 35 was last..,1: Last reload of fuse word 35 was done without.." bitfld.long 0x4 2. "VLDF34,Valid flag for shadow register 34" "0: An error occurred while fuse word 34 was last..,1: Last reload of fuse word 34 was done without.." newline bitfld.long 0x4 1. "VLDF33,Valid flag for shadow register 33" "0: An error occurred while fuse word 33 was last..,1: Last reload of fuse word 33 was done without.." bitfld.long 0x4 0. "VLDF32,Valid flag for shadow register 32" "0: An error occurred while fuse word 32 was last..,1: Last reload of fuse word 32 was done without.." line.long 0x8 "BSEC_OTPVLDR2,BSEC OTP valid register 2" bitfld.long 0x8 31. "VLDF95,Valid flag for shadow register 95" "0: An error occurred while fuse word 95 was last..,1: Last reload of fuse word 95 was done without.." bitfld.long 0x8 30. "VLDF94,Valid flag for shadow register 94" "0: An error occurred while fuse word 94 was last..,1: Last reload of fuse word 94 was done without.." newline bitfld.long 0x8 29. "VLDF93,Valid flag for shadow register 93" "0: An error occurred while fuse word 93 was last..,1: Last reload of fuse word 93 was done without.." bitfld.long 0x8 28. "VLDF92,Valid flag for shadow register 92" "0: An error occurred while fuse word 92 was last..,1: Last reload of fuse word 92 was done without.." newline bitfld.long 0x8 27. "VLDF91,Valid flag for shadow register 91" "0: An error occurred while fuse word 91 was last..,1: Last reload of fuse word 91 was done without.." bitfld.long 0x8 26. "VLDF90,Valid flag for shadow register 90" "0: An error occurred while fuse word 90 was last..,1: Last reload of fuse word 90 was done without.." newline bitfld.long 0x8 25. "VLDF89,Valid flag for shadow register 89" "0: An error occurred while fuse word 89 was last..,1: Last reload of fuse word 89 was done without.." bitfld.long 0x8 24. "VLDF88,Valid flag for shadow register 88" "0: An error occurred while fuse word 88 was last..,1: Last reload of fuse word 88 was done without.." newline bitfld.long 0x8 23. "VLDF87,Valid flag for shadow register 87" "0: An error occurred while fuse word 87 was last..,1: Last reload of fuse word 87 was done without.." bitfld.long 0x8 22. "VLDF86,Valid flag for shadow register 86" "0: An error occurred while fuse word 86 was last..,1: Last reload of fuse word 86 was done without.." newline bitfld.long 0x8 21. "VLDF85,Valid flag for shadow register 85" "0: An error occurred while fuse word 85 was last..,1: Last reload of fuse word 85 was done without.." bitfld.long 0x8 20. "VLDF84,Valid flag for shadow register 84" "0: An error occurred while fuse word 84 was last..,1: Last reload of fuse word 84 was done without.." newline bitfld.long 0x8 19. "VLDF83,Valid flag for shadow register 83" "0: An error occurred while fuse word 83 was last..,1: Last reload of fuse word 83 was done without.." bitfld.long 0x8 18. "VLDF82,Valid flag for shadow register 82" "0: An error occurred while fuse word 82 was last..,1: Last reload of fuse word 82 was done without.." newline bitfld.long 0x8 17. "VLDF81,Valid flag for shadow register 81" "0: An error occurred while fuse word 81 was last..,1: Last reload of fuse word 81 was done without.." bitfld.long 0x8 16. "VLDF80,Valid flag for shadow register 80" "0: An error occurred while fuse word 80 was last..,1: Last reload of fuse word 80 was done without.." newline bitfld.long 0x8 15. "VLDF79,Valid flag for shadow register 79" "0: An error occurred while fuse word 79 was last..,1: Last reload of fuse word 79 was done without.." bitfld.long 0x8 14. "VLDF78,Valid flag for shadow register 78" "0: An error occurred while fuse word 78 was last..,1: Last reload of fuse word 78 was done without.." newline bitfld.long 0x8 13. "VLDF77,Valid flag for shadow register 77" "0: An error occurred while fuse word 77 was last..,1: Last reload of fuse word 77 was done without.." bitfld.long 0x8 12. "VLDF76,Valid flag for shadow register 76" "0: An error occurred while fuse word 76 was last..,1: Last reload of fuse word 76 was done without.." newline bitfld.long 0x8 11. "VLDF75,Valid flag for shadow register 75" "0: An error occurred while fuse word 75 was last..,1: Last reload of fuse word 75 was done without.." bitfld.long 0x8 10. "VLDF74,Valid flag for shadow register 74" "0: An error occurred while fuse word 74 was last..,1: Last reload of fuse word 74 was done without.." newline bitfld.long 0x8 9. "VLDF73,Valid flag for shadow register 73" "0: An error occurred while fuse word 73 was last..,1: Last reload of fuse word 73 was done without.." bitfld.long 0x8 8. "VLDF72,Valid flag for shadow register 72" "0: An error occurred while fuse word 72 was last..,1: Last reload of fuse word 72 was done without.." newline bitfld.long 0x8 7. "VLDF71,Valid flag for shadow register 71" "0: An error occurred while fuse word 71 was last..,1: Last reload of fuse word 71 was done without.." bitfld.long 0x8 6. "VLDF70,Valid flag for shadow register 70" "0: An error occurred while fuse word 70 was last..,1: Last reload of fuse word 70 was done without.." newline bitfld.long 0x8 5. "VLDF69,Valid flag for shadow register 69" "0: An error occurred while fuse word 69 was last..,1: Last reload of fuse word 69 was done without.." bitfld.long 0x8 4. "VLDF68,Valid flag for shadow register 68" "0: An error occurred while fuse word 68 was last..,1: Last reload of fuse word 68 was done without.." newline bitfld.long 0x8 3. "VLDF67,Valid flag for shadow register 67" "0: An error occurred while fuse word 67 was last..,1: Last reload of fuse word 67 was done without.." bitfld.long 0x8 2. "VLDF66,Valid flag for shadow register 66" "0: An error occurred while fuse word 66 was last..,1: Last reload of fuse word 66 was done without.." newline bitfld.long 0x8 1. "VLDF65,Valid flag for shadow register 65" "0: An error occurred while fuse word 65 was last..,1: Last reload of fuse word 65 was done without.." bitfld.long 0x8 0. "VLDF64,Valid flag for shadow register 64" "0: An error occurred while fuse word 64 was last..,1: Last reload of fuse word 64 was done without.." line.long 0xC "BSEC_OTPVLDR3,BSEC OTP valid register 3" bitfld.long 0xC 31. "VLDF127,Valid flag for shadow register 127" "0: An error occurred while fuse word 127 was last..,1: Last reload of fuse word 127 was done without.." bitfld.long 0xC 30. "VLDF126,Valid flag for shadow register 126" "0: An error occurred while fuse word 126 was last..,1: Last reload of fuse word 126 was done without.." newline bitfld.long 0xC 29. "VLDF125,Valid flag for shadow register 125" "0: An error occurred while fuse word 125 was last..,1: Last reload of fuse word 125 was done without.." bitfld.long 0xC 28. "VLDF124,Valid flag for shadow register 124" "0: An error occurred while fuse word 124 was last..,1: Last reload of fuse word 124 was done without.." newline bitfld.long 0xC 27. "VLDF123,Valid flag for shadow register 123" "0: An error occurred while fuse word 123 was last..,1: Last reload of fuse word 123 was done without.." bitfld.long 0xC 26. "VLDF122,Valid flag for shadow register 122" "0: An error occurred while fuse word 122 was last..,1: Last reload of fuse word 122 was done without.." newline bitfld.long 0xC 25. "VLDF121,Valid flag for shadow register 121" "0: An error occurred while fuse word 121 was last..,1: Last reload of fuse word 121 was done without.." bitfld.long 0xC 24. "VLDF120,Valid flag for shadow register 120" "0: An error occurred while fuse word 120 was last..,1: Last reload of fuse word 120 was done without.." newline bitfld.long 0xC 23. "VLDF119,Valid flag for shadow register 119" "0: An error occurred while fuse word 119 was last..,1: Last reload of fuse word 119 was done without.." bitfld.long 0xC 22. "VLDF118,Valid flag for shadow register 118" "0: An error occurred while fuse word 118 was last..,1: Last reload of fuse word 118 was done without.." newline bitfld.long 0xC 21. "VLDF117,Valid flag for shadow register 117" "0: An error occurred while fuse word 117 was last..,1: Last reload of fuse word 117 was done without.." bitfld.long 0xC 20. "VLDF116,Valid flag for shadow register 116" "0: An error occurred while fuse word 116 was last..,1: Last reload of fuse word 116 was done without.." newline bitfld.long 0xC 19. "VLDF115,Valid flag for shadow register 115" "0: An error occurred while fuse word 115 was last..,1: Last reload of fuse word 115 was done without.." bitfld.long 0xC 18. "VLDF114,Valid flag for shadow register 114" "0: An error occurred while fuse word 114 was last..,1: Last reload of fuse word 114 was done without.." newline bitfld.long 0xC 17. "VLDF113,Valid flag for shadow register 113" "0: An error occurred while fuse word 113 was last..,1: Last reload of fuse word 113 was done without.." bitfld.long 0xC 16. "VLDF112,Valid flag for shadow register 112" "0: An error occurred while fuse word 112 was last..,1: Last reload of fuse word 112 was done without.." newline bitfld.long 0xC 15. "VLDF111,Valid flag for shadow register 111" "0: An error occurred while fuse word 111 was last..,1: Last reload of fuse word 111 was done without.." bitfld.long 0xC 14. "VLDF110,Valid flag for shadow register 110" "0: An error occurred while fuse word 110 was last..,1: Last reload of fuse word 110 was done without.." newline bitfld.long 0xC 13. "VLDF109,Valid flag for shadow register 109" "0: An error occurred while fuse word 109 was last..,1: Last reload of fuse word 109 was done without.." bitfld.long 0xC 12. "VLDF108,Valid flag for shadow register 108" "0: An error occurred while fuse word 108 was last..,1: Last reload of fuse word 108 was done without.." newline bitfld.long 0xC 11. "VLDF107,Valid flag for shadow register 107" "0: An error occurred while fuse word 107 was last..,1: Last reload of fuse word 107 was done without.." bitfld.long 0xC 10. "VLDF106,Valid flag for shadow register 106" "0: An error occurred while fuse word 106 was last..,1: Last reload of fuse word 106 was done without.." newline bitfld.long 0xC 9. "VLDF105,Valid flag for shadow register 105" "0: An error occurred while fuse word 105 was last..,1: Last reload of fuse word 105 was done without.." bitfld.long 0xC 8. "VLDF104,Valid flag for shadow register 104" "0: An error occurred while fuse word 104 was last..,1: Last reload of fuse word 104 was done without.." newline bitfld.long 0xC 7. "VLDF103,Valid flag for shadow register 103" "0: An error occurred while fuse word 103 was last..,1: Last reload of fuse word 103 was done without.." bitfld.long 0xC 6. "VLDF102,Valid flag for shadow register 102" "0: An error occurred while fuse word 102 was last..,1: Last reload of fuse word 102 was done without.." newline bitfld.long 0xC 5. "VLDF101,Valid flag for shadow register 101" "0: An error occurred while fuse word 101 was last..,1: Last reload of fuse word 101 was done without.." bitfld.long 0xC 4. "VLDF100,Valid flag for shadow register 100" "0: An error occurred while fuse word 100 was last..,1: Last reload of fuse word 100 was done without.." newline bitfld.long 0xC 3. "VLDF99,Valid flag for shadow register 99" "0: An error occurred while fuse word 99 was last..,1: Last reload of fuse word 99 was done without.." bitfld.long 0xC 2. "VLDF98,Valid flag for shadow register 98" "0: An error occurred while fuse word 98 was last..,1: Last reload of fuse word 98 was done without.." newline bitfld.long 0xC 1. "VLDF97,Valid flag for shadow register 97" "0: An error occurred while fuse word 97 was last..,1: Last reload of fuse word 97 was done without.." bitfld.long 0xC 0. "VLDF96,Valid flag for shadow register 96" "0: An error occurred while fuse word 96 was last..,1: Last reload of fuse word 96 was done without.." line.long 0x10 "BSEC_OTPVLDR4,BSEC OTP valid register 4" bitfld.long 0x10 31. "VLDF159,Valid flag for shadow register 159" "0: An error occurred while fuse word 159 was last..,1: Last reload of fuse word 159 was done without.." bitfld.long 0x10 30. "VLDF158,Valid flag for shadow register 158" "0: An error occurred while fuse word 158 was last..,1: Last reload of fuse word 158 was done without.." newline bitfld.long 0x10 29. "VLDF157,Valid flag for shadow register 157" "0: An error occurred while fuse word 157 was last..,1: Last reload of fuse word 157 was done without.." bitfld.long 0x10 28. "VLDF156,Valid flag for shadow register 156" "0: An error occurred while fuse word 156 was last..,1: Last reload of fuse word 156 was done without.." newline bitfld.long 0x10 27. "VLDF155,Valid flag for shadow register 155" "0: An error occurred while fuse word 155 was last..,1: Last reload of fuse word 155 was done without.." bitfld.long 0x10 26. "VLDF154,Valid flag for shadow register 154" "0: An error occurred while fuse word 154 was last..,1: Last reload of fuse word 154 was done without.." newline bitfld.long 0x10 25. "VLDF153,Valid flag for shadow register 153" "0: An error occurred while fuse word 153 was last..,1: Last reload of fuse word 153 was done without.." bitfld.long 0x10 24. "VLDF152,Valid flag for shadow register 152" "0: An error occurred while fuse word 152 was last..,1: Last reload of fuse word 152 was done without.." newline bitfld.long 0x10 23. "VLDF151,Valid flag for shadow register 151" "0: An error occurred while fuse word 151 was last..,1: Last reload of fuse word 151 was done without.." bitfld.long 0x10 22. "VLDF150,Valid flag for shadow register 150" "0: An error occurred while fuse word 150 was last..,1: Last reload of fuse word 150 was done without.." newline bitfld.long 0x10 21. "VLDF149,Valid flag for shadow register 149" "0: An error occurred while fuse word 149 was last..,1: Last reload of fuse word 149 was done without.." bitfld.long 0x10 20. "VLDF148,Valid flag for shadow register 148" "0: An error occurred while fuse word 148 was last..,1: Last reload of fuse word 148 was done without.." newline bitfld.long 0x10 19. "VLDF147,Valid flag for shadow register 147" "0: An error occurred while fuse word 147 was last..,1: Last reload of fuse word 147 was done without.." bitfld.long 0x10 18. "VLDF146,Valid flag for shadow register 146" "0: An error occurred while fuse word 146 was last..,1: Last reload of fuse word 146 was done without.." newline bitfld.long 0x10 17. "VLDF145,Valid flag for shadow register 145" "0: An error occurred while fuse word 145 was last..,1: Last reload of fuse word 145 was done without.." bitfld.long 0x10 16. "VLDF144,Valid flag for shadow register 144" "0: An error occurred while fuse word 144 was last..,1: Last reload of fuse word 144 was done without.." newline bitfld.long 0x10 15. "VLDF143,Valid flag for shadow register 143" "0: An error occurred while fuse word 143 was last..,1: Last reload of fuse word 143 was done without.." bitfld.long 0x10 14. "VLDF142,Valid flag for shadow register 142" "0: An error occurred while fuse word 142 was last..,1: Last reload of fuse word 142 was done without.." newline bitfld.long 0x10 13. "VLDF141,Valid flag for shadow register 141" "0: An error occurred while fuse word 141 was last..,1: Last reload of fuse word 141 was done without.." bitfld.long 0x10 12. "VLDF140,Valid flag for shadow register 140" "0: An error occurred while fuse word 140 was last..,1: Last reload of fuse word 140 was done without.." newline bitfld.long 0x10 11. "VLDF139,Valid flag for shadow register 139" "0: An error occurred while fuse word 139 was last..,1: Last reload of fuse word 139 was done without.." bitfld.long 0x10 10. "VLDF138,Valid flag for shadow register 138" "0: An error occurred while fuse word 138 was last..,1: Last reload of fuse word 138 was done without.." newline bitfld.long 0x10 9. "VLDF137,Valid flag for shadow register 137" "0: An error occurred while fuse word 137 was last..,1: Last reload of fuse word 137 was done without.." bitfld.long 0x10 8. "VLDF136,Valid flag for shadow register 136" "0: An error occurred while fuse word 136 was last..,1: Last reload of fuse word 136 was done without.." newline bitfld.long 0x10 7. "VLDF135,Valid flag for shadow register 135" "0: An error occurred while fuse word 135 was last..,1: Last reload of fuse word 135 was done without.." bitfld.long 0x10 6. "VLDF134,Valid flag for shadow register 134" "0: An error occurred while fuse word 134 was last..,1: Last reload of fuse word 134 was done without.." newline bitfld.long 0x10 5. "VLDF133,Valid flag for shadow register 133" "0: An error occurred while fuse word 133 was last..,1: Last reload of fuse word 133 was done without.." bitfld.long 0x10 4. "VLDF132,Valid flag for shadow register 132" "0: An error occurred while fuse word 132 was last..,1: Last reload of fuse word 132 was done without.." newline bitfld.long 0x10 3. "VLDF131,Valid flag for shadow register 131" "0: An error occurred while fuse word 131 was last..,1: Last reload of fuse word 131 was done without.." bitfld.long 0x10 2. "VLDF130,Valid flag for shadow register 130" "0: An error occurred while fuse word 130 was last..,1: Last reload of fuse word 130 was done without.." newline bitfld.long 0x10 1. "VLDF129,Valid flag for shadow register 129" "0: An error occurred while fuse word 129 was last..,1: Last reload of fuse word 129 was done without.." bitfld.long 0x10 0. "VLDF128,Valid flag for shadow register 128" "0: An error occurred while fuse word 128 was last..,1: Last reload of fuse word 128 was done without.." line.long 0x14 "BSEC_OTPVLDR5,BSEC OTP valid register 5" bitfld.long 0x14 31. "VLDF191,Valid flag for shadow register 191" "0: An error occurred while fuse word 191 was last..,1: Last reload of fuse word 191 was done without.." bitfld.long 0x14 30. "VLDF190,Valid flag for shadow register 190" "0: An error occurred while fuse word 190 was last..,1: Last reload of fuse word 190 was done without.." newline bitfld.long 0x14 29. "VLDF189,Valid flag for shadow register 189" "0: An error occurred while fuse word 189 was last..,1: Last reload of fuse word 189 was done without.." bitfld.long 0x14 28. "VLDF188,Valid flag for shadow register 188" "0: An error occurred while fuse word 188 was last..,1: Last reload of fuse word 188 was done without.." newline bitfld.long 0x14 27. "VLDF187,Valid flag for shadow register 187" "0: An error occurred while fuse word 187 was last..,1: Last reload of fuse word 187 was done without.." bitfld.long 0x14 26. "VLDF186,Valid flag for shadow register 186" "0: An error occurred while fuse word 186 was last..,1: Last reload of fuse word 186 was done without.." newline bitfld.long 0x14 25. "VLDF185,Valid flag for shadow register 185" "0: An error occurred while fuse word 185 was last..,1: Last reload of fuse word 185 was done without.." bitfld.long 0x14 24. "VLDF184,Valid flag for shadow register 184" "0: An error occurred while fuse word 184 was last..,1: Last reload of fuse word 184 was done without.." newline bitfld.long 0x14 23. "VLDF183,Valid flag for shadow register 183" "0: An error occurred while fuse word 183 was last..,1: Last reload of fuse word 183 was done without.." bitfld.long 0x14 22. "VLDF182,Valid flag for shadow register 182" "0: An error occurred while fuse word 182 was last..,1: Last reload of fuse word 182 was done without.." newline bitfld.long 0x14 21. "VLDF181,Valid flag for shadow register 181" "0: An error occurred while fuse word 181 was last..,1: Last reload of fuse word 181 was done without.." bitfld.long 0x14 20. "VLDF180,Valid flag for shadow register 180" "0: An error occurred while fuse word 180 was last..,1: Last reload of fuse word 180 was done without.." newline bitfld.long 0x14 19. "VLDF179,Valid flag for shadow register 179" "0: An error occurred while fuse word 179 was last..,1: Last reload of fuse word 179 was done without.." bitfld.long 0x14 18. "VLDF178,Valid flag for shadow register 178" "0: An error occurred while fuse word 178 was last..,1: Last reload of fuse word 178 was done without.." newline bitfld.long 0x14 17. "VLDF177,Valid flag for shadow register 177" "0: An error occurred while fuse word 177 was last..,1: Last reload of fuse word 177 was done without.." bitfld.long 0x14 16. "VLDF176,Valid flag for shadow register 176" "0: An error occurred while fuse word 176 was last..,1: Last reload of fuse word 176 was done without.." newline bitfld.long 0x14 15. "VLDF175,Valid flag for shadow register 175" "0: An error occurred while fuse word 175 was last..,1: Last reload of fuse word 175 was done without.." bitfld.long 0x14 14. "VLDF174,Valid flag for shadow register 174" "0: An error occurred while fuse word 174 was last..,1: Last reload of fuse word 174 was done without.." newline bitfld.long 0x14 13. "VLDF173,Valid flag for shadow register 173" "0: An error occurred while fuse word 173 was last..,1: Last reload of fuse word 173 was done without.." bitfld.long 0x14 12. "VLDF172,Valid flag for shadow register 172" "0: An error occurred while fuse word 172 was last..,1: Last reload of fuse word 172 was done without.." newline bitfld.long 0x14 11. "VLDF171,Valid flag for shadow register 171" "0: An error occurred while fuse word 171 was last..,1: Last reload of fuse word 171 was done without.." bitfld.long 0x14 10. "VLDF170,Valid flag for shadow register 170" "0: An error occurred while fuse word 170 was last..,1: Last reload of fuse word 170 was done without.." newline bitfld.long 0x14 9. "VLDF169,Valid flag for shadow register 169" "0: An error occurred while fuse word 169 was last..,1: Last reload of fuse word 169 was done without.." bitfld.long 0x14 8. "VLDF168,Valid flag for shadow register 168" "0: An error occurred while fuse word 168 was last..,1: Last reload of fuse word 168 was done without.." newline bitfld.long 0x14 7. "VLDF167,Valid flag for shadow register 167" "0: An error occurred while fuse word 167 was last..,1: Last reload of fuse word 167 was done without.." bitfld.long 0x14 6. "VLDF166,Valid flag for shadow register 166" "0: An error occurred while fuse word 166 was last..,1: Last reload of fuse word 166 was done without.." newline bitfld.long 0x14 5. "VLDF165,Valid flag for shadow register 165" "0: An error occurred while fuse word 165 was last..,1: Last reload of fuse word 165 was done without.." bitfld.long 0x14 4. "VLDF164,Valid flag for shadow register 164" "0: An error occurred while fuse word 164 was last..,1: Last reload of fuse word 164 was done without.." newline bitfld.long 0x14 3. "VLDF163,Valid flag for shadow register 163" "0: An error occurred while fuse word 163 was last..,1: Last reload of fuse word 163 was done without.." bitfld.long 0x14 2. "VLDF162,Valid flag for shadow register 162" "0: An error occurred while fuse word 162 was last..,1: Last reload of fuse word 162 was done without.." newline bitfld.long 0x14 1. "VLDF161,Valid flag for shadow register 161" "0: An error occurred while fuse word 161 was last..,1: Last reload of fuse word 161 was done without.." bitfld.long 0x14 0. "VLDF160,Valid flag for shadow register 160" "0: An error occurred while fuse word 160 was last..,1: Last reload of fuse word 160 was done without.." line.long 0x18 "BSEC_OTPVLDR6,BSEC OTP valid register 6" bitfld.long 0x18 31. "VLDF223,Valid flag for shadow register 223" "0: An error occurred while fuse word 223 was last..,1: Last reload of fuse word 223 was done without.." bitfld.long 0x18 30. "VLDF222,Valid flag for shadow register 222" "0: An error occurred while fuse word 222 was last..,1: Last reload of fuse word 222 was done without.." newline bitfld.long 0x18 29. "VLDF221,Valid flag for shadow register 221" "0: An error occurred while fuse word 221 was last..,1: Last reload of fuse word 221 was done without.." bitfld.long 0x18 28. "VLDF220,Valid flag for shadow register 220" "0: An error occurred while fuse word 220 was last..,1: Last reload of fuse word 220 was done without.." newline bitfld.long 0x18 27. "VLDF219,Valid flag for shadow register 219" "0: An error occurred while fuse word 219 was last..,1: Last reload of fuse word 219 was done without.." bitfld.long 0x18 26. "VLDF218,Valid flag for shadow register 218" "0: An error occurred while fuse word 218 was last..,1: Last reload of fuse word 218 was done without.." newline bitfld.long 0x18 25. "VLDF217,Valid flag for shadow register 217" "0: An error occurred while fuse word 217 was last..,1: Last reload of fuse word 217 was done without.." bitfld.long 0x18 24. "VLDF216,Valid flag for shadow register 216" "0: An error occurred while fuse word 216 was last..,1: Last reload of fuse word 216 was done without.." newline bitfld.long 0x18 23. "VLDF215,Valid flag for shadow register 215" "0: An error occurred while fuse word 215 was last..,1: Last reload of fuse word 215 was done without.." bitfld.long 0x18 22. "VLDF214,Valid flag for shadow register 214" "0: An error occurred while fuse word 214 was last..,1: Last reload of fuse word 214 was done without.." newline bitfld.long 0x18 21. "VLDF213,Valid flag for shadow register 213" "0: An error occurred while fuse word 213 was last..,1: Last reload of fuse word 213 was done without.." bitfld.long 0x18 20. "VLDF212,Valid flag for shadow register 212" "0: An error occurred while fuse word 212 was last..,1: Last reload of fuse word 212 was done without.." newline bitfld.long 0x18 19. "VLDF211,Valid flag for shadow register 211" "0: An error occurred while fuse word 211 was last..,1: Last reload of fuse word 211 was done without.." bitfld.long 0x18 18. "VLDF210,Valid flag for shadow register 210" "0: An error occurred while fuse word 210 was last..,1: Last reload of fuse word 210 was done without.." newline bitfld.long 0x18 17. "VLDF209,Valid flag for shadow register 209" "0: An error occurred while fuse word 209 was last..,1: Last reload of fuse word 209 was done without.." bitfld.long 0x18 16. "VLDF208,Valid flag for shadow register 208" "0: An error occurred while fuse word 208 was last..,1: Last reload of fuse word 208 was done without.." newline bitfld.long 0x18 15. "VLDF207,Valid flag for shadow register 207" "0: An error occurred while fuse word 207 was last..,1: Last reload of fuse word 207 was done without.." bitfld.long 0x18 14. "VLDF206,Valid flag for shadow register 206" "0: An error occurred while fuse word 206 was last..,1: Last reload of fuse word 206 was done without.." newline bitfld.long 0x18 13. "VLDF205,Valid flag for shadow register 205" "0: An error occurred while fuse word 205 was last..,1: Last reload of fuse word 205 was done without.." bitfld.long 0x18 12. "VLDF204,Valid flag for shadow register 204" "0: An error occurred while fuse word 204 was last..,1: Last reload of fuse word 204 was done without.." newline bitfld.long 0x18 11. "VLDF203,Valid flag for shadow register 203" "0: An error occurred while fuse word 203 was last..,1: Last reload of fuse word 203 was done without.." bitfld.long 0x18 10. "VLDF202,Valid flag for shadow register 202" "0: An error occurred while fuse word 202 was last..,1: Last reload of fuse word 202 was done without.." newline bitfld.long 0x18 9. "VLDF201,Valid flag for shadow register 201" "0: An error occurred while fuse word 201 was last..,1: Last reload of fuse word 201 was done without.." bitfld.long 0x18 8. "VLDF200,Valid flag for shadow register 200" "0: An error occurred while fuse word 200 was last..,1: Last reload of fuse word 200 was done without.." newline bitfld.long 0x18 7. "VLDF199,Valid flag for shadow register 199" "0: An error occurred while fuse word 199 was last..,1: Last reload of fuse word 199 was done without.." bitfld.long 0x18 6. "VLDF198,Valid flag for shadow register 198" "0: An error occurred while fuse word 198 was last..,1: Last reload of fuse word 198 was done without.." newline bitfld.long 0x18 5. "VLDF197,Valid flag for shadow register 197" "0: An error occurred while fuse word 197 was last..,1: Last reload of fuse word 197 was done without.." bitfld.long 0x18 4. "VLDF196,Valid flag for shadow register 196" "0: An error occurred while fuse word 196 was last..,1: Last reload of fuse word 196 was done without.." newline bitfld.long 0x18 3. "VLDF195,Valid flag for shadow register 195" "0: An error occurred while fuse word 195 was last..,1: Last reload of fuse word 195 was done without.." bitfld.long 0x18 2. "VLDF194,Valid flag for shadow register 194" "0: An error occurred while fuse word 194 was last..,1: Last reload of fuse word 194 was done without.." newline bitfld.long 0x18 1. "VLDF193,Valid flag for shadow register 193" "0: An error occurred while fuse word 193 was last..,1: Last reload of fuse word 193 was done without.." bitfld.long 0x18 0. "VLDF192,Valid flag for shadow register 192" "0: An error occurred while fuse word 192 was last..,1: Last reload of fuse word 192 was done without.." line.long 0x1C "BSEC_OTPVLDR7,BSEC OTP valid register 7" bitfld.long 0x1C 31. "VLDF255,Valid flag for shadow register 255" "0: An error occurred while fuse word 255 was last..,1: Last reload of fuse word 255 was done without.." bitfld.long 0x1C 30. "VLDF254,Valid flag for shadow register 254" "0: An error occurred while fuse word 254 was last..,1: Last reload of fuse word 254 was done without.." newline bitfld.long 0x1C 29. "VLDF253,Valid flag for shadow register 253" "0: An error occurred while fuse word 253 was last..,1: Last reload of fuse word 253 was done without.." bitfld.long 0x1C 28. "VLDF252,Valid flag for shadow register 252" "0: An error occurred while fuse word 252 was last..,1: Last reload of fuse word 252 was done without.." newline bitfld.long 0x1C 27. "VLDF251,Valid flag for shadow register 251" "0: An error occurred while fuse word 251 was last..,1: Last reload of fuse word 251 was done without.." bitfld.long 0x1C 26. "VLDF250,Valid flag for shadow register 250" "0: An error occurred while fuse word 250 was last..,1: Last reload of fuse word 250 was done without.." newline bitfld.long 0x1C 25. "VLDF249,Valid flag for shadow register 249" "0: An error occurred while fuse word 249 was last..,1: Last reload of fuse word 249 was done without.." bitfld.long 0x1C 24. "VLDF248,Valid flag for shadow register 248" "0: An error occurred while fuse word 248 was last..,1: Last reload of fuse word 248 was done without.." newline bitfld.long 0x1C 23. "VLDF247,Valid flag for shadow register 247" "0: An error occurred while fuse word 247 was last..,1: Last reload of fuse word 247 was done without.." bitfld.long 0x1C 22. "VLDF246,Valid flag for shadow register 246" "0: An error occurred while fuse word 246 was last..,1: Last reload of fuse word 246 was done without.." newline bitfld.long 0x1C 21. "VLDF245,Valid flag for shadow register 245" "0: An error occurred while fuse word 245 was last..,1: Last reload of fuse word 245 was done without.." bitfld.long 0x1C 20. "VLDF244,Valid flag for shadow register 244" "0: An error occurred while fuse word 244 was last..,1: Last reload of fuse word 244 was done without.." newline bitfld.long 0x1C 19. "VLDF243,Valid flag for shadow register 243" "0: An error occurred while fuse word 243 was last..,1: Last reload of fuse word 243 was done without.." bitfld.long 0x1C 18. "VLDF242,Valid flag for shadow register 242" "0: An error occurred while fuse word 242 was last..,1: Last reload of fuse word 242 was done without.." newline bitfld.long 0x1C 17. "VLDF241,Valid flag for shadow register 241" "0: An error occurred while fuse word 241 was last..,1: Last reload of fuse word 241 was done without.." bitfld.long 0x1C 16. "VLDF240,Valid flag for shadow register 240" "0: An error occurred while fuse word 240 was last..,1: Last reload of fuse word 240 was done without.." newline bitfld.long 0x1C 15. "VLDF239,Valid flag for shadow register 239" "0: An error occurred while fuse word 239 was last..,1: Last reload of fuse word 239 was done without.." bitfld.long 0x1C 14. "VLDF238,Valid flag for shadow register 238" "0: An error occurred while fuse word 238 was last..,1: Last reload of fuse word 238 was done without.." newline bitfld.long 0x1C 13. "VLDF237,Valid flag for shadow register 237" "0: An error occurred while fuse word 237 was last..,1: Last reload of fuse word 237 was done without.." bitfld.long 0x1C 12. "VLDF236,Valid flag for shadow register 236" "0: An error occurred while fuse word 236 was last..,1: Last reload of fuse word 236 was done without.." newline bitfld.long 0x1C 11. "VLDF235,Valid flag for shadow register 235" "0: An error occurred while fuse word 235 was last..,1: Last reload of fuse word 235 was done without.." bitfld.long 0x1C 10. "VLDF234,Valid flag for shadow register 234" "0: An error occurred while fuse word 234 was last..,1: Last reload of fuse word 234 was done without.." newline bitfld.long 0x1C 9. "VLDF233,Valid flag for shadow register 233" "0: An error occurred while fuse word 233 was last..,1: Last reload of fuse word 233 was done without.." bitfld.long 0x1C 8. "VLDF232,Valid flag for shadow register 232" "0: An error occurred while fuse word 232 was last..,1: Last reload of fuse word 232 was done without.." newline bitfld.long 0x1C 7. "VLDF231,Valid flag for shadow register 231" "0: An error occurred while fuse word 231 was last..,1: Last reload of fuse word 231 was done without.." bitfld.long 0x1C 6. "VLDF230,Valid flag for shadow register 230" "0: An error occurred while fuse word 230 was last..,1: Last reload of fuse word 230 was done without.." newline bitfld.long 0x1C 5. "VLDF229,Valid flag for shadow register 229" "0: An error occurred while fuse word 229 was last..,1: Last reload of fuse word 229 was done without.." bitfld.long 0x1C 4. "VLDF228,Valid flag for shadow register 228" "0: An error occurred while fuse word 228 was last..,1: Last reload of fuse word 228 was done without.." newline bitfld.long 0x1C 3. "VLDF227,Valid flag for shadow register 227" "0: An error occurred while fuse word 227 was last..,1: Last reload of fuse word 227 was done without.." bitfld.long 0x1C 2. "VLDF226,Valid flag for shadow register 226" "0: An error occurred while fuse word 226 was last..,1: Last reload of fuse word 226 was done without.." newline bitfld.long 0x1C 1. "VLDF225,Valid flag for shadow register 225" "0: An error occurred while fuse word 225 was last..,1: Last reload of fuse word 225 was done without.." bitfld.long 0x1C 0. "VLDF224,Valid flag for shadow register 224" "0: An error occurred while fuse word 224 was last..,1: Last reload of fuse word 224 was done without.." line.long 0x20 "BSEC_OTPVLDR8,BSEC OTP valid register 8" bitfld.long 0x20 31. "VLDF287,Valid flag for shadow register 287" "0: An error occurred while fuse word 287 was last..,1: Last reload of fuse word 287 was done without.." bitfld.long 0x20 30. "VLDF286,Valid flag for shadow register 286" "0: An error occurred while fuse word 286 was last..,1: Last reload of fuse word 286 was done without.." newline bitfld.long 0x20 29. "VLDF285,Valid flag for shadow register 285" "0: An error occurred while fuse word 285 was last..,1: Last reload of fuse word 285 was done without.." bitfld.long 0x20 28. "VLDF284,Valid flag for shadow register 284" "0: An error occurred while fuse word 284 was last..,1: Last reload of fuse word 284 was done without.." newline bitfld.long 0x20 27. "VLDF283,Valid flag for shadow register 283" "0: An error occurred while fuse word 283 was last..,1: Last reload of fuse word 283 was done without.." bitfld.long 0x20 26. "VLDF282,Valid flag for shadow register 282" "0: An error occurred while fuse word 282 was last..,1: Last reload of fuse word 282 was done without.." newline bitfld.long 0x20 25. "VLDF281,Valid flag for shadow register 281" "0: An error occurred while fuse word 281 was last..,1: Last reload of fuse word 281 was done without.." bitfld.long 0x20 24. "VLDF280,Valid flag for shadow register 280" "0: An error occurred while fuse word 280 was last..,1: Last reload of fuse word 280 was done without.." newline bitfld.long 0x20 23. "VLDF279,Valid flag for shadow register 279" "0: An error occurred while fuse word 279 was last..,1: Last reload of fuse word 279 was done without.." bitfld.long 0x20 22. "VLDF278,Valid flag for shadow register 278" "0: An error occurred while fuse word 278 was last..,1: Last reload of fuse word 278 was done without.." newline bitfld.long 0x20 21. "VLDF277,Valid flag for shadow register 277" "0: An error occurred while fuse word 277 was last..,1: Last reload of fuse word 277 was done without.." bitfld.long 0x20 20. "VLDF276,Valid flag for shadow register 276" "0: An error occurred while fuse word 276 was last..,1: Last reload of fuse word 276 was done without.." newline bitfld.long 0x20 19. "VLDF275,Valid flag for shadow register 275" "0: An error occurred while fuse word 275 was last..,1: Last reload of fuse word 275 was done without.." bitfld.long 0x20 18. "VLDF274,Valid flag for shadow register 274" "0: An error occurred while fuse word 274 was last..,1: Last reload of fuse word 274 was done without.." newline bitfld.long 0x20 17. "VLDF273,Valid flag for shadow register 273" "0: An error occurred while fuse word 273 was last..,1: Last reload of fuse word 273 was done without.." bitfld.long 0x20 16. "VLDF272,Valid flag for shadow register 272" "0: An error occurred while fuse word 272 was last..,1: Last reload of fuse word 272 was done without.." newline bitfld.long 0x20 15. "VLDF271,Valid flag for shadow register 271" "0: An error occurred while fuse word 271 was last..,1: Last reload of fuse word 271 was done without.." bitfld.long 0x20 14. "VLDF270,Valid flag for shadow register 270" "0: An error occurred while fuse word 270 was last..,1: Last reload of fuse word 270 was done without.." newline bitfld.long 0x20 13. "VLDF269,Valid flag for shadow register 269" "0: An error occurred while fuse word 269 was last..,1: Last reload of fuse word 269 was done without.." bitfld.long 0x20 12. "VLDF268,Valid flag for shadow register 268" "0: An error occurred while fuse word 268 was last..,1: Last reload of fuse word 268 was done without.." newline bitfld.long 0x20 11. "VLDF267,Valid flag for shadow register 267" "0: An error occurred while fuse word 267 was last..,1: Last reload of fuse word 267 was done without.." bitfld.long 0x20 10. "VLDF266,Valid flag for shadow register 266" "0: An error occurred while fuse word 266 was last..,1: Last reload of fuse word 266 was done without.." newline bitfld.long 0x20 9. "VLDF265,Valid flag for shadow register 265" "0: An error occurred while fuse word 265 was last..,1: Last reload of fuse word 265 was done without.." bitfld.long 0x20 8. "VLDF264,Valid flag for shadow register 264" "0: An error occurred while fuse word 264 was last..,1: Last reload of fuse word 264 was done without.." newline bitfld.long 0x20 7. "VLDF263,Valid flag for shadow register 263" "0: An error occurred while fuse word 263 was last..,1: Last reload of fuse word 263 was done without.." bitfld.long 0x20 6. "VLDF262,Valid flag for shadow register 262" "0: An error occurred while fuse word 262 was last..,1: Last reload of fuse word 262 was done without.." newline bitfld.long 0x20 5. "VLDF261,Valid flag for shadow register 261" "0: An error occurred while fuse word 261 was last..,1: Last reload of fuse word 261 was done without.." bitfld.long 0x20 4. "VLDF260,Valid flag for shadow register 260" "0: An error occurred while fuse word 260 was last..,1: Last reload of fuse word 260 was done without.." newline bitfld.long 0x20 3. "VLDF259,Valid flag for shadow register 259" "0: An error occurred while fuse word 259 was last..,1: Last reload of fuse word 259 was done without.." bitfld.long 0x20 2. "VLDF258,Valid flag for shadow register 258" "0: An error occurred while fuse word 258 was last..,1: Last reload of fuse word 258 was done without.." newline bitfld.long 0x20 1. "VLDF257,Valid flag for shadow register 257" "0: An error occurred while fuse word 257 was last..,1: Last reload of fuse word 257 was done without.." bitfld.long 0x20 0. "VLDF256,Valid flag for shadow register 256" "0: An error occurred while fuse word 256 was last..,1: Last reload of fuse word 256 was done without.." line.long 0x24 "BSEC_OTPVLDR9,BSEC OTP valid register 9" bitfld.long 0x24 31. "VLDF319,Valid flag for shadow register 319" "0: An error occurred while fuse word 319 was last..,1: Last reload of fuse word 319 was done without.." bitfld.long 0x24 30. "VLDF318,Valid flag for shadow register 318" "0: An error occurred while fuse word 318 was last..,1: Last reload of fuse word 318 was done without.." newline bitfld.long 0x24 29. "VLDF317,Valid flag for shadow register 317" "0: An error occurred while fuse word 317 was last..,1: Last reload of fuse word 317 was done without.." bitfld.long 0x24 28. "VLDF316,Valid flag for shadow register 316" "0: An error occurred while fuse word 316 was last..,1: Last reload of fuse word 316 was done without.." newline bitfld.long 0x24 27. "VLDF315,Valid flag for shadow register 315" "0: An error occurred while fuse word 315 was last..,1: Last reload of fuse word 315 was done without.." bitfld.long 0x24 26. "VLDF314,Valid flag for shadow register 314" "0: An error occurred while fuse word 314 was last..,1: Last reload of fuse word 314 was done without.." newline bitfld.long 0x24 25. "VLDF313,Valid flag for shadow register 313" "0: An error occurred while fuse word 313 was last..,1: Last reload of fuse word 313 was done without.." bitfld.long 0x24 24. "VLDF312,Valid flag for shadow register 312" "0: An error occurred while fuse word 312 was last..,1: Last reload of fuse word 312 was done without.." newline bitfld.long 0x24 23. "VLDF311,Valid flag for shadow register 311" "0: An error occurred while fuse word 311 was last..,1: Last reload of fuse word 311 was done without.." bitfld.long 0x24 22. "VLDF310,Valid flag for shadow register 310" "0: An error occurred while fuse word 310 was last..,1: Last reload of fuse word 310 was done without.." newline bitfld.long 0x24 21. "VLDF309,Valid flag for shadow register 309" "0: An error occurred while fuse word 309 was last..,1: Last reload of fuse word 309 was done without.." bitfld.long 0x24 20. "VLDF308,Valid flag for shadow register 308" "0: An error occurred while fuse word 308 was last..,1: Last reload of fuse word 308 was done without.." newline bitfld.long 0x24 19. "VLDF307,Valid flag for shadow register 307" "0: An error occurred while fuse word 307 was last..,1: Last reload of fuse word 307 was done without.." bitfld.long 0x24 18. "VLDF306,Valid flag for shadow register 306" "0: An error occurred while fuse word 306 was last..,1: Last reload of fuse word 306 was done without.." newline bitfld.long 0x24 17. "VLDF305,Valid flag for shadow register 305" "0: An error occurred while fuse word 305 was last..,1: Last reload of fuse word 305 was done without.." bitfld.long 0x24 16. "VLDF304,Valid flag for shadow register 304" "0: An error occurred while fuse word 304 was last..,1: Last reload of fuse word 304 was done without.." newline bitfld.long 0x24 15. "VLDF303,Valid flag for shadow register 303" "0: An error occurred while fuse word 303 was last..,1: Last reload of fuse word 303 was done without.." bitfld.long 0x24 14. "VLDF302,Valid flag for shadow register 302" "0: An error occurred while fuse word 302 was last..,1: Last reload of fuse word 302 was done without.." newline bitfld.long 0x24 13. "VLDF301,Valid flag for shadow register 301" "0: An error occurred while fuse word 301 was last..,1: Last reload of fuse word 301 was done without.." bitfld.long 0x24 12. "VLDF300,Valid flag for shadow register 300" "0: An error occurred while fuse word 300 was last..,1: Last reload of fuse word 300 was done without.." newline bitfld.long 0x24 11. "VLDF299,Valid flag for shadow register 299" "0: An error occurred while fuse word 299 was last..,1: Last reload of fuse word 299 was done without.." bitfld.long 0x24 10. "VLDF298,Valid flag for shadow register 298" "0: An error occurred while fuse word 298 was last..,1: Last reload of fuse word 298 was done without.." newline bitfld.long 0x24 9. "VLDF297,Valid flag for shadow register 297" "0: An error occurred while fuse word 297 was last..,1: Last reload of fuse word 297 was done without.." bitfld.long 0x24 8. "VLDF296,Valid flag for shadow register 296" "0: An error occurred while fuse word 296 was last..,1: Last reload of fuse word 296 was done without.." newline bitfld.long 0x24 7. "VLDF295,Valid flag for shadow register 295" "0: An error occurred while fuse word 295 was last..,1: Last reload of fuse word 295 was done without.." bitfld.long 0x24 6. "VLDF294,Valid flag for shadow register 294" "0: An error occurred while fuse word 294 was last..,1: Last reload of fuse word 294 was done without.." newline bitfld.long 0x24 5. "VLDF293,Valid flag for shadow register 293" "0: An error occurred while fuse word 293 was last..,1: Last reload of fuse word 293 was done without.." bitfld.long 0x24 4. "VLDF292,Valid flag for shadow register 292" "0: An error occurred while fuse word 292 was last..,1: Last reload of fuse word 292 was done without.." newline bitfld.long 0x24 3. "VLDF291,Valid flag for shadow register 291" "0: An error occurred while fuse word 291 was last..,1: Last reload of fuse word 291 was done without.." bitfld.long 0x24 2. "VLDF290,Valid flag for shadow register 290" "0: An error occurred while fuse word 290 was last..,1: Last reload of fuse word 290 was done without.." newline bitfld.long 0x24 1. "VLDF289,Valid flag for shadow register 289" "0: An error occurred while fuse word 289 was last..,1: Last reload of fuse word 289 was done without.." bitfld.long 0x24 0. "VLDF288,Valid flag for shadow register 288" "0: An error occurred while fuse word 288 was last..,1: Last reload of fuse word 288 was done without.." line.long 0x28 "BSEC_OTPVLDR10,BSEC OTP valid register 10" bitfld.long 0x28 31. "VLDF351,Valid flag for shadow register 351" "0: An error occurred while fuse word 351 was last..,1: Last reload of fuse word 351 was done without.." bitfld.long 0x28 30. "VLDF350,Valid flag for shadow register 350" "0: An error occurred while fuse word 350 was last..,1: Last reload of fuse word 350 was done without.." newline bitfld.long 0x28 29. "VLDF349,Valid flag for shadow register 349" "0: An error occurred while fuse word 349 was last..,1: Last reload of fuse word 349 was done without.." bitfld.long 0x28 28. "VLDF348,Valid flag for shadow register 348" "0: An error occurred while fuse word 348 was last..,1: Last reload of fuse word 348 was done without.." newline bitfld.long 0x28 27. "VLDF347,Valid flag for shadow register 347" "0: An error occurred while fuse word 347 was last..,1: Last reload of fuse word 347 was done without.." bitfld.long 0x28 26. "VLDF346,Valid flag for shadow register 346" "0: An error occurred while fuse word 346 was last..,1: Last reload of fuse word 346 was done without.." newline bitfld.long 0x28 25. "VLDF345,Valid flag for shadow register 345" "0: An error occurred while fuse word 345 was last..,1: Last reload of fuse word 345 was done without.." bitfld.long 0x28 24. "VLDF344,Valid flag for shadow register 344" "0: An error occurred while fuse word 344 was last..,1: Last reload of fuse word 344 was done without.." newline bitfld.long 0x28 23. "VLDF343,Valid flag for shadow register 343" "0: An error occurred while fuse word 343 was last..,1: Last reload of fuse word 343 was done without.." bitfld.long 0x28 22. "VLDF342,Valid flag for shadow register 342" "0: An error occurred while fuse word 342 was last..,1: Last reload of fuse word 342 was done without.." newline bitfld.long 0x28 21. "VLDF341,Valid flag for shadow register 341" "0: An error occurred while fuse word 341 was last..,1: Last reload of fuse word 341 was done without.." bitfld.long 0x28 20. "VLDF340,Valid flag for shadow register 340" "0: An error occurred while fuse word 340 was last..,1: Last reload of fuse word 340 was done without.." newline bitfld.long 0x28 19. "VLDF339,Valid flag for shadow register 339" "0: An error occurred while fuse word 339 was last..,1: Last reload of fuse word 339 was done without.." bitfld.long 0x28 18. "VLDF338,Valid flag for shadow register 338" "0: An error occurred while fuse word 338 was last..,1: Last reload of fuse word 338 was done without.." newline bitfld.long 0x28 17. "VLDF337,Valid flag for shadow register 337" "0: An error occurred while fuse word 337 was last..,1: Last reload of fuse word 337 was done without.." bitfld.long 0x28 16. "VLDF336,Valid flag for shadow register 336" "0: An error occurred while fuse word 336 was last..,1: Last reload of fuse word 336 was done without.." newline bitfld.long 0x28 15. "VLDF335,Valid flag for shadow register 335" "0: An error occurred while fuse word 335 was last..,1: Last reload of fuse word 335 was done without.." bitfld.long 0x28 14. "VLDF334,Valid flag for shadow register 334" "0: An error occurred while fuse word 334 was last..,1: Last reload of fuse word 334 was done without.." newline bitfld.long 0x28 13. "VLDF333,Valid flag for shadow register 333" "0: An error occurred while fuse word 333 was last..,1: Last reload of fuse word 333 was done without.." bitfld.long 0x28 12. "VLDF332,Valid flag for shadow register 332" "0: An error occurred while fuse word 332 was last..,1: Last reload of fuse word 332 was done without.." newline bitfld.long 0x28 11. "VLDF331,Valid flag for shadow register 331" "0: An error occurred while fuse word 331 was last..,1: Last reload of fuse word 331 was done without.." bitfld.long 0x28 10. "VLDF330,Valid flag for shadow register 330" "0: An error occurred while fuse word 330 was last..,1: Last reload of fuse word 330 was done without.." newline bitfld.long 0x28 9. "VLDF329,Valid flag for shadow register 329" "0: An error occurred while fuse word 329 was last..,1: Last reload of fuse word 329 was done without.." bitfld.long 0x28 8. "VLDF328,Valid flag for shadow register 328" "0: An error occurred while fuse word 328 was last..,1: Last reload of fuse word 328 was done without.." newline bitfld.long 0x28 7. "VLDF327,Valid flag for shadow register 327" "0: An error occurred while fuse word 327 was last..,1: Last reload of fuse word 327 was done without.." bitfld.long 0x28 6. "VLDF326,Valid flag for shadow register 326" "0: An error occurred while fuse word 326 was last..,1: Last reload of fuse word 326 was done without.." newline bitfld.long 0x28 5. "VLDF325,Valid flag for shadow register 325" "0: An error occurred while fuse word 325 was last..,1: Last reload of fuse word 325 was done without.." bitfld.long 0x28 4. "VLDF324,Valid flag for shadow register 324" "0: An error occurred while fuse word 324 was last..,1: Last reload of fuse word 324 was done without.." newline bitfld.long 0x28 3. "VLDF323,Valid flag for shadow register 323" "0: An error occurred while fuse word 323 was last..,1: Last reload of fuse word 323 was done without.." bitfld.long 0x28 2. "VLDF322,Valid flag for shadow register 322" "0: An error occurred while fuse word 322 was last..,1: Last reload of fuse word 322 was done without.." newline bitfld.long 0x28 1. "VLDF321,Valid flag for shadow register 321" "0: An error occurred while fuse word 321 was last..,1: Last reload of fuse word 321 was done without.." bitfld.long 0x28 0. "VLDF320,Valid flag for shadow register 320" "0: An error occurred while fuse word 320 was last..,1: Last reload of fuse word 320 was done without.." line.long 0x2C "BSEC_OTPVLDR11,BSEC OTP valid register 11" bitfld.long 0x2C 31. "VLDF383,Valid flag for shadow register 383" "0: An error occurred while fuse word 383 was last..,1: Last reload of fuse word 383 was done without.." bitfld.long 0x2C 30. "VLDF382,Valid flag for shadow register 382" "0: An error occurred while fuse word 382 was last..,1: Last reload of fuse word 382 was done without.." newline bitfld.long 0x2C 29. "VLDF381,Valid flag for shadow register 381" "0: An error occurred while fuse word 381 was last..,1: Last reload of fuse word 381 was done without.." bitfld.long 0x2C 28. "VLDF380,Valid flag for shadow register 380" "0: An error occurred while fuse word 380 was last..,1: Last reload of fuse word 380 was done without.." newline bitfld.long 0x2C 27. "VLDF379,Valid flag for shadow register 379" "0: An error occurred while fuse word 379 was last..,1: Last reload of fuse word 379 was done without.." bitfld.long 0x2C 26. "VLDF378,Valid flag for shadow register 378" "0: An error occurred while fuse word 378 was last..,1: Last reload of fuse word 378 was done without.." newline bitfld.long 0x2C 25. "VLDF377,Valid flag for shadow register 377" "0: An error occurred while fuse word 377 was last..,1: Last reload of fuse word 377 was done without.." bitfld.long 0x2C 24. "VLDF376,Valid flag for shadow register 376" "0: An error occurred while fuse word 376 was last..,1: Last reload of fuse word 376 was done without.." newline bitfld.long 0x2C 23. "VLDF375,Valid flag for shadow register 375" "0: An error occurred while fuse word 375 was last..,1: Last reload of fuse word 375 was done without.." bitfld.long 0x2C 22. "VLDF374,Valid flag for shadow register 374" "0: An error occurred while fuse word 374 was last..,1: Last reload of fuse word 374 was done without.." newline bitfld.long 0x2C 21. "VLDF373,Valid flag for shadow register 373" "0: An error occurred while fuse word 373 was last..,1: Last reload of fuse word 373 was done without.." bitfld.long 0x2C 20. "VLDF372,Valid flag for shadow register 372" "0: An error occurred while fuse word 372 was last..,1: Last reload of fuse word 372 was done without.." newline bitfld.long 0x2C 19. "VLDF371,Valid flag for shadow register 371" "0: An error occurred while fuse word 371 was last..,1: Last reload of fuse word 371 was done without.." bitfld.long 0x2C 18. "VLDF370,Valid flag for shadow register 370" "0: An error occurred while fuse word 370 was last..,1: Last reload of fuse word 370 was done without.." newline bitfld.long 0x2C 17. "VLDF369,Valid flag for shadow register 369" "0: An error occurred while fuse word 369 was last..,1: Last reload of fuse word 369 was done without.." bitfld.long 0x2C 16. "VLDF368,Valid flag for shadow register 368" "0: An error occurred while fuse word 368 was last..,1: Last reload of fuse word 368 was done without.." newline bitfld.long 0x2C 15. "VLDF367,Valid flag for shadow register 367" "0: An error occurred while fuse word 367 was last..,1: Last reload of fuse word 367 was done without.." bitfld.long 0x2C 14. "VLDF366,Valid flag for shadow register 366" "0: An error occurred while fuse word 366 was last..,1: Last reload of fuse word 366 was done without.." newline bitfld.long 0x2C 13. "VLDF365,Valid flag for shadow register 365" "0: An error occurred while fuse word 365 was last..,1: Last reload of fuse word 365 was done without.." bitfld.long 0x2C 12. "VLDF364,Valid flag for shadow register 364" "0: An error occurred while fuse word 364 was last..,1: Last reload of fuse word 364 was done without.." newline bitfld.long 0x2C 11. "VLDF363,Valid flag for shadow register 363" "0: An error occurred while fuse word 363 was last..,1: Last reload of fuse word 363 was done without.." bitfld.long 0x2C 10. "VLDF362,Valid flag for shadow register 362" "0: An error occurred while fuse word 362 was last..,1: Last reload of fuse word 362 was done without.." newline bitfld.long 0x2C 9. "VLDF361,Valid flag for shadow register 361" "0: An error occurred while fuse word 361 was last..,1: Last reload of fuse word 361 was done without.." bitfld.long 0x2C 8. "VLDF360,Valid flag for shadow register 360" "0: An error occurred while fuse word 360 was last..,1: Last reload of fuse word 360 was done without.." newline bitfld.long 0x2C 7. "VLDF359,Valid flag for shadow register 359" "0: An error occurred while fuse word 359 was last..,1: Last reload of fuse word 359 was done without.." bitfld.long 0x2C 6. "VLDF358,Valid flag for shadow register 358" "0: An error occurred while fuse word 358 was last..,1: Last reload of fuse word 358 was done without.." newline bitfld.long 0x2C 5. "VLDF357,Valid flag for shadow register 357" "0: An error occurred while fuse word 357 was last..,1: Last reload of fuse word 357 was done without.." bitfld.long 0x2C 4. "VLDF356,Valid flag for shadow register 356" "0: An error occurred while fuse word 356 was last..,1: Last reload of fuse word 356 was done without.." newline bitfld.long 0x2C 3. "VLDF355,Valid flag for shadow register 355" "0: An error occurred while fuse word 355 was last..,1: Last reload of fuse word 355 was done without.." bitfld.long 0x2C 2. "VLDF354,Valid flag for shadow register 354" "0: An error occurred while fuse word 354 was last..,1: Last reload of fuse word 354 was done without.." newline bitfld.long 0x2C 1. "VLDF353,Valid flag for shadow register 353" "0: An error occurred while fuse word 353 was last..,1: Last reload of fuse word 353 was done without.." bitfld.long 0x2C 0. "VLDF352,Valid flag for shadow register 352" "0: An error occurred while fuse word 352 was last..,1: Last reload of fuse word 352 was done without.." rgroup.long 0x940++0x2F line.long 0x0 "BSEC_SFSR0,BSEC shadowed fuses status register 0" bitfld.long 0x0 31. "SFW31,Shadowed fuse word 31" "0: Fuse word 31 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR31 register." bitfld.long 0x0 30. "SFW30,Shadowed fuse word 30" "0: Fuse word 30 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR30 register." newline bitfld.long 0x0 29. "SFW29,Shadowed fuse word 29" "0: Fuse word 29 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR29 register." bitfld.long 0x0 28. "SFW28,Shadowed fuse word 28" "0: Fuse word 28 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR28 register." newline bitfld.long 0x0 27. "SFW27,Shadowed fuse word 27" "0: Fuse word 27 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR27 register." bitfld.long 0x0 26. "SFW26,Shadowed fuse word 26" "0: Fuse word 26 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR26 register." newline bitfld.long 0x0 25. "SFW25,Shadowed fuse word 25" "0: Fuse word 25 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR25 register." bitfld.long 0x0 24. "SFW24,Shadowed fuse word 24" "0: Fuse word 24 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR24 register." newline bitfld.long 0x0 23. "SFW23,Shadowed fuse word 23" "0: Fuse word 23 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR23 register." bitfld.long 0x0 22. "SFW22,Shadowed fuse word 22" "0: Fuse word 22 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR22 register." newline bitfld.long 0x0 21. "SFW21,Shadowed fuse word 21" "0: Fuse word 21 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR21 register." bitfld.long 0x0 20. "SFW20,Shadowed fuse word 20" "0: Fuse word 20 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR20 register." newline bitfld.long 0x0 19. "SFW19,Shadowed fuse word 19" "0: Fuse word 19 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR19 register." bitfld.long 0x0 18. "SFW18,Shadowed fuse word 18" "0: Fuse word 18 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR18 register." newline bitfld.long 0x0 17. "SFW17,Shadowed fuse word 17" "0: Fuse word 17 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR17 register." bitfld.long 0x0 16. "SFW16,Shadowed fuse word 16" "0: Fuse word 16 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR16 register." newline bitfld.long 0x0 15. "SFW15,Shadowed fuse word 15" "0: Fuse word 15 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR15 register." bitfld.long 0x0 14. "SFW14,Shadowed fuse word 14" "0: Fuse word 14 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR14 register." newline bitfld.long 0x0 13. "SFW13,Shadowed fuse word 13" "0: Fuse word 13 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR13 register." bitfld.long 0x0 12. "SFW12,Shadowed fuse word 12" "0: Fuse word 12 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR12 register." newline bitfld.long 0x0 11. "SFW11,Shadowed fuse word 11" "0: Fuse word 11 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR11 register." bitfld.long 0x0 10. "SFW10,Shadowed fuse word 10" "0: Fuse word 10 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR10 register." newline bitfld.long 0x0 9. "SFW9,Shadowed fuse word 9" "0: Fuse word 9 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR9 register." bitfld.long 0x0 8. "SFW8,Shadowed fuse word 8" "0: Fuse word 8 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR8 register." newline bitfld.long 0x0 7. "SFW7,Shadowed fuse word 7" "0: Fuse word 7 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR7 register." bitfld.long 0x0 6. "SFW6,Shadowed fuse word 6" "0: Fuse word 6 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR6 register." newline bitfld.long 0x0 5. "SFW5,Shadowed fuse word 5" "0: Fuse word 5 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR5 register." bitfld.long 0x0 4. "SFW4,Shadowed fuse word 4" "0: Fuse word 4 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR4 register." newline bitfld.long 0x0 3. "SFW3,Shadowed fuse word 3" "0: Fuse word 3 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR3 register." bitfld.long 0x0 2. "SFW2,Shadowed fuse word 2" "0: Fuse word 2 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR2 register." newline bitfld.long 0x0 1. "SFW1,Shadowed fuse word 1" "0: Fuse word 1 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR1 register." bitfld.long 0x0 0. "SFW0,Shadowed fuse word 0" "0: Fuse word 0 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR0 register." line.long 0x4 "BSEC_SFSR1,BSEC shadowed fuses status register 1" bitfld.long 0x4 31. "SFW63,Shadowed fuse word 63" "0: Fuse word 63 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR63 register." bitfld.long 0x4 30. "SFW62,Shadowed fuse word 62" "0: Fuse word 62 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR62 register." newline bitfld.long 0x4 29. "SFW61,Shadowed fuse word 61" "0: Fuse word 61 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR61 register." bitfld.long 0x4 28. "SFW60,Shadowed fuse word 60" "0: Fuse word 60 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR60 register." newline bitfld.long 0x4 27. "SFW59,Shadowed fuse word 59" "0: Fuse word 59 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR59 register." bitfld.long 0x4 26. "SFW58,Shadowed fuse word 58" "0: Fuse word 58 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR58 register." newline bitfld.long 0x4 25. "SFW57,Shadowed fuse word 57" "0: Fuse word 57 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR57 register." bitfld.long 0x4 24. "SFW56,Shadowed fuse word 56" "0: Fuse word 56 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR56 register." newline bitfld.long 0x4 23. "SFW55,Shadowed fuse word 55" "0: Fuse word 55 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR55 register." bitfld.long 0x4 22. "SFW54,Shadowed fuse word 54" "0: Fuse word 54 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR54 register." newline bitfld.long 0x4 21. "SFW53,Shadowed fuse word 53" "0: Fuse word 53 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR53 register." bitfld.long 0x4 20. "SFW52,Shadowed fuse word 52" "0: Fuse word 52 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR52 register." newline bitfld.long 0x4 19. "SFW51,Shadowed fuse word 51" "0: Fuse word 51 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR51 register." bitfld.long 0x4 18. "SFW50,Shadowed fuse word 50" "0: Fuse word 50 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR50 register." newline bitfld.long 0x4 17. "SFW49,Shadowed fuse word 49" "0: Fuse word 49 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR49 register." bitfld.long 0x4 16. "SFW48,Shadowed fuse word 48" "0: Fuse word 48 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR48 register." newline bitfld.long 0x4 15. "SFW47,Shadowed fuse word 47" "0: Fuse word 47 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR47 register." bitfld.long 0x4 14. "SFW46,Shadowed fuse word 46" "0: Fuse word 46 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR46 register." newline bitfld.long 0x4 13. "SFW45,Shadowed fuse word 45" "0: Fuse word 45 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR45 register." bitfld.long 0x4 12. "SFW44,Shadowed fuse word 44" "0: Fuse word 44 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR44 register." newline bitfld.long 0x4 11. "SFW43,Shadowed fuse word 43" "0: Fuse word 43 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR43 register." bitfld.long 0x4 10. "SFW42,Shadowed fuse word 42" "0: Fuse word 42 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR42 register." newline bitfld.long 0x4 9. "SFW41,Shadowed fuse word 41" "0: Fuse word 41 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR41 register." bitfld.long 0x4 8. "SFW40,Shadowed fuse word 40" "0: Fuse word 40 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR40 register." newline bitfld.long 0x4 7. "SFW39,Shadowed fuse word 39" "0: Fuse word 39 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR39 register." bitfld.long 0x4 6. "SFW38,Shadowed fuse word 38" "0: Fuse word 38 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR38 register." newline bitfld.long 0x4 5. "SFW37,Shadowed fuse word 37" "0: Fuse word 37 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR37 register." bitfld.long 0x4 4. "SFW36,Shadowed fuse word 36" "0: Fuse word 36 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR36 register." newline bitfld.long 0x4 3. "SFW35,Shadowed fuse word 35" "0: Fuse word 35 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR35 register." bitfld.long 0x4 2. "SFW34,Shadowed fuse word 34" "0: Fuse word 34 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR34 register." newline bitfld.long 0x4 1. "SFW33,Shadowed fuse word 33" "0: Fuse word 33 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR33 register." bitfld.long 0x4 0. "SFW32,Shadowed fuse word 32" "0: Fuse word 32 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR32 register." line.long 0x8 "BSEC_SFSR2,BSEC shadowed fuses status register 2" bitfld.long 0x8 31. "SFW95,Shadowed fuse word 95" "0: Fuse word 95 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR95 register." bitfld.long 0x8 30. "SFW94,Shadowed fuse word 94" "0: Fuse word 94 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR94 register." newline bitfld.long 0x8 29. "SFW93,Shadowed fuse word 93" "0: Fuse word 93 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR93 register." bitfld.long 0x8 28. "SFW92,Shadowed fuse word 92" "0: Fuse word 92 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR92 register." newline bitfld.long 0x8 27. "SFW91,Shadowed fuse word 91" "0: Fuse word 91 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR91 register." bitfld.long 0x8 26. "SFW90,Shadowed fuse word 90" "0: Fuse word 90 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR90 register." newline bitfld.long 0x8 25. "SFW89,Shadowed fuse word 89" "0: Fuse word 89 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR89 register." bitfld.long 0x8 24. "SFW88,Shadowed fuse word 88" "0: Fuse word 88 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR88 register." newline bitfld.long 0x8 23. "SFW87,Shadowed fuse word 87" "0: Fuse word 87 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR87 register." bitfld.long 0x8 22. "SFW86,Shadowed fuse word 86" "0: Fuse word 86 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR86 register." newline bitfld.long 0x8 21. "SFW85,Shadowed fuse word 85" "0: Fuse word 85 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR85 register." bitfld.long 0x8 20. "SFW84,Shadowed fuse word 84" "0: Fuse word 84 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR84 register." newline bitfld.long 0x8 19. "SFW83,Shadowed fuse word 83" "0: Fuse word 83 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR83 register." bitfld.long 0x8 18. "SFW82,Shadowed fuse word 82" "0: Fuse word 82 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR82 register." newline bitfld.long 0x8 17. "SFW81,Shadowed fuse word 81" "0: Fuse word 81 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR81 register." bitfld.long 0x8 16. "SFW80,Shadowed fuse word 80" "0: Fuse word 80 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR80 register." newline bitfld.long 0x8 15. "SFW79,Shadowed fuse word 79" "0: Fuse word 79 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR79 register." bitfld.long 0x8 14. "SFW78,Shadowed fuse word 78" "0: Fuse word 78 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR78 register." newline bitfld.long 0x8 13. "SFW77,Shadowed fuse word 77" "0: Fuse word 77 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR77 register." bitfld.long 0x8 12. "SFW76,Shadowed fuse word 76" "0: Fuse word 76 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR76 register." newline bitfld.long 0x8 11. "SFW75,Shadowed fuse word 75" "0: Fuse word 75 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR75 register." bitfld.long 0x8 10. "SFW74,Shadowed fuse word 74" "0: Fuse word 74 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR74 register." newline bitfld.long 0x8 9. "SFW73,Shadowed fuse word 73" "0: Fuse word 73 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR73 register." bitfld.long 0x8 8. "SFW72,Shadowed fuse word 72" "0: Fuse word 72 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR72 register." newline bitfld.long 0x8 7. "SFW71,Shadowed fuse word 71" "0: Fuse word 71 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR71 register." bitfld.long 0x8 6. "SFW70,Shadowed fuse word 70" "0: Fuse word 70 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR70 register." newline bitfld.long 0x8 5. "SFW69,Shadowed fuse word 69" "0: Fuse word 69 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR69 register." bitfld.long 0x8 4. "SFW68,Shadowed fuse word 68" "0: Fuse word 68 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR68 register." newline bitfld.long 0x8 3. "SFW67,Shadowed fuse word 67" "0: Fuse word 67 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR67 register." bitfld.long 0x8 2. "SFW66,Shadowed fuse word 66" "0: Fuse word 66 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR66 register." newline bitfld.long 0x8 1. "SFW65,Shadowed fuse word 65" "0: Fuse word 65 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR65 register." bitfld.long 0x8 0. "SFW64,Shadowed fuse word 64" "0: Fuse word 64 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR64 register." line.long 0xC "BSEC_SFSR3,BSEC shadowed fuses status register 3" bitfld.long 0xC 31. "SFW127,Shadowed fuse word 127" "0: Fuse word 127 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR127 register." bitfld.long 0xC 30. "SFW126,Shadowed fuse word 126" "0: Fuse word 126 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR126 register." newline bitfld.long 0xC 29. "SFW125,Shadowed fuse word 125" "0: Fuse word 125 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR125 register." bitfld.long 0xC 28. "SFW124,Shadowed fuse word 124" "0: Fuse word 124 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR124 register." newline bitfld.long 0xC 27. "SFW123,Shadowed fuse word 123" "0: Fuse word 123 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR123 register." bitfld.long 0xC 26. "SFW122,Shadowed fuse word 122" "0: Fuse word 122 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR122 register." newline bitfld.long 0xC 25. "SFW121,Shadowed fuse word 121" "0: Fuse word 121 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR121 register." bitfld.long 0xC 24. "SFW120,Shadowed fuse word 120" "0: Fuse word 120 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR120 register." newline bitfld.long 0xC 23. "SFW119,Shadowed fuse word 119" "0: Fuse word 119 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR119 register." bitfld.long 0xC 22. "SFW118,Shadowed fuse word 118" "0: Fuse word 118 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR118 register." newline bitfld.long 0xC 21. "SFW117,Shadowed fuse word 117" "0: Fuse word 117 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR117 register." bitfld.long 0xC 20. "SFW116,Shadowed fuse word 116" "0: Fuse word 116 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR116 register." newline bitfld.long 0xC 19. "SFW115,Shadowed fuse word 115" "0: Fuse word 115 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR115 register." bitfld.long 0xC 18. "SFW114,Shadowed fuse word 114" "0: Fuse word 114 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR114 register." newline bitfld.long 0xC 17. "SFW113,Shadowed fuse word 113" "0: Fuse word 113 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR113 register." bitfld.long 0xC 16. "SFW112,Shadowed fuse word 112" "0: Fuse word 112 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR112 register." newline bitfld.long 0xC 15. "SFW111,Shadowed fuse word 111" "0: Fuse word 111 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR111 register." bitfld.long 0xC 14. "SFW110,Shadowed fuse word 110" "0: Fuse word 110 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR110 register." newline bitfld.long 0xC 13. "SFW109,Shadowed fuse word 109" "0: Fuse word 109 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR109 register." bitfld.long 0xC 12. "SFW108,Shadowed fuse word 108" "0: Fuse word 108 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR108 register." newline bitfld.long 0xC 11. "SFW107,Shadowed fuse word 107" "0: Fuse word 107 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR107 register." bitfld.long 0xC 10. "SFW106,Shadowed fuse word 106" "0: Fuse word 106 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR106 register." newline bitfld.long 0xC 9. "SFW105,Shadowed fuse word 105" "0: Fuse word 105 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR105 register." bitfld.long 0xC 8. "SFW104,Shadowed fuse word 104" "0: Fuse word 104 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR104 register." newline bitfld.long 0xC 7. "SFW103,Shadowed fuse word 103" "0: Fuse word 103 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR103 register." bitfld.long 0xC 6. "SFW102,Shadowed fuse word 102" "0: Fuse word 102 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR102 register." newline bitfld.long 0xC 5. "SFW101,Shadowed fuse word 101" "0: Fuse word 101 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR101 register." bitfld.long 0xC 4. "SFW100,Shadowed fuse word 100" "0: Fuse word 100 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR100 register." newline bitfld.long 0xC 3. "SFW99,Shadowed fuse word 99" "0: Fuse word 99 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR99 register." bitfld.long 0xC 2. "SFW98,Shadowed fuse word 98" "0: Fuse word 98 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR98 register." newline bitfld.long 0xC 1. "SFW97,Shadowed fuse word 97" "0: Fuse word 97 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR97 register." bitfld.long 0xC 0. "SFW96,Shadowed fuse word 96" "0: Fuse word 96 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR96 register." line.long 0x10 "BSEC_SFSR4,BSEC shadowed fuses status register 4" bitfld.long 0x10 31. "SFW159,Shadowed fuse word 159" "0: Fuse word 159 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR159 register." bitfld.long 0x10 30. "SFW158,Shadowed fuse word 158" "0: Fuse word 158 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR158 register." newline bitfld.long 0x10 29. "SFW157,Shadowed fuse word 157" "0: Fuse word 157 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR157 register." bitfld.long 0x10 28. "SFW156,Shadowed fuse word 156" "0: Fuse word 156 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR156 register." newline bitfld.long 0x10 27. "SFW155,Shadowed fuse word 155" "0: Fuse word 155 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR155 register." bitfld.long 0x10 26. "SFW154,Shadowed fuse word 154" "0: Fuse word 154 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR154 register." newline bitfld.long 0x10 25. "SFW153,Shadowed fuse word 153" "0: Fuse word 153 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR153 register." bitfld.long 0x10 24. "SFW152,Shadowed fuse word 152" "0: Fuse word 152 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR152 register." newline bitfld.long 0x10 23. "SFW151,Shadowed fuse word 151" "0: Fuse word 151 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR151 register." bitfld.long 0x10 22. "SFW150,Shadowed fuse word 150" "0: Fuse word 150 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR150 register." newline bitfld.long 0x10 21. "SFW149,Shadowed fuse word 149" "0: Fuse word 149 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR149 register." bitfld.long 0x10 20. "SFW148,Shadowed fuse word 148" "0: Fuse word 148 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR148 register." newline bitfld.long 0x10 19. "SFW147,Shadowed fuse word 147" "0: Fuse word 147 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR147 register." bitfld.long 0x10 18. "SFW146,Shadowed fuse word 146" "0: Fuse word 146 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR146 register." newline bitfld.long 0x10 17. "SFW145,Shadowed fuse word 145" "0: Fuse word 145 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR145 register." bitfld.long 0x10 16. "SFW144,Shadowed fuse word 144" "0: Fuse word 144 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR144 register." newline bitfld.long 0x10 15. "SFW143,Shadowed fuse word 143" "0: Fuse word 143 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR143 register." bitfld.long 0x10 14. "SFW142,Shadowed fuse word 142" "0: Fuse word 142 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR142 register." newline bitfld.long 0x10 13. "SFW141,Shadowed fuse word 141" "0: Fuse word 141 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR141 register." bitfld.long 0x10 12. "SFW140,Shadowed fuse word 140" "0: Fuse word 140 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR140 register." newline bitfld.long 0x10 11. "SFW139,Shadowed fuse word 139" "0: Fuse word 139 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR139 register." bitfld.long 0x10 10. "SFW138,Shadowed fuse word 138" "0: Fuse word 138 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR138 register." newline bitfld.long 0x10 9. "SFW137,Shadowed fuse word 137" "0: Fuse word 137 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR137 register." bitfld.long 0x10 8. "SFW136,Shadowed fuse word 136" "0: Fuse word 136 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR136 register." newline bitfld.long 0x10 7. "SFW135,Shadowed fuse word 135" "0: Fuse word 135 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR135 register." bitfld.long 0x10 6. "SFW134,Shadowed fuse word 134" "0: Fuse word 134 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR134 register." newline bitfld.long 0x10 5. "SFW133,Shadowed fuse word 133" "0: Fuse word 133 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR133 register." bitfld.long 0x10 4. "SFW132,Shadowed fuse word 132" "0: Fuse word 132 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR132 register." newline bitfld.long 0x10 3. "SFW131,Shadowed fuse word 131" "0: Fuse word 131 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR131 register." bitfld.long 0x10 2. "SFW130,Shadowed fuse word 130" "0: Fuse word 130 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR130 register." newline bitfld.long 0x10 1. "SFW129,Shadowed fuse word 129" "0: Fuse word 129 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR129 register." bitfld.long 0x10 0. "SFW128,Shadowed fuse word 128" "0: Fuse word 128 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR128 register." line.long 0x14 "BSEC_SFSR5,BSEC shadowed fuses status register 5" bitfld.long 0x14 31. "SFW191,Shadowed fuse word 191" "0: Fuse word 191 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR191 register." bitfld.long 0x14 30. "SFW190,Shadowed fuse word 190" "0: Fuse word 190 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR190 register." newline bitfld.long 0x14 29. "SFW189,Shadowed fuse word 189" "0: Fuse word 189 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR189 register." bitfld.long 0x14 28. "SFW188,Shadowed fuse word 188" "0: Fuse word 188 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR188 register." newline bitfld.long 0x14 27. "SFW187,Shadowed fuse word 187" "0: Fuse word 187 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR187 register." bitfld.long 0x14 26. "SFW186,Shadowed fuse word 186" "0: Fuse word 186 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR186 register." newline bitfld.long 0x14 25. "SFW185,Shadowed fuse word 185" "0: Fuse word 185 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR185 register." bitfld.long 0x14 24. "SFW184,Shadowed fuse word 184" "0: Fuse word 184 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR184 register." newline bitfld.long 0x14 23. "SFW183,Shadowed fuse word 183" "0: Fuse word 183 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR183 register." bitfld.long 0x14 22. "SFW182,Shadowed fuse word 182" "0: Fuse word 182 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR182 register." newline bitfld.long 0x14 21. "SFW181,Shadowed fuse word 181" "0: Fuse word 181 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR181 register." bitfld.long 0x14 20. "SFW180,Shadowed fuse word 180" "0: Fuse word 180 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR180 register." newline bitfld.long 0x14 19. "SFW179,Shadowed fuse word 179" "0: Fuse word 179 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR179 register." bitfld.long 0x14 18. "SFW178,Shadowed fuse word 178" "0: Fuse word 178 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR178 register." newline bitfld.long 0x14 17. "SFW177,Shadowed fuse word 177" "0: Fuse word 177 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR177 register." bitfld.long 0x14 16. "SFW176,Shadowed fuse word 176" "0: Fuse word 176 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR176 register." newline bitfld.long 0x14 15. "SFW175,Shadowed fuse word 175" "0: Fuse word 175 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR175 register." bitfld.long 0x14 14. "SFW174,Shadowed fuse word 174" "0: Fuse word 174 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR174 register." newline bitfld.long 0x14 13. "SFW173,Shadowed fuse word 173" "0: Fuse word 173 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR173 register." bitfld.long 0x14 12. "SFW172,Shadowed fuse word 172" "0: Fuse word 172 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR172 register." newline bitfld.long 0x14 11. "SFW171,Shadowed fuse word 171" "0: Fuse word 171 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR171 register." bitfld.long 0x14 10. "SFW170,Shadowed fuse word 170" "0: Fuse word 170 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR170 register." newline bitfld.long 0x14 9. "SFW169,Shadowed fuse word 169" "0: Fuse word 169 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR169 register." bitfld.long 0x14 8. "SFW168,Shadowed fuse word 168" "0: Fuse word 168 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR168 register." newline bitfld.long 0x14 7. "SFW167,Shadowed fuse word 167" "0: Fuse word 167 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR167 register." bitfld.long 0x14 6. "SFW166,Shadowed fuse word 166" "0: Fuse word 166 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR166 register." newline bitfld.long 0x14 5. "SFW165,Shadowed fuse word 165" "0: Fuse word 165 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR165 register." bitfld.long 0x14 4. "SFW164,Shadowed fuse word 164" "0: Fuse word 164 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR164 register." newline bitfld.long 0x14 3. "SFW163,Shadowed fuse word 163" "0: Fuse word 163 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR163 register." bitfld.long 0x14 2. "SFW162,Shadowed fuse word 162" "0: Fuse word 162 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR162 register." newline bitfld.long 0x14 1. "SFW161,Shadowed fuse word 161" "0: Fuse word 161 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR161 register." bitfld.long 0x14 0. "SFW160,Shadowed fuse word 160" "0: Fuse word 160 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR160 register." line.long 0x18 "BSEC_SFSR6,BSEC shadowed fuses status register 6" bitfld.long 0x18 31. "SFW223,Shadowed fuse word 223" "0: Fuse word 223 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR223 register." bitfld.long 0x18 30. "SFW222,Shadowed fuse word 222" "0: Fuse word 222 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR222 register." newline bitfld.long 0x18 29. "SFW221,Shadowed fuse word 221" "0: Fuse word 221 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR221 register." bitfld.long 0x18 28. "SFW220,Shadowed fuse word 220" "0: Fuse word 220 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR220 register." newline bitfld.long 0x18 27. "SFW219,Shadowed fuse word 219" "0: Fuse word 219 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR219 register." bitfld.long 0x18 26. "SFW218,Shadowed fuse word 218" "0: Fuse word 218 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR218 register." newline bitfld.long 0x18 25. "SFW217,Shadowed fuse word 217" "0: Fuse word 217 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR217 register." bitfld.long 0x18 24. "SFW216,Shadowed fuse word 216" "0: Fuse word 216 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR216 register." newline bitfld.long 0x18 23. "SFW215,Shadowed fuse word 215" "0: Fuse word 215 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR215 register." bitfld.long 0x18 22. "SFW214,Shadowed fuse word 214" "0: Fuse word 214 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR214 register." newline bitfld.long 0x18 21. "SFW213,Shadowed fuse word 213" "0: Fuse word 213 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR213 register." bitfld.long 0x18 20. "SFW212,Shadowed fuse word 212" "0: Fuse word 212 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR212 register." newline bitfld.long 0x18 19. "SFW211,Shadowed fuse word 211" "0: Fuse word 211 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR211 register." bitfld.long 0x18 18. "SFW210,Shadowed fuse word 210" "0: Fuse word 210 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR210 register." newline bitfld.long 0x18 17. "SFW209,Shadowed fuse word 209" "0: Fuse word 209 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR209 register." bitfld.long 0x18 16. "SFW208,Shadowed fuse word 208" "0: Fuse word 208 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR208 register." newline bitfld.long 0x18 15. "SFW207,Shadowed fuse word 207" "0: Fuse word 207 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR207 register." bitfld.long 0x18 14. "SFW206,Shadowed fuse word 206" "0: Fuse word 206 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR206 register." newline bitfld.long 0x18 13. "SFW205,Shadowed fuse word 205" "0: Fuse word 205 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR205 register." bitfld.long 0x18 12. "SFW204,Shadowed fuse word 204" "0: Fuse word 204 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR204 register." newline bitfld.long 0x18 11. "SFW203,Shadowed fuse word 203" "0: Fuse word 203 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR203 register." bitfld.long 0x18 10. "SFW202,Shadowed fuse word 202" "0: Fuse word 202 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR202 register." newline bitfld.long 0x18 9. "SFW201,Shadowed fuse word 201" "0: Fuse word 201 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR201 register." bitfld.long 0x18 8. "SFW200,Shadowed fuse word 200" "0: Fuse word 200 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR200 register." newline bitfld.long 0x18 7. "SFW199,Shadowed fuse word 199" "0: Fuse word 199 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR199 register." bitfld.long 0x18 6. "SFW198,Shadowed fuse word 198" "0: Fuse word 198 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR198 register." newline bitfld.long 0x18 5. "SFW197,Shadowed fuse word 197" "0: Fuse word 197 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR197 register." bitfld.long 0x18 4. "SFW196,Shadowed fuse word 196" "0: Fuse word 196 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR196 register." newline bitfld.long 0x18 3. "SFW195,Shadowed fuse word 195" "0: Fuse word 195 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR195 register." bitfld.long 0x18 2. "SFW194,Shadowed fuse word 194" "0: Fuse word 194 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR194 register." newline bitfld.long 0x18 1. "SFW193,Shadowed fuse word 193" "0: Fuse word 193 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR193 register." bitfld.long 0x18 0. "SFW192,Shadowed fuse word 192" "0: Fuse word 192 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR192 register." line.long 0x1C "BSEC_SFSR7,BSEC shadowed fuses status register 7" bitfld.long 0x1C 31. "SFW255,Shadowed fuse word 255" "0: Fuse word 255 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR255 register." bitfld.long 0x1C 30. "SFW254,Shadowed fuse word 254" "0: Fuse word 254 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR254 register." newline bitfld.long 0x1C 29. "SFW253,Shadowed fuse word 253" "0: Fuse word 253 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR253 register." bitfld.long 0x1C 28. "SFW252,Shadowed fuse word 252" "0: Fuse word 252 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR252 register." newline bitfld.long 0x1C 27. "SFW251,Shadowed fuse word 251" "0: Fuse word 251 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR251 register." bitfld.long 0x1C 26. "SFW250,Shadowed fuse word 250" "0: Fuse word 250 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR250 register." newline bitfld.long 0x1C 25. "SFW249,Shadowed fuse word 249" "0: Fuse word 249 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR249 register." bitfld.long 0x1C 24. "SFW248,Shadowed fuse word 248" "0: Fuse word 248 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR248 register." newline bitfld.long 0x1C 23. "SFW247,Shadowed fuse word 247" "0: Fuse word 247 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR247 register." bitfld.long 0x1C 22. "SFW246,Shadowed fuse word 246" "0: Fuse word 246 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR246 register." newline bitfld.long 0x1C 21. "SFW245,Shadowed fuse word 245" "0: Fuse word 245 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR245 register." bitfld.long 0x1C 20. "SFW244,Shadowed fuse word 244" "0: Fuse word 244 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR244 register." newline bitfld.long 0x1C 19. "SFW243,Shadowed fuse word 243" "0: Fuse word 243 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR243 register." bitfld.long 0x1C 18. "SFW242,Shadowed fuse word 242" "0: Fuse word 242 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR242 register." newline bitfld.long 0x1C 17. "SFW241,Shadowed fuse word 241" "0: Fuse word 241 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR241 register." bitfld.long 0x1C 16. "SFW240,Shadowed fuse word 240" "0: Fuse word 240 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR240 register." newline bitfld.long 0x1C 15. "SFW239,Shadowed fuse word 239" "0: Fuse word 239 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR239 register." bitfld.long 0x1C 14. "SFW238,Shadowed fuse word 238" "0: Fuse word 238 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR238 register." newline bitfld.long 0x1C 13. "SFW237,Shadowed fuse word 237" "0: Fuse word 237 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR237 register." bitfld.long 0x1C 12. "SFW236,Shadowed fuse word 236" "0: Fuse word 236 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR236 register." newline bitfld.long 0x1C 11. "SFW235,Shadowed fuse word 235" "0: Fuse word 235 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR235 register." bitfld.long 0x1C 10. "SFW234,Shadowed fuse word 234" "0: Fuse word 234 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR234 register." newline bitfld.long 0x1C 9. "SFW233,Shadowed fuse word 233" "0: Fuse word 233 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR233 register." bitfld.long 0x1C 8. "SFW232,Shadowed fuse word 232" "0: Fuse word 232 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR232 register." newline bitfld.long 0x1C 7. "SFW231,Shadowed fuse word 231" "0: Fuse word 231 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR231 register." bitfld.long 0x1C 6. "SFW230,Shadowed fuse word 230" "0: Fuse word 230 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR230 register." newline bitfld.long 0x1C 5. "SFW229,Shadowed fuse word 229" "0: Fuse word 229 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR229 register." bitfld.long 0x1C 4. "SFW228,Shadowed fuse word 228" "0: Fuse word 228 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR228 register." newline bitfld.long 0x1C 3. "SFW227,Shadowed fuse word 227" "0: Fuse word 227 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR227 register." bitfld.long 0x1C 2. "SFW226,Shadowed fuse word 226" "0: Fuse word 226 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR226 register." newline bitfld.long 0x1C 1. "SFW225,Shadowed fuse word 225" "0: Fuse word 225 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR225 register." bitfld.long 0x1C 0. "SFW224,Shadowed fuse word 224" "0: Fuse word 224 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR224 register." line.long 0x20 "BSEC_SFSR8,BSEC shadowed fuses status register 8" bitfld.long 0x20 31. "SFW287,Shadowed fuse word 287" "0: Fuse word 287 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR287 register." bitfld.long 0x20 30. "SFW286,Shadowed fuse word 286" "0: Fuse word 286 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR286 register." newline bitfld.long 0x20 29. "SFW285,Shadowed fuse word 285" "0: Fuse word 285 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR285 register." bitfld.long 0x20 28. "SFW284,Shadowed fuse word 284" "0: Fuse word 284 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR284 register." newline bitfld.long 0x20 27. "SFW283,Shadowed fuse word 283" "0: Fuse word 283 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR283 register." bitfld.long 0x20 26. "SFW282,Shadowed fuse word 282" "0: Fuse word 282 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR282 register." newline bitfld.long 0x20 25. "SFW281,Shadowed fuse word 281" "0: Fuse word 281 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR281 register." bitfld.long 0x20 24. "SFW280,Shadowed fuse word 280" "0: Fuse word 280 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR280 register." newline bitfld.long 0x20 23. "SFW279,Shadowed fuse word 279" "0: Fuse word 279 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR279 register." bitfld.long 0x20 22. "SFW278,Shadowed fuse word 278" "0: Fuse word 278 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR278 register." newline bitfld.long 0x20 21. "SFW277,Shadowed fuse word 277" "0: Fuse word 277 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR277 register." bitfld.long 0x20 20. "SFW276,Shadowed fuse word 276" "0: Fuse word 276 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR276 register." newline bitfld.long 0x20 19. "SFW275,Shadowed fuse word 275" "0: Fuse word 275 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR275 register." bitfld.long 0x20 18. "SFW274,Shadowed fuse word 274" "0: Fuse word 274 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR274 register." newline bitfld.long 0x20 17. "SFW273,Shadowed fuse word 273" "0: Fuse word 273 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR273 register." bitfld.long 0x20 16. "SFW272,Shadowed fuse word 272" "0: Fuse word 272 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR272 register." newline bitfld.long 0x20 15. "SFW271,Shadowed fuse word 271" "0: Fuse word 271 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR271 register." bitfld.long 0x20 14. "SFW270,Shadowed fuse word 270" "0: Fuse word 270 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR270 register." newline bitfld.long 0x20 13. "SFW269,Shadowed fuse word 269" "0: Fuse word 269 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR269 register." bitfld.long 0x20 12. "SFW268,Shadowed fuse word 268" "0: Fuse word 268 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR268 register." newline bitfld.long 0x20 11. "SFW267,Shadowed fuse word 267" "0: Fuse word 267 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR267 register." bitfld.long 0x20 10. "SFW266,Shadowed fuse word 266" "0: Fuse word 266 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR266 register." newline bitfld.long 0x20 9. "SFW265,Shadowed fuse word 265" "0: Fuse word 265 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR265 register." bitfld.long 0x20 8. "SFW264,Shadowed fuse word 264" "0: Fuse word 264 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR264 register." newline bitfld.long 0x20 7. "SFW263,Shadowed fuse word 263" "0: Fuse word 263 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR263 register." bitfld.long 0x20 6. "SFW262,Shadowed fuse word 262" "0: Fuse word 262 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR262 register." newline bitfld.long 0x20 5. "SFW261,Shadowed fuse word 261" "0: Fuse word 261 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR261 register." bitfld.long 0x20 4. "SFW260,Shadowed fuse word 260" "0: Fuse word 260 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR260 register." newline bitfld.long 0x20 3. "SFW259,Shadowed fuse word 259" "0: Fuse word 259 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR259 register." bitfld.long 0x20 2. "SFW258,Shadowed fuse word 258" "0: Fuse word 258 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR258 register." newline bitfld.long 0x20 1. "SFW257,Shadowed fuse word 257" "0: Fuse word 257 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR257 register." bitfld.long 0x20 0. "SFW256,Shadowed fuse word 256" "0: Fuse word 256 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR256 register." line.long 0x24 "BSEC_SFSR9,BSEC shadowed fuses status register 9" bitfld.long 0x24 31. "SFW319,Shadowed fuse word 319" "0: Fuse word 319 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR319 register." bitfld.long 0x24 30. "SFW318,Shadowed fuse word 318" "0: Fuse word 318 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR318 register." newline bitfld.long 0x24 29. "SFW317,Shadowed fuse word 317" "0: Fuse word 317 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR317 register." bitfld.long 0x24 28. "SFW316,Shadowed fuse word 316" "0: Fuse word 316 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR316 register." newline bitfld.long 0x24 27. "SFW315,Shadowed fuse word 315" "0: Fuse word 315 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR315 register." bitfld.long 0x24 26. "SFW314,Shadowed fuse word 314" "0: Fuse word 314 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR314 register." newline bitfld.long 0x24 25. "SFW313,Shadowed fuse word 313" "0: Fuse word 313 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR313 register." bitfld.long 0x24 24. "SFW312,Shadowed fuse word 312" "0: Fuse word 312 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR312 register." newline bitfld.long 0x24 23. "SFW311,Shadowed fuse word 311" "0: Fuse word 311 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR311 register." bitfld.long 0x24 22. "SFW310,Shadowed fuse word 310" "0: Fuse word 310 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR310 register." newline bitfld.long 0x24 21. "SFW309,Shadowed fuse word 309" "0: Fuse word 309 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR309 register." bitfld.long 0x24 20. "SFW308,Shadowed fuse word 308" "0: Fuse word 308 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR308 register." newline bitfld.long 0x24 19. "SFW307,Shadowed fuse word 307" "0: Fuse word 307 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR307 register." bitfld.long 0x24 18. "SFW306,Shadowed fuse word 306" "0: Fuse word 306 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR306 register." newline bitfld.long 0x24 17. "SFW305,Shadowed fuse word 305" "0: Fuse word 305 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR305 register." bitfld.long 0x24 16. "SFW304,Shadowed fuse word 304" "0: Fuse word 304 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR304 register." newline bitfld.long 0x24 15. "SFW303,Shadowed fuse word 303" "0: Fuse word 303 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR303 register." bitfld.long 0x24 14. "SFW302,Shadowed fuse word 302" "0: Fuse word 302 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR302 register." newline bitfld.long 0x24 13. "SFW301,Shadowed fuse word 301" "0: Fuse word 301 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR301 register." bitfld.long 0x24 12. "SFW300,Shadowed fuse word 300" "0: Fuse word 300 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR300 register." newline bitfld.long 0x24 11. "SFW299,Shadowed fuse word 299" "0: Fuse word 299 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR299 register." bitfld.long 0x24 10. "SFW298,Shadowed fuse word 298" "0: Fuse word 298 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR298 register." newline bitfld.long 0x24 9. "SFW297,Shadowed fuse word 297" "0: Fuse word 297 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR297 register." bitfld.long 0x24 8. "SFW296,Shadowed fuse word 296" "0: Fuse word 296 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR296 register." newline bitfld.long 0x24 7. "SFW295,Shadowed fuse word 295" "0: Fuse word 295 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR295 register." bitfld.long 0x24 6. "SFW294,Shadowed fuse word 294" "0: Fuse word 294 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR294 register." newline bitfld.long 0x24 5. "SFW293,Shadowed fuse word 293" "0: Fuse word 293 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR293 register." bitfld.long 0x24 4. "SFW292,Shadowed fuse word 292" "0: Fuse word 292 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR292 register." newline bitfld.long 0x24 3. "SFW291,Shadowed fuse word 291" "0: Fuse word 291 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR291 register." bitfld.long 0x24 2. "SFW290,Shadowed fuse word 290" "0: Fuse word 290 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR290 register." newline bitfld.long 0x24 1. "SFW289,Shadowed fuse word 289" "0: Fuse word 289 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR289 register." bitfld.long 0x24 0. "SFW288,Shadowed fuse word 288" "0: Fuse word 288 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR288 register." line.long 0x28 "BSEC_SFSR10,BSEC shadowed fuses status register 10" bitfld.long 0x28 31. "SFW351,Shadowed fuse word 351" "0: Fuse word 351 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR351 register." bitfld.long 0x28 30. "SFW350,Shadowed fuse word 350" "0: Fuse word 350 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR350 register." newline bitfld.long 0x28 29. "SFW349,Shadowed fuse word 349" "0: Fuse word 349 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR349 register." bitfld.long 0x28 28. "SFW348,Shadowed fuse word 348" "0: Fuse word 348 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR348 register." newline bitfld.long 0x28 27. "SFW347,Shadowed fuse word 347" "0: Fuse word 347 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR347 register." bitfld.long 0x28 26. "SFW346,Shadowed fuse word 346" "0: Fuse word 346 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR346 register." newline bitfld.long 0x28 25. "SFW345,Shadowed fuse word 345" "0: Fuse word 345 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR345 register." bitfld.long 0x28 24. "SFW344,Shadowed fuse word 344" "0: Fuse word 344 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR344 register." newline bitfld.long 0x28 23. "SFW343,Shadowed fuse word 343" "0: Fuse word 343 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR343 register." bitfld.long 0x28 22. "SFW342,Shadowed fuse word 342" "0: Fuse word 342 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR342 register." newline bitfld.long 0x28 21. "SFW341,Shadowed fuse word 341" "0: Fuse word 341 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR341 register." bitfld.long 0x28 20. "SFW340,Shadowed fuse word 340" "0: Fuse word 340 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR340 register." newline bitfld.long 0x28 19. "SFW339,Shadowed fuse word 339" "0: Fuse word 339 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR339 register." bitfld.long 0x28 18. "SFW338,Shadowed fuse word 338" "0: Fuse word 338 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR338 register." newline bitfld.long 0x28 17. "SFW337,Shadowed fuse word 337" "0: Fuse word 337 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR337 register." bitfld.long 0x28 16. "SFW336,Shadowed fuse word 336" "0: Fuse word 336 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR336 register." newline bitfld.long 0x28 15. "SFW335,Shadowed fuse word 335" "0: Fuse word 335 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR335 register." bitfld.long 0x28 14. "SFW334,Shadowed fuse word 334" "0: Fuse word 334 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR334 register." newline bitfld.long 0x28 13. "SFW333,Shadowed fuse word 333" "0: Fuse word 333 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR333 register." bitfld.long 0x28 12. "SFW332,Shadowed fuse word 332" "0: Fuse word 332 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR332 register." newline bitfld.long 0x28 11. "SFW331,Shadowed fuse word 331" "0: Fuse word 331 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR331 register." bitfld.long 0x28 10. "SFW330,Shadowed fuse word 330" "0: Fuse word 330 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR330 register." newline bitfld.long 0x28 9. "SFW329,Shadowed fuse word 329" "0: Fuse word 329 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR329 register." bitfld.long 0x28 8. "SFW328,Shadowed fuse word 328" "0: Fuse word 328 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR328 register." newline bitfld.long 0x28 7. "SFW327,Shadowed fuse word 327" "0: Fuse word 327 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR327 register." bitfld.long 0x28 6. "SFW326,Shadowed fuse word 326" "0: Fuse word 326 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR326 register." newline bitfld.long 0x28 5. "SFW325,Shadowed fuse word 325" "0: Fuse word 325 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR325 register." bitfld.long 0x28 4. "SFW324,Shadowed fuse word 324" "0: Fuse word 324 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR324 register." newline bitfld.long 0x28 3. "SFW323,Shadowed fuse word 323" "0: Fuse word 323 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR323 register." bitfld.long 0x28 2. "SFW322,Shadowed fuse word 322" "0: Fuse word 322 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR322 register." newline bitfld.long 0x28 1. "SFW321,Shadowed fuse word 321" "0: Fuse word 321 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR321 register." bitfld.long 0x28 0. "SFW320,Shadowed fuse word 320" "0: Fuse word 320 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR320 register." line.long 0x2C "BSEC_SFSR11,BSEC shadowed fuses status register 11" bitfld.long 0x2C 31. "SFW383,Shadowed fuse word 383" "0: Fuse word 383 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR383 register." bitfld.long 0x2C 30. "SFW382,Shadowed fuse word 382" "0: Fuse word 382 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR382 register." newline bitfld.long 0x2C 29. "SFW381,Shadowed fuse word 381" "0: Fuse word 381 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR381 register." bitfld.long 0x2C 28. "SFW380,Shadowed fuse word 380" "0: Fuse word 380 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR380 register." newline bitfld.long 0x2C 27. "SFW379,Shadowed fuse word 379" "0: Fuse word 379 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR379 register." bitfld.long 0x2C 26. "SFW378,Shadowed fuse word 378" "0: Fuse word 378 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR378 register." newline bitfld.long 0x2C 25. "SFW377,Shadowed fuse word 377" "0: Fuse word 377 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR377 register." bitfld.long 0x2C 24. "SFW376,Shadowed fuse word 376" "0: Fuse word 376 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR376 register." newline bitfld.long 0x2C 23. "SFW375,Shadowed fuse word 375" "0: Fuse word 375 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR375 register." bitfld.long 0x2C 22. "SFW374,Shadowed fuse word 374" "0: Fuse word 374 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR374 register." newline bitfld.long 0x2C 21. "SFW373,Shadowed fuse word 373" "0: Fuse word 373 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR373 register." bitfld.long 0x2C 20. "SFW372,Shadowed fuse word 372" "0: Fuse word 372 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR372 register." newline bitfld.long 0x2C 19. "SFW371,Shadowed fuse word 371" "0: Fuse word 371 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR371 register." bitfld.long 0x2C 18. "SFW370,Shadowed fuse word 370" "0: Fuse word 370 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR370 register." newline bitfld.long 0x2C 17. "SFW369,Shadowed fuse word 369" "0: Fuse word 369 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR369 register." bitfld.long 0x2C 16. "SFW368,Shadowed fuse word 368" "0: Fuse word 368 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR368 register." newline bitfld.long 0x2C 15. "SFW367,Shadowed fuse word 367" "0: Fuse word 367 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR367 register." bitfld.long 0x2C 14. "SFW366,Shadowed fuse word 366" "0: Fuse word 366 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR366 register." newline bitfld.long 0x2C 13. "SFW365,Shadowed fuse word 365" "0: Fuse word 365 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR365 register." bitfld.long 0x2C 12. "SFW364,Shadowed fuse word 364" "0: Fuse word 364 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR364 register." newline bitfld.long 0x2C 11. "SFW363,Shadowed fuse word 363" "0: Fuse word 363 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR363 register." bitfld.long 0x2C 10. "SFW362,Shadowed fuse word 362" "0: Fuse word 362 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR362 register." newline bitfld.long 0x2C 9. "SFW361,Shadowed fuse word 361" "0: Fuse word 361 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR361 register." bitfld.long 0x2C 8. "SFW360,Shadowed fuse word 360" "0: Fuse word 360 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR360 register." newline bitfld.long 0x2C 7. "SFW359,Shadowed fuse word 359" "0: Fuse word 359 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR359 register." bitfld.long 0x2C 6. "SFW358,Shadowed fuse word 358" "0: Fuse word 358 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR358 register." newline bitfld.long 0x2C 5. "SFW357,Shadowed fuse word 357" "0: Fuse word 357 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR357 register." bitfld.long 0x2C 4. "SFW356,Shadowed fuse word 356" "0: Fuse word 356 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR356 register." newline bitfld.long 0x2C 3. "SFW355,Shadowed fuse word 355" "0: Fuse word 355 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR355 register." bitfld.long 0x2C 2. "SFW354,Shadowed fuse word 354" "0: Fuse word 354 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR354 register." newline bitfld.long 0x2C 1. "SFW353,Shadowed fuse word 353" "0: Fuse word 353 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR353 register." bitfld.long 0x2C 0. "SFW352,Shadowed fuse word 352" "0: Fuse word 352 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR352 register." group.long 0xC04++0x3 line.long 0x0 "BSEC_OTPCR,BSEC OTP control register" rbitfld.long 0x0 19.--21. "LASTCID,Last CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 14. "PPLOCK,Permanent programming lock" "0: Fuse word at address ADDR[8:0] is programmed..,1: Fuse word at address ADDR[8:0] is locked.." newline bitfld.long 0x0 13. "PROG,Fuse word programming" "0: Fuse word read operation is required,1: Fuse word programming operation is required" hexmask.long.word 0x0 0.--8. 1. "ADDR,Fuse word address" wgroup.long 0xC08++0x3 line.long 0x0 "BSEC_WDR,BSEC write data register" hexmask.long 0x0 0.--31. 1. "WRDATA,OTP write data" group.long 0xE00++0x13 line.long 0x0 "BSEC_SCRATCHR0,BSEC scratch register 0" hexmask.long 0x0 0.--31. 1. "SDATA,Scratch data" line.long 0x4 "BSEC_SCRATCHR1,BSEC scratch register 1" hexmask.long 0x4 0.--31. 1. "SDATA,Scratch data" line.long 0x8 "BSEC_SCRATCHR2,BSEC scratch register 2" hexmask.long 0x8 0.--31. 1. "SDATA,Scratch data" line.long 0xC "BSEC_SCRATCHR3,BSEC scratch register 3" hexmask.long 0xC 0.--31. 1. "SDATA,Scratch data" line.long 0x10 "BSEC_LOCKR,BSEC lock register" bitfld.long 0x10 2. "HKLOCK,Hardware key lock" "0: Derived hardware unique key (DHUK) in SAES..,1: Derived hardware unique key (DHUK) in SAES.." bitfld.long 0x10 0. "GWLOCK,Global write lock" "0: Writes to BSEC registers are allowed,1: Writes to BSEC registers are ignored (fuse.." rgroup.long 0xE14++0x3 line.long 0x0 "BSEC_JTAGINR,BSEC JTAG input register" hexmask.long 0x0 0.--31. 1. "JDATAIN,JTAG input data" wgroup.long 0xE18++0x3 line.long 0x0 "BSEC_JTAGOUTR,BSEC JTAG output register" hexmask.long 0x0 0.--31. 1. "JDATAOUT,JTAG output data" group.long 0xE24++0x3 line.long 0x0 "BSEC_UNMAPR,BSEC unmap register" hexmask.long 0x0 0.--31. 1. "UNMAP,Unmap key" rgroup.long 0xE40++0x7 line.long 0x0 "BSEC_SR,BSEC status register" hexmask.long.byte 0x0 26.--31. 1. "NVSTATE,Non-volatile state" bitfld.long 0x0 16. "DBGREQ,debug request" "0: Host debugger is not requesting debug,1: Host debugger is requesting debug" newline bitfld.long 0x0 1. "HVALID,Hardware key valid" "0: Derived hardware unique key (DHUK) feature..,1: Derived hardware unique key (DHUK) feature can.." line.long 0x4 "BSEC_OTPSR,BSEC OTP status register" bitfld.long 0x4 22. "AMEF,Addresses mismatch error flag" "0,1" bitfld.long 0x4 21. "PPLMF,Permanent programming lock mismatch flag" "0,1" newline bitfld.long 0x4 20. "PPLF,Permanent programming lock flag" "0,1" bitfld.long 0x4 19. "SECF,Single error correction flag" "0,1" newline bitfld.long 0x4 18. "DEDF,Double error detection flag" "0,1" bitfld.long 0x4 17. "DISTURBF,Disturb flag" "0,1" newline bitfld.long 0x4 16. "PROGFAIL,Programming failed" "0,1" bitfld.long 0x4 6. "OTPSEC,OTP with single error correction" "0,1" newline bitfld.long 0x4 5. "OTPERR,OTP with error" "0,1" bitfld.long 0x4 4. "OTPNVIR,OTP not virgin" "0,1" newline bitfld.long 0x4 2. "HIDEUP,Hide upper fuse words" "0,1" bitfld.long 0x4 1. "INIT_DONE,Initialization done" "0,1" newline bitfld.long 0x4 0. "BUSY,Busy flag" "0: BSEC is idle,1: BSEC is busy" group.long 0xE80++0x13 line.long 0x0 "BSEC_EPOCHR0,BSEC epoch register" hexmask.long 0x0 0.--31. 1. "EPOCH,epoch" line.long 0x4 "BSEC_EPOCHR1,BSEC epoch register" hexmask.long 0x4 0.--31. 1. "EPOCH,epoch" line.long 0x8 "BSEC_EPOCH_SELR,BSEC epoch select register" bitfld.long 0x8 0. "EPSEL,Epoch selection. This value is wired out to the SAES peripheral." "0: SAES peripheral uses BSEC_EPOCHR0 as EPOCH value.,1: SAES peripheral uses BSEC_EPOCHR1 as EPOCH value." line.long 0xC "BSEC_DBGCR,BSEC Debug" hexmask.long.byte 0xC 24.--31. 1. "AUTH_SEC,any other value: secure debug not authorized (provided BSEC state is not OPEN)" hexmask.long.byte 0xC 16.--23. 1. "AUTH_HDPL,level at which debug may be opened." newline hexmask.long.byte 0xC 8.--15. 1. "UNLOCK,any other value: debug not authorized (provided BSEC state is not OPEN)" line.long 0x10 "BSEC_AP_UNLOCK,BSEC AP Unlock" hexmask.long.byte 0x10 0.--7. 1. "UNLOCK,any other value: do not unlock" rgroup.long 0xE94++0x3 line.long 0x0 "BSEC_HDPLSR,BSEC HDPL" hexmask.long.byte 0x0 0.--7. 1. "HDPL,current HDPL" wgroup.long 0xE98++0x3 line.long 0x0 "BSEC_HDPLCR,BSEC HDPL control" hexmask.long 0x0 0.--31. 1. "INCR_HDPL,Increment HDPL" group.long 0xE9C++0x3 line.long 0x0 "BSEC_NEXTLR,BSEC Next HDPL" bitfld.long 0x0 0.--1. "INCR,Increment" "0,1,2,3" group.long 0xF40++0x1F line.long 0x0 "BSEC_WOSCR0,BSEC write once scratch register 0" hexmask.long 0x0 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x4 "BSEC_WOSCR1,BSEC write once scratch register 1" hexmask.long 0x4 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x8 "BSEC_WOSCR2,BSEC write once scratch register 2" hexmask.long 0x8 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0xC "BSEC_WOSCR3,BSEC write once scratch register 3" hexmask.long 0xC 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x10 "BSEC_WOSCR4,BSEC write once scratch register 4" hexmask.long 0x10 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x14 "BSEC_WOSCR5,BSEC write once scratch register 5" hexmask.long 0x14 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x18 "BSEC_WOSCR6,BSEC write once scratch register 6" hexmask.long 0x18 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x1C "BSEC_WOSCR7,BSEC write once scratch register 7" hexmask.long 0x1C 0.--31. 1. "WOSDATA,Write once scratch data" rgroup.long 0xFE8++0x7 line.long 0x0 "BSEC_HRCR,BSEC hot reset count register" hexmask.long 0x0 0.--31. 1. "HRC,hot reset counter" line.long 0x4 "BSEC_WRCR,BSEC warm reset count register" hexmask.long 0x4 0.--31. 1. "WRC,Warm reset counter" tree.end tree "BSEC_S" base ad:0x56009000 group.long 0x0++0x5DF line.long 0x0 "BSEC_FVR0,BSEC fuse word 0 value register" hexmask.long 0x0 0.--31. 1. "FV,fuse value" line.long 0x4 "BSEC_FVR1,BSEC fuse word 1 value register" hexmask.long 0x4 0.--31. 1. "FV,fuse value" line.long 0x8 "BSEC_FVR2,BSEC fuse word 2 value register" hexmask.long 0x8 0.--31. 1. "FV,fuse value" line.long 0xC "BSEC_FVR3,BSEC fuse word 3 value register" hexmask.long 0xC 0.--31. 1. "FV,fuse value" line.long 0x10 "BSEC_FVR4,BSEC fuse word 4 value register" hexmask.long 0x10 0.--31. 1. "FV,fuse value" line.long 0x14 "BSEC_FVR5,BSEC fuse word 5 value register" hexmask.long 0x14 0.--31. 1. "FV,fuse value" line.long 0x18 "BSEC_FVR6,BSEC fuse word 6 value register" hexmask.long 0x18 0.--31. 1. "FV,fuse value" line.long 0x1C "BSEC_FVR7,BSEC fuse word 7 value register" hexmask.long 0x1C 0.--31. 1. "FV,fuse value" line.long 0x20 "BSEC_FVR8,BSEC fuse word 8 value register" hexmask.long 0x20 0.--31. 1. "FV,fuse value" line.long 0x24 "BSEC_FVR9,BSEC fuse word 9 value register" hexmask.long 0x24 0.--31. 1. "FV,fuse value" line.long 0x28 "BSEC_FVR10,BSEC fuse word 10 value register" hexmask.long 0x28 0.--31. 1. "FV,fuse value" line.long 0x2C "BSEC_FVR11,BSEC fuse word 11 value register" hexmask.long 0x2C 0.--31. 1. "FV,fuse value" line.long 0x30 "BSEC_FVR12,BSEC fuse word 12 value register" hexmask.long 0x30 0.--31. 1. "FV,fuse value" line.long 0x34 "BSEC_FVR13,BSEC fuse word 13 value register" hexmask.long 0x34 0.--31. 1. "FV,fuse value" line.long 0x38 "BSEC_FVR14,BSEC fuse word 14 value register" hexmask.long 0x38 0.--31. 1. "FV,fuse value" line.long 0x3C "BSEC_FVR15,BSEC fuse word 15 value register" hexmask.long 0x3C 0.--31. 1. "FV,fuse value" line.long 0x40 "BSEC_FVR16,BSEC fuse word 16 value register" hexmask.long 0x40 0.--31. 1. "FV,fuse value" line.long 0x44 "BSEC_FVR17,BSEC fuse word 17 value register" hexmask.long 0x44 0.--31. 1. "FV,fuse value" line.long 0x48 "BSEC_FVR18,BSEC fuse word 18 value register" hexmask.long 0x48 0.--31. 1. "FV,fuse value" line.long 0x4C "BSEC_FVR19,BSEC fuse word 19 value register" hexmask.long 0x4C 0.--31. 1. "FV,fuse value" line.long 0x50 "BSEC_FVR20,BSEC fuse word 20 value register" hexmask.long 0x50 0.--31. 1. "FV,fuse value" line.long 0x54 "BSEC_FVR21,BSEC fuse word 21 value register" hexmask.long 0x54 0.--31. 1. "FV,fuse value" line.long 0x58 "BSEC_FVR22,BSEC fuse word 22 value register" hexmask.long 0x58 0.--31. 1. "FV,fuse value" line.long 0x5C "BSEC_FVR23,BSEC fuse word 23 value register" hexmask.long 0x5C 0.--31. 1. "FV,fuse value" line.long 0x60 "BSEC_FVR24,BSEC fuse word 24 value register" hexmask.long 0x60 0.--31. 1. "FV,fuse value" line.long 0x64 "BSEC_FVR25,BSEC fuse word 25 value register" hexmask.long 0x64 0.--31. 1. "FV,fuse value" line.long 0x68 "BSEC_FVR26,BSEC fuse word 26 value register" hexmask.long 0x68 0.--31. 1. "FV,fuse value" line.long 0x6C "BSEC_FVR27,BSEC fuse word 27 value register" hexmask.long 0x6C 0.--31. 1. "FV,fuse value" line.long 0x70 "BSEC_FVR28,BSEC fuse word 28 value register" hexmask.long 0x70 0.--31. 1. "FV,fuse value" line.long 0x74 "BSEC_FVR29,BSEC fuse word 29 value register" hexmask.long 0x74 0.--31. 1. "FV,fuse value" line.long 0x78 "BSEC_FVR30,BSEC fuse word 30 value register" hexmask.long 0x78 0.--31. 1. "FV,fuse value" line.long 0x7C "BSEC_FVR31,BSEC fuse word 31 value register" hexmask.long 0x7C 0.--31. 1. "FV,fuse value" line.long 0x80 "BSEC_FVR32,BSEC fuse word 32 value register" hexmask.long 0x80 0.--31. 1. "FV,fuse value" line.long 0x84 "BSEC_FVR33,BSEC fuse word 33 value register" hexmask.long 0x84 0.--31. 1. "FV,fuse value" line.long 0x88 "BSEC_FVR34,BSEC fuse word 34 value register" hexmask.long 0x88 0.--31. 1. "FV,fuse value" line.long 0x8C "BSEC_FVR35,BSEC fuse word 35 value register" hexmask.long 0x8C 0.--31. 1. "FV,fuse value" line.long 0x90 "BSEC_FVR36,BSEC fuse word 36 value register" hexmask.long 0x90 0.--31. 1. "FV,fuse value" line.long 0x94 "BSEC_FVR37,BSEC fuse word 37 value register" hexmask.long 0x94 0.--31. 1. "FV,fuse value" line.long 0x98 "BSEC_FVR38,BSEC fuse word 38 value register" hexmask.long 0x98 0.--31. 1. "FV,fuse value" line.long 0x9C "BSEC_FVR39,BSEC fuse word 39 value register" hexmask.long 0x9C 0.--31. 1. "FV,fuse value" line.long 0xA0 "BSEC_FVR40,BSEC fuse word 40 value register" hexmask.long 0xA0 0.--31. 1. "FV,fuse value" line.long 0xA4 "BSEC_FVR41,BSEC fuse word 41 value register" hexmask.long 0xA4 0.--31. 1. "FV,fuse value" line.long 0xA8 "BSEC_FVR42,BSEC fuse word 42 value register" hexmask.long 0xA8 0.--31. 1. "FV,fuse value" line.long 0xAC "BSEC_FVR43,BSEC fuse word 43 value register" hexmask.long 0xAC 0.--31. 1. "FV,fuse value" line.long 0xB0 "BSEC_FVR44,BSEC fuse word 44 value register" hexmask.long 0xB0 0.--31. 1. "FV,fuse value" line.long 0xB4 "BSEC_FVR45,BSEC fuse word 45 value register" hexmask.long 0xB4 0.--31. 1. "FV,fuse value" line.long 0xB8 "BSEC_FVR46,BSEC fuse word 46 value register" hexmask.long 0xB8 0.--31. 1. "FV,fuse value" line.long 0xBC "BSEC_FVR47,BSEC fuse word 47 value register" hexmask.long 0xBC 0.--31. 1. "FV,fuse value" line.long 0xC0 "BSEC_FVR48,BSEC fuse word 48 value register" hexmask.long 0xC0 0.--31. 1. "FV,fuse value" line.long 0xC4 "BSEC_FVR49,BSEC fuse word 49 value register" hexmask.long 0xC4 0.--31. 1. "FV,fuse value" line.long 0xC8 "BSEC_FVR50,BSEC fuse word 50 value register" hexmask.long 0xC8 0.--31. 1. "FV,fuse value" line.long 0xCC "BSEC_FVR51,BSEC fuse word 51 value register" hexmask.long 0xCC 0.--31. 1. "FV,fuse value" line.long 0xD0 "BSEC_FVR52,BSEC fuse word 52 value register" hexmask.long 0xD0 0.--31. 1. "FV,fuse value" line.long 0xD4 "BSEC_FVR53,BSEC fuse word 53 value register" hexmask.long 0xD4 0.--31. 1. "FV,fuse value" line.long 0xD8 "BSEC_FVR54,BSEC fuse word 54 value register" hexmask.long 0xD8 0.--31. 1. "FV,fuse value" line.long 0xDC "BSEC_FVR55,BSEC fuse word 55 value register" hexmask.long 0xDC 0.--31. 1. "FV,fuse value" line.long 0xE0 "BSEC_FVR56,BSEC fuse word 56 value register" hexmask.long 0xE0 0.--31. 1. "FV,fuse value" line.long 0xE4 "BSEC_FVR57,BSEC fuse word 57 value register" hexmask.long 0xE4 0.--31. 1. "FV,fuse value" line.long 0xE8 "BSEC_FVR58,BSEC fuse word 58 value register" hexmask.long 0xE8 0.--31. 1. "FV,fuse value" line.long 0xEC "BSEC_FVR59,BSEC fuse word 59 value register" hexmask.long 0xEC 0.--31. 1. "FV,fuse value" line.long 0xF0 "BSEC_FVR60,BSEC fuse word 60 value register" hexmask.long 0xF0 0.--31. 1. "FV,fuse value" line.long 0xF4 "BSEC_FVR61,BSEC fuse word 61 value register" hexmask.long 0xF4 0.--31. 1. "FV,fuse value" line.long 0xF8 "BSEC_FVR62,BSEC fuse word 62 value register" hexmask.long 0xF8 0.--31. 1. "FV,fuse value" line.long 0xFC "BSEC_FVR63,BSEC fuse word 63 value register" hexmask.long 0xFC 0.--31. 1. "FV,fuse value" line.long 0x100 "BSEC_FVR64,BSEC fuse word 64 value register" hexmask.long 0x100 0.--31. 1. "FV,fuse value" line.long 0x104 "BSEC_FVR65,BSEC fuse word 65 value register" hexmask.long 0x104 0.--31. 1. "FV,fuse value" line.long 0x108 "BSEC_FVR66,BSEC fuse word 66 value register" hexmask.long 0x108 0.--31. 1. "FV,fuse value" line.long 0x10C "BSEC_FVR67,BSEC fuse word 67 value register" hexmask.long 0x10C 0.--31. 1. "FV,fuse value" line.long 0x110 "BSEC_FVR68,BSEC fuse word 68 value register" hexmask.long 0x110 0.--31. 1. "FV,fuse value" line.long 0x114 "BSEC_FVR69,BSEC fuse word 69 value register" hexmask.long 0x114 0.--31. 1. "FV,fuse value" line.long 0x118 "BSEC_FVR70,BSEC fuse word 70 value register" hexmask.long 0x118 0.--31. 1. "FV,fuse value" line.long 0x11C "BSEC_FVR71,BSEC fuse word 71 value register" hexmask.long 0x11C 0.--31. 1. "FV,fuse value" line.long 0x120 "BSEC_FVR72,BSEC fuse word 72 value register" hexmask.long 0x120 0.--31. 1. "FV,fuse value" line.long 0x124 "BSEC_FVR73,BSEC fuse word 73 value register" hexmask.long 0x124 0.--31. 1. "FV,fuse value" line.long 0x128 "BSEC_FVR74,BSEC fuse word 74 value register" hexmask.long 0x128 0.--31. 1. "FV,fuse value" line.long 0x12C "BSEC_FVR75,BSEC fuse word 75 value register" hexmask.long 0x12C 0.--31. 1. "FV,fuse value" line.long 0x130 "BSEC_FVR76,BSEC fuse word 76 value register" hexmask.long 0x130 0.--31. 1. "FV,fuse value" line.long 0x134 "BSEC_FVR77,BSEC fuse word 77 value register" hexmask.long 0x134 0.--31. 1. "FV,fuse value" line.long 0x138 "BSEC_FVR78,BSEC fuse word 78 value register" hexmask.long 0x138 0.--31. 1. "FV,fuse value" line.long 0x13C "BSEC_FVR79,BSEC fuse word 79 value register" hexmask.long 0x13C 0.--31. 1. "FV,fuse value" line.long 0x140 "BSEC_FVR80,BSEC fuse word 80 value register" hexmask.long 0x140 0.--31. 1. "FV,fuse value" line.long 0x144 "BSEC_FVR81,BSEC fuse word 81 value register" hexmask.long 0x144 0.--31. 1. "FV,fuse value" line.long 0x148 "BSEC_FVR82,BSEC fuse word 82 value register" hexmask.long 0x148 0.--31. 1. "FV,fuse value" line.long 0x14C "BSEC_FVR83,BSEC fuse word 83 value register" hexmask.long 0x14C 0.--31. 1. "FV,fuse value" line.long 0x150 "BSEC_FVR84,BSEC fuse word 84 value register" hexmask.long 0x150 0.--31. 1. "FV,fuse value" line.long 0x154 "BSEC_FVR85,BSEC fuse word 85 value register" hexmask.long 0x154 0.--31. 1. "FV,fuse value" line.long 0x158 "BSEC_FVR86,BSEC fuse word 86 value register" hexmask.long 0x158 0.--31. 1. "FV,fuse value" line.long 0x15C "BSEC_FVR87,BSEC fuse word 87 value register" hexmask.long 0x15C 0.--31. 1. "FV,fuse value" line.long 0x160 "BSEC_FVR88,BSEC fuse word 88 value register" hexmask.long 0x160 0.--31. 1. "FV,fuse value" line.long 0x164 "BSEC_FVR89,BSEC fuse word 89 value register" hexmask.long 0x164 0.--31. 1. "FV,fuse value" line.long 0x168 "BSEC_FVR90,BSEC fuse word 90 value register" hexmask.long 0x168 0.--31. 1. "FV,fuse value" line.long 0x16C "BSEC_FVR91,BSEC fuse word 91 value register" hexmask.long 0x16C 0.--31. 1. "FV,fuse value" line.long 0x170 "BSEC_FVR92,BSEC fuse word 92 value register" hexmask.long 0x170 0.--31. 1. "FV,fuse value" line.long 0x174 "BSEC_FVR93,BSEC fuse word 93 value register" hexmask.long 0x174 0.--31. 1. "FV,fuse value" line.long 0x178 "BSEC_FVR94,BSEC fuse word 94 value register" hexmask.long 0x178 0.--31. 1. "FV,fuse value" line.long 0x17C "BSEC_FVR95,BSEC fuse word 95 value register" hexmask.long 0x17C 0.--31. 1. "FV,fuse value" line.long 0x180 "BSEC_FVR96,BSEC fuse word 96 value register" hexmask.long 0x180 0.--31. 1. "FV,fuse value" line.long 0x184 "BSEC_FVR97,BSEC fuse word 97 value register" hexmask.long 0x184 0.--31. 1. "FV,fuse value" line.long 0x188 "BSEC_FVR98,BSEC fuse word 98 value register" hexmask.long 0x188 0.--31. 1. "FV,fuse value" line.long 0x18C "BSEC_FVR99,BSEC fuse word 99 value register" hexmask.long 0x18C 0.--31. 1. "FV,fuse value" line.long 0x190 "BSEC_FVR100,BSEC fuse word 100 value register" hexmask.long 0x190 0.--31. 1. "FV,fuse value" line.long 0x194 "BSEC_FVR101,BSEC fuse word 101 value register" hexmask.long 0x194 0.--31. 1. "FV,fuse value" line.long 0x198 "BSEC_FVR102,BSEC fuse word 102 value register" hexmask.long 0x198 0.--31. 1. "FV,fuse value" line.long 0x19C "BSEC_FVR103,BSEC fuse word 103 value register" hexmask.long 0x19C 0.--31. 1. "FV,fuse value" line.long 0x1A0 "BSEC_FVR104,BSEC fuse word 104 value register" hexmask.long 0x1A0 0.--31. 1. "FV,fuse value" line.long 0x1A4 "BSEC_FVR105,BSEC fuse word 105 value register" hexmask.long 0x1A4 0.--31. 1. "FV,fuse value" line.long 0x1A8 "BSEC_FVR106,BSEC fuse word 106 value register" hexmask.long 0x1A8 0.--31. 1. "FV,fuse value" line.long 0x1AC "BSEC_FVR107,BSEC fuse word 107 value register" hexmask.long 0x1AC 0.--31. 1. "FV,fuse value" line.long 0x1B0 "BSEC_FVR108,BSEC fuse word 108 value register" hexmask.long 0x1B0 0.--31. 1. "FV,fuse value" line.long 0x1B4 "BSEC_FVR109,BSEC fuse word 109 value register" hexmask.long 0x1B4 0.--31. 1. "FV,fuse value" line.long 0x1B8 "BSEC_FVR110,BSEC fuse word 110 value register" hexmask.long 0x1B8 0.--31. 1. "FV,fuse value" line.long 0x1BC "BSEC_FVR111,BSEC fuse word 111 value register" hexmask.long 0x1BC 0.--31. 1. "FV,fuse value" line.long 0x1C0 "BSEC_FVR112,BSEC fuse word 112 value register" hexmask.long 0x1C0 0.--31. 1. "FV,fuse value" line.long 0x1C4 "BSEC_FVR113,BSEC fuse word 113 value register" hexmask.long 0x1C4 0.--31. 1. "FV,fuse value" line.long 0x1C8 "BSEC_FVR114,BSEC fuse word 114 value register" hexmask.long 0x1C8 0.--31. 1. "FV,fuse value" line.long 0x1CC "BSEC_FVR115,BSEC fuse word 115 value register" hexmask.long 0x1CC 0.--31. 1. "FV,fuse value" line.long 0x1D0 "BSEC_FVR116,BSEC fuse word 116 value register" hexmask.long 0x1D0 0.--31. 1. "FV,fuse value" line.long 0x1D4 "BSEC_FVR117,BSEC fuse word 117 value register" hexmask.long 0x1D4 0.--31. 1. "FV,fuse value" line.long 0x1D8 "BSEC_FVR118,BSEC fuse word 118 value register" hexmask.long 0x1D8 0.--31. 1. "FV,fuse value" line.long 0x1DC "BSEC_FVR119,BSEC fuse word 119 value register" hexmask.long 0x1DC 0.--31. 1. "FV,fuse value" line.long 0x1E0 "BSEC_FVR120,BSEC fuse word 120 value register" hexmask.long 0x1E0 0.--31. 1. "FV,fuse value" line.long 0x1E4 "BSEC_FVR121,BSEC fuse word 121 value register" hexmask.long 0x1E4 0.--31. 1. "FV,fuse value" line.long 0x1E8 "BSEC_FVR122,BSEC fuse word 122 value register" hexmask.long 0x1E8 0.--31. 1. "FV,fuse value" line.long 0x1EC "BSEC_FVR123,BSEC fuse word 123 value register" hexmask.long 0x1EC 0.--31. 1. "FV,fuse value" line.long 0x1F0 "BSEC_FVR124,BSEC fuse word 124 value register" hexmask.long 0x1F0 0.--31. 1. "FV,fuse value" line.long 0x1F4 "BSEC_FVR125,BSEC fuse word 125 value register" hexmask.long 0x1F4 0.--31. 1. "FV,fuse value" line.long 0x1F8 "BSEC_FVR126,BSEC fuse word 126 value register" hexmask.long 0x1F8 0.--31. 1. "FV,fuse value" line.long 0x1FC "BSEC_FVR127,BSEC fuse word 127 value register" hexmask.long 0x1FC 0.--31. 1. "FV,fuse value" line.long 0x200 "BSEC_FVR128,BSEC fuse word 128 value register" hexmask.long 0x200 0.--31. 1. "FV,fuse value" line.long 0x204 "BSEC_FVR129,BSEC fuse word 129 value register" hexmask.long 0x204 0.--31. 1. "FV,fuse value" line.long 0x208 "BSEC_FVR130,BSEC fuse word 130 value register" hexmask.long 0x208 0.--31. 1. "FV,fuse value" line.long 0x20C "BSEC_FVR131,BSEC fuse word 131 value register" hexmask.long 0x20C 0.--31. 1. "FV,fuse value" line.long 0x210 "BSEC_FVR132,BSEC fuse word 132 value register" hexmask.long 0x210 0.--31. 1. "FV,fuse value" line.long 0x214 "BSEC_FVR133,BSEC fuse word 133 value register" hexmask.long 0x214 0.--31. 1. "FV,fuse value" line.long 0x218 "BSEC_FVR134,BSEC fuse word 134 value register" hexmask.long 0x218 0.--31. 1. "FV,fuse value" line.long 0x21C "BSEC_FVR135,BSEC fuse word 135 value register" hexmask.long 0x21C 0.--31. 1. "FV,fuse value" line.long 0x220 "BSEC_FVR136,BSEC fuse word 136 value register" hexmask.long 0x220 0.--31. 1. "FV,fuse value" line.long 0x224 "BSEC_FVR137,BSEC fuse word 137 value register" hexmask.long 0x224 0.--31. 1. "FV,fuse value" line.long 0x228 "BSEC_FVR138,BSEC fuse word 138 value register" hexmask.long 0x228 0.--31. 1. "FV,fuse value" line.long 0x22C "BSEC_FVR139,BSEC fuse word 139 value register" hexmask.long 0x22C 0.--31. 1. "FV,fuse value" line.long 0x230 "BSEC_FVR140,BSEC fuse word 140 value register" hexmask.long 0x230 0.--31. 1. "FV,fuse value" line.long 0x234 "BSEC_FVR141,BSEC fuse word 141 value register" hexmask.long 0x234 0.--31. 1. "FV,fuse value" line.long 0x238 "BSEC_FVR142,BSEC fuse word 142 value register" hexmask.long 0x238 0.--31. 1. "FV,fuse value" line.long 0x23C "BSEC_FVR143,BSEC fuse word 143 value register" hexmask.long 0x23C 0.--31. 1. "FV,fuse value" line.long 0x240 "BSEC_FVR144,BSEC fuse word 144 value register" hexmask.long 0x240 0.--31. 1. "FV,fuse value" line.long 0x244 "BSEC_FVR145,BSEC fuse word 145 value register" hexmask.long 0x244 0.--31. 1. "FV,fuse value" line.long 0x248 "BSEC_FVR146,BSEC fuse word 146 value register" hexmask.long 0x248 0.--31. 1. "FV,fuse value" line.long 0x24C "BSEC_FVR147,BSEC fuse word 147 value register" hexmask.long 0x24C 0.--31. 1. "FV,fuse value" line.long 0x250 "BSEC_FVR148,BSEC fuse word 148 value register" hexmask.long 0x250 0.--31. 1. "FV,fuse value" line.long 0x254 "BSEC_FVR149,BSEC fuse word 149 value register" hexmask.long 0x254 0.--31. 1. "FV,fuse value" line.long 0x258 "BSEC_FVR150,BSEC fuse word 150 value register" hexmask.long 0x258 0.--31. 1. "FV,fuse value" line.long 0x25C "BSEC_FVR151,BSEC fuse word 151 value register" hexmask.long 0x25C 0.--31. 1. "FV,fuse value" line.long 0x260 "BSEC_FVR152,BSEC fuse word 152 value register" hexmask.long 0x260 0.--31. 1. "FV,fuse value" line.long 0x264 "BSEC_FVR153,BSEC fuse word 153 value register" hexmask.long 0x264 0.--31. 1. "FV,fuse value" line.long 0x268 "BSEC_FVR154,BSEC fuse word 154 value register" hexmask.long 0x268 0.--31. 1. "FV,fuse value" line.long 0x26C "BSEC_FVR155,BSEC fuse word 155 value register" hexmask.long 0x26C 0.--31. 1. "FV,fuse value" line.long 0x270 "BSEC_FVR156,BSEC fuse word 156 value register" hexmask.long 0x270 0.--31. 1. "FV,fuse value" line.long 0x274 "BSEC_FVR157,BSEC fuse word 157 value register" hexmask.long 0x274 0.--31. 1. "FV,fuse value" line.long 0x278 "BSEC_FVR158,BSEC fuse word 158 value register" hexmask.long 0x278 0.--31. 1. "FV,fuse value" line.long 0x27C "BSEC_FVR159,BSEC fuse word 159 value register" hexmask.long 0x27C 0.--31. 1. "FV,fuse value" line.long 0x280 "BSEC_FVR160,BSEC fuse word 160 value register" hexmask.long 0x280 0.--31. 1. "FV,fuse value" line.long 0x284 "BSEC_FVR161,BSEC fuse word 161 value register" hexmask.long 0x284 0.--31. 1. "FV,fuse value" line.long 0x288 "BSEC_FVR162,BSEC fuse word 162 value register" hexmask.long 0x288 0.--31. 1. "FV,fuse value" line.long 0x28C "BSEC_FVR163,BSEC fuse word 163 value register" hexmask.long 0x28C 0.--31. 1. "FV,fuse value" line.long 0x290 "BSEC_FVR164,BSEC fuse word 164 value register" hexmask.long 0x290 0.--31. 1. "FV,fuse value" line.long 0x294 "BSEC_FVR165,BSEC fuse word 165 value register" hexmask.long 0x294 0.--31. 1. "FV,fuse value" line.long 0x298 "BSEC_FVR166,BSEC fuse word 166 value register" hexmask.long 0x298 0.--31. 1. "FV,fuse value" line.long 0x29C "BSEC_FVR167,BSEC fuse word 167 value register" hexmask.long 0x29C 0.--31. 1. "FV,fuse value" line.long 0x2A0 "BSEC_FVR168,BSEC fuse word 168 value register" hexmask.long 0x2A0 0.--31. 1. "FV,fuse value" line.long 0x2A4 "BSEC_FVR169,BSEC fuse word 169 value register" hexmask.long 0x2A4 0.--31. 1. "FV,fuse value" line.long 0x2A8 "BSEC_FVR170,BSEC fuse word 170 value register" hexmask.long 0x2A8 0.--31. 1. "FV,fuse value" line.long 0x2AC "BSEC_FVR171,BSEC fuse word 171 value register" hexmask.long 0x2AC 0.--31. 1. "FV,fuse value" line.long 0x2B0 "BSEC_FVR172,BSEC fuse word 172 value register" hexmask.long 0x2B0 0.--31. 1. "FV,fuse value" line.long 0x2B4 "BSEC_FVR173,BSEC fuse word 173 value register" hexmask.long 0x2B4 0.--31. 1. "FV,fuse value" line.long 0x2B8 "BSEC_FVR174,BSEC fuse word 174 value register" hexmask.long 0x2B8 0.--31. 1. "FV,fuse value" line.long 0x2BC "BSEC_FVR175,BSEC fuse word 175 value register" hexmask.long 0x2BC 0.--31. 1. "FV,fuse value" line.long 0x2C0 "BSEC_FVR176,BSEC fuse word 176 value register" hexmask.long 0x2C0 0.--31. 1. "FV,fuse value" line.long 0x2C4 "BSEC_FVR177,BSEC fuse word 177 value register" hexmask.long 0x2C4 0.--31. 1. "FV,fuse value" line.long 0x2C8 "BSEC_FVR178,BSEC fuse word 178 value register" hexmask.long 0x2C8 0.--31. 1. "FV,fuse value" line.long 0x2CC "BSEC_FVR179,BSEC fuse word 179 value register" hexmask.long 0x2CC 0.--31. 1. "FV,fuse value" line.long 0x2D0 "BSEC_FVR180,BSEC fuse word 180 value register" hexmask.long 0x2D0 0.--31. 1. "FV,fuse value" line.long 0x2D4 "BSEC_FVR181,BSEC fuse word 181 value register" hexmask.long 0x2D4 0.--31. 1. "FV,fuse value" line.long 0x2D8 "BSEC_FVR182,BSEC fuse word 182 value register" hexmask.long 0x2D8 0.--31. 1. "FV,fuse value" line.long 0x2DC "BSEC_FVR183,BSEC fuse word 183 value register" hexmask.long 0x2DC 0.--31. 1. "FV,fuse value" line.long 0x2E0 "BSEC_FVR184,BSEC fuse word 184 value register" hexmask.long 0x2E0 0.--31. 1. "FV,fuse value" line.long 0x2E4 "BSEC_FVR185,BSEC fuse word 185 value register" hexmask.long 0x2E4 0.--31. 1. "FV,fuse value" line.long 0x2E8 "BSEC_FVR186,BSEC fuse word 186 value register" hexmask.long 0x2E8 0.--31. 1. "FV,fuse value" line.long 0x2EC "BSEC_FVR187,BSEC fuse word 187 value register" hexmask.long 0x2EC 0.--31. 1. "FV,fuse value" line.long 0x2F0 "BSEC_FVR188,BSEC fuse word 188 value register" hexmask.long 0x2F0 0.--31. 1. "FV,fuse value" line.long 0x2F4 "BSEC_FVR189,BSEC fuse word 189 value register" hexmask.long 0x2F4 0.--31. 1. "FV,fuse value" line.long 0x2F8 "BSEC_FVR190,BSEC fuse word 190 value register" hexmask.long 0x2F8 0.--31. 1. "FV,fuse value" line.long 0x2FC "BSEC_FVR191,BSEC fuse word 191 value register" hexmask.long 0x2FC 0.--31. 1. "FV,fuse value" line.long 0x300 "BSEC_FVR192,BSEC fuse word 192 value register" hexmask.long 0x300 0.--31. 1. "FV,fuse value" line.long 0x304 "BSEC_FVR193,BSEC fuse word 193 value register" hexmask.long 0x304 0.--31. 1. "FV,fuse value" line.long 0x308 "BSEC_FVR194,BSEC fuse word 194 value register" hexmask.long 0x308 0.--31. 1. "FV,fuse value" line.long 0x30C "BSEC_FVR195,BSEC fuse word 195 value register" hexmask.long 0x30C 0.--31. 1. "FV,fuse value" line.long 0x310 "BSEC_FVR196,BSEC fuse word 196 value register" hexmask.long 0x310 0.--31. 1. "FV,fuse value" line.long 0x314 "BSEC_FVR197,BSEC fuse word 197 value register" hexmask.long 0x314 0.--31. 1. "FV,fuse value" line.long 0x318 "BSEC_FVR198,BSEC fuse word 198 value register" hexmask.long 0x318 0.--31. 1. "FV,fuse value" line.long 0x31C "BSEC_FVR199,BSEC fuse word 199 value register" hexmask.long 0x31C 0.--31. 1. "FV,fuse value" line.long 0x320 "BSEC_FVR200,BSEC fuse word 200 value register" hexmask.long 0x320 0.--31. 1. "FV,fuse value" line.long 0x324 "BSEC_FVR201,BSEC fuse word 201 value register" hexmask.long 0x324 0.--31. 1. "FV,fuse value" line.long 0x328 "BSEC_FVR202,BSEC fuse word 202 value register" hexmask.long 0x328 0.--31. 1. "FV,fuse value" line.long 0x32C "BSEC_FVR203,BSEC fuse word 203 value register" hexmask.long 0x32C 0.--31. 1. "FV,fuse value" line.long 0x330 "BSEC_FVR204,BSEC fuse word 204 value register" hexmask.long 0x330 0.--31. 1. "FV,fuse value" line.long 0x334 "BSEC_FVR205,BSEC fuse word 205 value register" hexmask.long 0x334 0.--31. 1. "FV,fuse value" line.long 0x338 "BSEC_FVR206,BSEC fuse word 206 value register" hexmask.long 0x338 0.--31. 1. "FV,fuse value" line.long 0x33C "BSEC_FVR207,BSEC fuse word 207 value register" hexmask.long 0x33C 0.--31. 1. "FV,fuse value" line.long 0x340 "BSEC_FVR208,BSEC fuse word 208 value register" hexmask.long 0x340 0.--31. 1. "FV,fuse value" line.long 0x344 "BSEC_FVR209,BSEC fuse word 209 value register" hexmask.long 0x344 0.--31. 1. "FV,fuse value" line.long 0x348 "BSEC_FVR210,BSEC fuse word 210 value register" hexmask.long 0x348 0.--31. 1. "FV,fuse value" line.long 0x34C "BSEC_FVR211,BSEC fuse word 211 value register" hexmask.long 0x34C 0.--31. 1. "FV,fuse value" line.long 0x350 "BSEC_FVR212,BSEC fuse word 212 value register" hexmask.long 0x350 0.--31. 1. "FV,fuse value" line.long 0x354 "BSEC_FVR213,BSEC fuse word 213 value register" hexmask.long 0x354 0.--31. 1. "FV,fuse value" line.long 0x358 "BSEC_FVR214,BSEC fuse word 214 value register" hexmask.long 0x358 0.--31. 1. "FV,fuse value" line.long 0x35C "BSEC_FVR215,BSEC fuse word 215 value register" hexmask.long 0x35C 0.--31. 1. "FV,fuse value" line.long 0x360 "BSEC_FVR216,BSEC fuse word 216 value register" hexmask.long 0x360 0.--31. 1. "FV,fuse value" line.long 0x364 "BSEC_FVR217,BSEC fuse word 217 value register" hexmask.long 0x364 0.--31. 1. "FV,fuse value" line.long 0x368 "BSEC_FVR218,BSEC fuse word 218 value register" hexmask.long 0x368 0.--31. 1. "FV,fuse value" line.long 0x36C "BSEC_FVR219,BSEC fuse word 219 value register" hexmask.long 0x36C 0.--31. 1. "FV,fuse value" line.long 0x370 "BSEC_FVR220,BSEC fuse word 220 value register" hexmask.long 0x370 0.--31. 1. "FV,fuse value" line.long 0x374 "BSEC_FVR221,BSEC fuse word 221 value register" hexmask.long 0x374 0.--31. 1. "FV,fuse value" line.long 0x378 "BSEC_FVR222,BSEC fuse word 222 value register" hexmask.long 0x378 0.--31. 1. "FV,fuse value" line.long 0x37C "BSEC_FVR223,BSEC fuse word 223 value register" hexmask.long 0x37C 0.--31. 1. "FV,fuse value" line.long 0x380 "BSEC_FVR224,BSEC fuse word 224 value register" hexmask.long 0x380 0.--31. 1. "FV,fuse value" line.long 0x384 "BSEC_FVR225,BSEC fuse word 225 value register" hexmask.long 0x384 0.--31. 1. "FV,fuse value" line.long 0x388 "BSEC_FVR226,BSEC fuse word 226 value register" hexmask.long 0x388 0.--31. 1. "FV,fuse value" line.long 0x38C "BSEC_FVR227,BSEC fuse word 227 value register" hexmask.long 0x38C 0.--31. 1. "FV,fuse value" line.long 0x390 "BSEC_FVR228,BSEC fuse word 228 value register" hexmask.long 0x390 0.--31. 1. "FV,fuse value" line.long 0x394 "BSEC_FVR229,BSEC fuse word 229 value register" hexmask.long 0x394 0.--31. 1. "FV,fuse value" line.long 0x398 "BSEC_FVR230,BSEC fuse word 230 value register" hexmask.long 0x398 0.--31. 1. "FV,fuse value" line.long 0x39C "BSEC_FVR231,BSEC fuse word 231 value register" hexmask.long 0x39C 0.--31. 1. "FV,fuse value" line.long 0x3A0 "BSEC_FVR232,BSEC fuse word 232 value register" hexmask.long 0x3A0 0.--31. 1. "FV,fuse value" line.long 0x3A4 "BSEC_FVR233,BSEC fuse word 233 value register" hexmask.long 0x3A4 0.--31. 1. "FV,fuse value" line.long 0x3A8 "BSEC_FVR234,BSEC fuse word 234 value register" hexmask.long 0x3A8 0.--31. 1. "FV,fuse value" line.long 0x3AC "BSEC_FVR235,BSEC fuse word 235 value register" hexmask.long 0x3AC 0.--31. 1. "FV,fuse value" line.long 0x3B0 "BSEC_FVR236,BSEC fuse word 236 value register" hexmask.long 0x3B0 0.--31. 1. "FV,fuse value" line.long 0x3B4 "BSEC_FVR237,BSEC fuse word 237 value register" hexmask.long 0x3B4 0.--31. 1. "FV,fuse value" line.long 0x3B8 "BSEC_FVR238,BSEC fuse word 238 value register" hexmask.long 0x3B8 0.--31. 1. "FV,fuse value" line.long 0x3BC "BSEC_FVR239,BSEC fuse word 239 value register" hexmask.long 0x3BC 0.--31. 1. "FV,fuse value" line.long 0x3C0 "BSEC_FVR240,BSEC fuse word 240 value register" hexmask.long 0x3C0 0.--31. 1. "FV,fuse value" line.long 0x3C4 "BSEC_FVR241,BSEC fuse word 241 value register" hexmask.long 0x3C4 0.--31. 1. "FV,fuse value" line.long 0x3C8 "BSEC_FVR242,BSEC fuse word 242 value register" hexmask.long 0x3C8 0.--31. 1. "FV,fuse value" line.long 0x3CC "BSEC_FVR243,BSEC fuse word 243 value register" hexmask.long 0x3CC 0.--31. 1. "FV,fuse value" line.long 0x3D0 "BSEC_FVR244,BSEC fuse word 244 value register" hexmask.long 0x3D0 0.--31. 1. "FV,fuse value" line.long 0x3D4 "BSEC_FVR245,BSEC fuse word 245 value register" hexmask.long 0x3D4 0.--31. 1. "FV,fuse value" line.long 0x3D8 "BSEC_FVR246,BSEC fuse word 246 value register" hexmask.long 0x3D8 0.--31. 1. "FV,fuse value" line.long 0x3DC "BSEC_FVR247,BSEC fuse word 247 value register" hexmask.long 0x3DC 0.--31. 1. "FV,fuse value" line.long 0x3E0 "BSEC_FVR248,BSEC fuse word 248 value register" hexmask.long 0x3E0 0.--31. 1. "FV,fuse value" line.long 0x3E4 "BSEC_FVR249,BSEC fuse word 249 value register" hexmask.long 0x3E4 0.--31. 1. "FV,fuse value" line.long 0x3E8 "BSEC_FVR250,BSEC fuse word 250 value register" hexmask.long 0x3E8 0.--31. 1. "FV,fuse value" line.long 0x3EC "BSEC_FVR251,BSEC fuse word 251 value register" hexmask.long 0x3EC 0.--31. 1. "FV,fuse value" line.long 0x3F0 "BSEC_FVR252,BSEC fuse word 252 value register" hexmask.long 0x3F0 0.--31. 1. "FV,fuse value" line.long 0x3F4 "BSEC_FVR253,BSEC fuse word 253 value register" hexmask.long 0x3F4 0.--31. 1. "FV,fuse value" line.long 0x3F8 "BSEC_FVR254,BSEC fuse word 254 value register" hexmask.long 0x3F8 0.--31. 1. "FV,fuse value" line.long 0x3FC "BSEC_FVR255,BSEC fuse word 255 value register" hexmask.long 0x3FC 0.--31. 1. "FV,fuse value" line.long 0x400 "BSEC_FVR256,BSEC fuse word 256 value register" hexmask.long 0x400 0.--31. 1. "FV,fuse value" line.long 0x404 "BSEC_FVR257,BSEC fuse word 257 value register" hexmask.long 0x404 0.--31. 1. "FV,fuse value" line.long 0x408 "BSEC_FVR258,BSEC fuse word 258 value register" hexmask.long 0x408 0.--31. 1. "FV,fuse value" line.long 0x40C "BSEC_FVR259,BSEC fuse word 259 value register" hexmask.long 0x40C 0.--31. 1. "FV,fuse value" line.long 0x410 "BSEC_FVR260,BSEC fuse word 260 value register" hexmask.long 0x410 0.--31. 1. "FV,fuse value" line.long 0x414 "BSEC_FVR261,BSEC fuse word 261 value register" hexmask.long 0x414 0.--31. 1. "FV,fuse value" line.long 0x418 "BSEC_FVR262,BSEC fuse word 262 value register" hexmask.long 0x418 0.--31. 1. "FV,fuse value" line.long 0x41C "BSEC_FVR263,BSEC fuse word 263 value register" hexmask.long 0x41C 0.--31. 1. "FV,fuse value" line.long 0x420 "BSEC_FVR264,BSEC fuse word 264 value register" hexmask.long 0x420 0.--31. 1. "FV,fuse value" line.long 0x424 "BSEC_FVR265,BSEC fuse word 265 value register" hexmask.long 0x424 0.--31. 1. "FV,fuse value" line.long 0x428 "BSEC_FVR266,BSEC fuse word 266 value register" hexmask.long 0x428 0.--31. 1. "FV,fuse value" line.long 0x42C "BSEC_FVR267,BSEC fuse word 267 value register" hexmask.long 0x42C 0.--31. 1. "FV,fuse value" line.long 0x430 "BSEC_FVR268,BSEC fuse word 268 value register" hexmask.long 0x430 0.--31. 1. "FV,fuse value" line.long 0x434 "BSEC_FVR269,BSEC fuse word 269 value register" hexmask.long 0x434 0.--31. 1. "FV,fuse value" line.long 0x438 "BSEC_FVR270,BSEC fuse word 270 value register" hexmask.long 0x438 0.--31. 1. "FV,fuse value" line.long 0x43C "BSEC_FVR271,BSEC fuse word 271 value register" hexmask.long 0x43C 0.--31. 1. "FV,fuse value" line.long 0x440 "BSEC_FVR272,BSEC fuse word 272 value register" hexmask.long 0x440 0.--31. 1. "FV,fuse value" line.long 0x444 "BSEC_FVR273,BSEC fuse word 273 value register" hexmask.long 0x444 0.--31. 1. "FV,fuse value" line.long 0x448 "BSEC_FVR274,BSEC fuse word 274 value register" hexmask.long 0x448 0.--31. 1. "FV,fuse value" line.long 0x44C "BSEC_FVR275,BSEC fuse word 275 value register" hexmask.long 0x44C 0.--31. 1. "FV,fuse value" line.long 0x450 "BSEC_FVR276,BSEC fuse word 276 value register" hexmask.long 0x450 0.--31. 1. "FV,fuse value" line.long 0x454 "BSEC_FVR277,BSEC fuse word 277 value register" hexmask.long 0x454 0.--31. 1. "FV,fuse value" line.long 0x458 "BSEC_FVR278,BSEC fuse word 278 value register" hexmask.long 0x458 0.--31. 1. "FV,fuse value" line.long 0x45C "BSEC_FVR279,BSEC fuse word 279 value register" hexmask.long 0x45C 0.--31. 1. "FV,fuse value" line.long 0x460 "BSEC_FVR280,BSEC fuse word 280 value register" hexmask.long 0x460 0.--31. 1. "FV,fuse value" line.long 0x464 "BSEC_FVR281,BSEC fuse word 281 value register" hexmask.long 0x464 0.--31. 1. "FV,fuse value" line.long 0x468 "BSEC_FVR282,BSEC fuse word 282 value register" hexmask.long 0x468 0.--31. 1. "FV,fuse value" line.long 0x46C "BSEC_FVR283,BSEC fuse word 283 value register" hexmask.long 0x46C 0.--31. 1. "FV,fuse value" line.long 0x470 "BSEC_FVR284,BSEC fuse word 284 value register" hexmask.long 0x470 0.--31. 1. "FV,fuse value" line.long 0x474 "BSEC_FVR285,BSEC fuse word 285 value register" hexmask.long 0x474 0.--31. 1. "FV,fuse value" line.long 0x478 "BSEC_FVR286,BSEC fuse word 286 value register" hexmask.long 0x478 0.--31. 1. "FV,fuse value" line.long 0x47C "BSEC_FVR287,BSEC fuse word 287 value register" hexmask.long 0x47C 0.--31. 1. "FV,fuse value" line.long 0x480 "BSEC_FVR288,BSEC fuse word 288 value register" hexmask.long 0x480 0.--31. 1. "FV,fuse value" line.long 0x484 "BSEC_FVR289,BSEC fuse word 289 value register" hexmask.long 0x484 0.--31. 1. "FV,fuse value" line.long 0x488 "BSEC_FVR290,BSEC fuse word 290 value register" hexmask.long 0x488 0.--31. 1. "FV,fuse value" line.long 0x48C "BSEC_FVR291,BSEC fuse word 291 value register" hexmask.long 0x48C 0.--31. 1. "FV,fuse value" line.long 0x490 "BSEC_FVR292,BSEC fuse word 292 value register" hexmask.long 0x490 0.--31. 1. "FV,fuse value" line.long 0x494 "BSEC_FVR293,BSEC fuse word 293 value register" hexmask.long 0x494 0.--31. 1. "FV,fuse value" line.long 0x498 "BSEC_FVR294,BSEC fuse word 294 value register" hexmask.long 0x498 0.--31. 1. "FV,fuse value" line.long 0x49C "BSEC_FVR295,BSEC fuse word 295 value register" hexmask.long 0x49C 0.--31. 1. "FV,fuse value" line.long 0x4A0 "BSEC_FVR296,BSEC fuse word 296 value register" hexmask.long 0x4A0 0.--31. 1. "FV,fuse value" line.long 0x4A4 "BSEC_FVR297,BSEC fuse word 297 value register" hexmask.long 0x4A4 0.--31. 1. "FV,fuse value" line.long 0x4A8 "BSEC_FVR298,BSEC fuse word 298 value register" hexmask.long 0x4A8 0.--31. 1. "FV,fuse value" line.long 0x4AC "BSEC_FVR299,BSEC fuse word 299 value register" hexmask.long 0x4AC 0.--31. 1. "FV,fuse value" line.long 0x4B0 "BSEC_FVR300,BSEC fuse word 300 value register" hexmask.long 0x4B0 0.--31. 1. "FV,fuse value" line.long 0x4B4 "BSEC_FVR301,BSEC fuse word 301 value register" hexmask.long 0x4B4 0.--31. 1. "FV,fuse value" line.long 0x4B8 "BSEC_FVR302,BSEC fuse word 302 value register" hexmask.long 0x4B8 0.--31. 1. "FV,fuse value" line.long 0x4BC "BSEC_FVR303,BSEC fuse word 303 value register" hexmask.long 0x4BC 0.--31. 1. "FV,fuse value" line.long 0x4C0 "BSEC_FVR304,BSEC fuse word 304 value register" hexmask.long 0x4C0 0.--31. 1. "FV,fuse value" line.long 0x4C4 "BSEC_FVR305,BSEC fuse word 305 value register" hexmask.long 0x4C4 0.--31. 1. "FV,fuse value" line.long 0x4C8 "BSEC_FVR306,BSEC fuse word 306 value register" hexmask.long 0x4C8 0.--31. 1. "FV,fuse value" line.long 0x4CC "BSEC_FVR307,BSEC fuse word 307 value register" hexmask.long 0x4CC 0.--31. 1. "FV,fuse value" line.long 0x4D0 "BSEC_FVR308,BSEC fuse word 308 value register" hexmask.long 0x4D0 0.--31. 1. "FV,fuse value" line.long 0x4D4 "BSEC_FVR309,BSEC fuse word 309 value register" hexmask.long 0x4D4 0.--31. 1. "FV,fuse value" line.long 0x4D8 "BSEC_FVR310,BSEC fuse word 310 value register" hexmask.long 0x4D8 0.--31. 1. "FV,fuse value" line.long 0x4DC "BSEC_FVR311,BSEC fuse word 311 value register" hexmask.long 0x4DC 0.--31. 1. "FV,fuse value" line.long 0x4E0 "BSEC_FVR312,BSEC fuse word 312 value register" hexmask.long 0x4E0 0.--31. 1. "FV,fuse value" line.long 0x4E4 "BSEC_FVR313,BSEC fuse word 313 value register" hexmask.long 0x4E4 0.--31. 1. "FV,fuse value" line.long 0x4E8 "BSEC_FVR314,BSEC fuse word 314 value register" hexmask.long 0x4E8 0.--31. 1. "FV,fuse value" line.long 0x4EC "BSEC_FVR315,BSEC fuse word 315 value register" hexmask.long 0x4EC 0.--31. 1. "FV,fuse value" line.long 0x4F0 "BSEC_FVR316,BSEC fuse word 316 value register" hexmask.long 0x4F0 0.--31. 1. "FV,fuse value" line.long 0x4F4 "BSEC_FVR317,BSEC fuse word 317 value register" hexmask.long 0x4F4 0.--31. 1. "FV,fuse value" line.long 0x4F8 "BSEC_FVR318,BSEC fuse word 318 value register" hexmask.long 0x4F8 0.--31. 1. "FV,fuse value" line.long 0x4FC "BSEC_FVR319,BSEC fuse word 319 value register" hexmask.long 0x4FC 0.--31. 1. "FV,fuse value" line.long 0x500 "BSEC_FVR320,BSEC fuse word 320 value register" hexmask.long 0x500 0.--31. 1. "FV,fuse value" line.long 0x504 "BSEC_FVR321,BSEC fuse word 321 value register" hexmask.long 0x504 0.--31. 1. "FV,fuse value" line.long 0x508 "BSEC_FVR322,BSEC fuse word 322 value register" hexmask.long 0x508 0.--31. 1. "FV,fuse value" line.long 0x50C "BSEC_FVR323,BSEC fuse word 323 value register" hexmask.long 0x50C 0.--31. 1. "FV,fuse value" line.long 0x510 "BSEC_FVR324,BSEC fuse word 324 value register" hexmask.long 0x510 0.--31. 1. "FV,fuse value" line.long 0x514 "BSEC_FVR325,BSEC fuse word 325 value register" hexmask.long 0x514 0.--31. 1. "FV,fuse value" line.long 0x518 "BSEC_FVR326,BSEC fuse word 326 value register" hexmask.long 0x518 0.--31. 1. "FV,fuse value" line.long 0x51C "BSEC_FVR327,BSEC fuse word 327 value register" hexmask.long 0x51C 0.--31. 1. "FV,fuse value" line.long 0x520 "BSEC_FVR328,BSEC fuse word 328 value register" hexmask.long 0x520 0.--31. 1. "FV,fuse value" line.long 0x524 "BSEC_FVR329,BSEC fuse word 329 value register" hexmask.long 0x524 0.--31. 1. "FV,fuse value" line.long 0x528 "BSEC_FVR330,BSEC fuse word 330 value register" hexmask.long 0x528 0.--31. 1. "FV,fuse value" line.long 0x52C "BSEC_FVR331,BSEC fuse word 331 value register" hexmask.long 0x52C 0.--31. 1. "FV,fuse value" line.long 0x530 "BSEC_FVR332,BSEC fuse word 332 value register" hexmask.long 0x530 0.--31. 1. "FV,fuse value" line.long 0x534 "BSEC_FVR333,BSEC fuse word 333 value register" hexmask.long 0x534 0.--31. 1. "FV,fuse value" line.long 0x538 "BSEC_FVR334,BSEC fuse word 334 value register" hexmask.long 0x538 0.--31. 1. "FV,fuse value" line.long 0x53C "BSEC_FVR335,BSEC fuse word 335 value register" hexmask.long 0x53C 0.--31. 1. "FV,fuse value" line.long 0x540 "BSEC_FVR336,BSEC fuse word 336 value register" hexmask.long 0x540 0.--31. 1. "FV,fuse value" line.long 0x544 "BSEC_FVR337,BSEC fuse word 337 value register" hexmask.long 0x544 0.--31. 1. "FV,fuse value" line.long 0x548 "BSEC_FVR338,BSEC fuse word 338 value register" hexmask.long 0x548 0.--31. 1. "FV,fuse value" line.long 0x54C "BSEC_FVR339,BSEC fuse word 339 value register" hexmask.long 0x54C 0.--31. 1. "FV,fuse value" line.long 0x550 "BSEC_FVR340,BSEC fuse word 340 value register" hexmask.long 0x550 0.--31. 1. "FV,fuse value" line.long 0x554 "BSEC_FVR341,BSEC fuse word 341 value register" hexmask.long 0x554 0.--31. 1. "FV,fuse value" line.long 0x558 "BSEC_FVR342,BSEC fuse word 342 value register" hexmask.long 0x558 0.--31. 1. "FV,fuse value" line.long 0x55C "BSEC_FVR343,BSEC fuse word 343 value register" hexmask.long 0x55C 0.--31. 1. "FV,fuse value" line.long 0x560 "BSEC_FVR344,BSEC fuse word 344 value register" hexmask.long 0x560 0.--31. 1. "FV,fuse value" line.long 0x564 "BSEC_FVR345,BSEC fuse word 345 value register" hexmask.long 0x564 0.--31. 1. "FV,fuse value" line.long 0x568 "BSEC_FVR346,BSEC fuse word 346 value register" hexmask.long 0x568 0.--31. 1. "FV,fuse value" line.long 0x56C "BSEC_FVR347,BSEC fuse word 347 value register" hexmask.long 0x56C 0.--31. 1. "FV,fuse value" line.long 0x570 "BSEC_FVR348,BSEC fuse word 348 value register" hexmask.long 0x570 0.--31. 1. "FV,fuse value" line.long 0x574 "BSEC_FVR349,BSEC fuse word 349 value register" hexmask.long 0x574 0.--31. 1. "FV,fuse value" line.long 0x578 "BSEC_FVR350,BSEC fuse word 350 value register" hexmask.long 0x578 0.--31. 1. "FV,fuse value" line.long 0x57C "BSEC_FVR351,BSEC fuse word 351 value register" hexmask.long 0x57C 0.--31. 1. "FV,fuse value" line.long 0x580 "BSEC_FVR352,BSEC fuse word 352 value register" hexmask.long 0x580 0.--31. 1. "FV,fuse value" line.long 0x584 "BSEC_FVR353,BSEC fuse word 353 value register" hexmask.long 0x584 0.--31. 1. "FV,fuse value" line.long 0x588 "BSEC_FVR354,BSEC fuse word 354 value register" hexmask.long 0x588 0.--31. 1. "FV,fuse value" line.long 0x58C "BSEC_FVR355,BSEC fuse word 355 value register" hexmask.long 0x58C 0.--31. 1. "FV,fuse value" line.long 0x590 "BSEC_FVR356,BSEC fuse word 356 value register" hexmask.long 0x590 0.--31. 1. "FV,fuse value" line.long 0x594 "BSEC_FVR357,BSEC fuse word 357 value register" hexmask.long 0x594 0.--31. 1. "FV,fuse value" line.long 0x598 "BSEC_FVR358,BSEC fuse word 358 value register" hexmask.long 0x598 0.--31. 1. "FV,fuse value" line.long 0x59C "BSEC_FVR359,BSEC fuse word 359 value register" hexmask.long 0x59C 0.--31. 1. "FV,fuse value" line.long 0x5A0 "BSEC_FVR360,BSEC fuse word 360 value register" hexmask.long 0x5A0 0.--31. 1. "FV,fuse value" line.long 0x5A4 "BSEC_FVR361,BSEC fuse word 361 value register" hexmask.long 0x5A4 0.--31. 1. "FV,fuse value" line.long 0x5A8 "BSEC_FVR362,BSEC fuse word 362 value register" hexmask.long 0x5A8 0.--31. 1. "FV,fuse value" line.long 0x5AC "BSEC_FVR363,BSEC fuse word 363 value register" hexmask.long 0x5AC 0.--31. 1. "FV,fuse value" line.long 0x5B0 "BSEC_FVR364,BSEC fuse word 364 value register" hexmask.long 0x5B0 0.--31. 1. "FV,fuse value" line.long 0x5B4 "BSEC_FVR365,BSEC fuse word 365 value register" hexmask.long 0x5B4 0.--31. 1. "FV,fuse value" line.long 0x5B8 "BSEC_FVR366,BSEC fuse word 366 value register" hexmask.long 0x5B8 0.--31. 1. "FV,fuse value" line.long 0x5BC "BSEC_FVR367,BSEC fuse word 367 value register" hexmask.long 0x5BC 0.--31. 1. "FV,fuse value" line.long 0x5C0 "BSEC_FVR368,BSEC fuse word 368 value register" hexmask.long 0x5C0 0.--31. 1. "FV,fuse value" line.long 0x5C4 "BSEC_FVR369,BSEC fuse word 369 value register" hexmask.long 0x5C4 0.--31. 1. "FV,fuse value" line.long 0x5C8 "BSEC_FVR370,BSEC fuse word 370 value register" hexmask.long 0x5C8 0.--31. 1. "FV,fuse value" line.long 0x5CC "BSEC_FVR371,BSEC fuse word 371 value register" hexmask.long 0x5CC 0.--31. 1. "FV,fuse value" line.long 0x5D0 "BSEC_FVR372,BSEC fuse word 372 value register" hexmask.long 0x5D0 0.--31. 1. "FV,fuse value" line.long 0x5D4 "BSEC_FVR373,BSEC fuse word 373 value register" hexmask.long 0x5D4 0.--31. 1. "FV,fuse value" line.long 0x5D8 "BSEC_FVR374,BSEC fuse word 374 value register" hexmask.long 0x5D8 0.--31. 1. "FV,fuse value" line.long 0x5DC "BSEC_FVR375,BSEC fuse word 375 value register" hexmask.long 0x5DC 0.--31. 1. "FV,fuse value" group.long 0x800++0x2F line.long 0x0 "BSEC_SPLOCK0,BSEC sticky programming lock register 0" bitfld.long 0x0 31. "SPLOCK31,Sticky programming lock for word 31" "0: Fuse word 31 can be burnt in fuse memory array,1: Attempt to program fuse word 31 in OTP memory.." bitfld.long 0x0 30. "SPLOCK30,Sticky programming lock for word 30" "0: Fuse word 30 can be burnt in fuse memory array,1: Attempt to program fuse word 30 in OTP memory.." newline bitfld.long 0x0 29. "SPLOCK29,Sticky programming lock for word 29" "0: Fuse word 29 can be burnt in fuse memory array,1: Attempt to program fuse word 29 in OTP memory.." bitfld.long 0x0 28. "SPLOCK28,Sticky programming lock for word 28" "0: Fuse word 28 can be burnt in fuse memory array,1: Attempt to program fuse word 28 in OTP memory.." newline bitfld.long 0x0 27. "SPLOCK27,Sticky programming lock for word 27" "0: Fuse word 27 can be burnt in fuse memory array,1: Attempt to program fuse word 27 in OTP memory.." bitfld.long 0x0 26. "SPLOCK26,Sticky programming lock for word 26" "0: Fuse word 26 can be burnt in fuse memory array,1: Attempt to program fuse word 26 in OTP memory.." newline bitfld.long 0x0 25. "SPLOCK25,Sticky programming lock for word 25" "0: Fuse word 25 can be burnt in fuse memory array,1: Attempt to program fuse word 25 in OTP memory.." bitfld.long 0x0 24. "SPLOCK24,Sticky programming lock for word 24" "0: Fuse word 24 can be burnt in fuse memory array,1: Attempt to program fuse word 24 in OTP memory.." newline bitfld.long 0x0 23. "SPLOCK23,Sticky programming lock for word 23" "0: Fuse word 23 can be burnt in fuse memory array,1: Attempt to program fuse word 23 in OTP memory.." bitfld.long 0x0 22. "SPLOCK22,Sticky programming lock for word 22" "0: Fuse word 22 can be burnt in fuse memory array,1: Attempt to program fuse word 22 in OTP memory.." newline bitfld.long 0x0 21. "SPLOCK21,Sticky programming lock for word 21" "0: Fuse word 21 can be burnt in fuse memory array,1: Attempt to program fuse word 21 in OTP memory.." bitfld.long 0x0 20. "SPLOCK20,Sticky programming lock for word 20" "0: Fuse word 20 can be burnt in fuse memory array,1: Attempt to program fuse word 20 in OTP memory.." newline bitfld.long 0x0 19. "SPLOCK19,Sticky programming lock for word 19" "0: Fuse word 19 can be burnt in fuse memory array,1: Attempt to program fuse word 19 in OTP memory.." bitfld.long 0x0 18. "SPLOCK18,Sticky programming lock for word 18" "0: Fuse word 18 can be burnt in fuse memory array,1: Attempt to program fuse word 18 in OTP memory.." newline bitfld.long 0x0 17. "SPLOCK17,Sticky programming lock for word 17" "0: Fuse word 17 can be burnt in fuse memory array,1: Attempt to program fuse word 17 in OTP memory.." bitfld.long 0x0 16. "SPLOCK16,Sticky programming lock for word 16" "0: Fuse word 16 can be burnt in fuse memory array,1: Attempt to program fuse word 16 in OTP memory.." newline bitfld.long 0x0 15. "SPLOCK15,Sticky programming lock for word 15" "0: Fuse word 15 can be burnt in fuse memory array,1: Attempt to program fuse word 15 in OTP memory.." bitfld.long 0x0 14. "SPLOCK14,Sticky programming lock for word 14" "0: Fuse word 14 can be burnt in fuse memory array,1: Attempt to program fuse word 14 in OTP memory.." newline bitfld.long 0x0 13. "SPLOCK13,Sticky programming lock for word 13" "0: Fuse word 13 can be burnt in fuse memory array,1: Attempt to program fuse word 13 in OTP memory.." bitfld.long 0x0 12. "SPLOCK12,Sticky programming lock for word 12" "0: Fuse word 12 can be burnt in fuse memory array,1: Attempt to program fuse word 12 in OTP memory.." newline bitfld.long 0x0 11. "SPLOCK11,Sticky programming lock for word 11" "0: Fuse word 11 can be burnt in fuse memory array,1: Attempt to program fuse word 11 in OTP memory.." bitfld.long 0x0 10. "SPLOCK10,Sticky programming lock for word 10" "0: Fuse word 10 can be burnt in fuse memory array,1: Attempt to program fuse word 10 in OTP memory.." newline bitfld.long 0x0 9. "SPLOCK9,Sticky programming lock for word 9" "0: Fuse word 9 can be burnt in fuse memory array,1: Attempt to program fuse word 9 in OTP memory.." bitfld.long 0x0 8. "SPLOCK8,Sticky programming lock for word 8" "0: Fuse word 8 can be burnt in fuse memory array,1: Attempt to program fuse word 8 in OTP memory.." newline bitfld.long 0x0 7. "SPLOCK7,Sticky programming lock for word 7" "0: Fuse word 7 can be burnt in fuse memory array,1: Attempt to program fuse word 7 in OTP memory.." bitfld.long 0x0 6. "SPLOCK6,Sticky programming lock for word 6" "0: Fuse word 6 can be burnt in fuse memory array,1: Attempt to program fuse word 6 in OTP memory.." newline bitfld.long 0x0 5. "SPLOCK5,Sticky programming lock for word 5" "0: Fuse word 5 can be burnt in fuse memory array,1: Attempt to program fuse word 5 in OTP memory.." bitfld.long 0x0 4. "SPLOCK4,Sticky programming lock for word 4" "0: Fuse word 4 can be burnt in fuse memory array,1: Attempt to program fuse word 4 in OTP memory.." newline bitfld.long 0x0 3. "SPLOCK3,Sticky programming lock for word 3" "0: Fuse word 3 can be burnt in fuse memory array,1: Attempt to program fuse word 3 in OTP memory.." bitfld.long 0x0 2. "SPLOCK2,Sticky programming lock for word 2" "0: Fuse word 2 can be burnt in fuse memory array,1: Attempt to program fuse word 2 in OTP memory.." newline bitfld.long 0x0 1. "SPLOCK1,Sticky programming lock for word 1" "0: Fuse word 1 can be burnt in fuse memory array,1: Attempt to program fuse word 1 in OTP memory.." bitfld.long 0x0 0. "SPLOCK0,Sticky programming lock for word 0" "0: Fuse word 0 can be burnt in fuse memory array,1: Attempt to program fuse word 0 in OTP memory.." line.long 0x4 "BSEC_SPLOCK1,BSEC sticky programming lock register 1" bitfld.long 0x4 31. "SPLOCK63,Sticky programming lock for word 63" "0: Fuse word 63 can be burnt in fuse memory array,1: Attempt to program fuse word 63 in OTP memory.." bitfld.long 0x4 30. "SPLOCK62,Sticky programming lock for word 62" "0: Fuse word 62 can be burnt in fuse memory array,1: Attempt to program fuse word 62 in OTP memory.." newline bitfld.long 0x4 29. "SPLOCK61,Sticky programming lock for word 61" "0: Fuse word 61 can be burnt in fuse memory array,1: Attempt to program fuse word 61 in OTP memory.." bitfld.long 0x4 28. "SPLOCK60,Sticky programming lock for word 60" "0: Fuse word 60 can be burnt in fuse memory array,1: Attempt to program fuse word 60 in OTP memory.." newline bitfld.long 0x4 27. "SPLOCK59,Sticky programming lock for word 59" "0: Fuse word 59 can be burnt in fuse memory array,1: Attempt to program fuse word 59 in OTP memory.." bitfld.long 0x4 26. "SPLOCK58,Sticky programming lock for word 58" "0: Fuse word 58 can be burnt in fuse memory array,1: Attempt to program fuse word 58 in OTP memory.." newline bitfld.long 0x4 25. "SPLOCK57,Sticky programming lock for word 57" "0: Fuse word 57 can be burnt in fuse memory array,1: Attempt to program fuse word 57 in OTP memory.." bitfld.long 0x4 24. "SPLOCK56,Sticky programming lock for word 56" "0: Fuse word 56 can be burnt in fuse memory array,1: Attempt to program fuse word 56 in OTP memory.." newline bitfld.long 0x4 23. "SPLOCK55,Sticky programming lock for word 55" "0: Fuse word 55 can be burnt in fuse memory array,1: Attempt to program fuse word 55 in OTP memory.." bitfld.long 0x4 22. "SPLOCK54,Sticky programming lock for word 54" "0: Fuse word 54 can be burnt in fuse memory array,1: Attempt to program fuse word 54 in OTP memory.." newline bitfld.long 0x4 21. "SPLOCK53,Sticky programming lock for word 53" "0: Fuse word 53 can be burnt in fuse memory array,1: Attempt to program fuse word 53 in OTP memory.." bitfld.long 0x4 20. "SPLOCK52,Sticky programming lock for word 52" "0: Fuse word 52 can be burnt in fuse memory array,1: Attempt to program fuse word 52 in OTP memory.." newline bitfld.long 0x4 19. "SPLOCK51,Sticky programming lock for word 51" "0: Fuse word 51 can be burnt in fuse memory array,1: Attempt to program fuse word 51 in OTP memory.." bitfld.long 0x4 18. "SPLOCK50,Sticky programming lock for word 50" "0: Fuse word 50 can be burnt in fuse memory array,1: Attempt to program fuse word 50 in OTP memory.." newline bitfld.long 0x4 17. "SPLOCK49,Sticky programming lock for word 49" "0: Fuse word 49 can be burnt in fuse memory array,1: Attempt to program fuse word 49 in OTP memory.." bitfld.long 0x4 16. "SPLOCK48,Sticky programming lock for word 48" "0: Fuse word 48 can be burnt in fuse memory array,1: Attempt to program fuse word 48 in OTP memory.." newline bitfld.long 0x4 15. "SPLOCK47,Sticky programming lock for word 47" "0: Fuse word 47 can be burnt in fuse memory array,1: Attempt to program fuse word 47 in OTP memory.." bitfld.long 0x4 14. "SPLOCK46,Sticky programming lock for word 46" "0: Fuse word 46 can be burnt in fuse memory array,1: Attempt to program fuse word 46 in OTP memory.." newline bitfld.long 0x4 13. "SPLOCK45,Sticky programming lock for word 45" "0: Fuse word 45 can be burnt in fuse memory array,1: Attempt to program fuse word 45 in OTP memory.." bitfld.long 0x4 12. "SPLOCK44,Sticky programming lock for word 44" "0: Fuse word 44 can be burnt in fuse memory array,1: Attempt to program fuse word 44 in OTP memory.." newline bitfld.long 0x4 11. "SPLOCK43,Sticky programming lock for word 43" "0: Fuse word 43 can be burnt in fuse memory array,1: Attempt to program fuse word 43 in OTP memory.." bitfld.long 0x4 10. "SPLOCK42,Sticky programming lock for word 42" "0: Fuse word 42 can be burnt in fuse memory array,1: Attempt to program fuse word 42 in OTP memory.." newline bitfld.long 0x4 9. "SPLOCK41,Sticky programming lock for word 41" "0: Fuse word 41 can be burnt in fuse memory array,1: Attempt to program fuse word 41 in OTP memory.." bitfld.long 0x4 8. "SPLOCK40,Sticky programming lock for word 40" "0: Fuse word 40 can be burnt in fuse memory array,1: Attempt to program fuse word 40 in OTP memory.." newline bitfld.long 0x4 7. "SPLOCK39,Sticky programming lock for word 39" "0: Fuse word 39 can be burnt in fuse memory array,1: Attempt to program fuse word 39 in OTP memory.." bitfld.long 0x4 6. "SPLOCK38,Sticky programming lock for word 38" "0: Fuse word 38 can be burnt in fuse memory array,1: Attempt to program fuse word 38 in OTP memory.." newline bitfld.long 0x4 5. "SPLOCK37,Sticky programming lock for word 37" "0: Fuse word 37 can be burnt in fuse memory array,1: Attempt to program fuse word 37 in OTP memory.." bitfld.long 0x4 4. "SPLOCK36,Sticky programming lock for word 36" "0: Fuse word 36 can be burnt in fuse memory array,1: Attempt to program fuse word 36 in OTP memory.." newline bitfld.long 0x4 3. "SPLOCK35,Sticky programming lock for word 35" "0: Fuse word 35 can be burnt in fuse memory array,1: Attempt to program fuse word 35 in OTP memory.." bitfld.long 0x4 2. "SPLOCK34,Sticky programming lock for word 34" "0: Fuse word 34 can be burnt in fuse memory array,1: Attempt to program fuse word 34 in OTP memory.." newline bitfld.long 0x4 1. "SPLOCK33,Sticky programming lock for word 33" "0: Fuse word 33 can be burnt in fuse memory array,1: Attempt to program fuse word 33 in OTP memory.." bitfld.long 0x4 0. "SPLOCK32,Sticky programming lock for word 32" "0: Fuse word 32 can be burnt in fuse memory array,1: Attempt to program fuse word 32 in OTP memory.." line.long 0x8 "BSEC_SPLOCK2,BSEC sticky programming lock register 2" bitfld.long 0x8 31. "SPLOCK95,Sticky programming lock for word 95" "0: Fuse word 95 can be burnt in fuse memory array,1: Attempt to program fuse word 95 in OTP memory.." bitfld.long 0x8 30. "SPLOCK94,Sticky programming lock for word 94" "0: Fuse word 94 can be burnt in fuse memory array,1: Attempt to program fuse word 94 in OTP memory.." newline bitfld.long 0x8 29. "SPLOCK93,Sticky programming lock for word 93" "0: Fuse word 93 can be burnt in fuse memory array,1: Attempt to program fuse word 93 in OTP memory.." bitfld.long 0x8 28. "SPLOCK92,Sticky programming lock for word 92" "0: Fuse word 92 can be burnt in fuse memory array,1: Attempt to program fuse word 92 in OTP memory.." newline bitfld.long 0x8 27. "SPLOCK91,Sticky programming lock for word 91" "0: Fuse word 91 can be burnt in fuse memory array,1: Attempt to program fuse word 91 in OTP memory.." bitfld.long 0x8 26. "SPLOCK90,Sticky programming lock for word 90" "0: Fuse word 90 can be burnt in fuse memory array,1: Attempt to program fuse word 90 in OTP memory.." newline bitfld.long 0x8 25. "SPLOCK89,Sticky programming lock for word 89" "0: Fuse word 89 can be burnt in fuse memory array,1: Attempt to program fuse word 89 in OTP memory.." bitfld.long 0x8 24. "SPLOCK88,Sticky programming lock for word 88" "0: Fuse word 88 can be burnt in fuse memory array,1: Attempt to program fuse word 88 in OTP memory.." newline bitfld.long 0x8 23. "SPLOCK87,Sticky programming lock for word 87" "0: Fuse word 87 can be burnt in fuse memory array,1: Attempt to program fuse word 87 in OTP memory.." bitfld.long 0x8 22. "SPLOCK86,Sticky programming lock for word 86" "0: Fuse word 86 can be burnt in fuse memory array,1: Attempt to program fuse word 86 in OTP memory.." newline bitfld.long 0x8 21. "SPLOCK85,Sticky programming lock for word 85" "0: Fuse word 85 can be burnt in fuse memory array,1: Attempt to program fuse word 85 in OTP memory.." bitfld.long 0x8 20. "SPLOCK84,Sticky programming lock for word 84" "0: Fuse word 84 can be burnt in fuse memory array,1: Attempt to program fuse word 84 in OTP memory.." newline bitfld.long 0x8 19. "SPLOCK83,Sticky programming lock for word 83" "0: Fuse word 83 can be burnt in fuse memory array,1: Attempt to program fuse word 83 in OTP memory.." bitfld.long 0x8 18. "SPLOCK82,Sticky programming lock for word 82" "0: Fuse word 82 can be burnt in fuse memory array,1: Attempt to program fuse word 82 in OTP memory.." newline bitfld.long 0x8 17. "SPLOCK81,Sticky programming lock for word 81" "0: Fuse word 81 can be burnt in fuse memory array,1: Attempt to program fuse word 81 in OTP memory.." bitfld.long 0x8 16. "SPLOCK80,Sticky programming lock for word 80" "0: Fuse word 80 can be burnt in fuse memory array,1: Attempt to program fuse word 80 in OTP memory.." newline bitfld.long 0x8 15. "SPLOCK79,Sticky programming lock for word 79" "0: Fuse word 79 can be burnt in fuse memory array,1: Attempt to program fuse word 79 in OTP memory.." bitfld.long 0x8 14. "SPLOCK78,Sticky programming lock for word 78" "0: Fuse word 78 can be burnt in fuse memory array,1: Attempt to program fuse word 78 in OTP memory.." newline bitfld.long 0x8 13. "SPLOCK77,Sticky programming lock for word 77" "0: Fuse word 77 can be burnt in fuse memory array,1: Attempt to program fuse word 77 in OTP memory.." bitfld.long 0x8 12. "SPLOCK76,Sticky programming lock for word 76" "0: Fuse word 76 can be burnt in fuse memory array,1: Attempt to program fuse word 76 in OTP memory.." newline bitfld.long 0x8 11. "SPLOCK75,Sticky programming lock for word 75" "0: Fuse word 75 can be burnt in fuse memory array,1: Attempt to program fuse word 75 in OTP memory.." bitfld.long 0x8 10. "SPLOCK74,Sticky programming lock for word 74" "0: Fuse word 74 can be burnt in fuse memory array,1: Attempt to program fuse word 74 in OTP memory.." newline bitfld.long 0x8 9. "SPLOCK73,Sticky programming lock for word 73" "0: Fuse word 73 can be burnt in fuse memory array,1: Attempt to program fuse word 73 in OTP memory.." bitfld.long 0x8 8. "SPLOCK72,Sticky programming lock for word 72" "0: Fuse word 72 can be burnt in fuse memory array,1: Attempt to program fuse word 72 in OTP memory.." newline bitfld.long 0x8 7. "SPLOCK71,Sticky programming lock for word 71" "0: Fuse word 71 can be burnt in fuse memory array,1: Attempt to program fuse word 71 in OTP memory.." bitfld.long 0x8 6. "SPLOCK70,Sticky programming lock for word 70" "0: Fuse word 70 can be burnt in fuse memory array,1: Attempt to program fuse word 70 in OTP memory.." newline bitfld.long 0x8 5. "SPLOCK69,Sticky programming lock for word 69" "0: Fuse word 69 can be burnt in fuse memory array,1: Attempt to program fuse word 69 in OTP memory.." bitfld.long 0x8 4. "SPLOCK68,Sticky programming lock for word 68" "0: Fuse word 68 can be burnt in fuse memory array,1: Attempt to program fuse word 68 in OTP memory.." newline bitfld.long 0x8 3. "SPLOCK67,Sticky programming lock for word 67" "0: Fuse word 67 can be burnt in fuse memory array,1: Attempt to program fuse word 67 in OTP memory.." bitfld.long 0x8 2. "SPLOCK66,Sticky programming lock for word 66" "0: Fuse word 66 can be burnt in fuse memory array,1: Attempt to program fuse word 66 in OTP memory.." newline bitfld.long 0x8 1. "SPLOCK65,Sticky programming lock for word 65" "0: Fuse word 65 can be burnt in fuse memory array,1: Attempt to program fuse word 65 in OTP memory.." bitfld.long 0x8 0. "SPLOCK64,Sticky programming lock for word 64" "0: Fuse word 64 can be burnt in fuse memory array,1: Attempt to program fuse word 64 in OTP memory.." line.long 0xC "BSEC_SPLOCK3,BSEC sticky programming lock register 3" bitfld.long 0xC 31. "SPLOCK127,Sticky programming lock for word 127" "0: Fuse word 127 can be burnt in fuse memory array,1: Attempt to program fuse word 127 in OTP memory.." bitfld.long 0xC 30. "SPLOCK126,Sticky programming lock for word 126" "0: Fuse word 126 can be burnt in fuse memory array,1: Attempt to program fuse word 126 in OTP memory.." newline bitfld.long 0xC 29. "SPLOCK125,Sticky programming lock for word 125" "0: Fuse word 125 can be burnt in fuse memory array,1: Attempt to program fuse word 125 in OTP memory.." bitfld.long 0xC 28. "SPLOCK124,Sticky programming lock for word 124" "0: Fuse word 124 can be burnt in fuse memory array,1: Attempt to program fuse word 124 in OTP memory.." newline bitfld.long 0xC 27. "SPLOCK123,Sticky programming lock for word 123" "0: Fuse word 123 can be burnt in fuse memory array,1: Attempt to program fuse word 123 in OTP memory.." bitfld.long 0xC 26. "SPLOCK122,Sticky programming lock for word 122" "0: Fuse word 122 can be burnt in fuse memory array,1: Attempt to program fuse word 122 in OTP memory.." newline bitfld.long 0xC 25. "SPLOCK121,Sticky programming lock for word 121" "0: Fuse word 121 can be burnt in fuse memory array,1: Attempt to program fuse word 121 in OTP memory.." bitfld.long 0xC 24. "SPLOCK120,Sticky programming lock for word 120" "0: Fuse word 120 can be burnt in fuse memory array,1: Attempt to program fuse word 120 in OTP memory.." newline bitfld.long 0xC 23. "SPLOCK119,Sticky programming lock for word 119" "0: Fuse word 119 can be burnt in fuse memory array,1: Attempt to program fuse word 119 in OTP memory.." bitfld.long 0xC 22. "SPLOCK118,Sticky programming lock for word 118" "0: Fuse word 118 can be burnt in fuse memory array,1: Attempt to program fuse word 118 in OTP memory.." newline bitfld.long 0xC 21. "SPLOCK117,Sticky programming lock for word 117" "0: Fuse word 117 can be burnt in fuse memory array,1: Attempt to program fuse word 117 in OTP memory.." bitfld.long 0xC 20. "SPLOCK116,Sticky programming lock for word 116" "0: Fuse word 116 can be burnt in fuse memory array,1: Attempt to program fuse word 116 in OTP memory.." newline bitfld.long 0xC 19. "SPLOCK115,Sticky programming lock for word 115" "0: Fuse word 115 can be burnt in fuse memory array,1: Attempt to program fuse word 115 in OTP memory.." bitfld.long 0xC 18. "SPLOCK114,Sticky programming lock for word 114" "0: Fuse word 114 can be burnt in fuse memory array,1: Attempt to program fuse word 114 in OTP memory.." newline bitfld.long 0xC 17. "SPLOCK113,Sticky programming lock for word 113" "0: Fuse word 113 can be burnt in fuse memory array,1: Attempt to program fuse word 113 in OTP memory.." bitfld.long 0xC 16. "SPLOCK112,Sticky programming lock for word 112" "0: Fuse word 112 can be burnt in fuse memory array,1: Attempt to program fuse word 112 in OTP memory.." newline bitfld.long 0xC 15. "SPLOCK111,Sticky programming lock for word 111" "0: Fuse word 111 can be burnt in fuse memory array,1: Attempt to program fuse word 111 in OTP memory.." bitfld.long 0xC 14. "SPLOCK110,Sticky programming lock for word 110" "0: Fuse word 110 can be burnt in fuse memory array,1: Attempt to program fuse word 110 in OTP memory.." newline bitfld.long 0xC 13. "SPLOCK109,Sticky programming lock for word 109" "0: Fuse word 109 can be burnt in fuse memory array,1: Attempt to program fuse word 109 in OTP memory.." bitfld.long 0xC 12. "SPLOCK108,Sticky programming lock for word 108" "0: Fuse word 108 can be burnt in fuse memory array,1: Attempt to program fuse word 108 in OTP memory.." newline bitfld.long 0xC 11. "SPLOCK107,Sticky programming lock for word 107" "0: Fuse word 107 can be burnt in fuse memory array,1: Attempt to program fuse word 107 in OTP memory.." bitfld.long 0xC 10. "SPLOCK106,Sticky programming lock for word 106" "0: Fuse word 106 can be burnt in fuse memory array,1: Attempt to program fuse word 106 in OTP memory.." newline bitfld.long 0xC 9. "SPLOCK105,Sticky programming lock for word 105" "0: Fuse word 105 can be burnt in fuse memory array,1: Attempt to program fuse word 105 in OTP memory.." bitfld.long 0xC 8. "SPLOCK104,Sticky programming lock for word 104" "0: Fuse word 104 can be burnt in fuse memory array,1: Attempt to program fuse word 104 in OTP memory.." newline bitfld.long 0xC 7. "SPLOCK103,Sticky programming lock for word 103" "0: Fuse word 103 can be burnt in fuse memory array,1: Attempt to program fuse word 103 in OTP memory.." bitfld.long 0xC 6. "SPLOCK102,Sticky programming lock for word 102" "0: Fuse word 102 can be burnt in fuse memory array,1: Attempt to program fuse word 102 in OTP memory.." newline bitfld.long 0xC 5. "SPLOCK101,Sticky programming lock for word 101" "0: Fuse word 101 can be burnt in fuse memory array,1: Attempt to program fuse word 101 in OTP memory.." bitfld.long 0xC 4. "SPLOCK100,Sticky programming lock for word 100" "0: Fuse word 100 can be burnt in fuse memory array,1: Attempt to program fuse word 100 in OTP memory.." newline bitfld.long 0xC 3. "SPLOCK99,Sticky programming lock for word 99" "0: Fuse word 99 can be burnt in fuse memory array,1: Attempt to program fuse word 99 in OTP memory.." bitfld.long 0xC 2. "SPLOCK98,Sticky programming lock for word 98" "0: Fuse word 98 can be burnt in fuse memory array,1: Attempt to program fuse word 98 in OTP memory.." newline bitfld.long 0xC 1. "SPLOCK97,Sticky programming lock for word 97" "0: Fuse word 97 can be burnt in fuse memory array,1: Attempt to program fuse word 97 in OTP memory.." bitfld.long 0xC 0. "SPLOCK96,Sticky programming lock for word 96" "0: Fuse word 96 can be burnt in fuse memory array,1: Attempt to program fuse word 96 in OTP memory.." line.long 0x10 "BSEC_SPLOCK4,BSEC sticky programming lock register 4" bitfld.long 0x10 31. "SPLOCK159,Sticky programming lock for word 159" "0: Fuse word 159 can be burnt in fuse memory array,1: Attempt to program fuse word 159 in OTP memory.." bitfld.long 0x10 30. "SPLOCK158,Sticky programming lock for word 158" "0: Fuse word 158 can be burnt in fuse memory array,1: Attempt to program fuse word 158 in OTP memory.." newline bitfld.long 0x10 29. "SPLOCK157,Sticky programming lock for word 157" "0: Fuse word 157 can be burnt in fuse memory array,1: Attempt to program fuse word 157 in OTP memory.." bitfld.long 0x10 28. "SPLOCK156,Sticky programming lock for word 156" "0: Fuse word 156 can be burnt in fuse memory array,1: Attempt to program fuse word 156 in OTP memory.." newline bitfld.long 0x10 27. "SPLOCK155,Sticky programming lock for word 155" "0: Fuse word 155 can be burnt in fuse memory array,1: Attempt to program fuse word 155 in OTP memory.." bitfld.long 0x10 26. "SPLOCK154,Sticky programming lock for word 154" "0: Fuse word 154 can be burnt in fuse memory array,1: Attempt to program fuse word 154 in OTP memory.." newline bitfld.long 0x10 25. "SPLOCK153,Sticky programming lock for word 153" "0: Fuse word 153 can be burnt in fuse memory array,1: Attempt to program fuse word 153 in OTP memory.." bitfld.long 0x10 24. "SPLOCK152,Sticky programming lock for word 152" "0: Fuse word 152 can be burnt in fuse memory array,1: Attempt to program fuse word 152 in OTP memory.." newline bitfld.long 0x10 23. "SPLOCK151,Sticky programming lock for word 151" "0: Fuse word 151 can be burnt in fuse memory array,1: Attempt to program fuse word 151 in OTP memory.." bitfld.long 0x10 22. "SPLOCK150,Sticky programming lock for word 150" "0: Fuse word 150 can be burnt in fuse memory array,1: Attempt to program fuse word 150 in OTP memory.." newline bitfld.long 0x10 21. "SPLOCK149,Sticky programming lock for word 149" "0: Fuse word 149 can be burnt in fuse memory array,1: Attempt to program fuse word 149 in OTP memory.." bitfld.long 0x10 20. "SPLOCK148,Sticky programming lock for word 148" "0: Fuse word 148 can be burnt in fuse memory array,1: Attempt to program fuse word 148 in OTP memory.." newline bitfld.long 0x10 19. "SPLOCK147,Sticky programming lock for word 147" "0: Fuse word 147 can be burnt in fuse memory array,1: Attempt to program fuse word 147 in OTP memory.." bitfld.long 0x10 18. "SPLOCK146,Sticky programming lock for word 146" "0: Fuse word 146 can be burnt in fuse memory array,1: Attempt to program fuse word 146 in OTP memory.." newline bitfld.long 0x10 17. "SPLOCK145,Sticky programming lock for word 145" "0: Fuse word 145 can be burnt in fuse memory array,1: Attempt to program fuse word 145 in OTP memory.." bitfld.long 0x10 16. "SPLOCK144,Sticky programming lock for word 144" "0: Fuse word 144 can be burnt in fuse memory array,1: Attempt to program fuse word 144 in OTP memory.." newline bitfld.long 0x10 15. "SPLOCK143,Sticky programming lock for word 143" "0: Fuse word 143 can be burnt in fuse memory array,1: Attempt to program fuse word 143 in OTP memory.." bitfld.long 0x10 14. "SPLOCK142,Sticky programming lock for word 142" "0: Fuse word 142 can be burnt in fuse memory array,1: Attempt to program fuse word 142 in OTP memory.." newline bitfld.long 0x10 13. "SPLOCK141,Sticky programming lock for word 141" "0: Fuse word 141 can be burnt in fuse memory array,1: Attempt to program fuse word 141 in OTP memory.." bitfld.long 0x10 12. "SPLOCK140,Sticky programming lock for word 140" "0: Fuse word 140 can be burnt in fuse memory array,1: Attempt to program fuse word 140 in OTP memory.." newline bitfld.long 0x10 11. "SPLOCK139,Sticky programming lock for word 139" "0: Fuse word 139 can be burnt in fuse memory array,1: Attempt to program fuse word 139 in OTP memory.." bitfld.long 0x10 10. "SPLOCK138,Sticky programming lock for word 138" "0: Fuse word 138 can be burnt in fuse memory array,1: Attempt to program fuse word 138 in OTP memory.." newline bitfld.long 0x10 9. "SPLOCK137,Sticky programming lock for word 137" "0: Fuse word 137 can be burnt in fuse memory array,1: Attempt to program fuse word 137 in OTP memory.." bitfld.long 0x10 8. "SPLOCK136,Sticky programming lock for word 136" "0: Fuse word 136 can be burnt in fuse memory array,1: Attempt to program fuse word 136 in OTP memory.." newline bitfld.long 0x10 7. "SPLOCK135,Sticky programming lock for word 135" "0: Fuse word 135 can be burnt in fuse memory array,1: Attempt to program fuse word 135 in OTP memory.." bitfld.long 0x10 6. "SPLOCK134,Sticky programming lock for word 134" "0: Fuse word 134 can be burnt in fuse memory array,1: Attempt to program fuse word 134 in OTP memory.." newline bitfld.long 0x10 5. "SPLOCK133,Sticky programming lock for word 133" "0: Fuse word 133 can be burnt in fuse memory array,1: Attempt to program fuse word 133 in OTP memory.." bitfld.long 0x10 4. "SPLOCK132,Sticky programming lock for word 132" "0: Fuse word 132 can be burnt in fuse memory array,1: Attempt to program fuse word 132 in OTP memory.." newline bitfld.long 0x10 3. "SPLOCK131,Sticky programming lock for word 131" "0: Fuse word 131 can be burnt in fuse memory array,1: Attempt to program fuse word 131 in OTP memory.." bitfld.long 0x10 2. "SPLOCK130,Sticky programming lock for word 130" "0: Fuse word 130 can be burnt in fuse memory array,1: Attempt to program fuse word 130 in OTP memory.." newline bitfld.long 0x10 1. "SPLOCK129,Sticky programming lock for word 129" "0: Fuse word 129 can be burnt in fuse memory array,1: Attempt to program fuse word 129 in OTP memory.." bitfld.long 0x10 0. "SPLOCK128,Sticky programming lock for word 128" "0: Fuse word 128 can be burnt in fuse memory array,1: Attempt to program fuse word 128 in OTP memory.." line.long 0x14 "BSEC_SPLOCK5,BSEC sticky programming lock register 5" bitfld.long 0x14 31. "SPLOCK191,Sticky programming lock for word 191" "0: Fuse word 191 can be burnt in fuse memory array,1: Attempt to program fuse word 191 in OTP memory.." bitfld.long 0x14 30. "SPLOCK190,Sticky programming lock for word 190" "0: Fuse word 190 can be burnt in fuse memory array,1: Attempt to program fuse word 190 in OTP memory.." newline bitfld.long 0x14 29. "SPLOCK189,Sticky programming lock for word 189" "0: Fuse word 189 can be burnt in fuse memory array,1: Attempt to program fuse word 189 in OTP memory.." bitfld.long 0x14 28. "SPLOCK188,Sticky programming lock for word 188" "0: Fuse word 188 can be burnt in fuse memory array,1: Attempt to program fuse word 188 in OTP memory.." newline bitfld.long 0x14 27. "SPLOCK187,Sticky programming lock for word 187" "0: Fuse word 187 can be burnt in fuse memory array,1: Attempt to program fuse word 187 in OTP memory.." bitfld.long 0x14 26. "SPLOCK186,Sticky programming lock for word 186" "0: Fuse word 186 can be burnt in fuse memory array,1: Attempt to program fuse word 186 in OTP memory.." newline bitfld.long 0x14 25. "SPLOCK185,Sticky programming lock for word 185" "0: Fuse word 185 can be burnt in fuse memory array,1: Attempt to program fuse word 185 in OTP memory.." bitfld.long 0x14 24. "SPLOCK184,Sticky programming lock for word 184" "0: Fuse word 184 can be burnt in fuse memory array,1: Attempt to program fuse word 184 in OTP memory.." newline bitfld.long 0x14 23. "SPLOCK183,Sticky programming lock for word 183" "0: Fuse word 183 can be burnt in fuse memory array,1: Attempt to program fuse word 183 in OTP memory.." bitfld.long 0x14 22. "SPLOCK182,Sticky programming lock for word 182" "0: Fuse word 182 can be burnt in fuse memory array,1: Attempt to program fuse word 182 in OTP memory.." newline bitfld.long 0x14 21. "SPLOCK181,Sticky programming lock for word 181" "0: Fuse word 181 can be burnt in fuse memory array,1: Attempt to program fuse word 181 in OTP memory.." bitfld.long 0x14 20. "SPLOCK180,Sticky programming lock for word 180" "0: Fuse word 180 can be burnt in fuse memory array,1: Attempt to program fuse word 180 in OTP memory.." newline bitfld.long 0x14 19. "SPLOCK179,Sticky programming lock for word 179" "0: Fuse word 179 can be burnt in fuse memory array,1: Attempt to program fuse word 179 in OTP memory.." bitfld.long 0x14 18. "SPLOCK178,Sticky programming lock for word 178" "0: Fuse word 178 can be burnt in fuse memory array,1: Attempt to program fuse word 178 in OTP memory.." newline bitfld.long 0x14 17. "SPLOCK177,Sticky programming lock for word 177" "0: Fuse word 177 can be burnt in fuse memory array,1: Attempt to program fuse word 177 in OTP memory.." bitfld.long 0x14 16. "SPLOCK176,Sticky programming lock for word 176" "0: Fuse word 176 can be burnt in fuse memory array,1: Attempt to program fuse word 176 in OTP memory.." newline bitfld.long 0x14 15. "SPLOCK175,Sticky programming lock for word 175" "0: Fuse word 175 can be burnt in fuse memory array,1: Attempt to program fuse word 175 in OTP memory.." bitfld.long 0x14 14. "SPLOCK174,Sticky programming lock for word 174" "0: Fuse word 174 can be burnt in fuse memory array,1: Attempt to program fuse word 174 in OTP memory.." newline bitfld.long 0x14 13. "SPLOCK173,Sticky programming lock for word 173" "0: Fuse word 173 can be burnt in fuse memory array,1: Attempt to program fuse word 173 in OTP memory.." bitfld.long 0x14 12. "SPLOCK172,Sticky programming lock for word 172" "0: Fuse word 172 can be burnt in fuse memory array,1: Attempt to program fuse word 172 in OTP memory.." newline bitfld.long 0x14 11. "SPLOCK171,Sticky programming lock for word 171" "0: Fuse word 171 can be burnt in fuse memory array,1: Attempt to program fuse word 171 in OTP memory.." bitfld.long 0x14 10. "SPLOCK170,Sticky programming lock for word 170" "0: Fuse word 170 can be burnt in fuse memory array,1: Attempt to program fuse word 170 in OTP memory.." newline bitfld.long 0x14 9. "SPLOCK169,Sticky programming lock for word 169" "0: Fuse word 169 can be burnt in fuse memory array,1: Attempt to program fuse word 169 in OTP memory.." bitfld.long 0x14 8. "SPLOCK168,Sticky programming lock for word 168" "0: Fuse word 168 can be burnt in fuse memory array,1: Attempt to program fuse word 168 in OTP memory.." newline bitfld.long 0x14 7. "SPLOCK167,Sticky programming lock for word 167" "0: Fuse word 167 can be burnt in fuse memory array,1: Attempt to program fuse word 167 in OTP memory.." bitfld.long 0x14 6. "SPLOCK166,Sticky programming lock for word 166" "0: Fuse word 166 can be burnt in fuse memory array,1: Attempt to program fuse word 166 in OTP memory.." newline bitfld.long 0x14 5. "SPLOCK165,Sticky programming lock for word 165" "0: Fuse word 165 can be burnt in fuse memory array,1: Attempt to program fuse word 165 in OTP memory.." bitfld.long 0x14 4. "SPLOCK164,Sticky programming lock for word 164" "0: Fuse word 164 can be burnt in fuse memory array,1: Attempt to program fuse word 164 in OTP memory.." newline bitfld.long 0x14 3. "SPLOCK163,Sticky programming lock for word 163" "0: Fuse word 163 can be burnt in fuse memory array,1: Attempt to program fuse word 163 in OTP memory.." bitfld.long 0x14 2. "SPLOCK162,Sticky programming lock for word 162" "0: Fuse word 162 can be burnt in fuse memory array,1: Attempt to program fuse word 162 in OTP memory.." newline bitfld.long 0x14 1. "SPLOCK161,Sticky programming lock for word 161" "0: Fuse word 161 can be burnt in fuse memory array,1: Attempt to program fuse word 161 in OTP memory.." bitfld.long 0x14 0. "SPLOCK160,Sticky programming lock for word 160" "0: Fuse word 160 can be burnt in fuse memory array,1: Attempt to program fuse word 160 in OTP memory.." line.long 0x18 "BSEC_SPLOCK6,BSEC sticky programming lock register 6" bitfld.long 0x18 31. "SPLOCK223,Sticky programming lock for word 223" "0: Fuse word 223 can be burnt in fuse memory array,1: Attempt to program fuse word 223 in OTP memory.." bitfld.long 0x18 30. "SPLOCK222,Sticky programming lock for word 222" "0: Fuse word 222 can be burnt in fuse memory array,1: Attempt to program fuse word 222 in OTP memory.." newline bitfld.long 0x18 29. "SPLOCK221,Sticky programming lock for word 221" "0: Fuse word 221 can be burnt in fuse memory array,1: Attempt to program fuse word 221 in OTP memory.." bitfld.long 0x18 28. "SPLOCK220,Sticky programming lock for word 220" "0: Fuse word 220 can be burnt in fuse memory array,1: Attempt to program fuse word 220 in OTP memory.." newline bitfld.long 0x18 27. "SPLOCK219,Sticky programming lock for word 219" "0: Fuse word 219 can be burnt in fuse memory array,1: Attempt to program fuse word 219 in OTP memory.." bitfld.long 0x18 26. "SPLOCK218,Sticky programming lock for word 218" "0: Fuse word 218 can be burnt in fuse memory array,1: Attempt to program fuse word 218 in OTP memory.." newline bitfld.long 0x18 25. "SPLOCK217,Sticky programming lock for word 217" "0: Fuse word 217 can be burnt in fuse memory array,1: Attempt to program fuse word 217 in OTP memory.." bitfld.long 0x18 24. "SPLOCK216,Sticky programming lock for word 216" "0: Fuse word 216 can be burnt in fuse memory array,1: Attempt to program fuse word 216 in OTP memory.." newline bitfld.long 0x18 23. "SPLOCK215,Sticky programming lock for word 215" "0: Fuse word 215 can be burnt in fuse memory array,1: Attempt to program fuse word 215 in OTP memory.." bitfld.long 0x18 22. "SPLOCK214,Sticky programming lock for word 214" "0: Fuse word 214 can be burnt in fuse memory array,1: Attempt to program fuse word 214 in OTP memory.." newline bitfld.long 0x18 21. "SPLOCK213,Sticky programming lock for word 213" "0: Fuse word 213 can be burnt in fuse memory array,1: Attempt to program fuse word 213 in OTP memory.." bitfld.long 0x18 20. "SPLOCK212,Sticky programming lock for word 212" "0: Fuse word 212 can be burnt in fuse memory array,1: Attempt to program fuse word 212 in OTP memory.." newline bitfld.long 0x18 19. "SPLOCK211,Sticky programming lock for word 211" "0: Fuse word 211 can be burnt in fuse memory array,1: Attempt to program fuse word 211 in OTP memory.." bitfld.long 0x18 18. "SPLOCK210,Sticky programming lock for word 210" "0: Fuse word 210 can be burnt in fuse memory array,1: Attempt to program fuse word 210 in OTP memory.." newline bitfld.long 0x18 17. "SPLOCK209,Sticky programming lock for word 209" "0: Fuse word 209 can be burnt in fuse memory array,1: Attempt to program fuse word 209 in OTP memory.." bitfld.long 0x18 16. "SPLOCK208,Sticky programming lock for word 208" "0: Fuse word 208 can be burnt in fuse memory array,1: Attempt to program fuse word 208 in OTP memory.." newline bitfld.long 0x18 15. "SPLOCK207,Sticky programming lock for word 207" "0: Fuse word 207 can be burnt in fuse memory array,1: Attempt to program fuse word 207 in OTP memory.." bitfld.long 0x18 14. "SPLOCK206,Sticky programming lock for word 206" "0: Fuse word 206 can be burnt in fuse memory array,1: Attempt to program fuse word 206 in OTP memory.." newline bitfld.long 0x18 13. "SPLOCK205,Sticky programming lock for word 205" "0: Fuse word 205 can be burnt in fuse memory array,1: Attempt to program fuse word 205 in OTP memory.." bitfld.long 0x18 12. "SPLOCK204,Sticky programming lock for word 204" "0: Fuse word 204 can be burnt in fuse memory array,1: Attempt to program fuse word 204 in OTP memory.." newline bitfld.long 0x18 11. "SPLOCK203,Sticky programming lock for word 203" "0: Fuse word 203 can be burnt in fuse memory array,1: Attempt to program fuse word 203 in OTP memory.." bitfld.long 0x18 10. "SPLOCK202,Sticky programming lock for word 202" "0: Fuse word 202 can be burnt in fuse memory array,1: Attempt to program fuse word 202 in OTP memory.." newline bitfld.long 0x18 9. "SPLOCK201,Sticky programming lock for word 201" "0: Fuse word 201 can be burnt in fuse memory array,1: Attempt to program fuse word 201 in OTP memory.." bitfld.long 0x18 8. "SPLOCK200,Sticky programming lock for word 200" "0: Fuse word 200 can be burnt in fuse memory array,1: Attempt to program fuse word 200 in OTP memory.." newline bitfld.long 0x18 7. "SPLOCK199,Sticky programming lock for word 199" "0: Fuse word 199 can be burnt in fuse memory array,1: Attempt to program fuse word 199 in OTP memory.." bitfld.long 0x18 6. "SPLOCK198,Sticky programming lock for word 198" "0: Fuse word 198 can be burnt in fuse memory array,1: Attempt to program fuse word 198 in OTP memory.." newline bitfld.long 0x18 5. "SPLOCK197,Sticky programming lock for word 197" "0: Fuse word 197 can be burnt in fuse memory array,1: Attempt to program fuse word 197 in OTP memory.." bitfld.long 0x18 4. "SPLOCK196,Sticky programming lock for word 196" "0: Fuse word 196 can be burnt in fuse memory array,1: Attempt to program fuse word 196 in OTP memory.." newline bitfld.long 0x18 3. "SPLOCK195,Sticky programming lock for word 195" "0: Fuse word 195 can be burnt in fuse memory array,1: Attempt to program fuse word 195 in OTP memory.." bitfld.long 0x18 2. "SPLOCK194,Sticky programming lock for word 194" "0: Fuse word 194 can be burnt in fuse memory array,1: Attempt to program fuse word 194 in OTP memory.." newline bitfld.long 0x18 1. "SPLOCK193,Sticky programming lock for word 193" "0: Fuse word 193 can be burnt in fuse memory array,1: Attempt to program fuse word 193 in OTP memory.." bitfld.long 0x18 0. "SPLOCK192,Sticky programming lock for word 192" "0: Fuse word 192 can be burnt in fuse memory array,1: Attempt to program fuse word 192 in OTP memory.." line.long 0x1C "BSEC_SPLOCK7,BSEC sticky programming lock register 7" bitfld.long 0x1C 31. "SPLOCK255,Sticky programming lock for word 255" "0: Fuse word 255 can be burnt in fuse memory array,1: Attempt to program fuse word 255 in OTP memory.." bitfld.long 0x1C 30. "SPLOCK254,Sticky programming lock for word 254" "0: Fuse word 254 can be burnt in fuse memory array,1: Attempt to program fuse word 254 in OTP memory.." newline bitfld.long 0x1C 29. "SPLOCK253,Sticky programming lock for word 253" "0: Fuse word 253 can be burnt in fuse memory array,1: Attempt to program fuse word 253 in OTP memory.." bitfld.long 0x1C 28. "SPLOCK252,Sticky programming lock for word 252" "0: Fuse word 252 can be burnt in fuse memory array,1: Attempt to program fuse word 252 in OTP memory.." newline bitfld.long 0x1C 27. "SPLOCK251,Sticky programming lock for word 251" "0: Fuse word 251 can be burnt in fuse memory array,1: Attempt to program fuse word 251 in OTP memory.." bitfld.long 0x1C 26. "SPLOCK250,Sticky programming lock for word 250" "0: Fuse word 250 can be burnt in fuse memory array,1: Attempt to program fuse word 250 in OTP memory.." newline bitfld.long 0x1C 25. "SPLOCK249,Sticky programming lock for word 249" "0: Fuse word 249 can be burnt in fuse memory array,1: Attempt to program fuse word 249 in OTP memory.." bitfld.long 0x1C 24. "SPLOCK248,Sticky programming lock for word 248" "0: Fuse word 248 can be burnt in fuse memory array,1: Attempt to program fuse word 248 in OTP memory.." newline bitfld.long 0x1C 23. "SPLOCK247,Sticky programming lock for word 247" "0: Fuse word 247 can be burnt in fuse memory array,1: Attempt to program fuse word 247 in OTP memory.." bitfld.long 0x1C 22. "SPLOCK246,Sticky programming lock for word 246" "0: Fuse word 246 can be burnt in fuse memory array,1: Attempt to program fuse word 246 in OTP memory.." newline bitfld.long 0x1C 21. "SPLOCK245,Sticky programming lock for word 245" "0: Fuse word 245 can be burnt in fuse memory array,1: Attempt to program fuse word 245 in OTP memory.." bitfld.long 0x1C 20. "SPLOCK244,Sticky programming lock for word 244" "0: Fuse word 244 can be burnt in fuse memory array,1: Attempt to program fuse word 244 in OTP memory.." newline bitfld.long 0x1C 19. "SPLOCK243,Sticky programming lock for word 243" "0: Fuse word 243 can be burnt in fuse memory array,1: Attempt to program fuse word 243 in OTP memory.." bitfld.long 0x1C 18. "SPLOCK242,Sticky programming lock for word 242" "0: Fuse word 242 can be burnt in fuse memory array,1: Attempt to program fuse word 242 in OTP memory.." newline bitfld.long 0x1C 17. "SPLOCK241,Sticky programming lock for word 241" "0: Fuse word 241 can be burnt in fuse memory array,1: Attempt to program fuse word 241 in OTP memory.." bitfld.long 0x1C 16. "SPLOCK240,Sticky programming lock for word 240" "0: Fuse word 240 can be burnt in fuse memory array,1: Attempt to program fuse word 240 in OTP memory.." newline bitfld.long 0x1C 15. "SPLOCK239,Sticky programming lock for word 239" "0: Fuse word 239 can be burnt in fuse memory array,1: Attempt to program fuse word 239 in OTP memory.." bitfld.long 0x1C 14. "SPLOCK238,Sticky programming lock for word 238" "0: Fuse word 238 can be burnt in fuse memory array,1: Attempt to program fuse word 238 in OTP memory.." newline bitfld.long 0x1C 13. "SPLOCK237,Sticky programming lock for word 237" "0: Fuse word 237 can be burnt in fuse memory array,1: Attempt to program fuse word 237 in OTP memory.." bitfld.long 0x1C 12. "SPLOCK236,Sticky programming lock for word 236" "0: Fuse word 236 can be burnt in fuse memory array,1: Attempt to program fuse word 236 in OTP memory.." newline bitfld.long 0x1C 11. "SPLOCK235,Sticky programming lock for word 235" "0: Fuse word 235 can be burnt in fuse memory array,1: Attempt to program fuse word 235 in OTP memory.." bitfld.long 0x1C 10. "SPLOCK234,Sticky programming lock for word 234" "0: Fuse word 234 can be burnt in fuse memory array,1: Attempt to program fuse word 234 in OTP memory.." newline bitfld.long 0x1C 9. "SPLOCK233,Sticky programming lock for word 233" "0: Fuse word 233 can be burnt in fuse memory array,1: Attempt to program fuse word 233 in OTP memory.." bitfld.long 0x1C 8. "SPLOCK232,Sticky programming lock for word 232" "0: Fuse word 232 can be burnt in fuse memory array,1: Attempt to program fuse word 232 in OTP memory.." newline bitfld.long 0x1C 7. "SPLOCK231,Sticky programming lock for word 231" "0: Fuse word 231 can be burnt in fuse memory array,1: Attempt to program fuse word 231 in OTP memory.." bitfld.long 0x1C 6. "SPLOCK230,Sticky programming lock for word 230" "0: Fuse word 230 can be burnt in fuse memory array,1: Attempt to program fuse word 230 in OTP memory.." newline bitfld.long 0x1C 5. "SPLOCK229,Sticky programming lock for word 229" "0: Fuse word 229 can be burnt in fuse memory array,1: Attempt to program fuse word 229 in OTP memory.." bitfld.long 0x1C 4. "SPLOCK228,Sticky programming lock for word 228" "0: Fuse word 228 can be burnt in fuse memory array,1: Attempt to program fuse word 228 in OTP memory.." newline bitfld.long 0x1C 3. "SPLOCK227,Sticky programming lock for word 227" "0: Fuse word 227 can be burnt in fuse memory array,1: Attempt to program fuse word 227 in OTP memory.." bitfld.long 0x1C 2. "SPLOCK226,Sticky programming lock for word 226" "0: Fuse word 226 can be burnt in fuse memory array,1: Attempt to program fuse word 226 in OTP memory.." newline bitfld.long 0x1C 1. "SPLOCK225,Sticky programming lock for word 225" "0: Fuse word 225 can be burnt in fuse memory array,1: Attempt to program fuse word 225 in OTP memory.." bitfld.long 0x1C 0. "SPLOCK224,Sticky programming lock for word 224" "0: Fuse word 224 can be burnt in fuse memory array,1: Attempt to program fuse word 224 in OTP memory.." line.long 0x20 "BSEC_SPLOCK8,BSEC sticky programming lock register 8" bitfld.long 0x20 31. "SPLOCK287,Sticky programming lock for word 287" "0: Fuse word 287 can be burnt in fuse memory array,1: Attempt to program fuse word 287 in OTP memory.." bitfld.long 0x20 30. "SPLOCK286,Sticky programming lock for word 286" "0: Fuse word 286 can be burnt in fuse memory array,1: Attempt to program fuse word 286 in OTP memory.." newline bitfld.long 0x20 29. "SPLOCK285,Sticky programming lock for word 285" "0: Fuse word 285 can be burnt in fuse memory array,1: Attempt to program fuse word 285 in OTP memory.." bitfld.long 0x20 28. "SPLOCK284,Sticky programming lock for word 284" "0: Fuse word 284 can be burnt in fuse memory array,1: Attempt to program fuse word 284 in OTP memory.." newline bitfld.long 0x20 27. "SPLOCK283,Sticky programming lock for word 283" "0: Fuse word 283 can be burnt in fuse memory array,1: Attempt to program fuse word 283 in OTP memory.." bitfld.long 0x20 26. "SPLOCK282,Sticky programming lock for word 282" "0: Fuse word 282 can be burnt in fuse memory array,1: Attempt to program fuse word 282 in OTP memory.." newline bitfld.long 0x20 25. "SPLOCK281,Sticky programming lock for word 281" "0: Fuse word 281 can be burnt in fuse memory array,1: Attempt to program fuse word 281 in OTP memory.." bitfld.long 0x20 24. "SPLOCK280,Sticky programming lock for word 280" "0: Fuse word 280 can be burnt in fuse memory array,1: Attempt to program fuse word 280 in OTP memory.." newline bitfld.long 0x20 23. "SPLOCK279,Sticky programming lock for word 279" "0: Fuse word 279 can be burnt in fuse memory array,1: Attempt to program fuse word 279 in OTP memory.." bitfld.long 0x20 22. "SPLOCK278,Sticky programming lock for word 278" "0: Fuse word 278 can be burnt in fuse memory array,1: Attempt to program fuse word 278 in OTP memory.." newline bitfld.long 0x20 21. "SPLOCK277,Sticky programming lock for word 277" "0: Fuse word 277 can be burnt in fuse memory array,1: Attempt to program fuse word 277 in OTP memory.." bitfld.long 0x20 20. "SPLOCK276,Sticky programming lock for word 276" "0: Fuse word 276 can be burnt in fuse memory array,1: Attempt to program fuse word 276 in OTP memory.." newline bitfld.long 0x20 19. "SPLOCK275,Sticky programming lock for word 275" "0: Fuse word 275 can be burnt in fuse memory array,1: Attempt to program fuse word 275 in OTP memory.." bitfld.long 0x20 18. "SPLOCK274,Sticky programming lock for word 274" "0: Fuse word 274 can be burnt in fuse memory array,1: Attempt to program fuse word 274 in OTP memory.." newline bitfld.long 0x20 17. "SPLOCK273,Sticky programming lock for word 273" "0: Fuse word 273 can be burnt in fuse memory array,1: Attempt to program fuse word 273 in OTP memory.." bitfld.long 0x20 16. "SPLOCK272,Sticky programming lock for word 272" "0: Fuse word 272 can be burnt in fuse memory array,1: Attempt to program fuse word 272 in OTP memory.." newline bitfld.long 0x20 15. "SPLOCK271,Sticky programming lock for word 271" "0: Fuse word 271 can be burnt in fuse memory array,1: Attempt to program fuse word 271 in OTP memory.." bitfld.long 0x20 14. "SPLOCK270,Sticky programming lock for word 270" "0: Fuse word 270 can be burnt in fuse memory array,1: Attempt to program fuse word 270 in OTP memory.." newline bitfld.long 0x20 13. "SPLOCK269,Sticky programming lock for word 269" "0: Fuse word 269 can be burnt in fuse memory array,1: Attempt to program fuse word 269 in OTP memory.." bitfld.long 0x20 12. "SPLOCK268,Sticky programming lock for word 268" "0: Fuse word 268 can be burnt in fuse memory array,1: Attempt to program fuse word 268 in OTP memory.." newline bitfld.long 0x20 11. "SPLOCK267,Sticky programming lock for word 267" "0: Fuse word 267 can be burnt in fuse memory array,1: Attempt to program fuse word 267 in OTP memory.." bitfld.long 0x20 10. "SPLOCK266,Sticky programming lock for word 266" "0: Fuse word 266 can be burnt in fuse memory array,1: Attempt to program fuse word 266 in OTP memory.." newline bitfld.long 0x20 9. "SPLOCK265,Sticky programming lock for word 265" "0: Fuse word 265 can be burnt in fuse memory array,1: Attempt to program fuse word 265 in OTP memory.." bitfld.long 0x20 8. "SPLOCK264,Sticky programming lock for word 264" "0: Fuse word 264 can be burnt in fuse memory array,1: Attempt to program fuse word 264 in OTP memory.." newline bitfld.long 0x20 7. "SPLOCK263,Sticky programming lock for word 263" "0: Fuse word 263 can be burnt in fuse memory array,1: Attempt to program fuse word 263 in OTP memory.." bitfld.long 0x20 6. "SPLOCK262,Sticky programming lock for word 262" "0: Fuse word 262 can be burnt in fuse memory array,1: Attempt to program fuse word 262 in OTP memory.." newline bitfld.long 0x20 5. "SPLOCK261,Sticky programming lock for word 261" "0: Fuse word 261 can be burnt in fuse memory array,1: Attempt to program fuse word 261 in OTP memory.." bitfld.long 0x20 4. "SPLOCK260,Sticky programming lock for word 260" "0: Fuse word 260 can be burnt in fuse memory array,1: Attempt to program fuse word 260 in OTP memory.." newline bitfld.long 0x20 3. "SPLOCK259,Sticky programming lock for word 259" "0: Fuse word 259 can be burnt in fuse memory array,1: Attempt to program fuse word 259 in OTP memory.." bitfld.long 0x20 2. "SPLOCK258,Sticky programming lock for word 258" "0: Fuse word 258 can be burnt in fuse memory array,1: Attempt to program fuse word 258 in OTP memory.." newline bitfld.long 0x20 1. "SPLOCK257,Sticky programming lock for word 257" "0: Fuse word 257 can be burnt in fuse memory array,1: Attempt to program fuse word 257 in OTP memory.." bitfld.long 0x20 0. "SPLOCK256,Sticky programming lock for word 256" "0: Fuse word 256 can be burnt in fuse memory array,1: Attempt to program fuse word 256 in OTP memory.." line.long 0x24 "BSEC_SPLOCK9,BSEC sticky programming lock register 9" bitfld.long 0x24 31. "SPLOCK319,Sticky programming lock for word 319" "0: Fuse word 319 can be burnt in fuse memory array,1: Attempt to program fuse word 319 in OTP memory.." bitfld.long 0x24 30. "SPLOCK318,Sticky programming lock for word 318" "0: Fuse word 318 can be burnt in fuse memory array,1: Attempt to program fuse word 318 in OTP memory.." newline bitfld.long 0x24 29. "SPLOCK317,Sticky programming lock for word 317" "0: Fuse word 317 can be burnt in fuse memory array,1: Attempt to program fuse word 317 in OTP memory.." bitfld.long 0x24 28. "SPLOCK316,Sticky programming lock for word 316" "0: Fuse word 316 can be burnt in fuse memory array,1: Attempt to program fuse word 316 in OTP memory.." newline bitfld.long 0x24 27. "SPLOCK315,Sticky programming lock for word 315" "0: Fuse word 315 can be burnt in fuse memory array,1: Attempt to program fuse word 315 in OTP memory.." bitfld.long 0x24 26. "SPLOCK314,Sticky programming lock for word 314" "0: Fuse word 314 can be burnt in fuse memory array,1: Attempt to program fuse word 314 in OTP memory.." newline bitfld.long 0x24 25. "SPLOCK313,Sticky programming lock for word 313" "0: Fuse word 313 can be burnt in fuse memory array,1: Attempt to program fuse word 313 in OTP memory.." bitfld.long 0x24 24. "SPLOCK312,Sticky programming lock for word 312" "0: Fuse word 312 can be burnt in fuse memory array,1: Attempt to program fuse word 312 in OTP memory.." newline bitfld.long 0x24 23. "SPLOCK311,Sticky programming lock for word 311" "0: Fuse word 311 can be burnt in fuse memory array,1: Attempt to program fuse word 311 in OTP memory.." bitfld.long 0x24 22. "SPLOCK310,Sticky programming lock for word 310" "0: Fuse word 310 can be burnt in fuse memory array,1: Attempt to program fuse word 310 in OTP memory.." newline bitfld.long 0x24 21. "SPLOCK309,Sticky programming lock for word 309" "0: Fuse word 309 can be burnt in fuse memory array,1: Attempt to program fuse word 309 in OTP memory.." bitfld.long 0x24 20. "SPLOCK308,Sticky programming lock for word 308" "0: Fuse word 308 can be burnt in fuse memory array,1: Attempt to program fuse word 308 in OTP memory.." newline bitfld.long 0x24 19. "SPLOCK307,Sticky programming lock for word 307" "0: Fuse word 307 can be burnt in fuse memory array,1: Attempt to program fuse word 307 in OTP memory.." bitfld.long 0x24 18. "SPLOCK306,Sticky programming lock for word 306" "0: Fuse word 306 can be burnt in fuse memory array,1: Attempt to program fuse word 306 in OTP memory.." newline bitfld.long 0x24 17. "SPLOCK305,Sticky programming lock for word 305" "0: Fuse word 305 can be burnt in fuse memory array,1: Attempt to program fuse word 305 in OTP memory.." bitfld.long 0x24 16. "SPLOCK304,Sticky programming lock for word 304" "0: Fuse word 304 can be burnt in fuse memory array,1: Attempt to program fuse word 304 in OTP memory.." newline bitfld.long 0x24 15. "SPLOCK303,Sticky programming lock for word 303" "0: Fuse word 303 can be burnt in fuse memory array,1: Attempt to program fuse word 303 in OTP memory.." bitfld.long 0x24 14. "SPLOCK302,Sticky programming lock for word 302" "0: Fuse word 302 can be burnt in fuse memory array,1: Attempt to program fuse word 302 in OTP memory.." newline bitfld.long 0x24 13. "SPLOCK301,Sticky programming lock for word 301" "0: Fuse word 301 can be burnt in fuse memory array,1: Attempt to program fuse word 301 in OTP memory.." bitfld.long 0x24 12. "SPLOCK300,Sticky programming lock for word 300" "0: Fuse word 300 can be burnt in fuse memory array,1: Attempt to program fuse word 300 in OTP memory.." newline bitfld.long 0x24 11. "SPLOCK299,Sticky programming lock for word 299" "0: Fuse word 299 can be burnt in fuse memory array,1: Attempt to program fuse word 299 in OTP memory.." bitfld.long 0x24 10. "SPLOCK298,Sticky programming lock for word 298" "0: Fuse word 298 can be burnt in fuse memory array,1: Attempt to program fuse word 298 in OTP memory.." newline bitfld.long 0x24 9. "SPLOCK297,Sticky programming lock for word 297" "0: Fuse word 297 can be burnt in fuse memory array,1: Attempt to program fuse word 297 in OTP memory.." bitfld.long 0x24 8. "SPLOCK296,Sticky programming lock for word 296" "0: Fuse word 296 can be burnt in fuse memory array,1: Attempt to program fuse word 296 in OTP memory.." newline bitfld.long 0x24 7. "SPLOCK295,Sticky programming lock for word 295" "0: Fuse word 295 can be burnt in fuse memory array,1: Attempt to program fuse word 295 in OTP memory.." bitfld.long 0x24 6. "SPLOCK294,Sticky programming lock for word 294" "0: Fuse word 294 can be burnt in fuse memory array,1: Attempt to program fuse word 294 in OTP memory.." newline bitfld.long 0x24 5. "SPLOCK293,Sticky programming lock for word 293" "0: Fuse word 293 can be burnt in fuse memory array,1: Attempt to program fuse word 293 in OTP memory.." bitfld.long 0x24 4. "SPLOCK292,Sticky programming lock for word 292" "0: Fuse word 292 can be burnt in fuse memory array,1: Attempt to program fuse word 292 in OTP memory.." newline bitfld.long 0x24 3. "SPLOCK291,Sticky programming lock for word 291" "0: Fuse word 291 can be burnt in fuse memory array,1: Attempt to program fuse word 291 in OTP memory.." bitfld.long 0x24 2. "SPLOCK290,Sticky programming lock for word 290" "0: Fuse word 290 can be burnt in fuse memory array,1: Attempt to program fuse word 290 in OTP memory.." newline bitfld.long 0x24 1. "SPLOCK289,Sticky programming lock for word 289" "0: Fuse word 289 can be burnt in fuse memory array,1: Attempt to program fuse word 289 in OTP memory.." bitfld.long 0x24 0. "SPLOCK288,Sticky programming lock for word 288" "0: Fuse word 288 can be burnt in fuse memory array,1: Attempt to program fuse word 288 in OTP memory.." line.long 0x28 "BSEC_SPLOCK10,BSEC sticky programming lock register 10" bitfld.long 0x28 31. "SPLOCK351,Sticky programming lock for word 351" "0: Fuse word 351 can be burnt in fuse memory array,1: Attempt to program fuse word 351 in OTP memory.." bitfld.long 0x28 30. "SPLOCK350,Sticky programming lock for word 350" "0: Fuse word 350 can be burnt in fuse memory array,1: Attempt to program fuse word 350 in OTP memory.." newline bitfld.long 0x28 29. "SPLOCK349,Sticky programming lock for word 349" "0: Fuse word 349 can be burnt in fuse memory array,1: Attempt to program fuse word 349 in OTP memory.." bitfld.long 0x28 28. "SPLOCK348,Sticky programming lock for word 348" "0: Fuse word 348 can be burnt in fuse memory array,1: Attempt to program fuse word 348 in OTP memory.." newline bitfld.long 0x28 27. "SPLOCK347,Sticky programming lock for word 347" "0: Fuse word 347 can be burnt in fuse memory array,1: Attempt to program fuse word 347 in OTP memory.." bitfld.long 0x28 26. "SPLOCK346,Sticky programming lock for word 346" "0: Fuse word 346 can be burnt in fuse memory array,1: Attempt to program fuse word 346 in OTP memory.." newline bitfld.long 0x28 25. "SPLOCK345,Sticky programming lock for word 345" "0: Fuse word 345 can be burnt in fuse memory array,1: Attempt to program fuse word 345 in OTP memory.." bitfld.long 0x28 24. "SPLOCK344,Sticky programming lock for word 344" "0: Fuse word 344 can be burnt in fuse memory array,1: Attempt to program fuse word 344 in OTP memory.." newline bitfld.long 0x28 23. "SPLOCK343,Sticky programming lock for word 343" "0: Fuse word 343 can be burnt in fuse memory array,1: Attempt to program fuse word 343 in OTP memory.." bitfld.long 0x28 22. "SPLOCK342,Sticky programming lock for word 342" "0: Fuse word 342 can be burnt in fuse memory array,1: Attempt to program fuse word 342 in OTP memory.." newline bitfld.long 0x28 21. "SPLOCK341,Sticky programming lock for word 341" "0: Fuse word 341 can be burnt in fuse memory array,1: Attempt to program fuse word 341 in OTP memory.." bitfld.long 0x28 20. "SPLOCK340,Sticky programming lock for word 340" "0: Fuse word 340 can be burnt in fuse memory array,1: Attempt to program fuse word 340 in OTP memory.." newline bitfld.long 0x28 19. "SPLOCK339,Sticky programming lock for word 339" "0: Fuse word 339 can be burnt in fuse memory array,1: Attempt to program fuse word 339 in OTP memory.." bitfld.long 0x28 18. "SPLOCK338,Sticky programming lock for word 338" "0: Fuse word 338 can be burnt in fuse memory array,1: Attempt to program fuse word 338 in OTP memory.." newline bitfld.long 0x28 17. "SPLOCK337,Sticky programming lock for word 337" "0: Fuse word 337 can be burnt in fuse memory array,1: Attempt to program fuse word 337 in OTP memory.." bitfld.long 0x28 16. "SPLOCK336,Sticky programming lock for word 336" "0: Fuse word 336 can be burnt in fuse memory array,1: Attempt to program fuse word 336 in OTP memory.." newline bitfld.long 0x28 15. "SPLOCK335,Sticky programming lock for word 335" "0: Fuse word 335 can be burnt in fuse memory array,1: Attempt to program fuse word 335 in OTP memory.." bitfld.long 0x28 14. "SPLOCK334,Sticky programming lock for word 334" "0: Fuse word 334 can be burnt in fuse memory array,1: Attempt to program fuse word 334 in OTP memory.." newline bitfld.long 0x28 13. "SPLOCK333,Sticky programming lock for word 333" "0: Fuse word 333 can be burnt in fuse memory array,1: Attempt to program fuse word 333 in OTP memory.." bitfld.long 0x28 12. "SPLOCK332,Sticky programming lock for word 332" "0: Fuse word 332 can be burnt in fuse memory array,1: Attempt to program fuse word 332 in OTP memory.." newline bitfld.long 0x28 11. "SPLOCK331,Sticky programming lock for word 331" "0: Fuse word 331 can be burnt in fuse memory array,1: Attempt to program fuse word 331 in OTP memory.." bitfld.long 0x28 10. "SPLOCK330,Sticky programming lock for word 330" "0: Fuse word 330 can be burnt in fuse memory array,1: Attempt to program fuse word 330 in OTP memory.." newline bitfld.long 0x28 9. "SPLOCK329,Sticky programming lock for word 329" "0: Fuse word 329 can be burnt in fuse memory array,1: Attempt to program fuse word 329 in OTP memory.." bitfld.long 0x28 8. "SPLOCK328,Sticky programming lock for word 328" "0: Fuse word 328 can be burnt in fuse memory array,1: Attempt to program fuse word 328 in OTP memory.." newline bitfld.long 0x28 7. "SPLOCK327,Sticky programming lock for word 327" "0: Fuse word 327 can be burnt in fuse memory array,1: Attempt to program fuse word 327 in OTP memory.." bitfld.long 0x28 6. "SPLOCK326,Sticky programming lock for word 326" "0: Fuse word 326 can be burnt in fuse memory array,1: Attempt to program fuse word 326 in OTP memory.." newline bitfld.long 0x28 5. "SPLOCK325,Sticky programming lock for word 325" "0: Fuse word 325 can be burnt in fuse memory array,1: Attempt to program fuse word 325 in OTP memory.." bitfld.long 0x28 4. "SPLOCK324,Sticky programming lock for word 324" "0: Fuse word 324 can be burnt in fuse memory array,1: Attempt to program fuse word 324 in OTP memory.." newline bitfld.long 0x28 3. "SPLOCK323,Sticky programming lock for word 323" "0: Fuse word 323 can be burnt in fuse memory array,1: Attempt to program fuse word 323 in OTP memory.." bitfld.long 0x28 2. "SPLOCK322,Sticky programming lock for word 322" "0: Fuse word 322 can be burnt in fuse memory array,1: Attempt to program fuse word 322 in OTP memory.." newline bitfld.long 0x28 1. "SPLOCK321,Sticky programming lock for word 321" "0: Fuse word 321 can be burnt in fuse memory array,1: Attempt to program fuse word 321 in OTP memory.." bitfld.long 0x28 0. "SPLOCK320,Sticky programming lock for word 320" "0: Fuse word 320 can be burnt in fuse memory array,1: Attempt to program fuse word 320 in OTP memory.." line.long 0x2C "BSEC_SPLOCK11,BSEC sticky programming lock register 11" bitfld.long 0x2C 31. "SPLOCK383,Sticky programming lock for word 383" "0: Fuse word 383 can be burnt in fuse memory array,1: Attempt to program fuse word 383 in OTP memory.." bitfld.long 0x2C 30. "SPLOCK382,Sticky programming lock for word 382" "0: Fuse word 382 can be burnt in fuse memory array,1: Attempt to program fuse word 382 in OTP memory.." newline bitfld.long 0x2C 29. "SPLOCK381,Sticky programming lock for word 381" "0: Fuse word 381 can be burnt in fuse memory array,1: Attempt to program fuse word 381 in OTP memory.." bitfld.long 0x2C 28. "SPLOCK380,Sticky programming lock for word 380" "0: Fuse word 380 can be burnt in fuse memory array,1: Attempt to program fuse word 380 in OTP memory.." newline bitfld.long 0x2C 27. "SPLOCK379,Sticky programming lock for word 379" "0: Fuse word 379 can be burnt in fuse memory array,1: Attempt to program fuse word 379 in OTP memory.." bitfld.long 0x2C 26. "SPLOCK378,Sticky programming lock for word 378" "0: Fuse word 378 can be burnt in fuse memory array,1: Attempt to program fuse word 378 in OTP memory.." newline bitfld.long 0x2C 25. "SPLOCK377,Sticky programming lock for word 377" "0: Fuse word 377 can be burnt in fuse memory array,1: Attempt to program fuse word 377 in OTP memory.." bitfld.long 0x2C 24. "SPLOCK376,Sticky programming lock for word 376" "0: Fuse word 376 can be burnt in fuse memory array,1: Attempt to program fuse word 376 in OTP memory.." newline bitfld.long 0x2C 23. "SPLOCK375,Sticky programming lock for word 375" "0: Fuse word 375 can be burnt in fuse memory array,1: Attempt to program fuse word 375 in OTP memory.." bitfld.long 0x2C 22. "SPLOCK374,Sticky programming lock for word 374" "0: Fuse word 374 can be burnt in fuse memory array,1: Attempt to program fuse word 374 in OTP memory.." newline bitfld.long 0x2C 21. "SPLOCK373,Sticky programming lock for word 373" "0: Fuse word 373 can be burnt in fuse memory array,1: Attempt to program fuse word 373 in OTP memory.." bitfld.long 0x2C 20. "SPLOCK372,Sticky programming lock for word 372" "0: Fuse word 372 can be burnt in fuse memory array,1: Attempt to program fuse word 372 in OTP memory.." newline bitfld.long 0x2C 19. "SPLOCK371,Sticky programming lock for word 371" "0: Fuse word 371 can be burnt in fuse memory array,1: Attempt to program fuse word 371 in OTP memory.." bitfld.long 0x2C 18. "SPLOCK370,Sticky programming lock for word 370" "0: Fuse word 370 can be burnt in fuse memory array,1: Attempt to program fuse word 370 in OTP memory.." newline bitfld.long 0x2C 17. "SPLOCK369,Sticky programming lock for word 369" "0: Fuse word 369 can be burnt in fuse memory array,1: Attempt to program fuse word 369 in OTP memory.." bitfld.long 0x2C 16. "SPLOCK368,Sticky programming lock for word 368" "0: Fuse word 368 can be burnt in fuse memory array,1: Attempt to program fuse word 368 in OTP memory.." newline bitfld.long 0x2C 15. "SPLOCK367,Sticky programming lock for word 367" "0: Fuse word 367 can be burnt in fuse memory array,1: Attempt to program fuse word 367 in OTP memory.." bitfld.long 0x2C 14. "SPLOCK366,Sticky programming lock for word 366" "0: Fuse word 366 can be burnt in fuse memory array,1: Attempt to program fuse word 366 in OTP memory.." newline bitfld.long 0x2C 13. "SPLOCK365,Sticky programming lock for word 365" "0: Fuse word 365 can be burnt in fuse memory array,1: Attempt to program fuse word 365 in OTP memory.." bitfld.long 0x2C 12. "SPLOCK364,Sticky programming lock for word 364" "0: Fuse word 364 can be burnt in fuse memory array,1: Attempt to program fuse word 364 in OTP memory.." newline bitfld.long 0x2C 11. "SPLOCK363,Sticky programming lock for word 363" "0: Fuse word 363 can be burnt in fuse memory array,1: Attempt to program fuse word 363 in OTP memory.." bitfld.long 0x2C 10. "SPLOCK362,Sticky programming lock for word 362" "0: Fuse word 362 can be burnt in fuse memory array,1: Attempt to program fuse word 362 in OTP memory.." newline bitfld.long 0x2C 9. "SPLOCK361,Sticky programming lock for word 361" "0: Fuse word 361 can be burnt in fuse memory array,1: Attempt to program fuse word 361 in OTP memory.." bitfld.long 0x2C 8. "SPLOCK360,Sticky programming lock for word 360" "0: Fuse word 360 can be burnt in fuse memory array,1: Attempt to program fuse word 360 in OTP memory.." newline bitfld.long 0x2C 7. "SPLOCK359,Sticky programming lock for word 359" "0: Fuse word 359 can be burnt in fuse memory array,1: Attempt to program fuse word 359 in OTP memory.." bitfld.long 0x2C 6. "SPLOCK358,Sticky programming lock for word 358" "0: Fuse word 358 can be burnt in fuse memory array,1: Attempt to program fuse word 358 in OTP memory.." newline bitfld.long 0x2C 5. "SPLOCK357,Sticky programming lock for word 357" "0: Fuse word 357 can be burnt in fuse memory array,1: Attempt to program fuse word 357 in OTP memory.." bitfld.long 0x2C 4. "SPLOCK356,Sticky programming lock for word 356" "0: Fuse word 356 can be burnt in fuse memory array,1: Attempt to program fuse word 356 in OTP memory.." newline bitfld.long 0x2C 3. "SPLOCK355,Sticky programming lock for word 355" "0: Fuse word 355 can be burnt in fuse memory array,1: Attempt to program fuse word 355 in OTP memory.." bitfld.long 0x2C 2. "SPLOCK354,Sticky programming lock for word 354" "0: Fuse word 354 can be burnt in fuse memory array,1: Attempt to program fuse word 354 in OTP memory.." newline bitfld.long 0x2C 1. "SPLOCK353,Sticky programming lock for word 353" "0: Fuse word 353 can be burnt in fuse memory array,1: Attempt to program fuse word 353 in OTP memory.." bitfld.long 0x2C 0. "SPLOCK352,Sticky programming lock for word 352" "0: Fuse word 352 can be burnt in fuse memory array,1: Attempt to program fuse word 352 in OTP memory.." group.long 0x840++0x2F line.long 0x0 "BSEC_SWLOCK0,BSEC sticky write lock register 0" bitfld.long 0x0 31. "SWLOCK31,sticky write lock for shadow register 31" "0: Write to shadow register BSEC_FVR31 is allowed,1: Writes to shadow register BSEC_FVR31 are.." bitfld.long 0x0 30. "SWLOCK30,sticky write lock for shadow register 30" "0: Write to shadow register BSEC_FVR30 is allowed,1: Writes to shadow register BSEC_FVR30 are.." newline bitfld.long 0x0 29. "SWLOCK29,sticky write lock for shadow register 29" "0: Write to shadow register BSEC_FVR29 is allowed,1: Writes to shadow register BSEC_FVR29 are.." bitfld.long 0x0 28. "SWLOCK28,sticky write lock for shadow register 28" "0: Write to shadow register BSEC_FVR28 is allowed,1: Writes to shadow register BSEC_FVR28 are.." newline bitfld.long 0x0 27. "SWLOCK27,sticky write lock for shadow register 27" "0: Write to shadow register BSEC_FVR27 is allowed,1: Writes to shadow register BSEC_FVR27 are.." bitfld.long 0x0 26. "SWLOCK26,sticky write lock for shadow register 26" "0: Write to shadow register BSEC_FVR26 is allowed,1: Writes to shadow register BSEC_FVR26 are.." newline bitfld.long 0x0 25. "SWLOCK25,sticky write lock for shadow register 25" "0: Write to shadow register BSEC_FVR25 is allowed,1: Writes to shadow register BSEC_FVR25 are.." bitfld.long 0x0 24. "SWLOCK24,sticky write lock for shadow register 24" "0: Write to shadow register BSEC_FVR24 is allowed,1: Writes to shadow register BSEC_FVR24 are.." newline bitfld.long 0x0 23. "SWLOCK23,sticky write lock for shadow register 23" "0: Write to shadow register BSEC_FVR23 is allowed,1: Writes to shadow register BSEC_FVR23 are.." bitfld.long 0x0 22. "SWLOCK22,sticky write lock for shadow register 22" "0: Write to shadow register BSEC_FVR22 is allowed,1: Writes to shadow register BSEC_FVR22 are.." newline bitfld.long 0x0 21. "SWLOCK21,sticky write lock for shadow register 21" "0: Write to shadow register BSEC_FVR21 is allowed,1: Writes to shadow register BSEC_FVR21 are.." bitfld.long 0x0 20. "SWLOCK20,sticky write lock for shadow register 20" "0: Write to shadow register BSEC_FVR20 is allowed,1: Writes to shadow register BSEC_FVR20 are.." newline bitfld.long 0x0 19. "SWLOCK19,sticky write lock for shadow register 19" "0: Write to shadow register BSEC_FVR19 is allowed,1: Writes to shadow register BSEC_FVR19 are.." bitfld.long 0x0 18. "SWLOCK18,sticky write lock for shadow register 18" "0: Write to shadow register BSEC_FVR18 is allowed,1: Writes to shadow register BSEC_FVR18 are.." newline bitfld.long 0x0 17. "SWLOCK17,sticky write lock for shadow register 17" "0: Write to shadow register BSEC_FVR17 is allowed,1: Writes to shadow register BSEC_FVR17 are.." bitfld.long 0x0 16. "SWLOCK16,sticky write lock for shadow register 16" "0: Write to shadow register BSEC_FVR16 is allowed,1: Writes to shadow register BSEC_FVR16 are.." newline bitfld.long 0x0 15. "SWLOCK15,sticky write lock for shadow register 15" "0: Write to shadow register BSEC_FVR15 is allowed,1: Writes to shadow register BSEC_FVR15 are.." bitfld.long 0x0 14. "SWLOCK14,sticky write lock for shadow register 14" "0: Write to shadow register BSEC_FVR14 is allowed,1: Writes to shadow register BSEC_FVR14 are.." newline bitfld.long 0x0 13. "SWLOCK13,sticky write lock for shadow register 13" "0: Write to shadow register BSEC_FVR13 is allowed,1: Writes to shadow register BSEC_FVR13 are.." bitfld.long 0x0 12. "SWLOCK12,sticky write lock for shadow register 12" "0: Write to shadow register BSEC_FVR12 is allowed,1: Writes to shadow register BSEC_FVR12 are.." newline bitfld.long 0x0 11. "SWLOCK11,sticky write lock for shadow register 11" "0: Write to shadow register BSEC_FVR11 is allowed,1: Writes to shadow register BSEC_FVR11 are.." bitfld.long 0x0 10. "SWLOCK10,sticky write lock for shadow register 10" "0: Write to shadow register BSEC_FVR10 is allowed,1: Writes to shadow register BSEC_FVR10 are.." newline bitfld.long 0x0 9. "SWLOCK9,sticky write lock for shadow register 9" "0: Write to shadow register BSEC_FVR9 is allowed,1: Writes to shadow register BSEC_FVR9 are silently.." bitfld.long 0x0 8. "SWLOCK8,sticky write lock for shadow register 8" "0: Write to shadow register BSEC_FVR8 is allowed,1: Writes to shadow register BSEC_FVR8 are silently.." newline bitfld.long 0x0 7. "SWLOCK7,sticky write lock for shadow register 7" "0: Write to shadow register BSEC_FVR7 is allowed,1: Writes to shadow register BSEC_FVR7 are silently.." bitfld.long 0x0 6. "SWLOCK6,sticky write lock for shadow register 6" "0: Write to shadow register BSEC_FVR6 is allowed,1: Writes to shadow register BSEC_FVR6 are silently.." newline bitfld.long 0x0 5. "SWLOCK5,sticky write lock for shadow register 5" "0: Write to shadow register BSEC_FVR5 is allowed,1: Writes to shadow register BSEC_FVR5 are silently.." bitfld.long 0x0 4. "SWLOCK4,sticky write lock for shadow register 4" "0: Write to shadow register BSEC_FVR4 is allowed,1: Writes to shadow register BSEC_FVR4 are silently.." newline bitfld.long 0x0 3. "SWLOCK3,sticky write lock for shadow register 3" "0: Write to shadow register BSEC_FVR3 is allowed,1: Writes to shadow register BSEC_FVR3 are silently.." bitfld.long 0x0 2. "SWLOCK2,sticky write lock for shadow register 2" "0: Write to shadow register BSEC_FVR2 is allowed,1: Writes to shadow register BSEC_FVR2 are silently.." newline bitfld.long 0x0 1. "SWLOCK1,sticky write lock for shadow register 1" "0: Write to shadow register BSEC_FVR1 is allowed,1: Writes to shadow register BSEC_FVR1 are silently.." bitfld.long 0x0 0. "SWLOCK0,sticky write lock for shadow register 0" "0: Write to shadow register BSEC_FVR0 is allowed,1: Writes to shadow register BSEC_FVR0 are silently.." line.long 0x4 "BSEC_SWLOCK1,BSEC sticky write lock register 1" bitfld.long 0x4 31. "SWLOCK63,sticky write lock for shadow register 63" "0: Write to shadow register BSEC_FVR63 is allowed,1: Writes to shadow register BSEC_FVR63 are.." bitfld.long 0x4 30. "SWLOCK62,sticky write lock for shadow register 62" "0: Write to shadow register BSEC_FVR62 is allowed,1: Writes to shadow register BSEC_FVR62 are.." newline bitfld.long 0x4 29. "SWLOCK61,sticky write lock for shadow register 61" "0: Write to shadow register BSEC_FVR61 is allowed,1: Writes to shadow register BSEC_FVR61 are.." bitfld.long 0x4 28. "SWLOCK60,sticky write lock for shadow register 60" "0: Write to shadow register BSEC_FVR60 is allowed,1: Writes to shadow register BSEC_FVR60 are.." newline bitfld.long 0x4 27. "SWLOCK59,sticky write lock for shadow register 59" "0: Write to shadow register BSEC_FVR59 is allowed,1: Writes to shadow register BSEC_FVR59 are.." bitfld.long 0x4 26. "SWLOCK58,sticky write lock for shadow register 58" "0: Write to shadow register BSEC_FVR58 is allowed,1: Writes to shadow register BSEC_FVR58 are.." newline bitfld.long 0x4 25. "SWLOCK57,sticky write lock for shadow register 57" "0: Write to shadow register BSEC_FVR57 is allowed,1: Writes to shadow register BSEC_FVR57 are.." bitfld.long 0x4 24. "SWLOCK56,sticky write lock for shadow register 56" "0: Write to shadow register BSEC_FVR56 is allowed,1: Writes to shadow register BSEC_FVR56 are.." newline bitfld.long 0x4 23. "SWLOCK55,sticky write lock for shadow register 55" "0: Write to shadow register BSEC_FVR55 is allowed,1: Writes to shadow register BSEC_FVR55 are.." bitfld.long 0x4 22. "SWLOCK54,sticky write lock for shadow register 54" "0: Write to shadow register BSEC_FVR54 is allowed,1: Writes to shadow register BSEC_FVR54 are.." newline bitfld.long 0x4 21. "SWLOCK53,sticky write lock for shadow register 53" "0: Write to shadow register BSEC_FVR53 is allowed,1: Writes to shadow register BSEC_FVR53 are.." bitfld.long 0x4 20. "SWLOCK52,sticky write lock for shadow register 52" "0: Write to shadow register BSEC_FVR52 is allowed,1: Writes to shadow register BSEC_FVR52 are.." newline bitfld.long 0x4 19. "SWLOCK51,sticky write lock for shadow register 51" "0: Write to shadow register BSEC_FVR51 is allowed,1: Writes to shadow register BSEC_FVR51 are.." bitfld.long 0x4 18. "SWLOCK50,sticky write lock for shadow register 50" "0: Write to shadow register BSEC_FVR50 is allowed,1: Writes to shadow register BSEC_FVR50 are.." newline bitfld.long 0x4 17. "SWLOCK49,sticky write lock for shadow register 49" "0: Write to shadow register BSEC_FVR49 is allowed,1: Writes to shadow register BSEC_FVR49 are.." bitfld.long 0x4 16. "SWLOCK48,sticky write lock for shadow register 48" "0: Write to shadow register BSEC_FVR48 is allowed,1: Writes to shadow register BSEC_FVR48 are.." newline bitfld.long 0x4 15. "SWLOCK47,sticky write lock for shadow register 47" "0: Write to shadow register BSEC_FVR47 is allowed,1: Writes to shadow register BSEC_FVR47 are.." bitfld.long 0x4 14. "SWLOCK46,sticky write lock for shadow register 46" "0: Write to shadow register BSEC_FVR46 is allowed,1: Writes to shadow register BSEC_FVR46 are.." newline bitfld.long 0x4 13. "SWLOCK45,sticky write lock for shadow register 45" "0: Write to shadow register BSEC_FVR45 is allowed,1: Writes to shadow register BSEC_FVR45 are.." bitfld.long 0x4 12. "SWLOCK44,sticky write lock for shadow register 44" "0: Write to shadow register BSEC_FVR44 is allowed,1: Writes to shadow register BSEC_FVR44 are.." newline bitfld.long 0x4 11. "SWLOCK43,sticky write lock for shadow register 43" "0: Write to shadow register BSEC_FVR43 is allowed,1: Writes to shadow register BSEC_FVR43 are.." bitfld.long 0x4 10. "SWLOCK42,sticky write lock for shadow register 42" "0: Write to shadow register BSEC_FVR42 is allowed,1: Writes to shadow register BSEC_FVR42 are.." newline bitfld.long 0x4 9. "SWLOCK41,sticky write lock for shadow register 41" "0: Write to shadow register BSEC_FVR41 is allowed,1: Writes to shadow register BSEC_FVR41 are.." bitfld.long 0x4 8. "SWLOCK40,sticky write lock for shadow register 40" "0: Write to shadow register BSEC_FVR40 is allowed,1: Writes to shadow register BSEC_FVR40 are.." newline bitfld.long 0x4 7. "SWLOCK39,sticky write lock for shadow register 39" "0: Write to shadow register BSEC_FVR39 is allowed,1: Writes to shadow register BSEC_FVR39 are.." bitfld.long 0x4 6. "SWLOCK38,sticky write lock for shadow register 38" "0: Write to shadow register BSEC_FVR38 is allowed,1: Writes to shadow register BSEC_FVR38 are.." newline bitfld.long 0x4 5. "SWLOCK37,sticky write lock for shadow register 37" "0: Write to shadow register BSEC_FVR37 is allowed,1: Writes to shadow register BSEC_FVR37 are.." bitfld.long 0x4 4. "SWLOCK36,sticky write lock for shadow register 36" "0: Write to shadow register BSEC_FVR36 is allowed,1: Writes to shadow register BSEC_FVR36 are.." newline bitfld.long 0x4 3. "SWLOCK35,sticky write lock for shadow register 35" "0: Write to shadow register BSEC_FVR35 is allowed,1: Writes to shadow register BSEC_FVR35 are.." bitfld.long 0x4 2. "SWLOCK34,sticky write lock for shadow register 34" "0: Write to shadow register BSEC_FVR34 is allowed,1: Writes to shadow register BSEC_FVR34 are.." newline bitfld.long 0x4 1. "SWLOCK33,sticky write lock for shadow register 33" "0: Write to shadow register BSEC_FVR33 is allowed,1: Writes to shadow register BSEC_FVR33 are.." bitfld.long 0x4 0. "SWLOCK32,sticky write lock for shadow register 32" "0: Write to shadow register BSEC_FVR32 is allowed,1: Writes to shadow register BSEC_FVR32 are.." line.long 0x8 "BSEC_SWLOCK2,BSEC sticky write lock register 2" bitfld.long 0x8 31. "SWLOCK95,sticky write lock for shadow register 95" "0: Write to shadow register BSEC_FVR95 is allowed,1: Writes to shadow register BSEC_FVR95 are.." bitfld.long 0x8 30. "SWLOCK94,sticky write lock for shadow register 94" "0: Write to shadow register BSEC_FVR94 is allowed,1: Writes to shadow register BSEC_FVR94 are.." newline bitfld.long 0x8 29. "SWLOCK93,sticky write lock for shadow register 93" "0: Write to shadow register BSEC_FVR93 is allowed,1: Writes to shadow register BSEC_FVR93 are.." bitfld.long 0x8 28. "SWLOCK92,sticky write lock for shadow register 92" "0: Write to shadow register BSEC_FVR92 is allowed,1: Writes to shadow register BSEC_FVR92 are.." newline bitfld.long 0x8 27. "SWLOCK91,sticky write lock for shadow register 91" "0: Write to shadow register BSEC_FVR91 is allowed,1: Writes to shadow register BSEC_FVR91 are.." bitfld.long 0x8 26. "SWLOCK90,sticky write lock for shadow register 90" "0: Write to shadow register BSEC_FVR90 is allowed,1: Writes to shadow register BSEC_FVR90 are.." newline bitfld.long 0x8 25. "SWLOCK89,sticky write lock for shadow register 89" "0: Write to shadow register BSEC_FVR89 is allowed,1: Writes to shadow register BSEC_FVR89 are.." bitfld.long 0x8 24. "SWLOCK88,sticky write lock for shadow register 88" "0: Write to shadow register BSEC_FVR88 is allowed,1: Writes to shadow register BSEC_FVR88 are.." newline bitfld.long 0x8 23. "SWLOCK87,sticky write lock for shadow register 87" "0: Write to shadow register BSEC_FVR87 is allowed,1: Writes to shadow register BSEC_FVR87 are.." bitfld.long 0x8 22. "SWLOCK86,sticky write lock for shadow register 86" "0: Write to shadow register BSEC_FVR86 is allowed,1: Writes to shadow register BSEC_FVR86 are.." newline bitfld.long 0x8 21. "SWLOCK85,sticky write lock for shadow register 85" "0: Write to shadow register BSEC_FVR85 is allowed,1: Writes to shadow register BSEC_FVR85 are.." bitfld.long 0x8 20. "SWLOCK84,sticky write lock for shadow register 84" "0: Write to shadow register BSEC_FVR84 is allowed,1: Writes to shadow register BSEC_FVR84 are.." newline bitfld.long 0x8 19. "SWLOCK83,sticky write lock for shadow register 83" "0: Write to shadow register BSEC_FVR83 is allowed,1: Writes to shadow register BSEC_FVR83 are.." bitfld.long 0x8 18. "SWLOCK82,sticky write lock for shadow register 82" "0: Write to shadow register BSEC_FVR82 is allowed,1: Writes to shadow register BSEC_FVR82 are.." newline bitfld.long 0x8 17. "SWLOCK81,sticky write lock for shadow register 81" "0: Write to shadow register BSEC_FVR81 is allowed,1: Writes to shadow register BSEC_FVR81 are.." bitfld.long 0x8 16. "SWLOCK80,sticky write lock for shadow register 80" "0: Write to shadow register BSEC_FVR80 is allowed,1: Writes to shadow register BSEC_FVR80 are.." newline bitfld.long 0x8 15. "SWLOCK79,sticky write lock for shadow register 79" "0: Write to shadow register BSEC_FVR79 is allowed,1: Writes to shadow register BSEC_FVR79 are.." bitfld.long 0x8 14. "SWLOCK78,sticky write lock for shadow register 78" "0: Write to shadow register BSEC_FVR78 is allowed,1: Writes to shadow register BSEC_FVR78 are.." newline bitfld.long 0x8 13. "SWLOCK77,sticky write lock for shadow register 77" "0: Write to shadow register BSEC_FVR77 is allowed,1: Writes to shadow register BSEC_FVR77 are.." bitfld.long 0x8 12. "SWLOCK76,sticky write lock for shadow register 76" "0: Write to shadow register BSEC_FVR76 is allowed,1: Writes to shadow register BSEC_FVR76 are.." newline bitfld.long 0x8 11. "SWLOCK75,sticky write lock for shadow register 75" "0: Write to shadow register BSEC_FVR75 is allowed,1: Writes to shadow register BSEC_FVR75 are.." bitfld.long 0x8 10. "SWLOCK74,sticky write lock for shadow register 74" "0: Write to shadow register BSEC_FVR74 is allowed,1: Writes to shadow register BSEC_FVR74 are.." newline bitfld.long 0x8 9. "SWLOCK73,sticky write lock for shadow register 73" "0: Write to shadow register BSEC_FVR73 is allowed,1: Writes to shadow register BSEC_FVR73 are.." bitfld.long 0x8 8. "SWLOCK72,sticky write lock for shadow register 72" "0: Write to shadow register BSEC_FVR72 is allowed,1: Writes to shadow register BSEC_FVR72 are.." newline bitfld.long 0x8 7. "SWLOCK71,sticky write lock for shadow register 71" "0: Write to shadow register BSEC_FVR71 is allowed,1: Writes to shadow register BSEC_FVR71 are.." bitfld.long 0x8 6. "SWLOCK70,sticky write lock for shadow register 70" "0: Write to shadow register BSEC_FVR70 is allowed,1: Writes to shadow register BSEC_FVR70 are.." newline bitfld.long 0x8 5. "SWLOCK69,sticky write lock for shadow register 69" "0: Write to shadow register BSEC_FVR69 is allowed,1: Writes to shadow register BSEC_FVR69 are.." bitfld.long 0x8 4. "SWLOCK68,sticky write lock for shadow register 68" "0: Write to shadow register BSEC_FVR68 is allowed,1: Writes to shadow register BSEC_FVR68 are.." newline bitfld.long 0x8 3. "SWLOCK67,sticky write lock for shadow register 67" "0: Write to shadow register BSEC_FVR67 is allowed,1: Writes to shadow register BSEC_FVR67 are.." bitfld.long 0x8 2. "SWLOCK66,sticky write lock for shadow register 66" "0: Write to shadow register BSEC_FVR66 is allowed,1: Writes to shadow register BSEC_FVR66 are.." newline bitfld.long 0x8 1. "SWLOCK65,sticky write lock for shadow register 65" "0: Write to shadow register BSEC_FVR65 is allowed,1: Writes to shadow register BSEC_FVR65 are.." bitfld.long 0x8 0. "SWLOCK64,sticky write lock for shadow register 64" "0: Write to shadow register BSEC_FVR64 is allowed,1: Writes to shadow register BSEC_FVR64 are.." line.long 0xC "BSEC_SWLOCK3,BSEC sticky write lock register 3" bitfld.long 0xC 31. "SWLOCK127,sticky write lock for shadow register 127" "0: Write to shadow register BSEC_FVR127 is allowed,1: Writes to shadow register BSEC_FVR127 are.." bitfld.long 0xC 30. "SWLOCK126,sticky write lock for shadow register 126" "0: Write to shadow register BSEC_FVR126 is allowed,1: Writes to shadow register BSEC_FVR126 are.." newline bitfld.long 0xC 29. "SWLOCK125,sticky write lock for shadow register 125" "0: Write to shadow register BSEC_FVR125 is allowed,1: Writes to shadow register BSEC_FVR125 are.." bitfld.long 0xC 28. "SWLOCK124,sticky write lock for shadow register 124" "0: Write to shadow register BSEC_FVR124 is allowed,1: Writes to shadow register BSEC_FVR124 are.." newline bitfld.long 0xC 27. "SWLOCK123,sticky write lock for shadow register 123" "0: Write to shadow register BSEC_FVR123 is allowed,1: Writes to shadow register BSEC_FVR123 are.." bitfld.long 0xC 26. "SWLOCK122,sticky write lock for shadow register 122" "0: Write to shadow register BSEC_FVR122 is allowed,1: Writes to shadow register BSEC_FVR122 are.." newline bitfld.long 0xC 25. "SWLOCK121,sticky write lock for shadow register 121" "0: Write to shadow register BSEC_FVR121 is allowed,1: Writes to shadow register BSEC_FVR121 are.." bitfld.long 0xC 24. "SWLOCK120,sticky write lock for shadow register 120" "0: Write to shadow register BSEC_FVR120 is allowed,1: Writes to shadow register BSEC_FVR120 are.." newline bitfld.long 0xC 23. "SWLOCK119,sticky write lock for shadow register 119" "0: Write to shadow register BSEC_FVR119 is allowed,1: Writes to shadow register BSEC_FVR119 are.." bitfld.long 0xC 22. "SWLOCK118,sticky write lock for shadow register 118" "0: Write to shadow register BSEC_FVR118 is allowed,1: Writes to shadow register BSEC_FVR118 are.." newline bitfld.long 0xC 21. "SWLOCK117,sticky write lock for shadow register 117" "0: Write to shadow register BSEC_FVR117 is allowed,1: Writes to shadow register BSEC_FVR117 are.." bitfld.long 0xC 20. "SWLOCK116,sticky write lock for shadow register 116" "0: Write to shadow register BSEC_FVR116 is allowed,1: Writes to shadow register BSEC_FVR116 are.." newline bitfld.long 0xC 19. "SWLOCK115,sticky write lock for shadow register 115" "0: Write to shadow register BSEC_FVR115 is allowed,1: Writes to shadow register BSEC_FVR115 are.." bitfld.long 0xC 18. "SWLOCK114,sticky write lock for shadow register 114" "0: Write to shadow register BSEC_FVR114 is allowed,1: Writes to shadow register BSEC_FVR114 are.." newline bitfld.long 0xC 17. "SWLOCK113,sticky write lock for shadow register 113" "0: Write to shadow register BSEC_FVR113 is allowed,1: Writes to shadow register BSEC_FVR113 are.." bitfld.long 0xC 16. "SWLOCK112,sticky write lock for shadow register 112" "0: Write to shadow register BSEC_FVR112 is allowed,1: Writes to shadow register BSEC_FVR112 are.." newline bitfld.long 0xC 15. "SWLOCK111,sticky write lock for shadow register 111" "0: Write to shadow register BSEC_FVR111 is allowed,1: Writes to shadow register BSEC_FVR111 are.." bitfld.long 0xC 14. "SWLOCK110,sticky write lock for shadow register 110" "0: Write to shadow register BSEC_FVR110 is allowed,1: Writes to shadow register BSEC_FVR110 are.." newline bitfld.long 0xC 13. "SWLOCK109,sticky write lock for shadow register 109" "0: Write to shadow register BSEC_FVR109 is allowed,1: Writes to shadow register BSEC_FVR109 are.." bitfld.long 0xC 12. "SWLOCK108,sticky write lock for shadow register 108" "0: Write to shadow register BSEC_FVR108 is allowed,1: Writes to shadow register BSEC_FVR108 are.." newline bitfld.long 0xC 11. "SWLOCK107,sticky write lock for shadow register 107" "0: Write to shadow register BSEC_FVR107 is allowed,1: Writes to shadow register BSEC_FVR107 are.." bitfld.long 0xC 10. "SWLOCK106,sticky write lock for shadow register 106" "0: Write to shadow register BSEC_FVR106 is allowed,1: Writes to shadow register BSEC_FVR106 are.." newline bitfld.long 0xC 9. "SWLOCK105,sticky write lock for shadow register 105" "0: Write to shadow register BSEC_FVR105 is allowed,1: Writes to shadow register BSEC_FVR105 are.." bitfld.long 0xC 8. "SWLOCK104,sticky write lock for shadow register 104" "0: Write to shadow register BSEC_FVR104 is allowed,1: Writes to shadow register BSEC_FVR104 are.." newline bitfld.long 0xC 7. "SWLOCK103,sticky write lock for shadow register 103" "0: Write to shadow register BSEC_FVR103 is allowed,1: Writes to shadow register BSEC_FVR103 are.." bitfld.long 0xC 6. "SWLOCK102,sticky write lock for shadow register 102" "0: Write to shadow register BSEC_FVR102 is allowed,1: Writes to shadow register BSEC_FVR102 are.." newline bitfld.long 0xC 5. "SWLOCK101,sticky write lock for shadow register 101" "0: Write to shadow register BSEC_FVR101 is allowed,1: Writes to shadow register BSEC_FVR101 are.." bitfld.long 0xC 4. "SWLOCK100,sticky write lock for shadow register 100" "0: Write to shadow register BSEC_FVR100 is allowed,1: Writes to shadow register BSEC_FVR100 are.." newline bitfld.long 0xC 3. "SWLOCK99,sticky write lock for shadow register 99" "0: Write to shadow register BSEC_FVR99 is allowed,1: Writes to shadow register BSEC_FVR99 are.." bitfld.long 0xC 2. "SWLOCK98,sticky write lock for shadow register 98" "0: Write to shadow register BSEC_FVR98 is allowed,1: Writes to shadow register BSEC_FVR98 are.." newline bitfld.long 0xC 1. "SWLOCK97,sticky write lock for shadow register 97" "0: Write to shadow register BSEC_FVR97 is allowed,1: Writes to shadow register BSEC_FVR97 are.." bitfld.long 0xC 0. "SWLOCK96,sticky write lock for shadow register 96" "0: Write to shadow register BSEC_FVR96 is allowed,1: Writes to shadow register BSEC_FVR96 are.." line.long 0x10 "BSEC_SWLOCK4,BSEC sticky write lock register 4" bitfld.long 0x10 31. "SWLOCK159,sticky write lock for shadow register 159" "0: Write to shadow register BSEC_FVR159 is allowed,1: Writes to shadow register BSEC_FVR159 are.." bitfld.long 0x10 30. "SWLOCK158,sticky write lock for shadow register 158" "0: Write to shadow register BSEC_FVR158 is allowed,1: Writes to shadow register BSEC_FVR158 are.." newline bitfld.long 0x10 29. "SWLOCK157,sticky write lock for shadow register 157" "0: Write to shadow register BSEC_FVR157 is allowed,1: Writes to shadow register BSEC_FVR157 are.." bitfld.long 0x10 28. "SWLOCK156,sticky write lock for shadow register 156" "0: Write to shadow register BSEC_FVR156 is allowed,1: Writes to shadow register BSEC_FVR156 are.." newline bitfld.long 0x10 27. "SWLOCK155,sticky write lock for shadow register 155" "0: Write to shadow register BSEC_FVR155 is allowed,1: Writes to shadow register BSEC_FVR155 are.." bitfld.long 0x10 26. "SWLOCK154,sticky write lock for shadow register 154" "0: Write to shadow register BSEC_FVR154 is allowed,1: Writes to shadow register BSEC_FVR154 are.." newline bitfld.long 0x10 25. "SWLOCK153,sticky write lock for shadow register 153" "0: Write to shadow register BSEC_FVR153 is allowed,1: Writes to shadow register BSEC_FVR153 are.." bitfld.long 0x10 24. "SWLOCK152,sticky write lock for shadow register 152" "0: Write to shadow register BSEC_FVR152 is allowed,1: Writes to shadow register BSEC_FVR152 are.." newline bitfld.long 0x10 23. "SWLOCK151,sticky write lock for shadow register 151" "0: Write to shadow register BSEC_FVR151 is allowed,1: Writes to shadow register BSEC_FVR151 are.." bitfld.long 0x10 22. "SWLOCK150,sticky write lock for shadow register 150" "0: Write to shadow register BSEC_FVR150 is allowed,1: Writes to shadow register BSEC_FVR150 are.." newline bitfld.long 0x10 21. "SWLOCK149,sticky write lock for shadow register 149" "0: Write to shadow register BSEC_FVR149 is allowed,1: Writes to shadow register BSEC_FVR149 are.." bitfld.long 0x10 20. "SWLOCK148,sticky write lock for shadow register 148" "0: Write to shadow register BSEC_FVR148 is allowed,1: Writes to shadow register BSEC_FVR148 are.." newline bitfld.long 0x10 19. "SWLOCK147,sticky write lock for shadow register 147" "0: Write to shadow register BSEC_FVR147 is allowed,1: Writes to shadow register BSEC_FVR147 are.." bitfld.long 0x10 18. "SWLOCK146,sticky write lock for shadow register 146" "0: Write to shadow register BSEC_FVR146 is allowed,1: Writes to shadow register BSEC_FVR146 are.." newline bitfld.long 0x10 17. "SWLOCK145,sticky write lock for shadow register 145" "0: Write to shadow register BSEC_FVR145 is allowed,1: Writes to shadow register BSEC_FVR145 are.." bitfld.long 0x10 16. "SWLOCK144,sticky write lock for shadow register 144" "0: Write to shadow register BSEC_FVR144 is allowed,1: Writes to shadow register BSEC_FVR144 are.." newline bitfld.long 0x10 15. "SWLOCK143,sticky write lock for shadow register 143" "0: Write to shadow register BSEC_FVR143 is allowed,1: Writes to shadow register BSEC_FVR143 are.." bitfld.long 0x10 14. "SWLOCK142,sticky write lock for shadow register 142" "0: Write to shadow register BSEC_FVR142 is allowed,1: Writes to shadow register BSEC_FVR142 are.." newline bitfld.long 0x10 13. "SWLOCK141,sticky write lock for shadow register 141" "0: Write to shadow register BSEC_FVR141 is allowed,1: Writes to shadow register BSEC_FVR141 are.." bitfld.long 0x10 12. "SWLOCK140,sticky write lock for shadow register 140" "0: Write to shadow register BSEC_FVR140 is allowed,1: Writes to shadow register BSEC_FVR140 are.." newline bitfld.long 0x10 11. "SWLOCK139,sticky write lock for shadow register 139" "0: Write to shadow register BSEC_FVR139 is allowed,1: Writes to shadow register BSEC_FVR139 are.." bitfld.long 0x10 10. "SWLOCK138,sticky write lock for shadow register 138" "0: Write to shadow register BSEC_FVR138 is allowed,1: Writes to shadow register BSEC_FVR138 are.." newline bitfld.long 0x10 9. "SWLOCK137,sticky write lock for shadow register 137" "0: Write to shadow register BSEC_FVR137 is allowed,1: Writes to shadow register BSEC_FVR137 are.." bitfld.long 0x10 8. "SWLOCK136,sticky write lock for shadow register 136" "0: Write to shadow register BSEC_FVR136 is allowed,1: Writes to shadow register BSEC_FVR136 are.." newline bitfld.long 0x10 7. "SWLOCK135,sticky write lock for shadow register 135" "0: Write to shadow register BSEC_FVR135 is allowed,1: Writes to shadow register BSEC_FVR135 are.." bitfld.long 0x10 6. "SWLOCK134,sticky write lock for shadow register 134" "0: Write to shadow register BSEC_FVR134 is allowed,1: Writes to shadow register BSEC_FVR134 are.." newline bitfld.long 0x10 5. "SWLOCK133,sticky write lock for shadow register 133" "0: Write to shadow register BSEC_FVR133 is allowed,1: Writes to shadow register BSEC_FVR133 are.." bitfld.long 0x10 4. "SWLOCK132,sticky write lock for shadow register 132" "0: Write to shadow register BSEC_FVR132 is allowed,1: Writes to shadow register BSEC_FVR132 are.." newline bitfld.long 0x10 3. "SWLOCK131,sticky write lock for shadow register 131" "0: Write to shadow register BSEC_FVR131 is allowed,1: Writes to shadow register BSEC_FVR131 are.." bitfld.long 0x10 2. "SWLOCK130,sticky write lock for shadow register 130" "0: Write to shadow register BSEC_FVR130 is allowed,1: Writes to shadow register BSEC_FVR130 are.." newline bitfld.long 0x10 1. "SWLOCK129,sticky write lock for shadow register 129" "0: Write to shadow register BSEC_FVR129 is allowed,1: Writes to shadow register BSEC_FVR129 are.." bitfld.long 0x10 0. "SWLOCK128,sticky write lock for shadow register 128" "0: Write to shadow register BSEC_FVR128 is allowed,1: Writes to shadow register BSEC_FVR128 are.." line.long 0x14 "BSEC_SWLOCK5,BSEC sticky write lock register 5" bitfld.long 0x14 31. "SWLOCK191,sticky write lock for shadow register 191" "0: Write to shadow register BSEC_FVR191 is allowed,1: Writes to shadow register BSEC_FVR191 are.." bitfld.long 0x14 30. "SWLOCK190,sticky write lock for shadow register 190" "0: Write to shadow register BSEC_FVR190 is allowed,1: Writes to shadow register BSEC_FVR190 are.." newline bitfld.long 0x14 29. "SWLOCK189,sticky write lock for shadow register 189" "0: Write to shadow register BSEC_FVR189 is allowed,1: Writes to shadow register BSEC_FVR189 are.." bitfld.long 0x14 28. "SWLOCK188,sticky write lock for shadow register 188" "0: Write to shadow register BSEC_FVR188 is allowed,1: Writes to shadow register BSEC_FVR188 are.." newline bitfld.long 0x14 27. "SWLOCK187,sticky write lock for shadow register 187" "0: Write to shadow register BSEC_FVR187 is allowed,1: Writes to shadow register BSEC_FVR187 are.." bitfld.long 0x14 26. "SWLOCK186,sticky write lock for shadow register 186" "0: Write to shadow register BSEC_FVR186 is allowed,1: Writes to shadow register BSEC_FVR186 are.." newline bitfld.long 0x14 25. "SWLOCK185,sticky write lock for shadow register 185" "0: Write to shadow register BSEC_FVR185 is allowed,1: Writes to shadow register BSEC_FVR185 are.." bitfld.long 0x14 24. "SWLOCK184,sticky write lock for shadow register 184" "0: Write to shadow register BSEC_FVR184 is allowed,1: Writes to shadow register BSEC_FVR184 are.." newline bitfld.long 0x14 23. "SWLOCK183,sticky write lock for shadow register 183" "0: Write to shadow register BSEC_FVR183 is allowed,1: Writes to shadow register BSEC_FVR183 are.." bitfld.long 0x14 22. "SWLOCK182,sticky write lock for shadow register 182" "0: Write to shadow register BSEC_FVR182 is allowed,1: Writes to shadow register BSEC_FVR182 are.." newline bitfld.long 0x14 21. "SWLOCK181,sticky write lock for shadow register 181" "0: Write to shadow register BSEC_FVR181 is allowed,1: Writes to shadow register BSEC_FVR181 are.." bitfld.long 0x14 20. "SWLOCK180,sticky write lock for shadow register 180" "0: Write to shadow register BSEC_FVR180 is allowed,1: Writes to shadow register BSEC_FVR180 are.." newline bitfld.long 0x14 19. "SWLOCK179,sticky write lock for shadow register 179" "0: Write to shadow register BSEC_FVR179 is allowed,1: Writes to shadow register BSEC_FVR179 are.." bitfld.long 0x14 18. "SWLOCK178,sticky write lock for shadow register 178" "0: Write to shadow register BSEC_FVR178 is allowed,1: Writes to shadow register BSEC_FVR178 are.." newline bitfld.long 0x14 17. "SWLOCK177,sticky write lock for shadow register 177" "0: Write to shadow register BSEC_FVR177 is allowed,1: Writes to shadow register BSEC_FVR177 are.." bitfld.long 0x14 16. "SWLOCK176,sticky write lock for shadow register 176" "0: Write to shadow register BSEC_FVR176 is allowed,1: Writes to shadow register BSEC_FVR176 are.." newline bitfld.long 0x14 15. "SWLOCK175,sticky write lock for shadow register 175" "0: Write to shadow register BSEC_FVR175 is allowed,1: Writes to shadow register BSEC_FVR175 are.." bitfld.long 0x14 14. "SWLOCK174,sticky write lock for shadow register 174" "0: Write to shadow register BSEC_FVR174 is allowed,1: Writes to shadow register BSEC_FVR174 are.." newline bitfld.long 0x14 13. "SWLOCK173,sticky write lock for shadow register 173" "0: Write to shadow register BSEC_FVR173 is allowed,1: Writes to shadow register BSEC_FVR173 are.." bitfld.long 0x14 12. "SWLOCK172,sticky write lock for shadow register 172" "0: Write to shadow register BSEC_FVR172 is allowed,1: Writes to shadow register BSEC_FVR172 are.." newline bitfld.long 0x14 11. "SWLOCK171,sticky write lock for shadow register 171" "0: Write to shadow register BSEC_FVR171 is allowed,1: Writes to shadow register BSEC_FVR171 are.." bitfld.long 0x14 10. "SWLOCK170,sticky write lock for shadow register 170" "0: Write to shadow register BSEC_FVR170 is allowed,1: Writes to shadow register BSEC_FVR170 are.." newline bitfld.long 0x14 9. "SWLOCK169,sticky write lock for shadow register 169" "0: Write to shadow register BSEC_FVR169 is allowed,1: Writes to shadow register BSEC_FVR169 are.." bitfld.long 0x14 8. "SWLOCK168,sticky write lock for shadow register 168" "0: Write to shadow register BSEC_FVR168 is allowed,1: Writes to shadow register BSEC_FVR168 are.." newline bitfld.long 0x14 7. "SWLOCK167,sticky write lock for shadow register 167" "0: Write to shadow register BSEC_FVR167 is allowed,1: Writes to shadow register BSEC_FVR167 are.." bitfld.long 0x14 6. "SWLOCK166,sticky write lock for shadow register 166" "0: Write to shadow register BSEC_FVR166 is allowed,1: Writes to shadow register BSEC_FVR166 are.." newline bitfld.long 0x14 5. "SWLOCK165,sticky write lock for shadow register 165" "0: Write to shadow register BSEC_FVR165 is allowed,1: Writes to shadow register BSEC_FVR165 are.." bitfld.long 0x14 4. "SWLOCK164,sticky write lock for shadow register 164" "0: Write to shadow register BSEC_FVR164 is allowed,1: Writes to shadow register BSEC_FVR164 are.." newline bitfld.long 0x14 3. "SWLOCK163,sticky write lock for shadow register 163" "0: Write to shadow register BSEC_FVR163 is allowed,1: Writes to shadow register BSEC_FVR163 are.." bitfld.long 0x14 2. "SWLOCK162,sticky write lock for shadow register 162" "0: Write to shadow register BSEC_FVR162 is allowed,1: Writes to shadow register BSEC_FVR162 are.." newline bitfld.long 0x14 1. "SWLOCK161,sticky write lock for shadow register 161" "0: Write to shadow register BSEC_FVR161 is allowed,1: Writes to shadow register BSEC_FVR161 are.." bitfld.long 0x14 0. "SWLOCK160,sticky write lock for shadow register 160" "0: Write to shadow register BSEC_FVR160 is allowed,1: Writes to shadow register BSEC_FVR160 are.." line.long 0x18 "BSEC_SWLOCK6,BSEC sticky write lock register 6" bitfld.long 0x18 31. "SWLOCK223,sticky write lock for shadow register 223" "0: Write to shadow register BSEC_FVR223 is allowed,1: Writes to shadow register BSEC_FVR223 are.." bitfld.long 0x18 30. "SWLOCK222,sticky write lock for shadow register 222" "0: Write to shadow register BSEC_FVR222 is allowed,1: Writes to shadow register BSEC_FVR222 are.." newline bitfld.long 0x18 29. "SWLOCK221,sticky write lock for shadow register 221" "0: Write to shadow register BSEC_FVR221 is allowed,1: Writes to shadow register BSEC_FVR221 are.." bitfld.long 0x18 28. "SWLOCK220,sticky write lock for shadow register 220" "0: Write to shadow register BSEC_FVR220 is allowed,1: Writes to shadow register BSEC_FVR220 are.." newline bitfld.long 0x18 27. "SWLOCK219,sticky write lock for shadow register 219" "0: Write to shadow register BSEC_FVR219 is allowed,1: Writes to shadow register BSEC_FVR219 are.." bitfld.long 0x18 26. "SWLOCK218,sticky write lock for shadow register 218" "0: Write to shadow register BSEC_FVR218 is allowed,1: Writes to shadow register BSEC_FVR218 are.." newline bitfld.long 0x18 25. "SWLOCK217,sticky write lock for shadow register 217" "0: Write to shadow register BSEC_FVR217 is allowed,1: Writes to shadow register BSEC_FVR217 are.." bitfld.long 0x18 24. "SWLOCK216,sticky write lock for shadow register 216" "0: Write to shadow register BSEC_FVR216 is allowed,1: Writes to shadow register BSEC_FVR216 are.." newline bitfld.long 0x18 23. "SWLOCK215,sticky write lock for shadow register 215" "0: Write to shadow register BSEC_FVR215 is allowed,1: Writes to shadow register BSEC_FVR215 are.." bitfld.long 0x18 22. "SWLOCK214,sticky write lock for shadow register 214" "0: Write to shadow register BSEC_FVR214 is allowed,1: Writes to shadow register BSEC_FVR214 are.." newline bitfld.long 0x18 21. "SWLOCK213,sticky write lock for shadow register 213" "0: Write to shadow register BSEC_FVR213 is allowed,1: Writes to shadow register BSEC_FVR213 are.." bitfld.long 0x18 20. "SWLOCK212,sticky write lock for shadow register 212" "0: Write to shadow register BSEC_FVR212 is allowed,1: Writes to shadow register BSEC_FVR212 are.." newline bitfld.long 0x18 19. "SWLOCK211,sticky write lock for shadow register 211" "0: Write to shadow register BSEC_FVR211 is allowed,1: Writes to shadow register BSEC_FVR211 are.." bitfld.long 0x18 18. "SWLOCK210,sticky write lock for shadow register 210" "0: Write to shadow register BSEC_FVR210 is allowed,1: Writes to shadow register BSEC_FVR210 are.." newline bitfld.long 0x18 17. "SWLOCK209,sticky write lock for shadow register 209" "0: Write to shadow register BSEC_FVR209 is allowed,1: Writes to shadow register BSEC_FVR209 are.." bitfld.long 0x18 16. "SWLOCK208,sticky write lock for shadow register 208" "0: Write to shadow register BSEC_FVR208 is allowed,1: Writes to shadow register BSEC_FVR208 are.." newline bitfld.long 0x18 15. "SWLOCK207,sticky write lock for shadow register 207" "0: Write to shadow register BSEC_FVR207 is allowed,1: Writes to shadow register BSEC_FVR207 are.." bitfld.long 0x18 14. "SWLOCK206,sticky write lock for shadow register 206" "0: Write to shadow register BSEC_FVR206 is allowed,1: Writes to shadow register BSEC_FVR206 are.." newline bitfld.long 0x18 13. "SWLOCK205,sticky write lock for shadow register 205" "0: Write to shadow register BSEC_FVR205 is allowed,1: Writes to shadow register BSEC_FVR205 are.." bitfld.long 0x18 12. "SWLOCK204,sticky write lock for shadow register 204" "0: Write to shadow register BSEC_FVR204 is allowed,1: Writes to shadow register BSEC_FVR204 are.." newline bitfld.long 0x18 11. "SWLOCK203,sticky write lock for shadow register 203" "0: Write to shadow register BSEC_FVR203 is allowed,1: Writes to shadow register BSEC_FVR203 are.." bitfld.long 0x18 10. "SWLOCK202,sticky write lock for shadow register 202" "0: Write to shadow register BSEC_FVR202 is allowed,1: Writes to shadow register BSEC_FVR202 are.." newline bitfld.long 0x18 9. "SWLOCK201,sticky write lock for shadow register 201" "0: Write to shadow register BSEC_FVR201 is allowed,1: Writes to shadow register BSEC_FVR201 are.." bitfld.long 0x18 8. "SWLOCK200,sticky write lock for shadow register 200" "0: Write to shadow register BSEC_FVR200 is allowed,1: Writes to shadow register BSEC_FVR200 are.." newline bitfld.long 0x18 7. "SWLOCK199,sticky write lock for shadow register 199" "0: Write to shadow register BSEC_FVR199 is allowed,1: Writes to shadow register BSEC_FVR199 are.." bitfld.long 0x18 6. "SWLOCK198,sticky write lock for shadow register 198" "0: Write to shadow register BSEC_FVR198 is allowed,1: Writes to shadow register BSEC_FVR198 are.." newline bitfld.long 0x18 5. "SWLOCK197,sticky write lock for shadow register 197" "0: Write to shadow register BSEC_FVR197 is allowed,1: Writes to shadow register BSEC_FVR197 are.." bitfld.long 0x18 4. "SWLOCK196,sticky write lock for shadow register 196" "0: Write to shadow register BSEC_FVR196 is allowed,1: Writes to shadow register BSEC_FVR196 are.." newline bitfld.long 0x18 3. "SWLOCK195,sticky write lock for shadow register 195" "0: Write to shadow register BSEC_FVR195 is allowed,1: Writes to shadow register BSEC_FVR195 are.." bitfld.long 0x18 2. "SWLOCK194,sticky write lock for shadow register 194" "0: Write to shadow register BSEC_FVR194 is allowed,1: Writes to shadow register BSEC_FVR194 are.." newline bitfld.long 0x18 1. "SWLOCK193,sticky write lock for shadow register 193" "0: Write to shadow register BSEC_FVR193 is allowed,1: Writes to shadow register BSEC_FVR193 are.." bitfld.long 0x18 0. "SWLOCK192,sticky write lock for shadow register 192" "0: Write to shadow register BSEC_FVR192 is allowed,1: Writes to shadow register BSEC_FVR192 are.." line.long 0x1C "BSEC_SWLOCK7,BSEC sticky write lock register 7" bitfld.long 0x1C 31. "SWLOCK255,sticky write lock for shadow register 255" "0: Write to shadow register BSEC_FVR255 is allowed,1: Writes to shadow register BSEC_FVR255 are.." bitfld.long 0x1C 30. "SWLOCK254,sticky write lock for shadow register 254" "0: Write to shadow register BSEC_FVR254 is allowed,1: Writes to shadow register BSEC_FVR254 are.." newline bitfld.long 0x1C 29. "SWLOCK253,sticky write lock for shadow register 253" "0: Write to shadow register BSEC_FVR253 is allowed,1: Writes to shadow register BSEC_FVR253 are.." bitfld.long 0x1C 28. "SWLOCK252,sticky write lock for shadow register 252" "0: Write to shadow register BSEC_FVR252 is allowed,1: Writes to shadow register BSEC_FVR252 are.." newline bitfld.long 0x1C 27. "SWLOCK251,sticky write lock for shadow register 251" "0: Write to shadow register BSEC_FVR251 is allowed,1: Writes to shadow register BSEC_FVR251 are.." bitfld.long 0x1C 26. "SWLOCK250,sticky write lock for shadow register 250" "0: Write to shadow register BSEC_FVR250 is allowed,1: Writes to shadow register BSEC_FVR250 are.." newline bitfld.long 0x1C 25. "SWLOCK249,sticky write lock for shadow register 249" "0: Write to shadow register BSEC_FVR249 is allowed,1: Writes to shadow register BSEC_FVR249 are.." bitfld.long 0x1C 24. "SWLOCK248,sticky write lock for shadow register 248" "0: Write to shadow register BSEC_FVR248 is allowed,1: Writes to shadow register BSEC_FVR248 are.." newline bitfld.long 0x1C 23. "SWLOCK247,sticky write lock for shadow register 247" "0: Write to shadow register BSEC_FVR247 is allowed,1: Writes to shadow register BSEC_FVR247 are.." bitfld.long 0x1C 22. "SWLOCK246,sticky write lock for shadow register 246" "0: Write to shadow register BSEC_FVR246 is allowed,1: Writes to shadow register BSEC_FVR246 are.." newline bitfld.long 0x1C 21. "SWLOCK245,sticky write lock for shadow register 245" "0: Write to shadow register BSEC_FVR245 is allowed,1: Writes to shadow register BSEC_FVR245 are.." bitfld.long 0x1C 20. "SWLOCK244,sticky write lock for shadow register 244" "0: Write to shadow register BSEC_FVR244 is allowed,1: Writes to shadow register BSEC_FVR244 are.." newline bitfld.long 0x1C 19. "SWLOCK243,sticky write lock for shadow register 243" "0: Write to shadow register BSEC_FVR243 is allowed,1: Writes to shadow register BSEC_FVR243 are.." bitfld.long 0x1C 18. "SWLOCK242,sticky write lock for shadow register 242" "0: Write to shadow register BSEC_FVR242 is allowed,1: Writes to shadow register BSEC_FVR242 are.." newline bitfld.long 0x1C 17. "SWLOCK241,sticky write lock for shadow register 241" "0: Write to shadow register BSEC_FVR241 is allowed,1: Writes to shadow register BSEC_FVR241 are.." bitfld.long 0x1C 16. "SWLOCK240,sticky write lock for shadow register 240" "0: Write to shadow register BSEC_FVR240 is allowed,1: Writes to shadow register BSEC_FVR240 are.." newline bitfld.long 0x1C 15. "SWLOCK239,sticky write lock for shadow register 239" "0: Write to shadow register BSEC_FVR239 is allowed,1: Writes to shadow register BSEC_FVR239 are.." bitfld.long 0x1C 14. "SWLOCK238,sticky write lock for shadow register 238" "0: Write to shadow register BSEC_FVR238 is allowed,1: Writes to shadow register BSEC_FVR238 are.." newline bitfld.long 0x1C 13. "SWLOCK237,sticky write lock for shadow register 237" "0: Write to shadow register BSEC_FVR237 is allowed,1: Writes to shadow register BSEC_FVR237 are.." bitfld.long 0x1C 12. "SWLOCK236,sticky write lock for shadow register 236" "0: Write to shadow register BSEC_FVR236 is allowed,1: Writes to shadow register BSEC_FVR236 are.." newline bitfld.long 0x1C 11. "SWLOCK235,sticky write lock for shadow register 235" "0: Write to shadow register BSEC_FVR235 is allowed,1: Writes to shadow register BSEC_FVR235 are.." bitfld.long 0x1C 10. "SWLOCK234,sticky write lock for shadow register 234" "0: Write to shadow register BSEC_FVR234 is allowed,1: Writes to shadow register BSEC_FVR234 are.." newline bitfld.long 0x1C 9. "SWLOCK233,sticky write lock for shadow register 233" "0: Write to shadow register BSEC_FVR233 is allowed,1: Writes to shadow register BSEC_FVR233 are.." bitfld.long 0x1C 8. "SWLOCK232,sticky write lock for shadow register 232" "0: Write to shadow register BSEC_FVR232 is allowed,1: Writes to shadow register BSEC_FVR232 are.." newline bitfld.long 0x1C 7. "SWLOCK231,sticky write lock for shadow register 231" "0: Write to shadow register BSEC_FVR231 is allowed,1: Writes to shadow register BSEC_FVR231 are.." bitfld.long 0x1C 6. "SWLOCK230,sticky write lock for shadow register 230" "0: Write to shadow register BSEC_FVR230 is allowed,1: Writes to shadow register BSEC_FVR230 are.." newline bitfld.long 0x1C 5. "SWLOCK229,sticky write lock for shadow register 229" "0: Write to shadow register BSEC_FVR229 is allowed,1: Writes to shadow register BSEC_FVR229 are.." bitfld.long 0x1C 4. "SWLOCK228,sticky write lock for shadow register 228" "0: Write to shadow register BSEC_FVR228 is allowed,1: Writes to shadow register BSEC_FVR228 are.." newline bitfld.long 0x1C 3. "SWLOCK227,sticky write lock for shadow register 227" "0: Write to shadow register BSEC_FVR227 is allowed,1: Writes to shadow register BSEC_FVR227 are.." bitfld.long 0x1C 2. "SWLOCK226,sticky write lock for shadow register 226" "0: Write to shadow register BSEC_FVR226 is allowed,1: Writes to shadow register BSEC_FVR226 are.." newline bitfld.long 0x1C 1. "SWLOCK225,sticky write lock for shadow register 225" "0: Write to shadow register BSEC_FVR225 is allowed,1: Writes to shadow register BSEC_FVR225 are.." bitfld.long 0x1C 0. "SWLOCK224,sticky write lock for shadow register 224" "0: Write to shadow register BSEC_FVR224 is allowed,1: Writes to shadow register BSEC_FVR224 are.." line.long 0x20 "BSEC_SWLOCK8,BSEC sticky write lock register 8" bitfld.long 0x20 31. "SWLOCK287,sticky write lock for shadow register 287" "0: Write to shadow register BSEC_FVR287 is allowed,1: Writes to shadow register BSEC_FVR287 are.." bitfld.long 0x20 30. "SWLOCK286,sticky write lock for shadow register 286" "0: Write to shadow register BSEC_FVR286 is allowed,1: Writes to shadow register BSEC_FVR286 are.." newline bitfld.long 0x20 29. "SWLOCK285,sticky write lock for shadow register 285" "0: Write to shadow register BSEC_FVR285 is allowed,1: Writes to shadow register BSEC_FVR285 are.." bitfld.long 0x20 28. "SWLOCK284,sticky write lock for shadow register 284" "0: Write to shadow register BSEC_FVR284 is allowed,1: Writes to shadow register BSEC_FVR284 are.." newline bitfld.long 0x20 27. "SWLOCK283,sticky write lock for shadow register 283" "0: Write to shadow register BSEC_FVR283 is allowed,1: Writes to shadow register BSEC_FVR283 are.." bitfld.long 0x20 26. "SWLOCK282,sticky write lock for shadow register 282" "0: Write to shadow register BSEC_FVR282 is allowed,1: Writes to shadow register BSEC_FVR282 are.." newline bitfld.long 0x20 25. "SWLOCK281,sticky write lock for shadow register 281" "0: Write to shadow register BSEC_FVR281 is allowed,1: Writes to shadow register BSEC_FVR281 are.." bitfld.long 0x20 24. "SWLOCK280,sticky write lock for shadow register 280" "0: Write to shadow register BSEC_FVR280 is allowed,1: Writes to shadow register BSEC_FVR280 are.." newline bitfld.long 0x20 23. "SWLOCK279,sticky write lock for shadow register 279" "0: Write to shadow register BSEC_FVR279 is allowed,1: Writes to shadow register BSEC_FVR279 are.." bitfld.long 0x20 22. "SWLOCK278,sticky write lock for shadow register 278" "0: Write to shadow register BSEC_FVR278 is allowed,1: Writes to shadow register BSEC_FVR278 are.." newline bitfld.long 0x20 21. "SWLOCK277,sticky write lock for shadow register 277" "0: Write to shadow register BSEC_FVR277 is allowed,1: Writes to shadow register BSEC_FVR277 are.." bitfld.long 0x20 20. "SWLOCK276,sticky write lock for shadow register 276" "0: Write to shadow register BSEC_FVR276 is allowed,1: Writes to shadow register BSEC_FVR276 are.." newline bitfld.long 0x20 19. "SWLOCK275,sticky write lock for shadow register 275" "0: Write to shadow register BSEC_FVR275 is allowed,1: Writes to shadow register BSEC_FVR275 are.." bitfld.long 0x20 18. "SWLOCK274,sticky write lock for shadow register 274" "0: Write to shadow register BSEC_FVR274 is allowed,1: Writes to shadow register BSEC_FVR274 are.." newline bitfld.long 0x20 17. "SWLOCK273,sticky write lock for shadow register 273" "0: Write to shadow register BSEC_FVR273 is allowed,1: Writes to shadow register BSEC_FVR273 are.." bitfld.long 0x20 16. "SWLOCK272,sticky write lock for shadow register 272" "0: Write to shadow register BSEC_FVR272 is allowed,1: Writes to shadow register BSEC_FVR272 are.." newline bitfld.long 0x20 15. "SWLOCK271,sticky write lock for shadow register 271" "0: Write to shadow register BSEC_FVR271 is allowed,1: Writes to shadow register BSEC_FVR271 are.." bitfld.long 0x20 14. "SWLOCK270,sticky write lock for shadow register 270" "0: Write to shadow register BSEC_FVR270 is allowed,1: Writes to shadow register BSEC_FVR270 are.." newline bitfld.long 0x20 13. "SWLOCK269,sticky write lock for shadow register 269" "0: Write to shadow register BSEC_FVR269 is allowed,1: Writes to shadow register BSEC_FVR269 are.." bitfld.long 0x20 12. "SWLOCK268,sticky write lock for shadow register 268" "0: Write to shadow register BSEC_FVR268 is allowed,1: Writes to shadow register BSEC_FVR268 are.." newline bitfld.long 0x20 11. "SWLOCK267,sticky write lock for shadow register 267" "0: Write to shadow register BSEC_FVR267 is allowed,1: Writes to shadow register BSEC_FVR267 are.." bitfld.long 0x20 10. "SWLOCK266,sticky write lock for shadow register 266" "0: Write to shadow register BSEC_FVR266 is allowed,1: Writes to shadow register BSEC_FVR266 are.." newline bitfld.long 0x20 9. "SWLOCK265,sticky write lock for shadow register 265" "0: Write to shadow register BSEC_FVR265 is allowed,1: Writes to shadow register BSEC_FVR265 are.." bitfld.long 0x20 8. "SWLOCK264,sticky write lock for shadow register 264" "0: Write to shadow register BSEC_FVR264 is allowed,1: Writes to shadow register BSEC_FVR264 are.." newline bitfld.long 0x20 7. "SWLOCK263,sticky write lock for shadow register 263" "0: Write to shadow register BSEC_FVR263 is allowed,1: Writes to shadow register BSEC_FVR263 are.." bitfld.long 0x20 6. "SWLOCK262,sticky write lock for shadow register 262" "0: Write to shadow register BSEC_FVR262 is allowed,1: Writes to shadow register BSEC_FVR262 are.." newline bitfld.long 0x20 5. "SWLOCK261,sticky write lock for shadow register 261" "0: Write to shadow register BSEC_FVR261 is allowed,1: Writes to shadow register BSEC_FVR261 are.." bitfld.long 0x20 4. "SWLOCK260,sticky write lock for shadow register 260" "0: Write to shadow register BSEC_FVR260 is allowed,1: Writes to shadow register BSEC_FVR260 are.." newline bitfld.long 0x20 3. "SWLOCK259,sticky write lock for shadow register 259" "0: Write to shadow register BSEC_FVR259 is allowed,1: Writes to shadow register BSEC_FVR259 are.." bitfld.long 0x20 2. "SWLOCK258,sticky write lock for shadow register 258" "0: Write to shadow register BSEC_FVR258 is allowed,1: Writes to shadow register BSEC_FVR258 are.." newline bitfld.long 0x20 1. "SWLOCK257,sticky write lock for shadow register 257" "0: Write to shadow register BSEC_FVR257 is allowed,1: Writes to shadow register BSEC_FVR257 are.." bitfld.long 0x20 0. "SWLOCK256,sticky write lock for shadow register 256" "0: Write to shadow register BSEC_FVR256 is allowed,1: Writes to shadow register BSEC_FVR256 are.." line.long 0x24 "BSEC_SWLOCK9,BSEC sticky write lock register 9" bitfld.long 0x24 31. "SWLOCK319,sticky write lock for shadow register 319" "0: Write to shadow register BSEC_FVR319 is allowed,1: Writes to shadow register BSEC_FVR319 are.." bitfld.long 0x24 30. "SWLOCK318,sticky write lock for shadow register 318" "0: Write to shadow register BSEC_FVR318 is allowed,1: Writes to shadow register BSEC_FVR318 are.." newline bitfld.long 0x24 29. "SWLOCK317,sticky write lock for shadow register 317" "0: Write to shadow register BSEC_FVR317 is allowed,1: Writes to shadow register BSEC_FVR317 are.." bitfld.long 0x24 28. "SWLOCK316,sticky write lock for shadow register 316" "0: Write to shadow register BSEC_FVR316 is allowed,1: Writes to shadow register BSEC_FVR316 are.." newline bitfld.long 0x24 27. "SWLOCK315,sticky write lock for shadow register 315" "0: Write to shadow register BSEC_FVR315 is allowed,1: Writes to shadow register BSEC_FVR315 are.." bitfld.long 0x24 26. "SWLOCK314,sticky write lock for shadow register 314" "0: Write to shadow register BSEC_FVR314 is allowed,1: Writes to shadow register BSEC_FVR314 are.." newline bitfld.long 0x24 25. "SWLOCK313,sticky write lock for shadow register 313" "0: Write to shadow register BSEC_FVR313 is allowed,1: Writes to shadow register BSEC_FVR313 are.." bitfld.long 0x24 24. "SWLOCK312,sticky write lock for shadow register 312" "0: Write to shadow register BSEC_FVR312 is allowed,1: Writes to shadow register BSEC_FVR312 are.." newline bitfld.long 0x24 23. "SWLOCK311,sticky write lock for shadow register 311" "0: Write to shadow register BSEC_FVR311 is allowed,1: Writes to shadow register BSEC_FVR311 are.." bitfld.long 0x24 22. "SWLOCK310,sticky write lock for shadow register 310" "0: Write to shadow register BSEC_FVR310 is allowed,1: Writes to shadow register BSEC_FVR310 are.." newline bitfld.long 0x24 21. "SWLOCK309,sticky write lock for shadow register 309" "0: Write to shadow register BSEC_FVR309 is allowed,1: Writes to shadow register BSEC_FVR309 are.." bitfld.long 0x24 20. "SWLOCK308,sticky write lock for shadow register 308" "0: Write to shadow register BSEC_FVR308 is allowed,1: Writes to shadow register BSEC_FVR308 are.." newline bitfld.long 0x24 19. "SWLOCK307,sticky write lock for shadow register 307" "0: Write to shadow register BSEC_FVR307 is allowed,1: Writes to shadow register BSEC_FVR307 are.." bitfld.long 0x24 18. "SWLOCK306,sticky write lock for shadow register 306" "0: Write to shadow register BSEC_FVR306 is allowed,1: Writes to shadow register BSEC_FVR306 are.." newline bitfld.long 0x24 17. "SWLOCK305,sticky write lock for shadow register 305" "0: Write to shadow register BSEC_FVR305 is allowed,1: Writes to shadow register BSEC_FVR305 are.." bitfld.long 0x24 16. "SWLOCK304,sticky write lock for shadow register 304" "0: Write to shadow register BSEC_FVR304 is allowed,1: Writes to shadow register BSEC_FVR304 are.." newline bitfld.long 0x24 15. "SWLOCK303,sticky write lock for shadow register 303" "0: Write to shadow register BSEC_FVR303 is allowed,1: Writes to shadow register BSEC_FVR303 are.." bitfld.long 0x24 14. "SWLOCK302,sticky write lock for shadow register 302" "0: Write to shadow register BSEC_FVR302 is allowed,1: Writes to shadow register BSEC_FVR302 are.." newline bitfld.long 0x24 13. "SWLOCK301,sticky write lock for shadow register 301" "0: Write to shadow register BSEC_FVR301 is allowed,1: Writes to shadow register BSEC_FVR301 are.." bitfld.long 0x24 12. "SWLOCK300,sticky write lock for shadow register 300" "0: Write to shadow register BSEC_FVR300 is allowed,1: Writes to shadow register BSEC_FVR300 are.." newline bitfld.long 0x24 11. "SWLOCK299,sticky write lock for shadow register 299" "0: Write to shadow register BSEC_FVR299 is allowed,1: Writes to shadow register BSEC_FVR299 are.." bitfld.long 0x24 10. "SWLOCK298,sticky write lock for shadow register 298" "0: Write to shadow register BSEC_FVR298 is allowed,1: Writes to shadow register BSEC_FVR298 are.." newline bitfld.long 0x24 9. "SWLOCK297,sticky write lock for shadow register 297" "0: Write to shadow register BSEC_FVR297 is allowed,1: Writes to shadow register BSEC_FVR297 are.." bitfld.long 0x24 8. "SWLOCK296,sticky write lock for shadow register 296" "0: Write to shadow register BSEC_FVR296 is allowed,1: Writes to shadow register BSEC_FVR296 are.." newline bitfld.long 0x24 7. "SWLOCK295,sticky write lock for shadow register 295" "0: Write to shadow register BSEC_FVR295 is allowed,1: Writes to shadow register BSEC_FVR295 are.." bitfld.long 0x24 6. "SWLOCK294,sticky write lock for shadow register 294" "0: Write to shadow register BSEC_FVR294 is allowed,1: Writes to shadow register BSEC_FVR294 are.." newline bitfld.long 0x24 5. "SWLOCK293,sticky write lock for shadow register 293" "0: Write to shadow register BSEC_FVR293 is allowed,1: Writes to shadow register BSEC_FVR293 are.." bitfld.long 0x24 4. "SWLOCK292,sticky write lock for shadow register 292" "0: Write to shadow register BSEC_FVR292 is allowed,1: Writes to shadow register BSEC_FVR292 are.." newline bitfld.long 0x24 3. "SWLOCK291,sticky write lock for shadow register 291" "0: Write to shadow register BSEC_FVR291 is allowed,1: Writes to shadow register BSEC_FVR291 are.." bitfld.long 0x24 2. "SWLOCK290,sticky write lock for shadow register 290" "0: Write to shadow register BSEC_FVR290 is allowed,1: Writes to shadow register BSEC_FVR290 are.." newline bitfld.long 0x24 1. "SWLOCK289,sticky write lock for shadow register 289" "0: Write to shadow register BSEC_FVR289 is allowed,1: Writes to shadow register BSEC_FVR289 are.." bitfld.long 0x24 0. "SWLOCK288,sticky write lock for shadow register 288" "0: Write to shadow register BSEC_FVR288 is allowed,1: Writes to shadow register BSEC_FVR288 are.." line.long 0x28 "BSEC_SWLOCK10,BSEC sticky write lock register 10" bitfld.long 0x28 31. "SWLOCK351,sticky write lock for shadow register 351" "0: Write to shadow register BSEC_FVR351 is allowed,1: Writes to shadow register BSEC_FVR351 are.." bitfld.long 0x28 30. "SWLOCK350,sticky write lock for shadow register 350" "0: Write to shadow register BSEC_FVR350 is allowed,1: Writes to shadow register BSEC_FVR350 are.." newline bitfld.long 0x28 29. "SWLOCK349,sticky write lock for shadow register 349" "0: Write to shadow register BSEC_FVR349 is allowed,1: Writes to shadow register BSEC_FVR349 are.." bitfld.long 0x28 28. "SWLOCK348,sticky write lock for shadow register 348" "0: Write to shadow register BSEC_FVR348 is allowed,1: Writes to shadow register BSEC_FVR348 are.." newline bitfld.long 0x28 27. "SWLOCK347,sticky write lock for shadow register 347" "0: Write to shadow register BSEC_FVR347 is allowed,1: Writes to shadow register BSEC_FVR347 are.." bitfld.long 0x28 26. "SWLOCK346,sticky write lock for shadow register 346" "0: Write to shadow register BSEC_FVR346 is allowed,1: Writes to shadow register BSEC_FVR346 are.." newline bitfld.long 0x28 25. "SWLOCK345,sticky write lock for shadow register 345" "0: Write to shadow register BSEC_FVR345 is allowed,1: Writes to shadow register BSEC_FVR345 are.." bitfld.long 0x28 24. "SWLOCK344,sticky write lock for shadow register 344" "0: Write to shadow register BSEC_FVR344 is allowed,1: Writes to shadow register BSEC_FVR344 are.." newline bitfld.long 0x28 23. "SWLOCK343,sticky write lock for shadow register 343" "0: Write to shadow register BSEC_FVR343 is allowed,1: Writes to shadow register BSEC_FVR343 are.." bitfld.long 0x28 22. "SWLOCK342,sticky write lock for shadow register 342" "0: Write to shadow register BSEC_FVR342 is allowed,1: Writes to shadow register BSEC_FVR342 are.." newline bitfld.long 0x28 21. "SWLOCK341,sticky write lock for shadow register 341" "0: Write to shadow register BSEC_FVR341 is allowed,1: Writes to shadow register BSEC_FVR341 are.." bitfld.long 0x28 20. "SWLOCK340,sticky write lock for shadow register 340" "0: Write to shadow register BSEC_FVR340 is allowed,1: Writes to shadow register BSEC_FVR340 are.." newline bitfld.long 0x28 19. "SWLOCK339,sticky write lock for shadow register 339" "0: Write to shadow register BSEC_FVR339 is allowed,1: Writes to shadow register BSEC_FVR339 are.." bitfld.long 0x28 18. "SWLOCK338,sticky write lock for shadow register 338" "0: Write to shadow register BSEC_FVR338 is allowed,1: Writes to shadow register BSEC_FVR338 are.." newline bitfld.long 0x28 17. "SWLOCK337,sticky write lock for shadow register 337" "0: Write to shadow register BSEC_FVR337 is allowed,1: Writes to shadow register BSEC_FVR337 are.." bitfld.long 0x28 16. "SWLOCK336,sticky write lock for shadow register 336" "0: Write to shadow register BSEC_FVR336 is allowed,1: Writes to shadow register BSEC_FVR336 are.." newline bitfld.long 0x28 15. "SWLOCK335,sticky write lock for shadow register 335" "0: Write to shadow register BSEC_FVR335 is allowed,1: Writes to shadow register BSEC_FVR335 are.." bitfld.long 0x28 14. "SWLOCK334,sticky write lock for shadow register 334" "0: Write to shadow register BSEC_FVR334 is allowed,1: Writes to shadow register BSEC_FVR334 are.." newline bitfld.long 0x28 13. "SWLOCK333,sticky write lock for shadow register 333" "0: Write to shadow register BSEC_FVR333 is allowed,1: Writes to shadow register BSEC_FVR333 are.." bitfld.long 0x28 12. "SWLOCK332,sticky write lock for shadow register 332" "0: Write to shadow register BSEC_FVR332 is allowed,1: Writes to shadow register BSEC_FVR332 are.." newline bitfld.long 0x28 11. "SWLOCK331,sticky write lock for shadow register 331" "0: Write to shadow register BSEC_FVR331 is allowed,1: Writes to shadow register BSEC_FVR331 are.." bitfld.long 0x28 10. "SWLOCK330,sticky write lock for shadow register 330" "0: Write to shadow register BSEC_FVR330 is allowed,1: Writes to shadow register BSEC_FVR330 are.." newline bitfld.long 0x28 9. "SWLOCK329,sticky write lock for shadow register 329" "0: Write to shadow register BSEC_FVR329 is allowed,1: Writes to shadow register BSEC_FVR329 are.." bitfld.long 0x28 8. "SWLOCK328,sticky write lock for shadow register 328" "0: Write to shadow register BSEC_FVR328 is allowed,1: Writes to shadow register BSEC_FVR328 are.." newline bitfld.long 0x28 7. "SWLOCK327,sticky write lock for shadow register 327" "0: Write to shadow register BSEC_FVR327 is allowed,1: Writes to shadow register BSEC_FVR327 are.." bitfld.long 0x28 6. "SWLOCK326,sticky write lock for shadow register 326" "0: Write to shadow register BSEC_FVR326 is allowed,1: Writes to shadow register BSEC_FVR326 are.." newline bitfld.long 0x28 5. "SWLOCK325,sticky write lock for shadow register 325" "0: Write to shadow register BSEC_FVR325 is allowed,1: Writes to shadow register BSEC_FVR325 are.." bitfld.long 0x28 4. "SWLOCK324,sticky write lock for shadow register 324" "0: Write to shadow register BSEC_FVR324 is allowed,1: Writes to shadow register BSEC_FVR324 are.." newline bitfld.long 0x28 3. "SWLOCK323,sticky write lock for shadow register 323" "0: Write to shadow register BSEC_FVR323 is allowed,1: Writes to shadow register BSEC_FVR323 are.." bitfld.long 0x28 2. "SWLOCK322,sticky write lock for shadow register 322" "0: Write to shadow register BSEC_FVR322 is allowed,1: Writes to shadow register BSEC_FVR322 are.." newline bitfld.long 0x28 1. "SWLOCK321,sticky write lock for shadow register 321" "0: Write to shadow register BSEC_FVR321 is allowed,1: Writes to shadow register BSEC_FVR321 are.." bitfld.long 0x28 0. "SWLOCK320,sticky write lock for shadow register 320" "0: Write to shadow register BSEC_FVR320 is allowed,1: Writes to shadow register BSEC_FVR320 are.." line.long 0x2C "BSEC_SWLOCK11,BSEC sticky write lock register 11" bitfld.long 0x2C 31. "SWLOCK383,sticky write lock for shadow register 383" "0: Write to shadow register BSEC_FVR383 is allowed,1: Writes to shadow register BSEC_FVR383 are.." bitfld.long 0x2C 30. "SWLOCK382,sticky write lock for shadow register 382" "0: Write to shadow register BSEC_FVR382 is allowed,1: Writes to shadow register BSEC_FVR382 are.." newline bitfld.long 0x2C 29. "SWLOCK381,sticky write lock for shadow register 381" "0: Write to shadow register BSEC_FVR381 is allowed,1: Writes to shadow register BSEC_FVR381 are.." bitfld.long 0x2C 28. "SWLOCK380,sticky write lock for shadow register 380" "0: Write to shadow register BSEC_FVR380 is allowed,1: Writes to shadow register BSEC_FVR380 are.." newline bitfld.long 0x2C 27. "SWLOCK379,sticky write lock for shadow register 379" "0: Write to shadow register BSEC_FVR379 is allowed,1: Writes to shadow register BSEC_FVR379 are.." bitfld.long 0x2C 26. "SWLOCK378,sticky write lock for shadow register 378" "0: Write to shadow register BSEC_FVR378 is allowed,1: Writes to shadow register BSEC_FVR378 are.." newline bitfld.long 0x2C 25. "SWLOCK377,sticky write lock for shadow register 377" "0: Write to shadow register BSEC_FVR377 is allowed,1: Writes to shadow register BSEC_FVR377 are.." bitfld.long 0x2C 24. "SWLOCK376,sticky write lock for shadow register 376" "0: Write to shadow register BSEC_FVR376 is allowed,1: Writes to shadow register BSEC_FVR376 are.." newline bitfld.long 0x2C 23. "SWLOCK375,sticky write lock for shadow register 375" "0: Write to shadow register BSEC_FVR375 is allowed,1: Writes to shadow register BSEC_FVR375 are.." bitfld.long 0x2C 22. "SWLOCK374,sticky write lock for shadow register 374" "0: Write to shadow register BSEC_FVR374 is allowed,1: Writes to shadow register BSEC_FVR374 are.." newline bitfld.long 0x2C 21. "SWLOCK373,sticky write lock for shadow register 373" "0: Write to shadow register BSEC_FVR373 is allowed,1: Writes to shadow register BSEC_FVR373 are.." bitfld.long 0x2C 20. "SWLOCK372,sticky write lock for shadow register 372" "0: Write to shadow register BSEC_FVR372 is allowed,1: Writes to shadow register BSEC_FVR372 are.." newline bitfld.long 0x2C 19. "SWLOCK371,sticky write lock for shadow register 371" "0: Write to shadow register BSEC_FVR371 is allowed,1: Writes to shadow register BSEC_FVR371 are.." bitfld.long 0x2C 18. "SWLOCK370,sticky write lock for shadow register 370" "0: Write to shadow register BSEC_FVR370 is allowed,1: Writes to shadow register BSEC_FVR370 are.." newline bitfld.long 0x2C 17. "SWLOCK369,sticky write lock for shadow register 369" "0: Write to shadow register BSEC_FVR369 is allowed,1: Writes to shadow register BSEC_FVR369 are.." bitfld.long 0x2C 16. "SWLOCK368,sticky write lock for shadow register 368" "0: Write to shadow register BSEC_FVR368 is allowed,1: Writes to shadow register BSEC_FVR368 are.." newline bitfld.long 0x2C 15. "SWLOCK367,sticky write lock for shadow register 367" "0: Write to shadow register BSEC_FVR367 is allowed,1: Writes to shadow register BSEC_FVR367 are.." bitfld.long 0x2C 14. "SWLOCK366,sticky write lock for shadow register 366" "0: Write to shadow register BSEC_FVR366 is allowed,1: Writes to shadow register BSEC_FVR366 are.." newline bitfld.long 0x2C 13. "SWLOCK365,sticky write lock for shadow register 365" "0: Write to shadow register BSEC_FVR365 is allowed,1: Writes to shadow register BSEC_FVR365 are.." bitfld.long 0x2C 12. "SWLOCK364,sticky write lock for shadow register 364" "0: Write to shadow register BSEC_FVR364 is allowed,1: Writes to shadow register BSEC_FVR364 are.." newline bitfld.long 0x2C 11. "SWLOCK363,sticky write lock for shadow register 363" "0: Write to shadow register BSEC_FVR363 is allowed,1: Writes to shadow register BSEC_FVR363 are.." bitfld.long 0x2C 10. "SWLOCK362,sticky write lock for shadow register 362" "0: Write to shadow register BSEC_FVR362 is allowed,1: Writes to shadow register BSEC_FVR362 are.." newline bitfld.long 0x2C 9. "SWLOCK361,sticky write lock for shadow register 361" "0: Write to shadow register BSEC_FVR361 is allowed,1: Writes to shadow register BSEC_FVR361 are.." bitfld.long 0x2C 8. "SWLOCK360,sticky write lock for shadow register 360" "0: Write to shadow register BSEC_FVR360 is allowed,1: Writes to shadow register BSEC_FVR360 are.." newline bitfld.long 0x2C 7. "SWLOCK359,sticky write lock for shadow register 359" "0: Write to shadow register BSEC_FVR359 is allowed,1: Writes to shadow register BSEC_FVR359 are.." bitfld.long 0x2C 6. "SWLOCK358,sticky write lock for shadow register 358" "0: Write to shadow register BSEC_FVR358 is allowed,1: Writes to shadow register BSEC_FVR358 are.." newline bitfld.long 0x2C 5. "SWLOCK357,sticky write lock for shadow register 357" "0: Write to shadow register BSEC_FVR357 is allowed,1: Writes to shadow register BSEC_FVR357 are.." bitfld.long 0x2C 4. "SWLOCK356,sticky write lock for shadow register 356" "0: Write to shadow register BSEC_FVR356 is allowed,1: Writes to shadow register BSEC_FVR356 are.." newline bitfld.long 0x2C 3. "SWLOCK355,sticky write lock for shadow register 355" "0: Write to shadow register BSEC_FVR355 is allowed,1: Writes to shadow register BSEC_FVR355 are.." bitfld.long 0x2C 2. "SWLOCK354,sticky write lock for shadow register 354" "0: Write to shadow register BSEC_FVR354 is allowed,1: Writes to shadow register BSEC_FVR354 are.." newline bitfld.long 0x2C 1. "SWLOCK353,sticky write lock for shadow register 353" "0: Write to shadow register BSEC_FVR353 is allowed,1: Writes to shadow register BSEC_FVR353 are.." bitfld.long 0x2C 0. "SWLOCK352,sticky write lock for shadow register 352" "0: Write to shadow register BSEC_FVR352 is allowed,1: Writes to shadow register BSEC_FVR352 are.." group.long 0x880++0x2F line.long 0x0 "BSEC_SRLOCK0,BSEC sticky reload lock register 0" bitfld.long 0x0 31. "SRLOCK31,sticky reload lock for fuse word 31" "0: Fuse word 31 loading through BSEC_OTPCR is..,1: Fuse word 31 loading through BSEC_OTPCR is.." bitfld.long 0x0 30. "SRLOCK30,sticky reload lock for fuse word 30" "0: Fuse word 30 loading through BSEC_OTPCR is..,1: Fuse word 30 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 29. "SRLOCK29,sticky reload lock for fuse word 29" "0: Fuse word 29 loading through BSEC_OTPCR is..,1: Fuse word 29 loading through BSEC_OTPCR is.." bitfld.long 0x0 28. "SRLOCK28,sticky reload lock for fuse word 28" "0: Fuse word 28 loading through BSEC_OTPCR is..,1: Fuse word 28 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 27. "SRLOCK27,sticky reload lock for fuse word 27" "0: Fuse word 27 loading through BSEC_OTPCR is..,1: Fuse word 27 loading through BSEC_OTPCR is.." bitfld.long 0x0 26. "SRLOCK26,sticky reload lock for fuse word 26" "0: Fuse word 26 loading through BSEC_OTPCR is..,1: Fuse word 26 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 25. "SRLOCK25,sticky reload lock for fuse word 25" "0: Fuse word 25 loading through BSEC_OTPCR is..,1: Fuse word 25 loading through BSEC_OTPCR is.." bitfld.long 0x0 24. "SRLOCK24,sticky reload lock for fuse word 24" "0: Fuse word 24 loading through BSEC_OTPCR is..,1: Fuse word 24 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 23. "SRLOCK23,sticky reload lock for fuse word 23" "0: Fuse word 23 loading through BSEC_OTPCR is..,1: Fuse word 23 loading through BSEC_OTPCR is.." bitfld.long 0x0 22. "SRLOCK22,sticky reload lock for fuse word 22" "0: Fuse word 22 loading through BSEC_OTPCR is..,1: Fuse word 22 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 21. "SRLOCK21,sticky reload lock for fuse word 21" "0: Fuse word 21 loading through BSEC_OTPCR is..,1: Fuse word 21 loading through BSEC_OTPCR is.." bitfld.long 0x0 20. "SRLOCK20,sticky reload lock for fuse word 20" "0: Fuse word 20 loading through BSEC_OTPCR is..,1: Fuse word 20 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 19. "SRLOCK19,sticky reload lock for fuse word 19" "0: Fuse word 19 loading through BSEC_OTPCR is..,1: Fuse word 19 loading through BSEC_OTPCR is.." bitfld.long 0x0 18. "SRLOCK18,sticky reload lock for fuse word 18" "0: Fuse word 18 loading through BSEC_OTPCR is..,1: Fuse word 18 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 17. "SRLOCK17,sticky reload lock for fuse word 17" "0: Fuse word 17 loading through BSEC_OTPCR is..,1: Fuse word 17 loading through BSEC_OTPCR is.." bitfld.long 0x0 16. "SRLOCK16,sticky reload lock for fuse word 16" "0: Fuse word 16 loading through BSEC_OTPCR is..,1: Fuse word 16 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 15. "SRLOCK15,sticky reload lock for fuse word 15" "0: Fuse word 15 loading through BSEC_OTPCR is..,1: Fuse word 15 loading through BSEC_OTPCR is.." bitfld.long 0x0 14. "SRLOCK14,sticky reload lock for fuse word 14" "0: Fuse word 14 loading through BSEC_OTPCR is..,1: Fuse word 14 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 13. "SRLOCK13,sticky reload lock for fuse word 13" "0: Fuse word 13 loading through BSEC_OTPCR is..,1: Fuse word 13 loading through BSEC_OTPCR is.." bitfld.long 0x0 12. "SRLOCK12,sticky reload lock for fuse word 12" "0: Fuse word 12 loading through BSEC_OTPCR is..,1: Fuse word 12 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 11. "SRLOCK11,sticky reload lock for fuse word 11" "0: Fuse word 11 loading through BSEC_OTPCR is..,1: Fuse word 11 loading through BSEC_OTPCR is.." bitfld.long 0x0 10. "SRLOCK10,sticky reload lock for fuse word 10" "0: Fuse word 10 loading through BSEC_OTPCR is..,1: Fuse word 10 loading through BSEC_OTPCR is.." newline bitfld.long 0x0 9. "SRLOCK9,sticky reload lock for fuse word 9" "0: Fuse word 9 loading through BSEC_OTPCR is..,1: Fuse word 9 loading through BSEC_OTPCR is denied.." bitfld.long 0x0 8. "SRLOCK8,sticky reload lock for fuse word 8" "0: Fuse word 8 loading through BSEC_OTPCR is..,1: Fuse word 8 loading through BSEC_OTPCR is denied.." newline bitfld.long 0x0 7. "SRLOCK7,sticky reload lock for fuse word 7" "0: Fuse word 7 loading through BSEC_OTPCR is..,1: Fuse word 7 loading through BSEC_OTPCR is denied.." bitfld.long 0x0 6. "SRLOCK6,sticky reload lock for fuse word 6" "0: Fuse word 6 loading through BSEC_OTPCR is..,1: Fuse word 6 loading through BSEC_OTPCR is denied.." newline bitfld.long 0x0 5. "SRLOCK5,sticky reload lock for fuse word 5" "0: Fuse word 5 loading through BSEC_OTPCR is..,1: Fuse word 5 loading through BSEC_OTPCR is denied.." bitfld.long 0x0 4. "SRLOCK4,sticky reload lock for fuse word 4" "0: Fuse word 4 loading through BSEC_OTPCR is..,1: Fuse word 4 loading through BSEC_OTPCR is denied.." newline bitfld.long 0x0 3. "SRLOCK3,sticky reload lock for fuse word 3" "0: Fuse word 3 loading through BSEC_OTPCR is..,1: Fuse word 3 loading through BSEC_OTPCR is denied.." bitfld.long 0x0 2. "SRLOCK2,sticky reload lock for fuse word 2" "0: Fuse word 2 loading through BSEC_OTPCR is..,1: Fuse word 2 loading through BSEC_OTPCR is denied.." newline bitfld.long 0x0 1. "SRLOCK1,sticky reload lock for fuse word 1" "0: Fuse word 1 loading through BSEC_OTPCR is..,1: Fuse word 1 loading through BSEC_OTPCR is denied.." bitfld.long 0x0 0. "SRLOCK0,sticky reload lock for fuse word 0" "0: Fuse word 0 loading through BSEC_OTPCR is..,1: Fuse word 0 loading through BSEC_OTPCR is denied.." line.long 0x4 "BSEC_SRLOCK1,BSEC sticky reload lock register 1" bitfld.long 0x4 31. "SRLOCK63,sticky reload lock for fuse word 63" "0: Fuse word 63 loading through BSEC_OTPCR is..,1: Fuse word 63 loading through BSEC_OTPCR is.." bitfld.long 0x4 30. "SRLOCK62,sticky reload lock for fuse word 62" "0: Fuse word 62 loading through BSEC_OTPCR is..,1: Fuse word 62 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 29. "SRLOCK61,sticky reload lock for fuse word 61" "0: Fuse word 61 loading through BSEC_OTPCR is..,1: Fuse word 61 loading through BSEC_OTPCR is.." bitfld.long 0x4 28. "SRLOCK60,sticky reload lock for fuse word 60" "0: Fuse word 60 loading through BSEC_OTPCR is..,1: Fuse word 60 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 27. "SRLOCK59,sticky reload lock for fuse word 59" "0: Fuse word 59 loading through BSEC_OTPCR is..,1: Fuse word 59 loading through BSEC_OTPCR is.." bitfld.long 0x4 26. "SRLOCK58,sticky reload lock for fuse word 58" "0: Fuse word 58 loading through BSEC_OTPCR is..,1: Fuse word 58 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 25. "SRLOCK57,sticky reload lock for fuse word 57" "0: Fuse word 57 loading through BSEC_OTPCR is..,1: Fuse word 57 loading through BSEC_OTPCR is.." bitfld.long 0x4 24. "SRLOCK56,sticky reload lock for fuse word 56" "0: Fuse word 56 loading through BSEC_OTPCR is..,1: Fuse word 56 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 23. "SRLOCK55,sticky reload lock for fuse word 55" "0: Fuse word 55 loading through BSEC_OTPCR is..,1: Fuse word 55 loading through BSEC_OTPCR is.." bitfld.long 0x4 22. "SRLOCK54,sticky reload lock for fuse word 54" "0: Fuse word 54 loading through BSEC_OTPCR is..,1: Fuse word 54 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 21. "SRLOCK53,sticky reload lock for fuse word 53" "0: Fuse word 53 loading through BSEC_OTPCR is..,1: Fuse word 53 loading through BSEC_OTPCR is.." bitfld.long 0x4 20. "SRLOCK52,sticky reload lock for fuse word 52" "0: Fuse word 52 loading through BSEC_OTPCR is..,1: Fuse word 52 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 19. "SRLOCK51,sticky reload lock for fuse word 51" "0: Fuse word 51 loading through BSEC_OTPCR is..,1: Fuse word 51 loading through BSEC_OTPCR is.." bitfld.long 0x4 18. "SRLOCK50,sticky reload lock for fuse word 50" "0: Fuse word 50 loading through BSEC_OTPCR is..,1: Fuse word 50 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 17. "SRLOCK49,sticky reload lock for fuse word 49" "0: Fuse word 49 loading through BSEC_OTPCR is..,1: Fuse word 49 loading through BSEC_OTPCR is.." bitfld.long 0x4 16. "SRLOCK48,sticky reload lock for fuse word 48" "0: Fuse word 48 loading through BSEC_OTPCR is..,1: Fuse word 48 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 15. "SRLOCK47,sticky reload lock for fuse word 47" "0: Fuse word 47 loading through BSEC_OTPCR is..,1: Fuse word 47 loading through BSEC_OTPCR is.." bitfld.long 0x4 14. "SRLOCK46,sticky reload lock for fuse word 46" "0: Fuse word 46 loading through BSEC_OTPCR is..,1: Fuse word 46 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 13. "SRLOCK45,sticky reload lock for fuse word 45" "0: Fuse word 45 loading through BSEC_OTPCR is..,1: Fuse word 45 loading through BSEC_OTPCR is.." bitfld.long 0x4 12. "SRLOCK44,sticky reload lock for fuse word 44" "0: Fuse word 44 loading through BSEC_OTPCR is..,1: Fuse word 44 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 11. "SRLOCK43,sticky reload lock for fuse word 43" "0: Fuse word 43 loading through BSEC_OTPCR is..,1: Fuse word 43 loading through BSEC_OTPCR is.." bitfld.long 0x4 10. "SRLOCK42,sticky reload lock for fuse word 42" "0: Fuse word 42 loading through BSEC_OTPCR is..,1: Fuse word 42 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 9. "SRLOCK41,sticky reload lock for fuse word 41" "0: Fuse word 41 loading through BSEC_OTPCR is..,1: Fuse word 41 loading through BSEC_OTPCR is.." bitfld.long 0x4 8. "SRLOCK40,sticky reload lock for fuse word 40" "0: Fuse word 40 loading through BSEC_OTPCR is..,1: Fuse word 40 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 7. "SRLOCK39,sticky reload lock for fuse word 39" "0: Fuse word 39 loading through BSEC_OTPCR is..,1: Fuse word 39 loading through BSEC_OTPCR is.." bitfld.long 0x4 6. "SRLOCK38,sticky reload lock for fuse word 38" "0: Fuse word 38 loading through BSEC_OTPCR is..,1: Fuse word 38 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 5. "SRLOCK37,sticky reload lock for fuse word 37" "0: Fuse word 37 loading through BSEC_OTPCR is..,1: Fuse word 37 loading through BSEC_OTPCR is.." bitfld.long 0x4 4. "SRLOCK36,sticky reload lock for fuse word 36" "0: Fuse word 36 loading through BSEC_OTPCR is..,1: Fuse word 36 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 3. "SRLOCK35,sticky reload lock for fuse word 35" "0: Fuse word 35 loading through BSEC_OTPCR is..,1: Fuse word 35 loading through BSEC_OTPCR is.." bitfld.long 0x4 2. "SRLOCK34,sticky reload lock for fuse word 34" "0: Fuse word 34 loading through BSEC_OTPCR is..,1: Fuse word 34 loading through BSEC_OTPCR is.." newline bitfld.long 0x4 1. "SRLOCK33,sticky reload lock for fuse word 33" "0: Fuse word 33 loading through BSEC_OTPCR is..,1: Fuse word 33 loading through BSEC_OTPCR is.." bitfld.long 0x4 0. "SRLOCK32,sticky reload lock for fuse word 32" "0: Fuse word 32 loading through BSEC_OTPCR is..,1: Fuse word 32 loading through BSEC_OTPCR is.." line.long 0x8 "BSEC_SRLOCK2,BSEC sticky reload lock register 2" bitfld.long 0x8 31. "SRLOCK95,sticky reload lock for fuse word 95" "0: Fuse word 95 loading through BSEC_OTPCR is..,1: Fuse word 95 loading through BSEC_OTPCR is.." bitfld.long 0x8 30. "SRLOCK94,sticky reload lock for fuse word 94" "0: Fuse word 94 loading through BSEC_OTPCR is..,1: Fuse word 94 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 29. "SRLOCK93,sticky reload lock for fuse word 93" "0: Fuse word 93 loading through BSEC_OTPCR is..,1: Fuse word 93 loading through BSEC_OTPCR is.." bitfld.long 0x8 28. "SRLOCK92,sticky reload lock for fuse word 92" "0: Fuse word 92 loading through BSEC_OTPCR is..,1: Fuse word 92 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 27. "SRLOCK91,sticky reload lock for fuse word 91" "0: Fuse word 91 loading through BSEC_OTPCR is..,1: Fuse word 91 loading through BSEC_OTPCR is.." bitfld.long 0x8 26. "SRLOCK90,sticky reload lock for fuse word 90" "0: Fuse word 90 loading through BSEC_OTPCR is..,1: Fuse word 90 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 25. "SRLOCK89,sticky reload lock for fuse word 89" "0: Fuse word 89 loading through BSEC_OTPCR is..,1: Fuse word 89 loading through BSEC_OTPCR is.." bitfld.long 0x8 24. "SRLOCK88,sticky reload lock for fuse word 88" "0: Fuse word 88 loading through BSEC_OTPCR is..,1: Fuse word 88 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 23. "SRLOCK87,sticky reload lock for fuse word 87" "0: Fuse word 87 loading through BSEC_OTPCR is..,1: Fuse word 87 loading through BSEC_OTPCR is.." bitfld.long 0x8 22. "SRLOCK86,sticky reload lock for fuse word 86" "0: Fuse word 86 loading through BSEC_OTPCR is..,1: Fuse word 86 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 21. "SRLOCK85,sticky reload lock for fuse word 85" "0: Fuse word 85 loading through BSEC_OTPCR is..,1: Fuse word 85 loading through BSEC_OTPCR is.." bitfld.long 0x8 20. "SRLOCK84,sticky reload lock for fuse word 84" "0: Fuse word 84 loading through BSEC_OTPCR is..,1: Fuse word 84 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 19. "SRLOCK83,sticky reload lock for fuse word 83" "0: Fuse word 83 loading through BSEC_OTPCR is..,1: Fuse word 83 loading through BSEC_OTPCR is.." bitfld.long 0x8 18. "SRLOCK82,sticky reload lock for fuse word 82" "0: Fuse word 82 loading through BSEC_OTPCR is..,1: Fuse word 82 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 17. "SRLOCK81,sticky reload lock for fuse word 81" "0: Fuse word 81 loading through BSEC_OTPCR is..,1: Fuse word 81 loading through BSEC_OTPCR is.." bitfld.long 0x8 16. "SRLOCK80,sticky reload lock for fuse word 80" "0: Fuse word 80 loading through BSEC_OTPCR is..,1: Fuse word 80 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 15. "SRLOCK79,sticky reload lock for fuse word 79" "0: Fuse word 79 loading through BSEC_OTPCR is..,1: Fuse word 79 loading through BSEC_OTPCR is.." bitfld.long 0x8 14. "SRLOCK78,sticky reload lock for fuse word 78" "0: Fuse word 78 loading through BSEC_OTPCR is..,1: Fuse word 78 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 13. "SRLOCK77,sticky reload lock for fuse word 77" "0: Fuse word 77 loading through BSEC_OTPCR is..,1: Fuse word 77 loading through BSEC_OTPCR is.." bitfld.long 0x8 12. "SRLOCK76,sticky reload lock for fuse word 76" "0: Fuse word 76 loading through BSEC_OTPCR is..,1: Fuse word 76 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 11. "SRLOCK75,sticky reload lock for fuse word 75" "0: Fuse word 75 loading through BSEC_OTPCR is..,1: Fuse word 75 loading through BSEC_OTPCR is.." bitfld.long 0x8 10. "SRLOCK74,sticky reload lock for fuse word 74" "0: Fuse word 74 loading through BSEC_OTPCR is..,1: Fuse word 74 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 9. "SRLOCK73,sticky reload lock for fuse word 73" "0: Fuse word 73 loading through BSEC_OTPCR is..,1: Fuse word 73 loading through BSEC_OTPCR is.." bitfld.long 0x8 8. "SRLOCK72,sticky reload lock for fuse word 72" "0: Fuse word 72 loading through BSEC_OTPCR is..,1: Fuse word 72 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 7. "SRLOCK71,sticky reload lock for fuse word 71" "0: Fuse word 71 loading through BSEC_OTPCR is..,1: Fuse word 71 loading through BSEC_OTPCR is.." bitfld.long 0x8 6. "SRLOCK70,sticky reload lock for fuse word 70" "0: Fuse word 70 loading through BSEC_OTPCR is..,1: Fuse word 70 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 5. "SRLOCK69,sticky reload lock for fuse word 69" "0: Fuse word 69 loading through BSEC_OTPCR is..,1: Fuse word 69 loading through BSEC_OTPCR is.." bitfld.long 0x8 4. "SRLOCK68,sticky reload lock for fuse word 68" "0: Fuse word 68 loading through BSEC_OTPCR is..,1: Fuse word 68 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 3. "SRLOCK67,sticky reload lock for fuse word 67" "0: Fuse word 67 loading through BSEC_OTPCR is..,1: Fuse word 67 loading through BSEC_OTPCR is.." bitfld.long 0x8 2. "SRLOCK66,sticky reload lock for fuse word 66" "0: Fuse word 66 loading through BSEC_OTPCR is..,1: Fuse word 66 loading through BSEC_OTPCR is.." newline bitfld.long 0x8 1. "SRLOCK65,sticky reload lock for fuse word 65" "0: Fuse word 65 loading through BSEC_OTPCR is..,1: Fuse word 65 loading through BSEC_OTPCR is.." bitfld.long 0x8 0. "SRLOCK64,sticky reload lock for fuse word 64" "0: Fuse word 64 loading through BSEC_OTPCR is..,1: Fuse word 64 loading through BSEC_OTPCR is.." line.long 0xC "BSEC_SRLOCK3,BSEC sticky reload lock register 3" bitfld.long 0xC 31. "SRLOCK127,sticky reload lock for fuse word 127" "0: Fuse word 127 loading through BSEC_OTPCR is..,1: Fuse word 127 loading through BSEC_OTPCR is.." bitfld.long 0xC 30. "SRLOCK126,sticky reload lock for fuse word 126" "0: Fuse word 126 loading through BSEC_OTPCR is..,1: Fuse word 126 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 29. "SRLOCK125,sticky reload lock for fuse word 125" "0: Fuse word 125 loading through BSEC_OTPCR is..,1: Fuse word 125 loading through BSEC_OTPCR is.." bitfld.long 0xC 28. "SRLOCK124,sticky reload lock for fuse word 124" "0: Fuse word 124 loading through BSEC_OTPCR is..,1: Fuse word 124 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 27. "SRLOCK123,sticky reload lock for fuse word 123" "0: Fuse word 123 loading through BSEC_OTPCR is..,1: Fuse word 123 loading through BSEC_OTPCR is.." bitfld.long 0xC 26. "SRLOCK122,sticky reload lock for fuse word 122" "0: Fuse word 122 loading through BSEC_OTPCR is..,1: Fuse word 122 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 25. "SRLOCK121,sticky reload lock for fuse word 121" "0: Fuse word 121 loading through BSEC_OTPCR is..,1: Fuse word 121 loading through BSEC_OTPCR is.." bitfld.long 0xC 24. "SRLOCK120,sticky reload lock for fuse word 120" "0: Fuse word 120 loading through BSEC_OTPCR is..,1: Fuse word 120 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 23. "SRLOCK119,sticky reload lock for fuse word 119" "0: Fuse word 119 loading through BSEC_OTPCR is..,1: Fuse word 119 loading through BSEC_OTPCR is.." bitfld.long 0xC 22. "SRLOCK118,sticky reload lock for fuse word 118" "0: Fuse word 118 loading through BSEC_OTPCR is..,1: Fuse word 118 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 21. "SRLOCK117,sticky reload lock for fuse word 117" "0: Fuse word 117 loading through BSEC_OTPCR is..,1: Fuse word 117 loading through BSEC_OTPCR is.." bitfld.long 0xC 20. "SRLOCK116,sticky reload lock for fuse word 116" "0: Fuse word 116 loading through BSEC_OTPCR is..,1: Fuse word 116 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 19. "SRLOCK115,sticky reload lock for fuse word 115" "0: Fuse word 115 loading through BSEC_OTPCR is..,1: Fuse word 115 loading through BSEC_OTPCR is.." bitfld.long 0xC 18. "SRLOCK114,sticky reload lock for fuse word 114" "0: Fuse word 114 loading through BSEC_OTPCR is..,1: Fuse word 114 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 17. "SRLOCK113,sticky reload lock for fuse word 113" "0: Fuse word 113 loading through BSEC_OTPCR is..,1: Fuse word 113 loading through BSEC_OTPCR is.." bitfld.long 0xC 16. "SRLOCK112,sticky reload lock for fuse word 112" "0: Fuse word 112 loading through BSEC_OTPCR is..,1: Fuse word 112 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 15. "SRLOCK111,sticky reload lock for fuse word 111" "0: Fuse word 111 loading through BSEC_OTPCR is..,1: Fuse word 111 loading through BSEC_OTPCR is.." bitfld.long 0xC 14. "SRLOCK110,sticky reload lock for fuse word 110" "0: Fuse word 110 loading through BSEC_OTPCR is..,1: Fuse word 110 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 13. "SRLOCK109,sticky reload lock for fuse word 109" "0: Fuse word 109 loading through BSEC_OTPCR is..,1: Fuse word 109 loading through BSEC_OTPCR is.." bitfld.long 0xC 12. "SRLOCK108,sticky reload lock for fuse word 108" "0: Fuse word 108 loading through BSEC_OTPCR is..,1: Fuse word 108 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 11. "SRLOCK107,sticky reload lock for fuse word 107" "0: Fuse word 107 loading through BSEC_OTPCR is..,1: Fuse word 107 loading through BSEC_OTPCR is.." bitfld.long 0xC 10. "SRLOCK106,sticky reload lock for fuse word 106" "0: Fuse word 106 loading through BSEC_OTPCR is..,1: Fuse word 106 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 9. "SRLOCK105,sticky reload lock for fuse word 105" "0: Fuse word 105 loading through BSEC_OTPCR is..,1: Fuse word 105 loading through BSEC_OTPCR is.." bitfld.long 0xC 8. "SRLOCK104,sticky reload lock for fuse word 104" "0: Fuse word 104 loading through BSEC_OTPCR is..,1: Fuse word 104 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 7. "SRLOCK103,sticky reload lock for fuse word 103" "0: Fuse word 103 loading through BSEC_OTPCR is..,1: Fuse word 103 loading through BSEC_OTPCR is.." bitfld.long 0xC 6. "SRLOCK102,sticky reload lock for fuse word 102" "0: Fuse word 102 loading through BSEC_OTPCR is..,1: Fuse word 102 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 5. "SRLOCK101,sticky reload lock for fuse word 101" "0: Fuse word 101 loading through BSEC_OTPCR is..,1: Fuse word 101 loading through BSEC_OTPCR is.." bitfld.long 0xC 4. "SRLOCK100,sticky reload lock for fuse word 100" "0: Fuse word 100 loading through BSEC_OTPCR is..,1: Fuse word 100 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 3. "SRLOCK99,sticky reload lock for fuse word 99" "0: Fuse word 99 loading through BSEC_OTPCR is..,1: Fuse word 99 loading through BSEC_OTPCR is.." bitfld.long 0xC 2. "SRLOCK98,sticky reload lock for fuse word 98" "0: Fuse word 98 loading through BSEC_OTPCR is..,1: Fuse word 98 loading through BSEC_OTPCR is.." newline bitfld.long 0xC 1. "SRLOCK97,sticky reload lock for fuse word 97" "0: Fuse word 97 loading through BSEC_OTPCR is..,1: Fuse word 97 loading through BSEC_OTPCR is.." bitfld.long 0xC 0. "SRLOCK96,sticky reload lock for fuse word 96" "0: Fuse word 96 loading through BSEC_OTPCR is..,1: Fuse word 96 loading through BSEC_OTPCR is.." line.long 0x10 "BSEC_SRLOCK4,BSEC sticky reload lock register 4" bitfld.long 0x10 31. "SRLOCK159,sticky reload lock for fuse word 159" "0: Fuse word 159 loading through BSEC_OTPCR is..,1: Fuse word 159 loading through BSEC_OTPCR is.." bitfld.long 0x10 30. "SRLOCK158,sticky reload lock for fuse word 158" "0: Fuse word 158 loading through BSEC_OTPCR is..,1: Fuse word 158 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 29. "SRLOCK157,sticky reload lock for fuse word 157" "0: Fuse word 157 loading through BSEC_OTPCR is..,1: Fuse word 157 loading through BSEC_OTPCR is.." bitfld.long 0x10 28. "SRLOCK156,sticky reload lock for fuse word 156" "0: Fuse word 156 loading through BSEC_OTPCR is..,1: Fuse word 156 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 27. "SRLOCK155,sticky reload lock for fuse word 155" "0: Fuse word 155 loading through BSEC_OTPCR is..,1: Fuse word 155 loading through BSEC_OTPCR is.." bitfld.long 0x10 26. "SRLOCK154,sticky reload lock for fuse word 154" "0: Fuse word 154 loading through BSEC_OTPCR is..,1: Fuse word 154 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 25. "SRLOCK153,sticky reload lock for fuse word 153" "0: Fuse word 153 loading through BSEC_OTPCR is..,1: Fuse word 153 loading through BSEC_OTPCR is.." bitfld.long 0x10 24. "SRLOCK152,sticky reload lock for fuse word 152" "0: Fuse word 152 loading through BSEC_OTPCR is..,1: Fuse word 152 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 23. "SRLOCK151,sticky reload lock for fuse word 151" "0: Fuse word 151 loading through BSEC_OTPCR is..,1: Fuse word 151 loading through BSEC_OTPCR is.." bitfld.long 0x10 22. "SRLOCK150,sticky reload lock for fuse word 150" "0: Fuse word 150 loading through BSEC_OTPCR is..,1: Fuse word 150 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 21. "SRLOCK149,sticky reload lock for fuse word 149" "0: Fuse word 149 loading through BSEC_OTPCR is..,1: Fuse word 149 loading through BSEC_OTPCR is.." bitfld.long 0x10 20. "SRLOCK148,sticky reload lock for fuse word 148" "0: Fuse word 148 loading through BSEC_OTPCR is..,1: Fuse word 148 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 19. "SRLOCK147,sticky reload lock for fuse word 147" "0: Fuse word 147 loading through BSEC_OTPCR is..,1: Fuse word 147 loading through BSEC_OTPCR is.." bitfld.long 0x10 18. "SRLOCK146,sticky reload lock for fuse word 146" "0: Fuse word 146 loading through BSEC_OTPCR is..,1: Fuse word 146 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 17. "SRLOCK145,sticky reload lock for fuse word 145" "0: Fuse word 145 loading through BSEC_OTPCR is..,1: Fuse word 145 loading through BSEC_OTPCR is.." bitfld.long 0x10 16. "SRLOCK144,sticky reload lock for fuse word 144" "0: Fuse word 144 loading through BSEC_OTPCR is..,1: Fuse word 144 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 15. "SRLOCK143,sticky reload lock for fuse word 143" "0: Fuse word 143 loading through BSEC_OTPCR is..,1: Fuse word 143 loading through BSEC_OTPCR is.." bitfld.long 0x10 14. "SRLOCK142,sticky reload lock for fuse word 142" "0: Fuse word 142 loading through BSEC_OTPCR is..,1: Fuse word 142 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 13. "SRLOCK141,sticky reload lock for fuse word 141" "0: Fuse word 141 loading through BSEC_OTPCR is..,1: Fuse word 141 loading through BSEC_OTPCR is.." bitfld.long 0x10 12. "SRLOCK140,sticky reload lock for fuse word 140" "0: Fuse word 140 loading through BSEC_OTPCR is..,1: Fuse word 140 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 11. "SRLOCK139,sticky reload lock for fuse word 139" "0: Fuse word 139 loading through BSEC_OTPCR is..,1: Fuse word 139 loading through BSEC_OTPCR is.." bitfld.long 0x10 10. "SRLOCK138,sticky reload lock for fuse word 138" "0: Fuse word 138 loading through BSEC_OTPCR is..,1: Fuse word 138 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 9. "SRLOCK137,sticky reload lock for fuse word 137" "0: Fuse word 137 loading through BSEC_OTPCR is..,1: Fuse word 137 loading through BSEC_OTPCR is.." bitfld.long 0x10 8. "SRLOCK136,sticky reload lock for fuse word 136" "0: Fuse word 136 loading through BSEC_OTPCR is..,1: Fuse word 136 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 7. "SRLOCK135,sticky reload lock for fuse word 135" "0: Fuse word 135 loading through BSEC_OTPCR is..,1: Fuse word 135 loading through BSEC_OTPCR is.." bitfld.long 0x10 6. "SRLOCK134,sticky reload lock for fuse word 134" "0: Fuse word 134 loading through BSEC_OTPCR is..,1: Fuse word 134 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 5. "SRLOCK133,sticky reload lock for fuse word 133" "0: Fuse word 133 loading through BSEC_OTPCR is..,1: Fuse word 133 loading through BSEC_OTPCR is.." bitfld.long 0x10 4. "SRLOCK132,sticky reload lock for fuse word 132" "0: Fuse word 132 loading through BSEC_OTPCR is..,1: Fuse word 132 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 3. "SRLOCK131,sticky reload lock for fuse word 131" "0: Fuse word 131 loading through BSEC_OTPCR is..,1: Fuse word 131 loading through BSEC_OTPCR is.." bitfld.long 0x10 2. "SRLOCK130,sticky reload lock for fuse word 130" "0: Fuse word 130 loading through BSEC_OTPCR is..,1: Fuse word 130 loading through BSEC_OTPCR is.." newline bitfld.long 0x10 1. "SRLOCK129,sticky reload lock for fuse word 129" "0: Fuse word 129 loading through BSEC_OTPCR is..,1: Fuse word 129 loading through BSEC_OTPCR is.." bitfld.long 0x10 0. "SRLOCK128,sticky reload lock for fuse word 128" "0: Fuse word 128 loading through BSEC_OTPCR is..,1: Fuse word 128 loading through BSEC_OTPCR is.." line.long 0x14 "BSEC_SRLOCK5,BSEC sticky reload lock register 5" bitfld.long 0x14 31. "SRLOCK191,sticky reload lock for fuse word 191" "0: Fuse word 191 loading through BSEC_OTPCR is..,1: Fuse word 191 loading through BSEC_OTPCR is.." bitfld.long 0x14 30. "SRLOCK190,sticky reload lock for fuse word 190" "0: Fuse word 190 loading through BSEC_OTPCR is..,1: Fuse word 190 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 29. "SRLOCK189,sticky reload lock for fuse word 189" "0: Fuse word 189 loading through BSEC_OTPCR is..,1: Fuse word 189 loading through BSEC_OTPCR is.." bitfld.long 0x14 28. "SRLOCK188,sticky reload lock for fuse word 188" "0: Fuse word 188 loading through BSEC_OTPCR is..,1: Fuse word 188 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 27. "SRLOCK187,sticky reload lock for fuse word 187" "0: Fuse word 187 loading through BSEC_OTPCR is..,1: Fuse word 187 loading through BSEC_OTPCR is.." bitfld.long 0x14 26. "SRLOCK186,sticky reload lock for fuse word 186" "0: Fuse word 186 loading through BSEC_OTPCR is..,1: Fuse word 186 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 25. "SRLOCK185,sticky reload lock for fuse word 185" "0: Fuse word 185 loading through BSEC_OTPCR is..,1: Fuse word 185 loading through BSEC_OTPCR is.." bitfld.long 0x14 24. "SRLOCK184,sticky reload lock for fuse word 184" "0: Fuse word 184 loading through BSEC_OTPCR is..,1: Fuse word 184 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 23. "SRLOCK183,sticky reload lock for fuse word 183" "0: Fuse word 183 loading through BSEC_OTPCR is..,1: Fuse word 183 loading through BSEC_OTPCR is.." bitfld.long 0x14 22. "SRLOCK182,sticky reload lock for fuse word 182" "0: Fuse word 182 loading through BSEC_OTPCR is..,1: Fuse word 182 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 21. "SRLOCK181,sticky reload lock for fuse word 181" "0: Fuse word 181 loading through BSEC_OTPCR is..,1: Fuse word 181 loading through BSEC_OTPCR is.." bitfld.long 0x14 20. "SRLOCK180,sticky reload lock for fuse word 180" "0: Fuse word 180 loading through BSEC_OTPCR is..,1: Fuse word 180 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 19. "SRLOCK179,sticky reload lock for fuse word 179" "0: Fuse word 179 loading through BSEC_OTPCR is..,1: Fuse word 179 loading through BSEC_OTPCR is.." bitfld.long 0x14 18. "SRLOCK178,sticky reload lock for fuse word 178" "0: Fuse word 178 loading through BSEC_OTPCR is..,1: Fuse word 178 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 17. "SRLOCK177,sticky reload lock for fuse word 177" "0: Fuse word 177 loading through BSEC_OTPCR is..,1: Fuse word 177 loading through BSEC_OTPCR is.." bitfld.long 0x14 16. "SRLOCK176,sticky reload lock for fuse word 176" "0: Fuse word 176 loading through BSEC_OTPCR is..,1: Fuse word 176 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 15. "SRLOCK175,sticky reload lock for fuse word 175" "0: Fuse word 175 loading through BSEC_OTPCR is..,1: Fuse word 175 loading through BSEC_OTPCR is.." bitfld.long 0x14 14. "SRLOCK174,sticky reload lock for fuse word 174" "0: Fuse word 174 loading through BSEC_OTPCR is..,1: Fuse word 174 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 13. "SRLOCK173,sticky reload lock for fuse word 173" "0: Fuse word 173 loading through BSEC_OTPCR is..,1: Fuse word 173 loading through BSEC_OTPCR is.." bitfld.long 0x14 12. "SRLOCK172,sticky reload lock for fuse word 172" "0: Fuse word 172 loading through BSEC_OTPCR is..,1: Fuse word 172 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 11. "SRLOCK171,sticky reload lock for fuse word 171" "0: Fuse word 171 loading through BSEC_OTPCR is..,1: Fuse word 171 loading through BSEC_OTPCR is.." bitfld.long 0x14 10. "SRLOCK170,sticky reload lock for fuse word 170" "0: Fuse word 170 loading through BSEC_OTPCR is..,1: Fuse word 170 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 9. "SRLOCK169,sticky reload lock for fuse word 169" "0: Fuse word 169 loading through BSEC_OTPCR is..,1: Fuse word 169 loading through BSEC_OTPCR is.." bitfld.long 0x14 8. "SRLOCK168,sticky reload lock for fuse word 168" "0: Fuse word 168 loading through BSEC_OTPCR is..,1: Fuse word 168 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 7. "SRLOCK167,sticky reload lock for fuse word 167" "0: Fuse word 167 loading through BSEC_OTPCR is..,1: Fuse word 167 loading through BSEC_OTPCR is.." bitfld.long 0x14 6. "SRLOCK166,sticky reload lock for fuse word 166" "0: Fuse word 166 loading through BSEC_OTPCR is..,1: Fuse word 166 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 5. "SRLOCK165,sticky reload lock for fuse word 165" "0: Fuse word 165 loading through BSEC_OTPCR is..,1: Fuse word 165 loading through BSEC_OTPCR is.." bitfld.long 0x14 4. "SRLOCK164,sticky reload lock for fuse word 164" "0: Fuse word 164 loading through BSEC_OTPCR is..,1: Fuse word 164 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 3. "SRLOCK163,sticky reload lock for fuse word 163" "0: Fuse word 163 loading through BSEC_OTPCR is..,1: Fuse word 163 loading through BSEC_OTPCR is.." bitfld.long 0x14 2. "SRLOCK162,sticky reload lock for fuse word 162" "0: Fuse word 162 loading through BSEC_OTPCR is..,1: Fuse word 162 loading through BSEC_OTPCR is.." newline bitfld.long 0x14 1. "SRLOCK161,sticky reload lock for fuse word 161" "0: Fuse word 161 loading through BSEC_OTPCR is..,1: Fuse word 161 loading through BSEC_OTPCR is.." bitfld.long 0x14 0. "SRLOCK160,sticky reload lock for fuse word 160" "0: Fuse word 160 loading through BSEC_OTPCR is..,1: Fuse word 160 loading through BSEC_OTPCR is.." line.long 0x18 "BSEC_SRLOCK6,BSEC sticky reload lock register 6" bitfld.long 0x18 31. "SRLOCK223,sticky reload lock for fuse word 223" "0: Fuse word 223 loading through BSEC_OTPCR is..,1: Fuse word 223 loading through BSEC_OTPCR is.." bitfld.long 0x18 30. "SRLOCK222,sticky reload lock for fuse word 222" "0: Fuse word 222 loading through BSEC_OTPCR is..,1: Fuse word 222 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 29. "SRLOCK221,sticky reload lock for fuse word 221" "0: Fuse word 221 loading through BSEC_OTPCR is..,1: Fuse word 221 loading through BSEC_OTPCR is.." bitfld.long 0x18 28. "SRLOCK220,sticky reload lock for fuse word 220" "0: Fuse word 220 loading through BSEC_OTPCR is..,1: Fuse word 220 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 27. "SRLOCK219,sticky reload lock for fuse word 219" "0: Fuse word 219 loading through BSEC_OTPCR is..,1: Fuse word 219 loading through BSEC_OTPCR is.." bitfld.long 0x18 26. "SRLOCK218,sticky reload lock for fuse word 218" "0: Fuse word 218 loading through BSEC_OTPCR is..,1: Fuse word 218 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 25. "SRLOCK217,sticky reload lock for fuse word 217" "0: Fuse word 217 loading through BSEC_OTPCR is..,1: Fuse word 217 loading through BSEC_OTPCR is.." bitfld.long 0x18 24. "SRLOCK216,sticky reload lock for fuse word 216" "0: Fuse word 216 loading through BSEC_OTPCR is..,1: Fuse word 216 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 23. "SRLOCK215,sticky reload lock for fuse word 215" "0: Fuse word 215 loading through BSEC_OTPCR is..,1: Fuse word 215 loading through BSEC_OTPCR is.." bitfld.long 0x18 22. "SRLOCK214,sticky reload lock for fuse word 214" "0: Fuse word 214 loading through BSEC_OTPCR is..,1: Fuse word 214 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 21. "SRLOCK213,sticky reload lock for fuse word 213" "0: Fuse word 213 loading through BSEC_OTPCR is..,1: Fuse word 213 loading through BSEC_OTPCR is.." bitfld.long 0x18 20. "SRLOCK212,sticky reload lock for fuse word 212" "0: Fuse word 212 loading through BSEC_OTPCR is..,1: Fuse word 212 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 19. "SRLOCK211,sticky reload lock for fuse word 211" "0: Fuse word 211 loading through BSEC_OTPCR is..,1: Fuse word 211 loading through BSEC_OTPCR is.." bitfld.long 0x18 18. "SRLOCK210,sticky reload lock for fuse word 210" "0: Fuse word 210 loading through BSEC_OTPCR is..,1: Fuse word 210 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 17. "SRLOCK209,sticky reload lock for fuse word 209" "0: Fuse word 209 loading through BSEC_OTPCR is..,1: Fuse word 209 loading through BSEC_OTPCR is.." bitfld.long 0x18 16. "SRLOCK208,sticky reload lock for fuse word 208" "0: Fuse word 208 loading through BSEC_OTPCR is..,1: Fuse word 208 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 15. "SRLOCK207,sticky reload lock for fuse word 207" "0: Fuse word 207 loading through BSEC_OTPCR is..,1: Fuse word 207 loading through BSEC_OTPCR is.." bitfld.long 0x18 14. "SRLOCK206,sticky reload lock for fuse word 206" "0: Fuse word 206 loading through BSEC_OTPCR is..,1: Fuse word 206 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 13. "SRLOCK205,sticky reload lock for fuse word 205" "0: Fuse word 205 loading through BSEC_OTPCR is..,1: Fuse word 205 loading through BSEC_OTPCR is.." bitfld.long 0x18 12. "SRLOCK204,sticky reload lock for fuse word 204" "0: Fuse word 204 loading through BSEC_OTPCR is..,1: Fuse word 204 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 11. "SRLOCK203,sticky reload lock for fuse word 203" "0: Fuse word 203 loading through BSEC_OTPCR is..,1: Fuse word 203 loading through BSEC_OTPCR is.." bitfld.long 0x18 10. "SRLOCK202,sticky reload lock for fuse word 202" "0: Fuse word 202 loading through BSEC_OTPCR is..,1: Fuse word 202 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 9. "SRLOCK201,sticky reload lock for fuse word 201" "0: Fuse word 201 loading through BSEC_OTPCR is..,1: Fuse word 201 loading through BSEC_OTPCR is.." bitfld.long 0x18 8. "SRLOCK200,sticky reload lock for fuse word 200" "0: Fuse word 200 loading through BSEC_OTPCR is..,1: Fuse word 200 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 7. "SRLOCK199,sticky reload lock for fuse word 199" "0: Fuse word 199 loading through BSEC_OTPCR is..,1: Fuse word 199 loading through BSEC_OTPCR is.." bitfld.long 0x18 6. "SRLOCK198,sticky reload lock for fuse word 198" "0: Fuse word 198 loading through BSEC_OTPCR is..,1: Fuse word 198 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 5. "SRLOCK197,sticky reload lock for fuse word 197" "0: Fuse word 197 loading through BSEC_OTPCR is..,1: Fuse word 197 loading through BSEC_OTPCR is.." bitfld.long 0x18 4. "SRLOCK196,sticky reload lock for fuse word 196" "0: Fuse word 196 loading through BSEC_OTPCR is..,1: Fuse word 196 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 3. "SRLOCK195,sticky reload lock for fuse word 195" "0: Fuse word 195 loading through BSEC_OTPCR is..,1: Fuse word 195 loading through BSEC_OTPCR is.." bitfld.long 0x18 2. "SRLOCK194,sticky reload lock for fuse word 194" "0: Fuse word 194 loading through BSEC_OTPCR is..,1: Fuse word 194 loading through BSEC_OTPCR is.." newline bitfld.long 0x18 1. "SRLOCK193,sticky reload lock for fuse word 193" "0: Fuse word 193 loading through BSEC_OTPCR is..,1: Fuse word 193 loading through BSEC_OTPCR is.." bitfld.long 0x18 0. "SRLOCK192,sticky reload lock for fuse word 192" "0: Fuse word 192 loading through BSEC_OTPCR is..,1: Fuse word 192 loading through BSEC_OTPCR is.." line.long 0x1C "BSEC_SRLOCK7,BSEC sticky reload lock register 7" bitfld.long 0x1C 31. "SRLOCK255,sticky reload lock for fuse word 255" "0: Fuse word 255 loading through BSEC_OTPCR is..,1: Fuse word 255 loading through BSEC_OTPCR is.." bitfld.long 0x1C 30. "SRLOCK254,sticky reload lock for fuse word 254" "0: Fuse word 254 loading through BSEC_OTPCR is..,1: Fuse word 254 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 29. "SRLOCK253,sticky reload lock for fuse word 253" "0: Fuse word 253 loading through BSEC_OTPCR is..,1: Fuse word 253 loading through BSEC_OTPCR is.." bitfld.long 0x1C 28. "SRLOCK252,sticky reload lock for fuse word 252" "0: Fuse word 252 loading through BSEC_OTPCR is..,1: Fuse word 252 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 27. "SRLOCK251,sticky reload lock for fuse word 251" "0: Fuse word 251 loading through BSEC_OTPCR is..,1: Fuse word 251 loading through BSEC_OTPCR is.." bitfld.long 0x1C 26. "SRLOCK250,sticky reload lock for fuse word 250" "0: Fuse word 250 loading through BSEC_OTPCR is..,1: Fuse word 250 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 25. "SRLOCK249,sticky reload lock for fuse word 249" "0: Fuse word 249 loading through BSEC_OTPCR is..,1: Fuse word 249 loading through BSEC_OTPCR is.." bitfld.long 0x1C 24. "SRLOCK248,sticky reload lock for fuse word 248" "0: Fuse word 248 loading through BSEC_OTPCR is..,1: Fuse word 248 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 23. "SRLOCK247,sticky reload lock for fuse word 247" "0: Fuse word 247 loading through BSEC_OTPCR is..,1: Fuse word 247 loading through BSEC_OTPCR is.." bitfld.long 0x1C 22. "SRLOCK246,sticky reload lock for fuse word 246" "0: Fuse word 246 loading through BSEC_OTPCR is..,1: Fuse word 246 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 21. "SRLOCK245,sticky reload lock for fuse word 245" "0: Fuse word 245 loading through BSEC_OTPCR is..,1: Fuse word 245 loading through BSEC_OTPCR is.." bitfld.long 0x1C 20. "SRLOCK244,sticky reload lock for fuse word 244" "0: Fuse word 244 loading through BSEC_OTPCR is..,1: Fuse word 244 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 19. "SRLOCK243,sticky reload lock for fuse word 243" "0: Fuse word 243 loading through BSEC_OTPCR is..,1: Fuse word 243 loading through BSEC_OTPCR is.." bitfld.long 0x1C 18. "SRLOCK242,sticky reload lock for fuse word 242" "0: Fuse word 242 loading through BSEC_OTPCR is..,1: Fuse word 242 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 17. "SRLOCK241,sticky reload lock for fuse word 241" "0: Fuse word 241 loading through BSEC_OTPCR is..,1: Fuse word 241 loading through BSEC_OTPCR is.." bitfld.long 0x1C 16. "SRLOCK240,sticky reload lock for fuse word 240" "0: Fuse word 240 loading through BSEC_OTPCR is..,1: Fuse word 240 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 15. "SRLOCK239,sticky reload lock for fuse word 239" "0: Fuse word 239 loading through BSEC_OTPCR is..,1: Fuse word 239 loading through BSEC_OTPCR is.." bitfld.long 0x1C 14. "SRLOCK238,sticky reload lock for fuse word 238" "0: Fuse word 238 loading through BSEC_OTPCR is..,1: Fuse word 238 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 13. "SRLOCK237,sticky reload lock for fuse word 237" "0: Fuse word 237 loading through BSEC_OTPCR is..,1: Fuse word 237 loading through BSEC_OTPCR is.." bitfld.long 0x1C 12. "SRLOCK236,sticky reload lock for fuse word 236" "0: Fuse word 236 loading through BSEC_OTPCR is..,1: Fuse word 236 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 11. "SRLOCK235,sticky reload lock for fuse word 235" "0: Fuse word 235 loading through BSEC_OTPCR is..,1: Fuse word 235 loading through BSEC_OTPCR is.." bitfld.long 0x1C 10. "SRLOCK234,sticky reload lock for fuse word 234" "0: Fuse word 234 loading through BSEC_OTPCR is..,1: Fuse word 234 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 9. "SRLOCK233,sticky reload lock for fuse word 233" "0: Fuse word 233 loading through BSEC_OTPCR is..,1: Fuse word 233 loading through BSEC_OTPCR is.." bitfld.long 0x1C 8. "SRLOCK232,sticky reload lock for fuse word 232" "0: Fuse word 232 loading through BSEC_OTPCR is..,1: Fuse word 232 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 7. "SRLOCK231,sticky reload lock for fuse word 231" "0: Fuse word 231 loading through BSEC_OTPCR is..,1: Fuse word 231 loading through BSEC_OTPCR is.." bitfld.long 0x1C 6. "SRLOCK230,sticky reload lock for fuse word 230" "0: Fuse word 230 loading through BSEC_OTPCR is..,1: Fuse word 230 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 5. "SRLOCK229,sticky reload lock for fuse word 229" "0: Fuse word 229 loading through BSEC_OTPCR is..,1: Fuse word 229 loading through BSEC_OTPCR is.." bitfld.long 0x1C 4. "SRLOCK228,sticky reload lock for fuse word 228" "0: Fuse word 228 loading through BSEC_OTPCR is..,1: Fuse word 228 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 3. "SRLOCK227,sticky reload lock for fuse word 227" "0: Fuse word 227 loading through BSEC_OTPCR is..,1: Fuse word 227 loading through BSEC_OTPCR is.." bitfld.long 0x1C 2. "SRLOCK226,sticky reload lock for fuse word 226" "0: Fuse word 226 loading through BSEC_OTPCR is..,1: Fuse word 226 loading through BSEC_OTPCR is.." newline bitfld.long 0x1C 1. "SRLOCK225,sticky reload lock for fuse word 225" "0: Fuse word 225 loading through BSEC_OTPCR is..,1: Fuse word 225 loading through BSEC_OTPCR is.." bitfld.long 0x1C 0. "SRLOCK224,sticky reload lock for fuse word 224" "0: Fuse word 224 loading through BSEC_OTPCR is..,1: Fuse word 224 loading through BSEC_OTPCR is.." line.long 0x20 "BSEC_SRLOCK8,BSEC sticky reload lock register 8" bitfld.long 0x20 31. "SRLOCK287,sticky reload lock for fuse word 287" "0: Fuse word 287 loading through BSEC_OTPCR is..,1: Fuse word 287 loading through BSEC_OTPCR is.." bitfld.long 0x20 30. "SRLOCK286,sticky reload lock for fuse word 286" "0: Fuse word 286 loading through BSEC_OTPCR is..,1: Fuse word 286 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 29. "SRLOCK285,sticky reload lock for fuse word 285" "0: Fuse word 285 loading through BSEC_OTPCR is..,1: Fuse word 285 loading through BSEC_OTPCR is.." bitfld.long 0x20 28. "SRLOCK284,sticky reload lock for fuse word 284" "0: Fuse word 284 loading through BSEC_OTPCR is..,1: Fuse word 284 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 27. "SRLOCK283,sticky reload lock for fuse word 283" "0: Fuse word 283 loading through BSEC_OTPCR is..,1: Fuse word 283 loading through BSEC_OTPCR is.." bitfld.long 0x20 26. "SRLOCK282,sticky reload lock for fuse word 282" "0: Fuse word 282 loading through BSEC_OTPCR is..,1: Fuse word 282 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 25. "SRLOCK281,sticky reload lock for fuse word 281" "0: Fuse word 281 loading through BSEC_OTPCR is..,1: Fuse word 281 loading through BSEC_OTPCR is.." bitfld.long 0x20 24. "SRLOCK280,sticky reload lock for fuse word 280" "0: Fuse word 280 loading through BSEC_OTPCR is..,1: Fuse word 280 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 23. "SRLOCK279,sticky reload lock for fuse word 279" "0: Fuse word 279 loading through BSEC_OTPCR is..,1: Fuse word 279 loading through BSEC_OTPCR is.." bitfld.long 0x20 22. "SRLOCK278,sticky reload lock for fuse word 278" "0: Fuse word 278 loading through BSEC_OTPCR is..,1: Fuse word 278 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 21. "SRLOCK277,sticky reload lock for fuse word 277" "0: Fuse word 277 loading through BSEC_OTPCR is..,1: Fuse word 277 loading through BSEC_OTPCR is.." bitfld.long 0x20 20. "SRLOCK276,sticky reload lock for fuse word 276" "0: Fuse word 276 loading through BSEC_OTPCR is..,1: Fuse word 276 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 19. "SRLOCK275,sticky reload lock for fuse word 275" "0: Fuse word 275 loading through BSEC_OTPCR is..,1: Fuse word 275 loading through BSEC_OTPCR is.." bitfld.long 0x20 18. "SRLOCK274,sticky reload lock for fuse word 274" "0: Fuse word 274 loading through BSEC_OTPCR is..,1: Fuse word 274 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 17. "SRLOCK273,sticky reload lock for fuse word 273" "0: Fuse word 273 loading through BSEC_OTPCR is..,1: Fuse word 273 loading through BSEC_OTPCR is.." bitfld.long 0x20 16. "SRLOCK272,sticky reload lock for fuse word 272" "0: Fuse word 272 loading through BSEC_OTPCR is..,1: Fuse word 272 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 15. "SRLOCK271,sticky reload lock for fuse word 271" "0: Fuse word 271 loading through BSEC_OTPCR is..,1: Fuse word 271 loading through BSEC_OTPCR is.." bitfld.long 0x20 14. "SRLOCK270,sticky reload lock for fuse word 270" "0: Fuse word 270 loading through BSEC_OTPCR is..,1: Fuse word 270 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 13. "SRLOCK269,sticky reload lock for fuse word 269" "0: Fuse word 269 loading through BSEC_OTPCR is..,1: Fuse word 269 loading through BSEC_OTPCR is.." bitfld.long 0x20 12. "SRLOCK268,sticky reload lock for fuse word 268" "0: Fuse word 268 loading through BSEC_OTPCR is..,1: Fuse word 268 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 11. "SRLOCK267,sticky reload lock for fuse word 267" "0: Fuse word 267 loading through BSEC_OTPCR is..,1: Fuse word 267 loading through BSEC_OTPCR is.." bitfld.long 0x20 10. "SRLOCK266,sticky reload lock for fuse word 266" "0: Fuse word 266 loading through BSEC_OTPCR is..,1: Fuse word 266 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 9. "SRLOCK265,sticky reload lock for fuse word 265" "0: Fuse word 265 loading through BSEC_OTPCR is..,1: Fuse word 265 loading through BSEC_OTPCR is.." bitfld.long 0x20 8. "SRLOCK264,sticky reload lock for fuse word 264" "0: Fuse word 264 loading through BSEC_OTPCR is..,1: Fuse word 264 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 7. "SRLOCK263,sticky reload lock for fuse word 263" "0: Fuse word 263 loading through BSEC_OTPCR is..,1: Fuse word 263 loading through BSEC_OTPCR is.." bitfld.long 0x20 6. "SRLOCK262,sticky reload lock for fuse word 262" "0: Fuse word 262 loading through BSEC_OTPCR is..,1: Fuse word 262 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 5. "SRLOCK261,sticky reload lock for fuse word 261" "0: Fuse word 261 loading through BSEC_OTPCR is..,1: Fuse word 261 loading through BSEC_OTPCR is.." bitfld.long 0x20 4. "SRLOCK260,sticky reload lock for fuse word 260" "0: Fuse word 260 loading through BSEC_OTPCR is..,1: Fuse word 260 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 3. "SRLOCK259,sticky reload lock for fuse word 259" "0: Fuse word 259 loading through BSEC_OTPCR is..,1: Fuse word 259 loading through BSEC_OTPCR is.." bitfld.long 0x20 2. "SRLOCK258,sticky reload lock for fuse word 258" "0: Fuse word 258 loading through BSEC_OTPCR is..,1: Fuse word 258 loading through BSEC_OTPCR is.." newline bitfld.long 0x20 1. "SRLOCK257,sticky reload lock for fuse word 257" "0: Fuse word 257 loading through BSEC_OTPCR is..,1: Fuse word 257 loading through BSEC_OTPCR is.." bitfld.long 0x20 0. "SRLOCK256,sticky reload lock for fuse word 256" "0: Fuse word 256 loading through BSEC_OTPCR is..,1: Fuse word 256 loading through BSEC_OTPCR is.." line.long 0x24 "BSEC_SRLOCK9,BSEC sticky reload lock register 9" bitfld.long 0x24 31. "SRLOCK319,sticky reload lock for fuse word 319" "0: Fuse word 319 loading through BSEC_OTPCR is..,1: Fuse word 319 loading through BSEC_OTPCR is.." bitfld.long 0x24 30. "SRLOCK318,sticky reload lock for fuse word 318" "0: Fuse word 318 loading through BSEC_OTPCR is..,1: Fuse word 318 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 29. "SRLOCK317,sticky reload lock for fuse word 317" "0: Fuse word 317 loading through BSEC_OTPCR is..,1: Fuse word 317 loading through BSEC_OTPCR is.." bitfld.long 0x24 28. "SRLOCK316,sticky reload lock for fuse word 316" "0: Fuse word 316 loading through BSEC_OTPCR is..,1: Fuse word 316 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 27. "SRLOCK315,sticky reload lock for fuse word 315" "0: Fuse word 315 loading through BSEC_OTPCR is..,1: Fuse word 315 loading through BSEC_OTPCR is.." bitfld.long 0x24 26. "SRLOCK314,sticky reload lock for fuse word 314" "0: Fuse word 314 loading through BSEC_OTPCR is..,1: Fuse word 314 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 25. "SRLOCK313,sticky reload lock for fuse word 313" "0: Fuse word 313 loading through BSEC_OTPCR is..,1: Fuse word 313 loading through BSEC_OTPCR is.." bitfld.long 0x24 24. "SRLOCK312,sticky reload lock for fuse word 312" "0: Fuse word 312 loading through BSEC_OTPCR is..,1: Fuse word 312 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 23. "SRLOCK311,sticky reload lock for fuse word 311" "0: Fuse word 311 loading through BSEC_OTPCR is..,1: Fuse word 311 loading through BSEC_OTPCR is.." bitfld.long 0x24 22. "SRLOCK310,sticky reload lock for fuse word 310" "0: Fuse word 310 loading through BSEC_OTPCR is..,1: Fuse word 310 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 21. "SRLOCK309,sticky reload lock for fuse word 309" "0: Fuse word 309 loading through BSEC_OTPCR is..,1: Fuse word 309 loading through BSEC_OTPCR is.." bitfld.long 0x24 20. "SRLOCK308,sticky reload lock for fuse word 308" "0: Fuse word 308 loading through BSEC_OTPCR is..,1: Fuse word 308 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 19. "SRLOCK307,sticky reload lock for fuse word 307" "0: Fuse word 307 loading through BSEC_OTPCR is..,1: Fuse word 307 loading through BSEC_OTPCR is.." bitfld.long 0x24 18. "SRLOCK306,sticky reload lock for fuse word 306" "0: Fuse word 306 loading through BSEC_OTPCR is..,1: Fuse word 306 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 17. "SRLOCK305,sticky reload lock for fuse word 305" "0: Fuse word 305 loading through BSEC_OTPCR is..,1: Fuse word 305 loading through BSEC_OTPCR is.." bitfld.long 0x24 16. "SRLOCK304,sticky reload lock for fuse word 304" "0: Fuse word 304 loading through BSEC_OTPCR is..,1: Fuse word 304 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 15. "SRLOCK303,sticky reload lock for fuse word 303" "0: Fuse word 303 loading through BSEC_OTPCR is..,1: Fuse word 303 loading through BSEC_OTPCR is.." bitfld.long 0x24 14. "SRLOCK302,sticky reload lock for fuse word 302" "0: Fuse word 302 loading through BSEC_OTPCR is..,1: Fuse word 302 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 13. "SRLOCK301,sticky reload lock for fuse word 301" "0: Fuse word 301 loading through BSEC_OTPCR is..,1: Fuse word 301 loading through BSEC_OTPCR is.." bitfld.long 0x24 12. "SRLOCK300,sticky reload lock for fuse word 300" "0: Fuse word 300 loading through BSEC_OTPCR is..,1: Fuse word 300 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 11. "SRLOCK299,sticky reload lock for fuse word 299" "0: Fuse word 299 loading through BSEC_OTPCR is..,1: Fuse word 299 loading through BSEC_OTPCR is.." bitfld.long 0x24 10. "SRLOCK298,sticky reload lock for fuse word 298" "0: Fuse word 298 loading through BSEC_OTPCR is..,1: Fuse word 298 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 9. "SRLOCK297,sticky reload lock for fuse word 297" "0: Fuse word 297 loading through BSEC_OTPCR is..,1: Fuse word 297 loading through BSEC_OTPCR is.." bitfld.long 0x24 8. "SRLOCK296,sticky reload lock for fuse word 296" "0: Fuse word 296 loading through BSEC_OTPCR is..,1: Fuse word 296 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 7. "SRLOCK295,sticky reload lock for fuse word 295" "0: Fuse word 295 loading through BSEC_OTPCR is..,1: Fuse word 295 loading through BSEC_OTPCR is.." bitfld.long 0x24 6. "SRLOCK294,sticky reload lock for fuse word 294" "0: Fuse word 294 loading through BSEC_OTPCR is..,1: Fuse word 294 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 5. "SRLOCK293,sticky reload lock for fuse word 293" "0: Fuse word 293 loading through BSEC_OTPCR is..,1: Fuse word 293 loading through BSEC_OTPCR is.." bitfld.long 0x24 4. "SRLOCK292,sticky reload lock for fuse word 292" "0: Fuse word 292 loading through BSEC_OTPCR is..,1: Fuse word 292 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 3. "SRLOCK291,sticky reload lock for fuse word 291" "0: Fuse word 291 loading through BSEC_OTPCR is..,1: Fuse word 291 loading through BSEC_OTPCR is.." bitfld.long 0x24 2. "SRLOCK290,sticky reload lock for fuse word 290" "0: Fuse word 290 loading through BSEC_OTPCR is..,1: Fuse word 290 loading through BSEC_OTPCR is.." newline bitfld.long 0x24 1. "SRLOCK289,sticky reload lock for fuse word 289" "0: Fuse word 289 loading through BSEC_OTPCR is..,1: Fuse word 289 loading through BSEC_OTPCR is.." bitfld.long 0x24 0. "SRLOCK288,sticky reload lock for fuse word 288" "0: Fuse word 288 loading through BSEC_OTPCR is..,1: Fuse word 288 loading through BSEC_OTPCR is.." line.long 0x28 "BSEC_SRLOCK10,BSEC sticky reload lock register 10" bitfld.long 0x28 31. "SRLOCK351,sticky reload lock for fuse word 351" "0: Fuse word 351 loading through BSEC_OTPCR is..,1: Fuse word 351 loading through BSEC_OTPCR is.." bitfld.long 0x28 30. "SRLOCK350,sticky reload lock for fuse word 350" "0: Fuse word 350 loading through BSEC_OTPCR is..,1: Fuse word 350 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 29. "SRLOCK349,sticky reload lock for fuse word 349" "0: Fuse word 349 loading through BSEC_OTPCR is..,1: Fuse word 349 loading through BSEC_OTPCR is.." bitfld.long 0x28 28. "SRLOCK348,sticky reload lock for fuse word 348" "0: Fuse word 348 loading through BSEC_OTPCR is..,1: Fuse word 348 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 27. "SRLOCK347,sticky reload lock for fuse word 347" "0: Fuse word 347 loading through BSEC_OTPCR is..,1: Fuse word 347 loading through BSEC_OTPCR is.." bitfld.long 0x28 26. "SRLOCK346,sticky reload lock for fuse word 346" "0: Fuse word 346 loading through BSEC_OTPCR is..,1: Fuse word 346 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 25. "SRLOCK345,sticky reload lock for fuse word 345" "0: Fuse word 345 loading through BSEC_OTPCR is..,1: Fuse word 345 loading through BSEC_OTPCR is.." bitfld.long 0x28 24. "SRLOCK344,sticky reload lock for fuse word 344" "0: Fuse word 344 loading through BSEC_OTPCR is..,1: Fuse word 344 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 23. "SRLOCK343,sticky reload lock for fuse word 343" "0: Fuse word 343 loading through BSEC_OTPCR is..,1: Fuse word 343 loading through BSEC_OTPCR is.." bitfld.long 0x28 22. "SRLOCK342,sticky reload lock for fuse word 342" "0: Fuse word 342 loading through BSEC_OTPCR is..,1: Fuse word 342 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 21. "SRLOCK341,sticky reload lock for fuse word 341" "0: Fuse word 341 loading through BSEC_OTPCR is..,1: Fuse word 341 loading through BSEC_OTPCR is.." bitfld.long 0x28 20. "SRLOCK340,sticky reload lock for fuse word 340" "0: Fuse word 340 loading through BSEC_OTPCR is..,1: Fuse word 340 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 19. "SRLOCK339,sticky reload lock for fuse word 339" "0: Fuse word 339 loading through BSEC_OTPCR is..,1: Fuse word 339 loading through BSEC_OTPCR is.." bitfld.long 0x28 18. "SRLOCK338,sticky reload lock for fuse word 338" "0: Fuse word 338 loading through BSEC_OTPCR is..,1: Fuse word 338 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 17. "SRLOCK337,sticky reload lock for fuse word 337" "0: Fuse word 337 loading through BSEC_OTPCR is..,1: Fuse word 337 loading through BSEC_OTPCR is.." bitfld.long 0x28 16. "SRLOCK336,sticky reload lock for fuse word 336" "0: Fuse word 336 loading through BSEC_OTPCR is..,1: Fuse word 336 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 15. "SRLOCK335,sticky reload lock for fuse word 335" "0: Fuse word 335 loading through BSEC_OTPCR is..,1: Fuse word 335 loading through BSEC_OTPCR is.." bitfld.long 0x28 14. "SRLOCK334,sticky reload lock for fuse word 334" "0: Fuse word 334 loading through BSEC_OTPCR is..,1: Fuse word 334 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 13. "SRLOCK333,sticky reload lock for fuse word 333" "0: Fuse word 333 loading through BSEC_OTPCR is..,1: Fuse word 333 loading through BSEC_OTPCR is.." bitfld.long 0x28 12. "SRLOCK332,sticky reload lock for fuse word 332" "0: Fuse word 332 loading through BSEC_OTPCR is..,1: Fuse word 332 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 11. "SRLOCK331,sticky reload lock for fuse word 331" "0: Fuse word 331 loading through BSEC_OTPCR is..,1: Fuse word 331 loading through BSEC_OTPCR is.." bitfld.long 0x28 10. "SRLOCK330,sticky reload lock for fuse word 330" "0: Fuse word 330 loading through BSEC_OTPCR is..,1: Fuse word 330 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 9. "SRLOCK329,sticky reload lock for fuse word 329" "0: Fuse word 329 loading through BSEC_OTPCR is..,1: Fuse word 329 loading through BSEC_OTPCR is.." bitfld.long 0x28 8. "SRLOCK328,sticky reload lock for fuse word 328" "0: Fuse word 328 loading through BSEC_OTPCR is..,1: Fuse word 328 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 7. "SRLOCK327,sticky reload lock for fuse word 327" "0: Fuse word 327 loading through BSEC_OTPCR is..,1: Fuse word 327 loading through BSEC_OTPCR is.." bitfld.long 0x28 6. "SRLOCK326,sticky reload lock for fuse word 326" "0: Fuse word 326 loading through BSEC_OTPCR is..,1: Fuse word 326 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 5. "SRLOCK325,sticky reload lock for fuse word 325" "0: Fuse word 325 loading through BSEC_OTPCR is..,1: Fuse word 325 loading through BSEC_OTPCR is.." bitfld.long 0x28 4. "SRLOCK324,sticky reload lock for fuse word 324" "0: Fuse word 324 loading through BSEC_OTPCR is..,1: Fuse word 324 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 3. "SRLOCK323,sticky reload lock for fuse word 323" "0: Fuse word 323 loading through BSEC_OTPCR is..,1: Fuse word 323 loading through BSEC_OTPCR is.." bitfld.long 0x28 2. "SRLOCK322,sticky reload lock for fuse word 322" "0: Fuse word 322 loading through BSEC_OTPCR is..,1: Fuse word 322 loading through BSEC_OTPCR is.." newline bitfld.long 0x28 1. "SRLOCK321,sticky reload lock for fuse word 321" "0: Fuse word 321 loading through BSEC_OTPCR is..,1: Fuse word 321 loading through BSEC_OTPCR is.." bitfld.long 0x28 0. "SRLOCK320,sticky reload lock for fuse word 320" "0: Fuse word 320 loading through BSEC_OTPCR is..,1: Fuse word 320 loading through BSEC_OTPCR is.." line.long 0x2C "BSEC_SRLOCK11,BSEC sticky reload lock register 11" bitfld.long 0x2C 31. "SRLOCK383,sticky reload lock for fuse word 383" "0: Fuse word 383 loading through BSEC_OTPCR is..,1: Fuse word 383 loading through BSEC_OTPCR is.." bitfld.long 0x2C 30. "SRLOCK382,sticky reload lock for fuse word 382" "0: Fuse word 382 loading through BSEC_OTPCR is..,1: Fuse word 382 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 29. "SRLOCK381,sticky reload lock for fuse word 381" "0: Fuse word 381 loading through BSEC_OTPCR is..,1: Fuse word 381 loading through BSEC_OTPCR is.." bitfld.long 0x2C 28. "SRLOCK380,sticky reload lock for fuse word 380" "0: Fuse word 380 loading through BSEC_OTPCR is..,1: Fuse word 380 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 27. "SRLOCK379,sticky reload lock for fuse word 379" "0: Fuse word 379 loading through BSEC_OTPCR is..,1: Fuse word 379 loading through BSEC_OTPCR is.." bitfld.long 0x2C 26. "SRLOCK378,sticky reload lock for fuse word 378" "0: Fuse word 378 loading through BSEC_OTPCR is..,1: Fuse word 378 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 25. "SRLOCK377,sticky reload lock for fuse word 377" "0: Fuse word 377 loading through BSEC_OTPCR is..,1: Fuse word 377 loading through BSEC_OTPCR is.." bitfld.long 0x2C 24. "SRLOCK376,sticky reload lock for fuse word 376" "0: Fuse word 376 loading through BSEC_OTPCR is..,1: Fuse word 376 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 23. "SRLOCK375,sticky reload lock for fuse word 375" "0: Fuse word 375 loading through BSEC_OTPCR is..,1: Fuse word 375 loading through BSEC_OTPCR is.." bitfld.long 0x2C 22. "SRLOCK374,sticky reload lock for fuse word 374" "0: Fuse word 374 loading through BSEC_OTPCR is..,1: Fuse word 374 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 21. "SRLOCK373,sticky reload lock for fuse word 373" "0: Fuse word 373 loading through BSEC_OTPCR is..,1: Fuse word 373 loading through BSEC_OTPCR is.." bitfld.long 0x2C 20. "SRLOCK372,sticky reload lock for fuse word 372" "0: Fuse word 372 loading through BSEC_OTPCR is..,1: Fuse word 372 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 19. "SRLOCK371,sticky reload lock for fuse word 371" "0: Fuse word 371 loading through BSEC_OTPCR is..,1: Fuse word 371 loading through BSEC_OTPCR is.." bitfld.long 0x2C 18. "SRLOCK370,sticky reload lock for fuse word 370" "0: Fuse word 370 loading through BSEC_OTPCR is..,1: Fuse word 370 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 17. "SRLOCK369,sticky reload lock for fuse word 369" "0: Fuse word 369 loading through BSEC_OTPCR is..,1: Fuse word 369 loading through BSEC_OTPCR is.." bitfld.long 0x2C 16. "SRLOCK368,sticky reload lock for fuse word 368" "0: Fuse word 368 loading through BSEC_OTPCR is..,1: Fuse word 368 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 15. "SRLOCK367,sticky reload lock for fuse word 367" "0: Fuse word 367 loading through BSEC_OTPCR is..,1: Fuse word 367 loading through BSEC_OTPCR is.." bitfld.long 0x2C 14. "SRLOCK366,sticky reload lock for fuse word 366" "0: Fuse word 366 loading through BSEC_OTPCR is..,1: Fuse word 366 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 13. "SRLOCK365,sticky reload lock for fuse word 365" "0: Fuse word 365 loading through BSEC_OTPCR is..,1: Fuse word 365 loading through BSEC_OTPCR is.." bitfld.long 0x2C 12. "SRLOCK364,sticky reload lock for fuse word 364" "0: Fuse word 364 loading through BSEC_OTPCR is..,1: Fuse word 364 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 11. "SRLOCK363,sticky reload lock for fuse word 363" "0: Fuse word 363 loading through BSEC_OTPCR is..,1: Fuse word 363 loading through BSEC_OTPCR is.." bitfld.long 0x2C 10. "SRLOCK362,sticky reload lock for fuse word 362" "0: Fuse word 362 loading through BSEC_OTPCR is..,1: Fuse word 362 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 9. "SRLOCK361,sticky reload lock for fuse word 361" "0: Fuse word 361 loading through BSEC_OTPCR is..,1: Fuse word 361 loading through BSEC_OTPCR is.." bitfld.long 0x2C 8. "SRLOCK360,sticky reload lock for fuse word 360" "0: Fuse word 360 loading through BSEC_OTPCR is..,1: Fuse word 360 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 7. "SRLOCK359,sticky reload lock for fuse word 359" "0: Fuse word 359 loading through BSEC_OTPCR is..,1: Fuse word 359 loading through BSEC_OTPCR is.." bitfld.long 0x2C 6. "SRLOCK358,sticky reload lock for fuse word 358" "0: Fuse word 358 loading through BSEC_OTPCR is..,1: Fuse word 358 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 5. "SRLOCK357,sticky reload lock for fuse word 357" "0: Fuse word 357 loading through BSEC_OTPCR is..,1: Fuse word 357 loading through BSEC_OTPCR is.." bitfld.long 0x2C 4. "SRLOCK356,sticky reload lock for fuse word 356" "0: Fuse word 356 loading through BSEC_OTPCR is..,1: Fuse word 356 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 3. "SRLOCK355,sticky reload lock for fuse word 355" "0: Fuse word 355 loading through BSEC_OTPCR is..,1: Fuse word 355 loading through BSEC_OTPCR is.." bitfld.long 0x2C 2. "SRLOCK354,sticky reload lock for fuse word 354" "0: Fuse word 354 loading through BSEC_OTPCR is..,1: Fuse word 354 loading through BSEC_OTPCR is.." newline bitfld.long 0x2C 1. "SRLOCK353,sticky reload lock for fuse word 353" "0: Fuse word 353 loading through BSEC_OTPCR is..,1: Fuse word 353 loading through BSEC_OTPCR is.." bitfld.long 0x2C 0. "SRLOCK352,sticky reload lock for fuse word 352" "0: Fuse word 352 loading through BSEC_OTPCR is..,1: Fuse word 352 loading through BSEC_OTPCR is.." rgroup.long 0x8C0++0x2F line.long 0x0 "BSEC_OTPVLDR0,BSEC OTP valid register 0" bitfld.long 0x0 31. "VLDF31,Valid flag for shadow register 31" "0: An error occurred while fuse word 31 was last..,1: Last reload of fuse word 31 was done without.." bitfld.long 0x0 30. "VLDF30,Valid flag for shadow register 30" "0: An error occurred while fuse word 30 was last..,1: Last reload of fuse word 30 was done without.." newline bitfld.long 0x0 29. "VLDF29,Valid flag for shadow register 29" "0: An error occurred while fuse word 29 was last..,1: Last reload of fuse word 29 was done without.." bitfld.long 0x0 28. "VLDF28,Valid flag for shadow register 28" "0: An error occurred while fuse word 28 was last..,1: Last reload of fuse word 28 was done without.." newline bitfld.long 0x0 27. "VLDF27,Valid flag for shadow register 27" "0: An error occurred while fuse word 27 was last..,1: Last reload of fuse word 27 was done without.." bitfld.long 0x0 26. "VLDF26,Valid flag for shadow register 26" "0: An error occurred while fuse word 26 was last..,1: Last reload of fuse word 26 was done without.." newline bitfld.long 0x0 25. "VLDF25,Valid flag for shadow register 25" "0: An error occurred while fuse word 25 was last..,1: Last reload of fuse word 25 was done without.." bitfld.long 0x0 24. "VLDF24,Valid flag for shadow register 24" "0: An error occurred while fuse word 24 was last..,1: Last reload of fuse word 24 was done without.." newline bitfld.long 0x0 23. "VLDF23,Valid flag for shadow register 23" "0: An error occurred while fuse word 23 was last..,1: Last reload of fuse word 23 was done without.." bitfld.long 0x0 22. "VLDF22,Valid flag for shadow register 22" "0: An error occurred while fuse word 22 was last..,1: Last reload of fuse word 22 was done without.." newline bitfld.long 0x0 21. "VLDF21,Valid flag for shadow register 21" "0: An error occurred while fuse word 21 was last..,1: Last reload of fuse word 21 was done without.." bitfld.long 0x0 20. "VLDF20,Valid flag for shadow register 20" "0: An error occurred while fuse word 20 was last..,1: Last reload of fuse word 20 was done without.." newline bitfld.long 0x0 19. "VLDF19,Valid flag for shadow register 19" "0: An error occurred while fuse word 19 was last..,1: Last reload of fuse word 19 was done without.." bitfld.long 0x0 18. "VLDF18,Valid flag for shadow register 18" "0: An error occurred while fuse word 18 was last..,1: Last reload of fuse word 18 was done without.." newline bitfld.long 0x0 17. "VLDF17,Valid flag for shadow register 17" "0: An error occurred while fuse word 17 was last..,1: Last reload of fuse word 17 was done without.." bitfld.long 0x0 16. "VLDF16,Valid flag for shadow register 16" "0: An error occurred while fuse word 16 was last..,1: Last reload of fuse word 16 was done without.." newline bitfld.long 0x0 15. "VLDF15,Valid flag for shadow register 15" "0: An error occurred while fuse word 15 was last..,1: Last reload of fuse word 15 was done without.." bitfld.long 0x0 14. "VLDF14,Valid flag for shadow register 14" "0: An error occurred while fuse word 14 was last..,1: Last reload of fuse word 14 was done without.." newline bitfld.long 0x0 13. "VLDF13,Valid flag for shadow register 13" "0: An error occurred while fuse word 13 was last..,1: Last reload of fuse word 13 was done without.." bitfld.long 0x0 12. "VLDF12,Valid flag for shadow register 12" "0: An error occurred while fuse word 12 was last..,1: Last reload of fuse word 12 was done without.." newline bitfld.long 0x0 11. "VLDF11,Valid flag for shadow register 11" "0: An error occurred while fuse word 11 was last..,1: Last reload of fuse word 11 was done without.." bitfld.long 0x0 10. "VLDF10,Valid flag for shadow register 10" "0: An error occurred while fuse word 10 was last..,1: Last reload of fuse word 10 was done without.." newline bitfld.long 0x0 9. "VLDF9,Valid flag for shadow register 9" "0: An error occurred while fuse word 9 was last..,1: Last reload of fuse word 9 was done without error." bitfld.long 0x0 8. "VLDF8,Valid flag for shadow register 8" "0: An error occurred while fuse word 8 was last..,1: Last reload of fuse word 8 was done without error." newline bitfld.long 0x0 7. "VLDF7,Valid flag for shadow register 7" "0: An error occurred while fuse word 7 was last..,1: Last reload of fuse word 7 was done without error." bitfld.long 0x0 6. "VLDF6,Valid flag for shadow register 6" "0: An error occurred while fuse word 6 was last..,1: Last reload of fuse word 6 was done without error." newline bitfld.long 0x0 5. "VLDF5,Valid flag for shadow register 5" "0: An error occurred while fuse word 5 was last..,1: Last reload of fuse word 5 was done without error." bitfld.long 0x0 4. "VLDF4,Valid flag for shadow register 4" "0: An error occurred while fuse word 4 was last..,1: Last reload of fuse word 4 was done without error." newline bitfld.long 0x0 3. "VLDF3,Valid flag for shadow register 3" "0: An error occurred while fuse word 3 was last..,1: Last reload of fuse word 3 was done without error." bitfld.long 0x0 2. "VLDF2,Valid flag for shadow register 2" "0: An error occurred while fuse word 2 was last..,1: Last reload of fuse word 2 was done without error." newline bitfld.long 0x0 1. "VLDF1,Valid flag for shadow register 1" "0: An error occurred while fuse word 1 was last..,1: Last reload of fuse word 1 was done without error." bitfld.long 0x0 0. "VLDF0,Valid flag for shadow register 0" "0: An error occurred while fuse word 0 was last..,1: Last reload of fuse word 0 was done without error." line.long 0x4 "BSEC_OTPVLDR1,BSEC OTP valid register 1" bitfld.long 0x4 31. "VLDF63,Valid flag for shadow register 63" "0: An error occurred while fuse word 63 was last..,1: Last reload of fuse word 63 was done without.." bitfld.long 0x4 30. "VLDF62,Valid flag for shadow register 62" "0: An error occurred while fuse word 62 was last..,1: Last reload of fuse word 62 was done without.." newline bitfld.long 0x4 29. "VLDF61,Valid flag for shadow register 61" "0: An error occurred while fuse word 61 was last..,1: Last reload of fuse word 61 was done without.." bitfld.long 0x4 28. "VLDF60,Valid flag for shadow register 60" "0: An error occurred while fuse word 60 was last..,1: Last reload of fuse word 60 was done without.." newline bitfld.long 0x4 27. "VLDF59,Valid flag for shadow register 59" "0: An error occurred while fuse word 59 was last..,1: Last reload of fuse word 59 was done without.." bitfld.long 0x4 26. "VLDF58,Valid flag for shadow register 58" "0: An error occurred while fuse word 58 was last..,1: Last reload of fuse word 58 was done without.." newline bitfld.long 0x4 25. "VLDF57,Valid flag for shadow register 57" "0: An error occurred while fuse word 57 was last..,1: Last reload of fuse word 57 was done without.." bitfld.long 0x4 24. "VLDF56,Valid flag for shadow register 56" "0: An error occurred while fuse word 56 was last..,1: Last reload of fuse word 56 was done without.." newline bitfld.long 0x4 23. "VLDF55,Valid flag for shadow register 55" "0: An error occurred while fuse word 55 was last..,1: Last reload of fuse word 55 was done without.." bitfld.long 0x4 22. "VLDF54,Valid flag for shadow register 54" "0: An error occurred while fuse word 54 was last..,1: Last reload of fuse word 54 was done without.." newline bitfld.long 0x4 21. "VLDF53,Valid flag for shadow register 53" "0: An error occurred while fuse word 53 was last..,1: Last reload of fuse word 53 was done without.." bitfld.long 0x4 20. "VLDF52,Valid flag for shadow register 52" "0: An error occurred while fuse word 52 was last..,1: Last reload of fuse word 52 was done without.." newline bitfld.long 0x4 19. "VLDF51,Valid flag for shadow register 51" "0: An error occurred while fuse word 51 was last..,1: Last reload of fuse word 51 was done without.." bitfld.long 0x4 18. "VLDF50,Valid flag for shadow register 50" "0: An error occurred while fuse word 50 was last..,1: Last reload of fuse word 50 was done without.." newline bitfld.long 0x4 17. "VLDF49,Valid flag for shadow register 49" "0: An error occurred while fuse word 49 was last..,1: Last reload of fuse word 49 was done without.." bitfld.long 0x4 16. "VLDF48,Valid flag for shadow register 48" "0: An error occurred while fuse word 48 was last..,1: Last reload of fuse word 48 was done without.." newline bitfld.long 0x4 15. "VLDF47,Valid flag for shadow register 47" "0: An error occurred while fuse word 47 was last..,1: Last reload of fuse word 47 was done without.." bitfld.long 0x4 14. "VLDF46,Valid flag for shadow register 46" "0: An error occurred while fuse word 46 was last..,1: Last reload of fuse word 46 was done without.." newline bitfld.long 0x4 13. "VLDF45,Valid flag for shadow register 45" "0: An error occurred while fuse word 45 was last..,1: Last reload of fuse word 45 was done without.." bitfld.long 0x4 12. "VLDF44,Valid flag for shadow register 44" "0: An error occurred while fuse word 44 was last..,1: Last reload of fuse word 44 was done without.." newline bitfld.long 0x4 11. "VLDF43,Valid flag for shadow register 43" "0: An error occurred while fuse word 43 was last..,1: Last reload of fuse word 43 was done without.." bitfld.long 0x4 10. "VLDF42,Valid flag for shadow register 42" "0: An error occurred while fuse word 42 was last..,1: Last reload of fuse word 42 was done without.." newline bitfld.long 0x4 9. "VLDF41,Valid flag for shadow register 41" "0: An error occurred while fuse word 41 was last..,1: Last reload of fuse word 41 was done without.." bitfld.long 0x4 8. "VLDF40,Valid flag for shadow register 40" "0: An error occurred while fuse word 40 was last..,1: Last reload of fuse word 40 was done without.." newline bitfld.long 0x4 7. "VLDF39,Valid flag for shadow register 39" "0: An error occurred while fuse word 39 was last..,1: Last reload of fuse word 39 was done without.." bitfld.long 0x4 6. "VLDF38,Valid flag for shadow register 38" "0: An error occurred while fuse word 38 was last..,1: Last reload of fuse word 38 was done without.." newline bitfld.long 0x4 5. "VLDF37,Valid flag for shadow register 37" "0: An error occurred while fuse word 37 was last..,1: Last reload of fuse word 37 was done without.." bitfld.long 0x4 4. "VLDF36,Valid flag for shadow register 36" "0: An error occurred while fuse word 36 was last..,1: Last reload of fuse word 36 was done without.." newline bitfld.long 0x4 3. "VLDF35,Valid flag for shadow register 35" "0: An error occurred while fuse word 35 was last..,1: Last reload of fuse word 35 was done without.." bitfld.long 0x4 2. "VLDF34,Valid flag for shadow register 34" "0: An error occurred while fuse word 34 was last..,1: Last reload of fuse word 34 was done without.." newline bitfld.long 0x4 1. "VLDF33,Valid flag for shadow register 33" "0: An error occurred while fuse word 33 was last..,1: Last reload of fuse word 33 was done without.." bitfld.long 0x4 0. "VLDF32,Valid flag for shadow register 32" "0: An error occurred while fuse word 32 was last..,1: Last reload of fuse word 32 was done without.." line.long 0x8 "BSEC_OTPVLDR2,BSEC OTP valid register 2" bitfld.long 0x8 31. "VLDF95,Valid flag for shadow register 95" "0: An error occurred while fuse word 95 was last..,1: Last reload of fuse word 95 was done without.." bitfld.long 0x8 30. "VLDF94,Valid flag for shadow register 94" "0: An error occurred while fuse word 94 was last..,1: Last reload of fuse word 94 was done without.." newline bitfld.long 0x8 29. "VLDF93,Valid flag for shadow register 93" "0: An error occurred while fuse word 93 was last..,1: Last reload of fuse word 93 was done without.." bitfld.long 0x8 28. "VLDF92,Valid flag for shadow register 92" "0: An error occurred while fuse word 92 was last..,1: Last reload of fuse word 92 was done without.." newline bitfld.long 0x8 27. "VLDF91,Valid flag for shadow register 91" "0: An error occurred while fuse word 91 was last..,1: Last reload of fuse word 91 was done without.." bitfld.long 0x8 26. "VLDF90,Valid flag for shadow register 90" "0: An error occurred while fuse word 90 was last..,1: Last reload of fuse word 90 was done without.." newline bitfld.long 0x8 25. "VLDF89,Valid flag for shadow register 89" "0: An error occurred while fuse word 89 was last..,1: Last reload of fuse word 89 was done without.." bitfld.long 0x8 24. "VLDF88,Valid flag for shadow register 88" "0: An error occurred while fuse word 88 was last..,1: Last reload of fuse word 88 was done without.." newline bitfld.long 0x8 23. "VLDF87,Valid flag for shadow register 87" "0: An error occurred while fuse word 87 was last..,1: Last reload of fuse word 87 was done without.." bitfld.long 0x8 22. "VLDF86,Valid flag for shadow register 86" "0: An error occurred while fuse word 86 was last..,1: Last reload of fuse word 86 was done without.." newline bitfld.long 0x8 21. "VLDF85,Valid flag for shadow register 85" "0: An error occurred while fuse word 85 was last..,1: Last reload of fuse word 85 was done without.." bitfld.long 0x8 20. "VLDF84,Valid flag for shadow register 84" "0: An error occurred while fuse word 84 was last..,1: Last reload of fuse word 84 was done without.." newline bitfld.long 0x8 19. "VLDF83,Valid flag for shadow register 83" "0: An error occurred while fuse word 83 was last..,1: Last reload of fuse word 83 was done without.." bitfld.long 0x8 18. "VLDF82,Valid flag for shadow register 82" "0: An error occurred while fuse word 82 was last..,1: Last reload of fuse word 82 was done without.." newline bitfld.long 0x8 17. "VLDF81,Valid flag for shadow register 81" "0: An error occurred while fuse word 81 was last..,1: Last reload of fuse word 81 was done without.." bitfld.long 0x8 16. "VLDF80,Valid flag for shadow register 80" "0: An error occurred while fuse word 80 was last..,1: Last reload of fuse word 80 was done without.." newline bitfld.long 0x8 15. "VLDF79,Valid flag for shadow register 79" "0: An error occurred while fuse word 79 was last..,1: Last reload of fuse word 79 was done without.." bitfld.long 0x8 14. "VLDF78,Valid flag for shadow register 78" "0: An error occurred while fuse word 78 was last..,1: Last reload of fuse word 78 was done without.." newline bitfld.long 0x8 13. "VLDF77,Valid flag for shadow register 77" "0: An error occurred while fuse word 77 was last..,1: Last reload of fuse word 77 was done without.." bitfld.long 0x8 12. "VLDF76,Valid flag for shadow register 76" "0: An error occurred while fuse word 76 was last..,1: Last reload of fuse word 76 was done without.." newline bitfld.long 0x8 11. "VLDF75,Valid flag for shadow register 75" "0: An error occurred while fuse word 75 was last..,1: Last reload of fuse word 75 was done without.." bitfld.long 0x8 10. "VLDF74,Valid flag for shadow register 74" "0: An error occurred while fuse word 74 was last..,1: Last reload of fuse word 74 was done without.." newline bitfld.long 0x8 9. "VLDF73,Valid flag for shadow register 73" "0: An error occurred while fuse word 73 was last..,1: Last reload of fuse word 73 was done without.." bitfld.long 0x8 8. "VLDF72,Valid flag for shadow register 72" "0: An error occurred while fuse word 72 was last..,1: Last reload of fuse word 72 was done without.." newline bitfld.long 0x8 7. "VLDF71,Valid flag for shadow register 71" "0: An error occurred while fuse word 71 was last..,1: Last reload of fuse word 71 was done without.." bitfld.long 0x8 6. "VLDF70,Valid flag for shadow register 70" "0: An error occurred while fuse word 70 was last..,1: Last reload of fuse word 70 was done without.." newline bitfld.long 0x8 5. "VLDF69,Valid flag for shadow register 69" "0: An error occurred while fuse word 69 was last..,1: Last reload of fuse word 69 was done without.." bitfld.long 0x8 4. "VLDF68,Valid flag for shadow register 68" "0: An error occurred while fuse word 68 was last..,1: Last reload of fuse word 68 was done without.." newline bitfld.long 0x8 3. "VLDF67,Valid flag for shadow register 67" "0: An error occurred while fuse word 67 was last..,1: Last reload of fuse word 67 was done without.." bitfld.long 0x8 2. "VLDF66,Valid flag for shadow register 66" "0: An error occurred while fuse word 66 was last..,1: Last reload of fuse word 66 was done without.." newline bitfld.long 0x8 1. "VLDF65,Valid flag for shadow register 65" "0: An error occurred while fuse word 65 was last..,1: Last reload of fuse word 65 was done without.." bitfld.long 0x8 0. "VLDF64,Valid flag for shadow register 64" "0: An error occurred while fuse word 64 was last..,1: Last reload of fuse word 64 was done without.." line.long 0xC "BSEC_OTPVLDR3,BSEC OTP valid register 3" bitfld.long 0xC 31. "VLDF127,Valid flag for shadow register 127" "0: An error occurred while fuse word 127 was last..,1: Last reload of fuse word 127 was done without.." bitfld.long 0xC 30. "VLDF126,Valid flag for shadow register 126" "0: An error occurred while fuse word 126 was last..,1: Last reload of fuse word 126 was done without.." newline bitfld.long 0xC 29. "VLDF125,Valid flag for shadow register 125" "0: An error occurred while fuse word 125 was last..,1: Last reload of fuse word 125 was done without.." bitfld.long 0xC 28. "VLDF124,Valid flag for shadow register 124" "0: An error occurred while fuse word 124 was last..,1: Last reload of fuse word 124 was done without.." newline bitfld.long 0xC 27. "VLDF123,Valid flag for shadow register 123" "0: An error occurred while fuse word 123 was last..,1: Last reload of fuse word 123 was done without.." bitfld.long 0xC 26. "VLDF122,Valid flag for shadow register 122" "0: An error occurred while fuse word 122 was last..,1: Last reload of fuse word 122 was done without.." newline bitfld.long 0xC 25. "VLDF121,Valid flag for shadow register 121" "0: An error occurred while fuse word 121 was last..,1: Last reload of fuse word 121 was done without.." bitfld.long 0xC 24. "VLDF120,Valid flag for shadow register 120" "0: An error occurred while fuse word 120 was last..,1: Last reload of fuse word 120 was done without.." newline bitfld.long 0xC 23. "VLDF119,Valid flag for shadow register 119" "0: An error occurred while fuse word 119 was last..,1: Last reload of fuse word 119 was done without.." bitfld.long 0xC 22. "VLDF118,Valid flag for shadow register 118" "0: An error occurred while fuse word 118 was last..,1: Last reload of fuse word 118 was done without.." newline bitfld.long 0xC 21. "VLDF117,Valid flag for shadow register 117" "0: An error occurred while fuse word 117 was last..,1: Last reload of fuse word 117 was done without.." bitfld.long 0xC 20. "VLDF116,Valid flag for shadow register 116" "0: An error occurred while fuse word 116 was last..,1: Last reload of fuse word 116 was done without.." newline bitfld.long 0xC 19. "VLDF115,Valid flag for shadow register 115" "0: An error occurred while fuse word 115 was last..,1: Last reload of fuse word 115 was done without.." bitfld.long 0xC 18. "VLDF114,Valid flag for shadow register 114" "0: An error occurred while fuse word 114 was last..,1: Last reload of fuse word 114 was done without.." newline bitfld.long 0xC 17. "VLDF113,Valid flag for shadow register 113" "0: An error occurred while fuse word 113 was last..,1: Last reload of fuse word 113 was done without.." bitfld.long 0xC 16. "VLDF112,Valid flag for shadow register 112" "0: An error occurred while fuse word 112 was last..,1: Last reload of fuse word 112 was done without.." newline bitfld.long 0xC 15. "VLDF111,Valid flag for shadow register 111" "0: An error occurred while fuse word 111 was last..,1: Last reload of fuse word 111 was done without.." bitfld.long 0xC 14. "VLDF110,Valid flag for shadow register 110" "0: An error occurred while fuse word 110 was last..,1: Last reload of fuse word 110 was done without.." newline bitfld.long 0xC 13. "VLDF109,Valid flag for shadow register 109" "0: An error occurred while fuse word 109 was last..,1: Last reload of fuse word 109 was done without.." bitfld.long 0xC 12. "VLDF108,Valid flag for shadow register 108" "0: An error occurred while fuse word 108 was last..,1: Last reload of fuse word 108 was done without.." newline bitfld.long 0xC 11. "VLDF107,Valid flag for shadow register 107" "0: An error occurred while fuse word 107 was last..,1: Last reload of fuse word 107 was done without.." bitfld.long 0xC 10. "VLDF106,Valid flag for shadow register 106" "0: An error occurred while fuse word 106 was last..,1: Last reload of fuse word 106 was done without.." newline bitfld.long 0xC 9. "VLDF105,Valid flag for shadow register 105" "0: An error occurred while fuse word 105 was last..,1: Last reload of fuse word 105 was done without.." bitfld.long 0xC 8. "VLDF104,Valid flag for shadow register 104" "0: An error occurred while fuse word 104 was last..,1: Last reload of fuse word 104 was done without.." newline bitfld.long 0xC 7. "VLDF103,Valid flag for shadow register 103" "0: An error occurred while fuse word 103 was last..,1: Last reload of fuse word 103 was done without.." bitfld.long 0xC 6. "VLDF102,Valid flag for shadow register 102" "0: An error occurred while fuse word 102 was last..,1: Last reload of fuse word 102 was done without.." newline bitfld.long 0xC 5. "VLDF101,Valid flag for shadow register 101" "0: An error occurred while fuse word 101 was last..,1: Last reload of fuse word 101 was done without.." bitfld.long 0xC 4. "VLDF100,Valid flag for shadow register 100" "0: An error occurred while fuse word 100 was last..,1: Last reload of fuse word 100 was done without.." newline bitfld.long 0xC 3. "VLDF99,Valid flag for shadow register 99" "0: An error occurred while fuse word 99 was last..,1: Last reload of fuse word 99 was done without.." bitfld.long 0xC 2. "VLDF98,Valid flag for shadow register 98" "0: An error occurred while fuse word 98 was last..,1: Last reload of fuse word 98 was done without.." newline bitfld.long 0xC 1. "VLDF97,Valid flag for shadow register 97" "0: An error occurred while fuse word 97 was last..,1: Last reload of fuse word 97 was done without.." bitfld.long 0xC 0. "VLDF96,Valid flag for shadow register 96" "0: An error occurred while fuse word 96 was last..,1: Last reload of fuse word 96 was done without.." line.long 0x10 "BSEC_OTPVLDR4,BSEC OTP valid register 4" bitfld.long 0x10 31. "VLDF159,Valid flag for shadow register 159" "0: An error occurred while fuse word 159 was last..,1: Last reload of fuse word 159 was done without.." bitfld.long 0x10 30. "VLDF158,Valid flag for shadow register 158" "0: An error occurred while fuse word 158 was last..,1: Last reload of fuse word 158 was done without.." newline bitfld.long 0x10 29. "VLDF157,Valid flag for shadow register 157" "0: An error occurred while fuse word 157 was last..,1: Last reload of fuse word 157 was done without.." bitfld.long 0x10 28. "VLDF156,Valid flag for shadow register 156" "0: An error occurred while fuse word 156 was last..,1: Last reload of fuse word 156 was done without.." newline bitfld.long 0x10 27. "VLDF155,Valid flag for shadow register 155" "0: An error occurred while fuse word 155 was last..,1: Last reload of fuse word 155 was done without.." bitfld.long 0x10 26. "VLDF154,Valid flag for shadow register 154" "0: An error occurred while fuse word 154 was last..,1: Last reload of fuse word 154 was done without.." newline bitfld.long 0x10 25. "VLDF153,Valid flag for shadow register 153" "0: An error occurred while fuse word 153 was last..,1: Last reload of fuse word 153 was done without.." bitfld.long 0x10 24. "VLDF152,Valid flag for shadow register 152" "0: An error occurred while fuse word 152 was last..,1: Last reload of fuse word 152 was done without.." newline bitfld.long 0x10 23. "VLDF151,Valid flag for shadow register 151" "0: An error occurred while fuse word 151 was last..,1: Last reload of fuse word 151 was done without.." bitfld.long 0x10 22. "VLDF150,Valid flag for shadow register 150" "0: An error occurred while fuse word 150 was last..,1: Last reload of fuse word 150 was done without.." newline bitfld.long 0x10 21. "VLDF149,Valid flag for shadow register 149" "0: An error occurred while fuse word 149 was last..,1: Last reload of fuse word 149 was done without.." bitfld.long 0x10 20. "VLDF148,Valid flag for shadow register 148" "0: An error occurred while fuse word 148 was last..,1: Last reload of fuse word 148 was done without.." newline bitfld.long 0x10 19. "VLDF147,Valid flag for shadow register 147" "0: An error occurred while fuse word 147 was last..,1: Last reload of fuse word 147 was done without.." bitfld.long 0x10 18. "VLDF146,Valid flag for shadow register 146" "0: An error occurred while fuse word 146 was last..,1: Last reload of fuse word 146 was done without.." newline bitfld.long 0x10 17. "VLDF145,Valid flag for shadow register 145" "0: An error occurred while fuse word 145 was last..,1: Last reload of fuse word 145 was done without.." bitfld.long 0x10 16. "VLDF144,Valid flag for shadow register 144" "0: An error occurred while fuse word 144 was last..,1: Last reload of fuse word 144 was done without.." newline bitfld.long 0x10 15. "VLDF143,Valid flag for shadow register 143" "0: An error occurred while fuse word 143 was last..,1: Last reload of fuse word 143 was done without.." bitfld.long 0x10 14. "VLDF142,Valid flag for shadow register 142" "0: An error occurred while fuse word 142 was last..,1: Last reload of fuse word 142 was done without.." newline bitfld.long 0x10 13. "VLDF141,Valid flag for shadow register 141" "0: An error occurred while fuse word 141 was last..,1: Last reload of fuse word 141 was done without.." bitfld.long 0x10 12. "VLDF140,Valid flag for shadow register 140" "0: An error occurred while fuse word 140 was last..,1: Last reload of fuse word 140 was done without.." newline bitfld.long 0x10 11. "VLDF139,Valid flag for shadow register 139" "0: An error occurred while fuse word 139 was last..,1: Last reload of fuse word 139 was done without.." bitfld.long 0x10 10. "VLDF138,Valid flag for shadow register 138" "0: An error occurred while fuse word 138 was last..,1: Last reload of fuse word 138 was done without.." newline bitfld.long 0x10 9. "VLDF137,Valid flag for shadow register 137" "0: An error occurred while fuse word 137 was last..,1: Last reload of fuse word 137 was done without.." bitfld.long 0x10 8. "VLDF136,Valid flag for shadow register 136" "0: An error occurred while fuse word 136 was last..,1: Last reload of fuse word 136 was done without.." newline bitfld.long 0x10 7. "VLDF135,Valid flag for shadow register 135" "0: An error occurred while fuse word 135 was last..,1: Last reload of fuse word 135 was done without.." bitfld.long 0x10 6. "VLDF134,Valid flag for shadow register 134" "0: An error occurred while fuse word 134 was last..,1: Last reload of fuse word 134 was done without.." newline bitfld.long 0x10 5. "VLDF133,Valid flag for shadow register 133" "0: An error occurred while fuse word 133 was last..,1: Last reload of fuse word 133 was done without.." bitfld.long 0x10 4. "VLDF132,Valid flag for shadow register 132" "0: An error occurred while fuse word 132 was last..,1: Last reload of fuse word 132 was done without.." newline bitfld.long 0x10 3. "VLDF131,Valid flag for shadow register 131" "0: An error occurred while fuse word 131 was last..,1: Last reload of fuse word 131 was done without.." bitfld.long 0x10 2. "VLDF130,Valid flag for shadow register 130" "0: An error occurred while fuse word 130 was last..,1: Last reload of fuse word 130 was done without.." newline bitfld.long 0x10 1. "VLDF129,Valid flag for shadow register 129" "0: An error occurred while fuse word 129 was last..,1: Last reload of fuse word 129 was done without.." bitfld.long 0x10 0. "VLDF128,Valid flag for shadow register 128" "0: An error occurred while fuse word 128 was last..,1: Last reload of fuse word 128 was done without.." line.long 0x14 "BSEC_OTPVLDR5,BSEC OTP valid register 5" bitfld.long 0x14 31. "VLDF191,Valid flag for shadow register 191" "0: An error occurred while fuse word 191 was last..,1: Last reload of fuse word 191 was done without.." bitfld.long 0x14 30. "VLDF190,Valid flag for shadow register 190" "0: An error occurred while fuse word 190 was last..,1: Last reload of fuse word 190 was done without.." newline bitfld.long 0x14 29. "VLDF189,Valid flag for shadow register 189" "0: An error occurred while fuse word 189 was last..,1: Last reload of fuse word 189 was done without.." bitfld.long 0x14 28. "VLDF188,Valid flag for shadow register 188" "0: An error occurred while fuse word 188 was last..,1: Last reload of fuse word 188 was done without.." newline bitfld.long 0x14 27. "VLDF187,Valid flag for shadow register 187" "0: An error occurred while fuse word 187 was last..,1: Last reload of fuse word 187 was done without.." bitfld.long 0x14 26. "VLDF186,Valid flag for shadow register 186" "0: An error occurred while fuse word 186 was last..,1: Last reload of fuse word 186 was done without.." newline bitfld.long 0x14 25. "VLDF185,Valid flag for shadow register 185" "0: An error occurred while fuse word 185 was last..,1: Last reload of fuse word 185 was done without.." bitfld.long 0x14 24. "VLDF184,Valid flag for shadow register 184" "0: An error occurred while fuse word 184 was last..,1: Last reload of fuse word 184 was done without.." newline bitfld.long 0x14 23. "VLDF183,Valid flag for shadow register 183" "0: An error occurred while fuse word 183 was last..,1: Last reload of fuse word 183 was done without.." bitfld.long 0x14 22. "VLDF182,Valid flag for shadow register 182" "0: An error occurred while fuse word 182 was last..,1: Last reload of fuse word 182 was done without.." newline bitfld.long 0x14 21. "VLDF181,Valid flag for shadow register 181" "0: An error occurred while fuse word 181 was last..,1: Last reload of fuse word 181 was done without.." bitfld.long 0x14 20. "VLDF180,Valid flag for shadow register 180" "0: An error occurred while fuse word 180 was last..,1: Last reload of fuse word 180 was done without.." newline bitfld.long 0x14 19. "VLDF179,Valid flag for shadow register 179" "0: An error occurred while fuse word 179 was last..,1: Last reload of fuse word 179 was done without.." bitfld.long 0x14 18. "VLDF178,Valid flag for shadow register 178" "0: An error occurred while fuse word 178 was last..,1: Last reload of fuse word 178 was done without.." newline bitfld.long 0x14 17. "VLDF177,Valid flag for shadow register 177" "0: An error occurred while fuse word 177 was last..,1: Last reload of fuse word 177 was done without.." bitfld.long 0x14 16. "VLDF176,Valid flag for shadow register 176" "0: An error occurred while fuse word 176 was last..,1: Last reload of fuse word 176 was done without.." newline bitfld.long 0x14 15. "VLDF175,Valid flag for shadow register 175" "0: An error occurred while fuse word 175 was last..,1: Last reload of fuse word 175 was done without.." bitfld.long 0x14 14. "VLDF174,Valid flag for shadow register 174" "0: An error occurred while fuse word 174 was last..,1: Last reload of fuse word 174 was done without.." newline bitfld.long 0x14 13. "VLDF173,Valid flag for shadow register 173" "0: An error occurred while fuse word 173 was last..,1: Last reload of fuse word 173 was done without.." bitfld.long 0x14 12. "VLDF172,Valid flag for shadow register 172" "0: An error occurred while fuse word 172 was last..,1: Last reload of fuse word 172 was done without.." newline bitfld.long 0x14 11. "VLDF171,Valid flag for shadow register 171" "0: An error occurred while fuse word 171 was last..,1: Last reload of fuse word 171 was done without.." bitfld.long 0x14 10. "VLDF170,Valid flag for shadow register 170" "0: An error occurred while fuse word 170 was last..,1: Last reload of fuse word 170 was done without.." newline bitfld.long 0x14 9. "VLDF169,Valid flag for shadow register 169" "0: An error occurred while fuse word 169 was last..,1: Last reload of fuse word 169 was done without.." bitfld.long 0x14 8. "VLDF168,Valid flag for shadow register 168" "0: An error occurred while fuse word 168 was last..,1: Last reload of fuse word 168 was done without.." newline bitfld.long 0x14 7. "VLDF167,Valid flag for shadow register 167" "0: An error occurred while fuse word 167 was last..,1: Last reload of fuse word 167 was done without.." bitfld.long 0x14 6. "VLDF166,Valid flag for shadow register 166" "0: An error occurred while fuse word 166 was last..,1: Last reload of fuse word 166 was done without.." newline bitfld.long 0x14 5. "VLDF165,Valid flag for shadow register 165" "0: An error occurred while fuse word 165 was last..,1: Last reload of fuse word 165 was done without.." bitfld.long 0x14 4. "VLDF164,Valid flag for shadow register 164" "0: An error occurred while fuse word 164 was last..,1: Last reload of fuse word 164 was done without.." newline bitfld.long 0x14 3. "VLDF163,Valid flag for shadow register 163" "0: An error occurred while fuse word 163 was last..,1: Last reload of fuse word 163 was done without.." bitfld.long 0x14 2. "VLDF162,Valid flag for shadow register 162" "0: An error occurred while fuse word 162 was last..,1: Last reload of fuse word 162 was done without.." newline bitfld.long 0x14 1. "VLDF161,Valid flag for shadow register 161" "0: An error occurred while fuse word 161 was last..,1: Last reload of fuse word 161 was done without.." bitfld.long 0x14 0. "VLDF160,Valid flag for shadow register 160" "0: An error occurred while fuse word 160 was last..,1: Last reload of fuse word 160 was done without.." line.long 0x18 "BSEC_OTPVLDR6,BSEC OTP valid register 6" bitfld.long 0x18 31. "VLDF223,Valid flag for shadow register 223" "0: An error occurred while fuse word 223 was last..,1: Last reload of fuse word 223 was done without.." bitfld.long 0x18 30. "VLDF222,Valid flag for shadow register 222" "0: An error occurred while fuse word 222 was last..,1: Last reload of fuse word 222 was done without.." newline bitfld.long 0x18 29. "VLDF221,Valid flag for shadow register 221" "0: An error occurred while fuse word 221 was last..,1: Last reload of fuse word 221 was done without.." bitfld.long 0x18 28. "VLDF220,Valid flag for shadow register 220" "0: An error occurred while fuse word 220 was last..,1: Last reload of fuse word 220 was done without.." newline bitfld.long 0x18 27. "VLDF219,Valid flag for shadow register 219" "0: An error occurred while fuse word 219 was last..,1: Last reload of fuse word 219 was done without.." bitfld.long 0x18 26. "VLDF218,Valid flag for shadow register 218" "0: An error occurred while fuse word 218 was last..,1: Last reload of fuse word 218 was done without.." newline bitfld.long 0x18 25. "VLDF217,Valid flag for shadow register 217" "0: An error occurred while fuse word 217 was last..,1: Last reload of fuse word 217 was done without.." bitfld.long 0x18 24. "VLDF216,Valid flag for shadow register 216" "0: An error occurred while fuse word 216 was last..,1: Last reload of fuse word 216 was done without.." newline bitfld.long 0x18 23. "VLDF215,Valid flag for shadow register 215" "0: An error occurred while fuse word 215 was last..,1: Last reload of fuse word 215 was done without.." bitfld.long 0x18 22. "VLDF214,Valid flag for shadow register 214" "0: An error occurred while fuse word 214 was last..,1: Last reload of fuse word 214 was done without.." newline bitfld.long 0x18 21. "VLDF213,Valid flag for shadow register 213" "0: An error occurred while fuse word 213 was last..,1: Last reload of fuse word 213 was done without.." bitfld.long 0x18 20. "VLDF212,Valid flag for shadow register 212" "0: An error occurred while fuse word 212 was last..,1: Last reload of fuse word 212 was done without.." newline bitfld.long 0x18 19. "VLDF211,Valid flag for shadow register 211" "0: An error occurred while fuse word 211 was last..,1: Last reload of fuse word 211 was done without.." bitfld.long 0x18 18. "VLDF210,Valid flag for shadow register 210" "0: An error occurred while fuse word 210 was last..,1: Last reload of fuse word 210 was done without.." newline bitfld.long 0x18 17. "VLDF209,Valid flag for shadow register 209" "0: An error occurred while fuse word 209 was last..,1: Last reload of fuse word 209 was done without.." bitfld.long 0x18 16. "VLDF208,Valid flag for shadow register 208" "0: An error occurred while fuse word 208 was last..,1: Last reload of fuse word 208 was done without.." newline bitfld.long 0x18 15. "VLDF207,Valid flag for shadow register 207" "0: An error occurred while fuse word 207 was last..,1: Last reload of fuse word 207 was done without.." bitfld.long 0x18 14. "VLDF206,Valid flag for shadow register 206" "0: An error occurred while fuse word 206 was last..,1: Last reload of fuse word 206 was done without.." newline bitfld.long 0x18 13. "VLDF205,Valid flag for shadow register 205" "0: An error occurred while fuse word 205 was last..,1: Last reload of fuse word 205 was done without.." bitfld.long 0x18 12. "VLDF204,Valid flag for shadow register 204" "0: An error occurred while fuse word 204 was last..,1: Last reload of fuse word 204 was done without.." newline bitfld.long 0x18 11. "VLDF203,Valid flag for shadow register 203" "0: An error occurred while fuse word 203 was last..,1: Last reload of fuse word 203 was done without.." bitfld.long 0x18 10. "VLDF202,Valid flag for shadow register 202" "0: An error occurred while fuse word 202 was last..,1: Last reload of fuse word 202 was done without.." newline bitfld.long 0x18 9. "VLDF201,Valid flag for shadow register 201" "0: An error occurred while fuse word 201 was last..,1: Last reload of fuse word 201 was done without.." bitfld.long 0x18 8. "VLDF200,Valid flag for shadow register 200" "0: An error occurred while fuse word 200 was last..,1: Last reload of fuse word 200 was done without.." newline bitfld.long 0x18 7. "VLDF199,Valid flag for shadow register 199" "0: An error occurred while fuse word 199 was last..,1: Last reload of fuse word 199 was done without.." bitfld.long 0x18 6. "VLDF198,Valid flag for shadow register 198" "0: An error occurred while fuse word 198 was last..,1: Last reload of fuse word 198 was done without.." newline bitfld.long 0x18 5. "VLDF197,Valid flag for shadow register 197" "0: An error occurred while fuse word 197 was last..,1: Last reload of fuse word 197 was done without.." bitfld.long 0x18 4. "VLDF196,Valid flag for shadow register 196" "0: An error occurred while fuse word 196 was last..,1: Last reload of fuse word 196 was done without.." newline bitfld.long 0x18 3. "VLDF195,Valid flag for shadow register 195" "0: An error occurred while fuse word 195 was last..,1: Last reload of fuse word 195 was done without.." bitfld.long 0x18 2. "VLDF194,Valid flag for shadow register 194" "0: An error occurred while fuse word 194 was last..,1: Last reload of fuse word 194 was done without.." newline bitfld.long 0x18 1. "VLDF193,Valid flag for shadow register 193" "0: An error occurred while fuse word 193 was last..,1: Last reload of fuse word 193 was done without.." bitfld.long 0x18 0. "VLDF192,Valid flag for shadow register 192" "0: An error occurred while fuse word 192 was last..,1: Last reload of fuse word 192 was done without.." line.long 0x1C "BSEC_OTPVLDR7,BSEC OTP valid register 7" bitfld.long 0x1C 31. "VLDF255,Valid flag for shadow register 255" "0: An error occurred while fuse word 255 was last..,1: Last reload of fuse word 255 was done without.." bitfld.long 0x1C 30. "VLDF254,Valid flag for shadow register 254" "0: An error occurred while fuse word 254 was last..,1: Last reload of fuse word 254 was done without.." newline bitfld.long 0x1C 29. "VLDF253,Valid flag for shadow register 253" "0: An error occurred while fuse word 253 was last..,1: Last reload of fuse word 253 was done without.." bitfld.long 0x1C 28. "VLDF252,Valid flag for shadow register 252" "0: An error occurred while fuse word 252 was last..,1: Last reload of fuse word 252 was done without.." newline bitfld.long 0x1C 27. "VLDF251,Valid flag for shadow register 251" "0: An error occurred while fuse word 251 was last..,1: Last reload of fuse word 251 was done without.." bitfld.long 0x1C 26. "VLDF250,Valid flag for shadow register 250" "0: An error occurred while fuse word 250 was last..,1: Last reload of fuse word 250 was done without.." newline bitfld.long 0x1C 25. "VLDF249,Valid flag for shadow register 249" "0: An error occurred while fuse word 249 was last..,1: Last reload of fuse word 249 was done without.." bitfld.long 0x1C 24. "VLDF248,Valid flag for shadow register 248" "0: An error occurred while fuse word 248 was last..,1: Last reload of fuse word 248 was done without.." newline bitfld.long 0x1C 23. "VLDF247,Valid flag for shadow register 247" "0: An error occurred while fuse word 247 was last..,1: Last reload of fuse word 247 was done without.." bitfld.long 0x1C 22. "VLDF246,Valid flag for shadow register 246" "0: An error occurred while fuse word 246 was last..,1: Last reload of fuse word 246 was done without.." newline bitfld.long 0x1C 21. "VLDF245,Valid flag for shadow register 245" "0: An error occurred while fuse word 245 was last..,1: Last reload of fuse word 245 was done without.." bitfld.long 0x1C 20. "VLDF244,Valid flag for shadow register 244" "0: An error occurred while fuse word 244 was last..,1: Last reload of fuse word 244 was done without.." newline bitfld.long 0x1C 19. "VLDF243,Valid flag for shadow register 243" "0: An error occurred while fuse word 243 was last..,1: Last reload of fuse word 243 was done without.." bitfld.long 0x1C 18. "VLDF242,Valid flag for shadow register 242" "0: An error occurred while fuse word 242 was last..,1: Last reload of fuse word 242 was done without.." newline bitfld.long 0x1C 17. "VLDF241,Valid flag for shadow register 241" "0: An error occurred while fuse word 241 was last..,1: Last reload of fuse word 241 was done without.." bitfld.long 0x1C 16. "VLDF240,Valid flag for shadow register 240" "0: An error occurred while fuse word 240 was last..,1: Last reload of fuse word 240 was done without.." newline bitfld.long 0x1C 15. "VLDF239,Valid flag for shadow register 239" "0: An error occurred while fuse word 239 was last..,1: Last reload of fuse word 239 was done without.." bitfld.long 0x1C 14. "VLDF238,Valid flag for shadow register 238" "0: An error occurred while fuse word 238 was last..,1: Last reload of fuse word 238 was done without.." newline bitfld.long 0x1C 13. "VLDF237,Valid flag for shadow register 237" "0: An error occurred while fuse word 237 was last..,1: Last reload of fuse word 237 was done without.." bitfld.long 0x1C 12. "VLDF236,Valid flag for shadow register 236" "0: An error occurred while fuse word 236 was last..,1: Last reload of fuse word 236 was done without.." newline bitfld.long 0x1C 11. "VLDF235,Valid flag for shadow register 235" "0: An error occurred while fuse word 235 was last..,1: Last reload of fuse word 235 was done without.." bitfld.long 0x1C 10. "VLDF234,Valid flag for shadow register 234" "0: An error occurred while fuse word 234 was last..,1: Last reload of fuse word 234 was done without.." newline bitfld.long 0x1C 9. "VLDF233,Valid flag for shadow register 233" "0: An error occurred while fuse word 233 was last..,1: Last reload of fuse word 233 was done without.." bitfld.long 0x1C 8. "VLDF232,Valid flag for shadow register 232" "0: An error occurred while fuse word 232 was last..,1: Last reload of fuse word 232 was done without.." newline bitfld.long 0x1C 7. "VLDF231,Valid flag for shadow register 231" "0: An error occurred while fuse word 231 was last..,1: Last reload of fuse word 231 was done without.." bitfld.long 0x1C 6. "VLDF230,Valid flag for shadow register 230" "0: An error occurred while fuse word 230 was last..,1: Last reload of fuse word 230 was done without.." newline bitfld.long 0x1C 5. "VLDF229,Valid flag for shadow register 229" "0: An error occurred while fuse word 229 was last..,1: Last reload of fuse word 229 was done without.." bitfld.long 0x1C 4. "VLDF228,Valid flag for shadow register 228" "0: An error occurred while fuse word 228 was last..,1: Last reload of fuse word 228 was done without.." newline bitfld.long 0x1C 3. "VLDF227,Valid flag for shadow register 227" "0: An error occurred while fuse word 227 was last..,1: Last reload of fuse word 227 was done without.." bitfld.long 0x1C 2. "VLDF226,Valid flag for shadow register 226" "0: An error occurred while fuse word 226 was last..,1: Last reload of fuse word 226 was done without.." newline bitfld.long 0x1C 1. "VLDF225,Valid flag for shadow register 225" "0: An error occurred while fuse word 225 was last..,1: Last reload of fuse word 225 was done without.." bitfld.long 0x1C 0. "VLDF224,Valid flag for shadow register 224" "0: An error occurred while fuse word 224 was last..,1: Last reload of fuse word 224 was done without.." line.long 0x20 "BSEC_OTPVLDR8,BSEC OTP valid register 8" bitfld.long 0x20 31. "VLDF287,Valid flag for shadow register 287" "0: An error occurred while fuse word 287 was last..,1: Last reload of fuse word 287 was done without.." bitfld.long 0x20 30. "VLDF286,Valid flag for shadow register 286" "0: An error occurred while fuse word 286 was last..,1: Last reload of fuse word 286 was done without.." newline bitfld.long 0x20 29. "VLDF285,Valid flag for shadow register 285" "0: An error occurred while fuse word 285 was last..,1: Last reload of fuse word 285 was done without.." bitfld.long 0x20 28. "VLDF284,Valid flag for shadow register 284" "0: An error occurred while fuse word 284 was last..,1: Last reload of fuse word 284 was done without.." newline bitfld.long 0x20 27. "VLDF283,Valid flag for shadow register 283" "0: An error occurred while fuse word 283 was last..,1: Last reload of fuse word 283 was done without.." bitfld.long 0x20 26. "VLDF282,Valid flag for shadow register 282" "0: An error occurred while fuse word 282 was last..,1: Last reload of fuse word 282 was done without.." newline bitfld.long 0x20 25. "VLDF281,Valid flag for shadow register 281" "0: An error occurred while fuse word 281 was last..,1: Last reload of fuse word 281 was done without.." bitfld.long 0x20 24. "VLDF280,Valid flag for shadow register 280" "0: An error occurred while fuse word 280 was last..,1: Last reload of fuse word 280 was done without.." newline bitfld.long 0x20 23. "VLDF279,Valid flag for shadow register 279" "0: An error occurred while fuse word 279 was last..,1: Last reload of fuse word 279 was done without.." bitfld.long 0x20 22. "VLDF278,Valid flag for shadow register 278" "0: An error occurred while fuse word 278 was last..,1: Last reload of fuse word 278 was done without.." newline bitfld.long 0x20 21. "VLDF277,Valid flag for shadow register 277" "0: An error occurred while fuse word 277 was last..,1: Last reload of fuse word 277 was done without.." bitfld.long 0x20 20. "VLDF276,Valid flag for shadow register 276" "0: An error occurred while fuse word 276 was last..,1: Last reload of fuse word 276 was done without.." newline bitfld.long 0x20 19. "VLDF275,Valid flag for shadow register 275" "0: An error occurred while fuse word 275 was last..,1: Last reload of fuse word 275 was done without.." bitfld.long 0x20 18. "VLDF274,Valid flag for shadow register 274" "0: An error occurred while fuse word 274 was last..,1: Last reload of fuse word 274 was done without.." newline bitfld.long 0x20 17. "VLDF273,Valid flag for shadow register 273" "0: An error occurred while fuse word 273 was last..,1: Last reload of fuse word 273 was done without.." bitfld.long 0x20 16. "VLDF272,Valid flag for shadow register 272" "0: An error occurred while fuse word 272 was last..,1: Last reload of fuse word 272 was done without.." newline bitfld.long 0x20 15. "VLDF271,Valid flag for shadow register 271" "0: An error occurred while fuse word 271 was last..,1: Last reload of fuse word 271 was done without.." bitfld.long 0x20 14. "VLDF270,Valid flag for shadow register 270" "0: An error occurred while fuse word 270 was last..,1: Last reload of fuse word 270 was done without.." newline bitfld.long 0x20 13. "VLDF269,Valid flag for shadow register 269" "0: An error occurred while fuse word 269 was last..,1: Last reload of fuse word 269 was done without.." bitfld.long 0x20 12. "VLDF268,Valid flag for shadow register 268" "0: An error occurred while fuse word 268 was last..,1: Last reload of fuse word 268 was done without.." newline bitfld.long 0x20 11. "VLDF267,Valid flag for shadow register 267" "0: An error occurred while fuse word 267 was last..,1: Last reload of fuse word 267 was done without.." bitfld.long 0x20 10. "VLDF266,Valid flag for shadow register 266" "0: An error occurred while fuse word 266 was last..,1: Last reload of fuse word 266 was done without.." newline bitfld.long 0x20 9. "VLDF265,Valid flag for shadow register 265" "0: An error occurred while fuse word 265 was last..,1: Last reload of fuse word 265 was done without.." bitfld.long 0x20 8. "VLDF264,Valid flag for shadow register 264" "0: An error occurred while fuse word 264 was last..,1: Last reload of fuse word 264 was done without.." newline bitfld.long 0x20 7. "VLDF263,Valid flag for shadow register 263" "0: An error occurred while fuse word 263 was last..,1: Last reload of fuse word 263 was done without.." bitfld.long 0x20 6. "VLDF262,Valid flag for shadow register 262" "0: An error occurred while fuse word 262 was last..,1: Last reload of fuse word 262 was done without.." newline bitfld.long 0x20 5. "VLDF261,Valid flag for shadow register 261" "0: An error occurred while fuse word 261 was last..,1: Last reload of fuse word 261 was done without.." bitfld.long 0x20 4. "VLDF260,Valid flag for shadow register 260" "0: An error occurred while fuse word 260 was last..,1: Last reload of fuse word 260 was done without.." newline bitfld.long 0x20 3. "VLDF259,Valid flag for shadow register 259" "0: An error occurred while fuse word 259 was last..,1: Last reload of fuse word 259 was done without.." bitfld.long 0x20 2. "VLDF258,Valid flag for shadow register 258" "0: An error occurred while fuse word 258 was last..,1: Last reload of fuse word 258 was done without.." newline bitfld.long 0x20 1. "VLDF257,Valid flag for shadow register 257" "0: An error occurred while fuse word 257 was last..,1: Last reload of fuse word 257 was done without.." bitfld.long 0x20 0. "VLDF256,Valid flag for shadow register 256" "0: An error occurred while fuse word 256 was last..,1: Last reload of fuse word 256 was done without.." line.long 0x24 "BSEC_OTPVLDR9,BSEC OTP valid register 9" bitfld.long 0x24 31. "VLDF319,Valid flag for shadow register 319" "0: An error occurred while fuse word 319 was last..,1: Last reload of fuse word 319 was done without.." bitfld.long 0x24 30. "VLDF318,Valid flag for shadow register 318" "0: An error occurred while fuse word 318 was last..,1: Last reload of fuse word 318 was done without.." newline bitfld.long 0x24 29. "VLDF317,Valid flag for shadow register 317" "0: An error occurred while fuse word 317 was last..,1: Last reload of fuse word 317 was done without.." bitfld.long 0x24 28. "VLDF316,Valid flag for shadow register 316" "0: An error occurred while fuse word 316 was last..,1: Last reload of fuse word 316 was done without.." newline bitfld.long 0x24 27. "VLDF315,Valid flag for shadow register 315" "0: An error occurred while fuse word 315 was last..,1: Last reload of fuse word 315 was done without.." bitfld.long 0x24 26. "VLDF314,Valid flag for shadow register 314" "0: An error occurred while fuse word 314 was last..,1: Last reload of fuse word 314 was done without.." newline bitfld.long 0x24 25. "VLDF313,Valid flag for shadow register 313" "0: An error occurred while fuse word 313 was last..,1: Last reload of fuse word 313 was done without.." bitfld.long 0x24 24. "VLDF312,Valid flag for shadow register 312" "0: An error occurred while fuse word 312 was last..,1: Last reload of fuse word 312 was done without.." newline bitfld.long 0x24 23. "VLDF311,Valid flag for shadow register 311" "0: An error occurred while fuse word 311 was last..,1: Last reload of fuse word 311 was done without.." bitfld.long 0x24 22. "VLDF310,Valid flag for shadow register 310" "0: An error occurred while fuse word 310 was last..,1: Last reload of fuse word 310 was done without.." newline bitfld.long 0x24 21. "VLDF309,Valid flag for shadow register 309" "0: An error occurred while fuse word 309 was last..,1: Last reload of fuse word 309 was done without.." bitfld.long 0x24 20. "VLDF308,Valid flag for shadow register 308" "0: An error occurred while fuse word 308 was last..,1: Last reload of fuse word 308 was done without.." newline bitfld.long 0x24 19. "VLDF307,Valid flag for shadow register 307" "0: An error occurred while fuse word 307 was last..,1: Last reload of fuse word 307 was done without.." bitfld.long 0x24 18. "VLDF306,Valid flag for shadow register 306" "0: An error occurred while fuse word 306 was last..,1: Last reload of fuse word 306 was done without.." newline bitfld.long 0x24 17. "VLDF305,Valid flag for shadow register 305" "0: An error occurred while fuse word 305 was last..,1: Last reload of fuse word 305 was done without.." bitfld.long 0x24 16. "VLDF304,Valid flag for shadow register 304" "0: An error occurred while fuse word 304 was last..,1: Last reload of fuse word 304 was done without.." newline bitfld.long 0x24 15. "VLDF303,Valid flag for shadow register 303" "0: An error occurred while fuse word 303 was last..,1: Last reload of fuse word 303 was done without.." bitfld.long 0x24 14. "VLDF302,Valid flag for shadow register 302" "0: An error occurred while fuse word 302 was last..,1: Last reload of fuse word 302 was done without.." newline bitfld.long 0x24 13. "VLDF301,Valid flag for shadow register 301" "0: An error occurred while fuse word 301 was last..,1: Last reload of fuse word 301 was done without.." bitfld.long 0x24 12. "VLDF300,Valid flag for shadow register 300" "0: An error occurred while fuse word 300 was last..,1: Last reload of fuse word 300 was done without.." newline bitfld.long 0x24 11. "VLDF299,Valid flag for shadow register 299" "0: An error occurred while fuse word 299 was last..,1: Last reload of fuse word 299 was done without.." bitfld.long 0x24 10. "VLDF298,Valid flag for shadow register 298" "0: An error occurred while fuse word 298 was last..,1: Last reload of fuse word 298 was done without.." newline bitfld.long 0x24 9. "VLDF297,Valid flag for shadow register 297" "0: An error occurred while fuse word 297 was last..,1: Last reload of fuse word 297 was done without.." bitfld.long 0x24 8. "VLDF296,Valid flag for shadow register 296" "0: An error occurred while fuse word 296 was last..,1: Last reload of fuse word 296 was done without.." newline bitfld.long 0x24 7. "VLDF295,Valid flag for shadow register 295" "0: An error occurred while fuse word 295 was last..,1: Last reload of fuse word 295 was done without.." bitfld.long 0x24 6. "VLDF294,Valid flag for shadow register 294" "0: An error occurred while fuse word 294 was last..,1: Last reload of fuse word 294 was done without.." newline bitfld.long 0x24 5. "VLDF293,Valid flag for shadow register 293" "0: An error occurred while fuse word 293 was last..,1: Last reload of fuse word 293 was done without.." bitfld.long 0x24 4. "VLDF292,Valid flag for shadow register 292" "0: An error occurred while fuse word 292 was last..,1: Last reload of fuse word 292 was done without.." newline bitfld.long 0x24 3. "VLDF291,Valid flag for shadow register 291" "0: An error occurred while fuse word 291 was last..,1: Last reload of fuse word 291 was done without.." bitfld.long 0x24 2. "VLDF290,Valid flag for shadow register 290" "0: An error occurred while fuse word 290 was last..,1: Last reload of fuse word 290 was done without.." newline bitfld.long 0x24 1. "VLDF289,Valid flag for shadow register 289" "0: An error occurred while fuse word 289 was last..,1: Last reload of fuse word 289 was done without.." bitfld.long 0x24 0. "VLDF288,Valid flag for shadow register 288" "0: An error occurred while fuse word 288 was last..,1: Last reload of fuse word 288 was done without.." line.long 0x28 "BSEC_OTPVLDR10,BSEC OTP valid register 10" bitfld.long 0x28 31. "VLDF351,Valid flag for shadow register 351" "0: An error occurred while fuse word 351 was last..,1: Last reload of fuse word 351 was done without.." bitfld.long 0x28 30. "VLDF350,Valid flag for shadow register 350" "0: An error occurred while fuse word 350 was last..,1: Last reload of fuse word 350 was done without.." newline bitfld.long 0x28 29. "VLDF349,Valid flag for shadow register 349" "0: An error occurred while fuse word 349 was last..,1: Last reload of fuse word 349 was done without.." bitfld.long 0x28 28. "VLDF348,Valid flag for shadow register 348" "0: An error occurred while fuse word 348 was last..,1: Last reload of fuse word 348 was done without.." newline bitfld.long 0x28 27. "VLDF347,Valid flag for shadow register 347" "0: An error occurred while fuse word 347 was last..,1: Last reload of fuse word 347 was done without.." bitfld.long 0x28 26. "VLDF346,Valid flag for shadow register 346" "0: An error occurred while fuse word 346 was last..,1: Last reload of fuse word 346 was done without.." newline bitfld.long 0x28 25. "VLDF345,Valid flag for shadow register 345" "0: An error occurred while fuse word 345 was last..,1: Last reload of fuse word 345 was done without.." bitfld.long 0x28 24. "VLDF344,Valid flag for shadow register 344" "0: An error occurred while fuse word 344 was last..,1: Last reload of fuse word 344 was done without.." newline bitfld.long 0x28 23. "VLDF343,Valid flag for shadow register 343" "0: An error occurred while fuse word 343 was last..,1: Last reload of fuse word 343 was done without.." bitfld.long 0x28 22. "VLDF342,Valid flag for shadow register 342" "0: An error occurred while fuse word 342 was last..,1: Last reload of fuse word 342 was done without.." newline bitfld.long 0x28 21. "VLDF341,Valid flag for shadow register 341" "0: An error occurred while fuse word 341 was last..,1: Last reload of fuse word 341 was done without.." bitfld.long 0x28 20. "VLDF340,Valid flag for shadow register 340" "0: An error occurred while fuse word 340 was last..,1: Last reload of fuse word 340 was done without.." newline bitfld.long 0x28 19. "VLDF339,Valid flag for shadow register 339" "0: An error occurred while fuse word 339 was last..,1: Last reload of fuse word 339 was done without.." bitfld.long 0x28 18. "VLDF338,Valid flag for shadow register 338" "0: An error occurred while fuse word 338 was last..,1: Last reload of fuse word 338 was done without.." newline bitfld.long 0x28 17. "VLDF337,Valid flag for shadow register 337" "0: An error occurred while fuse word 337 was last..,1: Last reload of fuse word 337 was done without.." bitfld.long 0x28 16. "VLDF336,Valid flag for shadow register 336" "0: An error occurred while fuse word 336 was last..,1: Last reload of fuse word 336 was done without.." newline bitfld.long 0x28 15. "VLDF335,Valid flag for shadow register 335" "0: An error occurred while fuse word 335 was last..,1: Last reload of fuse word 335 was done without.." bitfld.long 0x28 14. "VLDF334,Valid flag for shadow register 334" "0: An error occurred while fuse word 334 was last..,1: Last reload of fuse word 334 was done without.." newline bitfld.long 0x28 13. "VLDF333,Valid flag for shadow register 333" "0: An error occurred while fuse word 333 was last..,1: Last reload of fuse word 333 was done without.." bitfld.long 0x28 12. "VLDF332,Valid flag for shadow register 332" "0: An error occurred while fuse word 332 was last..,1: Last reload of fuse word 332 was done without.." newline bitfld.long 0x28 11. "VLDF331,Valid flag for shadow register 331" "0: An error occurred while fuse word 331 was last..,1: Last reload of fuse word 331 was done without.." bitfld.long 0x28 10. "VLDF330,Valid flag for shadow register 330" "0: An error occurred while fuse word 330 was last..,1: Last reload of fuse word 330 was done without.." newline bitfld.long 0x28 9. "VLDF329,Valid flag for shadow register 329" "0: An error occurred while fuse word 329 was last..,1: Last reload of fuse word 329 was done without.." bitfld.long 0x28 8. "VLDF328,Valid flag for shadow register 328" "0: An error occurred while fuse word 328 was last..,1: Last reload of fuse word 328 was done without.." newline bitfld.long 0x28 7. "VLDF327,Valid flag for shadow register 327" "0: An error occurred while fuse word 327 was last..,1: Last reload of fuse word 327 was done without.." bitfld.long 0x28 6. "VLDF326,Valid flag for shadow register 326" "0: An error occurred while fuse word 326 was last..,1: Last reload of fuse word 326 was done without.." newline bitfld.long 0x28 5. "VLDF325,Valid flag for shadow register 325" "0: An error occurred while fuse word 325 was last..,1: Last reload of fuse word 325 was done without.." bitfld.long 0x28 4. "VLDF324,Valid flag for shadow register 324" "0: An error occurred while fuse word 324 was last..,1: Last reload of fuse word 324 was done without.." newline bitfld.long 0x28 3. "VLDF323,Valid flag for shadow register 323" "0: An error occurred while fuse word 323 was last..,1: Last reload of fuse word 323 was done without.." bitfld.long 0x28 2. "VLDF322,Valid flag for shadow register 322" "0: An error occurred while fuse word 322 was last..,1: Last reload of fuse word 322 was done without.." newline bitfld.long 0x28 1. "VLDF321,Valid flag for shadow register 321" "0: An error occurred while fuse word 321 was last..,1: Last reload of fuse word 321 was done without.." bitfld.long 0x28 0. "VLDF320,Valid flag for shadow register 320" "0: An error occurred while fuse word 320 was last..,1: Last reload of fuse word 320 was done without.." line.long 0x2C "BSEC_OTPVLDR11,BSEC OTP valid register 11" bitfld.long 0x2C 31. "VLDF383,Valid flag for shadow register 383" "0: An error occurred while fuse word 383 was last..,1: Last reload of fuse word 383 was done without.." bitfld.long 0x2C 30. "VLDF382,Valid flag for shadow register 382" "0: An error occurred while fuse word 382 was last..,1: Last reload of fuse word 382 was done without.." newline bitfld.long 0x2C 29. "VLDF381,Valid flag for shadow register 381" "0: An error occurred while fuse word 381 was last..,1: Last reload of fuse word 381 was done without.." bitfld.long 0x2C 28. "VLDF380,Valid flag for shadow register 380" "0: An error occurred while fuse word 380 was last..,1: Last reload of fuse word 380 was done without.." newline bitfld.long 0x2C 27. "VLDF379,Valid flag for shadow register 379" "0: An error occurred while fuse word 379 was last..,1: Last reload of fuse word 379 was done without.." bitfld.long 0x2C 26. "VLDF378,Valid flag for shadow register 378" "0: An error occurred while fuse word 378 was last..,1: Last reload of fuse word 378 was done without.." newline bitfld.long 0x2C 25. "VLDF377,Valid flag for shadow register 377" "0: An error occurred while fuse word 377 was last..,1: Last reload of fuse word 377 was done without.." bitfld.long 0x2C 24. "VLDF376,Valid flag for shadow register 376" "0: An error occurred while fuse word 376 was last..,1: Last reload of fuse word 376 was done without.." newline bitfld.long 0x2C 23. "VLDF375,Valid flag for shadow register 375" "0: An error occurred while fuse word 375 was last..,1: Last reload of fuse word 375 was done without.." bitfld.long 0x2C 22. "VLDF374,Valid flag for shadow register 374" "0: An error occurred while fuse word 374 was last..,1: Last reload of fuse word 374 was done without.." newline bitfld.long 0x2C 21. "VLDF373,Valid flag for shadow register 373" "0: An error occurred while fuse word 373 was last..,1: Last reload of fuse word 373 was done without.." bitfld.long 0x2C 20. "VLDF372,Valid flag for shadow register 372" "0: An error occurred while fuse word 372 was last..,1: Last reload of fuse word 372 was done without.." newline bitfld.long 0x2C 19. "VLDF371,Valid flag for shadow register 371" "0: An error occurred while fuse word 371 was last..,1: Last reload of fuse word 371 was done without.." bitfld.long 0x2C 18. "VLDF370,Valid flag for shadow register 370" "0: An error occurred while fuse word 370 was last..,1: Last reload of fuse word 370 was done without.." newline bitfld.long 0x2C 17. "VLDF369,Valid flag for shadow register 369" "0: An error occurred while fuse word 369 was last..,1: Last reload of fuse word 369 was done without.." bitfld.long 0x2C 16. "VLDF368,Valid flag for shadow register 368" "0: An error occurred while fuse word 368 was last..,1: Last reload of fuse word 368 was done without.." newline bitfld.long 0x2C 15. "VLDF367,Valid flag for shadow register 367" "0: An error occurred while fuse word 367 was last..,1: Last reload of fuse word 367 was done without.." bitfld.long 0x2C 14. "VLDF366,Valid flag for shadow register 366" "0: An error occurred while fuse word 366 was last..,1: Last reload of fuse word 366 was done without.." newline bitfld.long 0x2C 13. "VLDF365,Valid flag for shadow register 365" "0: An error occurred while fuse word 365 was last..,1: Last reload of fuse word 365 was done without.." bitfld.long 0x2C 12. "VLDF364,Valid flag for shadow register 364" "0: An error occurred while fuse word 364 was last..,1: Last reload of fuse word 364 was done without.." newline bitfld.long 0x2C 11. "VLDF363,Valid flag for shadow register 363" "0: An error occurred while fuse word 363 was last..,1: Last reload of fuse word 363 was done without.." bitfld.long 0x2C 10. "VLDF362,Valid flag for shadow register 362" "0: An error occurred while fuse word 362 was last..,1: Last reload of fuse word 362 was done without.." newline bitfld.long 0x2C 9. "VLDF361,Valid flag for shadow register 361" "0: An error occurred while fuse word 361 was last..,1: Last reload of fuse word 361 was done without.." bitfld.long 0x2C 8. "VLDF360,Valid flag for shadow register 360" "0: An error occurred while fuse word 360 was last..,1: Last reload of fuse word 360 was done without.." newline bitfld.long 0x2C 7. "VLDF359,Valid flag for shadow register 359" "0: An error occurred while fuse word 359 was last..,1: Last reload of fuse word 359 was done without.." bitfld.long 0x2C 6. "VLDF358,Valid flag for shadow register 358" "0: An error occurred while fuse word 358 was last..,1: Last reload of fuse word 358 was done without.." newline bitfld.long 0x2C 5. "VLDF357,Valid flag for shadow register 357" "0: An error occurred while fuse word 357 was last..,1: Last reload of fuse word 357 was done without.." bitfld.long 0x2C 4. "VLDF356,Valid flag for shadow register 356" "0: An error occurred while fuse word 356 was last..,1: Last reload of fuse word 356 was done without.." newline bitfld.long 0x2C 3. "VLDF355,Valid flag for shadow register 355" "0: An error occurred while fuse word 355 was last..,1: Last reload of fuse word 355 was done without.." bitfld.long 0x2C 2. "VLDF354,Valid flag for shadow register 354" "0: An error occurred while fuse word 354 was last..,1: Last reload of fuse word 354 was done without.." newline bitfld.long 0x2C 1. "VLDF353,Valid flag for shadow register 353" "0: An error occurred while fuse word 353 was last..,1: Last reload of fuse word 353 was done without.." bitfld.long 0x2C 0. "VLDF352,Valid flag for shadow register 352" "0: An error occurred while fuse word 352 was last..,1: Last reload of fuse word 352 was done without.." rgroup.long 0x940++0x2F line.long 0x0 "BSEC_SFSR0,BSEC shadowed fuses status register 0" bitfld.long 0x0 31. "SFW31,Shadowed fuse word 31" "0: Fuse word 31 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR31 register." bitfld.long 0x0 30. "SFW30,Shadowed fuse word 30" "0: Fuse word 30 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR30 register." newline bitfld.long 0x0 29. "SFW29,Shadowed fuse word 29" "0: Fuse word 29 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR29 register." bitfld.long 0x0 28. "SFW28,Shadowed fuse word 28" "0: Fuse word 28 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR28 register." newline bitfld.long 0x0 27. "SFW27,Shadowed fuse word 27" "0: Fuse word 27 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR27 register." bitfld.long 0x0 26. "SFW26,Shadowed fuse word 26" "0: Fuse word 26 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR26 register." newline bitfld.long 0x0 25. "SFW25,Shadowed fuse word 25" "0: Fuse word 25 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR25 register." bitfld.long 0x0 24. "SFW24,Shadowed fuse word 24" "0: Fuse word 24 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR24 register." newline bitfld.long 0x0 23. "SFW23,Shadowed fuse word 23" "0: Fuse word 23 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR23 register." bitfld.long 0x0 22. "SFW22,Shadowed fuse word 22" "0: Fuse word 22 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR22 register." newline bitfld.long 0x0 21. "SFW21,Shadowed fuse word 21" "0: Fuse word 21 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR21 register." bitfld.long 0x0 20. "SFW20,Shadowed fuse word 20" "0: Fuse word 20 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR20 register." newline bitfld.long 0x0 19. "SFW19,Shadowed fuse word 19" "0: Fuse word 19 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR19 register." bitfld.long 0x0 18. "SFW18,Shadowed fuse word 18" "0: Fuse word 18 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR18 register." newline bitfld.long 0x0 17. "SFW17,Shadowed fuse word 17" "0: Fuse word 17 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR17 register." bitfld.long 0x0 16. "SFW16,Shadowed fuse word 16" "0: Fuse word 16 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR16 register." newline bitfld.long 0x0 15. "SFW15,Shadowed fuse word 15" "0: Fuse word 15 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR15 register." bitfld.long 0x0 14. "SFW14,Shadowed fuse word 14" "0: Fuse word 14 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR14 register." newline bitfld.long 0x0 13. "SFW13,Shadowed fuse word 13" "0: Fuse word 13 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR13 register." bitfld.long 0x0 12. "SFW12,Shadowed fuse word 12" "0: Fuse word 12 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR12 register." newline bitfld.long 0x0 11. "SFW11,Shadowed fuse word 11" "0: Fuse word 11 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR11 register." bitfld.long 0x0 10. "SFW10,Shadowed fuse word 10" "0: Fuse word 10 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR10 register." newline bitfld.long 0x0 9. "SFW9,Shadowed fuse word 9" "0: Fuse word 9 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR9 register." bitfld.long 0x0 8. "SFW8,Shadowed fuse word 8" "0: Fuse word 8 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR8 register." newline bitfld.long 0x0 7. "SFW7,Shadowed fuse word 7" "0: Fuse word 7 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR7 register." bitfld.long 0x0 6. "SFW6,Shadowed fuse word 6" "0: Fuse word 6 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR6 register." newline bitfld.long 0x0 5. "SFW5,Shadowed fuse word 5" "0: Fuse word 5 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR5 register." bitfld.long 0x0 4. "SFW4,Shadowed fuse word 4" "0: Fuse word 4 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR4 register." newline bitfld.long 0x0 3. "SFW3,Shadowed fuse word 3" "0: Fuse word 3 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR3 register." bitfld.long 0x0 2. "SFW2,Shadowed fuse word 2" "0: Fuse word 2 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR2 register." newline bitfld.long 0x0 1. "SFW1,Shadowed fuse word 1" "0: Fuse word 1 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR1 register." bitfld.long 0x0 0. "SFW0,Shadowed fuse word 0" "0: Fuse word 0 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR0 register." line.long 0x4 "BSEC_SFSR1,BSEC shadowed fuses status register 1" bitfld.long 0x4 31. "SFW63,Shadowed fuse word 63" "0: Fuse word 63 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR63 register." bitfld.long 0x4 30. "SFW62,Shadowed fuse word 62" "0: Fuse word 62 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR62 register." newline bitfld.long 0x4 29. "SFW61,Shadowed fuse word 61" "0: Fuse word 61 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR61 register." bitfld.long 0x4 28. "SFW60,Shadowed fuse word 60" "0: Fuse word 60 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR60 register." newline bitfld.long 0x4 27. "SFW59,Shadowed fuse word 59" "0: Fuse word 59 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR59 register." bitfld.long 0x4 26. "SFW58,Shadowed fuse word 58" "0: Fuse word 58 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR58 register." newline bitfld.long 0x4 25. "SFW57,Shadowed fuse word 57" "0: Fuse word 57 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR57 register." bitfld.long 0x4 24. "SFW56,Shadowed fuse word 56" "0: Fuse word 56 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR56 register." newline bitfld.long 0x4 23. "SFW55,Shadowed fuse word 55" "0: Fuse word 55 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR55 register." bitfld.long 0x4 22. "SFW54,Shadowed fuse word 54" "0: Fuse word 54 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR54 register." newline bitfld.long 0x4 21. "SFW53,Shadowed fuse word 53" "0: Fuse word 53 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR53 register." bitfld.long 0x4 20. "SFW52,Shadowed fuse word 52" "0: Fuse word 52 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR52 register." newline bitfld.long 0x4 19. "SFW51,Shadowed fuse word 51" "0: Fuse word 51 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR51 register." bitfld.long 0x4 18. "SFW50,Shadowed fuse word 50" "0: Fuse word 50 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR50 register." newline bitfld.long 0x4 17. "SFW49,Shadowed fuse word 49" "0: Fuse word 49 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR49 register." bitfld.long 0x4 16. "SFW48,Shadowed fuse word 48" "0: Fuse word 48 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR48 register." newline bitfld.long 0x4 15. "SFW47,Shadowed fuse word 47" "0: Fuse word 47 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR47 register." bitfld.long 0x4 14. "SFW46,Shadowed fuse word 46" "0: Fuse word 46 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR46 register." newline bitfld.long 0x4 13. "SFW45,Shadowed fuse word 45" "0: Fuse word 45 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR45 register." bitfld.long 0x4 12. "SFW44,Shadowed fuse word 44" "0: Fuse word 44 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR44 register." newline bitfld.long 0x4 11. "SFW43,Shadowed fuse word 43" "0: Fuse word 43 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR43 register." bitfld.long 0x4 10. "SFW42,Shadowed fuse word 42" "0: Fuse word 42 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR42 register." newline bitfld.long 0x4 9. "SFW41,Shadowed fuse word 41" "0: Fuse word 41 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR41 register." bitfld.long 0x4 8. "SFW40,Shadowed fuse word 40" "0: Fuse word 40 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR40 register." newline bitfld.long 0x4 7. "SFW39,Shadowed fuse word 39" "0: Fuse word 39 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR39 register." bitfld.long 0x4 6. "SFW38,Shadowed fuse word 38" "0: Fuse word 38 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR38 register." newline bitfld.long 0x4 5. "SFW37,Shadowed fuse word 37" "0: Fuse word 37 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR37 register." bitfld.long 0x4 4. "SFW36,Shadowed fuse word 36" "0: Fuse word 36 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR36 register." newline bitfld.long 0x4 3. "SFW35,Shadowed fuse word 35" "0: Fuse word 35 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR35 register." bitfld.long 0x4 2. "SFW34,Shadowed fuse word 34" "0: Fuse word 34 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR34 register." newline bitfld.long 0x4 1. "SFW33,Shadowed fuse word 33" "0: Fuse word 33 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR33 register." bitfld.long 0x4 0. "SFW32,Shadowed fuse word 32" "0: Fuse word 32 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR32 register." line.long 0x8 "BSEC_SFSR2,BSEC shadowed fuses status register 2" bitfld.long 0x8 31. "SFW95,Shadowed fuse word 95" "0: Fuse word 95 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR95 register." bitfld.long 0x8 30. "SFW94,Shadowed fuse word 94" "0: Fuse word 94 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR94 register." newline bitfld.long 0x8 29. "SFW93,Shadowed fuse word 93" "0: Fuse word 93 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR93 register." bitfld.long 0x8 28. "SFW92,Shadowed fuse word 92" "0: Fuse word 92 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR92 register." newline bitfld.long 0x8 27. "SFW91,Shadowed fuse word 91" "0: Fuse word 91 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR91 register." bitfld.long 0x8 26. "SFW90,Shadowed fuse word 90" "0: Fuse word 90 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR90 register." newline bitfld.long 0x8 25. "SFW89,Shadowed fuse word 89" "0: Fuse word 89 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR89 register." bitfld.long 0x8 24. "SFW88,Shadowed fuse word 88" "0: Fuse word 88 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR88 register." newline bitfld.long 0x8 23. "SFW87,Shadowed fuse word 87" "0: Fuse word 87 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR87 register." bitfld.long 0x8 22. "SFW86,Shadowed fuse word 86" "0: Fuse word 86 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR86 register." newline bitfld.long 0x8 21. "SFW85,Shadowed fuse word 85" "0: Fuse word 85 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR85 register." bitfld.long 0x8 20. "SFW84,Shadowed fuse word 84" "0: Fuse word 84 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR84 register." newline bitfld.long 0x8 19. "SFW83,Shadowed fuse word 83" "0: Fuse word 83 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR83 register." bitfld.long 0x8 18. "SFW82,Shadowed fuse word 82" "0: Fuse word 82 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR82 register." newline bitfld.long 0x8 17. "SFW81,Shadowed fuse word 81" "0: Fuse word 81 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR81 register." bitfld.long 0x8 16. "SFW80,Shadowed fuse word 80" "0: Fuse word 80 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR80 register." newline bitfld.long 0x8 15. "SFW79,Shadowed fuse word 79" "0: Fuse word 79 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR79 register." bitfld.long 0x8 14. "SFW78,Shadowed fuse word 78" "0: Fuse word 78 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR78 register." newline bitfld.long 0x8 13. "SFW77,Shadowed fuse word 77" "0: Fuse word 77 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR77 register." bitfld.long 0x8 12. "SFW76,Shadowed fuse word 76" "0: Fuse word 76 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR76 register." newline bitfld.long 0x8 11. "SFW75,Shadowed fuse word 75" "0: Fuse word 75 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR75 register." bitfld.long 0x8 10. "SFW74,Shadowed fuse word 74" "0: Fuse word 74 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR74 register." newline bitfld.long 0x8 9. "SFW73,Shadowed fuse word 73" "0: Fuse word 73 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR73 register." bitfld.long 0x8 8. "SFW72,Shadowed fuse word 72" "0: Fuse word 72 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR72 register." newline bitfld.long 0x8 7. "SFW71,Shadowed fuse word 71" "0: Fuse word 71 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR71 register." bitfld.long 0x8 6. "SFW70,Shadowed fuse word 70" "0: Fuse word 70 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR70 register." newline bitfld.long 0x8 5. "SFW69,Shadowed fuse word 69" "0: Fuse word 69 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR69 register." bitfld.long 0x8 4. "SFW68,Shadowed fuse word 68" "0: Fuse word 68 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR68 register." newline bitfld.long 0x8 3. "SFW67,Shadowed fuse word 67" "0: Fuse word 67 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR67 register." bitfld.long 0x8 2. "SFW66,Shadowed fuse word 66" "0: Fuse word 66 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR66 register." newline bitfld.long 0x8 1. "SFW65,Shadowed fuse word 65" "0: Fuse word 65 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR65 register." bitfld.long 0x8 0. "SFW64,Shadowed fuse word 64" "0: Fuse word 64 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR64 register." line.long 0xC "BSEC_SFSR3,BSEC shadowed fuses status register 3" bitfld.long 0xC 31. "SFW127,Shadowed fuse word 127" "0: Fuse word 127 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR127 register." bitfld.long 0xC 30. "SFW126,Shadowed fuse word 126" "0: Fuse word 126 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR126 register." newline bitfld.long 0xC 29. "SFW125,Shadowed fuse word 125" "0: Fuse word 125 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR125 register." bitfld.long 0xC 28. "SFW124,Shadowed fuse word 124" "0: Fuse word 124 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR124 register." newline bitfld.long 0xC 27. "SFW123,Shadowed fuse word 123" "0: Fuse word 123 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR123 register." bitfld.long 0xC 26. "SFW122,Shadowed fuse word 122" "0: Fuse word 122 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR122 register." newline bitfld.long 0xC 25. "SFW121,Shadowed fuse word 121" "0: Fuse word 121 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR121 register." bitfld.long 0xC 24. "SFW120,Shadowed fuse word 120" "0: Fuse word 120 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR120 register." newline bitfld.long 0xC 23. "SFW119,Shadowed fuse word 119" "0: Fuse word 119 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR119 register." bitfld.long 0xC 22. "SFW118,Shadowed fuse word 118" "0: Fuse word 118 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR118 register." newline bitfld.long 0xC 21. "SFW117,Shadowed fuse word 117" "0: Fuse word 117 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR117 register." bitfld.long 0xC 20. "SFW116,Shadowed fuse word 116" "0: Fuse word 116 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR116 register." newline bitfld.long 0xC 19. "SFW115,Shadowed fuse word 115" "0: Fuse word 115 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR115 register." bitfld.long 0xC 18. "SFW114,Shadowed fuse word 114" "0: Fuse word 114 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR114 register." newline bitfld.long 0xC 17. "SFW113,Shadowed fuse word 113" "0: Fuse word 113 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR113 register." bitfld.long 0xC 16. "SFW112,Shadowed fuse word 112" "0: Fuse word 112 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR112 register." newline bitfld.long 0xC 15. "SFW111,Shadowed fuse word 111" "0: Fuse word 111 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR111 register." bitfld.long 0xC 14. "SFW110,Shadowed fuse word 110" "0: Fuse word 110 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR110 register." newline bitfld.long 0xC 13. "SFW109,Shadowed fuse word 109" "0: Fuse word 109 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR109 register." bitfld.long 0xC 12. "SFW108,Shadowed fuse word 108" "0: Fuse word 108 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR108 register." newline bitfld.long 0xC 11. "SFW107,Shadowed fuse word 107" "0: Fuse word 107 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR107 register." bitfld.long 0xC 10. "SFW106,Shadowed fuse word 106" "0: Fuse word 106 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR106 register." newline bitfld.long 0xC 9. "SFW105,Shadowed fuse word 105" "0: Fuse word 105 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR105 register." bitfld.long 0xC 8. "SFW104,Shadowed fuse word 104" "0: Fuse word 104 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR104 register." newline bitfld.long 0xC 7. "SFW103,Shadowed fuse word 103" "0: Fuse word 103 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR103 register." bitfld.long 0xC 6. "SFW102,Shadowed fuse word 102" "0: Fuse word 102 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR102 register." newline bitfld.long 0xC 5. "SFW101,Shadowed fuse word 101" "0: Fuse word 101 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR101 register." bitfld.long 0xC 4. "SFW100,Shadowed fuse word 100" "0: Fuse word 100 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR100 register." newline bitfld.long 0xC 3. "SFW99,Shadowed fuse word 99" "0: Fuse word 99 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR99 register." bitfld.long 0xC 2. "SFW98,Shadowed fuse word 98" "0: Fuse word 98 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR98 register." newline bitfld.long 0xC 1. "SFW97,Shadowed fuse word 97" "0: Fuse word 97 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR97 register." bitfld.long 0xC 0. "SFW96,Shadowed fuse word 96" "0: Fuse word 96 is not shadowed. Fuse value must be..,1: Fuse word is shadowed in BSEC_FVR96 register." line.long 0x10 "BSEC_SFSR4,BSEC shadowed fuses status register 4" bitfld.long 0x10 31. "SFW159,Shadowed fuse word 159" "0: Fuse word 159 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR159 register." bitfld.long 0x10 30. "SFW158,Shadowed fuse word 158" "0: Fuse word 158 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR158 register." newline bitfld.long 0x10 29. "SFW157,Shadowed fuse word 157" "0: Fuse word 157 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR157 register." bitfld.long 0x10 28. "SFW156,Shadowed fuse word 156" "0: Fuse word 156 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR156 register." newline bitfld.long 0x10 27. "SFW155,Shadowed fuse word 155" "0: Fuse word 155 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR155 register." bitfld.long 0x10 26. "SFW154,Shadowed fuse word 154" "0: Fuse word 154 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR154 register." newline bitfld.long 0x10 25. "SFW153,Shadowed fuse word 153" "0: Fuse word 153 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR153 register." bitfld.long 0x10 24. "SFW152,Shadowed fuse word 152" "0: Fuse word 152 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR152 register." newline bitfld.long 0x10 23. "SFW151,Shadowed fuse word 151" "0: Fuse word 151 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR151 register." bitfld.long 0x10 22. "SFW150,Shadowed fuse word 150" "0: Fuse word 150 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR150 register." newline bitfld.long 0x10 21. "SFW149,Shadowed fuse word 149" "0: Fuse word 149 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR149 register." bitfld.long 0x10 20. "SFW148,Shadowed fuse word 148" "0: Fuse word 148 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR148 register." newline bitfld.long 0x10 19. "SFW147,Shadowed fuse word 147" "0: Fuse word 147 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR147 register." bitfld.long 0x10 18. "SFW146,Shadowed fuse word 146" "0: Fuse word 146 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR146 register." newline bitfld.long 0x10 17. "SFW145,Shadowed fuse word 145" "0: Fuse word 145 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR145 register." bitfld.long 0x10 16. "SFW144,Shadowed fuse word 144" "0: Fuse word 144 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR144 register." newline bitfld.long 0x10 15. "SFW143,Shadowed fuse word 143" "0: Fuse word 143 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR143 register." bitfld.long 0x10 14. "SFW142,Shadowed fuse word 142" "0: Fuse word 142 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR142 register." newline bitfld.long 0x10 13. "SFW141,Shadowed fuse word 141" "0: Fuse word 141 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR141 register." bitfld.long 0x10 12. "SFW140,Shadowed fuse word 140" "0: Fuse word 140 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR140 register." newline bitfld.long 0x10 11. "SFW139,Shadowed fuse word 139" "0: Fuse word 139 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR139 register." bitfld.long 0x10 10. "SFW138,Shadowed fuse word 138" "0: Fuse word 138 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR138 register." newline bitfld.long 0x10 9. "SFW137,Shadowed fuse word 137" "0: Fuse word 137 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR137 register." bitfld.long 0x10 8. "SFW136,Shadowed fuse word 136" "0: Fuse word 136 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR136 register." newline bitfld.long 0x10 7. "SFW135,Shadowed fuse word 135" "0: Fuse word 135 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR135 register." bitfld.long 0x10 6. "SFW134,Shadowed fuse word 134" "0: Fuse word 134 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR134 register." newline bitfld.long 0x10 5. "SFW133,Shadowed fuse word 133" "0: Fuse word 133 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR133 register." bitfld.long 0x10 4. "SFW132,Shadowed fuse word 132" "0: Fuse word 132 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR132 register." newline bitfld.long 0x10 3. "SFW131,Shadowed fuse word 131" "0: Fuse word 131 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR131 register." bitfld.long 0x10 2. "SFW130,Shadowed fuse word 130" "0: Fuse word 130 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR130 register." newline bitfld.long 0x10 1. "SFW129,Shadowed fuse word 129" "0: Fuse word 129 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR129 register." bitfld.long 0x10 0. "SFW128,Shadowed fuse word 128" "0: Fuse word 128 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR128 register." line.long 0x14 "BSEC_SFSR5,BSEC shadowed fuses status register 5" bitfld.long 0x14 31. "SFW191,Shadowed fuse word 191" "0: Fuse word 191 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR191 register." bitfld.long 0x14 30. "SFW190,Shadowed fuse word 190" "0: Fuse word 190 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR190 register." newline bitfld.long 0x14 29. "SFW189,Shadowed fuse word 189" "0: Fuse word 189 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR189 register." bitfld.long 0x14 28. "SFW188,Shadowed fuse word 188" "0: Fuse word 188 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR188 register." newline bitfld.long 0x14 27. "SFW187,Shadowed fuse word 187" "0: Fuse word 187 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR187 register." bitfld.long 0x14 26. "SFW186,Shadowed fuse word 186" "0: Fuse word 186 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR186 register." newline bitfld.long 0x14 25. "SFW185,Shadowed fuse word 185" "0: Fuse word 185 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR185 register." bitfld.long 0x14 24. "SFW184,Shadowed fuse word 184" "0: Fuse word 184 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR184 register." newline bitfld.long 0x14 23. "SFW183,Shadowed fuse word 183" "0: Fuse word 183 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR183 register." bitfld.long 0x14 22. "SFW182,Shadowed fuse word 182" "0: Fuse word 182 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR182 register." newline bitfld.long 0x14 21. "SFW181,Shadowed fuse word 181" "0: Fuse word 181 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR181 register." bitfld.long 0x14 20. "SFW180,Shadowed fuse word 180" "0: Fuse word 180 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR180 register." newline bitfld.long 0x14 19. "SFW179,Shadowed fuse word 179" "0: Fuse word 179 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR179 register." bitfld.long 0x14 18. "SFW178,Shadowed fuse word 178" "0: Fuse word 178 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR178 register." newline bitfld.long 0x14 17. "SFW177,Shadowed fuse word 177" "0: Fuse word 177 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR177 register." bitfld.long 0x14 16. "SFW176,Shadowed fuse word 176" "0: Fuse word 176 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR176 register." newline bitfld.long 0x14 15. "SFW175,Shadowed fuse word 175" "0: Fuse word 175 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR175 register." bitfld.long 0x14 14. "SFW174,Shadowed fuse word 174" "0: Fuse word 174 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR174 register." newline bitfld.long 0x14 13. "SFW173,Shadowed fuse word 173" "0: Fuse word 173 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR173 register." bitfld.long 0x14 12. "SFW172,Shadowed fuse word 172" "0: Fuse word 172 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR172 register." newline bitfld.long 0x14 11. "SFW171,Shadowed fuse word 171" "0: Fuse word 171 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR171 register." bitfld.long 0x14 10. "SFW170,Shadowed fuse word 170" "0: Fuse word 170 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR170 register." newline bitfld.long 0x14 9. "SFW169,Shadowed fuse word 169" "0: Fuse word 169 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR169 register." bitfld.long 0x14 8. "SFW168,Shadowed fuse word 168" "0: Fuse word 168 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR168 register." newline bitfld.long 0x14 7. "SFW167,Shadowed fuse word 167" "0: Fuse word 167 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR167 register." bitfld.long 0x14 6. "SFW166,Shadowed fuse word 166" "0: Fuse word 166 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR166 register." newline bitfld.long 0x14 5. "SFW165,Shadowed fuse word 165" "0: Fuse word 165 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR165 register." bitfld.long 0x14 4. "SFW164,Shadowed fuse word 164" "0: Fuse word 164 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR164 register." newline bitfld.long 0x14 3. "SFW163,Shadowed fuse word 163" "0: Fuse word 163 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR163 register." bitfld.long 0x14 2. "SFW162,Shadowed fuse word 162" "0: Fuse word 162 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR162 register." newline bitfld.long 0x14 1. "SFW161,Shadowed fuse word 161" "0: Fuse word 161 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR161 register." bitfld.long 0x14 0. "SFW160,Shadowed fuse word 160" "0: Fuse word 160 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR160 register." line.long 0x18 "BSEC_SFSR6,BSEC shadowed fuses status register 6" bitfld.long 0x18 31. "SFW223,Shadowed fuse word 223" "0: Fuse word 223 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR223 register." bitfld.long 0x18 30. "SFW222,Shadowed fuse word 222" "0: Fuse word 222 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR222 register." newline bitfld.long 0x18 29. "SFW221,Shadowed fuse word 221" "0: Fuse word 221 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR221 register." bitfld.long 0x18 28. "SFW220,Shadowed fuse word 220" "0: Fuse word 220 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR220 register." newline bitfld.long 0x18 27. "SFW219,Shadowed fuse word 219" "0: Fuse word 219 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR219 register." bitfld.long 0x18 26. "SFW218,Shadowed fuse word 218" "0: Fuse word 218 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR218 register." newline bitfld.long 0x18 25. "SFW217,Shadowed fuse word 217" "0: Fuse word 217 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR217 register." bitfld.long 0x18 24. "SFW216,Shadowed fuse word 216" "0: Fuse word 216 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR216 register." newline bitfld.long 0x18 23. "SFW215,Shadowed fuse word 215" "0: Fuse word 215 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR215 register." bitfld.long 0x18 22. "SFW214,Shadowed fuse word 214" "0: Fuse word 214 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR214 register." newline bitfld.long 0x18 21. "SFW213,Shadowed fuse word 213" "0: Fuse word 213 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR213 register." bitfld.long 0x18 20. "SFW212,Shadowed fuse word 212" "0: Fuse word 212 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR212 register." newline bitfld.long 0x18 19. "SFW211,Shadowed fuse word 211" "0: Fuse word 211 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR211 register." bitfld.long 0x18 18. "SFW210,Shadowed fuse word 210" "0: Fuse word 210 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR210 register." newline bitfld.long 0x18 17. "SFW209,Shadowed fuse word 209" "0: Fuse word 209 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR209 register." bitfld.long 0x18 16. "SFW208,Shadowed fuse word 208" "0: Fuse word 208 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR208 register." newline bitfld.long 0x18 15. "SFW207,Shadowed fuse word 207" "0: Fuse word 207 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR207 register." bitfld.long 0x18 14. "SFW206,Shadowed fuse word 206" "0: Fuse word 206 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR206 register." newline bitfld.long 0x18 13. "SFW205,Shadowed fuse word 205" "0: Fuse word 205 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR205 register." bitfld.long 0x18 12. "SFW204,Shadowed fuse word 204" "0: Fuse word 204 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR204 register." newline bitfld.long 0x18 11. "SFW203,Shadowed fuse word 203" "0: Fuse word 203 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR203 register." bitfld.long 0x18 10. "SFW202,Shadowed fuse word 202" "0: Fuse word 202 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR202 register." newline bitfld.long 0x18 9. "SFW201,Shadowed fuse word 201" "0: Fuse word 201 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR201 register." bitfld.long 0x18 8. "SFW200,Shadowed fuse word 200" "0: Fuse word 200 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR200 register." newline bitfld.long 0x18 7. "SFW199,Shadowed fuse word 199" "0: Fuse word 199 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR199 register." bitfld.long 0x18 6. "SFW198,Shadowed fuse word 198" "0: Fuse word 198 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR198 register." newline bitfld.long 0x18 5. "SFW197,Shadowed fuse word 197" "0: Fuse word 197 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR197 register." bitfld.long 0x18 4. "SFW196,Shadowed fuse word 196" "0: Fuse word 196 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR196 register." newline bitfld.long 0x18 3. "SFW195,Shadowed fuse word 195" "0: Fuse word 195 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR195 register." bitfld.long 0x18 2. "SFW194,Shadowed fuse word 194" "0: Fuse word 194 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR194 register." newline bitfld.long 0x18 1. "SFW193,Shadowed fuse word 193" "0: Fuse word 193 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR193 register." bitfld.long 0x18 0. "SFW192,Shadowed fuse word 192" "0: Fuse word 192 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR192 register." line.long 0x1C "BSEC_SFSR7,BSEC shadowed fuses status register 7" bitfld.long 0x1C 31. "SFW255,Shadowed fuse word 255" "0: Fuse word 255 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR255 register." bitfld.long 0x1C 30. "SFW254,Shadowed fuse word 254" "0: Fuse word 254 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR254 register." newline bitfld.long 0x1C 29. "SFW253,Shadowed fuse word 253" "0: Fuse word 253 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR253 register." bitfld.long 0x1C 28. "SFW252,Shadowed fuse word 252" "0: Fuse word 252 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR252 register." newline bitfld.long 0x1C 27. "SFW251,Shadowed fuse word 251" "0: Fuse word 251 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR251 register." bitfld.long 0x1C 26. "SFW250,Shadowed fuse word 250" "0: Fuse word 250 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR250 register." newline bitfld.long 0x1C 25. "SFW249,Shadowed fuse word 249" "0: Fuse word 249 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR249 register." bitfld.long 0x1C 24. "SFW248,Shadowed fuse word 248" "0: Fuse word 248 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR248 register." newline bitfld.long 0x1C 23. "SFW247,Shadowed fuse word 247" "0: Fuse word 247 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR247 register." bitfld.long 0x1C 22. "SFW246,Shadowed fuse word 246" "0: Fuse word 246 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR246 register." newline bitfld.long 0x1C 21. "SFW245,Shadowed fuse word 245" "0: Fuse word 245 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR245 register." bitfld.long 0x1C 20. "SFW244,Shadowed fuse word 244" "0: Fuse word 244 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR244 register." newline bitfld.long 0x1C 19. "SFW243,Shadowed fuse word 243" "0: Fuse word 243 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR243 register." bitfld.long 0x1C 18. "SFW242,Shadowed fuse word 242" "0: Fuse word 242 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR242 register." newline bitfld.long 0x1C 17. "SFW241,Shadowed fuse word 241" "0: Fuse word 241 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR241 register." bitfld.long 0x1C 16. "SFW240,Shadowed fuse word 240" "0: Fuse word 240 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR240 register." newline bitfld.long 0x1C 15. "SFW239,Shadowed fuse word 239" "0: Fuse word 239 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR239 register." bitfld.long 0x1C 14. "SFW238,Shadowed fuse word 238" "0: Fuse word 238 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR238 register." newline bitfld.long 0x1C 13. "SFW237,Shadowed fuse word 237" "0: Fuse word 237 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR237 register." bitfld.long 0x1C 12. "SFW236,Shadowed fuse word 236" "0: Fuse word 236 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR236 register." newline bitfld.long 0x1C 11. "SFW235,Shadowed fuse word 235" "0: Fuse word 235 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR235 register." bitfld.long 0x1C 10. "SFW234,Shadowed fuse word 234" "0: Fuse word 234 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR234 register." newline bitfld.long 0x1C 9. "SFW233,Shadowed fuse word 233" "0: Fuse word 233 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR233 register." bitfld.long 0x1C 8. "SFW232,Shadowed fuse word 232" "0: Fuse word 232 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR232 register." newline bitfld.long 0x1C 7. "SFW231,Shadowed fuse word 231" "0: Fuse word 231 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR231 register." bitfld.long 0x1C 6. "SFW230,Shadowed fuse word 230" "0: Fuse word 230 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR230 register." newline bitfld.long 0x1C 5. "SFW229,Shadowed fuse word 229" "0: Fuse word 229 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR229 register." bitfld.long 0x1C 4. "SFW228,Shadowed fuse word 228" "0: Fuse word 228 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR228 register." newline bitfld.long 0x1C 3. "SFW227,Shadowed fuse word 227" "0: Fuse word 227 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR227 register." bitfld.long 0x1C 2. "SFW226,Shadowed fuse word 226" "0: Fuse word 226 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR226 register." newline bitfld.long 0x1C 1. "SFW225,Shadowed fuse word 225" "0: Fuse word 225 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR225 register." bitfld.long 0x1C 0. "SFW224,Shadowed fuse word 224" "0: Fuse word 224 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR224 register." line.long 0x20 "BSEC_SFSR8,BSEC shadowed fuses status register 8" bitfld.long 0x20 31. "SFW287,Shadowed fuse word 287" "0: Fuse word 287 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR287 register." bitfld.long 0x20 30. "SFW286,Shadowed fuse word 286" "0: Fuse word 286 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR286 register." newline bitfld.long 0x20 29. "SFW285,Shadowed fuse word 285" "0: Fuse word 285 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR285 register." bitfld.long 0x20 28. "SFW284,Shadowed fuse word 284" "0: Fuse word 284 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR284 register." newline bitfld.long 0x20 27. "SFW283,Shadowed fuse word 283" "0: Fuse word 283 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR283 register." bitfld.long 0x20 26. "SFW282,Shadowed fuse word 282" "0: Fuse word 282 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR282 register." newline bitfld.long 0x20 25. "SFW281,Shadowed fuse word 281" "0: Fuse word 281 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR281 register." bitfld.long 0x20 24. "SFW280,Shadowed fuse word 280" "0: Fuse word 280 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR280 register." newline bitfld.long 0x20 23. "SFW279,Shadowed fuse word 279" "0: Fuse word 279 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR279 register." bitfld.long 0x20 22. "SFW278,Shadowed fuse word 278" "0: Fuse word 278 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR278 register." newline bitfld.long 0x20 21. "SFW277,Shadowed fuse word 277" "0: Fuse word 277 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR277 register." bitfld.long 0x20 20. "SFW276,Shadowed fuse word 276" "0: Fuse word 276 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR276 register." newline bitfld.long 0x20 19. "SFW275,Shadowed fuse word 275" "0: Fuse word 275 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR275 register." bitfld.long 0x20 18. "SFW274,Shadowed fuse word 274" "0: Fuse word 274 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR274 register." newline bitfld.long 0x20 17. "SFW273,Shadowed fuse word 273" "0: Fuse word 273 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR273 register." bitfld.long 0x20 16. "SFW272,Shadowed fuse word 272" "0: Fuse word 272 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR272 register." newline bitfld.long 0x20 15. "SFW271,Shadowed fuse word 271" "0: Fuse word 271 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR271 register." bitfld.long 0x20 14. "SFW270,Shadowed fuse word 270" "0: Fuse word 270 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR270 register." newline bitfld.long 0x20 13. "SFW269,Shadowed fuse word 269" "0: Fuse word 269 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR269 register." bitfld.long 0x20 12. "SFW268,Shadowed fuse word 268" "0: Fuse word 268 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR268 register." newline bitfld.long 0x20 11. "SFW267,Shadowed fuse word 267" "0: Fuse word 267 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR267 register." bitfld.long 0x20 10. "SFW266,Shadowed fuse word 266" "0: Fuse word 266 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR266 register." newline bitfld.long 0x20 9. "SFW265,Shadowed fuse word 265" "0: Fuse word 265 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR265 register." bitfld.long 0x20 8. "SFW264,Shadowed fuse word 264" "0: Fuse word 264 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR264 register." newline bitfld.long 0x20 7. "SFW263,Shadowed fuse word 263" "0: Fuse word 263 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR263 register." bitfld.long 0x20 6. "SFW262,Shadowed fuse word 262" "0: Fuse word 262 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR262 register." newline bitfld.long 0x20 5. "SFW261,Shadowed fuse word 261" "0: Fuse word 261 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR261 register." bitfld.long 0x20 4. "SFW260,Shadowed fuse word 260" "0: Fuse word 260 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR260 register." newline bitfld.long 0x20 3. "SFW259,Shadowed fuse word 259" "0: Fuse word 259 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR259 register." bitfld.long 0x20 2. "SFW258,Shadowed fuse word 258" "0: Fuse word 258 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR258 register." newline bitfld.long 0x20 1. "SFW257,Shadowed fuse word 257" "0: Fuse word 257 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR257 register." bitfld.long 0x20 0. "SFW256,Shadowed fuse word 256" "0: Fuse word 256 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR256 register." line.long 0x24 "BSEC_SFSR9,BSEC shadowed fuses status register 9" bitfld.long 0x24 31. "SFW319,Shadowed fuse word 319" "0: Fuse word 319 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR319 register." bitfld.long 0x24 30. "SFW318,Shadowed fuse word 318" "0: Fuse word 318 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR318 register." newline bitfld.long 0x24 29. "SFW317,Shadowed fuse word 317" "0: Fuse word 317 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR317 register." bitfld.long 0x24 28. "SFW316,Shadowed fuse word 316" "0: Fuse word 316 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR316 register." newline bitfld.long 0x24 27. "SFW315,Shadowed fuse word 315" "0: Fuse word 315 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR315 register." bitfld.long 0x24 26. "SFW314,Shadowed fuse word 314" "0: Fuse word 314 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR314 register." newline bitfld.long 0x24 25. "SFW313,Shadowed fuse word 313" "0: Fuse word 313 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR313 register." bitfld.long 0x24 24. "SFW312,Shadowed fuse word 312" "0: Fuse word 312 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR312 register." newline bitfld.long 0x24 23. "SFW311,Shadowed fuse word 311" "0: Fuse word 311 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR311 register." bitfld.long 0x24 22. "SFW310,Shadowed fuse word 310" "0: Fuse word 310 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR310 register." newline bitfld.long 0x24 21. "SFW309,Shadowed fuse word 309" "0: Fuse word 309 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR309 register." bitfld.long 0x24 20. "SFW308,Shadowed fuse word 308" "0: Fuse word 308 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR308 register." newline bitfld.long 0x24 19. "SFW307,Shadowed fuse word 307" "0: Fuse word 307 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR307 register." bitfld.long 0x24 18. "SFW306,Shadowed fuse word 306" "0: Fuse word 306 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR306 register." newline bitfld.long 0x24 17. "SFW305,Shadowed fuse word 305" "0: Fuse word 305 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR305 register." bitfld.long 0x24 16. "SFW304,Shadowed fuse word 304" "0: Fuse word 304 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR304 register." newline bitfld.long 0x24 15. "SFW303,Shadowed fuse word 303" "0: Fuse word 303 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR303 register." bitfld.long 0x24 14. "SFW302,Shadowed fuse word 302" "0: Fuse word 302 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR302 register." newline bitfld.long 0x24 13. "SFW301,Shadowed fuse word 301" "0: Fuse word 301 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR301 register." bitfld.long 0x24 12. "SFW300,Shadowed fuse word 300" "0: Fuse word 300 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR300 register." newline bitfld.long 0x24 11. "SFW299,Shadowed fuse word 299" "0: Fuse word 299 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR299 register." bitfld.long 0x24 10. "SFW298,Shadowed fuse word 298" "0: Fuse word 298 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR298 register." newline bitfld.long 0x24 9. "SFW297,Shadowed fuse word 297" "0: Fuse word 297 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR297 register." bitfld.long 0x24 8. "SFW296,Shadowed fuse word 296" "0: Fuse word 296 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR296 register." newline bitfld.long 0x24 7. "SFW295,Shadowed fuse word 295" "0: Fuse word 295 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR295 register." bitfld.long 0x24 6. "SFW294,Shadowed fuse word 294" "0: Fuse word 294 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR294 register." newline bitfld.long 0x24 5. "SFW293,Shadowed fuse word 293" "0: Fuse word 293 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR293 register." bitfld.long 0x24 4. "SFW292,Shadowed fuse word 292" "0: Fuse word 292 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR292 register." newline bitfld.long 0x24 3. "SFW291,Shadowed fuse word 291" "0: Fuse word 291 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR291 register." bitfld.long 0x24 2. "SFW290,Shadowed fuse word 290" "0: Fuse word 290 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR290 register." newline bitfld.long 0x24 1. "SFW289,Shadowed fuse word 289" "0: Fuse word 289 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR289 register." bitfld.long 0x24 0. "SFW288,Shadowed fuse word 288" "0: Fuse word 288 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR288 register." line.long 0x28 "BSEC_SFSR10,BSEC shadowed fuses status register 10" bitfld.long 0x28 31. "SFW351,Shadowed fuse word 351" "0: Fuse word 351 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR351 register." bitfld.long 0x28 30. "SFW350,Shadowed fuse word 350" "0: Fuse word 350 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR350 register." newline bitfld.long 0x28 29. "SFW349,Shadowed fuse word 349" "0: Fuse word 349 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR349 register." bitfld.long 0x28 28. "SFW348,Shadowed fuse word 348" "0: Fuse word 348 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR348 register." newline bitfld.long 0x28 27. "SFW347,Shadowed fuse word 347" "0: Fuse word 347 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR347 register." bitfld.long 0x28 26. "SFW346,Shadowed fuse word 346" "0: Fuse word 346 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR346 register." newline bitfld.long 0x28 25. "SFW345,Shadowed fuse word 345" "0: Fuse word 345 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR345 register." bitfld.long 0x28 24. "SFW344,Shadowed fuse word 344" "0: Fuse word 344 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR344 register." newline bitfld.long 0x28 23. "SFW343,Shadowed fuse word 343" "0: Fuse word 343 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR343 register." bitfld.long 0x28 22. "SFW342,Shadowed fuse word 342" "0: Fuse word 342 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR342 register." newline bitfld.long 0x28 21. "SFW341,Shadowed fuse word 341" "0: Fuse word 341 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR341 register." bitfld.long 0x28 20. "SFW340,Shadowed fuse word 340" "0: Fuse word 340 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR340 register." newline bitfld.long 0x28 19. "SFW339,Shadowed fuse word 339" "0: Fuse word 339 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR339 register." bitfld.long 0x28 18. "SFW338,Shadowed fuse word 338" "0: Fuse word 338 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR338 register." newline bitfld.long 0x28 17. "SFW337,Shadowed fuse word 337" "0: Fuse word 337 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR337 register." bitfld.long 0x28 16. "SFW336,Shadowed fuse word 336" "0: Fuse word 336 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR336 register." newline bitfld.long 0x28 15. "SFW335,Shadowed fuse word 335" "0: Fuse word 335 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR335 register." bitfld.long 0x28 14. "SFW334,Shadowed fuse word 334" "0: Fuse word 334 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR334 register." newline bitfld.long 0x28 13. "SFW333,Shadowed fuse word 333" "0: Fuse word 333 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR333 register." bitfld.long 0x28 12. "SFW332,Shadowed fuse word 332" "0: Fuse word 332 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR332 register." newline bitfld.long 0x28 11. "SFW331,Shadowed fuse word 331" "0: Fuse word 331 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR331 register." bitfld.long 0x28 10. "SFW330,Shadowed fuse word 330" "0: Fuse word 330 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR330 register." newline bitfld.long 0x28 9. "SFW329,Shadowed fuse word 329" "0: Fuse word 329 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR329 register." bitfld.long 0x28 8. "SFW328,Shadowed fuse word 328" "0: Fuse word 328 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR328 register." newline bitfld.long 0x28 7. "SFW327,Shadowed fuse word 327" "0: Fuse word 327 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR327 register." bitfld.long 0x28 6. "SFW326,Shadowed fuse word 326" "0: Fuse word 326 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR326 register." newline bitfld.long 0x28 5. "SFW325,Shadowed fuse word 325" "0: Fuse word 325 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR325 register." bitfld.long 0x28 4. "SFW324,Shadowed fuse word 324" "0: Fuse word 324 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR324 register." newline bitfld.long 0x28 3. "SFW323,Shadowed fuse word 323" "0: Fuse word 323 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR323 register." bitfld.long 0x28 2. "SFW322,Shadowed fuse word 322" "0: Fuse word 322 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR322 register." newline bitfld.long 0x28 1. "SFW321,Shadowed fuse word 321" "0: Fuse word 321 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR321 register." bitfld.long 0x28 0. "SFW320,Shadowed fuse word 320" "0: Fuse word 320 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR320 register." line.long 0x2C "BSEC_SFSR11,BSEC shadowed fuses status register 11" bitfld.long 0x2C 31. "SFW383,Shadowed fuse word 383" "0: Fuse word 383 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR383 register." bitfld.long 0x2C 30. "SFW382,Shadowed fuse word 382" "0: Fuse word 382 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR382 register." newline bitfld.long 0x2C 29. "SFW381,Shadowed fuse word 381" "0: Fuse word 381 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR381 register." bitfld.long 0x2C 28. "SFW380,Shadowed fuse word 380" "0: Fuse word 380 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR380 register." newline bitfld.long 0x2C 27. "SFW379,Shadowed fuse word 379" "0: Fuse word 379 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR379 register." bitfld.long 0x2C 26. "SFW378,Shadowed fuse word 378" "0: Fuse word 378 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR378 register." newline bitfld.long 0x2C 25. "SFW377,Shadowed fuse word 377" "0: Fuse word 377 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR377 register." bitfld.long 0x2C 24. "SFW376,Shadowed fuse word 376" "0: Fuse word 376 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR376 register." newline bitfld.long 0x2C 23. "SFW375,Shadowed fuse word 375" "0: Fuse word 375 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR375 register." bitfld.long 0x2C 22. "SFW374,Shadowed fuse word 374" "0: Fuse word 374 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR374 register." newline bitfld.long 0x2C 21. "SFW373,Shadowed fuse word 373" "0: Fuse word 373 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR373 register." bitfld.long 0x2C 20. "SFW372,Shadowed fuse word 372" "0: Fuse word 372 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR372 register." newline bitfld.long 0x2C 19. "SFW371,Shadowed fuse word 371" "0: Fuse word 371 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR371 register." bitfld.long 0x2C 18. "SFW370,Shadowed fuse word 370" "0: Fuse word 370 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR370 register." newline bitfld.long 0x2C 17. "SFW369,Shadowed fuse word 369" "0: Fuse word 369 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR369 register." bitfld.long 0x2C 16. "SFW368,Shadowed fuse word 368" "0: Fuse word 368 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR368 register." newline bitfld.long 0x2C 15. "SFW367,Shadowed fuse word 367" "0: Fuse word 367 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR367 register." bitfld.long 0x2C 14. "SFW366,Shadowed fuse word 366" "0: Fuse word 366 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR366 register." newline bitfld.long 0x2C 13. "SFW365,Shadowed fuse word 365" "0: Fuse word 365 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR365 register." bitfld.long 0x2C 12. "SFW364,Shadowed fuse word 364" "0: Fuse word 364 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR364 register." newline bitfld.long 0x2C 11. "SFW363,Shadowed fuse word 363" "0: Fuse word 363 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR363 register." bitfld.long 0x2C 10. "SFW362,Shadowed fuse word 362" "0: Fuse word 362 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR362 register." newline bitfld.long 0x2C 9. "SFW361,Shadowed fuse word 361" "0: Fuse word 361 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR361 register." bitfld.long 0x2C 8. "SFW360,Shadowed fuse word 360" "0: Fuse word 360 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR360 register." newline bitfld.long 0x2C 7. "SFW359,Shadowed fuse word 359" "0: Fuse word 359 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR359 register." bitfld.long 0x2C 6. "SFW358,Shadowed fuse word 358" "0: Fuse word 358 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR358 register." newline bitfld.long 0x2C 5. "SFW357,Shadowed fuse word 357" "0: Fuse word 357 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR357 register." bitfld.long 0x2C 4. "SFW356,Shadowed fuse word 356" "0: Fuse word 356 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR356 register." newline bitfld.long 0x2C 3. "SFW355,Shadowed fuse word 355" "0: Fuse word 355 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR355 register." bitfld.long 0x2C 2. "SFW354,Shadowed fuse word 354" "0: Fuse word 354 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR354 register." newline bitfld.long 0x2C 1. "SFW353,Shadowed fuse word 353" "0: Fuse word 353 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR353 register." bitfld.long 0x2C 0. "SFW352,Shadowed fuse word 352" "0: Fuse word 352 is not shadowed. Fuse value must..,1: Fuse word is shadowed in BSEC_FVR352 register." group.long 0xC04++0x3 line.long 0x0 "BSEC_OTPCR,BSEC OTP control register" rbitfld.long 0x0 19.--21. "LASTCID,Last CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 14. "PPLOCK,Permanent programming lock" "0: Fuse word at address ADDR[8:0] is programmed..,1: Fuse word at address ADDR[8:0] is locked.." newline bitfld.long 0x0 13. "PROG,Fuse word programming" "0: Fuse word read operation is required,1: Fuse word programming operation is required" hexmask.long.word 0x0 0.--8. 1. "ADDR,Fuse word address" wgroup.long 0xC08++0x3 line.long 0x0 "BSEC_WDR,BSEC write data register" hexmask.long 0x0 0.--31. 1. "WRDATA,OTP write data" group.long 0xE00++0x13 line.long 0x0 "BSEC_SCRATCHR0,BSEC scratch register 0" hexmask.long 0x0 0.--31. 1. "SDATA,Scratch data" line.long 0x4 "BSEC_SCRATCHR1,BSEC scratch register 1" hexmask.long 0x4 0.--31. 1. "SDATA,Scratch data" line.long 0x8 "BSEC_SCRATCHR2,BSEC scratch register 2" hexmask.long 0x8 0.--31. 1. "SDATA,Scratch data" line.long 0xC "BSEC_SCRATCHR3,BSEC scratch register 3" hexmask.long 0xC 0.--31. 1. "SDATA,Scratch data" line.long 0x10 "BSEC_LOCKR,BSEC lock register" bitfld.long 0x10 2. "HKLOCK,Hardware key lock" "0: Derived hardware unique key (DHUK) in SAES..,1: Derived hardware unique key (DHUK) in SAES.." bitfld.long 0x10 0. "GWLOCK,Global write lock" "0: Writes to BSEC registers are allowed,1: Writes to BSEC registers are ignored (fuse.." rgroup.long 0xE14++0x3 line.long 0x0 "BSEC_JTAGINR,BSEC JTAG input register" hexmask.long 0x0 0.--31. 1. "JDATAIN,JTAG input data" wgroup.long 0xE18++0x3 line.long 0x0 "BSEC_JTAGOUTR,BSEC JTAG output register" hexmask.long 0x0 0.--31. 1. "JDATAOUT,JTAG output data" group.long 0xE24++0x3 line.long 0x0 "BSEC_UNMAPR,BSEC unmap register" hexmask.long 0x0 0.--31. 1. "UNMAP,Unmap key" rgroup.long 0xE40++0x7 line.long 0x0 "BSEC_SR,BSEC status register" hexmask.long.byte 0x0 26.--31. 1. "NVSTATE,Non-volatile state" bitfld.long 0x0 16. "DBGREQ,debug request" "0: Host debugger is not requesting debug,1: Host debugger is requesting debug" newline bitfld.long 0x0 1. "HVALID,Hardware key valid" "0: Derived hardware unique key (DHUK) feature..,1: Derived hardware unique key (DHUK) feature can.." line.long 0x4 "BSEC_OTPSR,BSEC OTP status register" bitfld.long 0x4 22. "AMEF,Addresses mismatch error flag" "0,1" bitfld.long 0x4 21. "PPLMF,Permanent programming lock mismatch flag" "0,1" newline bitfld.long 0x4 20. "PPLF,Permanent programming lock flag" "0,1" bitfld.long 0x4 19. "SECF,Single error correction flag" "0,1" newline bitfld.long 0x4 18. "DEDF,Double error detection flag" "0,1" bitfld.long 0x4 17. "DISTURBF,Disturb flag" "0,1" newline bitfld.long 0x4 16. "PROGFAIL,Programming failed" "0,1" bitfld.long 0x4 6. "OTPSEC,OTP with single error correction" "0,1" newline bitfld.long 0x4 5. "OTPERR,OTP with error" "0,1" bitfld.long 0x4 4. "OTPNVIR,OTP not virgin" "0,1" newline bitfld.long 0x4 2. "HIDEUP,Hide upper fuse words" "0,1" bitfld.long 0x4 1. "INIT_DONE,Initialization done" "0,1" newline bitfld.long 0x4 0. "BUSY,Busy flag" "0: BSEC is idle,1: BSEC is busy" group.long 0xE80++0x13 line.long 0x0 "BSEC_EPOCHR0,BSEC epoch register" hexmask.long 0x0 0.--31. 1. "EPOCH,epoch" line.long 0x4 "BSEC_EPOCHR1,BSEC epoch register" hexmask.long 0x4 0.--31. 1. "EPOCH,epoch" line.long 0x8 "BSEC_EPOCH_SELR,BSEC epoch select register" bitfld.long 0x8 0. "EPSEL,Epoch selection. This value is wired out to the SAES peripheral." "0: SAES peripheral uses BSEC_EPOCHR0 as EPOCH value.,1: SAES peripheral uses BSEC_EPOCHR1 as EPOCH value." line.long 0xC "BSEC_DBGCR,BSEC Debug" hexmask.long.byte 0xC 24.--31. 1. "AUTH_SEC,any other value: secure debug not authorized (provided BSEC state is not OPEN)" hexmask.long.byte 0xC 16.--23. 1. "AUTH_HDPL,level at which debug may be opened." newline hexmask.long.byte 0xC 8.--15. 1. "UNLOCK,any other value: debug not authorized (provided BSEC state is not OPEN)" line.long 0x10 "BSEC_AP_UNLOCK,BSEC AP Unlock" hexmask.long.byte 0x10 0.--7. 1. "UNLOCK,any other value: do not unlock" rgroup.long 0xE94++0x3 line.long 0x0 "BSEC_HDPLSR,BSEC HDPL" hexmask.long.byte 0x0 0.--7. 1. "HDPL,current HDPL" wgroup.long 0xE98++0x3 line.long 0x0 "BSEC_HDPLCR,BSEC HDPL control" hexmask.long 0x0 0.--31. 1. "INCR_HDPL,Increment HDPL" group.long 0xE9C++0x3 line.long 0x0 "BSEC_NEXTLR,BSEC Next HDPL" bitfld.long 0x0 0.--1. "INCR,Increment" "0,1,2,3" group.long 0xF40++0x1F line.long 0x0 "BSEC_WOSCR0,BSEC write once scratch register 0" hexmask.long 0x0 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x4 "BSEC_WOSCR1,BSEC write once scratch register 1" hexmask.long 0x4 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x8 "BSEC_WOSCR2,BSEC write once scratch register 2" hexmask.long 0x8 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0xC "BSEC_WOSCR3,BSEC write once scratch register 3" hexmask.long 0xC 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x10 "BSEC_WOSCR4,BSEC write once scratch register 4" hexmask.long 0x10 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x14 "BSEC_WOSCR5,BSEC write once scratch register 5" hexmask.long 0x14 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x18 "BSEC_WOSCR6,BSEC write once scratch register 6" hexmask.long 0x18 0.--31. 1. "WOSDATA,Write once scratch data" line.long 0x1C "BSEC_WOSCR7,BSEC write once scratch register 7" hexmask.long 0x1C 0.--31. 1. "WOSDATA,Write once scratch data" rgroup.long 0xFE8++0x7 line.long 0x0 "BSEC_HRCR,BSEC hot reset count register" hexmask.long 0x0 0.--31. 1. "HRC,hot reset counter" line.long 0x4 "BSEC_WRCR,BSEC warm reset count register" hexmask.long 0x4 0.--31. 1. "WRC,Warm reset counter" tree.end tree.end tree "CACHEAXI (AXI Cache)" base ad:0x0 tree "CACHEAXI" base ad:0x480DFC00 group.long 0x0++0x3 line.long 0x0 "CACHEAXI_CR1,CACHEAXI control register 1" bitfld.long 0x0 31. "EVIMRST,eviction monitor reset" "0: no effect,1: reset cache eviction monitor" bitfld.long 0x0 30. "WTMRST,write-through monitor reset" "0: no effect,1: reset cache write-through monitor" newline bitfld.long 0x0 29. "EVIMEN,eviction monitor enable" "0: cache eviction monitor switched off. Stopping..,1: cache eviction monitor enabled" bitfld.long 0x0 28. "WTMEN,write-through monitor enable" "0: cache write-through monitor switched off.,1: cache write-through monitor enabled" newline bitfld.long 0x0 27. "WAMMRST,write-allocate miss monitor reset" "0: no effect,1: reset cache write-allocate miss monitor" bitfld.long 0x0 26. "RAMMRST,read-allocate miss monitor reset" "0: no effect,1: reset cache read-allocate miss monitor" newline bitfld.long 0x0 25. "WAMMEN,write-allocate miss monitor enable" "0: cache write-allocate miss monitor switched off.,1: cache write-allocate miss monitor enabled" bitfld.long 0x0 24. "RAMMEN,read-allocate miss monitor enable" "0: cache read-allocate miss monitor switched off.,1: cache read-allocate miss monitor enabled" newline bitfld.long 0x0 23. "WMISSMRST,write-miss monitor reset" "0: no effect,1: reset cache write-miss monitor" bitfld.long 0x0 22. "WHITMRST,write-hit monitor reset" "0: no effect,1: reset cache write-hit monitor" newline bitfld.long 0x0 21. "WMISSMEN,write-miss monitor enable" "0: cache write-miss monitor switched off. Stopping..,1: cache write-miss monitor enabled" bitfld.long 0x0 20. "WHITMEN,write-hit monitor enable" "0: cache write-hit monitor switched off. Stopping..,1: cache write-hit monitor enabled" newline bitfld.long 0x0 19. "RMISSMRST,read-miss monitor reset" "0: no effect,1: reset cache read-miss monitor" bitfld.long 0x0 18. "RHITMRST,read-hit monitor reset" "0: no effect,1: reset cache read-hit monitor" newline bitfld.long 0x0 17. "RMISSMEN,read-miss monitor enable" "0: cache read-miss monitor switched off. Stopping..,1: cache read-miss monitor enabled" bitfld.long 0x0 16. "RHITMEN,read-hit monitor enable" "0: cache read-hit monitor switched off. Stopping..,1: cache read-hit monitor enabled" newline bitfld.long 0x0 1. "CACHEINV,full cache invalidation" "0: no effect,1: invalidate entire cache (all cache lines valid.." bitfld.long 0x0 0. "EN,enable" "0: cache mode disabled (CACHEAXI bypassed or in..,1: cache mode enabled" rgroup.long 0x4++0x3 line.long 0x0 "CACHEAXI_SR,CACHEAXI status register" bitfld.long 0x0 4. "CMDENDF,command end flag" "0: cache busy or in idle,1: CACHECMD command finished" bitfld.long 0x0 3. "BUSYCMDF,command busy flag" "0: cache not busy on a CACHECMD command,1: cache busy on a CACHECMD command (clean or.." newline bitfld.long 0x0 2. "ERRF,cache error flag" "0: no error,1: an error occurred during the operation (eviction.." bitfld.long 0x0 1. "BSYENDF,full invalidate busy end flag" "0: cache busy or in idle,1: full invalidate CACHEINV operation finished" newline bitfld.long 0x0 0. "BUSYF,full invalidate busy flag" "0: cache not busy on a CACHEINV operation,1: cache executing a full invalidate CACHEINV.." group.long 0x8++0x3 line.long 0x0 "CACHEAXI_IER,CACHEAXI interrupt enable register" bitfld.long 0x0 4. "CMDENDIE,interrupt enable on command end" "0: interrupt disabled on command end,1: interrupt enabled on command end" bitfld.long 0x0 2. "ERRIE,interrupt enable on cache error" "0: interrupt disabled on error,1: interrupt enabled on error" newline bitfld.long 0x0 1. "BSYENDIE,interrupt enable on busy end" "0: Interrupt disabled on busy end,1: Interrupt enabled on busy end" wgroup.long 0xC++0x3 line.long 0x0 "CACHEAXI_FCR,CACHEAXI flag clear register" bitfld.long 0x0 4. "CCMDENDF,clear command end flag" "0: no effect,1: clears CMDENDF flag in CACHEAXI_SR." bitfld.long 0x0 2. "CERRF,clear cache error flag" "0: no effect,1: clears ERRF flag in CACHEAXI_SR." newline bitfld.long 0x0 1. "CBSYENDF,clear full invalidate busy end flag" "0: no effect,1: clears BSYENDF flag in CACHEAXI_SR." rgroup.long 0x10++0x1F line.long 0x0 "CACHEAXI_RHMONR,CACHEAXI read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,cache read-hit monitor counter" line.long 0x4 "CACHEAXI_RMMONR,CACHEAXI read-miss monitor register" hexmask.long 0x4 0.--31. 1. "RMISSMON,cache read-miss monitor counter" line.long 0x8 "CACHEAXI_RAMMONR,CACHEAXI read-allocate miss monitor register" hexmask.long 0x8 0.--31. 1. "RAMMON,cache read-allocate miss monitor counter" line.long 0xC "CACHEAXI_EVIMONR,CACHEAXI eviction monitor register" hexmask.long 0xC 0.--31. 1. "EVIMON,cache eviction monitor counter" line.long 0x10 "CACHEAXI_WHMONR,CACHEAXI write-hit monitor register" hexmask.long 0x10 0.--31. 1. "WHITMON,cache write-hit monitor counter" line.long 0x14 "CACHEAXI_WMMONR,CACHEAXI write-miss monitor register" hexmask.long 0x14 0.--31. 1. "WMISSMON,cache write-miss monitor counter" line.long 0x18 "CACHEAXI_WAMMONR,CACHEAXI write-allocate miss monitor register" hexmask.long 0x18 0.--31. 1. "WAMMON,cache write-allocate miss monitor counter" line.long 0x1C "CACHEAXI_WTMONR,CACHEAXI write-through monitor register" hexmask.long 0x1C 0.--31. 1. "WTMON,cache write-through monitor counter" group.long 0x100++0xB line.long 0x0 "CACHEAXI_CR2,CACHEAXI control register 2" bitfld.long 0x0 1.--2. "CACHECMD,cache command maintenance operation (clean or clean-and-invalidate an address range)" "0: no operation,1: clean range,?,3: clean and invalidate range" bitfld.long 0x0 0. "STARTCMD,starts maintenance range command (maintenance operation defined in CACHECMD)." "0: command operation (cache maintenance) finished,1: start maintenance command (cache maintenance)" line.long 0x4 "CACHEAXI_CMDRSADDRR,CACHEAXI command range start address register" hexmask.long 0x4 6.--31. 1. "CMDSTARTADDR,start address of range to which the cache maintenance command specified in CACHEAXI_CR2.CACHECMD field applies" line.long 0x8 "CACHEAXI_CMDREADDRR,CACHEAXI command range end address register" hexmask.long 0x8 6.--31. 1. "CMDENDADDR,end address of range to which the cache maintenance command specified in CACHEAXI_CR2.CACHECMD field applies" tree.end tree "CACHEAXI_S" base ad:0x580DFC00 group.long 0x0++0x3 line.long 0x0 "CACHEAXI_CR1,CACHEAXI control register 1" bitfld.long 0x0 31. "EVIMRST,eviction monitor reset" "0: no effect,1: reset cache eviction monitor" bitfld.long 0x0 30. "WTMRST,write-through monitor reset" "0: no effect,1: reset cache write-through monitor" newline bitfld.long 0x0 29. "EVIMEN,eviction monitor enable" "0: cache eviction monitor switched off. Stopping..,1: cache eviction monitor enabled" bitfld.long 0x0 28. "WTMEN,write-through monitor enable" "0: cache write-through monitor switched off.,1: cache write-through monitor enabled" newline bitfld.long 0x0 27. "WAMMRST,write-allocate miss monitor reset" "0: no effect,1: reset cache write-allocate miss monitor" bitfld.long 0x0 26. "RAMMRST,read-allocate miss monitor reset" "0: no effect,1: reset cache read-allocate miss monitor" newline bitfld.long 0x0 25. "WAMMEN,write-allocate miss monitor enable" "0: cache write-allocate miss monitor switched off.,1: cache write-allocate miss monitor enabled" bitfld.long 0x0 24. "RAMMEN,read-allocate miss monitor enable" "0: cache read-allocate miss monitor switched off.,1: cache read-allocate miss monitor enabled" newline bitfld.long 0x0 23. "WMISSMRST,write-miss monitor reset" "0: no effect,1: reset cache write-miss monitor" bitfld.long 0x0 22. "WHITMRST,write-hit monitor reset" "0: no effect,1: reset cache write-hit monitor" newline bitfld.long 0x0 21. "WMISSMEN,write-miss monitor enable" "0: cache write-miss monitor switched off. Stopping..,1: cache write-miss monitor enabled" bitfld.long 0x0 20. "WHITMEN,write-hit monitor enable" "0: cache write-hit monitor switched off. Stopping..,1: cache write-hit monitor enabled" newline bitfld.long 0x0 19. "RMISSMRST,read-miss monitor reset" "0: no effect,1: reset cache read-miss monitor" bitfld.long 0x0 18. "RHITMRST,read-hit monitor reset" "0: no effect,1: reset cache read-hit monitor" newline bitfld.long 0x0 17. "RMISSMEN,read-miss monitor enable" "0: cache read-miss monitor switched off. Stopping..,1: cache read-miss monitor enabled" bitfld.long 0x0 16. "RHITMEN,read-hit monitor enable" "0: cache read-hit monitor switched off. Stopping..,1: cache read-hit monitor enabled" newline bitfld.long 0x0 1. "CACHEINV,full cache invalidation" "0: no effect,1: invalidate entire cache (all cache lines valid.." bitfld.long 0x0 0. "EN,enable" "0: cache mode disabled (CACHEAXI bypassed or in..,1: cache mode enabled" rgroup.long 0x4++0x3 line.long 0x0 "CACHEAXI_SR,CACHEAXI status register" bitfld.long 0x0 4. "CMDENDF,command end flag" "0: cache busy or in idle,1: CACHECMD command finished" bitfld.long 0x0 3. "BUSYCMDF,command busy flag" "0: cache not busy on a CACHECMD command,1: cache busy on a CACHECMD command (clean or.." newline bitfld.long 0x0 2. "ERRF,cache error flag" "0: no error,1: an error occurred during the operation (eviction.." bitfld.long 0x0 1. "BSYENDF,full invalidate busy end flag" "0: cache busy or in idle,1: full invalidate CACHEINV operation finished" newline bitfld.long 0x0 0. "BUSYF,full invalidate busy flag" "0: cache not busy on a CACHEINV operation,1: cache executing a full invalidate CACHEINV.." group.long 0x8++0x3 line.long 0x0 "CACHEAXI_IER,CACHEAXI interrupt enable register" bitfld.long 0x0 4. "CMDENDIE,interrupt enable on command end" "0: interrupt disabled on command end,1: interrupt enabled on command end" bitfld.long 0x0 2. "ERRIE,interrupt enable on cache error" "0: interrupt disabled on error,1: interrupt enabled on error" newline bitfld.long 0x0 1. "BSYENDIE,interrupt enable on busy end" "0: Interrupt disabled on busy end,1: Interrupt enabled on busy end" wgroup.long 0xC++0x3 line.long 0x0 "CACHEAXI_FCR,CACHEAXI flag clear register" bitfld.long 0x0 4. "CCMDENDF,clear command end flag" "0: no effect,1: clears CMDENDF flag in CACHEAXI_SR." bitfld.long 0x0 2. "CERRF,clear cache error flag" "0: no effect,1: clears ERRF flag in CACHEAXI_SR." newline bitfld.long 0x0 1. "CBSYENDF,clear full invalidate busy end flag" "0: no effect,1: clears BSYENDF flag in CACHEAXI_SR." rgroup.long 0x10++0x1F line.long 0x0 "CACHEAXI_RHMONR,CACHEAXI read-hit monitor register" hexmask.long 0x0 0.--31. 1. "RHITMON,cache read-hit monitor counter" line.long 0x4 "CACHEAXI_RMMONR,CACHEAXI read-miss monitor register" hexmask.long 0x4 0.--31. 1. "RMISSMON,cache read-miss monitor counter" line.long 0x8 "CACHEAXI_RAMMONR,CACHEAXI read-allocate miss monitor register" hexmask.long 0x8 0.--31. 1. "RAMMON,cache read-allocate miss monitor counter" line.long 0xC "CACHEAXI_EVIMONR,CACHEAXI eviction monitor register" hexmask.long 0xC 0.--31. 1. "EVIMON,cache eviction monitor counter" line.long 0x10 "CACHEAXI_WHMONR,CACHEAXI write-hit monitor register" hexmask.long 0x10 0.--31. 1. "WHITMON,cache write-hit monitor counter" line.long 0x14 "CACHEAXI_WMMONR,CACHEAXI write-miss monitor register" hexmask.long 0x14 0.--31. 1. "WMISSMON,cache write-miss monitor counter" line.long 0x18 "CACHEAXI_WAMMONR,CACHEAXI write-allocate miss monitor register" hexmask.long 0x18 0.--31. 1. "WAMMON,cache write-allocate miss monitor counter" line.long 0x1C "CACHEAXI_WTMONR,CACHEAXI write-through monitor register" hexmask.long 0x1C 0.--31. 1. "WTMON,cache write-through monitor counter" group.long 0x100++0xB line.long 0x0 "CACHEAXI_CR2,CACHEAXI control register 2" bitfld.long 0x0 1.--2. "CACHECMD,cache command maintenance operation (clean or clean-and-invalidate an address range)" "0: no operation,1: clean range,?,3: clean and invalidate range" bitfld.long 0x0 0. "STARTCMD,starts maintenance range command (maintenance operation defined in CACHECMD)." "0: command operation (cache maintenance) finished,1: start maintenance command (cache maintenance)" line.long 0x4 "CACHEAXI_CMDRSADDRR,CACHEAXI command range start address register" hexmask.long 0x4 6.--31. 1. "CMDSTARTADDR,start address of range to which the cache maintenance command specified in CACHEAXI_CR2.CACHECMD field applies" line.long 0x8 "CACHEAXI_CMDREADDRR,CACHEAXI command range end address register" hexmask.long 0x8 6.--31. 1. "CMDENDADDR,end address of range to which the cache maintenance command specified in CACHEAXI_CR2.CACHECMD field applies" tree.end tree.end tree "CRC (Cyclic Redundancy Check)" base ad:0x0 tree "CRC" base ad:0x46024C00 group.long 0x0++0xB line.long 0x0 "CRC_DR,CRC data register" hexmask.long 0x0 0.--31. 1. "DR,Data register bits" line.long 0x4 "CRC_IDR,CRC independent data register" hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register bits" line.long 0x8 "CRC_CR,CRC control register" bitfld.long 0x8 10. "RTYPE_OUT,Reverse type output" "0: Bit level output,1: Byte or half-word level output" bitfld.long 0x8 9. "RTYPE_IN,Reverse type input" "0: Bit level input,1: Byte or half-word level input" newline bitfld.long 0x8 7.--8. "REV_OUT,Reverse output data" "0: Bit order not affected (RTYPE_OUT = 0 or 1),1: Bit-reversed output format (RTYPE_OUT = 0) or..,2: Bit order not affected (RTYPE_OUT = 0) or byte..,3: Bit order not affected (RTYPE_OUT = 0 or 1)" bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected (RTYPE_IN = 0 or 1),1: Bit reversal done by byte (RTYPE_IN = 0) or..,2: Bit reversal done by half-word (RTYPE_IN = 0) or..,3: Bit reversal done by word (RTYPE_IN = 0) or bit.." newline bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial" bitfld.long 0x8 0. "RESET,RESET bit" "0,1" group.long 0x10++0x7 line.long 0x0 "CRC_INIT,CRC initial value" hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC value" line.long 0x4 "CRC_POL,CRC polynomial" hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial" tree.end tree "CRC_S" base ad:0x56024C00 group.long 0x0++0xB line.long 0x0 "CRC_DR,CRC data register" hexmask.long 0x0 0.--31. 1. "DR,Data register bits" line.long 0x4 "CRC_IDR,CRC independent data register" hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register bits" line.long 0x8 "CRC_CR,CRC control register" bitfld.long 0x8 10. "RTYPE_OUT,Reverse type output" "0: Bit level output,1: Byte or half-word level output" bitfld.long 0x8 9. "RTYPE_IN,Reverse type input" "0: Bit level input,1: Byte or half-word level input" newline bitfld.long 0x8 7.--8. "REV_OUT,Reverse output data" "0: Bit order not affected (RTYPE_OUT = 0 or 1),1: Bit-reversed output format (RTYPE_OUT = 0) or..,2: Bit order not affected (RTYPE_OUT = 0) or byte..,3: Bit order not affected (RTYPE_OUT = 0 or 1)" bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected (RTYPE_IN = 0 or 1),1: Bit reversal done by byte (RTYPE_IN = 0) or..,2: Bit reversal done by half-word (RTYPE_IN = 0) or..,3: Bit reversal done by word (RTYPE_IN = 0) or bit.." newline bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial" bitfld.long 0x8 0. "RESET,RESET bit" "0,1" group.long 0x10++0x7 line.long 0x0 "CRC_INIT,CRC initial value" hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC value" line.long 0x4 "CRC_POL,CRC polynomial" hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial" tree.end tree.end sif (cpuis("STM32N655*")||cpuis("STM32N657*")) tree "CRYP (Cryptographic Processor)" base ad:0x0 tree "CRYP" base ad:0x44020800 group.long 0x0++0x3 line.long 0x0 "CRYP_CR,CRYP control register" bitfld.long 0x0 31. "IPRST,CRYP peripheral software reset" "0,1" bitfld.long 0x0 24.--25. "KMOD,Key mode selection" "0: Normal-key mode. Key registers are freely usable.,?,2: Shared-key mode. If shared-key mode is properly..,?" newline hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block" bitfld.long 0x0 19. "ALGOMODE_1,ALGOMODE[3]" "0,1" newline bitfld.long 0x0 16.--17. "GCM_CCMPH,GCM or CCM phase selection" "0: Initialization phase,1: Header phase,2: Payload phase,3: Final phase" bitfld.long 0x0 15. "CRYPEN,CRYP enable" "0: CRYP disabled,1: CRYP enabled" newline bitfld.long 0x0 14. "FFLUSH,FIFO flush" "0: No effect,1: FIFO flush enabled" bitfld.long 0x0 8.--9. "KEYSIZE,Key size selection" "0: 128-bits,1: 192 bits,2: 256 bits,?" newline bitfld.long 0x0 6.--7. "DATATYPE,Data type" "0: No swapping (32-bit data).,1: Half-word swapping (16-bit data).,2: Byte swapping (8-bit data).,3: Bit-level swapping." bitfld.long 0x0 3.--5. "ALGOMODE,ALGOMODE[2:0]: Algorithm mode" "?,?,?,?,4: Electronic codebook (ECB),5: Cipher Block Chaining (CBC),6: Counter mode (CTR),7: AES key preparation for ECB or CBC decryption" newline bitfld.long 0x0 2. "ALGODIR,Algorithm direction" "0: Encryption,1: Decryption" rgroup.long 0x4++0x3 line.long 0x0 "CRYP_SR,CRYP status register" bitfld.long 0x0 7. "KEYVALID,Key valid flag" "0: Key not valid,1: Key valid" bitfld.long 0x0 6. "KERF,Key error flag" "0: No key error detected,1: Key information failed to load into key registers" newline bitfld.long 0x0 4. "BUSY,Busy bit" "0: Idle,1: Busy" bitfld.long 0x0 3. "OFFU,Output FIFO full flag" "0: Output FIFO is not full,1: Output FIFO is full" newline bitfld.long 0x0 2. "OFNE,Output FIFO not empty flag" "0: Output FIFO is empty,1: Output FIFO is not empty" bitfld.long 0x0 1. "IFNF,Input FIFO not full flag" "0: Input FIFO is full,1: Input FIFO is not full" newline bitfld.long 0x0 0. "IFEM,Input FIFO empty flag" "0: Input FIFO is not empty,1: Input FIFO is empty" group.long 0x8++0x3 line.long 0x0 "CRYP_DINR,CRYP data input register" hexmask.long 0x0 0.--31. 1. "DIN,Data input" rgroup.long 0xC++0x3 line.long 0x0 "CRYP_DOUTR,CRYP data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Data output" group.long 0x10++0x7 line.long 0x0 "CRYP_DMACR,CRYP DMA control register" bitfld.long 0x0 1. "DOEN,DMA output enable" "0: Outgoing data transfer from CRYP via DMA is..,1: Outgoing data transfer from CRYP via DMA is.." bitfld.long 0x0 0. "DIEN,DMA input enable" "0: Incoming data transfer to CRYP via DMA is disabled,1: Incoming data transfer to CRYP via DMA is disabled" line.long 0x4 "CRYP_IMSCR,CRYP interrupt mask set/clear register" bitfld.long 0x4 1. "OUTIM,Output FIFO service interrupt mask" "0: Output FIFO interrupt is disabled (masked)..,1: Output FIFO interrupt is enabled (not masked)" bitfld.long 0x4 0. "INIM,Input FIFO service interrupt mask" "0: Input FIFO interrupt is disabled (masked) masked..,1: Input FIFO interrupt is enabled (not masked)" rgroup.long 0x18++0x7 line.long 0x0 "CRYP_RISR,CRYP raw interrupt status register" bitfld.long 0x0 1. "OUTRIS,Output FIFO service raw interrupt status" "0: No output FIFO event detected,1: Output FIFO full or not empty detected; an.." bitfld.long 0x0 0. "INRIS,Input FIFO service raw interrupt status" "0: No input FIFO event detected,1: Input FIFO empty or not full detected; an.." line.long 0x4 "CRYP_MISR,CRYP masked interrupt status register" bitfld.long 0x4 1. "OUTMIS,Output FIFO service masked interrupt status" "0: No output FIFO event detected or OUTIM mask..,1: Output FIFO full or not empty detected with an.." bitfld.long 0x4 0. "INMIS,Input FIFO service masked interrupt status" "0: No input FIFO event detected or INIM mask..,1: Input FIFO empty or not full detected with an.." wgroup.long 0x20++0x1F line.long 0x0 "CRYP_K0LR,CRYP key register 0L" hexmask.long 0x0 0.--31. 1. "K,Key bit x" line.long 0x4 "CRYP_K0RR,CRYP key register 0R" hexmask.long 0x4 0.--31. 1. "K,Key bit x" line.long 0x8 "CRYP_K1LR,CRYP key register 1L" hexmask.long 0x8 0.--31. 1. "K,Key bit x" line.long 0xC "CRYP_K1RR,CRYP key register 1R" hexmask.long 0xC 0.--31. 1. "K,Key bit x" line.long 0x10 "CRYP_K2LR,CRYP key register 2L" hexmask.long 0x10 0.--31. 1. "K,Key bit x" line.long 0x14 "CRYP_K2RR,CRYP key register 2R" hexmask.long 0x14 0.--31. 1. "K,Key bit x" line.long 0x18 "CRYP_K3LR,CRYP key register 3L" hexmask.long 0x18 0.--31. 1. "K,Key bit x" line.long 0x1C "CRYP_K3RR,CRYP key register 3R" hexmask.long 0x1C 0.--31. 1. "K,Key bit x" group.long 0x40++0x4F line.long 0x0 "CRYP_IV0LR,CRYP initialization vector register 0L" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector bit x" line.long 0x4 "CRYP_IV0RR,CRYP initialization vector register 0R" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector bit x" line.long 0x8 "CRYP_IV1LR,CRYP initialization vector register 1L" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector bit x" line.long 0xC "CRYP_IV1RR,CRYP initialization vector register 1R" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector bit x" line.long 0x10 "CRYP_CSGCMCCM0R,CRYP context swap GCM-CCM registers" hexmask.long 0x10 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x14 "CRYP_CSGCMCCM1R,CRYP context swap GCM-CCM registers" hexmask.long 0x14 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x18 "CRYP_CSGCMCCM2R,CRYP context swap GCM-CCM registers" hexmask.long 0x18 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x1C "CRYP_CSGCMCCM3R,CRYP context swap GCM-CCM registers" hexmask.long 0x1C 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x20 "CRYP_CSGCMCCM4R,CRYP context swap GCM-CCM registers" hexmask.long 0x20 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x24 "CRYP_CSGCMCCM5R,CRYP context swap GCM-CCM registers" hexmask.long 0x24 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x28 "CRYP_CSGCMCCM6R,CRYP context swap GCM-CCM registers" hexmask.long 0x28 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x2C "CRYP_CSGCMCCM7R,CRYP context swap GCM-CCM registers" hexmask.long 0x2C 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x30 "CRYP_CSGCM0R,CRYP context swap GCM registers" hexmask.long 0x30 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x34 "CRYP_CSGCM1R,CRYP context swap GCM registers" hexmask.long 0x34 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x38 "CRYP_CSGCM2R,CRYP context swap GCM registers" hexmask.long 0x38 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x3C "CRYP_CSGCM3R,CRYP context swap GCM registers" hexmask.long 0x3C 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x40 "CRYP_CSGCM4R,CRYP context swap GCM registers" hexmask.long 0x40 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x44 "CRYP_CSGCM5R,CRYP context swap GCM registers" hexmask.long 0x44 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x48 "CRYP_CSGCM6R,CRYP context swap GCM registers" hexmask.long 0x48 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x4C "CRYP_CSGCM7R,CRYP context swap GCM registers" hexmask.long 0x4C 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" tree.end tree "CRYP_S" base ad:0x54020800 group.long 0x0++0x3 line.long 0x0 "CRYP_CR,CRYP control register" bitfld.long 0x0 31. "IPRST,CRYP peripheral software reset" "0,1" bitfld.long 0x0 24.--25. "KMOD,Key mode selection" "0: Normal-key mode. Key registers are freely usable.,?,2: Shared-key mode. If shared-key mode is properly..,?" newline hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block" bitfld.long 0x0 19. "ALGOMODE_1,ALGOMODE[3]" "0,1" newline bitfld.long 0x0 16.--17. "GCM_CCMPH,GCM or CCM phase selection" "0: Initialization phase,1: Header phase,2: Payload phase,3: Final phase" bitfld.long 0x0 15. "CRYPEN,CRYP enable" "0: CRYP disabled,1: CRYP enabled" newline bitfld.long 0x0 14. "FFLUSH,FIFO flush" "0: No effect,1: FIFO flush enabled" bitfld.long 0x0 8.--9. "KEYSIZE,Key size selection" "0: 128-bits,1: 192 bits,2: 256 bits,?" newline bitfld.long 0x0 6.--7. "DATATYPE,Data type" "0: No swapping (32-bit data).,1: Half-word swapping (16-bit data).,2: Byte swapping (8-bit data).,3: Bit-level swapping." bitfld.long 0x0 3.--5. "ALGOMODE,ALGOMODE[2:0]: Algorithm mode" "?,?,?,?,4: Electronic codebook (ECB),5: Cipher Block Chaining (CBC),6: Counter mode (CTR),7: AES key preparation for ECB or CBC decryption" newline bitfld.long 0x0 2. "ALGODIR,Algorithm direction" "0: Encryption,1: Decryption" rgroup.long 0x4++0x3 line.long 0x0 "CRYP_SR,CRYP status register" bitfld.long 0x0 7. "KEYVALID,Key valid flag" "0: Key not valid,1: Key valid" bitfld.long 0x0 6. "KERF,Key error flag" "0: No key error detected,1: Key information failed to load into key registers" newline bitfld.long 0x0 4. "BUSY,Busy bit" "0: Idle,1: Busy" bitfld.long 0x0 3. "OFFU,Output FIFO full flag" "0: Output FIFO is not full,1: Output FIFO is full" newline bitfld.long 0x0 2. "OFNE,Output FIFO not empty flag" "0: Output FIFO is empty,1: Output FIFO is not empty" bitfld.long 0x0 1. "IFNF,Input FIFO not full flag" "0: Input FIFO is full,1: Input FIFO is not full" newline bitfld.long 0x0 0. "IFEM,Input FIFO empty flag" "0: Input FIFO is not empty,1: Input FIFO is empty" group.long 0x8++0x3 line.long 0x0 "CRYP_DINR,CRYP data input register" hexmask.long 0x0 0.--31. 1. "DIN,Data input" rgroup.long 0xC++0x3 line.long 0x0 "CRYP_DOUTR,CRYP data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Data output" group.long 0x10++0x7 line.long 0x0 "CRYP_DMACR,CRYP DMA control register" bitfld.long 0x0 1. "DOEN,DMA output enable" "0: Outgoing data transfer from CRYP via DMA is..,1: Outgoing data transfer from CRYP via DMA is.." bitfld.long 0x0 0. "DIEN,DMA input enable" "0: Incoming data transfer to CRYP via DMA is disabled,1: Incoming data transfer to CRYP via DMA is disabled" line.long 0x4 "CRYP_IMSCR,CRYP interrupt mask set/clear register" bitfld.long 0x4 1. "OUTIM,Output FIFO service interrupt mask" "0: Output FIFO interrupt is disabled (masked)..,1: Output FIFO interrupt is enabled (not masked)" bitfld.long 0x4 0. "INIM,Input FIFO service interrupt mask" "0: Input FIFO interrupt is disabled (masked) masked..,1: Input FIFO interrupt is enabled (not masked)" rgroup.long 0x18++0x7 line.long 0x0 "CRYP_RISR,CRYP raw interrupt status register" bitfld.long 0x0 1. "OUTRIS,Output FIFO service raw interrupt status" "0: No output FIFO event detected,1: Output FIFO full or not empty detected; an.." bitfld.long 0x0 0. "INRIS,Input FIFO service raw interrupt status" "0: No input FIFO event detected,1: Input FIFO empty or not full detected; an.." line.long 0x4 "CRYP_MISR,CRYP masked interrupt status register" bitfld.long 0x4 1. "OUTMIS,Output FIFO service masked interrupt status" "0: No output FIFO event detected or OUTIM mask..,1: Output FIFO full or not empty detected with an.." bitfld.long 0x4 0. "INMIS,Input FIFO service masked interrupt status" "0: No input FIFO event detected or INIM mask..,1: Input FIFO empty or not full detected with an.." wgroup.long 0x20++0x1F line.long 0x0 "CRYP_K0LR,CRYP key register 0L" hexmask.long 0x0 0.--31. 1. "K,Key bit x" line.long 0x4 "CRYP_K0RR,CRYP key register 0R" hexmask.long 0x4 0.--31. 1. "K,Key bit x" line.long 0x8 "CRYP_K1LR,CRYP key register 1L" hexmask.long 0x8 0.--31. 1. "K,Key bit x" line.long 0xC "CRYP_K1RR,CRYP key register 1R" hexmask.long 0xC 0.--31. 1. "K,Key bit x" line.long 0x10 "CRYP_K2LR,CRYP key register 2L" hexmask.long 0x10 0.--31. 1. "K,Key bit x" line.long 0x14 "CRYP_K2RR,CRYP key register 2R" hexmask.long 0x14 0.--31. 1. "K,Key bit x" line.long 0x18 "CRYP_K3LR,CRYP key register 3L" hexmask.long 0x18 0.--31. 1. "K,Key bit x" line.long 0x1C "CRYP_K3RR,CRYP key register 3R" hexmask.long 0x1C 0.--31. 1. "K,Key bit x" group.long 0x40++0x4F line.long 0x0 "CRYP_IV0LR,CRYP initialization vector register 0L" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector bit x" line.long 0x4 "CRYP_IV0RR,CRYP initialization vector register 0R" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector bit x" line.long 0x8 "CRYP_IV1LR,CRYP initialization vector register 1L" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector bit x" line.long 0xC "CRYP_IV1RR,CRYP initialization vector register 1R" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector bit x" line.long 0x10 "CRYP_CSGCMCCM0R,CRYP context swap GCM-CCM registers" hexmask.long 0x10 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x14 "CRYP_CSGCMCCM1R,CRYP context swap GCM-CCM registers" hexmask.long 0x14 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x18 "CRYP_CSGCMCCM2R,CRYP context swap GCM-CCM registers" hexmask.long 0x18 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x1C "CRYP_CSGCMCCM3R,CRYP context swap GCM-CCM registers" hexmask.long 0x1C 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x20 "CRYP_CSGCMCCM4R,CRYP context swap GCM-CCM registers" hexmask.long 0x20 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x24 "CRYP_CSGCMCCM5R,CRYP context swap GCM-CCM registers" hexmask.long 0x24 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x28 "CRYP_CSGCMCCM6R,CRYP context swap GCM-CCM registers" hexmask.long 0x28 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x2C "CRYP_CSGCMCCM7R,CRYP context swap GCM-CCM registers" hexmask.long 0x2C 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes" line.long 0x30 "CRYP_CSGCM0R,CRYP context swap GCM registers" hexmask.long 0x30 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x34 "CRYP_CSGCM1R,CRYP context swap GCM registers" hexmask.long 0x34 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x38 "CRYP_CSGCM2R,CRYP context swap GCM registers" hexmask.long 0x38 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x3C "CRYP_CSGCM3R,CRYP context swap GCM registers" hexmask.long 0x3C 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x40 "CRYP_CSGCM4R,CRYP context swap GCM registers" hexmask.long 0x40 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x44 "CRYP_CSGCM5R,CRYP context swap GCM registers" hexmask.long 0x44 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x48 "CRYP_CSGCM6R,CRYP context swap GCM registers" hexmask.long 0x48 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" line.long 0x4C "CRYP_CSGCM7R,CRYP context swap GCM registers" hexmask.long 0x4C 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes" tree.end tree.end endif tree "CSI (CSI-2 Host)" base ad:0x0 tree "CSI" base ad:0x48006000 group.long 0x0++0x7 line.long 0x0 "CSI_CR,CSI-2 Host control register" bitfld.long 0x0 15. "VC3STOP,Virtual channel 3 stop" "0: No effect,1: Pulse generation to stop the virtual channel 3.." bitfld.long 0x0 14. "VC3START,Virtual channel 3 start" "0: No effect,1: Pulse generation to start the virtual channel 3.." newline bitfld.long 0x0 11. "VC2STOP,Virtual channel 2 stop" "0: No effect,1: Pulse generation to stop the virtual channel 2.." bitfld.long 0x0 10. "VC2START,Virtual channel 2 start" "0: No effect,1: Pulse generation to start the virtual channel 2.." newline bitfld.long 0x0 7. "VC1STOP,Virtual channel 1 stop" "0: No effect,1: Pulse generation to stop the virtual channel 1.." bitfld.long 0x0 6. "VC1START,Virtual channel 1 start" "0: No effect,1: Pulse generation to start the virtual channel 1.." newline bitfld.long 0x0 3. "VC0STOP,Virtual channel 0 stop" "0: No effect,1: Pulse generation to stop the virtual channel 0.." bitfld.long 0x0 2. "VC0START,Virtual channel 0 start" "0: No effect,1: Pulse generation to start the virtual channel 0.." newline bitfld.long 0x0 0. "CSIEN,CSI-2 enable" "0: CSI-2 disabled,1: CSI-2 enabled" line.long 0x4 "CSI_PCR,CSI-2 Host DPHY_RX control register" bitfld.long 0x4 3. "DL1EN,D-PHY_RX data lane 1 enable" "0: Data lane 1 module is in shutdown mode.,1: Enable the data lane 1 module." bitfld.long 0x4 2. "DL0EN,D-PHY_RX data lane 0 enable" "0: Data lane 0 module is in shutdown mode.,1: Enable the data lane 0 module." newline bitfld.long 0x4 1. "CLEN,Clock lane enable" "0: Clock lanes disabled,1: Clock lanes enabled" bitfld.long 0x4 0. "PWRDOWN,Power down" "0: Active state,1: Power down the D-PHY_RX" group.long 0x10++0x6B line.long 0x0 "CSI_VC0CFGR1,CSI-2 Host virtual channel 0 configuration register 1" hexmask.long.byte 0x0 24.--28. 1. "DT0FT,Data type 0 format" hexmask.long.byte 0x0 16.--21. 1. "DT0,Data type 0 class selection for virtual channel x" newline hexmask.long.byte 0x0 8.--12. 1. "CDTFT,Common format for all data types" bitfld.long 0x0 7. "DT6EN,Data type 6 enable" "0: Data type 6 for virtual channel x is disabled.,1: Data type 6 for virtual channel x is enabled." newline bitfld.long 0x0 6. "DT5EN,Data type 5 enable" "0: Data type 5 for virtual channel x is disabled.,1: Data type 5 for virtual channel x is enabled." bitfld.long 0x0 5. "DT4EN,Data type 4 enable" "0: Data type 4 for virtual channel x is disabled.,1: Data type 4 for virtual channel x is enabled." newline bitfld.long 0x0 4. "DT3EN,Data type 3 enable" "0: Data type 3 for virtual channel x is disabled.,1: Data type 3 for virtual channel x is enabled." bitfld.long 0x0 3. "DT2EN,Data type 2 enable" "0: Data type 2 for virtual channel x is disabled.,1: Data type 2 for virtual channel x is enabled." newline bitfld.long 0x0 2. "DT1EN,Data type 1 enable" "0: Data type 1 for virtual channel x is disabled.,1: Data type 1 for virtual channel x is enabled." bitfld.long 0x0 1. "DT0EN,Data type 0 enable" "0: Data type 0 for virtual channel x is disabled.,1: Data type 0 for virtual channel x is enabled." newline bitfld.long 0x0 0. "ALLDT,All data types enable for the virtual channel x" "0: Data type capture managed individually,1: All data types captured for virtual channel x" line.long 0x4 "CSI_VC0CFGR2,CSI-2 Host virtual channel 0 configuration register 2" hexmask.long.byte 0x4 24.--28. 1. "DT2FT,Data type 2 format" hexmask.long.byte 0x4 16.--21. 1. "DT2,Data type 2 class selection for virtual channel x" newline hexmask.long.byte 0x4 8.--12. 1. "DT1FT,Data type 1 format" hexmask.long.byte 0x4 0.--5. 1. "DT1,Data type 1 class selection for virtual channel x" line.long 0x8 "CSI_VC0CFGR3,CSI-2 Host virtual channel 0 configuration register 3" hexmask.long.byte 0x8 24.--28. 1. "DT4FT,Data type 4 format" hexmask.long.byte 0x8 16.--21. 1. "DT4,Data type 4 class selection for virtual channel x" newline hexmask.long.byte 0x8 8.--12. 1. "DT3FT,Data type 3 format" hexmask.long.byte 0x8 0.--5. 1. "DT3,Data type 3 class selection for virtual channel x" line.long 0xC "CSI_VC0CFGR4,CSI-2 Host virtual channel 0 configuration register 4" hexmask.long.byte 0xC 24.--28. 1. "DT6FT,Data type 6 format" hexmask.long.byte 0xC 16.--21. 1. "DT6,Data type 6 class selection for virtual channel x" newline hexmask.long.byte 0xC 8.--12. 1. "DT5FT,Data type 5 format" hexmask.long.byte 0xC 0.--5. 1. "DT5,Data type 5 class selection for virtual channel x" line.long 0x10 "CSI_VC1CFGR1,CSI-2 Host virtual channel 1 configuration register 1" hexmask.long.byte 0x10 24.--28. 1. "DT0FT,Data type 0 format" hexmask.long.byte 0x10 16.--21. 1. "DT0,Data type 0 class selection for virtual channel x" newline hexmask.long.byte 0x10 8.--12. 1. "CDTFT,Common format for all data types" bitfld.long 0x10 7. "DT6EN,Data type 6 enable" "0: Data type 6 for virtual channel x is disabled.,1: Data type 6 for virtual channel x is enabled." newline bitfld.long 0x10 6. "DT5EN,Data type 5 enable" "0: Data type 5 for virtual channel x is disabled.,1: Data type 5 for virtual channel x is enabled." bitfld.long 0x10 5. "DT4EN,Data type 4 enable" "0: Data type 4 for virtual channel x is disabled.,1: Data type 4 for virtual channel x is enabled." newline bitfld.long 0x10 4. "DT3EN,Data type 3 enable" "0: Data type 3 for virtual channel x is disabled.,1: Data type 3 for virtual channel x is enabled." bitfld.long 0x10 3. "DT2EN,Data type 2 enable" "0: Data type 2 for virtual channel x is disabled.,1: Data type 2 for virtual channel x is enabled." newline bitfld.long 0x10 2. "DT1EN,Data type 1 enable" "0: Data type 1 for virtual channel x is disabled.,1: Data type 1 for virtual channel x is enabled." bitfld.long 0x10 1. "DT0EN,Data type 0 enable" "0: Data type 0 for virtual channel x is disabled.,1: Data type 0 for virtual channel x is enabled." newline bitfld.long 0x10 0. "ALLDT,All data types enable for the virtual channel x" "0: Data type capture managed individually,1: All data types captured for virtual channel x" line.long 0x14 "CSI_VC1CFGR2,CSI-2 Host virtual channel 1 configuration register 2" hexmask.long.byte 0x14 24.--28. 1. "DT2FT,Data type 2 format" hexmask.long.byte 0x14 16.--21. 1. "DT2,Data type 2 class selection for virtual channel x" newline hexmask.long.byte 0x14 8.--12. 1. "DT1FT,Data type 1 format" hexmask.long.byte 0x14 0.--5. 1. "DT1,Data type 1 class selection for virtual channel x" line.long 0x18 "CSI_VC1CFGR3,CSI-2 Host virtual channel 1 configuration register 3" hexmask.long.byte 0x18 24.--28. 1. "DT4FT,Data type 4 format" hexmask.long.byte 0x18 16.--21. 1. "DT4,Data type 4 class selection for virtual channel x" newline hexmask.long.byte 0x18 8.--12. 1. "DT3FT,Data type 3 format" hexmask.long.byte 0x18 0.--5. 1. "DT3,Data type 3 class selection for virtual channel x" line.long 0x1C "CSI_VC1CFGR4,CSI-2 Host virtual channel 1 configuration register 4" hexmask.long.byte 0x1C 24.--28. 1. "DT6FT,Data type 6 format" hexmask.long.byte 0x1C 16.--21. 1. "DT6,Data type 6 class selection for virtual channel x" newline hexmask.long.byte 0x1C 8.--12. 1. "DT5FT,Data type 5 format" hexmask.long.byte 0x1C 0.--5. 1. "DT5,Data type 5 class selection for virtual channel x" line.long 0x20 "CSI_VC2CFGR1,CSI-2 Host virtual channel 2 configuration register 1" hexmask.long.byte 0x20 24.--28. 1. "DT0FT,Data type 0 format" hexmask.long.byte 0x20 16.--21. 1. "DT0,Data type 0 class selection for virtual channel x" newline hexmask.long.byte 0x20 8.--12. 1. "CDTFT,Common format for all data types" bitfld.long 0x20 7. "DT6EN,Data type 6 enable" "0: Data type 6 for virtual channel x is disabled.,1: Data type 6 for virtual channel x is enabled." newline bitfld.long 0x20 6. "DT5EN,Data type 5 enable" "0: Data type 5 for virtual channel x is disabled.,1: Data type 5 for virtual channel x is enabled." bitfld.long 0x20 5. "DT4EN,Data type 4 enable" "0: Data type 4 for virtual channel x is disabled.,1: Data type 4 for virtual channel x is enabled." newline bitfld.long 0x20 4. "DT3EN,Data type 3 enable" "0: Data type 3 for virtual channel x is disabled.,1: Data type 3 for virtual channel x is enabled." bitfld.long 0x20 3. "DT2EN,Data type 2 enable" "0: Data type 2 for virtual channel x is disabled.,1: Data type 2 for virtual channel x is enabled." newline bitfld.long 0x20 2. "DT1EN,Data type 1 enable" "0: Data type 1 for virtual channel x is disabled.,1: Data type 1 for virtual channel x is enabled." bitfld.long 0x20 1. "DT0EN,Data type 0 enable" "0: Data type 0 for virtual channel x is disabled.,1: Data type 0 for virtual channel x is enabled." newline bitfld.long 0x20 0. "ALLDT,All data types enable for the virtual channel x" "0: Data type capture managed individually,1: All data types captured for virtual channel x" line.long 0x24 "CSI_VC2CFGR2,CSI-2 Host virtual channel 2 configuration register 2" hexmask.long.byte 0x24 24.--28. 1. "DT2FT,Data type 2 format" hexmask.long.byte 0x24 16.--21. 1. "DT2,Data type 2 class selection for virtual channel x" newline hexmask.long.byte 0x24 8.--12. 1. "DT1FT,Data type 1 format" hexmask.long.byte 0x24 0.--5. 1. "DT1,Data type 1 class selection for virtual channel x" line.long 0x28 "CSI_VC2CFGR3,CSI-2 Host virtual channel 2 configuration register 3" hexmask.long.byte 0x28 24.--28. 1. "DT4FT,Data type 4 format" hexmask.long.byte 0x28 16.--21. 1. "DT4,Data type 4 class selection for virtual channel x" newline hexmask.long.byte 0x28 8.--12. 1. "DT3FT,Data type 3 format" hexmask.long.byte 0x28 0.--5. 1. "DT3,Data type 3 class selection for virtual channel x" line.long 0x2C "CSI_VC2CFGR4,CSI-2 Host virtual channel 2 configuration register 4" hexmask.long.byte 0x2C 24.--28. 1. "DT6FT,Data type 6 format" hexmask.long.byte 0x2C 16.--21. 1. "DT6,Data type 6 class selection for virtual channel x" newline hexmask.long.byte 0x2C 8.--12. 1. "DT5FT,Data type 5 format" hexmask.long.byte 0x2C 0.--5. 1. "DT5,Data type 5 class selection for virtual channel x" line.long 0x30 "CSI_VC3CFGR1,CSI-2 Host virtual channel 3 configuration register 1" hexmask.long.byte 0x30 24.--28. 1. "DT0FT,Data type 0 format" hexmask.long.byte 0x30 16.--21. 1. "DT0,Data type 0 class selection for virtual channel x" newline hexmask.long.byte 0x30 8.--12. 1. "CDTFT,Common format for all data types" bitfld.long 0x30 7. "DT6EN,Data type 6 enable" "0: Data type 6 for virtual channel x is disabled.,1: Data type 6 for virtual channel x is enabled." newline bitfld.long 0x30 6. "DT5EN,Data type 5 enable" "0: Data type 5 for virtual channel x is disabled.,1: Data type 5 for virtual channel x is enabled." bitfld.long 0x30 5. "DT4EN,Data type 4 enable" "0: Data type 4 for virtual channel x is disabled.,1: Data type 4 for virtual channel x is enabled." newline bitfld.long 0x30 4. "DT3EN,Data type 3 enable" "0: Data type 3 for virtual channel x is disabled.,1: Data type 3 for virtual channel x is enabled." bitfld.long 0x30 3. "DT2EN,Data type 2 enable" "0: Data type 2 for virtual channel x is disabled.,1: Data type 2 for virtual channel x is enabled." newline bitfld.long 0x30 2. "DT1EN,Data type 1 enable" "0: Data type 1 for virtual channel x is disabled.,1: Data type 1 for virtual channel x is enabled." bitfld.long 0x30 1. "DT0EN,Data type 0 enable" "0: Data type 0 for virtual channel x is disabled.,1: Data type 0 for virtual channel x is enabled." newline bitfld.long 0x30 0. "ALLDT,All data types enable for the virtual channel x" "0: Data type capture managed individually,1: All data types captured for virtual channel x" line.long 0x34 "CSI_VC3CFGR2,CSI-2 Host virtual channel 3 configuration register 2" hexmask.long.byte 0x34 24.--28. 1. "DT2FT,Data type 2 format" hexmask.long.byte 0x34 16.--21. 1. "DT2,Data type 2 class selection for virtual channel x" newline hexmask.long.byte 0x34 8.--12. 1. "DT1FT,Data type 1 format" hexmask.long.byte 0x34 0.--5. 1. "DT1,Data type 1 class selection for virtual channel x" line.long 0x38 "CSI_VC3CFGR3,CSI-2 Host virtual channel 3 configuration register 3" hexmask.long.byte 0x38 24.--28. 1. "DT4FT,Data type 4 format" hexmask.long.byte 0x38 16.--21. 1. "DT4,Data type 4 class selection for virtual channel x" newline hexmask.long.byte 0x38 8.--12. 1. "DT3FT,Data type 3 format" hexmask.long.byte 0x38 0.--5. 1. "DT3,Data type 3 class selection for virtual channel x" line.long 0x3C "CSI_VC3CFGR4,CSI-2 Host virtual channel 3 configuration register 4" hexmask.long.byte 0x3C 24.--28. 1. "DT6FT,Data type 6 format" hexmask.long.byte 0x3C 16.--21. 1. "DT6,Data type 6 class selection for virtual channel x" newline hexmask.long.byte 0x3C 8.--12. 1. "DT5FT,Data type 5 format" hexmask.long.byte 0x3C 0.--5. 1. "DT5,Data type 5 class selection for virtual channel x" line.long 0x40 "CSI_LB0CFGR,CSI-2 Host line byte 0 configuration register" hexmask.long.word 0x40 16.--31. 1. "LINECNT,Line counter" hexmask.long.word 0x40 0.--15. 1. "BYTECNT,Byte counter" line.long 0x44 "CSI_LB1CFGR,CSI-2 Host line byte 1 configuration register" hexmask.long.word 0x44 16.--31. 1. "LINECNT,Line counter" hexmask.long.word 0x44 0.--15. 1. "BYTECNT,Byte counter" line.long 0x48 "CSI_LB2CFGR,CSI-2 Host line byte 2 configuration register" hexmask.long.word 0x48 16.--31. 1. "LINECNT,Line counter" hexmask.long.word 0x48 0.--15. 1. "BYTECNT,Byte counter" line.long 0x4C "CSI_LB3CFGR,CSI-2 Host line byte 3 configuration register" hexmask.long.word 0x4C 16.--31. 1. "LINECNT,Line counter" hexmask.long.word 0x4C 0.--15. 1. "BYTECNT,Byte counter" line.long 0x50 "CSI_TIM0CFGR,CSI-2 Host timer 0 configuration register" hexmask.long 0x50 0.--24. 1. "COUNT,Clock cycle counter" line.long 0x54 "CSI_TIM1CFGR,CSI-2 Host timer 1 configuration register" hexmask.long 0x54 0.--24. 1. "COUNT,Clock cycle counter" line.long 0x58 "CSI_TIM2CFGR,CSI-2 Host timer 2 configuration register" hexmask.long 0x58 0.--24. 1. "COUNT,Clock cycle counter" line.long 0x5C "CSI_TIM3CFGR,CSI-2 Host timer 3 configuration register" hexmask.long 0x5C 0.--24. 1. "COUNT,Clock cycle counter" line.long 0x60 "CSI_LMCFGR,CSI-2 Host lane merger configuration register" bitfld.long 0x60 20.--22. "DL1MAP,Physical mapping of logical data lane 1" "?,1: Physical data lane 1 connected to logical data..,2: Physical data lane 1 connected to logical data..,?,?,?,?,?" bitfld.long 0x60 16.--18. "DL0MAP,Physical mapping of logical data lane 0" "?,1: Physical data lane 0 connected to logical data..,2: Physical data lane 0 connected to logical data..,?,?,?,?,?" newline bitfld.long 0x60 8.--10. "LANENB,Number of lanes" "?,1: 1 lane for the reception,2: 2 lanes for the reception,?,?,?,?,?" line.long 0x64 "CSI_PRGITR,CSI-2 Host program interrupt register" bitfld.long 0x64 31. "TIM3EN,TIM3 base time enable" "0: Timer 3 clock cycle counter not active,1: Timer 3 clock cycle counter active" bitfld.long 0x64 30. "TIM3EOF,TIM3 base time starting from the EOF" "0: SOF selected as starting point for the counter,1: EOF selected as starting point for the counter" newline bitfld.long 0x64 28.--29. "TIM3VC,TIM3 base time linked to a virtual channel" "0: Virtual channel 0 used to generate the TIM3 event,1: Virtual channel 1 used to generate the TIM3 event,2: Virtual channel 2 used to generate the TIM3 event,3: Virtual channel 3 used to generate the TIM3 event" bitfld.long 0x64 27. "TIM2EN,TIM2 base time enable" "0: Timer 2 clock cycle counter not active.,1: Timer 2 clock cycle counter active" newline bitfld.long 0x64 26. "TIM2EOF,TIM2 base time starting from the EOF" "0: SOF selected as starting point for the counter,1: EOF selected as starting point for the counter" bitfld.long 0x64 24.--25. "TIM2VC,TIM2 base time linked to a virtual channel" "0: Virtual channel 0 used to generate the TIM2 event,1: Virtual channel 1 used to generate the TIM2 event,2: Virtual channel 2 used to generate the TIM2 event,3: Virtual channel 3 used to generate the TIM2 event" newline bitfld.long 0x64 23. "TIM1EN,TIM1 base time enable" "0: Timer 1 clock cycle counter not active.,1: Timer 1 clock cycle counter active" bitfld.long 0x64 22. "TIM1EOF,TIM1 base time starting from the EOF" "0: SOF selected as starting point for the counter,1: EOF selected as starting point for the counter" newline bitfld.long 0x64 20.--21. "TIM1VC,TIM1 base time linked to a virtual channel" "0: Virtual channel 0 used to generate the TIM1 event,1: Virtual channel 1 used to generate the TIM1 event,2: Virtual channel 2 used to generate the TIM1 event,3: Virtual channel 3 used to generate the TIM1 event" bitfld.long 0x64 19. "TIM0EN,TIM0 base time enable" "0: Timer 0 clock cycle counter not active,1: Timer 0 clock cycle counter active" newline bitfld.long 0x64 18. "TIM0EOF,TIM0 base time starting from the EOF" "0: SOF selected e as starting point for the counter,1: EOF selected as starting point for the counter" bitfld.long 0x64 16.--17. "TIM0VC,TIM0 base time linked to a virtual channel" "0: Virtual channel 0 used to generate the TIM0 event,1: Virtual channel 1 used to generate the TIM0 event,2: Virtual channel 2 used to generate the TIM0 event,3: Virtual channel 3 used to generate the TIM0 event" newline bitfld.long 0x64 15. "LB3EN,Line/byte 3 counter enable" "0: Line/byte 3 counter stopped,1: Line/byte 3 counter active" bitfld.long 0x64 12.--13. "LB3VC,Line/byte counter 3 linked to a virtual channel" "0: Virtual channel 0 used to generate the line/byte..,1: Virtual channel 1 used to generate the line/byte..,2: Virtual channel 2 used to generate the line/byte..,3: Virtual channel 3 used to generate the line/byte.." newline bitfld.long 0x64 11. "LB2EN,Line/byte 2 counter enable" "0: Line/byte 2 counter stopped,1: Line/byte 2 counter active" bitfld.long 0x64 8.--9. "LB2VC,Line/byte counter 2 linked to a virtual channel" "0: Virtual channel 0 used to generate the line/byte..,1: Virtual channel 1 used to generate the line/byte..,2: Virtual channel 2 used to generate the line/byte..,3: Virtual channel 3 used to generate the line/byte.." newline bitfld.long 0x64 7. "LB1EN,Line/byte 1 counter enable" "0: Line/byte 1 counter stopped,1: Line/byte 1 counter active" bitfld.long 0x64 4.--5. "LB1VC,Line/byte counter 1 linked to a virtual channel" "0: Virtual channel 0 used to generate the line/byte..,1: Virtual channel 1 used to generate the line/byte..,2: Virtual channel 2 used to generate the line/byte..,3: Virtual channel 3 used to generate the line/byte.." newline bitfld.long 0x64 3. "LB0EN,Line/byte 0 counter enable" "0: Line/byte 0 counter stopped,1: Line/byte 0 counter active" bitfld.long 0x64 0.--1. "LB0VC,Line/byte counter 0 linked to a virtual channel" "0: Virtual channel 0 used to generate the line/byte..,1: Virtual channel 1 used to generate the line/byte..,2: Virtual channel 2 used to generate the line/byte..,3: Virtual channel 3 used to generate the line/byte.." line.long 0x68 "CSI_WDR,CSI-2 Host watchdog register" hexmask.long 0x68 0.--31. 1. "CNT,Watchdog counter" group.long 0x80++0x7 line.long 0x0 "CSI_IER0,CSI-2 Host interrupt enable register 0" bitfld.long 0x0 30. "SYNCERRIE,Invalid synchronization error interrupt enable" "0: Interrupt on invalid synchronization error..,1: Interrupt on invalid synchronization error enabled" bitfld.long 0x0 29. "WDERRIE,Watchdog error interrupt enable" "0: Interrupt on watchdog error disabled,1: Interrupt on watchdog error enabled" newline bitfld.long 0x0 28. "SPKTERRIE,Short packet error interrupt enable" "0: Interrupt on short packet error disabled,1: Interrupt on short packet error enabled" bitfld.long 0x0 27. "IDERRIE,Data type ID error interrupt enable" "0: Interrupt on reception of reserved data type..,1: Interrupt on reception of reserved data type.." newline bitfld.long 0x0 26. "CECCERRIE,Corrected ECC error interrupt enable" "0: Interrupt on corrected ECC error detection..,1: Interrupt on corrected ECC error detection enabled" bitfld.long 0x0 25. "ECCERRIE,ECC error interrupt enable" "0: Interrupt on ECC error detection disabled,1: Interrupt on ECC error detection enabled" newline bitfld.long 0x0 24. "CRCERRIE,CRC error interrupt enable" "0: Interrupt on CRC error detection disabled,1: Interrupt on CRC error detection enabled" bitfld.long 0x0 21. "CCFIFOFIE,Clock changer FIFO full interrupt enable" "0: Interrupt on clock changer FIFO full detection..,1: Interrupt on clock changer FIFO full detection.." newline bitfld.long 0x0 16. "SPKTIE,Short packet interrupt enable" "0: Short packet detection interrupt disabled,1: Short packet detection interrupt enabled" bitfld.long 0x0 15. "EOF3IE,EOF for virtual channel 3 interrupt enable" "0: EOF on virtual channel 3 interrupt disabled,1: EOF on virtual channel 3 interrupt enabled" newline bitfld.long 0x0 14. "EOF2IE,EOF for virtual channel 2 interrupt enable" "0: EOF on virtual channel 2 interrupt disabled,1: EOF on virtual channel 2 interrupt enabled" bitfld.long 0x0 13. "EOF1IE,EOF for virtual channel 1 interrupt enable" "0: EOF on virtual channel 1 interrupt disabled,1: EOF on virtual channel 1 interrupt enabled" newline bitfld.long 0x0 12. "EOF0IE,EOF for virtual channel 0 interrupt enable" "0: EOF on virtual channel 0 interrupt disabled,1: EOF on virtual channel 0 interrupt enabled" bitfld.long 0x0 11. "SOF3IE,SOF for virtual channel 3 interrupt enable" "0: SOF on virtual channel 3 interrupt disabled,1: SOF on virtual channel 3 interrupt enabled" newline bitfld.long 0x0 10. "SOF2IE,SOF for virtual channel 2 interrupt enable" "0: SOF on virtual channel 2 interrupt disabled,1: SOF on virtual channel 2 interrupt enabled" bitfld.long 0x0 9. "SOF1IE,SOF for virtual channel 1 interrupt enable" "0: SOF on virtual channel 1 interrupt disabled.,1: SOF on virtual channel 1 interrupt enabled." newline bitfld.long 0x0 8. "SOF0IE,SOF for virtual channel 0 interrupt enable" "0: SOF on virtual channel 0 interrupt disabled,1: SOF on virtual channel 0 interrupt enabled" bitfld.long 0x0 7. "TIM3IE,Timer 3 interrupt enable" "0: Timer 3 interrupt disabled,1: Timer 3 interrupt enabled" newline bitfld.long 0x0 6. "TIM2IE,Timer 2 interrupt enable" "0: Timer 2 interrupt disabled,1: Timer 2 interrupt enabled" bitfld.long 0x0 5. "TIM1IE,Timer 1 interrupt enable" "0: Timer 1 interrupt disabled,1: Timer 1 interrupt enabled" newline bitfld.long 0x0 4. "TIM0IE,Timer 0 interrupt enable" "0: Timer 0 interrupt disabled,1: Timer 0 interrupt enabled" bitfld.long 0x0 3. "LB3IE,Line/byte counter 3 interrupt enable" "0,1" newline bitfld.long 0x0 2. "LB2IE,Line/byte counter 2 interrupt enable" "0,1" bitfld.long 0x0 1. "LB1IE,Line/byte counter 1 interrupt enable" "0,1" newline bitfld.long 0x0 0. "LB0IE,Line/byte counter 0 interrupt enable" "0,1" line.long 0x4 "CSI_IER1,CSI-2 Host interrupt enable register 1" bitfld.long 0x4 12. "ECTRLDL1IE,D-PHY_RX lane 1 control error interrupt enable" "0: Lane 1 control error interrupt disabled,1: Lane 1 control error interrupt enabled" bitfld.long 0x4 11. "ESYNCESCDL1IE,D-PHY_RX lane 1 low-power data transmission synchronization error interrupt enable" "0: Lane 1 low-power data transmission interrupt..,1: Lane 1 low-power data transmission Interrupt.." newline bitfld.long 0x4 10. "EESCDL1IE,D-PHY_RX lane 1 escape entry error interrupt enable" "0: Lane 1 unrecognized escape entry command..,1: Lane 1 unrecognized escape entry command.." bitfld.long 0x4 9. "ESOTSYNCDL1IE,SOT synchronization interrupt error enable on lane 1" "0: Lane 1 SOT synchronization interrupt error..,1: Lane 1 SOT synchronization interrupt error enabled" newline bitfld.long 0x4 8. "ESOTDL1IE,SOT error interrupt enable on lane 1" "0: Lane 1 SOT interrupt error disabled,1: Lane 1 SOT interrupt error enabled" bitfld.long 0x4 4. "ECTRLDL0IE,D-PHY_RX lane 0 control error interrupt enable" "0: Lane 0 control error interrupt disabled,1: Lane 0 control error interrupt enabled" newline bitfld.long 0x4 3. "ESYNCESCDL0IE,D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable" "0: Lane 0 low-power data transmission interrupt..,1: Lane 0 low-power data transmission Interrupt.." bitfld.long 0x4 2. "EESCDL0IE,D-PHY_RX lane 0 escape entry error interrupt enable" "0: Lane 0 unrecognized escape entry command..,1: Lane 0 unrecognized escape entry command.." newline bitfld.long 0x4 1. "ESOTSYNCDL0IE,SOT synchronization interrupt error enable on lane 0" "0: Lane 0 SOT synchronization interrupt error..,1: Lane 0 SOT synchronization interrupt error enabled" bitfld.long 0x4 0. "ESOTDL0IE,SOT error interrupt enable on lane 0" "0: Lane 0 SOT interrupt error disabled,1: Lane 0 SOT interrupt error enabled" rgroup.long 0x90++0x7 line.long 0x0 "CSI_SR0,CSI-2 Host status register 0" bitfld.long 0x0 30. "SYNCERRF,Invalid synchronization error flag" "0,1" bitfld.long 0x0 29. "WDERRF,Watchdog error flag" "0,1" newline bitfld.long 0x0 28. "SPKTERRF,Short packet error flag" "0,1" bitfld.long 0x0 27. "IDERRF,Data type ID error flag" "0,1" newline bitfld.long 0x0 26. "CECCERRF,Corrected ECC error flag" "0,1" bitfld.long 0x0 25. "ECCERRF,ECC error flag" "0,1" newline bitfld.long 0x0 24. "CRCERRF,CRC error flag" "0,1" bitfld.long 0x0 21. "CCFIFOFF,Clock changer FIFO full flag" "0,1" newline bitfld.long 0x0 20. "VC3STATEF,Virtual channel 3 state flag" "0: Virtual channel inactive,1: Virtual channel active" bitfld.long 0x0 19. "VC2STATEF,Virtual channel 2 state flag" "0: Virtual channel inactive,1: Virtual channel active" newline bitfld.long 0x0 18. "VC1STATEF,Virtual channel 1 state flag" "0: Virtual channel inactive,1: Virtual channel active" bitfld.long 0x0 17. "VC0STATEF,Virtual channel 0 state flag" "0: Virtual channel inactive,1: Virtual channel active" newline bitfld.long 0x0 16. "SPKTF,Short packet flag" "0,1" bitfld.long 0x0 15. "EOF3F,EOF flag for virtual channel 3" "0,1" newline bitfld.long 0x0 14. "EOF2F,EOF flag for virtual channel 2" "0,1" bitfld.long 0x0 13. "EOF1F,EOF flag for virtual channel 1" "0,1" newline bitfld.long 0x0 12. "EOF0F,EOF flag for virtual channel 0" "0,1" bitfld.long 0x0 11. "SOF3F,SOF flag for virtual channel 3" "0,1" newline bitfld.long 0x0 10. "SOF2F,SOF flag for virtual channel 2" "0,1" bitfld.long 0x0 9. "SOF1F,SOF flag for virtual channel 1" "0,1" newline bitfld.long 0x0 8. "SOF0F,SOF flag for virtual channel 0" "0,1" bitfld.long 0x0 7. "TIM3F,Timer 3 flag" "0,1" newline bitfld.long 0x0 6. "TIM2F,Timer 2 flag" "0,1" bitfld.long 0x0 5. "TIM1F,Timer 1 flag" "0,1" newline bitfld.long 0x0 4. "TIM0F,Timer 0 flag" "0,1" bitfld.long 0x0 3. "LB3F,Line/byte counter 3 flag" "0,1" newline bitfld.long 0x0 2. "LB2F,Line/byte counter 2 flag" "0,1" bitfld.long 0x0 1. "LB1F,Line/byte counter 1 flag" "0,1" newline bitfld.long 0x0 0. "LB0F,Line/byte counter 0 flag" "0,1" line.long 0x4 "CSI_SR1,CSI-2 Host status register 1" bitfld.long 0x4 31. "ACTCLF,D-PHY_RX receiver clock active flag" "0,1" bitfld.long 0x4 30. "ULPNCLF,D-PHY_RX receiver Ultra-Low power state (not) on clock lane." "0,1" newline bitfld.long 0x4 29. "ULPNACTF,D-PHY_RX receiver ULP state (not) active" "0,1" bitfld.long 0x4 28. "STOPCLF,D-PHY_RX receiver in stop state for the clock lane" "0,1" newline bitfld.long 0x4 26. "ULPNDL1F,D-PHY_RX receiver ultra-low-power state (not) active on data lane 1" "0,1" bitfld.long 0x4 25. "STOPDL1F,D-PHY_RX receiver data lane 1 in stop state" "0,1" newline bitfld.long 0x4 24. "SKCALDL1F,D-PHY_RX lane 1 high-speed skew calibration" "0,1" bitfld.long 0x4 23. "SYNCDL1F,D-PHY_RX lane 1 receiver synchronization observed" "0,1" newline bitfld.long 0x4 22. "ACTDL1F,D-PHY_RX lane 1 high-speed reception active" "0,1" bitfld.long 0x4 20. "ULPNDL0F,D-PHY_RX receiver ultra-low-power state (not) active on data lane 0" "0,1" newline bitfld.long 0x4 19. "STOPDL0F,D-PHY_RX receiver data lane 0 in stop state" "0,1" bitfld.long 0x4 18. "SKCALDL0F,D-PHY_RX lane 0 high-speed skew calibration" "0,1" newline bitfld.long 0x4 17. "SYNCDL0F,D-PHY_RX lane 0 receiver synchronization observed" "0,1" bitfld.long 0x4 16. "ACTDL0F,D-PHY_RX lane 0 high-speed reception active" "0,1" newline bitfld.long 0x4 12. "ECTRLDL1F,D-PHY_RX lane 1 control error flag" "0,1" bitfld.long 0x4 11. "ESYNCESCDL1F,D-PHY_RX lane 1 low-power data transmission synchronization error flag" "0,1" newline bitfld.long 0x4 10. "EESCDL1F,D-PHY_RX lane 1 escape entry error flag" "0,1" bitfld.long 0x4 9. "ESOTSYNCDL1F,SOT synchronization error flag on lane 1" "0,1" newline bitfld.long 0x4 8. "ESOTDL1F,SOT error flag on lane 1" "0,1" bitfld.long 0x4 4. "ECTRLDL0F,D-PHY_RX lane 0 control error flag" "0,1" newline bitfld.long 0x4 3. "ESYNCESCDL0F,D-PHY_RX lane 0 low-power data transmission synchronization error flag" "0,1" bitfld.long 0x4 2. "EESCDL0F,D-PHY_RX lane 0 escape entry error flag" "0,1" newline bitfld.long 0x4 1. "ESOTSYNCDL0F,SOT synchronization error flag on lane 0" "0,1" bitfld.long 0x4 0. "ESOTDL0F,SOT error flag on lane 0" "0,1" wgroup.long 0x100++0x7 line.long 0x0 "CSI_FCR0,CSI-2 Host flag clear register 0" bitfld.long 0x0 30. "CSYNCERRF,Clear invalid synchronization error flag" "0,1" bitfld.long 0x0 29. "CWDERRF,Clear watchdog error flag" "0,1" newline bitfld.long 0x0 28. "CSPKTERRF,Clear short packet error flag" "0,1" bitfld.long 0x0 27. "CIDERRF,Clear data type ID error flag" "0,1" newline bitfld.long 0x0 26. "CCECCERRF,Clear corrected ECC error flag" "0,1" bitfld.long 0x0 25. "CECCERRF,Clear ECC error flag" "0,1" newline bitfld.long 0x0 24. "CCRCERRF,Clear CRC error flag" "0,1" bitfld.long 0x0 21. "CCCFIFOFF,Clear clock changer FIFO full flag" "0,1" newline bitfld.long 0x0 16. "CSPKTF,Clear short packet flag" "0,1" bitfld.long 0x0 15. "CEOF3F,Clear EOF flag for virtual channel 3" "0,1" newline bitfld.long 0x0 14. "CEOF2F,Clear EOF flag for virtual channel 2" "0,1" bitfld.long 0x0 13. "CEOF1F,Clear EOF flag for virtual channel 1" "0,1" newline bitfld.long 0x0 12. "CEOF0F,Clear EOF flag for virtual channel 0" "0,1" bitfld.long 0x0 11. "CSOF3F,Clear SOF flag for virtual channel 3" "0,1" newline bitfld.long 0x0 10. "CSOF2F,Clear SOF flag for virtual channel 2" "0,1" bitfld.long 0x0 9. "CSOF1F,Clear SOF flag for virtual channel 1" "0,1" newline bitfld.long 0x0 8. "CSOF0F,Clear SOF flag for virtual channel 0" "0,1" bitfld.long 0x0 7. "CTIM3F,Clear timer 3 flag" "0,1" newline bitfld.long 0x0 6. "CTIM2F,Clear timer 2 flag" "0,1" bitfld.long 0x0 5. "CTIM1F,Clear timer 1 flag" "0,1" newline bitfld.long 0x0 4. "CTIM0F,Clear timer 0 flag" "0,1" bitfld.long 0x0 3. "CLB3F,Clear line/byte counter 3 flag" "0,1" newline bitfld.long 0x0 2. "CLB2F,Clear line/byte counter 2 flag" "0,1" bitfld.long 0x0 1. "CLB1F,Clear line/byte counter 1 flag" "0,1" newline bitfld.long 0x0 0. "CLB0F,Clear line/byte counter 0 flag" "0,1" line.long 0x4 "CSI_FCR1,CSI-2 Host flag clear register 1" bitfld.long 0x4 12. "CECTRLDL1F,Clear D-PHY_RX lane 1 control error flag" "0,1" bitfld.long 0x4 11. "CESYNCESCDL1F,Clear D-PHY_RX lane 1 low-power data transmission synchronization error flag" "0,1" newline bitfld.long 0x4 10. "CEESCDL1F,Clear D-PHY_RX lane 1 escape entry error flag" "0,1" bitfld.long 0x4 9. "CESOTSYNCDL1F,Clear SOT synchronization error flag on lane 1" "0,1" newline bitfld.long 0x4 8. "CESOTDL1F,Clear SOT error flag on lane 1" "0,1" bitfld.long 0x4 4. "CECTRLDL0F,Clear D-PHY_RX lane 0 control error flag" "0,1" newline bitfld.long 0x4 3. "CESYNCESCDL0F,Clear D-PHY_RX lane 0 low-power data transmission synchronization error flag" "0,1" bitfld.long 0x4 2. "CEESCDL0F,Clear D-PHY_RX lane 0 escape entry error flag" "0,1" newline bitfld.long 0x4 1. "CESOTSYNCDL0F,Clear SOT synchronization error flag on lane 0" "0,1" bitfld.long 0x4 0. "CESOTDL0F,Clear SOT error flag on lane 0" "0,1" rgroup.long 0x110++0xB line.long 0x0 "CSI_SPDFR,CSI-2 Host short packet data field register" bitfld.long 0x0 22.--23. "VCHANNEL,Virtual channel" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "DATATYPE,Data type class" newline hexmask.long.word 0x0 0.--15. 1. "DATAFIELD,Data field" line.long 0x4 "CSI_ERR1,CSI-2 Host error register 1" bitfld.long 0x4 22.--23. "IDVCERR,Virtual channel having ID error" "0,1,2,3" hexmask.long.byte 0x4 16.--21. 1. "IDDTERR,Data type in error" newline bitfld.long 0x4 14.--15. "CECCVCERR,Virtual channel having a corrected ECC error" "0,1,2,3" hexmask.long.byte 0x4 8.--13. 1. "CECCDTERR,Data type having a corrected ECC error" newline bitfld.long 0x4 6.--7. "CRCVCERR,Virtual channel having a CRC error" "0,1,2,3" hexmask.long.byte 0x4 0.--5. 1. "CRCDTERR,Data type having a CRC error" line.long 0x8 "CSI_ERR2,CSI-2 Host error register 2" bitfld.long 0x8 18.--19. "SYNCVCERR,Virtual channel having synchronization error" "0,1,2,3" bitfld.long 0x8 16.--17. "WDVCERR,Virtual channel having a watchdog error" "0,1,2,3" newline bitfld.long 0x8 6.--7. "SPKTVCERR,Virtual channel having a short packet error" "0,1,2,3" hexmask.long.byte 0x8 0.--5. 1. "SPKTDTERR,Data type having a short packet error" group.long 0x1000++0xB line.long 0x0 "CSI_PRCR,CSI PHY reset control register" bitfld.long 0x0 1. "PEN,When set to 0 this bit places the digital section of the D-PHY in the reset state." "0: PHY is disabled (in reset state).,1: PHY is enabled (out of reset state)." line.long 0x4 "CSI_PMCR,CSI PHY mode control register" bitfld.long 0x4 16. "TUEXDL0,Tx ULP exit sequence data lane 0" "0,1" bitfld.long 0x4 12. "TUESDL0,Tx ULP escape-mode data lane 0" "0,1" newline bitfld.long 0x4 8. "RTDL0,Turn-around request data lane 0" "0: No request,1: Request for turn-around for DL0" bitfld.long 0x4 4. "DTDL,Disable turn-around data lane 0" "0: Disabled,1: Enabled" newline bitfld.long 0x4 2. "FTXSMDL0,Force to Tx Stop mode the data lane 0" "0: Disabled,1: Enabled" bitfld.long 0x4 1. "FRXMDL1,Force to Rx mode the data lane 1" "0: Disabled,1: Enabled" newline bitfld.long 0x4 0. "FRXMDL0,Force to Rx mode the data lane 0" "0: Disabled,1: Enabled" line.long 0x8 "CSI_PFCR,CSI PHY frequency control register" bitfld.long 0x8 16. "DLD,Data lane direction of lane 0" "0: Rx,1: Tx" hexmask.long.byte 0x8 8.--14. 1. "HSFR,PHY high-speed frequency range selection" newline hexmask.long.byte 0x8 0.--5. 1. "CCFR,Configuration clock frequency range selection" group.long 0x1010++0x7 line.long 0x0 "CSI_PTCR0,CSI PHY test control register 0" bitfld.long 0x0 1. "TRSEN,Test-interface reset enable for the TDI bus into the PHY" "0,1" bitfld.long 0x0 0. "TCKEN,Test-interface clock enable for the TDI bus into the PHY" "0,1" line.long 0x4 "CSI_PTCR1,CSI PHY test control register 1" bitfld.long 0x4 16. "TWM,Test-interface write mode selector" "0: Data write operation is set on the rising edge..,1: Address write operation is set on the falling.." hexmask.long.byte 0x4 0.--7. 1. "TDI,Test-interface data in" rgroup.long 0x1018++0x3 line.long 0x0 "CSI_PTSR,CSI PHY test status register" hexmask.long.byte 0x0 0.--7. 1. "TDO,CSI PHY test interface data output bus for read-back and internal probing functionalities" tree.end tree "CSI_S" base ad:0x58006000 group.long 0x0++0x7 line.long 0x0 "CSI_CR,CSI-2 Host control register" bitfld.long 0x0 15. "VC3STOP,Virtual channel 3 stop" "0: No effect,1: Pulse generation to stop the virtual channel 3.." bitfld.long 0x0 14. "VC3START,Virtual channel 3 start" "0: No effect,1: Pulse generation to start the virtual channel 3.." newline bitfld.long 0x0 11. "VC2STOP,Virtual channel 2 stop" "0: No effect,1: Pulse generation to stop the virtual channel 2.." bitfld.long 0x0 10. "VC2START,Virtual channel 2 start" "0: No effect,1: Pulse generation to start the virtual channel 2.." newline bitfld.long 0x0 7. "VC1STOP,Virtual channel 1 stop" "0: No effect,1: Pulse generation to stop the virtual channel 1.." bitfld.long 0x0 6. "VC1START,Virtual channel 1 start" "0: No effect,1: Pulse generation to start the virtual channel 1.." newline bitfld.long 0x0 3. "VC0STOP,Virtual channel 0 stop" "0: No effect,1: Pulse generation to stop the virtual channel 0.." bitfld.long 0x0 2. "VC0START,Virtual channel 0 start" "0: No effect,1: Pulse generation to start the virtual channel 0.." newline bitfld.long 0x0 0. "CSIEN,CSI-2 enable" "0: CSI-2 disabled,1: CSI-2 enabled" line.long 0x4 "CSI_PCR,CSI-2 Host DPHY_RX control register" bitfld.long 0x4 3. "DL1EN,D-PHY_RX data lane 1 enable" "0: Data lane 1 module is in shutdown mode.,1: Enable the data lane 1 module." bitfld.long 0x4 2. "DL0EN,D-PHY_RX data lane 0 enable" "0: Data lane 0 module is in shutdown mode.,1: Enable the data lane 0 module." newline bitfld.long 0x4 1. "CLEN,Clock lane enable" "0: Clock lanes disabled,1: Clock lanes enabled" bitfld.long 0x4 0. "PWRDOWN,Power down" "0: Active state,1: Power down the D-PHY_RX" group.long 0x10++0x6B line.long 0x0 "CSI_VC0CFGR1,CSI-2 Host virtual channel 0 configuration register 1" hexmask.long.byte 0x0 24.--28. 1. "DT0FT,Data type 0 format" hexmask.long.byte 0x0 16.--21. 1. "DT0,Data type 0 class selection for virtual channel x" newline hexmask.long.byte 0x0 8.--12. 1. "CDTFT,Common format for all data types" bitfld.long 0x0 7. "DT6EN,Data type 6 enable" "0: Data type 6 for virtual channel x is disabled.,1: Data type 6 for virtual channel x is enabled." newline bitfld.long 0x0 6. "DT5EN,Data type 5 enable" "0: Data type 5 for virtual channel x is disabled.,1: Data type 5 for virtual channel x is enabled." bitfld.long 0x0 5. "DT4EN,Data type 4 enable" "0: Data type 4 for virtual channel x is disabled.,1: Data type 4 for virtual channel x is enabled." newline bitfld.long 0x0 4. "DT3EN,Data type 3 enable" "0: Data type 3 for virtual channel x is disabled.,1: Data type 3 for virtual channel x is enabled." bitfld.long 0x0 3. "DT2EN,Data type 2 enable" "0: Data type 2 for virtual channel x is disabled.,1: Data type 2 for virtual channel x is enabled." newline bitfld.long 0x0 2. "DT1EN,Data type 1 enable" "0: Data type 1 for virtual channel x is disabled.,1: Data type 1 for virtual channel x is enabled." bitfld.long 0x0 1. "DT0EN,Data type 0 enable" "0: Data type 0 for virtual channel x is disabled.,1: Data type 0 for virtual channel x is enabled." newline bitfld.long 0x0 0. "ALLDT,All data types enable for the virtual channel x" "0: Data type capture managed individually,1: All data types captured for virtual channel x" line.long 0x4 "CSI_VC0CFGR2,CSI-2 Host virtual channel 0 configuration register 2" hexmask.long.byte 0x4 24.--28. 1. "DT2FT,Data type 2 format" hexmask.long.byte 0x4 16.--21. 1. "DT2,Data type 2 class selection for virtual channel x" newline hexmask.long.byte 0x4 8.--12. 1. "DT1FT,Data type 1 format" hexmask.long.byte 0x4 0.--5. 1. "DT1,Data type 1 class selection for virtual channel x" line.long 0x8 "CSI_VC0CFGR3,CSI-2 Host virtual channel 0 configuration register 3" hexmask.long.byte 0x8 24.--28. 1. "DT4FT,Data type 4 format" hexmask.long.byte 0x8 16.--21. 1. "DT4,Data type 4 class selection for virtual channel x" newline hexmask.long.byte 0x8 8.--12. 1. "DT3FT,Data type 3 format" hexmask.long.byte 0x8 0.--5. 1. "DT3,Data type 3 class selection for virtual channel x" line.long 0xC "CSI_VC0CFGR4,CSI-2 Host virtual channel 0 configuration register 4" hexmask.long.byte 0xC 24.--28. 1. "DT6FT,Data type 6 format" hexmask.long.byte 0xC 16.--21. 1. "DT6,Data type 6 class selection for virtual channel x" newline hexmask.long.byte 0xC 8.--12. 1. "DT5FT,Data type 5 format" hexmask.long.byte 0xC 0.--5. 1. "DT5,Data type 5 class selection for virtual channel x" line.long 0x10 "CSI_VC1CFGR1,CSI-2 Host virtual channel 1 configuration register 1" hexmask.long.byte 0x10 24.--28. 1. "DT0FT,Data type 0 format" hexmask.long.byte 0x10 16.--21. 1. "DT0,Data type 0 class selection for virtual channel x" newline hexmask.long.byte 0x10 8.--12. 1. "CDTFT,Common format for all data types" bitfld.long 0x10 7. "DT6EN,Data type 6 enable" "0: Data type 6 for virtual channel x is disabled.,1: Data type 6 for virtual channel x is enabled." newline bitfld.long 0x10 6. "DT5EN,Data type 5 enable" "0: Data type 5 for virtual channel x is disabled.,1: Data type 5 for virtual channel x is enabled." bitfld.long 0x10 5. "DT4EN,Data type 4 enable" "0: Data type 4 for virtual channel x is disabled.,1: Data type 4 for virtual channel x is enabled." newline bitfld.long 0x10 4. "DT3EN,Data type 3 enable" "0: Data type 3 for virtual channel x is disabled.,1: Data type 3 for virtual channel x is enabled." bitfld.long 0x10 3. "DT2EN,Data type 2 enable" "0: Data type 2 for virtual channel x is disabled.,1: Data type 2 for virtual channel x is enabled." newline bitfld.long 0x10 2. "DT1EN,Data type 1 enable" "0: Data type 1 for virtual channel x is disabled.,1: Data type 1 for virtual channel x is enabled." bitfld.long 0x10 1. "DT0EN,Data type 0 enable" "0: Data type 0 for virtual channel x is disabled.,1: Data type 0 for virtual channel x is enabled." newline bitfld.long 0x10 0. "ALLDT,All data types enable for the virtual channel x" "0: Data type capture managed individually,1: All data types captured for virtual channel x" line.long 0x14 "CSI_VC1CFGR2,CSI-2 Host virtual channel 1 configuration register 2" hexmask.long.byte 0x14 24.--28. 1. "DT2FT,Data type 2 format" hexmask.long.byte 0x14 16.--21. 1. "DT2,Data type 2 class selection for virtual channel x" newline hexmask.long.byte 0x14 8.--12. 1. "DT1FT,Data type 1 format" hexmask.long.byte 0x14 0.--5. 1. "DT1,Data type 1 class selection for virtual channel x" line.long 0x18 "CSI_VC1CFGR3,CSI-2 Host virtual channel 1 configuration register 3" hexmask.long.byte 0x18 24.--28. 1. "DT4FT,Data type 4 format" hexmask.long.byte 0x18 16.--21. 1. "DT4,Data type 4 class selection for virtual channel x" newline hexmask.long.byte 0x18 8.--12. 1. "DT3FT,Data type 3 format" hexmask.long.byte 0x18 0.--5. 1. "DT3,Data type 3 class selection for virtual channel x" line.long 0x1C "CSI_VC1CFGR4,CSI-2 Host virtual channel 1 configuration register 4" hexmask.long.byte 0x1C 24.--28. 1. "DT6FT,Data type 6 format" hexmask.long.byte 0x1C 16.--21. 1. "DT6,Data type 6 class selection for virtual channel x" newline hexmask.long.byte 0x1C 8.--12. 1. "DT5FT,Data type 5 format" hexmask.long.byte 0x1C 0.--5. 1. "DT5,Data type 5 class selection for virtual channel x" line.long 0x20 "CSI_VC2CFGR1,CSI-2 Host virtual channel 2 configuration register 1" hexmask.long.byte 0x20 24.--28. 1. "DT0FT,Data type 0 format" hexmask.long.byte 0x20 16.--21. 1. "DT0,Data type 0 class selection for virtual channel x" newline hexmask.long.byte 0x20 8.--12. 1. "CDTFT,Common format for all data types" bitfld.long 0x20 7. "DT6EN,Data type 6 enable" "0: Data type 6 for virtual channel x is disabled.,1: Data type 6 for virtual channel x is enabled." newline bitfld.long 0x20 6. "DT5EN,Data type 5 enable" "0: Data type 5 for virtual channel x is disabled.,1: Data type 5 for virtual channel x is enabled." bitfld.long 0x20 5. "DT4EN,Data type 4 enable" "0: Data type 4 for virtual channel x is disabled.,1: Data type 4 for virtual channel x is enabled." newline bitfld.long 0x20 4. "DT3EN,Data type 3 enable" "0: Data type 3 for virtual channel x is disabled.,1: Data type 3 for virtual channel x is enabled." bitfld.long 0x20 3. "DT2EN,Data type 2 enable" "0: Data type 2 for virtual channel x is disabled.,1: Data type 2 for virtual channel x is enabled." newline bitfld.long 0x20 2. "DT1EN,Data type 1 enable" "0: Data type 1 for virtual channel x is disabled.,1: Data type 1 for virtual channel x is enabled." bitfld.long 0x20 1. "DT0EN,Data type 0 enable" "0: Data type 0 for virtual channel x is disabled.,1: Data type 0 for virtual channel x is enabled." newline bitfld.long 0x20 0. "ALLDT,All data types enable for the virtual channel x" "0: Data type capture managed individually,1: All data types captured for virtual channel x" line.long 0x24 "CSI_VC2CFGR2,CSI-2 Host virtual channel 2 configuration register 2" hexmask.long.byte 0x24 24.--28. 1. "DT2FT,Data type 2 format" hexmask.long.byte 0x24 16.--21. 1. "DT2,Data type 2 class selection for virtual channel x" newline hexmask.long.byte 0x24 8.--12. 1. "DT1FT,Data type 1 format" hexmask.long.byte 0x24 0.--5. 1. "DT1,Data type 1 class selection for virtual channel x" line.long 0x28 "CSI_VC2CFGR3,CSI-2 Host virtual channel 2 configuration register 3" hexmask.long.byte 0x28 24.--28. 1. "DT4FT,Data type 4 format" hexmask.long.byte 0x28 16.--21. 1. "DT4,Data type 4 class selection for virtual channel x" newline hexmask.long.byte 0x28 8.--12. 1. "DT3FT,Data type 3 format" hexmask.long.byte 0x28 0.--5. 1. "DT3,Data type 3 class selection for virtual channel x" line.long 0x2C "CSI_VC2CFGR4,CSI-2 Host virtual channel 2 configuration register 4" hexmask.long.byte 0x2C 24.--28. 1. "DT6FT,Data type 6 format" hexmask.long.byte 0x2C 16.--21. 1. "DT6,Data type 6 class selection for virtual channel x" newline hexmask.long.byte 0x2C 8.--12. 1. "DT5FT,Data type 5 format" hexmask.long.byte 0x2C 0.--5. 1. "DT5,Data type 5 class selection for virtual channel x" line.long 0x30 "CSI_VC3CFGR1,CSI-2 Host virtual channel 3 configuration register 1" hexmask.long.byte 0x30 24.--28. 1. "DT0FT,Data type 0 format" hexmask.long.byte 0x30 16.--21. 1. "DT0,Data type 0 class selection for virtual channel x" newline hexmask.long.byte 0x30 8.--12. 1. "CDTFT,Common format for all data types" bitfld.long 0x30 7. "DT6EN,Data type 6 enable" "0: Data type 6 for virtual channel x is disabled.,1: Data type 6 for virtual channel x is enabled." newline bitfld.long 0x30 6. "DT5EN,Data type 5 enable" "0: Data type 5 for virtual channel x is disabled.,1: Data type 5 for virtual channel x is enabled." bitfld.long 0x30 5. "DT4EN,Data type 4 enable" "0: Data type 4 for virtual channel x is disabled.,1: Data type 4 for virtual channel x is enabled." newline bitfld.long 0x30 4. "DT3EN,Data type 3 enable" "0: Data type 3 for virtual channel x is disabled.,1: Data type 3 for virtual channel x is enabled." bitfld.long 0x30 3. "DT2EN,Data type 2 enable" "0: Data type 2 for virtual channel x is disabled.,1: Data type 2 for virtual channel x is enabled." newline bitfld.long 0x30 2. "DT1EN,Data type 1 enable" "0: Data type 1 for virtual channel x is disabled.,1: Data type 1 for virtual channel x is enabled." bitfld.long 0x30 1. "DT0EN,Data type 0 enable" "0: Data type 0 for virtual channel x is disabled.,1: Data type 0 for virtual channel x is enabled." newline bitfld.long 0x30 0. "ALLDT,All data types enable for the virtual channel x" "0: Data type capture managed individually,1: All data types captured for virtual channel x" line.long 0x34 "CSI_VC3CFGR2,CSI-2 Host virtual channel 3 configuration register 2" hexmask.long.byte 0x34 24.--28. 1. "DT2FT,Data type 2 format" hexmask.long.byte 0x34 16.--21. 1. "DT2,Data type 2 class selection for virtual channel x" newline hexmask.long.byte 0x34 8.--12. 1. "DT1FT,Data type 1 format" hexmask.long.byte 0x34 0.--5. 1. "DT1,Data type 1 class selection for virtual channel x" line.long 0x38 "CSI_VC3CFGR3,CSI-2 Host virtual channel 3 configuration register 3" hexmask.long.byte 0x38 24.--28. 1. "DT4FT,Data type 4 format" hexmask.long.byte 0x38 16.--21. 1. "DT4,Data type 4 class selection for virtual channel x" newline hexmask.long.byte 0x38 8.--12. 1. "DT3FT,Data type 3 format" hexmask.long.byte 0x38 0.--5. 1. "DT3,Data type 3 class selection for virtual channel x" line.long 0x3C "CSI_VC3CFGR4,CSI-2 Host virtual channel 3 configuration register 4" hexmask.long.byte 0x3C 24.--28. 1. "DT6FT,Data type 6 format" hexmask.long.byte 0x3C 16.--21. 1. "DT6,Data type 6 class selection for virtual channel x" newline hexmask.long.byte 0x3C 8.--12. 1. "DT5FT,Data type 5 format" hexmask.long.byte 0x3C 0.--5. 1. "DT5,Data type 5 class selection for virtual channel x" line.long 0x40 "CSI_LB0CFGR,CSI-2 Host line byte 0 configuration register" hexmask.long.word 0x40 16.--31. 1. "LINECNT,Line counter" hexmask.long.word 0x40 0.--15. 1. "BYTECNT,Byte counter" line.long 0x44 "CSI_LB1CFGR,CSI-2 Host line byte 1 configuration register" hexmask.long.word 0x44 16.--31. 1. "LINECNT,Line counter" hexmask.long.word 0x44 0.--15. 1. "BYTECNT,Byte counter" line.long 0x48 "CSI_LB2CFGR,CSI-2 Host line byte 2 configuration register" hexmask.long.word 0x48 16.--31. 1. "LINECNT,Line counter" hexmask.long.word 0x48 0.--15. 1. "BYTECNT,Byte counter" line.long 0x4C "CSI_LB3CFGR,CSI-2 Host line byte 3 configuration register" hexmask.long.word 0x4C 16.--31. 1. "LINECNT,Line counter" hexmask.long.word 0x4C 0.--15. 1. "BYTECNT,Byte counter" line.long 0x50 "CSI_TIM0CFGR,CSI-2 Host timer 0 configuration register" hexmask.long 0x50 0.--24. 1. "COUNT,Clock cycle counter" line.long 0x54 "CSI_TIM1CFGR,CSI-2 Host timer 1 configuration register" hexmask.long 0x54 0.--24. 1. "COUNT,Clock cycle counter" line.long 0x58 "CSI_TIM2CFGR,CSI-2 Host timer 2 configuration register" hexmask.long 0x58 0.--24. 1. "COUNT,Clock cycle counter" line.long 0x5C "CSI_TIM3CFGR,CSI-2 Host timer 3 configuration register" hexmask.long 0x5C 0.--24. 1. "COUNT,Clock cycle counter" line.long 0x60 "CSI_LMCFGR,CSI-2 Host lane merger configuration register" bitfld.long 0x60 20.--22. "DL1MAP,Physical mapping of logical data lane 1" "?,1: Physical data lane 1 connected to logical data..,2: Physical data lane 1 connected to logical data..,?,?,?,?,?" bitfld.long 0x60 16.--18. "DL0MAP,Physical mapping of logical data lane 0" "?,1: Physical data lane 0 connected to logical data..,2: Physical data lane 0 connected to logical data..,?,?,?,?,?" newline bitfld.long 0x60 8.--10. "LANENB,Number of lanes" "?,1: 1 lane for the reception,2: 2 lanes for the reception,?,?,?,?,?" line.long 0x64 "CSI_PRGITR,CSI-2 Host program interrupt register" bitfld.long 0x64 31. "TIM3EN,TIM3 base time enable" "0: Timer 3 clock cycle counter not active,1: Timer 3 clock cycle counter active" bitfld.long 0x64 30. "TIM3EOF,TIM3 base time starting from the EOF" "0: SOF selected as starting point for the counter,1: EOF selected as starting point for the counter" newline bitfld.long 0x64 28.--29. "TIM3VC,TIM3 base time linked to a virtual channel" "0: Virtual channel 0 used to generate the TIM3 event,1: Virtual channel 1 used to generate the TIM3 event,2: Virtual channel 2 used to generate the TIM3 event,3: Virtual channel 3 used to generate the TIM3 event" bitfld.long 0x64 27. "TIM2EN,TIM2 base time enable" "0: Timer 2 clock cycle counter not active.,1: Timer 2 clock cycle counter active" newline bitfld.long 0x64 26. "TIM2EOF,TIM2 base time starting from the EOF" "0: SOF selected as starting point for the counter,1: EOF selected as starting point for the counter" bitfld.long 0x64 24.--25. "TIM2VC,TIM2 base time linked to a virtual channel" "0: Virtual channel 0 used to generate the TIM2 event,1: Virtual channel 1 used to generate the TIM2 event,2: Virtual channel 2 used to generate the TIM2 event,3: Virtual channel 3 used to generate the TIM2 event" newline bitfld.long 0x64 23. "TIM1EN,TIM1 base time enable" "0: Timer 1 clock cycle counter not active.,1: Timer 1 clock cycle counter active" bitfld.long 0x64 22. "TIM1EOF,TIM1 base time starting from the EOF" "0: SOF selected as starting point for the counter,1: EOF selected as starting point for the counter" newline bitfld.long 0x64 20.--21. "TIM1VC,TIM1 base time linked to a virtual channel" "0: Virtual channel 0 used to generate the TIM1 event,1: Virtual channel 1 used to generate the TIM1 event,2: Virtual channel 2 used to generate the TIM1 event,3: Virtual channel 3 used to generate the TIM1 event" bitfld.long 0x64 19. "TIM0EN,TIM0 base time enable" "0: Timer 0 clock cycle counter not active,1: Timer 0 clock cycle counter active" newline bitfld.long 0x64 18. "TIM0EOF,TIM0 base time starting from the EOF" "0: SOF selected e as starting point for the counter,1: EOF selected as starting point for the counter" bitfld.long 0x64 16.--17. "TIM0VC,TIM0 base time linked to a virtual channel" "0: Virtual channel 0 used to generate the TIM0 event,1: Virtual channel 1 used to generate the TIM0 event,2: Virtual channel 2 used to generate the TIM0 event,3: Virtual channel 3 used to generate the TIM0 event" newline bitfld.long 0x64 15. "LB3EN,Line/byte 3 counter enable" "0: Line/byte 3 counter stopped,1: Line/byte 3 counter active" bitfld.long 0x64 12.--13. "LB3VC,Line/byte counter 3 linked to a virtual channel" "0: Virtual channel 0 used to generate the line/byte..,1: Virtual channel 1 used to generate the line/byte..,2: Virtual channel 2 used to generate the line/byte..,3: Virtual channel 3 used to generate the line/byte.." newline bitfld.long 0x64 11. "LB2EN,Line/byte 2 counter enable" "0: Line/byte 2 counter stopped,1: Line/byte 2 counter active" bitfld.long 0x64 8.--9. "LB2VC,Line/byte counter 2 linked to a virtual channel" "0: Virtual channel 0 used to generate the line/byte..,1: Virtual channel 1 used to generate the line/byte..,2: Virtual channel 2 used to generate the line/byte..,3: Virtual channel 3 used to generate the line/byte.." newline bitfld.long 0x64 7. "LB1EN,Line/byte 1 counter enable" "0: Line/byte 1 counter stopped,1: Line/byte 1 counter active" bitfld.long 0x64 4.--5. "LB1VC,Line/byte counter 1 linked to a virtual channel" "0: Virtual channel 0 used to generate the line/byte..,1: Virtual channel 1 used to generate the line/byte..,2: Virtual channel 2 used to generate the line/byte..,3: Virtual channel 3 used to generate the line/byte.." newline bitfld.long 0x64 3. "LB0EN,Line/byte 0 counter enable" "0: Line/byte 0 counter stopped,1: Line/byte 0 counter active" bitfld.long 0x64 0.--1. "LB0VC,Line/byte counter 0 linked to a virtual channel" "0: Virtual channel 0 used to generate the line/byte..,1: Virtual channel 1 used to generate the line/byte..,2: Virtual channel 2 used to generate the line/byte..,3: Virtual channel 3 used to generate the line/byte.." line.long 0x68 "CSI_WDR,CSI-2 Host watchdog register" hexmask.long 0x68 0.--31. 1. "CNT,Watchdog counter" group.long 0x80++0x7 line.long 0x0 "CSI_IER0,CSI-2 Host interrupt enable register 0" bitfld.long 0x0 30. "SYNCERRIE,Invalid synchronization error interrupt enable" "0: Interrupt on invalid synchronization error..,1: Interrupt on invalid synchronization error enabled" bitfld.long 0x0 29. "WDERRIE,Watchdog error interrupt enable" "0: Interrupt on watchdog error disabled,1: Interrupt on watchdog error enabled" newline bitfld.long 0x0 28. "SPKTERRIE,Short packet error interrupt enable" "0: Interrupt on short packet error disabled,1: Interrupt on short packet error enabled" bitfld.long 0x0 27. "IDERRIE,Data type ID error interrupt enable" "0: Interrupt on reception of reserved data type..,1: Interrupt on reception of reserved data type.." newline bitfld.long 0x0 26. "CECCERRIE,Corrected ECC error interrupt enable" "0: Interrupt on corrected ECC error detection..,1: Interrupt on corrected ECC error detection enabled" bitfld.long 0x0 25. "ECCERRIE,ECC error interrupt enable" "0: Interrupt on ECC error detection disabled,1: Interrupt on ECC error detection enabled" newline bitfld.long 0x0 24. "CRCERRIE,CRC error interrupt enable" "0: Interrupt on CRC error detection disabled,1: Interrupt on CRC error detection enabled" bitfld.long 0x0 21. "CCFIFOFIE,Clock changer FIFO full interrupt enable" "0: Interrupt on clock changer FIFO full detection..,1: Interrupt on clock changer FIFO full detection.." newline bitfld.long 0x0 16. "SPKTIE,Short packet interrupt enable" "0: Short packet detection interrupt disabled,1: Short packet detection interrupt enabled" bitfld.long 0x0 15. "EOF3IE,EOF for virtual channel 3 interrupt enable" "0: EOF on virtual channel 3 interrupt disabled,1: EOF on virtual channel 3 interrupt enabled" newline bitfld.long 0x0 14. "EOF2IE,EOF for virtual channel 2 interrupt enable" "0: EOF on virtual channel 2 interrupt disabled,1: EOF on virtual channel 2 interrupt enabled" bitfld.long 0x0 13. "EOF1IE,EOF for virtual channel 1 interrupt enable" "0: EOF on virtual channel 1 interrupt disabled,1: EOF on virtual channel 1 interrupt enabled" newline bitfld.long 0x0 12. "EOF0IE,EOF for virtual channel 0 interrupt enable" "0: EOF on virtual channel 0 interrupt disabled,1: EOF on virtual channel 0 interrupt enabled" bitfld.long 0x0 11. "SOF3IE,SOF for virtual channel 3 interrupt enable" "0: SOF on virtual channel 3 interrupt disabled,1: SOF on virtual channel 3 interrupt enabled" newline bitfld.long 0x0 10. "SOF2IE,SOF for virtual channel 2 interrupt enable" "0: SOF on virtual channel 2 interrupt disabled,1: SOF on virtual channel 2 interrupt enabled" bitfld.long 0x0 9. "SOF1IE,SOF for virtual channel 1 interrupt enable" "0: SOF on virtual channel 1 interrupt disabled.,1: SOF on virtual channel 1 interrupt enabled." newline bitfld.long 0x0 8. "SOF0IE,SOF for virtual channel 0 interrupt enable" "0: SOF on virtual channel 0 interrupt disabled,1: SOF on virtual channel 0 interrupt enabled" bitfld.long 0x0 7. "TIM3IE,Timer 3 interrupt enable" "0: Timer 3 interrupt disabled,1: Timer 3 interrupt enabled" newline bitfld.long 0x0 6. "TIM2IE,Timer 2 interrupt enable" "0: Timer 2 interrupt disabled,1: Timer 2 interrupt enabled" bitfld.long 0x0 5. "TIM1IE,Timer 1 interrupt enable" "0: Timer 1 interrupt disabled,1: Timer 1 interrupt enabled" newline bitfld.long 0x0 4. "TIM0IE,Timer 0 interrupt enable" "0: Timer 0 interrupt disabled,1: Timer 0 interrupt enabled" bitfld.long 0x0 3. "LB3IE,Line/byte counter 3 interrupt enable" "0,1" newline bitfld.long 0x0 2. "LB2IE,Line/byte counter 2 interrupt enable" "0,1" bitfld.long 0x0 1. "LB1IE,Line/byte counter 1 interrupt enable" "0,1" newline bitfld.long 0x0 0. "LB0IE,Line/byte counter 0 interrupt enable" "0,1" line.long 0x4 "CSI_IER1,CSI-2 Host interrupt enable register 1" bitfld.long 0x4 12. "ECTRLDL1IE,D-PHY_RX lane 1 control error interrupt enable" "0: Lane 1 control error interrupt disabled,1: Lane 1 control error interrupt enabled" bitfld.long 0x4 11. "ESYNCESCDL1IE,D-PHY_RX lane 1 low-power data transmission synchronization error interrupt enable" "0: Lane 1 low-power data transmission interrupt..,1: Lane 1 low-power data transmission Interrupt.." newline bitfld.long 0x4 10. "EESCDL1IE,D-PHY_RX lane 1 escape entry error interrupt enable" "0: Lane 1 unrecognized escape entry command..,1: Lane 1 unrecognized escape entry command.." bitfld.long 0x4 9. "ESOTSYNCDL1IE,SOT synchronization interrupt error enable on lane 1" "0: Lane 1 SOT synchronization interrupt error..,1: Lane 1 SOT synchronization interrupt error enabled" newline bitfld.long 0x4 8. "ESOTDL1IE,SOT error interrupt enable on lane 1" "0: Lane 1 SOT interrupt error disabled,1: Lane 1 SOT interrupt error enabled" bitfld.long 0x4 4. "ECTRLDL0IE,D-PHY_RX lane 0 control error interrupt enable" "0: Lane 0 control error interrupt disabled,1: Lane 0 control error interrupt enabled" newline bitfld.long 0x4 3. "ESYNCESCDL0IE,D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable" "0: Lane 0 low-power data transmission interrupt..,1: Lane 0 low-power data transmission Interrupt.." bitfld.long 0x4 2. "EESCDL0IE,D-PHY_RX lane 0 escape entry error interrupt enable" "0: Lane 0 unrecognized escape entry command..,1: Lane 0 unrecognized escape entry command.." newline bitfld.long 0x4 1. "ESOTSYNCDL0IE,SOT synchronization interrupt error enable on lane 0" "0: Lane 0 SOT synchronization interrupt error..,1: Lane 0 SOT synchronization interrupt error enabled" bitfld.long 0x4 0. "ESOTDL0IE,SOT error interrupt enable on lane 0" "0: Lane 0 SOT interrupt error disabled,1: Lane 0 SOT interrupt error enabled" rgroup.long 0x90++0x7 line.long 0x0 "CSI_SR0,CSI-2 Host status register 0" bitfld.long 0x0 30. "SYNCERRF,Invalid synchronization error flag" "0,1" bitfld.long 0x0 29. "WDERRF,Watchdog error flag" "0,1" newline bitfld.long 0x0 28. "SPKTERRF,Short packet error flag" "0,1" bitfld.long 0x0 27. "IDERRF,Data type ID error flag" "0,1" newline bitfld.long 0x0 26. "CECCERRF,Corrected ECC error flag" "0,1" bitfld.long 0x0 25. "ECCERRF,ECC error flag" "0,1" newline bitfld.long 0x0 24. "CRCERRF,CRC error flag" "0,1" bitfld.long 0x0 21. "CCFIFOFF,Clock changer FIFO full flag" "0,1" newline bitfld.long 0x0 20. "VC3STATEF,Virtual channel 3 state flag" "0: Virtual channel inactive,1: Virtual channel active" bitfld.long 0x0 19. "VC2STATEF,Virtual channel 2 state flag" "0: Virtual channel inactive,1: Virtual channel active" newline bitfld.long 0x0 18. "VC1STATEF,Virtual channel 1 state flag" "0: Virtual channel inactive,1: Virtual channel active" bitfld.long 0x0 17. "VC0STATEF,Virtual channel 0 state flag" "0: Virtual channel inactive,1: Virtual channel active" newline bitfld.long 0x0 16. "SPKTF,Short packet flag" "0,1" bitfld.long 0x0 15. "EOF3F,EOF flag for virtual channel 3" "0,1" newline bitfld.long 0x0 14. "EOF2F,EOF flag for virtual channel 2" "0,1" bitfld.long 0x0 13. "EOF1F,EOF flag for virtual channel 1" "0,1" newline bitfld.long 0x0 12. "EOF0F,EOF flag for virtual channel 0" "0,1" bitfld.long 0x0 11. "SOF3F,SOF flag for virtual channel 3" "0,1" newline bitfld.long 0x0 10. "SOF2F,SOF flag for virtual channel 2" "0,1" bitfld.long 0x0 9. "SOF1F,SOF flag for virtual channel 1" "0,1" newline bitfld.long 0x0 8. "SOF0F,SOF flag for virtual channel 0" "0,1" bitfld.long 0x0 7. "TIM3F,Timer 3 flag" "0,1" newline bitfld.long 0x0 6. "TIM2F,Timer 2 flag" "0,1" bitfld.long 0x0 5. "TIM1F,Timer 1 flag" "0,1" newline bitfld.long 0x0 4. "TIM0F,Timer 0 flag" "0,1" bitfld.long 0x0 3. "LB3F,Line/byte counter 3 flag" "0,1" newline bitfld.long 0x0 2. "LB2F,Line/byte counter 2 flag" "0,1" bitfld.long 0x0 1. "LB1F,Line/byte counter 1 flag" "0,1" newline bitfld.long 0x0 0. "LB0F,Line/byte counter 0 flag" "0,1" line.long 0x4 "CSI_SR1,CSI-2 Host status register 1" bitfld.long 0x4 31. "ACTCLF,D-PHY_RX receiver clock active flag" "0,1" bitfld.long 0x4 30. "ULPNCLF,D-PHY_RX receiver Ultra-Low power state (not) on clock lane." "0,1" newline bitfld.long 0x4 29. "ULPNACTF,D-PHY_RX receiver ULP state (not) active" "0,1" bitfld.long 0x4 28. "STOPCLF,D-PHY_RX receiver in stop state for the clock lane" "0,1" newline bitfld.long 0x4 26. "ULPNDL1F,D-PHY_RX receiver ultra-low-power state (not) active on data lane 1" "0,1" bitfld.long 0x4 25. "STOPDL1F,D-PHY_RX receiver data lane 1 in stop state" "0,1" newline bitfld.long 0x4 24. "SKCALDL1F,D-PHY_RX lane 1 high-speed skew calibration" "0,1" bitfld.long 0x4 23. "SYNCDL1F,D-PHY_RX lane 1 receiver synchronization observed" "0,1" newline bitfld.long 0x4 22. "ACTDL1F,D-PHY_RX lane 1 high-speed reception active" "0,1" bitfld.long 0x4 20. "ULPNDL0F,D-PHY_RX receiver ultra-low-power state (not) active on data lane 0" "0,1" newline bitfld.long 0x4 19. "STOPDL0F,D-PHY_RX receiver data lane 0 in stop state" "0,1" bitfld.long 0x4 18. "SKCALDL0F,D-PHY_RX lane 0 high-speed skew calibration" "0,1" newline bitfld.long 0x4 17. "SYNCDL0F,D-PHY_RX lane 0 receiver synchronization observed" "0,1" bitfld.long 0x4 16. "ACTDL0F,D-PHY_RX lane 0 high-speed reception active" "0,1" newline bitfld.long 0x4 12. "ECTRLDL1F,D-PHY_RX lane 1 control error flag" "0,1" bitfld.long 0x4 11. "ESYNCESCDL1F,D-PHY_RX lane 1 low-power data transmission synchronization error flag" "0,1" newline bitfld.long 0x4 10. "EESCDL1F,D-PHY_RX lane 1 escape entry error flag" "0,1" bitfld.long 0x4 9. "ESOTSYNCDL1F,SOT synchronization error flag on lane 1" "0,1" newline bitfld.long 0x4 8. "ESOTDL1F,SOT error flag on lane 1" "0,1" bitfld.long 0x4 4. "ECTRLDL0F,D-PHY_RX lane 0 control error flag" "0,1" newline bitfld.long 0x4 3. "ESYNCESCDL0F,D-PHY_RX lane 0 low-power data transmission synchronization error flag" "0,1" bitfld.long 0x4 2. "EESCDL0F,D-PHY_RX lane 0 escape entry error flag" "0,1" newline bitfld.long 0x4 1. "ESOTSYNCDL0F,SOT synchronization error flag on lane 0" "0,1" bitfld.long 0x4 0. "ESOTDL0F,SOT error flag on lane 0" "0,1" wgroup.long 0x100++0x7 line.long 0x0 "CSI_FCR0,CSI-2 Host flag clear register 0" bitfld.long 0x0 30. "CSYNCERRF,Clear invalid synchronization error flag" "0,1" bitfld.long 0x0 29. "CWDERRF,Clear watchdog error flag" "0,1" newline bitfld.long 0x0 28. "CSPKTERRF,Clear short packet error flag" "0,1" bitfld.long 0x0 27. "CIDERRF,Clear data type ID error flag" "0,1" newline bitfld.long 0x0 26. "CCECCERRF,Clear corrected ECC error flag" "0,1" bitfld.long 0x0 25. "CECCERRF,Clear ECC error flag" "0,1" newline bitfld.long 0x0 24. "CCRCERRF,Clear CRC error flag" "0,1" bitfld.long 0x0 21. "CCCFIFOFF,Clear clock changer FIFO full flag" "0,1" newline bitfld.long 0x0 16. "CSPKTF,Clear short packet flag" "0,1" bitfld.long 0x0 15. "CEOF3F,Clear EOF flag for virtual channel 3" "0,1" newline bitfld.long 0x0 14. "CEOF2F,Clear EOF flag for virtual channel 2" "0,1" bitfld.long 0x0 13. "CEOF1F,Clear EOF flag for virtual channel 1" "0,1" newline bitfld.long 0x0 12. "CEOF0F,Clear EOF flag for virtual channel 0" "0,1" bitfld.long 0x0 11. "CSOF3F,Clear SOF flag for virtual channel 3" "0,1" newline bitfld.long 0x0 10. "CSOF2F,Clear SOF flag for virtual channel 2" "0,1" bitfld.long 0x0 9. "CSOF1F,Clear SOF flag for virtual channel 1" "0,1" newline bitfld.long 0x0 8. "CSOF0F,Clear SOF flag for virtual channel 0" "0,1" bitfld.long 0x0 7. "CTIM3F,Clear timer 3 flag" "0,1" newline bitfld.long 0x0 6. "CTIM2F,Clear timer 2 flag" "0,1" bitfld.long 0x0 5. "CTIM1F,Clear timer 1 flag" "0,1" newline bitfld.long 0x0 4. "CTIM0F,Clear timer 0 flag" "0,1" bitfld.long 0x0 3. "CLB3F,Clear line/byte counter 3 flag" "0,1" newline bitfld.long 0x0 2. "CLB2F,Clear line/byte counter 2 flag" "0,1" bitfld.long 0x0 1. "CLB1F,Clear line/byte counter 1 flag" "0,1" newline bitfld.long 0x0 0. "CLB0F,Clear line/byte counter 0 flag" "0,1" line.long 0x4 "CSI_FCR1,CSI-2 Host flag clear register 1" bitfld.long 0x4 12. "CECTRLDL1F,Clear D-PHY_RX lane 1 control error flag" "0,1" bitfld.long 0x4 11. "CESYNCESCDL1F,Clear D-PHY_RX lane 1 low-power data transmission synchronization error flag" "0,1" newline bitfld.long 0x4 10. "CEESCDL1F,Clear D-PHY_RX lane 1 escape entry error flag" "0,1" bitfld.long 0x4 9. "CESOTSYNCDL1F,Clear SOT synchronization error flag on lane 1" "0,1" newline bitfld.long 0x4 8. "CESOTDL1F,Clear SOT error flag on lane 1" "0,1" bitfld.long 0x4 4. "CECTRLDL0F,Clear D-PHY_RX lane 0 control error flag" "0,1" newline bitfld.long 0x4 3. "CESYNCESCDL0F,Clear D-PHY_RX lane 0 low-power data transmission synchronization error flag" "0,1" bitfld.long 0x4 2. "CEESCDL0F,Clear D-PHY_RX lane 0 escape entry error flag" "0,1" newline bitfld.long 0x4 1. "CESOTSYNCDL0F,Clear SOT synchronization error flag on lane 0" "0,1" bitfld.long 0x4 0. "CESOTDL0F,Clear SOT error flag on lane 0" "0,1" rgroup.long 0x110++0xB line.long 0x0 "CSI_SPDFR,CSI-2 Host short packet data field register" bitfld.long 0x0 22.--23. "VCHANNEL,Virtual channel" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "DATATYPE,Data type class" newline hexmask.long.word 0x0 0.--15. 1. "DATAFIELD,Data field" line.long 0x4 "CSI_ERR1,CSI-2 Host error register 1" bitfld.long 0x4 22.--23. "IDVCERR,Virtual channel having ID error" "0,1,2,3" hexmask.long.byte 0x4 16.--21. 1. "IDDTERR,Data type in error" newline bitfld.long 0x4 14.--15. "CECCVCERR,Virtual channel having a corrected ECC error" "0,1,2,3" hexmask.long.byte 0x4 8.--13. 1. "CECCDTERR,Data type having a corrected ECC error" newline bitfld.long 0x4 6.--7. "CRCVCERR,Virtual channel having a CRC error" "0,1,2,3" hexmask.long.byte 0x4 0.--5. 1. "CRCDTERR,Data type having a CRC error" line.long 0x8 "CSI_ERR2,CSI-2 Host error register 2" bitfld.long 0x8 18.--19. "SYNCVCERR,Virtual channel having synchronization error" "0,1,2,3" bitfld.long 0x8 16.--17. "WDVCERR,Virtual channel having a watchdog error" "0,1,2,3" newline bitfld.long 0x8 6.--7. "SPKTVCERR,Virtual channel having a short packet error" "0,1,2,3" hexmask.long.byte 0x8 0.--5. 1. "SPKTDTERR,Data type having a short packet error" group.long 0x1000++0xB line.long 0x0 "CSI_PRCR,CSI PHY reset control register" bitfld.long 0x0 1. "PEN,When set to 0 this bit places the digital section of the D-PHY in the reset state." "0: PHY is disabled (in reset state).,1: PHY is enabled (out of reset state)." line.long 0x4 "CSI_PMCR,CSI PHY mode control register" bitfld.long 0x4 16. "TUEXDL0,Tx ULP exit sequence data lane 0" "0,1" bitfld.long 0x4 12. "TUESDL0,Tx ULP escape-mode data lane 0" "0,1" newline bitfld.long 0x4 8. "RTDL0,Turn-around request data lane 0" "0: No request,1: Request for turn-around for DL0" bitfld.long 0x4 4. "DTDL,Disable turn-around data lane 0" "0: Disabled,1: Enabled" newline bitfld.long 0x4 2. "FTXSMDL0,Force to Tx Stop mode the data lane 0" "0: Disabled,1: Enabled" bitfld.long 0x4 1. "FRXMDL1,Force to Rx mode the data lane 1" "0: Disabled,1: Enabled" newline bitfld.long 0x4 0. "FRXMDL0,Force to Rx mode the data lane 0" "0: Disabled,1: Enabled" line.long 0x8 "CSI_PFCR,CSI PHY frequency control register" bitfld.long 0x8 16. "DLD,Data lane direction of lane 0" "0: Rx,1: Tx" hexmask.long.byte 0x8 8.--14. 1. "HSFR,PHY high-speed frequency range selection" newline hexmask.long.byte 0x8 0.--5. 1. "CCFR,Configuration clock frequency range selection" group.long 0x1010++0x7 line.long 0x0 "CSI_PTCR0,CSI PHY test control register 0" bitfld.long 0x0 1. "TRSEN,Test-interface reset enable for the TDI bus into the PHY" "0,1" bitfld.long 0x0 0. "TCKEN,Test-interface clock enable for the TDI bus into the PHY" "0,1" line.long 0x4 "CSI_PTCR1,CSI PHY test control register 1" bitfld.long 0x4 16. "TWM,Test-interface write mode selector" "0: Data write operation is set on the rising edge..,1: Address write operation is set on the falling.." hexmask.long.byte 0x4 0.--7. 1. "TDI,Test-interface data in" rgroup.long 0x1018++0x3 line.long 0x0 "CSI_PTSR,CSI PHY test status register" hexmask.long.byte 0x0 0.--7. 1. "TDO,CSI PHY test interface data output bus for read-back and internal probing functionalities" tree.end tree.end tree "DBGMCU (MCU Debug Component)" base ad:0x0 tree "DBGMCU" base ad:0x44001000 rgroup.long 0x0++0x3 line.long 0x0 "DBGMCU_IDCODE,DBGMCU identity code register" hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision" newline hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device ID" group.long 0x4++0x3 line.long 0x0 "DBGMCU_CR,DBGMCU configuration register" bitfld.long 0x0 31. "HLT_TSGEN_EN,TSGEN halt enable" "0: TSGEN keeps on counting when processor is in halt.,1: TSGEN stops counting when processor is in halt." newline bitfld.long 0x0 28. "DBTRGOEN,DBTRGIO connection control" "0: DBTRGIO connected to DBTRGIN,1: DBTRGIO connected to DBTRGOUT" newline bitfld.long 0x0 21. "TRACECLKEN,TPIU export clock enable through software" "0: TPIU clock is off.,1: TPIU clock is on." newline bitfld.long 0x0 20. "DBGCLKEN,Debug clock enable through software" "0: Debug clock is off.,1: Debug clock is on." newline bitfld.long 0x0 2. "DBG_STANDBY,Allow debug in Standby mode" "0: Normal operation. All clocks are disabled and..,1: Automatic clock stop/power down disabled. All.." newline bitfld.long 0x0 1. "DBG_STOP,Allow debug in Stop mode" "0: Normal operation. All clocks are disabled..,1: Automatic clock stop disabled. All active clocks.." newline bitfld.long 0x0 0. "DBG_SLEEP,Allow debug in Sleep mode" "0: Normal operation. Peripheral clock are stopped..,1: Automatic clock stop disabled. Peripheral clock.." group.long 0x10++0x1B line.long 0x0 "DBGMCU_APB1LFZ1,DBGMCU APB1L peripheral freeze register" bitfld.long 0x0 25. "DBG_I3C2_STOP,I3C2 SMBUS timeout stop in debug" "0: Normal operation. I3C2 SMBUS timeout continues..,1: Stop in debug. I3C2 SMBUS timeout is frozen.." newline bitfld.long 0x0 24. "DBG_I3C1_STOP,I3C1 SMBUS timeout stop in debug" "0: Normal operation. I3C1 SMBUS timeout continues..,1: Stop in debug. I3C1 SMBUS timeout is frozen.." newline bitfld.long 0x0 23. "DBG_I2C3_STOP,I2C3 SMBUS timeout stop in debug" "0: Normal operation. I2C3 SMBUS timeout continues..,1: Stop in debug. I2C3 SMBUS timeout is frozen.." newline bitfld.long 0x0 22. "DBG_I2C2_STOP,I2C2 SMBUS timeout stop in debug" "0: Normal operation. I2C2 SMBUS timeout continues..,1: Stop in debug. I2C2 SMBUS timeout is frozen.." newline bitfld.long 0x0 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout stop in debug" "0: Normal operation. I2C1 SMBUS timeout continues..,1: Stop in debug. I2C1 SMBUS timeout is frozen.." newline bitfld.long 0x0 13. "DBG_TIM11_STOP,TIM11 stop in debug" "0: Normal operation. TIM11 continues to operate..,1: Stop in debug. TIM11 is frozen while Cortex-M55.." newline bitfld.long 0x0 12. "DBG_TIM10_STOP,TIM10 stop in debug" "0: Normal operation. TIM10 continues to operate..,1: Stop in debug. TIM10 is frozen while Cortex-M55.." newline bitfld.long 0x0 11. "DBG_WWDG1_STOP,WWDG1 stop in debug" "0: Normal operation. WWDG1 continues to operate..,1: Stop in debug. WWDG1 is frozen while Cortex-M55.." newline bitfld.long 0x0 9. "DBG_LPTIM1_STOP,LPTIM1 stop in debug" "0: Normal operation. LPTIM1 continues to operate..,1: Stop in debug. LPTIM1 is frozen while Cortex-M55.." newline bitfld.long 0x0 8. "DBG_TIM14_STOP,TIM14 stop in debug" "0: Normal operation. TIM14 continues to operate..,1: Stop in debug. TIM14 is frozen while Cortex-M55.." newline bitfld.long 0x0 7. "DBG_TIM13_STOP,TIM13 stop in debug" "0: Normal operation. TIM13 continues to operate..,1: Stop in debug. TIM13 is frozen while Cortex-M55.." newline bitfld.long 0x0 6. "DBG_TIM12_STOP,TIM12 stop in debug" "0: Normal operation. TIM12 continues to operate..,1: Stop in debug. TIM12 is frozen while Cortex-M55.." newline bitfld.long 0x0 5. "DBG_TIM7_STOP,TIM7 stop in debug" "0: Normal operation. TIM7 continues to operate..,1: Stop in debug. TIM7 is frozen while Cortex-M55.." newline bitfld.long 0x0 4. "DBG_TIM6_STOP,TIM6 stop in debug" "0: Normal operation. TIM6 continues to operate..,1: Stop in debug. TIM6 is frozen while Cortex-M55.." newline bitfld.long 0x0 3. "DBG_TIM5_STOP,TIM5 stop in debug" "0: Normal operation. TIM5 continues to operate..,1: Stop in debug. TIM5 is frozen while Cortex-M55.." newline bitfld.long 0x0 2. "DBG_TIM4_STOP,TIM4 stop in debug" "0: Normal operation. TIM4 continues to operate..,1: Stop in debug. TIM4 is frozen while Cortex-M55.." newline bitfld.long 0x0 1. "DBG_TIM3_STOP,TIM3 stop in debug" "0: Normal operation. TIM3 continues to operate..,1: Stop in debug. TIM3 is frozen while Cortex-M55.." newline bitfld.long 0x0 0. "DBG_TIM2_STOP,TIM2 stop in debug" "0: Normal operation. TIM2 continues to operate..,1: Stop in debug. TIM2 is frozen while Cortex-M55.." line.long 0x4 "DBGMCU_APB1HFZ1,DBGMCU APB1H peripheral freeze register" bitfld.long 0x4 8. "DBG_FDCAN_STOP,FDCAN stop in debug" "0: Normal operation. FDCAN continues to operate..,1: Stop in debug. FDCAN is frozen while Cortex-M55.." line.long 0x8 "DBGMCU_APB2FZ1,DBGMCU APB2 peripheral freeze register" bitfld.long 0x8 19. "DBG_TIM9_STOP,TIM9 stop in debug" "0: Normal operation. TIM9 continues to operate..,1: Stop in debug. TIM9 is frozen while Cortex-M55.." newline bitfld.long 0x8 18. "DBG_TIM17_STOP,TIM17 stop in debug" "0: Normal operation. TIM17 continues to operate..,1: Stop in debug. TIM17 is frozen while Cortex-M55.." newline bitfld.long 0x8 17. "DBG_TIM16_STOP,TIM16 stop in debug" "0: Normal operation. TIM16 continues to operate..,1: Stop in debug. TIM16 is frozen while Cortex-M55.." newline bitfld.long 0x8 16. "DBG_TIM15_STOP,TIM15 stop in debug" "0: Normal operation. TIM15 continues to operate..,1: Stop in debug. TIM15 is frozen while Cortex-M55.." newline bitfld.long 0x8 15. "DBG_TIM18_STOP,TIM18 stop in debug" "0: Normal operation. TIM18 continues to operate..,1: Stop in debug. TIM18 is frozen while Cortex-M55.." newline bitfld.long 0x8 1. "DBG_TIM8_STOP,TIM8 stop in debug" "0: Normal operation. TIM8 continues to operate..,1: Stop in debug. TIM8 is frozen while Cortex-M55.." newline bitfld.long 0x8 0. "DBG_TIM1_STOP,TIM1 stop in debug" "0: Normal operation. TIM1 continues to operate..,1: Stop in debug. TIM1 is frozen while Cortex-M55.." line.long 0xC "DBGMCU_APB4FZ1,DBGMCU APB4 peripheral freeze register" bitfld.long 0xC 18. "DBG_IWDG_STOP,WWDG stop in debug" "0: Normal operation. IWDG continues to operate..,1: Stop in debug. IWDG is frozen while Cortex-M55.." newline bitfld.long 0xC 16. "DBG_RTC_STOP,RTC clock is suspended in debug" "0: Normal operation. Real time clock continues to..,1: Stop in debug. Real time clock is suspended.." newline bitfld.long 0xC 12. "DBG_LPTIM5_STOP,LPTIM5 stop in debug" "0: Normal operation. LPTIM5 continues to operate..,1: Stop in debug. LPTIM5 is frozen while Cortex-M55.." newline bitfld.long 0xC 11. "DBG_LPTIM4_STOP,LPTIM4 stop in debug" "0: Normal operation. LPTIM4 continues to operate..,1: Stop in debug. LPTIM4 is frozen while Cortex-M55.." newline bitfld.long 0xC 10. "DBG_LPTIM3_STOP,LPTIM3 stop in debug" "0: Normal operation. LPTIM3 continues to operate..,1: Stop in debug. LPTIM3 is frozen while Cortex-M55.." newline bitfld.long 0xC 9. "DBG_LPTIM2_STOP,LPTIM2 stop in debug" "0: Normal operation. LPTIM2 continues to operate..,1: Stop in debug. LPTIM2 is frozen while Cortex-M55.." newline bitfld.long 0xC 8. "DBG_I2C4_STOP,I2C4 stop in debug" "0: Normal operation. I2C4 continues to operate..,1: Stop in debug. I2C4 is frozen while Cortex-M55.." line.long 0x10 "DBGMCU_APB5FZ1,DBGMCU APB5 peripheral freeze register" bitfld.long 0x10 4. "DBG_GFXTIM_STOP,GFXTIM stop in debug" "0: Normal operation. GFX timer continues counting..,1: Stop in debug. GFX timer is frozen while.." line.long 0x14 "DBGMCU_AHB1FZ1,DBGMCU AHB1 peripheral freeze register" bitfld.long 0x14 15. "DBG_GPDMA1_CH15_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 14. "DBG_GPDMA1_CH14_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 13. "DBG_GPDMA1_CH13_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 12. "DBG_GPDMA1_CH12_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 11. "DBG_GPDMA1_CH11_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 10. "DBG_GPDMA1_CH10_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 9. "DBG_GPDMA1_CH9_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 8. "DBG_GPDMA1_CH8_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 7. "DBG_GPDMA1_CH7_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 6. "DBG_GPDMA1_CH6_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 5. "DBG_GPDMA1_CH5_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 4. "DBG_GPDMA1_CH4_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 3. "DBG_GPDMA1_CH3_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 2. "DBG_GPDMA1_CH2_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 1. "DBG_GPDMA1_CH1_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 0. "DBG_GPDMA1_CH0_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." line.long 0x18 "DBGMCU_AHB5FZ1,DBGMCU AHB5 peripheral freeze register" bitfld.long 0x18 16. "NPU_DBG_FREEZE,NPU stop in debug mode" "0: Normal operation. The NPU continues to operate..,1: Stop in debug. NPU is suspended while Cortex-M55.." newline bitfld.long 0x18 15. "DBG_HPDMA1_CH15_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 14. "DBG_HPDMA1_CH14_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 13. "DBG_HPDMA1_CH13_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 12. "DBG_HPDMA1_CH12_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 11. "DBG_HPDMA1_CH11_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 10. "DBG_HPDMA1_CH10_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 9. "DBG_HPDMA1_CH9_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 8. "DBG_HPDMA1_CH8_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 7. "DBG_HPDMA1_CH7_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 6. "DBG_HPDMA1_CH6_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 5. "DBG_HPDMA1_CH5_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 4. "DBG_HPDMA1_CH4_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 3. "DBG_HPDMA1_CH3_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 2. "DBG_HPDMA1_CH2_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 1. "DBG_HPDMA1_CH1_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 0. "DBG_HPDMA1_CH0_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." rgroup.long 0xFC++0x3 line.long 0x0 "DBGMCU_SR,DBGMCU status register" bitfld.long 0x0 17. "AP1_ENABLE,Access point 1 enable" "0: AP disabled (debug access locked),1: AP enabled (debug access open)" newline bitfld.long 0x0 16. "AP0_ENABLE,Access point 0 enable" "?,1: Always enable" newline bitfld.long 0x0 1. "AP1_PRESENT,Access point 1 presence" "?,1: AP present" newline bitfld.long 0x0 0. "AP0_PRESENT,Access point 0 presence" "?,1: AP present" group.long 0x100++0x7 line.long 0x0 "DBGMCU_DBG_AUTH_HOST,DBGMCU host authentication register" hexmask.long 0x0 0.--31. 1. "MESSAGE,Mailbox between debugger and processor" line.long 0x4 "DBGMCU_DBG_AUTH_DEV,DBGMCU device authentication register" hexmask.long 0x4 0.--31. 1. "MESSAGE,Mailbox between debugger and processor" rgroup.long 0x108++0x3 line.long 0x0 "DBGMCU_DBG_AUTH_ACK,DBGMCU message read acknowledge authentication register" bitfld.long 0x0 1. "DEVICE_ACK,Access status to DBG_AUTH_DEV register" "0: Debugger has read DBG_AUTH_DEV.,1: Processor has written DBG_AUTH_DEV." newline bitfld.long 0x0 0. "HOST_ACK,Access status to DBG_AUTH_HOST register" "0: Processor has read DBG_AUTH_HOST.,1: Debugger has written DBG_AUTH_HOST." tree.end tree "DBGMCU_S" base ad:0x54001000 rgroup.long 0x0++0x3 line.long 0x0 "DBGMCU_IDCODE,DBGMCU identity code register" hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision" newline hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device ID" group.long 0x4++0x3 line.long 0x0 "DBGMCU_CR,DBGMCU configuration register" bitfld.long 0x0 31. "HLT_TSGEN_EN,TSGEN halt enable" "0: TSGEN keeps on counting when processor is in halt.,1: TSGEN stops counting when processor is in halt." newline bitfld.long 0x0 28. "DBTRGOEN,DBTRGIO connection control" "0: DBTRGIO connected to DBTRGIN,1: DBTRGIO connected to DBTRGOUT" newline bitfld.long 0x0 21. "TRACECLKEN,TPIU export clock enable through software" "0: TPIU clock is off.,1: TPIU clock is on." newline bitfld.long 0x0 20. "DBGCLKEN,Debug clock enable through software" "0: Debug clock is off.,1: Debug clock is on." newline bitfld.long 0x0 2. "DBG_STANDBY,Allow debug in Standby mode" "0: Normal operation. All clocks are disabled and..,1: Automatic clock stop/power down disabled. All.." newline bitfld.long 0x0 1. "DBG_STOP,Allow debug in Stop mode" "0: Normal operation. All clocks are disabled..,1: Automatic clock stop disabled. All active clocks.." newline bitfld.long 0x0 0. "DBG_SLEEP,Allow debug in Sleep mode" "0: Normal operation. Peripheral clock are stopped..,1: Automatic clock stop disabled. Peripheral clock.." group.long 0x10++0x1B line.long 0x0 "DBGMCU_APB1LFZ1,DBGMCU APB1L peripheral freeze register" bitfld.long 0x0 25. "DBG_I3C2_STOP,I3C2 SMBUS timeout stop in debug" "0: Normal operation. I3C2 SMBUS timeout continues..,1: Stop in debug. I3C2 SMBUS timeout is frozen.." newline bitfld.long 0x0 24. "DBG_I3C1_STOP,I3C1 SMBUS timeout stop in debug" "0: Normal operation. I3C1 SMBUS timeout continues..,1: Stop in debug. I3C1 SMBUS timeout is frozen.." newline bitfld.long 0x0 23. "DBG_I2C3_STOP,I2C3 SMBUS timeout stop in debug" "0: Normal operation. I2C3 SMBUS timeout continues..,1: Stop in debug. I2C3 SMBUS timeout is frozen.." newline bitfld.long 0x0 22. "DBG_I2C2_STOP,I2C2 SMBUS timeout stop in debug" "0: Normal operation. I2C2 SMBUS timeout continues..,1: Stop in debug. I2C2 SMBUS timeout is frozen.." newline bitfld.long 0x0 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout stop in debug" "0: Normal operation. I2C1 SMBUS timeout continues..,1: Stop in debug. I2C1 SMBUS timeout is frozen.." newline bitfld.long 0x0 13. "DBG_TIM11_STOP,TIM11 stop in debug" "0: Normal operation. TIM11 continues to operate..,1: Stop in debug. TIM11 is frozen while Cortex-M55.." newline bitfld.long 0x0 12. "DBG_TIM10_STOP,TIM10 stop in debug" "0: Normal operation. TIM10 continues to operate..,1: Stop in debug. TIM10 is frozen while Cortex-M55.." newline bitfld.long 0x0 11. "DBG_WWDG1_STOP,WWDG1 stop in debug" "0: Normal operation. WWDG1 continues to operate..,1: Stop in debug. WWDG1 is frozen while Cortex-M55.." newline bitfld.long 0x0 9. "DBG_LPTIM1_STOP,LPTIM1 stop in debug" "0: Normal operation. LPTIM1 continues to operate..,1: Stop in debug. LPTIM1 is frozen while Cortex-M55.." newline bitfld.long 0x0 8. "DBG_TIM14_STOP,TIM14 stop in debug" "0: Normal operation. TIM14 continues to operate..,1: Stop in debug. TIM14 is frozen while Cortex-M55.." newline bitfld.long 0x0 7. "DBG_TIM13_STOP,TIM13 stop in debug" "0: Normal operation. TIM13 continues to operate..,1: Stop in debug. TIM13 is frozen while Cortex-M55.." newline bitfld.long 0x0 6. "DBG_TIM12_STOP,TIM12 stop in debug" "0: Normal operation. TIM12 continues to operate..,1: Stop in debug. TIM12 is frozen while Cortex-M55.." newline bitfld.long 0x0 5. "DBG_TIM7_STOP,TIM7 stop in debug" "0: Normal operation. TIM7 continues to operate..,1: Stop in debug. TIM7 is frozen while Cortex-M55.." newline bitfld.long 0x0 4. "DBG_TIM6_STOP,TIM6 stop in debug" "0: Normal operation. TIM6 continues to operate..,1: Stop in debug. TIM6 is frozen while Cortex-M55.." newline bitfld.long 0x0 3. "DBG_TIM5_STOP,TIM5 stop in debug" "0: Normal operation. TIM5 continues to operate..,1: Stop in debug. TIM5 is frozen while Cortex-M55.." newline bitfld.long 0x0 2. "DBG_TIM4_STOP,TIM4 stop in debug" "0: Normal operation. TIM4 continues to operate..,1: Stop in debug. TIM4 is frozen while Cortex-M55.." newline bitfld.long 0x0 1. "DBG_TIM3_STOP,TIM3 stop in debug" "0: Normal operation. TIM3 continues to operate..,1: Stop in debug. TIM3 is frozen while Cortex-M55.." newline bitfld.long 0x0 0. "DBG_TIM2_STOP,TIM2 stop in debug" "0: Normal operation. TIM2 continues to operate..,1: Stop in debug. TIM2 is frozen while Cortex-M55.." line.long 0x4 "DBGMCU_APB1HFZ1,DBGMCU APB1H peripheral freeze register" bitfld.long 0x4 8. "DBG_FDCAN_STOP,FDCAN stop in debug" "0: Normal operation. FDCAN continues to operate..,1: Stop in debug. FDCAN is frozen while Cortex-M55.." line.long 0x8 "DBGMCU_APB2FZ1,DBGMCU APB2 peripheral freeze register" bitfld.long 0x8 19. "DBG_TIM9_STOP,TIM9 stop in debug" "0: Normal operation. TIM9 continues to operate..,1: Stop in debug. TIM9 is frozen while Cortex-M55.." newline bitfld.long 0x8 18. "DBG_TIM17_STOP,TIM17 stop in debug" "0: Normal operation. TIM17 continues to operate..,1: Stop in debug. TIM17 is frozen while Cortex-M55.." newline bitfld.long 0x8 17. "DBG_TIM16_STOP,TIM16 stop in debug" "0: Normal operation. TIM16 continues to operate..,1: Stop in debug. TIM16 is frozen while Cortex-M55.." newline bitfld.long 0x8 16. "DBG_TIM15_STOP,TIM15 stop in debug" "0: Normal operation. TIM15 continues to operate..,1: Stop in debug. TIM15 is frozen while Cortex-M55.." newline bitfld.long 0x8 15. "DBG_TIM18_STOP,TIM18 stop in debug" "0: Normal operation. TIM18 continues to operate..,1: Stop in debug. TIM18 is frozen while Cortex-M55.." newline bitfld.long 0x8 1. "DBG_TIM8_STOP,TIM8 stop in debug" "0: Normal operation. TIM8 continues to operate..,1: Stop in debug. TIM8 is frozen while Cortex-M55.." newline bitfld.long 0x8 0. "DBG_TIM1_STOP,TIM1 stop in debug" "0: Normal operation. TIM1 continues to operate..,1: Stop in debug. TIM1 is frozen while Cortex-M55.." line.long 0xC "DBGMCU_APB4FZ1,DBGMCU APB4 peripheral freeze register" bitfld.long 0xC 18. "DBG_IWDG_STOP,WWDG stop in debug" "0: Normal operation. IWDG continues to operate..,1: Stop in debug. IWDG is frozen while Cortex-M55.." newline bitfld.long 0xC 16. "DBG_RTC_STOP,RTC clock is suspended in debug" "0: Normal operation. Real time clock continues to..,1: Stop in debug. Real time clock is suspended.." newline bitfld.long 0xC 12. "DBG_LPTIM5_STOP,LPTIM5 stop in debug" "0: Normal operation. LPTIM5 continues to operate..,1: Stop in debug. LPTIM5 is frozen while Cortex-M55.." newline bitfld.long 0xC 11. "DBG_LPTIM4_STOP,LPTIM4 stop in debug" "0: Normal operation. LPTIM4 continues to operate..,1: Stop in debug. LPTIM4 is frozen while Cortex-M55.." newline bitfld.long 0xC 10. "DBG_LPTIM3_STOP,LPTIM3 stop in debug" "0: Normal operation. LPTIM3 continues to operate..,1: Stop in debug. LPTIM3 is frozen while Cortex-M55.." newline bitfld.long 0xC 9. "DBG_LPTIM2_STOP,LPTIM2 stop in debug" "0: Normal operation. LPTIM2 continues to operate..,1: Stop in debug. LPTIM2 is frozen while Cortex-M55.." newline bitfld.long 0xC 8. "DBG_I2C4_STOP,I2C4 stop in debug" "0: Normal operation. I2C4 continues to operate..,1: Stop in debug. I2C4 is frozen while Cortex-M55.." line.long 0x10 "DBGMCU_APB5FZ1,DBGMCU APB5 peripheral freeze register" bitfld.long 0x10 4. "DBG_GFXTIM_STOP,GFXTIM stop in debug" "0: Normal operation. GFX timer continues counting..,1: Stop in debug. GFX timer is frozen while.." line.long 0x14 "DBGMCU_AHB1FZ1,DBGMCU AHB1 peripheral freeze register" bitfld.long 0x14 15. "DBG_GPDMA1_CH15_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 14. "DBG_GPDMA1_CH14_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 13. "DBG_GPDMA1_CH13_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 12. "DBG_GPDMA1_CH12_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 11. "DBG_GPDMA1_CH11_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 10. "DBG_GPDMA1_CH10_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 9. "DBG_GPDMA1_CH9_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 8. "DBG_GPDMA1_CH8_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 7. "DBG_GPDMA1_CH7_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 6. "DBG_GPDMA1_CH6_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 5. "DBG_GPDMA1_CH5_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 4. "DBG_GPDMA1_CH4_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 3. "DBG_GPDMA1_CH3_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 2. "DBG_GPDMA1_CH2_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 1. "DBG_GPDMA1_CH1_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." newline bitfld.long 0x14 0. "DBG_GPDMA1_CH0_STOP,GPDMA1_CHn suspend in debug" "0: Normal operation. GPDMA1_CHn continues to..,1: Stop in debug. GPDMA1_CHn is suspended while.." line.long 0x18 "DBGMCU_AHB5FZ1,DBGMCU AHB5 peripheral freeze register" bitfld.long 0x18 16. "NPU_DBG_FREEZE,NPU stop in debug mode" "0: Normal operation. The NPU continues to operate..,1: Stop in debug. NPU is suspended while Cortex-M55.." newline bitfld.long 0x18 15. "DBG_HPDMA1_CH15_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 14. "DBG_HPDMA1_CH14_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 13. "DBG_HPDMA1_CH13_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 12. "DBG_HPDMA1_CH12_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 11. "DBG_HPDMA1_CH11_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 10. "DBG_HPDMA1_CH10_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 9. "DBG_HPDMA1_CH9_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 8. "DBG_HPDMA1_CH8_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 7. "DBG_HPDMA1_CH7_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 6. "DBG_HPDMA1_CH6_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 5. "DBG_HPDMA1_CH5_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 4. "DBG_HPDMA1_CH4_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 3. "DBG_HPDMA1_CH3_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 2. "DBG_HPDMA1_CH2_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 1. "DBG_HPDMA1_CH1_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." newline bitfld.long 0x18 0. "DBG_HPDMA1_CH0_STOP,HPDMA3_CHn suspend in debug" "0: Normal operation. HPDMA3_CHn continues to..,1: Stop in debug. HPDMA3_CHn is suspended while.." rgroup.long 0xFC++0x3 line.long 0x0 "DBGMCU_SR,DBGMCU status register" bitfld.long 0x0 17. "AP1_ENABLE,Access point 1 enable" "0: AP disabled (debug access locked),1: AP enabled (debug access open)" newline bitfld.long 0x0 16. "AP0_ENABLE,Access point 0 enable" "?,1: Always enable" newline bitfld.long 0x0 1. "AP1_PRESENT,Access point 1 presence" "?,1: AP present" newline bitfld.long 0x0 0. "AP0_PRESENT,Access point 0 presence" "?,1: AP present" group.long 0x100++0x7 line.long 0x0 "DBGMCU_DBG_AUTH_HOST,DBGMCU host authentication register" hexmask.long 0x0 0.--31. 1. "MESSAGE,Mailbox between debugger and processor" line.long 0x4 "DBGMCU_DBG_AUTH_DEV,DBGMCU device authentication register" hexmask.long 0x4 0.--31. 1. "MESSAGE,Mailbox between debugger and processor" rgroup.long 0x108++0x3 line.long 0x0 "DBGMCU_DBG_AUTH_ACK,DBGMCU message read acknowledge authentication register" bitfld.long 0x0 1. "DEVICE_ACK,Access status to DBG_AUTH_DEV register" "0: Debugger has read DBG_AUTH_DEV.,1: Processor has written DBG_AUTH_DEV." newline bitfld.long 0x0 0. "HOST_ACK,Access status to DBG_AUTH_HOST register" "0: Processor has read DBG_AUTH_HOST.,1: Debugger has written DBG_AUTH_HOST." tree.end tree.end tree "DCMI (Digital Camera Interface)" base ad:0x0 tree "DCMI" base ad:0x48028400 group.long 0x0++0x3 line.long 0x0 "DCMI_CR,DCMI control register" bitfld.long 0x0 20. "OELS,Odd/Even Line Select (Line Select Start)" "0: Interface captures first line after the frame..,1: Interface captures second line from the frame.." bitfld.long 0x0 19. "LSM,Line Select mode" "0: Interface captures all received lines.,1: Interface captures one line out of two." newline bitfld.long 0x0 18. "OEBS,Odd/Even Byte Select (Byte Select Start)" "0: Interface captures first data (byte or double..,1: Interface captures second data (byte or double.." bitfld.long 0x0 16.--17. "BSM,Byte Select mode" "0: Interface captures all received data.,1: Interface captures every other byte from the..,2: Interface captures one byte out of four.,3: Interface captures two bytes out of four." newline bitfld.long 0x0 14. "ENABLE,DCMI enable" "0: DCMI disabled,1: DCMI enabled" bitfld.long 0x0 10.--11. "EDM,Extended data mode" "0: Interface captures 8-bit data on every pixel..,1: Interface captures 10-bit data on every pixel..,2: Interface captures 12-bit data on every pixel..,3: Interface captures 14-bit data on every pixel.." newline bitfld.long 0x0 8.--9. "FCRC,Frame capture rate control" "0: All frames are captured.,1: Every alternate frame captured (50% bandwidth..,2: One frame out of four captured (75% bandwidth..,?" bitfld.long 0x0 7. "VSPOL,Vertical synchronization polarity" "0: DCMI_VSYNC active low,1: DCMI_VSYNC active high" newline bitfld.long 0x0 6. "HSPOL,Horizontal synchronization polarity" "0: DCMI_HSYNC active low,1: DCMI_HSYNC active high" bitfld.long 0x0 5. "PCKPOL,Pixel clock polarity" "0: Falling edge active,1: Rising edge active" newline bitfld.long 0x0 4. "ESS,Embedded synchronization select" "0: Hardware synchronization data capture..,1: Embedded synchronization data capture is.." bitfld.long 0x0 3. "JPEG,JPEG format" "0: Uncompressed video format,1: This bit is used for JPEG data transfers. The.." newline bitfld.long 0x0 2. "CROP,Crop feature" "0: The full image is captured. In this case the..,1: Only the data inside the window specified by the.." bitfld.long 0x0 1. "CM,Capture mode" "0: Continuous grab mode - The received data are..,1: Snapshot mode (single frame) - Once activated.." newline bitfld.long 0x0 0. "CAPTURE,Capture enable" "0: Capture disabled,1: Capture enabled" rgroup.long 0x4++0x7 line.long 0x0 "DCMI_SR,DCMI status register" bitfld.long 0x0 2. "FNE,FIFO not empty" "0: FIFO empty,1: FIFO contains valid data." bitfld.long 0x0 1. "VSYNC,Vertical synchronization" "0: active frame,1: synchronization between frames" newline bitfld.long 0x0 0. "HSYNC,Horizontal synchronization" "0: active line,1: synchronization between lines" line.long 0x4 "DCMI_RIS,DCMI raw interrupt status register" bitfld.long 0x4 4. "LINE_RIS,Line raw interrupt status" "0,1" bitfld.long 0x4 3. "VSYNC_RIS,DCMI_VSYNC raw interrupt status" "0,1" newline bitfld.long 0x4 2. "ERR_RIS,Synchronization error raw interrupt status" "0: No synchronization error detected,1: Embedded synchronization characters are not.." bitfld.long 0x4 1. "OVR_RIS,Overrun raw interrupt status" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and the data FIFO.." newline bitfld.long 0x4 0. "FRAME_RIS,Capture complete raw interrupt status" "0: No new capture,1: A frame has been captured." group.long 0xC++0x3 line.long 0x0 "DCMI_IER,DCMI interrupt enable register" bitfld.long 0x0 4. "LINE_IE,Line interrupt enable" "0: No interrupt generation when the line is received,1: An Interrupt is generated when a line has been.." bitfld.long 0x0 3. "VSYNC_IE,DCMI_VSYNC interrupt enable" "0: No interrupt generation,1: An interrupt is generated on each DCMI_VSYNC.." newline bitfld.long 0x0 2. "ERR_IE,Synchronization error interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the embedded.." bitfld.long 0x0 1. "OVR_IE,Overrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the DMA was not.." newline bitfld.long 0x0 0. "FRAME_IE,Capture complete interrupt enable" "0: No interrupt generation,1: An interrupt is generated at the end of each.." rgroup.long 0x10++0x3 line.long 0x0 "DCMI_MIS,DCMI masked interrupt status register" bitfld.long 0x0 4. "LINE_MIS,Line masked interrupt status" "0: No interrupt generation when the line is received,1: An Interrupt is generated when a line has been.." bitfld.long 0x0 3. "VSYNC_MIS,VSYNC masked interrupt status" "0: No interrupt is generated on DCMI_VSYNC..,1: An interrupt is generated on each DCMI_VSYNC.." newline bitfld.long 0x0 2. "ERR_MIS,Synchronization error masked interrupt status" "0: No interrupt is generated on a synchronization..,1: An interrupt is generated if the embedded.." bitfld.long 0x0 1. "OVR_MIS,Overrun masked interrupt status" "0: No interrupt is generated on overrun.,1: An interrupt is generated if the DMA was not.." newline bitfld.long 0x0 0. "FRAME_MIS,Capture complete masked interrupt status" "0: No interrupt is generated after a complete..,1: An interrupt is generated at the end of each.." wgroup.long 0x14++0x3 line.long 0x0 "DCMI_ICR,DCMI interrupt clear register" bitfld.long 0x0 4. "LINE_ISC,line interrupt status clear" "0,1" bitfld.long 0x0 3. "VSYNC_ISC,Vertical Synchronization interrupt status clear" "0,1" newline bitfld.long 0x0 2. "ERR_ISC,Synchronization error interrupt status clear" "0,1" bitfld.long 0x0 1. "OVR_ISC,Overrun interrupt status clear" "0,1" newline bitfld.long 0x0 0. "FRAME_ISC,Capture complete interrupt status clear" "0,1" group.long 0x18++0xF line.long 0x0 "DCMI_ESCR,DCMI embedded synchronization code register" hexmask.long.byte 0x0 24.--31. 1. "FEC,Frame end delimiter code" hexmask.long.byte 0x0 16.--23. 1. "LEC,Line end delimiter code" newline hexmask.long.byte 0x0 8.--15. 1. "LSC,Line start delimiter code" hexmask.long.byte 0x0 0.--7. 1. "FSC,Frame start delimiter code" line.long 0x4 "DCMI_ESUR,DCMI embedded synchronization unmask register" hexmask.long.byte 0x4 24.--31. 1. "FEU,Frame end delimiter unmask" hexmask.long.byte 0x4 16.--23. 1. "LEU,Line end delimiter unmask" newline hexmask.long.byte 0x4 8.--15. 1. "LSU,Line start delimiter unmask" hexmask.long.byte 0x4 0.--7. 1. "FSU,Frame start delimiter unmask" line.long 0x8 "DCMI_CWSTRT,DCMI crop window start" hexmask.long.word 0x8 16.--28. 1. "VST,Vertical start line count" hexmask.long.word 0x8 0.--13. 1. "HOFFCNT,Horizontal offset count" line.long 0xC "DCMI_CWSIZE,DCMI crop window size" hexmask.long.word 0xC 16.--29. 1. "VLINE,Vertical line count" hexmask.long.word 0xC 0.--13. 1. "CAPCNT,Capture count" rgroup.long 0x28++0x3 line.long 0x0 "DCMI_DR,DCMI data register" hexmask.long.byte 0x0 24.--31. 1. "BYTE3,Data byte 3" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,Data byte 2" newline hexmask.long.byte 0x0 8.--15. 1. "BYTE1,Data byte 1" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,Data byte 0" tree.end tree "DCMI_S" base ad:0x58028400 group.long 0x0++0x3 line.long 0x0 "DCMI_CR,DCMI control register" bitfld.long 0x0 20. "OELS,Odd/Even Line Select (Line Select Start)" "0: Interface captures first line after the frame..,1: Interface captures second line from the frame.." bitfld.long 0x0 19. "LSM,Line Select mode" "0: Interface captures all received lines.,1: Interface captures one line out of two." newline bitfld.long 0x0 18. "OEBS,Odd/Even Byte Select (Byte Select Start)" "0: Interface captures first data (byte or double..,1: Interface captures second data (byte or double.." bitfld.long 0x0 16.--17. "BSM,Byte Select mode" "0: Interface captures all received data.,1: Interface captures every other byte from the..,2: Interface captures one byte out of four.,3: Interface captures two bytes out of four." newline bitfld.long 0x0 14. "ENABLE,DCMI enable" "0: DCMI disabled,1: DCMI enabled" bitfld.long 0x0 10.--11. "EDM,Extended data mode" "0: Interface captures 8-bit data on every pixel..,1: Interface captures 10-bit data on every pixel..,2: Interface captures 12-bit data on every pixel..,3: Interface captures 14-bit data on every pixel.." newline bitfld.long 0x0 8.--9. "FCRC,Frame capture rate control" "0: All frames are captured.,1: Every alternate frame captured (50% bandwidth..,2: One frame out of four captured (75% bandwidth..,?" bitfld.long 0x0 7. "VSPOL,Vertical synchronization polarity" "0: DCMI_VSYNC active low,1: DCMI_VSYNC active high" newline bitfld.long 0x0 6. "HSPOL,Horizontal synchronization polarity" "0: DCMI_HSYNC active low,1: DCMI_HSYNC active high" bitfld.long 0x0 5. "PCKPOL,Pixel clock polarity" "0: Falling edge active,1: Rising edge active" newline bitfld.long 0x0 4. "ESS,Embedded synchronization select" "0: Hardware synchronization data capture..,1: Embedded synchronization data capture is.." bitfld.long 0x0 3. "JPEG,JPEG format" "0: Uncompressed video format,1: This bit is used for JPEG data transfers. The.." newline bitfld.long 0x0 2. "CROP,Crop feature" "0: The full image is captured. In this case the..,1: Only the data inside the window specified by the.." bitfld.long 0x0 1. "CM,Capture mode" "0: Continuous grab mode - The received data are..,1: Snapshot mode (single frame) - Once activated.." newline bitfld.long 0x0 0. "CAPTURE,Capture enable" "0: Capture disabled,1: Capture enabled" rgroup.long 0x4++0x7 line.long 0x0 "DCMI_SR,DCMI status register" bitfld.long 0x0 2. "FNE,FIFO not empty" "0: FIFO empty,1: FIFO contains valid data." bitfld.long 0x0 1. "VSYNC,Vertical synchronization" "0: active frame,1: synchronization between frames" newline bitfld.long 0x0 0. "HSYNC,Horizontal synchronization" "0: active line,1: synchronization between lines" line.long 0x4 "DCMI_RIS,DCMI raw interrupt status register" bitfld.long 0x4 4. "LINE_RIS,Line raw interrupt status" "0,1" bitfld.long 0x4 3. "VSYNC_RIS,DCMI_VSYNC raw interrupt status" "0,1" newline bitfld.long 0x4 2. "ERR_RIS,Synchronization error raw interrupt status" "0: No synchronization error detected,1: Embedded synchronization characters are not.." bitfld.long 0x4 1. "OVR_RIS,Overrun raw interrupt status" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and the data FIFO.." newline bitfld.long 0x4 0. "FRAME_RIS,Capture complete raw interrupt status" "0: No new capture,1: A frame has been captured." group.long 0xC++0x3 line.long 0x0 "DCMI_IER,DCMI interrupt enable register" bitfld.long 0x0 4. "LINE_IE,Line interrupt enable" "0: No interrupt generation when the line is received,1: An Interrupt is generated when a line has been.." bitfld.long 0x0 3. "VSYNC_IE,DCMI_VSYNC interrupt enable" "0: No interrupt generation,1: An interrupt is generated on each DCMI_VSYNC.." newline bitfld.long 0x0 2. "ERR_IE,Synchronization error interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the embedded.." bitfld.long 0x0 1. "OVR_IE,Overrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the DMA was not.." newline bitfld.long 0x0 0. "FRAME_IE,Capture complete interrupt enable" "0: No interrupt generation,1: An interrupt is generated at the end of each.." rgroup.long 0x10++0x3 line.long 0x0 "DCMI_MIS,DCMI masked interrupt status register" bitfld.long 0x0 4. "LINE_MIS,Line masked interrupt status" "0: No interrupt generation when the line is received,1: An Interrupt is generated when a line has been.." bitfld.long 0x0 3. "VSYNC_MIS,VSYNC masked interrupt status" "0: No interrupt is generated on DCMI_VSYNC..,1: An interrupt is generated on each DCMI_VSYNC.." newline bitfld.long 0x0 2. "ERR_MIS,Synchronization error masked interrupt status" "0: No interrupt is generated on a synchronization..,1: An interrupt is generated if the embedded.." bitfld.long 0x0 1. "OVR_MIS,Overrun masked interrupt status" "0: No interrupt is generated on overrun.,1: An interrupt is generated if the DMA was not.." newline bitfld.long 0x0 0. "FRAME_MIS,Capture complete masked interrupt status" "0: No interrupt is generated after a complete..,1: An interrupt is generated at the end of each.." wgroup.long 0x14++0x3 line.long 0x0 "DCMI_ICR,DCMI interrupt clear register" bitfld.long 0x0 4. "LINE_ISC,line interrupt status clear" "0,1" bitfld.long 0x0 3. "VSYNC_ISC,Vertical Synchronization interrupt status clear" "0,1" newline bitfld.long 0x0 2. "ERR_ISC,Synchronization error interrupt status clear" "0,1" bitfld.long 0x0 1. "OVR_ISC,Overrun interrupt status clear" "0,1" newline bitfld.long 0x0 0. "FRAME_ISC,Capture complete interrupt status clear" "0,1" group.long 0x18++0xF line.long 0x0 "DCMI_ESCR,DCMI embedded synchronization code register" hexmask.long.byte 0x0 24.--31. 1. "FEC,Frame end delimiter code" hexmask.long.byte 0x0 16.--23. 1. "LEC,Line end delimiter code" newline hexmask.long.byte 0x0 8.--15. 1. "LSC,Line start delimiter code" hexmask.long.byte 0x0 0.--7. 1. "FSC,Frame start delimiter code" line.long 0x4 "DCMI_ESUR,DCMI embedded synchronization unmask register" hexmask.long.byte 0x4 24.--31. 1. "FEU,Frame end delimiter unmask" hexmask.long.byte 0x4 16.--23. 1. "LEU,Line end delimiter unmask" newline hexmask.long.byte 0x4 8.--15. 1. "LSU,Line start delimiter unmask" hexmask.long.byte 0x4 0.--7. 1. "FSU,Frame start delimiter unmask" line.long 0x8 "DCMI_CWSTRT,DCMI crop window start" hexmask.long.word 0x8 16.--28. 1. "VST,Vertical start line count" hexmask.long.word 0x8 0.--13. 1. "HOFFCNT,Horizontal offset count" line.long 0xC "DCMI_CWSIZE,DCMI crop window size" hexmask.long.word 0xC 16.--29. 1. "VLINE,Vertical line count" hexmask.long.word 0xC 0.--13. 1. "CAPCNT,Capture count" rgroup.long 0x28++0x3 line.long 0x0 "DCMI_DR,DCMI data register" hexmask.long.byte 0x0 24.--31. 1. "BYTE3,Data byte 3" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,Data byte 2" newline hexmask.long.byte 0x0 8.--15. 1. "BYTE1,Data byte 1" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,Data byte 0" tree.end tree.end tree "DCMIPP (Digital Camera Interface Pixel Pipeline)" base ad:0x0 tree "DCMIPP" base ad:0x48002000 group.long 0x0++0x7 line.long 0x0 "DCMIPP_IPGR1,DCMIPP IPPLUG global register 1" bitfld.long 0x0 24. "QOS_MODE,Quality of service" "0,1" bitfld.long 0x0 0.--2. "MEMORYPAGE,Memory page size as power of 2 of 64-byte units:" "0: 64 bytes,1: 128 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPGR2,DCMIPP IPPLUG global register 2" bitfld.long 0x4 0. "PSTART,Request to lock the IP-Plug to allow reconfiguration." "0: No lock requested IP-Plug runs on demand by..,1: Lock requested: IP-Plug freezes shortly (see.." rgroup.long 0x8++0x3 line.long 0x0 "DCMIPP_IPGR3,DCMIPP IPPLUG global register 3" bitfld.long 0x0 0. "IDLE,Status of IP-Plug" "0: IP-Plug is running (on demand by background HW),1: IP-Plug is currently locked and can be.." rgroup.long 0x1C++0x3 line.long 0x0 "DCMIPP_IPGR8,DCMIPP IPPLUG identification register" hexmask.long.byte 0x0 24.--31. 1. "IPPID,IP identifier (0xAA)" hexmask.long.byte 0x0 16.--20. 1. "ARCHIID,Architecture identifier (0x04)" newline hexmask.long.byte 0x0 8.--12. 1. "REVID,Revision identifier (0x03)" hexmask.long.byte 0x0 0.--5. 1. "DID,Division identifier (0x14)" group.long 0x20++0xB line.long 0x0 "DCMIPP_IPC1R1,DCMIPP IPPLUG Clientx register 1" hexmask.long.byte 0x0 8.--11. 1. "OTR,Maximum outstanding transactions" bitfld.long 0x0 0.--2. "TRAFFIC,Burst size as power of 2 of 8-byte units" "0: 8 bytes,1: 16 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPC1R2,DCMIPP IPPLUG Clientx register 2" hexmask.long.byte 0x4 16.--19. 1. "WLRU,Ratio for WLRU[3:0] arbitration" hexmask.long.byte 0x4 8.--11. 1. "SVCMAPPING,Non-user must be kept at reset value." line.long 0x8 "DCMIPP_IPC1R3,DCMIPP IPPLUG Clientx register 3" hexmask.long.word 0x8 16.--25. 1. "DPREGEND,End word (AXI width = 64 bits) of the FIFO of Clientx." hexmask.long.word 0x8 0.--9. 1. "DPREGSTART,Start word (AXI width = 64 bits) of the FIFO of Clientx." group.long 0x30++0xB line.long 0x0 "DCMIPP_IPC2R1,DCMIPP IPPLUG Clientx register 1" hexmask.long.byte 0x0 8.--11. 1. "OTR,Maximum outstanding transactions" bitfld.long 0x0 0.--2. "TRAFFIC,Burst size as power of 2 of 8-byte units" "0: 8 bytes,1: 16 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPC2R2,DCMIPP IPPLUG Clientx register 2" hexmask.long.byte 0x4 16.--19. 1. "WLRU,Ratio for WLRU[3:0] arbitration" hexmask.long.byte 0x4 8.--11. 1. "SVCMAPPING,Non-user must be kept at reset value." line.long 0x8 "DCMIPP_IPC2R3,DCMIPP IPPLUG Clientx register 3" hexmask.long.word 0x8 16.--25. 1. "DPREGEND,End word (AXI width = 64 bits) of the FIFO of Clientx." hexmask.long.word 0x8 0.--9. 1. "DPREGSTART,Start word (AXI width = 64 bits) of the FIFO of Clientx." group.long 0x40++0xB line.long 0x0 "DCMIPP_IPC3R1,DCMIPP IPPLUG Clientx register 1" hexmask.long.byte 0x0 8.--11. 1. "OTR,Maximum outstanding transactions" bitfld.long 0x0 0.--2. "TRAFFIC,Burst size as power of 2 of 8-byte units" "0: 8 bytes,1: 16 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPC3R2,DCMIPP IPPLUG Clientx register 2" hexmask.long.byte 0x4 16.--19. 1. "WLRU,Ratio for WLRU[3:0] arbitration" hexmask.long.byte 0x4 8.--11. 1. "SVCMAPPING,Non-user must be kept at reset value." line.long 0x8 "DCMIPP_IPC3R3,DCMIPP IPPLUG Clientx register 3" hexmask.long.word 0x8 16.--25. 1. "DPREGEND,End word (AXI width = 64 bits) of the FIFO of Clientx." hexmask.long.word 0x8 0.--9. 1. "DPREGSTART,Start word (AXI width = 64 bits) of the FIFO of Clientx." group.long 0x50++0xB line.long 0x0 "DCMIPP_IPC4R1,DCMIPP IPPLUG Clientx register 1" hexmask.long.byte 0x0 8.--11. 1. "OTR,Maximum outstanding transactions" bitfld.long 0x0 0.--2. "TRAFFIC,Burst size as power of 2 of 8-byte units" "0: 8 bytes,1: 16 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPC4R2,DCMIPP IPPLUG Clientx register 2" hexmask.long.byte 0x4 16.--19. 1. "WLRU,Ratio for WLRU[3:0] arbitration" hexmask.long.byte 0x4 8.--11. 1. "SVCMAPPING,Non-user must be kept at reset value." line.long 0x8 "DCMIPP_IPC4R3,DCMIPP IPPLUG Clientx register 3" hexmask.long.word 0x8 16.--25. 1. "DPREGEND,End word (AXI width = 64 bits) of the FIFO of Clientx." hexmask.long.word 0x8 0.--9. 1. "DPREGSTART,Start word (AXI width = 64 bits) of the FIFO of Clientx." group.long 0x60++0xB line.long 0x0 "DCMIPP_IPC5R1,DCMIPP IPPLUG Clientx register 1" hexmask.long.byte 0x0 8.--11. 1. "OTR,Maximum outstanding transactions" bitfld.long 0x0 0.--2. "TRAFFIC,Burst size as power of 2 of 8-byte units" "0: 8 bytes,1: 16 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPC5R2,DCMIPP IPPLUG Clientx register 2" hexmask.long.byte 0x4 16.--19. 1. "WLRU,Ratio for WLRU[3:0] arbitration" hexmask.long.byte 0x4 8.--11. 1. "SVCMAPPING,Non-user must be kept at reset value." line.long 0x8 "DCMIPP_IPC5R3,DCMIPP IPPLUG Clientx register 3" hexmask.long.word 0x8 16.--25. 1. "DPREGEND,End word (AXI width = 64 bits) of the FIFO of Clientx." hexmask.long.word 0x8 0.--9. 1. "DPREGSTART,Start word (AXI width = 64 bits) of the FIFO of Clientx." group.long 0x104++0xB line.long 0x0 "DCMIPP_PRCR,DCMIPP parallel interface control register" bitfld.long 0x0 26. "SWAPBITS,Swap LSB vs. MSB within each received component" "0: As received,1: Swapped MSB vs. LSB" bitfld.long 0x0 25. "SWAPCYCLES,Swap data (cycle 0 vs. cycle 1) for pixels received on two cycles" "0: Default,1: Swap active: the data of cycle 1 is used before.." newline hexmask.long.byte 0x0 16.--23. 1. "FORMAT,Other values: data are captured and output as-is only through the data/dump pipeline (e.g. JPEG or byte input format)." bitfld.long 0x0 14. "ENABLE,Parallel interface enable" "0: Parallel interface disabled to lower power..,1: Parallel interface enabled" newline bitfld.long 0x0 10.--12. "EDM,Extended data mode" "0: Interface captures 8-bit data on every pixel clock,1: Interface captures 10-bit data on every pixel..,2: Interface captures 12-bit data on every pixel..,3: Interface captures 14-bit data on every pixel..,4: Interface captures 16-bit data on every pixel..,?,?,?" bitfld.long 0x0 7. "VSPOL,Vertical synchronization polarity" "0: VSYNC active low,1: VSYNC active high" newline bitfld.long 0x0 6. "HSPOL,Horizontal synchronization polarity" "0: HSYNC active low,1: HSYNC active high" bitfld.long 0x0 5. "PCKPOL,Pixel clock polarity" "0: Falling edge active,1: Rising edge active" newline bitfld.long 0x0 4. "ESS,Embedded synchronization select" "0: Hardware synchronization data capture..,1: Embedded synchronization data capture is.." line.long 0x4 "DCMIPP_PRESCR,DCMIPP parallel interface embedded synchronization code register" hexmask.long.byte 0x4 24.--31. 1. "FEC,Frame end delimiter code" hexmask.long.byte 0x4 16.--23. 1. "LEC,Line end delimiter code" newline hexmask.long.byte 0x4 8.--15. 1. "LSC,Line start delimiter code" hexmask.long.byte 0x4 0.--7. 1. "FSC,Frame start delimiter code" line.long 0x8 "DCMIPP_PRESUR,DCMIPP parallel interface embedded synchronization unmask register" hexmask.long.byte 0x8 24.--31. 1. "FEU,Frame end delimiter unmask" hexmask.long.byte 0x8 16.--23. 1. "LEU,Line end delimiter unmask" newline hexmask.long.byte 0x8 8.--15. 1. "LSU,Line start delimiter unmask" hexmask.long.byte 0x8 0.--7. 1. "FSU,Frame start delimiter unmask" group.long 0x1F4++0x3 line.long 0x0 "DCMIPP_PRIER,DCMIPP parallel interface interrupt enable register" bitfld.long 0x0 6. "ERRIE,Synchronization error interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the embedded.." rgroup.long 0x1F8++0x3 line.long 0x0 "DCMIPP_PRSR,DCMIPP parallel interface status register" bitfld.long 0x0 17. "VSYNC,This bit gives the state of the VSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit .." "0: Active frame,1: Synchronization between frames" bitfld.long 0x0 16. "HSYNC,This bit gives the state of the HSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit .." "0: Active line,1: Synchronization between lines" newline bitfld.long 0x0 6. "ERRF,Synchronization error raw interrupt status" "0: No synchronization error detected,1: Embedded synchronization characters are not.." wgroup.long 0x1FC++0x3 line.long 0x0 "DCMIPP_PRFCR,DCMIPP parallel interface interrupt clear register" bitfld.long 0x0 6. "CERRF,Synchronization error interrupt status clear" "0,1" group.long 0x204++0x3 line.long 0x0 "DCMIPP_CMCR,DCMIPP common configuration register" bitfld.long 0x0 7. "SWAPRB,Swap R/U and B/V" "0: RGB/VYU,1: BGR/UYV" bitfld.long 0x0 4. "CFC,Clear frame counter" "0,1" newline bitfld.long 0x0 1.--2. "PSFC,Pipe selection for the frame counter" "0: Frame counter mapped to Pipe0,1: Frame counter mapped to Pipe1,2: Frame counter mapped to Pipe2,?" bitfld.long 0x0 0. "INSEL,input selection" "0: DCMI,1: CSI-2" rgroup.long 0x208++0x3 line.long 0x0 "DCMIPP_CMFRCR,DCMIPP common frame counter register" hexmask.long 0x0 0.--31. 1. "FRMCNT,Frame counter read-only loops around." group.long 0x3F0++0x3 line.long 0x0 "DCMIPP_CMIER,DCMIPP common interrupt enable register" bitfld.long 0x0 31. "P2OVRIE,Overrun interrupt status enable for Pipe2" "0: No interrupt generation,1: An interrupt is generated" bitfld.long 0x0 26. "P2VSYNCIE,Vertical sync interrupt enable for Pipe2" "0: No interrupt generation,1: An interrupt is generated." newline bitfld.long 0x0 25. "P2FRAMEIE,Frame capture complete interrupt enable for Pipe2" "0: No interrupt generation,1: An interrupt is generated." bitfld.long 0x0 24. "P2LINEIE,Multi-line capture complete interrupt enable for Pipe2" "0: No interrupt generation,1: An interrupt is generated." newline bitfld.long 0x0 23. "P1OVRIE,Overrun interrupt enable for Pipe1" "0,1" bitfld.long 0x0 18. "P1VSYNCIE,Vertical sync interrupt enable for Pipe1" "0: No interrupt generation,1: An interrupt is generated" newline bitfld.long 0x0 17. "P1FRAMEIE,Frame capture complete interrupt enable for Pipe1" "0: No interrupt generation,1: An interrupt is generated" bitfld.long 0x0 16. "P1LINEIE,Multi-line capture complete interrupt status clear for Pipe1" "0: No interrupt generation,1: An interrupt is generated" newline bitfld.long 0x0 15. "P0OVRIE,Overrun interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated" bitfld.long 0x0 14. "P0LIMITIE,Limit interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated" newline bitfld.long 0x0 10. "P0VSYNCIE,Vertical sync interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated" bitfld.long 0x0 9. "P0FRAMEIE,Frame capture complete interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated" newline bitfld.long 0x0 8. "P0LINEIE,Multi-line capture complete interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated" bitfld.long 0x0 6. "PRERRIE,Limit interrupt enable for the parallel Interface" "0: No interrupt generation,1: An interrupt is generated" newline bitfld.long 0x0 5. "ATXERRIE,AXI transfer error interrupt enable for IPPLUG" "0: No interrupt generation,1: An interrupt is generated" rgroup.long 0x3F4++0x7 line.long 0x0 "DCMIPP_CMSR1,DCMIPP common status register 1" bitfld.long 0x0 31. "P2CPTACT,Active frame capture (active from start-of-frame to frame complete) for Pipe2" "0: No capture currently active,1: Capture currently active" bitfld.long 0x0 25. "P2LSTFRM,Last frame LSB bit sampled at frame capture complete event for Pipe2" "0,1" newline bitfld.long 0x0 24. "P2LSTLINE,Last line LSB bit sampled at frame capture complete event for Pipe2" "0,1" bitfld.long 0x0 23. "P1CPTACT,Active frame capture (active from start-of-frame to frame complete) for Pipe1" "0: No capture currently active,1: Capture currently active" newline bitfld.long 0x0 17. "P1LSTFRM,Last frame LSB bit sampled at frame capture complete event for Pipe1" "0,1" bitfld.long 0x0 16. "P1LSTLINE,Last line LSB bit sampled at Frame capture complete event for Pipe1" "0,1" newline bitfld.long 0x0 15. "P0CPTACT,Active frame capture (active from start-of-frame to frame complete) for Pipe0" "0: No capture currently active,1: Capture currently active" bitfld.long 0x0 9. "P0LSTFRM,Last frame LSB bit sampled at Frame capture complete event for Pipe0" "0,1" newline bitfld.long 0x0 8. "P0LSTLINE,Last line LSB bit sampled at Frame capture complete event for Pipe0" "0,1" bitfld.long 0x0 1. "PRVSYNC,This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the.." "0: Active frame,1: Synchronization between frames" newline bitfld.long 0x0 0. "PRHSYNC,This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the.." "0: Active line,1: Synchronization between lines" line.long 0x4 "DCMIPP_CMSR2,DCMIPP common status register 2" bitfld.long 0x4 31. "P2OVRF,Overrun raw interrupt status for Pipe2" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.." bitfld.long 0x4 26. "P2VSYNCF,VSYNC raw interrupt status for Pipe2" "0,1" newline bitfld.long 0x4 25. "P2FRAMEF,Frame capture completed raw interrupt status for Pipe2" "0: No capture or ongoing capture,1: All data of a frame have been captured" bitfld.long 0x4 24. "P2LINEF,Multi-line capture completed raw interrupt status for Pipe2" "0,1" newline bitfld.long 0x4 23. "P1OVRF,Overrun raw interrupt status for Pipe1" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.." bitfld.long 0x4 18. "P1VSYNCF,VSYNC raw interrupt status for Pipe1" "0,1" newline bitfld.long 0x4 17. "P1FRAMEF,Frame capture completed raw interrupt status for Pipe1" "0: No capture or ongoing capture,1: All data of a frame have been captured" bitfld.long 0x4 16. "P1LINEF,Multi-line capture completed raw interrupt status for Pipe1" "0,1" newline bitfld.long 0x4 15. "P0OVRF,Overrun raw interrupt status for Pipe0" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.." bitfld.long 0x4 14. "P0LIMITF,Limit raw interrupt status for Pipe0" "0,1" newline bitfld.long 0x4 10. "P0VSYNCF,VSYNC raw interrupt status for Pipe0" "0,1" bitfld.long 0x4 9. "P0FRAMEF,Frame capture completed raw interrupt status for Pipe0" "0: No capture or ongoing capture,1: All data of a frame have been captured" newline bitfld.long 0x4 8. "P0LINEF,Multi-line capture completed raw interrupt status for Pipe0" "0,1" bitfld.long 0x4 6. "PRERRF,Synchronization error raw interrupt status for the parallel interface." "0: No synchronization error detected,1: Embedded synchronization characters are not.." newline bitfld.long 0x4 5. "ATXERRF,AXI transfer error interrupt status flag for the IPPLUG." "0: No AXI transfer error detected,1: AXI transfer error occurred on an AXI client." wgroup.long 0x3FC++0x3 line.long 0x0 "DCMIPP_CMFCR,DCMIPP common interrupt clear register" bitfld.long 0x0 31. "CP2OVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 26. "CP2VSYNCF,Vertical synchronization interrupt status clear" "0,1" newline bitfld.long 0x0 25. "CP2FRAMEF,Frame capture complete interrupt status clear" "0,1" bitfld.long 0x0 24. "CP2LINEF,Multi-line capture complete interrupt status clear" "0,1" newline bitfld.long 0x0 23. "CP1OVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 18. "CP1VSYNCF,Vertical synchronization interrupt status clear" "0,1" newline bitfld.long 0x0 17. "CP1FRAMEF,Frame capture complete interrupt status clear" "0,1" bitfld.long 0x0 16. "CP1LINEF,Multi-line capture complete interrupt status clear" "0,1" newline bitfld.long 0x0 15. "CP0OVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 14. "CP0LIMITF,limit interrupt status clear" "0,1" newline bitfld.long 0x0 10. "CP0VSYNCF,Vertical synchronization interrupt status clear" "0,1" bitfld.long 0x0 9. "CP0FRAMEF,Frame capture complete interrupt status clear" "0,1" newline bitfld.long 0x0 8. "CP0LINEF,Multi-line capture complete interrupt status clear" "0,1" bitfld.long 0x0 6. "CPRERRF,Synchronization error interrupt status clear" "0,1" newline bitfld.long 0x0 5. "CATXERRF,AXI transfer error interrupt status clear" "0,1" group.long 0x404++0x3 line.long 0x0 "DCMIPP_P0FSCR,DCMIPP Pipe0 flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Activation of PipeN" "0: Pipe disabled,1: Pipe enabled can start capturing with CPTMODE.." bitfld.long 0x0 19.--20. "VC,Flow selection mode" "0,1,2,3" newline bitfld.long 0x0 16.--17. "DTMODE,Flow selection mode" "0: Only flow DTIDA from the selected virtual..,1: Flows DTIDA and/or DTIDB from the selected..,2: All data types from the selected virtual channel..,3: All data types of the selected virtual channel.." hexmask.long.byte 0x0 8.--13. 1. "DTIDB,Data type selection ID B" newline hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Data type selection ID A" group.long 0x500++0xB line.long 0x0 "DCMIPP_P0FCTCR,DCMIPP Pipe0 flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame,1: Capture requested for next frame" bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode - The received data are..,1: Snapshot mode (single frame) - Once activated.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P0SCSTR,DCMIPP Pipe0 stat/crop start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 words wide" line.long 0x8 "DCMIPP_P0SCSZR,DCMIPP Pipe0 stat/crop size register" bitfld.long 0x8 31. "ENABLE,This bit is set and cleared by software." "0: Bypass. All the data are computed if the..,1: Enable. Depending on bit POSNEG value the.." bitfld.long 0x8 30. "POSNEG,This bit is set and cleared by software. It has a meaning only if ENABLE bit is set." "0: Positive area the rectangle defined by VSIZE..,1: Negative area the area excluding the rectangle.." newline hexmask.long.word 0x8 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 word wide (data 32-bit)" rgroup.long 0x5B0++0x3 line.long 0x0 "DCMIPP_P0DCCNTR,DCMIPP Pipe0 dump counter register" hexmask.long 0x0 0.--25. 1. "CNT,Number of data dumped during the frame." group.long 0x5B4++0x3 line.long 0x0 "DCMIPP_P0DCLMTR,DCMIPP Pipe0 dump limit register" bitfld.long 0x0 31. "ENABLE,None" "0: Disabled no check on the amount of 32-bit words..,1: Enabled check done versus limit" hexmask.long.tbyte 0x0 0.--23. 1. "LIMIT,Maximum number of 32-bit data that can be dumped during a frame after the crop 2D operation." group.long 0x5C0++0xB line.long 0x0 "DCMIPP_P0PPCR,DCMIPP Pipe0 pixel packer configuration register" bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe0 always..,1: Double buffer mode activated. Dump address.." bitfld.long 0x0 13.--15. "LINEMULT,Amount of capture completed lines for LINE event and interrupt" "0: Event after one line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 11. "OELS,Odd/even line select (line select start)" "0: Interface captures first line after the frame..,1: Interface captures second line from the frame.." bitfld.long 0x0 10. "LSM,Line select mode" "0: Interface captures all received lines,1: Interface captures one line out of two" newline bitfld.long 0x0 9. "OEBS,Odd/even byte select (byte select start)" "0: Interface captures the first data (byte or..,1: Interface captures the second data (byte or.." bitfld.long 0x0 7.--8. "BSM,Byte select mode" "0: Interface captures all received data,1: Interface captures 1 data out of 2,2: Interface captures one byte out of four,3: Interface captures two bytes out of four" newline bitfld.long 0x0 6. "HEADEREN,CSI header dump enable" "0: CSI-2 headers are not dumped,1: CSI-2 headers are dumped as a 32-bit word." bitfld.long 0x0 5. "PAD,Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment." "0: Aligns on LSB (and pads null bits on MSB) for..,1: Aligns on MSB (and pads null bits on LSB) for.." newline bitfld.long 0x0 0. "SWAPYUV,Swaps within a 32-bit word byte 0-vs-1 and byte 2-vs-3. It corresponds for YUV422 pixels formats to swap between UYVY and YUYV." "0: Outputs the provided words as described in..,1: Swaps the bytes from provided words byte 0-vs.-1.." line.long 0x4 "DCMIPP_P0PPM0AR1,DCMIPP Pipe0 pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P0PPM0AR2,DCMIPP Pipe0 pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" rgroup.long 0x5D0++0x3 line.long 0x0 "DCMIPP_P0STM0AR,DCMIPP Pipe0 status Memory0 address register" hexmask.long 0x0 0.--31. 1. "M0A,Memory0 address" group.long 0x5F4++0x3 line.long 0x0 "DCMIPP_P0IER,DCMIPP Pipe0 interrupt enable register" bitfld.long 0x0 7. "OVRIE,Overrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the AXI master is.." bitfld.long 0x0 6. "LIMITIE,Limit interrupt enable" "0: No interrupt generation when the limit is reached,1: An interrupt is generated when the limit is.." newline bitfld.long 0x0 2. "VSYNCIE,VSYNC interrupt enable" "0: No interrupt generation,1: An interrupt is generated on each VSYNC.." bitfld.long 0x0 1. "FRAMEIE,Frame capture completed interrupt enable" "0: No interrupt generation,1: An interrupt is generated after the full capture.." newline bitfld.long 0x0 0. "LINEIE,Multi-line capture completed interrupt enable" "0: No interrupt generation when the line is received,1: An interrupt is generated after the full capture.." rgroup.long 0x5F8++0x3 line.long 0x0 "DCMIPP_P0SR,DCMIPP Pipe0 status register" bitfld.long 0x0 23. "CPTACT,Capture immediate status" "0: Capture currently inactive,1: Capture currently active" bitfld.long 0x0 17. "LSTFRM,Last frame LSB bit sampled at frame capture complete event. The information is extracted from the frame data number that can be delivered by the camera through the CSI2 interface." "0,1" newline bitfld.long 0x0 16. "LSTLINE,Last line LSB bit sampled at frame capture complete event." "0,1" bitfld.long 0x0 7. "OVRF,Overrun raw interrupt status" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.." newline bitfld.long 0x0 6. "LIMITF,Limit raw interrupt status" "0,1" bitfld.long 0x0 2. "VSYNCF,VSYNC raw interrupt status" "0,1" newline bitfld.long 0x0 1. "FRAMEF,Frame capture completed raw interrupt status" "0: No capture or ongoing capture,1: All data of a frame have been captured" bitfld.long 0x0 0. "LINEF,Multi-line capture completed raw interrupt status" "0,1" wgroup.long 0x5FC++0x3 line.long 0x0 "DCMIPP_P0FCR,DCMIPP Pipe0 interrupt clear register" bitfld.long 0x0 7. "COVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 6. "CLIMITF,limit interrupt status clear" "0,1" newline bitfld.long 0x0 2. "CVSYNCF,Vertical synchronization interrupt status clear" "0,1" bitfld.long 0x0 1. "CFRAMEF,Frame capture complete interrupt status clear" "0,1" newline bitfld.long 0x0 0. "CLINEF,Multi-line capture complete interrupt status clear" "0,1" rgroup.long 0x604++0x3 line.long 0x0 "DCMIPP_P0CFSCR,DCMIPP Pipe0 current flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Current activation of PipeN" "0: Pipe disabled,1: Pipe enabled can start capturing with CPTMODE.." bitfld.long 0x0 19.--20. "VC,Current flow selection mode" "0,1,2,3" newline bitfld.long 0x0 16.--17. "DTMODE,Flow selection mode" "0: Only flow DTIDA from the selected virtual..,1: Flows DTIDA and/or DTIDB from the selected..,2: All Datatypes from the selected virtual channel..,3: All Datatypes of the selected virtual channel VC.." hexmask.long.byte 0x0 8.--13. 1. "DTIDB,Current data type selection ID B" newline hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Current data type selection ID A" rgroup.long 0x700++0xB line.long 0x0 "DCMIPP_P0CFCTCR,DCMIPP Pipe0 current flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame.,1: Capture requested for next frame." bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode - The received data are..,1: Snapshot mode (single frame) - Once activated.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P0CSCSTR,DCMIPP Pipe0 current stat/crop start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 words wide" line.long 0x8 "DCMIPP_P0CSCSZR,DCMIPP Pipe0 current stat/crop size register" bitfld.long 0x8 31. "ENABLE,Current value of the ENABLE bit" "0: Bypass. All data are computed if the statistics..,1: Enable: Depending on bit POSNEG value the.." bitfld.long 0x8 30. "POSNEG,Current value of the POSNEG bit" "0: Positive area. The rectangle defined by VSIZE..,1: Negative area. The active area is the area.." newline hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high." hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 word wide (data 32-bit)." rgroup.long 0x7C0++0xB line.long 0x0 "DCMIPP_P0CPPCR,DCMIPP Pipe0 current pixel packer configuration register" bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe0 is always..,1: Double buffer mode activated. Dump address.." bitfld.long 0x0 13.--15. "LINEMULT,Current amount of capture completed lines for LINE event and interrupt" "0: Event after every line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 11. "OELS,Current odd/even line select (ine select start)" "0: Interface captures the first line after the..,1: Interface captures the second line from the.." bitfld.long 0x0 10. "LSM,Current Line select mode" "0: Interface captures all received lines,1: Interface captures one line out of two" newline bitfld.long 0x0 9. "OEBS,Current odd/even byte select (byte select start)" "0: Interface captures the first data (byte or..,1: Interface captures the second data (byte or.." bitfld.long 0x0 7.--8. "BSM,Current Byte select mode" "0: Interface captures all received data,1: Interface captures one data out of two,2: Interface captures one byte out of four,3: Interface captures two bytes out of four" newline bitfld.long 0x0 6. "HEADEREN,Current CSI header dump enable" "0: CSI-2 headers are not dumped.,1: CSI-2 headers are dumped as a 32-bit words." bitfld.long 0x0 5. "PAD,Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment" "0: Aligns on LSB (and pads null bits on MSB) for..,1: Aligns on MSB (and pads null bits on LSB) for.." newline bitfld.long 0x0 0. "SWAPYUV,Swaps within a 32-bit word byte 0 vs. 1 and byte 2 vs. 3. It corresponds for YUV422 pixels formats to swap between UYVY and YUYV." "0: Outputs the provided words as described in..,1: Swaps the bytes from provided words byte 0 vs. 1.." line.long 0x4 "DCMIPP_P0CPPM0AR1,DCMIPP Pipe0 current pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P0CPPM0AR2,DCMIPP Pipe0 current pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" group.long 0x804++0x3 line.long 0x0 "DCMIPP_P1FSCR,DCMIPP Pipe1 flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Activation of PipeN" "0: Pipe disabled,1: Pipe enabled can start capturing with CPTMODE.." bitfld.long 0x0 30. "FDTFEN,Force Datatype format enable." "0: Disable force Datatype format. The Datatype..,?" newline hexmask.long.byte 0x0 24.--29. 1. "FDTF,Force Datatype format." bitfld.long 0x0 19.--20. "VC,Flow selection mode" "0,1,2,3" newline bitfld.long 0x0 18. "PIPEDIFF,Differentiates Pipe2 from Pipe1" "0: Pipe2 receives the same data as Pipe1 (Ie data..,1: Pipe1 gets pixels from only VC and DT configured.." bitfld.long 0x0 16.--17. "DTMODE,Flow selection mode" "0: Only flow DTIDA from the selected virtual..,1: Flows DTIDA and/or DTIDB from the selected..,?,?" newline hexmask.long.byte 0x0 8.--13. 1. "DTIDB,Data type selection ID B" hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Data type selection ID A" group.long 0x820++0x7 line.long 0x0 "DCMIPP_P1SRCR,DCMIPP Pipe1 stat removal configuration register" bitfld.long 0x0 15. "CROPEN,Crop line enable" "0: No crop (all pixels are fed through),1: Crop" bitfld.long 0x0 12.--14. "FIRSTLINEDEL,Amount of first lines to delete when CROPEN = 1" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--11. 1. "LASTLINE,Amount of following lines to keep when CROPEN = 1. If LASTLINE = 0 all pixels after FIRSTLINEDEL are fed through." line.long 0x4 "DCMIPP_P1BPRCR,DCMIPP Pipe1 bad pixel removal control register" bitfld.long 0x4 1.--3. "STRENGTH,Strength (aggressiveness) of the bad pixel detection" "0: The filter is fairly tolerant: only a few pixels..,?,?,?,?,?,?,?" bitfld.long 0x4 0. "ENABLE,Bad pixel detection must be enabled only for raw Bayer flows as it corrupts RGB flows." "0: Bypass: bad pixel removal is not active all..,1: Enable: if bad pixel are detected they are.." rgroup.long 0x828++0x3 line.long 0x0 "DCMIPP_P1BPRSR,DCMIPP Pipe1 bad pixel removal status register" hexmask.long.word 0x0 0.--11. 1. "BADCNT,Amount of detected bad pixels" group.long 0x830++0x3 line.long 0x0 "DCMIPP_P1DECR,DCMIPP Pipe1 decimation register" bitfld.long 0x0 3.--4. "VDEC,Vertical decimation ratio" "0: All pixels are transmitted no vertical decimation,1: One line out of two transmitted (for raw Bayer..,?,?" bitfld.long 0x0 1.--2. "HDEC,Horizontal decimation ratio" "0: All pixels are transmitted no horizontal..,1: One line out of two transmitted (for raw Bayer..,?,?" newline bitfld.long 0x0 0. "ENABLE,None" "0: Bypass: decimation is not active all pixels are..,1: Enable: one pixel every 1 2 4 or 8 in H and V is.." group.long 0x840++0xB line.long 0x0 "DCMIPP_P1BLCCR,DCMIPP Pipe1 black level calibration control register" hexmask.long.byte 0x0 24.--31. 1. "BLCR,Black level calibration - Red" hexmask.long.byte 0x0 16.--23. 1. "BLCG,Black level calibration - Green" newline hexmask.long.byte 0x0 8.--15. 1. "BLCB,Black level calibration - Blue" bitfld.long 0x0 0. "ENABLE,Black level calibration" "0: Bypass: black level calibration is not active..,1: Enable: the BLC R G B are subtracted." line.long 0x4 "DCMIPP_P1EXCR1,DCMIPP Pipe1 exposure control register 1" bitfld.long 0x4 28.--30. "SHFR,Exposure shift - Red" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 20.--27. 1. "MULTR,Exposure multiplier - Red" newline bitfld.long 0x4 0. "ENABLE,Exposure control (multiplication and shift) of all red green and blue" "0: Bypass: exposure multiplier and shift are not..,1: Enable: the exposure multiplication and shift is.." line.long 0x8 "DCMIPP_P1EXCR2,DCMIPP Pipe1 exposure control register 2" bitfld.long 0x8 28.--30. "SHFG,Exposure shift - Green" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 20.--27. 1. "MULTG,Exposure multiplier - Green" newline bitfld.long 0x8 12.--14. "SHFB,Exposure shift - Blue" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 4.--11. 1. "MULTB,Exposure multiplier - Blue" group.long 0x850++0x13 line.long 0x0 "DCMIPP_P1ST1CR,DCMIPP Pipe1 statistics1 control register" bitfld.long 0x0 7. "MODE,Statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." bitfld.long 0x0 4.--6. "SRC,Statistics source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "BINS,Current bin definition" "0: All Pixels: Accu is incremented of Component if..,1: NoExt16: Accu is incremented of Component if 16..,?,?" bitfld.long 0x0 0. "ENABLE,None" "0: Disabled: statistics are not accumulated.,1: Enable: statistics are accumulated" line.long 0x4 "DCMIPP_P1ST2CR,DCMIPP Pipe1 statistics 2 control register" bitfld.long 0x4 7. "MODE,Statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." bitfld.long 0x4 4.--6. "SRC,Statistics source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "BINS,Bin definition" "0: AllPixels: Accu is incremented of Component if 0..,1: NoExt16: Accu is incremented of Component if 16..,?,?" bitfld.long 0x4 0. "ENABLE,None" "0: Disabled: statistics are not accumulated,1: Enabled: statistics are accumulated" line.long 0x8 "DCMIPP_P1ST3CR,DCMIPP Pipe1 statistics 3 control register" bitfld.long 0x8 7. "MODE,Statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." bitfld.long 0x8 4.--6. "SRC,Statistics source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 2.--3. "BINS,Bin definition" "0: AllPixels: Accu is incremented of Component if 0..,1: NoExt16: Accu is incremented of Component if 16..,?,?" bitfld.long 0x8 0. "ENABLE,None" "0: Disabled: statistics are not accumulated,1: Enabled: statistics are accumulated" line.long 0xC "DCMIPP_P1STSTR,DCMIPP Pipe1 statistics window start register" hexmask.long.word 0xC 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" hexmask.long.word 0xC 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P1STSZR,DCMIPP Pipe1 statistics window size register" bitfld.long 0x10 31. "CROPEN,None" "0: Bypass all pixels are used to compute the..,1: Enable only the rectangle defined by VSTART.." hexmask.long.word 0x10 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" newline hexmask.long.word 0x10 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" rgroup.long 0x864++0xB line.long 0x0 "DCMIPP_P1ST1SR,DCMIPP Pipe1 statistics 1 status register" hexmask.long.tbyte 0x0 0.--23. 1. "ACCU,Accumulation result divided by 256." line.long 0x4 "DCMIPP_P1ST2SR,DCMIPP Pipe1 statistics 2 status register" hexmask.long.tbyte 0x4 0.--23. 1. "ACCU,accumulation result divided by 256." line.long 0x8 "DCMIPP_P1ST3SR,DCMIPP Pipe1 statistics 3 status register" hexmask.long.tbyte 0x8 0.--23. 1. "ACCU,accumulation result divided by 256." group.long 0x870++0x3 line.long 0x0 "DCMIPP_P1DMCR,DCMIPP Pipe1 demosaicing configuration register" bitfld.long 0x0 28.--30. "EDGE,Strength of the edge detection" "0: No edge detection pure linear interpolation,?,?,?,?,?,?,?" bitfld.long 0x0 24.--26. "LINEH,Strength of the horizontal line detection" "0: No horizontal line detection pure linear..,?,?,?,?,?,?,?" newline bitfld.long 0x0 20.--22. "LINEV,Strength of the vertical line detection" "0: No vertical line detection pure linear..,?,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "PEAK,Strength of the peak detection" "0: No peak detection pure linear interpolation,?,?,?,?,?,?,?" newline bitfld.long 0x0 1.--2. "TYPE,Raw Bayer type" "0: RGGB,1: GRBG,2: GBRG,3: BGGR" bitfld.long 0x0 0. "ENABLE,None" "0: Bypass,1: Enable demosaicing" group.long 0x880++0x1B line.long 0x0 "DCMIPP_P1CCCR,DCMIPP Pipe1 ColorConv configuration register" bitfld.long 0x0 2. "CLAMP,Clamp the output samples" "0: Not activated (clamped to [0;255] by default),1: Activated depending on TYPE" bitfld.long 0x0 1. "TYPE,output samples type used while CLAMP is activated" "0: Clamped to [16;235] for Y and to [16;240] for U..,1: Clamped to [16;235] for R G and B" newline bitfld.long 0x0 0. "ENABLE,None" "0: ColorConv is bypassed,1: ColorConv is enabled" line.long 0x4 "DCMIPP_P1CCRR1,DCMIPP Pipe1 ColorConv red coefficient register 1" hexmask.long.word 0x4 16.--26. 1. "RG,Coefficient row 1 column 2 of the matrix" hexmask.long.word 0x4 0.--10. 1. "RR,Coefficient row 1 column 1 of the matrix" line.long 0x8 "DCMIPP_P1CCRR2,DCMIPP Pipe1 ColorConv red coefficient register 2" hexmask.long.word 0x8 16.--25. 1. "RA,Coefficient row 1 of the added column (signed integer value)" hexmask.long.word 0x8 0.--10. 1. "RB,Coefficient row 1 column 3 of the matrix" line.long 0xC "DCMIPP_P1CCGR1,DCMIPP Pipe1 ColorConv green coefficient register 1" hexmask.long.word 0xC 16.--26. 1. "GG,Coefficient row 2 column 2 of the matrix" hexmask.long.word 0xC 0.--10. 1. "GR,Coefficient row 2 column 1 of the matrix" line.long 0x10 "DCMIPP_P1CCGR2,DCMIPP Pipe1 ColorConv green coefficient register 2" hexmask.long.word 0x10 16.--25. 1. "GA,Coefficient row 2 of the added column (signed integer value)" hexmask.long.word 0x10 0.--10. 1. "GB,Coefficient row 2 column 3 of the matrix" line.long 0x14 "DCMIPP_P1CCBR1,DCMIPP Pipex ColorConv blue coefficient register 1" hexmask.long.word 0x14 16.--26. 1. "BG,Coefficient row 3 column 2 of the matrix" hexmask.long.word 0x14 0.--10. 1. "BR,Coefficient row 3 column 1 of the matrix" line.long 0x18 "DCMIPP_P1CCBR2,DCMIPP Pipe1 ColorConv blue coefficient register 2" hexmask.long.word 0x18 16.--25. 1. "BA,Coefficient row 3 of the added column (signed integer value)" hexmask.long.word 0x18 0.--10. 1. "BB,Coefficient row 3 column 3 of the matrix" group.long 0x8A0++0xB line.long 0x0 "DCMIPP_P1CTCR1,DCMIPP Pipe1 contrast control register 1" hexmask.long.byte 0x0 9.--14. 1. "LUM0,Luminance increase for input luminance of 0 (increase is idle with LUMx = 16)" bitfld.long 0x0 0. "ENABLE,None" "0: Bypass pixels are forwarded idle.,1: Enable contrast enhancement is applied on pixels." line.long 0x4 "DCMIPP_P1CTCR2,DCMIPP Pipe1 contrast control register 2" hexmask.long.byte 0x4 25.--30. 1. "LUM1,Luminance increase for input luminance of 32 (increase is idle with LUMx = 16)" hexmask.long.byte 0x4 17.--22. 1. "LUM2,Luminance increase for input luminance of 64 (increase is idle with LUMx = 16)" newline hexmask.long.byte 0x4 9.--14. 1. "LUM3,Luminance increase for input luminance of 96 (increase is idle with LUMx = 16)" hexmask.long.byte 0x4 1.--6. 1. "LUM4,Luminance increase for input luminance of 128 (increase is idle with LUMx = 16)" line.long 0x8 "DCMIPP_P1CTCR3,DCMIPP Pipe1 contrast control register 3" hexmask.long.byte 0x8 25.--30. 1. "LUM5,Luminance increase for input luminance of 160 (increase is idle with LUMx = 16)" hexmask.long.byte 0x8 17.--22. 1. "LUM6,Luminance increase for input luminance of 192 (increase is idle with LUMx = 16)" newline hexmask.long.byte 0x8 9.--14. 1. "LUM7,Luminance increase for input luminance of 224 (increase is idle with LUMx = 16)" hexmask.long.byte 0x8 1.--6. 1. "LUM8,Luminance increase for input luminance of 256 (increase is idle with LUMx = 16)" group.long 0x900++0x1B line.long 0x0 "DCMIPP_P1FCTCR,DCMIPP Pipex flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame,1: Capture requested for next frame" bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode. The received data are..,1: Snapshot mode (single frame). Once activated the.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P1CRSTR,DCMIPP Pipex crop window start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P1CRSZR,DCMIPP Pipex crop window size register" bitfld.long 0x8 31. "ENABLE,None" "0: Bypass all pixels are transmitted through (no..,1: Enable only the rectangle defined by VSIZE HSIZE.." hexmask.long.word 0x8 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high. If the value is maintained at 0 when enabling the crop thanks to the ENABLE bit the value is forced internally at 0xFFE which is the maximum value." newline hexmask.long.word 0x8 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide. If the value is maintained at 0 when enabling the crop by means of the ENABLE bit the value is forced internally at 0xFFE which is the maximum value." line.long 0xC "DCMIPP_P1DCCR,DCMIPP Pipex decimation register" bitfld.long 0xC 3.--4. "VDEC,Vertical decimation ratio" "0: All pixels are transmitted no vertical decimation,1: One line out of two transmitted,?,?" bitfld.long 0xC 1.--2. "HDEC,Horizontal decimation ratio" "0: All pixels are transmitted no horizontal..,1: One line out of two transmitted,?,?" newline bitfld.long 0xC 0. "ENABLE,None" "0: Bypass: decimation is not active all pixels are..,1: Enable: one pixel every 1 2 4 or 8 in H and V is.." line.long 0x10 "DCMIPP_P1DSCR,DCMIPP Pipex downsize configuration register" bitfld.long 0x10 31. "ENABLE,None" "0: Down scaler is bypassed,1: Down scaler is enabled" hexmask.long.word 0x10 16.--25. 1. "VDIV,Vertical division factor from 128 (8x) to 1023 (1x)" newline hexmask.long.word 0x10 0.--9. 1. "HDIV,Horizontal division factor from 128 (8x) to 1023 (1x)" line.long 0x14 "DCMIPP_P1DSRTIOR,DCMIPP Pipex downsize ratio register" hexmask.long.word 0x14 16.--31. 1. "VRATIO,Vertical ratio from 8192 (1x) to 65535 (8x)" hexmask.long.word 0x14 0.--15. 1. "HRATIO,Horizontal ratio from 8192 (1x) to 65535 (8x)" line.long 0x18 "DCMIPP_P1DSSZR,DCMIPP Pipex downsize destination size register" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" group.long 0x920++0x43 line.long 0x0 "DCMIPP_P1CMRICR,DCMIPP Pipex common ROI configuration register" bitfld.long 0x0 23. "ROI8EN,Region of interest 8 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 22. "ROI7EN,Region of interest 7 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 21. "ROI6EN,Region of interest 6 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 20. "ROI5EN,Region of interest 5 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 19. "ROI4EN,Region of interest 4 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 18. "ROI3EN,Region of interest 3 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 17. "ROI2EN,Region of interest 2 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 16. "ROI1EN,Region of interest 1 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 0.--1. "ROILSZ,Region of interest line size width" "0: Line width 1 pixel,1: Line width 2 pixels,2: Line width 4 pixels,3: Line width 8 pixels" line.long 0x4 "DCMIPP_P1RI1CR1,DCMIPP Pipe1 ROI1 configuration register 1" bitfld.long 0x4 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x4 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x4 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P1RI1CR2,DCMIPP Pipe1 ROI1 configuration register 2" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0xC "DCMIPP_P1RI2CR1,DCMIPP Pipe1 ROI2 configuration register 1" bitfld.long 0xC 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0xC 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0xC 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0xC 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0xC 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P1RI2CR2,DCMIPP Pipe1 ROI2 configuration register 2" hexmask.long.word 0x10 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x10 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x14 "DCMIPP_P1RI3CR1,DCMIPP Pipe1 ROI3 configuration register 1" bitfld.long 0x14 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x14 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x14 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x14 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x18 "DCMIPP_P1RI3CR2,DCMIPP Pipe1 ROI3 configuration register 2" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x1C "DCMIPP_P1RI4CR1,DCMIPP Pipe1 ROI4 configuration register 1" bitfld.long 0x1C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x1C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x1C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x1C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x1C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x20 "DCMIPP_P1RI4CR2,DCMIPP Pipe1 ROI4 configuration register 2" hexmask.long.word 0x20 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x20 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x24 "DCMIPP_P1RI5CR1,DCMIPP Pipe1 ROI5 configuration register 1" bitfld.long 0x24 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x24 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x24 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x24 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x24 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x28 "DCMIPP_P1RI5CR2,DCMIPP Pipe1 ROI5 configuration register 2" hexmask.long.word 0x28 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x28 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x2C "DCMIPP_P1RI6CR1,DCMIPP Pipe1 ROI6 configuration register 1" bitfld.long 0x2C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x2C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x2C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x2C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x2C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x30 "DCMIPP_P1RI6CR2,DCMIPP Pipe1 ROI6 configuration register 2" hexmask.long.word 0x30 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x30 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x34 "DCMIPP_P1RI7CR1,DCMIPP Pipe1 ROI7 configuration register 1" bitfld.long 0x34 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x34 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x34 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x34 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x34 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x38 "DCMIPP_P1RI7CR2,DCMIPP Pipe1 ROI7 configuration register 2" hexmask.long.word 0x38 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x38 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x3C "DCMIPP_P1RI8CR1,DCMIPP Pipe1 ROI8 configuration register 1" bitfld.long 0x3C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x3C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x3C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x3C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x3C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x40 "DCMIPP_P1RI8CR2,DCMIPP Pipe1 ROI8 configuration register 2" hexmask.long.word 0x40 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x40 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" group.long 0x970++0x3 line.long 0x0 "DCMIPP_P1GMCR,DCMIPP Pipex gamma configuration register" bitfld.long 0x0 0. "ENABLE,None" "0: Gamma is bypassed,1: Gamma is enabled" group.long 0x980++0x1B line.long 0x0 "DCMIPP_P1YUVCR,DCMIPP Pipe1 YUVConv configuration register" bitfld.long 0x0 2. "CLAMP,Clamp the output samples" "0: Not activated (clamped to [0;255] by default),1: Activated depending on TYPE" bitfld.long 0x0 1. "TYPE,Output samples type used while CLAMP is activated" "0: Clamped to [16;235] for Y and to [16;240] for U..,1: Clamped to [16;235] for R G and B" newline bitfld.long 0x0 0. "ENABLE,None" "0: ColorConv is bypassed,1: ColorConv is enabled" line.long 0x4 "DCMIPP_P1YUVRR1,DCMIPP Pipe1 YUVConv red coefficient register 1" hexmask.long.word 0x4 16.--26. 1. "RG,Coefficient row 1 column 2 of the matrix" hexmask.long.word 0x4 0.--10. 1. "RR,Coefficient row 1 column 1 of the matrix" line.long 0x8 "DCMIPP_P1YUVRR2,DCMIPP Pipe1 YUVConv red coefficient register 2" hexmask.long.word 0x8 16.--25. 1. "RA,Coefficient row 1 of the added column (signed integer value)" hexmask.long.word 0x8 0.--10. 1. "RB,Coefficient row 1 column 3 of the matrix" line.long 0xC "DCMIPP_P1YUVGR1,DCMIPP Pipe1 YUVConv green coefficient register 1" hexmask.long.word 0xC 16.--26. 1. "GG,Coefficient row 2 column 2 of the matrix" hexmask.long.word 0xC 0.--10. 1. "GR,Coefficient row 2 column 1 of the matrix" line.long 0x10 "DCMIPP_P1YUVGR2,DCMIPP Pipe1 YUVConv green coefficient register 2" hexmask.long.word 0x10 16.--25. 1. "GA,Coefficient row 2 of the added column (signed integer value)" hexmask.long.word 0x10 0.--10. 1. "GB,Coefficient row 2 column 3 of the matrix" line.long 0x14 "DCMIPP_P1YUVBR1,DCMIPP Pipe1 YUVConv blue coefficient register 1" hexmask.long.word 0x14 16.--26. 1. "BG,Coefficient row 3 column 2 of the matrix" hexmask.long.word 0x14 0.--10. 1. "BR,Coefficient row 3 column 1 of the matrix" line.long 0x18 "DCMIPP_P1YUVBR2,DCMIPP Pipe1 YUV blue coefficient register 2" hexmask.long.word 0x18 16.--25. 1. "BA,Coefficient row 3 of the added column (signed integer value)" hexmask.long.word 0x18 0.--10. 1. "BB,Coefficient row 3 column 3 of the matrix" group.long 0x9C0++0xF line.long 0x0 "DCMIPP_P1PPCR,DCMIPP Pipe1 pixel packer configuration register" bitfld.long 0x0 20. "LMAWE,Line multi address wrapping enable bit." "0: Line multi address wrapping disabled.,1: Line multi address wrapping enabled." bitfld.long 0x0 17.--19. "LMAWM,Line multi address wrapping modulo." "0: Wraps address after every line,1: Wraps address after two lines,2: Wraps address after four lines,3: Wraps address after eight lines,4: Wraps address after sixteen lines,5: Wraps address after 32 lines,6: Wraps address after 64 lines,7: Wraps address after 128 lines" newline bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe1 always..,1: Double buffer mode activated. Output pixels.." bitfld.long 0x0 13.--15. "LINEMULT,Amount of capture completed lines for LINE Event and Interrupt" "0: Event after one line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 4. "SWAPRB,Swaps R-vs-B components if RGB and U-vs-V components if YUV" "0: No swap of R-vs-B (U-vs-V),1: Swap active" hexmask.long.byte 0x0 0.--3. 1. "FORMAT,Memory format" line.long 0x4 "DCMIPP_P1PPM0AR1,DCMIPP Pipe1 pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P1PPM0AR2,DCMIPP Pipe1 pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" line.long 0xC "DCMIPP_P1PPM0PR,DCMIPP Pipex pixel packer Memory0 pitch register" hexmask.long.word 0xC 0.--14. 1. "PITCH,Number of bytes between the address of two consecutive lines." rgroup.long 0x9D0++0x3 line.long 0x0 "DCMIPP_P1STM0AR,DCMIPP Pipex status Memory0 address register" hexmask.long 0x0 0.--31. 1. "M0A,Memory0 address" group.long 0x9D4++0xB line.long 0x0 "DCMIPP_P1PPM1AR1,DCMIPP Pipex pixel packer Memory1 address register 1" hexmask.long 0x0 0.--31. 1. "M1A,Memory1 address" line.long 0x4 "DCMIPP_P1PPM1AR2,DCMIPP Pipex pixel packer Memory1 address register 2" hexmask.long 0x4 0.--31. 1. "M1A,Memory1 address" line.long 0x8 "DCMIPP_P1PPM1PR,DCMIPP Pipex pixel packer Memory1 pitch register" hexmask.long.word 0x8 0.--14. 1. "PITCH,Number of bytes between the address of two consecutive lines." rgroup.long 0x9E0++0x3 line.long 0x0 "DCMIPP_P1STM1AR,DCMIPP Pipex status Memory1 address register" hexmask.long 0x0 0.--31. 1. "M1A,Memory1 address" group.long 0x9E4++0x7 line.long 0x0 "DCMIPP_P1PPM2AR1,DCMIPP Pipex pixel packer memory2 address register 1" hexmask.long 0x0 0.--31. 1. "M2A,Memory 2 address" line.long 0x4 "DCMIPP_P1PPM2AR2,DCMIPP Pipex pixel packer memory2 address register 2" hexmask.long 0x4 0.--31. 1. "M2A,Memory 2 address" rgroup.long 0x9F0++0x3 line.long 0x0 "DCMIPP_P1STM2AR,DCMIPP Pipex status Memory2 address register" hexmask.long 0x0 0.--31. 1. "M2A,Memory2 address" group.long 0x9F4++0x3 line.long 0x0 "DCMIPP_P1IER,DCMIPP Pipe1 interrupt enable register" bitfld.long 0x0 7. "OVRIE,Overrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the AXI master is.." bitfld.long 0x0 2. "VSYNCIE,VSYNC interrupt enable" "0: No interrupt generation,1: An interrupt is generated on each VSYNC.." newline bitfld.long 0x0 1. "FRAMEIE,Frame capture completed interrupt enable" "0: No interrupt generation,1: An interrupt is generated after the full capture.." bitfld.long 0x0 0. "LINEIE,Multi-line capture completed interrupt enable" "0: No interrupt generation when the line is received,1: An interrupt is generated after the full capture.." rgroup.long 0x9F8++0x3 line.long 0x0 "DCMIPP_P1SR,DCMIPP Pipe1 status register" bitfld.long 0x0 23. "CPTACT,Capture immediate status" "0: Capture currently inactive,1: Capture currently active" bitfld.long 0x0 17. "LSTFRM,Last frame LSB bit sampled at frame capture complete event. The information is extracted from the frame data number which can be delivered by the camera through the CSI2 interface." "0,1" newline bitfld.long 0x0 16. "LSTLINE,Last line LSB bit sampled at frame capture complete event." "0,1" bitfld.long 0x0 7. "OVRF,Overrun raw interrupt status" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.." newline bitfld.long 0x0 2. "VSYNCF,VSYNC raw interrupt status" "0,1" bitfld.long 0x0 1. "FRAMEF,Frame capture completed raw interrupt status" "0: No capture or ongoing capture,1: All data of a frame have been captured." newline bitfld.long 0x0 0. "LINEF,Multi-line capture completed raw interrupt status" "0,1" wgroup.long 0x9FC++0x3 line.long 0x0 "DCMIPP_P1FCR,DCMIPP Pipe1 interrupt clear register" bitfld.long 0x0 7. "COVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 2. "CVSYNCF,Vertical synchronization interrupt status clear" "0,1" newline bitfld.long 0x0 1. "CFRAMEF,Frame capture complete interrupt status clear" "0,1" bitfld.long 0x0 0. "CLINEF,Multi-line capture complete interrupt status clear" "0,1" rgroup.long 0xA04++0x3 line.long 0x0 "DCMIPP_P1CFSCR,DCMIPP Pipe1 current flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Current activation of PipeN" "0: Pipe disabled,1: Pipe enabled can start capturing with CPTMODE.." bitfld.long 0x0 30. "FDTFEN,Current force data type format enable" "0: Disable force data type format. The data type..,1: Enable force data type format. When the data.." newline hexmask.long.byte 0x0 24.--29. 1. "FDTF,Current force data type format" bitfld.long 0x0 19.--20. "VC,Current flow selection mode" "0,1,2,3" newline bitfld.long 0x0 18. "PIPEDIFF,Current differentiates Pipe2 vs. Pipe1" "0: Pipe2 gets Pipe1 pixels after their processing..,1: Pipe1 gets pixels from only VC/DTID configured.." bitfld.long 0x0 16.--17. "DTMODE,Flow selection mode" "0: Only flow DTID A from the selected virtual..,1: Flows DTIDA and DTIDB from the selected virtual..,?,?" newline hexmask.long.byte 0x0 8.--13. 1. "DTIDB,Current data type ID B" hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Current data type ID A" rgroup.long 0xA24++0x3 line.long 0x0 "DCMIPP_P1CBPRCR,DCMIPP Pipe1 current bad pixel removal register" bitfld.long 0x0 1.--3. "STRENGTH,Current strength (aggressiveness) of the bad pixel detection:" "0: the filter is fairly tolerant: only a few pixels..,?,?,?,?,?,?,?" bitfld.long 0x0 0. "ENABLE,Current status of enable bit" "0: Bypass: bad pixel removal is not active all..,1: Enable: if bad pixel are detected they are.." rgroup.long 0xA40++0xB line.long 0x0 "DCMIPP_P1CBLCCR,DCMIPP Pipe1 current black level calibration control register" hexmask.long.byte 0x0 24.--31. 1. "BLCR,Current black level calibration - Red" hexmask.long.byte 0x0 16.--23. 1. "BLCG,Current black level calibration - Green" newline hexmask.long.byte 0x0 8.--15. 1. "BLCB,Current black level calibration - Blue" bitfld.long 0x0 0. "ENABLE,For current black level calibration" "0: Bypass: black level calibration is not active..,1: Enable: the BLCR G B are subtracted." line.long 0x4 "DCMIPP_P1CEXCR1,DCMIPP Pipe1 current exposure control register 1" bitfld.long 0x4 28.--30. "SHFR,Current exposure shift - Red" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 20.--27. 1. "MULTR,Current exposure multiplier - Red" newline bitfld.long 0x4 0. "ENABLE,for exposure control (multiplication and shift)" "0: Bypass: exposure multiplier and shift are not..,1: Enable: the exposure multiplication and shift is.." line.long 0x8 "DCMIPP_P1CEXCR2,DCMIPP Pipe1 current exposure control register 2" bitfld.long 0x8 28.--30. "SHFG,Current exposure shift - Green" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 20.--27. 1. "MULTG,Current exposure multiplier - Green" newline bitfld.long 0x8 12.--14. "SHFB,Current exposure shift - Blue" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 4.--11. 1. "MULTB,Current exposure multiplier - Blue" rgroup.long 0xA50++0x13 line.long 0x0 "DCMIPP_P1CST1CR,DCMIPP Pipe1 current statistics 1 control register" hexmask.long.tbyte 0x0 8.--31. 1. "ACCU,Current accumulation result divided by 256." bitfld.long 0x0 7. "MODE,Current statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." newline bitfld.long 0x0 4.--6. "SRC,Current source of statistics" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "BINS,Current bin definition" "0: AllPixels: Accu is incremented of Component if 0..,1: NoExt16: Accu is incremented of Component if 16..,?,?" newline bitfld.long 0x0 0. "ENABLE,Current enable bit value" "0: Disabled: statistics are not accumulated.,1: Enable: statistics are accumulated" line.long 0x4 "DCMIPP_P1CST2CR,DCMIPP Pipe1 current statistics 2 control register" hexmask.long.tbyte 0x4 8.--31. 1. "ACCU,Accumulation result divided by 256." bitfld.long 0x4 7. "MODE,Statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." newline bitfld.long 0x4 4.--6. "SRC,Statistics source" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "BINS,Bin definition" "0: AllPixels: Accu is incremented of Component if 0..,1: NoExt16: Accu is incremented of Component if 16..,?,?" newline bitfld.long 0x4 0. "ENABLE,None" "0: Disabled: statistics are not accumulated.,1: Enable: statistics are accumulated" line.long 0x8 "DCMIPP_P1CST3CR,DCMIPP Pipe1 current statistics 3 control register" hexmask.long.tbyte 0x8 8.--31. 1. "ACCU,Accumulation result divided by 256." bitfld.long 0x8 7. "MODE,Statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." newline bitfld.long 0x8 4.--6. "SRC,Statistics source" "0,1,2,3,4,5,6,7" bitfld.long 0x8 2.--3. "BINS,Current bin definition" "0: AllPixels: Accu is incremented of Component if 0..,1: NoExt16: Accu is incremented of Component if 16..,?,?" newline bitfld.long 0x8 0. "ENABLE,None" "0: Disabled: statistics are not accumulated.,1: Enable: statistics are accumulated" line.long 0xC "DCMIPP_P1CSTSTR,DCMIPP Pipe1 current statistics window start register" hexmask.long.word 0xC 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" hexmask.long.word 0xC 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P1CSTSZR,DCMIPP Pipe1 current statistics window size register" bitfld.long 0x10 31. "CROPEN,Current CROPEN bit value" "0: Bypass all pixels are used to compute the..,1: Enable only the rectangle defined by VSTART.." hexmask.long.word 0x10 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" newline hexmask.long.word 0x10 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" rgroup.long 0xA80++0x1B line.long 0x0 "DCMIPP_P1CCCCR,DCMIPP Pipe1 current ColorConv configuration register" bitfld.long 0x0 2. "CLAMP,Clamp the output samples" "0: Not activated (clamped to [0;255] by default),1: Activated depending on TYPE" bitfld.long 0x0 1. "TYPE,Output samples type used while CLAMP is activated" "0: clamped to [16;235] for Y and to [16;240] for U..,1: clamped to [16;235] for R G and B" newline bitfld.long 0x0 0. "ENABLE,Current value applied" "0: ColorConv is bypassed,1: ColorConv is enabled" line.long 0x4 "DCMIPP_P1CCCRR1,DCMIPP Pipe1 current ColorConv red coefficient register 1" hexmask.long.word 0x4 16.--26. 1. "RG,Current coefficient row 1 column 2 of the matrix" hexmask.long.word 0x4 0.--10. 1. "RR,Current coefficient row 1 column 1 of the matrix" line.long 0x8 "DCMIPP_P1CCCRR2,DCMIPP Pipe1 current ColorConv red coefficient register 2" hexmask.long.word 0x8 16.--25. 1. "RA,Current coefficient row 1 of the added column (signed integer value)" hexmask.long.word 0x8 0.--10. 1. "RB,Current coefficient row 1 column 3 of the matrix" line.long 0xC "DCMIPP_P1CCCGR1,DCMIPP Pipe1 current ColorConv green coefficient register 1" hexmask.long.word 0xC 16.--26. 1. "GG,Current coefficient row 2 column 2 of the matrix" hexmask.long.word 0xC 0.--10. 1. "GR,Current coefficient row 2 column 1 of the matrix" line.long 0x10 "DCMIPP_P1CCCGR2,DCMIPP Pipe1 current ColorConv green coefficient register 2" hexmask.long.word 0x10 16.--25. 1. "GA,Current coefficient row 2 of the added column (signed integer value)" hexmask.long.word 0x10 0.--10. 1. "GB,Current coefficient row 2 column 3 of the matrix" line.long 0x14 "DCMIPP_P1CCCBR1,DCMIPP Pipex current ColorConv blue coefficient register 1" hexmask.long.word 0x14 16.--26. 1. "BG,Current coefficient row 3 column 2 of the matrix" hexmask.long.word 0x14 0.--10. 1. "BR,Current coefficient row 3 column 1 of the matrix" line.long 0x18 "DCMIPP_P1CCCBR2,DCMIPP Pipe1 current ColorConv blue coefficient register 2" hexmask.long.word 0x18 16.--25. 1. "BA,Current coefficient row 3 of the added column (signed integer value)" hexmask.long.word 0x18 0.--10. 1. "BB,Current coefficient row 3 column 3 of the matrix" rgroup.long 0xAA0++0xB line.long 0x0 "DCMIPP_P1CCTCR1,DCMIPP Pipe1 current contrast control register 1" hexmask.long.byte 0x0 9.--14. 1. "LUM0,Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16)" bitfld.long 0x0 0. "ENABLE,Current ENABLE bit value" "0: Bypass pixels are forwarded idle.,1: Enable contrast enhancement is applied on pixels." line.long 0x4 "DCMIPP_P1CCTCR2,DCMIPP Pipe1 current contrast control register 2" hexmask.long.byte 0x4 25.--30. 1. "LUM1,Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16)" hexmask.long.byte 0x4 17.--22. 1. "LUM2,Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16)" newline hexmask.long.byte 0x4 9.--14. 1. "LUM3,Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16)" hexmask.long.byte 0x4 1.--6. 1. "LUM4,Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16)" line.long 0x8 "DCMIPP_P1CCTCR3,DCMIPP Pipe1 current contrast control register 3" hexmask.long.byte 0x8 25.--30. 1. "LUM5,Luminance increase for input luminance of 160 (increase is idle with LUMx = 16)" hexmask.long.byte 0x8 17.--22. 1. "LUM6,Luminance increase for input luminance of 192 (increase is idle with LUMx = 16)" newline hexmask.long.byte 0x8 9.--14. 1. "LUM7,Luminance increase for input luminance of 224 (increase is idle with LUMx = 16)" hexmask.long.byte 0x8 1.--6. 1. "LUM8,Luminance increase for input luminance of 256 (increase is idle with LUMx = 16)" rgroup.long 0xB00++0xB line.long 0x0 "DCMIPP_P1CFCTCR,DCMIPP Pipex current flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame.,1: Capture requested for next frame." bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode - Received data are..,1: Snapshot mode (single frame) - Once activated.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P1CCRSTR,DCMIPP Pipex current crop window start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P1CCRSZR,DCMIPP Pipex current crop window size register" bitfld.long 0x8 31. "ENABLE,Current ENABLE bit value." "0: Bypass all pixels are transmitted through (no..,1: Enable only the rectangle defined by VSIZE HSIZE.." hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" newline hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" group.long 0xB0C++0x3 line.long 0x0 "DCMIPP_P1CDCCR,DCMIPP Pipex current decimation register" bitfld.long 0x0 3.--4. "VDEC,Vertical decimation ratio" "0: All pixels are transmitted no vertical decimation,1: One line out of two transmitted,?,?" bitfld.long 0x0 1.--2. "HDEC,Horizontal decimation ratio" "0: All pixels are transmitted no horizontal..,1: One line out of two transmitted,?,?" newline bitfld.long 0x0 0. "ENABLE,None" "0: Bypass: decimation is not active all pixels are..,1: Enable: one pixel every 1 2 4 or 8 in H and V is.." rgroup.long 0xB10++0xB line.long 0x0 "DCMIPP_P1CDSCR,DCMIPP Pipex current downsize configuration register" bitfld.long 0x0 31. "ENABLE,Current value of bit ENABLE" "0: Down scaler is bypassed,1: Down scaler is enabled" hexmask.long.word 0x0 16.--25. 1. "VDIV,Current vertical division factor from 128 (8x) to 1023 (1x)" newline hexmask.long.word 0x0 0.--9. 1. "HDIV,Current horizontal division factor from 128 (8x) to 1023 (1x)" line.long 0x4 "DCMIPP_P1CDSRTIOR,DCMIPP Pipex current downsize ratio register" hexmask.long.word 0x4 16.--31. 1. "VRATIO,Current vertical ratio from 8192 (1x) to 65535 (8x)" hexmask.long.word 0x4 0.--15. 1. "HRATIO,Current horizontal ratio from 8192 (1x) to 65535 (8x)" line.long 0x8 "DCMIPP_P1CDSSZR,DCMIPP Pipex current downsize destination size register" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" rgroup.long 0xB20++0x43 line.long 0x0 "DCMIPP_P1CCMRICR,DCMIPP Pipex current common ROI configuration register" bitfld.long 0x0 23. "ROI8EN,Current region of interest 8 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 22. "ROI7EN,Current region of interest 7 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 21. "ROI6EN,Current region of interest 6 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 20. "ROI5EN,Current region of interest 5 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 19. "ROI4EN,Current region of interest 4 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 18. "ROI3EN,Current region of interest 3 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 17. "ROI2EN,Current region of interest 2 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 16. "ROI1EN,Current region of interest 1 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 0.--1. "ROILSZ,Current region of interest line size width" "0: Line width 1 pixel,1: Line width 2 pixels,2: Line width 4 pixels,3: Line width 8 pixels" line.long 0x4 "DCMIPP_P1CRI1CR1,DCMIPP Pipe1 current ROI1 configuration register 1" bitfld.long 0x4 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x4 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x4 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P1CRI1CR2,DCMIPP Pipe1 current ROI1 configuration register 2" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0xC "DCMIPP_P1CRI2CR1,DCMIPP Pipe1 current ROI2 configuration register 1" bitfld.long 0xC 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0xC 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0xC 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0xC 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0xC 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P1CRI2CR2,DCMIPP Pipe1 current ROI2 configuration register 2" hexmask.long.word 0x10 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x10 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x14 "DCMIPP_P1CRI3CR1,DCMIPP Pipe1 current ROI3 configuration register 1" bitfld.long 0x14 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x14 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x14 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x14 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x18 "DCMIPP_P1CRI3CR2,DCMIPP Pipe1 current ROI3 configuration register 2" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x1C "DCMIPP_P1CRI4CR1,DCMIPP Pipe1 current ROI4 configuration register 1" bitfld.long 0x1C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x1C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x1C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x1C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x1C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x20 "DCMIPP_P1CRI4CR2,DCMIPP Pipe1 current ROI4 configuration register 2" hexmask.long.word 0x20 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x20 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x24 "DCMIPP_P1CRI5CR1,DCMIPP Pipe1 current ROI5 configuration register 1" bitfld.long 0x24 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x24 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x24 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x24 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x24 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x28 "DCMIPP_P1CRI5CR2,DCMIPP Pipe1 current ROI5 configuration register 2" hexmask.long.word 0x28 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x28 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x2C "DCMIPP_P1CRI6CR1,DCMIPP Pipe1 current ROI6 configuration register 1" bitfld.long 0x2C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x2C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x2C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x2C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x2C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x30 "DCMIPP_P1CRI6CR2,DCMIPP Pipe1 current ROI6 configuration register 2" hexmask.long.word 0x30 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x30 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x34 "DCMIPP_P1CRI7CR1,DCMIPP Pipe1 current ROI7 configuration register 1" bitfld.long 0x34 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x34 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x34 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x34 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x34 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x38 "DCMIPP_P1CRI7CR2,DCMIPP Pipe1 current ROI7 configuration register 2" hexmask.long.word 0x38 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x38 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x3C "DCMIPP_P1CRI8CR1,DCMIPP Pipe1 current ROI8 configuration register 1" bitfld.long 0x3C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x3C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x3C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x3C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x3C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x40 "DCMIPP_P1CRI8CR2,DCMIPP Pipe1 current ROI8 configuration register 2" hexmask.long.word 0x40 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x40 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" rgroup.long 0xBC0++0xF line.long 0x0 "DCMIPP_P1CPPCR,DCMIPP Pipe1 current pixel packer configuration register" bitfld.long 0x0 20. "LMAWE,Line multi address wrapping enable bit" "0: Line multi address wrapping disabled.,1: Line multi address wrapping enabled." bitfld.long 0x0 17.--19. "LMAWM,Line multi address wrapping modulo" "0: Wraps address after every line,1: Wraps address after two lines,2: Wraps address after four lines,3: Wraps address after eight lines,4: Wraps address after sixteen lines,5: Wraps address after 32 lines,6: Wraps address after 64 lines,7: Wraps address after 128 lines" newline bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe1 always..,1: Double buffer mode activated. Output pixels.." bitfld.long 0x0 13.--15. "LINEMULT,Amount of capture completed lines for LINE Event and Interrupt" "0: Event after one line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 4. "SWAPRB,Swaps R-vs-B components if RGB and U-vs-V components if YUV" "0: No swap of R-vs-B (U-vs-V),1: Swap active" hexmask.long.byte 0x0 0.--3. 1. "FORMAT,Memory format" line.long 0x4 "DCMIPP_P1CPPM0AR1,DCMIPP Pipe1 current pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P1CPPM0AR2,DCMIPP Pipe1 current pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" line.long 0xC "DCMIPP_P1CPPM0PR,DCMIPP Pipex current pixel packer Memory0 pitch register" hexmask.long.word 0xC 0.--14. 1. "PITCH,Current number of bytes between the address of two consecutive lines." rgroup.long 0xBD4++0xB line.long 0x0 "DCMIPP_P1CPPM1AR1,DCMIPP Pipex current pixel packer Memory1 address register 1" hexmask.long 0x0 0.--31. 1. "M1A,Memory1 address" line.long 0x4 "DCMIPP_P1CPPM1AR2,DCMIPP Pipex current pixel packer Memory1 address register 2" hexmask.long 0x4 0.--31. 1. "M1A,Memory1 address" line.long 0x8 "DCMIPP_P1CPPM1PR,DCMIPP Pipex current pixel packer Memory1 pitch register" hexmask.long.word 0x8 0.--14. 1. "PITCH,Current number of bytes between the address of two consecutive lines" rgroup.long 0xBE4++0x7 line.long 0x0 "DCMIPP_P1CPPM2AR1,DCMIPP Pipex current pixel packer Memory2 address register 1" hexmask.long 0x0 0.--31. 1. "M2A,Memory 2 address" line.long 0x4 "DCMIPP_P1CPPM2AR2,DCMIPP Pipex current pixel packer Memory2 address register 1" hexmask.long 0x4 0.--31. 1. "M2A,Memory 2 address" group.long 0xC04++0x3 line.long 0x0 "DCMIPP_P2FSCR,DCMIPP Pipe2 flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Activation of PipeN" "0: PipeN disabled,1: PipeN enabled can start capturing with CPTMODE.." bitfld.long 0x0 30. "FDTFEN,Force data type format enable" "0: Disable force data type format. The data type..,1: Enable force data type format. When the data.." newline hexmask.long.byte 0x0 24.--29. 1. "FDTF,Force data type format" bitfld.long 0x0 19.--20. "VC,Flow selection mode" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Data type ID" group.long 0xD00++0x1B line.long 0x0 "DCMIPP_P2FCTCR,DCMIPP Pipex flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame,1: Capture requested for next frame" bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode. The received data are..,1: Snapshot mode (single frame). Once activated the.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P2CRSTR,DCMIPP Pipex crop window start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P2CRSZR,DCMIPP Pipex crop window size register" bitfld.long 0x8 31. "ENABLE,None" "0: Bypass all pixels are transmitted through (no..,1: Enable only the rectangle defined by VSIZE HSIZE.." hexmask.long.word 0x8 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high. If the value is maintained at 0 when enabling the crop thanks to the ENABLE bit the value is forced internally at 0xFFE which is the maximum value." newline hexmask.long.word 0x8 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide. If the value is maintained at 0 when enabling the crop by means of the ENABLE bit the value is forced internally at 0xFFE which is the maximum value." line.long 0xC "DCMIPP_P2DCCR,DCMIPP Pipex decimation register" bitfld.long 0xC 3.--4. "VDEC,Vertical decimation ratio" "0: All pixels are transmitted no vertical decimation,1: One line out of two transmitted,?,?" bitfld.long 0xC 1.--2. "HDEC,Horizontal decimation ratio" "0: All pixels are transmitted no horizontal..,1: One line out of two transmitted,?,?" newline bitfld.long 0xC 0. "ENABLE,None" "0: Bypass: decimation is not active all pixels are..,1: Enable: one pixel every 1 2 4 or 8 in H and V is.." line.long 0x10 "DCMIPP_P2DSCR,DCMIPP Pipex downsize configuration register" bitfld.long 0x10 31. "ENABLE,None" "0: Down scaler is bypassed,1: Down scaler is enabled" hexmask.long.word 0x10 16.--25. 1. "VDIV,Vertical division factor from 128 (8x) to 1023 (1x)" newline hexmask.long.word 0x10 0.--9. 1. "HDIV,Horizontal division factor from 128 (8x) to 1023 (1x)" line.long 0x14 "DCMIPP_P2DSRTIOR,DCMIPP Pipex downsize ratio register" hexmask.long.word 0x14 16.--31. 1. "VRATIO,Vertical ratio from 8192 (1x) to 65535 (8x)" hexmask.long.word 0x14 0.--15. 1. "HRATIO,Horizontal ratio from 8192 (1x) to 65535 (8x)" line.long 0x18 "DCMIPP_P2DSSZR,DCMIPP Pipex downsize destination size register" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" group.long 0xD20++0x43 line.long 0x0 "DCMIPP_P2CMRICR,DCMIPP Pipex common ROI configuration register" bitfld.long 0x0 23. "ROI8EN,Region of interest 8 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 22. "ROI7EN,Region of interest 7 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 21. "ROI6EN,Region of interest 6 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 20. "ROI5EN,Region of interest 5 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 19. "ROI4EN,Region of interest 4 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 18. "ROI3EN,Region of interest 3 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 17. "ROI2EN,Region of interest 2 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 16. "ROI1EN,Region of interest 1 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 0.--1. "ROILSZ,Region of interest line size width" "0: Line width 1 pixel,1: Line width 2 pixels,2: Line width 4 pixels,3: Line width 8 pixels" line.long 0x4 "DCMIPP_P2RI1CR1,DCMIPP Pipe2 ROI1 configuration register 1" bitfld.long 0x4 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x4 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x4 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P2RI1CR2,DCMIPP Pipe2 ROI1 configuration register 2" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0xC "DCMIPP_P2RI2CR1,DCMIPP Pipe2 ROI2 configuration register 1" bitfld.long 0xC 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0xC 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0xC 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0xC 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0xC 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P2RI2CR2,DCMIPP Pipe2 ROI2 configuration register 2" hexmask.long.word 0x10 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x10 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x14 "DCMIPP_P2RI3CR1,DCMIPP Pipe2 ROI3 configuration register 1" bitfld.long 0x14 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x14 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x14 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x14 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x18 "DCMIPP_P2RI3CR2,DCMIPP Pipe2 ROI3 configuration register 2" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x1C "DCMIPP_P2RI4CR1,DCMIPP Pipe2 ROI4 configuration register 1" bitfld.long 0x1C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x1C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x1C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x1C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x1C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x20 "DCMIPP_P2RI4CR2,DCMIPP Pipe2 ROI4 configuration register 2" hexmask.long.word 0x20 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x20 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x24 "DCMIPP_P2RI5CR1,DCMIPP Pipe2 ROI5 configuration register 1" bitfld.long 0x24 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x24 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x24 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x24 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x24 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x28 "DCMIPP_P2RI5CR2,DCMIPP Pipe2 ROI5 configuration register 2" hexmask.long.word 0x28 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x28 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x2C "DCMIPP_P2RI6CR1,DCMIPP Pipe2 ROI6 configuration register 1" bitfld.long 0x2C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x2C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x2C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x2C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x2C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x30 "DCMIPP_P2RI6CR2,DCMIPP Pipe2 ROI6 configuration register 2" hexmask.long.word 0x30 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x30 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x34 "DCMIPP_P2RI7CR1,DCMIPP Pipe2 ROI7 configuration register 1" bitfld.long 0x34 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x34 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x34 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x34 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x34 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x38 "DCMIPP_P2RI7CR2,DCMIPP Pipe2 ROI7 configuration register 2" hexmask.long.word 0x38 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x38 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x3C "DCMIPP_P2RI8CR1,DCMIPP Pipe2 ROI8 configuration register 1" bitfld.long 0x3C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x3C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x3C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x3C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x3C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x40 "DCMIPP_P2RI8CR2,DCMIPP Pipe2 ROI8 configuration register 2" hexmask.long.word 0x40 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x40 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" group.long 0xD70++0x3 line.long 0x0 "DCMIPP_P2GMCR,DCMIPP Pipex gamma configuration register" bitfld.long 0x0 0. "ENABLE,None" "0: Gamma is bypassed,1: Gamma is enabled" group.long 0xDC0++0xF line.long 0x0 "DCMIPP_P2PPCR,DCMIPP Pipe2 pixel packer configuration register" bitfld.long 0x0 20. "LMAWE,Line multi address wrapping enable bit" "0: Line multi address wrapping disabled.,1: Line multi address wrapping enabled." bitfld.long 0x0 17.--19. "LMAWM,Line multi address wrapping modulo" "0: Wraps address after every line,1: Wraps address after two lines,2: Wraps address after four lines,3: Wraps address after eight lines,4: Wraps address after sixteen lines,5: Wraps address after 32 lines,6: Wraps address after 64 lines,7: Wraps address after 128 lines" newline bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe2 is always..,1: Double buffer mode activated. Dump address.." bitfld.long 0x0 13.--15. "LINEMULT,Amount of capture completed lines for LINE event and interrupt" "0: Event after every line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 4. "SWAPRB,Swaps R-vs-B components if RGB and if YUV swaps U-vs-V components" "0: No swap of R-vs-B (U-vs-V),1: Swap active." hexmask.long.byte 0x0 0.--3. 1. "FORMAT,Memory format (only coplanar formats are supported in Pipe2)" line.long 0x4 "DCMIPP_P2PPM0AR1,DCMIPP Pipe2 pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P2PPM0AR2,DCMIPP Pipe2 pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" line.long 0xC "DCMIPP_P2PPM0PR,DCMIPP Pipex pixel packer Memory0 pitch register" hexmask.long.word 0xC 0.--14. 1. "PITCH,Number of bytes between the address of two consecutive lines." rgroup.long 0xDD0++0x3 line.long 0x0 "DCMIPP_P2STM0AR,DCMIPP Pipex status Memory0 address register" hexmask.long 0x0 0.--31. 1. "M0A,Memory0 address" group.long 0xDF4++0x3 line.long 0x0 "DCMIPP_P2IER,DCMIPP Pipe2 interrupt enable register" bitfld.long 0x0 7. "OVRIE,Overrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the AXI master is.." bitfld.long 0x0 2. "VSYNCIE,VSYNC interrupt enable" "0: No interrupt generation,1: An interrupt is generated on each VSYNC.." newline bitfld.long 0x0 1. "FRAMEIE,Frame capture completed interrupt enable" "0: No interrupt generation,1: An interrupt is generated after the full capture.." bitfld.long 0x0 0. "LINEIE,Multi-line capture completed interrupt enable" "0: No interrupt generation when the line is received,1: An interrupt is generated after the full capture.." rgroup.long 0xDF8++0x3 line.long 0x0 "DCMIPP_P2SR,DCMIPP Pipe2 status register" bitfld.long 0x0 23. "CPTACT,Capture immediate status" "0: Capture currently inactive,1: Capture currently active" bitfld.long 0x0 17. "LSTFRM,Last frame LSB bit sampled at frame capture complete event. The information is extracted from the frame data number which can be delivered by the camera through the CSI2 interface." "0,1" newline bitfld.long 0x0 16. "LSTLINE,Last line LSB bit sampled at frame capture complete event." "0,1" bitfld.long 0x0 7. "OVRF,Overrun raw interrupt status" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and data of this.." newline bitfld.long 0x0 2. "VSYNCF,VSYNC raw interrupt status" "0,1" bitfld.long 0x0 1. "FRAMEF,Frame capture completed raw interrupt status" "0: No capture or ongoing capture,1: All data of a frame have been captured" newline bitfld.long 0x0 0. "LINEF,Multi-line capture completed raw interrupt status" "0,1" wgroup.long 0xDFC++0x3 line.long 0x0 "DCMIPP_P2FCR,DCMIPP Pipe2 interrupt clear register" bitfld.long 0x0 7. "COVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 2. "CVSYNCF,Vertical synchronization interrupt status clear" "0,1" newline bitfld.long 0x0 1. "CFRAMEF,Frame capture complete interrupt status clear" "0,1" bitfld.long 0x0 0. "CLINEF,Multi-line capture complete interrupt status clear" "0,1" rgroup.long 0xE04++0x3 line.long 0x0 "DCMIPP_P2CFSCR,DCMIPP Pipe2 current flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Current activation of PipeN" "0: Pipe disabled,1: Pipe enabled can start capturing with CPTMODE.." bitfld.long 0x0 30. "FDTFEN,Current force data type format enable" "0: Disable force data type format. The data type..,1: Enable force data type format. When data type.." newline hexmask.long.byte 0x0 24.--29. 1. "FDTF,Current force data type format" bitfld.long 0x0 19.--20. "VC,Current flow selection mode" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Current data type ID" rgroup.long 0xF00++0xB line.long 0x0 "DCMIPP_P2CFCTCR,DCMIPP Pipex current flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame.,1: Capture requested for next frame." bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode - Received data are..,1: Snapshot mode (single frame) - Once activated.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P2CCRSTR,DCMIPP Pipex current crop window start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P2CCRSZR,DCMIPP Pipex current crop window size register" bitfld.long 0x8 31. "ENABLE,Current ENABLE bit value." "0: Bypass all pixels are transmitted through (no..,1: Enable only the rectangle defined by VSIZE HSIZE.." hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" newline hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" group.long 0xF0C++0x3 line.long 0x0 "DCMIPP_P2CDCCR,DCMIPP Pipex current decimation register" bitfld.long 0x0 3.--4. "VDEC,Vertical decimation ratio" "0: All pixels are transmitted no vertical decimation,1: One line out of two transmitted,?,?" bitfld.long 0x0 1.--2. "HDEC,Horizontal decimation ratio" "0: All pixels are transmitted no horizontal..,1: One line out of two transmitted,?,?" newline bitfld.long 0x0 0. "ENABLE,None" "0: Bypass: decimation is not active all pixels are..,1: Enable: one pixel every 1 2 4 or 8 in H and V is.." rgroup.long 0xF10++0xB line.long 0x0 "DCMIPP_P2CDSCR,DCMIPP Pipex current downsize configuration register" bitfld.long 0x0 31. "ENABLE,Current value of bit ENABLE" "0: Down scaler is bypassed,1: Down scaler is enabled" hexmask.long.word 0x0 16.--25. 1. "VDIV,Current vertical division factor from 128 (8x) to 1023 (1x)" newline hexmask.long.word 0x0 0.--9. 1. "HDIV,Current horizontal division factor from 128 (8x) to 1023 (1x)" line.long 0x4 "DCMIPP_P2CDSRTIOR,DCMIPP Pipex current downsize ratio register" hexmask.long.word 0x4 16.--31. 1. "VRATIO,Current vertical ratio from 8192 (1x) to 65535 (8x)" hexmask.long.word 0x4 0.--15. 1. "HRATIO,Current horizontal ratio from 8192 (1x) to 65535 (8x)" line.long 0x8 "DCMIPP_P2CDSSZR,DCMIPP Pipex current downsize destination size register" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" rgroup.long 0xF20++0x43 line.long 0x0 "DCMIPP_P2CCMRICR,DCMIPP Pipex current common ROI configuration register" bitfld.long 0x0 23. "ROI8EN,Current region of interest 8 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 22. "ROI7EN,Current region of interest 7 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 21. "ROI6EN,Current region of interest 6 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 20. "ROI5EN,Current region of interest 5 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 19. "ROI4EN,Current region of interest 4 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 18. "ROI3EN,Current region of interest 3 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 17. "ROI2EN,Current region of interest 2 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 16. "ROI1EN,Current region of interest 1 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 0.--1. "ROILSZ,Current region of interest line size width" "0: Line width 1 pixel,1: Line width 2 pixels,2: Line width 4 pixels,3: Line width 8 pixels" line.long 0x4 "DCMIPP_P2CRI1CR1,DCMIPP Pipe2 current ROI1 configuration register 1" bitfld.long 0x4 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x4 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x4 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P2CRI1CR2,DCMIPP Pipe2 current ROI1 configuration register 2" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0xC "DCMIPP_P2CRI2CR1,DCMIPP Pipe2 current ROI2 configuration register 1" bitfld.long 0xC 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0xC 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0xC 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0xC 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0xC 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P2CRI2CR2,DCMIPP Pipe2 current ROI2 configuration register 2" hexmask.long.word 0x10 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x10 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x14 "DCMIPP_P2CRI3CR1,DCMIPP Pipe2 current ROI3 configuration register 1" bitfld.long 0x14 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x14 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x14 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x14 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x18 "DCMIPP_P2CRI3CR2,DCMIPP Pipe2 current ROI3 configuration register 2" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x1C "DCMIPP_P2CRI4CR1,DCMIPP Pipe2 current ROI4 configuration register 1" bitfld.long 0x1C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x1C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x1C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x1C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x1C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x20 "DCMIPP_P2CRI4CR2,DCMIPP Pipe2 current ROI4 configuration register 2" hexmask.long.word 0x20 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x20 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x24 "DCMIPP_P2CRI5CR1,DCMIPP Pipe2 current ROI5 configuration register 1" bitfld.long 0x24 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x24 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x24 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x24 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x24 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x28 "DCMIPP_P2CRI5CR2,DCMIPP Pipe2 current ROI5 configuration register 2" hexmask.long.word 0x28 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x28 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x2C "DCMIPP_P2CRI6CR1,DCMIPP Pipe2 current ROI6 configuration register 1" bitfld.long 0x2C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x2C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x2C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x2C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x2C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x30 "DCMIPP_P2CRI6CR2,DCMIPP Pipe2 current ROI6 configuration register 2" hexmask.long.word 0x30 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x30 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x34 "DCMIPP_P2CRI7CR1,DCMIPP Pipe2 current ROI7 configuration register 1" bitfld.long 0x34 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x34 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x34 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x34 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x34 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x38 "DCMIPP_P2CRI7CR2,DCMIPP Pipe2 current ROI7 configuration register 2" hexmask.long.word 0x38 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x38 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x3C "DCMIPP_P2CRI8CR1,DCMIPP Pipe2 current ROI8 configuration register 1" bitfld.long 0x3C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x3C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x3C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x3C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x3C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x40 "DCMIPP_P2CRI8CR2,DCMIPP Pipe2 current ROI8 configuration register 2" hexmask.long.word 0x40 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x40 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" rgroup.long 0xFC0++0xB line.long 0x0 "DCMIPP_P2CPPCR,DCMIPP Pipe2 current pixel packer configuration register" bitfld.long 0x0 20. "LMAWE,Line multi address wrapping enable bit" "0: Line multi address wrapping disabled.,1: Line multi address wrapping enabled." bitfld.long 0x0 17.--19. "LMAWM,Line multi address wrapping modulo" "0: Wraps address after every line,1: Wraps address after two lines,2: Wraps address after four lines,3: Wraps address after eight lines,4: Wraps address after sixteen lines,5: Wraps address after 32 lines,6: Wraps address after 64 lines,7: Wraps address after 128 lines" newline bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe2 is always..,1: Double buffer mode activated. Dump address.." bitfld.long 0x0 13.--15. "LINEMULT,Amount of capture completed lines for LINE event and interrupt" "0: Event after every line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 4. "SWAPRB,Swaps R-vs-B components if RGB and if YUV swaps U-vs-V components" "0: No swap of R-vs-B (U-vs-V),1: Swap active." hexmask.long.byte 0x0 0.--3. 1. "FORMAT,Memory format (only coplanar formats are supported in Pipe2)" line.long 0x4 "DCMIPP_P2CPPM0AR1,DCMIPP Pipe2 current pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P2CPPM0AR2,DCMIPP Pipe2 current pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" tree.end tree "DCMIPP_S" base ad:0x58002000 group.long 0x0++0x7 line.long 0x0 "DCMIPP_IPGR1,DCMIPP IPPLUG global register 1" bitfld.long 0x0 24. "QOS_MODE,Quality of service" "0,1" bitfld.long 0x0 0.--2. "MEMORYPAGE,Memory page size as power of 2 of 64-byte units:" "0: 64 bytes,1: 128 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPGR2,DCMIPP IPPLUG global register 2" bitfld.long 0x4 0. "PSTART,Request to lock the IP-Plug to allow reconfiguration." "0: No lock requested IP-Plug runs on demand by..,1: Lock requested: IP-Plug freezes shortly (see.." rgroup.long 0x8++0x3 line.long 0x0 "DCMIPP_IPGR3,DCMIPP IPPLUG global register 3" bitfld.long 0x0 0. "IDLE,Status of IP-Plug" "0: IP-Plug is running (on demand by background HW),1: IP-Plug is currently locked and can be.." rgroup.long 0x1C++0x3 line.long 0x0 "DCMIPP_IPGR8,DCMIPP IPPLUG identification register" hexmask.long.byte 0x0 24.--31. 1. "IPPID,IP identifier (0xAA)" hexmask.long.byte 0x0 16.--20. 1. "ARCHIID,Architecture identifier (0x04)" newline hexmask.long.byte 0x0 8.--12. 1. "REVID,Revision identifier (0x03)" hexmask.long.byte 0x0 0.--5. 1. "DID,Division identifier (0x14)" group.long 0x20++0xB line.long 0x0 "DCMIPP_IPC1R1,DCMIPP IPPLUG Clientx register 1" hexmask.long.byte 0x0 8.--11. 1. "OTR,Maximum outstanding transactions" bitfld.long 0x0 0.--2. "TRAFFIC,Burst size as power of 2 of 8-byte units" "0: 8 bytes,1: 16 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPC1R2,DCMIPP IPPLUG Clientx register 2" hexmask.long.byte 0x4 16.--19. 1. "WLRU,Ratio for WLRU[3:0] arbitration" hexmask.long.byte 0x4 8.--11. 1. "SVCMAPPING,Non-user must be kept at reset value." line.long 0x8 "DCMIPP_IPC1R3,DCMIPP IPPLUG Clientx register 3" hexmask.long.word 0x8 16.--25. 1. "DPREGEND,End word (AXI width = 64 bits) of the FIFO of Clientx." hexmask.long.word 0x8 0.--9. 1. "DPREGSTART,Start word (AXI width = 64 bits) of the FIFO of Clientx." group.long 0x30++0xB line.long 0x0 "DCMIPP_IPC2R1,DCMIPP IPPLUG Clientx register 1" hexmask.long.byte 0x0 8.--11. 1. "OTR,Maximum outstanding transactions" bitfld.long 0x0 0.--2. "TRAFFIC,Burst size as power of 2 of 8-byte units" "0: 8 bytes,1: 16 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPC2R2,DCMIPP IPPLUG Clientx register 2" hexmask.long.byte 0x4 16.--19. 1. "WLRU,Ratio for WLRU[3:0] arbitration" hexmask.long.byte 0x4 8.--11. 1. "SVCMAPPING,Non-user must be kept at reset value." line.long 0x8 "DCMIPP_IPC2R3,DCMIPP IPPLUG Clientx register 3" hexmask.long.word 0x8 16.--25. 1. "DPREGEND,End word (AXI width = 64 bits) of the FIFO of Clientx." hexmask.long.word 0x8 0.--9. 1. "DPREGSTART,Start word (AXI width = 64 bits) of the FIFO of Clientx." group.long 0x40++0xB line.long 0x0 "DCMIPP_IPC3R1,DCMIPP IPPLUG Clientx register 1" hexmask.long.byte 0x0 8.--11. 1. "OTR,Maximum outstanding transactions" bitfld.long 0x0 0.--2. "TRAFFIC,Burst size as power of 2 of 8-byte units" "0: 8 bytes,1: 16 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPC3R2,DCMIPP IPPLUG Clientx register 2" hexmask.long.byte 0x4 16.--19. 1. "WLRU,Ratio for WLRU[3:0] arbitration" hexmask.long.byte 0x4 8.--11. 1. "SVCMAPPING,Non-user must be kept at reset value." line.long 0x8 "DCMIPP_IPC3R3,DCMIPP IPPLUG Clientx register 3" hexmask.long.word 0x8 16.--25. 1. "DPREGEND,End word (AXI width = 64 bits) of the FIFO of Clientx." hexmask.long.word 0x8 0.--9. 1. "DPREGSTART,Start word (AXI width = 64 bits) of the FIFO of Clientx." group.long 0x50++0xB line.long 0x0 "DCMIPP_IPC4R1,DCMIPP IPPLUG Clientx register 1" hexmask.long.byte 0x0 8.--11. 1. "OTR,Maximum outstanding transactions" bitfld.long 0x0 0.--2. "TRAFFIC,Burst size as power of 2 of 8-byte units" "0: 8 bytes,1: 16 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPC4R2,DCMIPP IPPLUG Clientx register 2" hexmask.long.byte 0x4 16.--19. 1. "WLRU,Ratio for WLRU[3:0] arbitration" hexmask.long.byte 0x4 8.--11. 1. "SVCMAPPING,Non-user must be kept at reset value." line.long 0x8 "DCMIPP_IPC4R3,DCMIPP IPPLUG Clientx register 3" hexmask.long.word 0x8 16.--25. 1. "DPREGEND,End word (AXI width = 64 bits) of the FIFO of Clientx." hexmask.long.word 0x8 0.--9. 1. "DPREGSTART,Start word (AXI width = 64 bits) of the FIFO of Clientx." group.long 0x60++0xB line.long 0x0 "DCMIPP_IPC5R1,DCMIPP IPPLUG Clientx register 1" hexmask.long.byte 0x0 8.--11. 1. "OTR,Maximum outstanding transactions" bitfld.long 0x0 0.--2. "TRAFFIC,Burst size as power of 2 of 8-byte units" "0: 8 bytes,1: 16 bytes,?,?,?,?,?,?" line.long 0x4 "DCMIPP_IPC5R2,DCMIPP IPPLUG Clientx register 2" hexmask.long.byte 0x4 16.--19. 1. "WLRU,Ratio for WLRU[3:0] arbitration" hexmask.long.byte 0x4 8.--11. 1. "SVCMAPPING,Non-user must be kept at reset value." line.long 0x8 "DCMIPP_IPC5R3,DCMIPP IPPLUG Clientx register 3" hexmask.long.word 0x8 16.--25. 1. "DPREGEND,End word (AXI width = 64 bits) of the FIFO of Clientx." hexmask.long.word 0x8 0.--9. 1. "DPREGSTART,Start word (AXI width = 64 bits) of the FIFO of Clientx." group.long 0x104++0xB line.long 0x0 "DCMIPP_PRCR,DCMIPP parallel interface control register" bitfld.long 0x0 26. "SWAPBITS,Swap LSB vs. MSB within each received component" "0: As received,1: Swapped MSB vs. LSB" bitfld.long 0x0 25. "SWAPCYCLES,Swap data (cycle 0 vs. cycle 1) for pixels received on two cycles" "0: Default,1: Swap active: the data of cycle 1 is used before.." newline hexmask.long.byte 0x0 16.--23. 1. "FORMAT,Other values: data are captured and output as-is only through the data/dump pipeline (e.g. JPEG or byte input format)." bitfld.long 0x0 14. "ENABLE,Parallel interface enable" "0: Parallel interface disabled to lower power..,1: Parallel interface enabled" newline bitfld.long 0x0 10.--12. "EDM,Extended data mode" "0: Interface captures 8-bit data on every pixel clock,1: Interface captures 10-bit data on every pixel..,2: Interface captures 12-bit data on every pixel..,3: Interface captures 14-bit data on every pixel..,4: Interface captures 16-bit data on every pixel..,?,?,?" bitfld.long 0x0 7. "VSPOL,Vertical synchronization polarity" "0: VSYNC active low,1: VSYNC active high" newline bitfld.long 0x0 6. "HSPOL,Horizontal synchronization polarity" "0: HSYNC active low,1: HSYNC active high" bitfld.long 0x0 5. "PCKPOL,Pixel clock polarity" "0: Falling edge active,1: Rising edge active" newline bitfld.long 0x0 4. "ESS,Embedded synchronization select" "0: Hardware synchronization data capture..,1: Embedded synchronization data capture is.." line.long 0x4 "DCMIPP_PRESCR,DCMIPP parallel interface embedded synchronization code register" hexmask.long.byte 0x4 24.--31. 1. "FEC,Frame end delimiter code" hexmask.long.byte 0x4 16.--23. 1. "LEC,Line end delimiter code" newline hexmask.long.byte 0x4 8.--15. 1. "LSC,Line start delimiter code" hexmask.long.byte 0x4 0.--7. 1. "FSC,Frame start delimiter code" line.long 0x8 "DCMIPP_PRESUR,DCMIPP parallel interface embedded synchronization unmask register" hexmask.long.byte 0x8 24.--31. 1. "FEU,Frame end delimiter unmask" hexmask.long.byte 0x8 16.--23. 1. "LEU,Line end delimiter unmask" newline hexmask.long.byte 0x8 8.--15. 1. "LSU,Line start delimiter unmask" hexmask.long.byte 0x8 0.--7. 1. "FSU,Frame start delimiter unmask" group.long 0x1F4++0x3 line.long 0x0 "DCMIPP_PRIER,DCMIPP parallel interface interrupt enable register" bitfld.long 0x0 6. "ERRIE,Synchronization error interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the embedded.." rgroup.long 0x1F8++0x3 line.long 0x0 "DCMIPP_PRSR,DCMIPP parallel interface status register" bitfld.long 0x0 17. "VSYNC,This bit gives the state of the VSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit .." "0: Active frame,1: Synchronization between frames" bitfld.long 0x0 16. "HSYNC,This bit gives the state of the HSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit .." "0: Active line,1: Synchronization between lines" newline bitfld.long 0x0 6. "ERRF,Synchronization error raw interrupt status" "0: No synchronization error detected,1: Embedded synchronization characters are not.." wgroup.long 0x1FC++0x3 line.long 0x0 "DCMIPP_PRFCR,DCMIPP parallel interface interrupt clear register" bitfld.long 0x0 6. "CERRF,Synchronization error interrupt status clear" "0,1" group.long 0x204++0x3 line.long 0x0 "DCMIPP_CMCR,DCMIPP common configuration register" bitfld.long 0x0 7. "SWAPRB,Swap R/U and B/V" "0: RGB/VYU,1: BGR/UYV" bitfld.long 0x0 4. "CFC,Clear frame counter" "0,1" newline bitfld.long 0x0 1.--2. "PSFC,Pipe selection for the frame counter" "0: Frame counter mapped to Pipe0,1: Frame counter mapped to Pipe1,2: Frame counter mapped to Pipe2,?" bitfld.long 0x0 0. "INSEL,input selection" "0: DCMI,1: CSI-2" rgroup.long 0x208++0x3 line.long 0x0 "DCMIPP_CMFRCR,DCMIPP common frame counter register" hexmask.long 0x0 0.--31. 1. "FRMCNT,Frame counter read-only loops around." group.long 0x3F0++0x3 line.long 0x0 "DCMIPP_CMIER,DCMIPP common interrupt enable register" bitfld.long 0x0 31. "P2OVRIE,Overrun interrupt status enable for Pipe2" "0: No interrupt generation,1: An interrupt is generated" bitfld.long 0x0 26. "P2VSYNCIE,Vertical sync interrupt enable for Pipe2" "0: No interrupt generation,1: An interrupt is generated." newline bitfld.long 0x0 25. "P2FRAMEIE,Frame capture complete interrupt enable for Pipe2" "0: No interrupt generation,1: An interrupt is generated." bitfld.long 0x0 24. "P2LINEIE,Multi-line capture complete interrupt enable for Pipe2" "0: No interrupt generation,1: An interrupt is generated." newline bitfld.long 0x0 23. "P1OVRIE,Overrun interrupt enable for Pipe1" "0,1" bitfld.long 0x0 18. "P1VSYNCIE,Vertical sync interrupt enable for Pipe1" "0: No interrupt generation,1: An interrupt is generated" newline bitfld.long 0x0 17. "P1FRAMEIE,Frame capture complete interrupt enable for Pipe1" "0: No interrupt generation,1: An interrupt is generated" bitfld.long 0x0 16. "P1LINEIE,Multi-line capture complete interrupt status clear for Pipe1" "0: No interrupt generation,1: An interrupt is generated" newline bitfld.long 0x0 15. "P0OVRIE,Overrun interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated" bitfld.long 0x0 14. "P0LIMITIE,Limit interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated" newline bitfld.long 0x0 10. "P0VSYNCIE,Vertical sync interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated" bitfld.long 0x0 9. "P0FRAMEIE,Frame capture complete interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated" newline bitfld.long 0x0 8. "P0LINEIE,Multi-line capture complete interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated" bitfld.long 0x0 6. "PRERRIE,Limit interrupt enable for the parallel Interface" "0: No interrupt generation,1: An interrupt is generated" newline bitfld.long 0x0 5. "ATXERRIE,AXI transfer error interrupt enable for IPPLUG" "0: No interrupt generation,1: An interrupt is generated" rgroup.long 0x3F4++0x7 line.long 0x0 "DCMIPP_CMSR1,DCMIPP common status register 1" bitfld.long 0x0 31. "P2CPTACT,Active frame capture (active from start-of-frame to frame complete) for Pipe2" "0: No capture currently active,1: Capture currently active" bitfld.long 0x0 25. "P2LSTFRM,Last frame LSB bit sampled at frame capture complete event for Pipe2" "0,1" newline bitfld.long 0x0 24. "P2LSTLINE,Last line LSB bit sampled at frame capture complete event for Pipe2" "0,1" bitfld.long 0x0 23. "P1CPTACT,Active frame capture (active from start-of-frame to frame complete) for Pipe1" "0: No capture currently active,1: Capture currently active" newline bitfld.long 0x0 17. "P1LSTFRM,Last frame LSB bit sampled at frame capture complete event for Pipe1" "0,1" bitfld.long 0x0 16. "P1LSTLINE,Last line LSB bit sampled at Frame capture complete event for Pipe1" "0,1" newline bitfld.long 0x0 15. "P0CPTACT,Active frame capture (active from start-of-frame to frame complete) for Pipe0" "0: No capture currently active,1: Capture currently active" bitfld.long 0x0 9. "P0LSTFRM,Last frame LSB bit sampled at Frame capture complete event for Pipe0" "0,1" newline bitfld.long 0x0 8. "P0LSTLINE,Last line LSB bit sampled at Frame capture complete event for Pipe0" "0,1" bitfld.long 0x0 1. "PRVSYNC,This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the.." "0: Active frame,1: Synchronization between frames" newline bitfld.long 0x0 0. "PRHSYNC,This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the.." "0: Active line,1: Synchronization between lines" line.long 0x4 "DCMIPP_CMSR2,DCMIPP common status register 2" bitfld.long 0x4 31. "P2OVRF,Overrun raw interrupt status for Pipe2" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.." bitfld.long 0x4 26. "P2VSYNCF,VSYNC raw interrupt status for Pipe2" "0,1" newline bitfld.long 0x4 25. "P2FRAMEF,Frame capture completed raw interrupt status for Pipe2" "0: No capture or ongoing capture,1: All data of a frame have been captured" bitfld.long 0x4 24. "P2LINEF,Multi-line capture completed raw interrupt status for Pipe2" "0,1" newline bitfld.long 0x4 23. "P1OVRF,Overrun raw interrupt status for Pipe1" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.." bitfld.long 0x4 18. "P1VSYNCF,VSYNC raw interrupt status for Pipe1" "0,1" newline bitfld.long 0x4 17. "P1FRAMEF,Frame capture completed raw interrupt status for Pipe1" "0: No capture or ongoing capture,1: All data of a frame have been captured" bitfld.long 0x4 16. "P1LINEF,Multi-line capture completed raw interrupt status for Pipe1" "0,1" newline bitfld.long 0x4 15. "P0OVRF,Overrun raw interrupt status for Pipe0" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.." bitfld.long 0x4 14. "P0LIMITF,Limit raw interrupt status for Pipe0" "0,1" newline bitfld.long 0x4 10. "P0VSYNCF,VSYNC raw interrupt status for Pipe0" "0,1" bitfld.long 0x4 9. "P0FRAMEF,Frame capture completed raw interrupt status for Pipe0" "0: No capture or ongoing capture,1: All data of a frame have been captured" newline bitfld.long 0x4 8. "P0LINEF,Multi-line capture completed raw interrupt status for Pipe0" "0,1" bitfld.long 0x4 6. "PRERRF,Synchronization error raw interrupt status for the parallel interface." "0: No synchronization error detected,1: Embedded synchronization characters are not.." newline bitfld.long 0x4 5. "ATXERRF,AXI transfer error interrupt status flag for the IPPLUG." "0: No AXI transfer error detected,1: AXI transfer error occurred on an AXI client." wgroup.long 0x3FC++0x3 line.long 0x0 "DCMIPP_CMFCR,DCMIPP common interrupt clear register" bitfld.long 0x0 31. "CP2OVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 26. "CP2VSYNCF,Vertical synchronization interrupt status clear" "0,1" newline bitfld.long 0x0 25. "CP2FRAMEF,Frame capture complete interrupt status clear" "0,1" bitfld.long 0x0 24. "CP2LINEF,Multi-line capture complete interrupt status clear" "0,1" newline bitfld.long 0x0 23. "CP1OVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 18. "CP1VSYNCF,Vertical synchronization interrupt status clear" "0,1" newline bitfld.long 0x0 17. "CP1FRAMEF,Frame capture complete interrupt status clear" "0,1" bitfld.long 0x0 16. "CP1LINEF,Multi-line capture complete interrupt status clear" "0,1" newline bitfld.long 0x0 15. "CP0OVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 14. "CP0LIMITF,limit interrupt status clear" "0,1" newline bitfld.long 0x0 10. "CP0VSYNCF,Vertical synchronization interrupt status clear" "0,1" bitfld.long 0x0 9. "CP0FRAMEF,Frame capture complete interrupt status clear" "0,1" newline bitfld.long 0x0 8. "CP0LINEF,Multi-line capture complete interrupt status clear" "0,1" bitfld.long 0x0 6. "CPRERRF,Synchronization error interrupt status clear" "0,1" newline bitfld.long 0x0 5. "CATXERRF,AXI transfer error interrupt status clear" "0,1" group.long 0x404++0x3 line.long 0x0 "DCMIPP_P0FSCR,DCMIPP Pipe0 flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Activation of PipeN" "0: Pipe disabled,1: Pipe enabled can start capturing with CPTMODE.." bitfld.long 0x0 19.--20. "VC,Flow selection mode" "0,1,2,3" newline bitfld.long 0x0 16.--17. "DTMODE,Flow selection mode" "0: Only flow DTIDA from the selected virtual..,1: Flows DTIDA and/or DTIDB from the selected..,2: All data types from the selected virtual channel..,3: All data types of the selected virtual channel.." hexmask.long.byte 0x0 8.--13. 1. "DTIDB,Data type selection ID B" newline hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Data type selection ID A" group.long 0x500++0xB line.long 0x0 "DCMIPP_P0FCTCR,DCMIPP Pipe0 flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame,1: Capture requested for next frame" bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode - The received data are..,1: Snapshot mode (single frame) - Once activated.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P0SCSTR,DCMIPP Pipe0 stat/crop start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 words wide" line.long 0x8 "DCMIPP_P0SCSZR,DCMIPP Pipe0 stat/crop size register" bitfld.long 0x8 31. "ENABLE,This bit is set and cleared by software." "0: Bypass. All the data are computed if the..,1: Enable. Depending on bit POSNEG value the.." bitfld.long 0x8 30. "POSNEG,This bit is set and cleared by software. It has a meaning only if ENABLE bit is set." "0: Positive area the rectangle defined by VSIZE..,1: Negative area the area excluding the rectangle.." newline hexmask.long.word 0x8 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 word wide (data 32-bit)" rgroup.long 0x5B0++0x3 line.long 0x0 "DCMIPP_P0DCCNTR,DCMIPP Pipe0 dump counter register" hexmask.long 0x0 0.--25. 1. "CNT,Number of data dumped during the frame." group.long 0x5B4++0x3 line.long 0x0 "DCMIPP_P0DCLMTR,DCMIPP Pipe0 dump limit register" bitfld.long 0x0 31. "ENABLE,None" "0: Disabled no check on the amount of 32-bit words..,1: Enabled check done versus limit" hexmask.long.tbyte 0x0 0.--23. 1. "LIMIT,Maximum number of 32-bit data that can be dumped during a frame after the crop 2D operation." group.long 0x5C0++0xB line.long 0x0 "DCMIPP_P0PPCR,DCMIPP Pipe0 pixel packer configuration register" bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe0 always..,1: Double buffer mode activated. Dump address.." bitfld.long 0x0 13.--15. "LINEMULT,Amount of capture completed lines for LINE event and interrupt" "0: Event after one line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 11. "OELS,Odd/even line select (line select start)" "0: Interface captures first line after the frame..,1: Interface captures second line from the frame.." bitfld.long 0x0 10. "LSM,Line select mode" "0: Interface captures all received lines,1: Interface captures one line out of two" newline bitfld.long 0x0 9. "OEBS,Odd/even byte select (byte select start)" "0: Interface captures the first data (byte or..,1: Interface captures the second data (byte or.." bitfld.long 0x0 7.--8. "BSM,Byte select mode" "0: Interface captures all received data,1: Interface captures 1 data out of 2,2: Interface captures one byte out of four,3: Interface captures two bytes out of four" newline bitfld.long 0x0 6. "HEADEREN,CSI header dump enable" "0: CSI-2 headers are not dumped,1: CSI-2 headers are dumped as a 32-bit word." bitfld.long 0x0 5. "PAD,Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment." "0: Aligns on LSB (and pads null bits on MSB) for..,1: Aligns on MSB (and pads null bits on LSB) for.." newline bitfld.long 0x0 0. "SWAPYUV,Swaps within a 32-bit word byte 0-vs-1 and byte 2-vs-3. It corresponds for YUV422 pixels formats to swap between UYVY and YUYV." "0: Outputs the provided words as described in..,1: Swaps the bytes from provided words byte 0-vs.-1.." line.long 0x4 "DCMIPP_P0PPM0AR1,DCMIPP Pipe0 pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P0PPM0AR2,DCMIPP Pipe0 pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" rgroup.long 0x5D0++0x3 line.long 0x0 "DCMIPP_P0STM0AR,DCMIPP Pipe0 status Memory0 address register" hexmask.long 0x0 0.--31. 1. "M0A,Memory0 address" group.long 0x5F4++0x3 line.long 0x0 "DCMIPP_P0IER,DCMIPP Pipe0 interrupt enable register" bitfld.long 0x0 7. "OVRIE,Overrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the AXI master is.." bitfld.long 0x0 6. "LIMITIE,Limit interrupt enable" "0: No interrupt generation when the limit is reached,1: An interrupt is generated when the limit is.." newline bitfld.long 0x0 2. "VSYNCIE,VSYNC interrupt enable" "0: No interrupt generation,1: An interrupt is generated on each VSYNC.." bitfld.long 0x0 1. "FRAMEIE,Frame capture completed interrupt enable" "0: No interrupt generation,1: An interrupt is generated after the full capture.." newline bitfld.long 0x0 0. "LINEIE,Multi-line capture completed interrupt enable" "0: No interrupt generation when the line is received,1: An interrupt is generated after the full capture.." rgroup.long 0x5F8++0x3 line.long 0x0 "DCMIPP_P0SR,DCMIPP Pipe0 status register" bitfld.long 0x0 23. "CPTACT,Capture immediate status" "0: Capture currently inactive,1: Capture currently active" bitfld.long 0x0 17. "LSTFRM,Last frame LSB bit sampled at frame capture complete event. The information is extracted from the frame data number that can be delivered by the camera through the CSI2 interface." "0,1" newline bitfld.long 0x0 16. "LSTLINE,Last line LSB bit sampled at frame capture complete event." "0,1" bitfld.long 0x0 7. "OVRF,Overrun raw interrupt status" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.." newline bitfld.long 0x0 6. "LIMITF,Limit raw interrupt status" "0,1" bitfld.long 0x0 2. "VSYNCF,VSYNC raw interrupt status" "0,1" newline bitfld.long 0x0 1. "FRAMEF,Frame capture completed raw interrupt status" "0: No capture or ongoing capture,1: All data of a frame have been captured" bitfld.long 0x0 0. "LINEF,Multi-line capture completed raw interrupt status" "0,1" wgroup.long 0x5FC++0x3 line.long 0x0 "DCMIPP_P0FCR,DCMIPP Pipe0 interrupt clear register" bitfld.long 0x0 7. "COVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 6. "CLIMITF,limit interrupt status clear" "0,1" newline bitfld.long 0x0 2. "CVSYNCF,Vertical synchronization interrupt status clear" "0,1" bitfld.long 0x0 1. "CFRAMEF,Frame capture complete interrupt status clear" "0,1" newline bitfld.long 0x0 0. "CLINEF,Multi-line capture complete interrupt status clear" "0,1" rgroup.long 0x604++0x3 line.long 0x0 "DCMIPP_P0CFSCR,DCMIPP Pipe0 current flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Current activation of PipeN" "0: Pipe disabled,1: Pipe enabled can start capturing with CPTMODE.." bitfld.long 0x0 19.--20. "VC,Current flow selection mode" "0,1,2,3" newline bitfld.long 0x0 16.--17. "DTMODE,Flow selection mode" "0: Only flow DTIDA from the selected virtual..,1: Flows DTIDA and/or DTIDB from the selected..,2: All Datatypes from the selected virtual channel..,3: All Datatypes of the selected virtual channel VC.." hexmask.long.byte 0x0 8.--13. 1. "DTIDB,Current data type selection ID B" newline hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Current data type selection ID A" rgroup.long 0x700++0xB line.long 0x0 "DCMIPP_P0CFCTCR,DCMIPP Pipe0 current flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame.,1: Capture requested for next frame." bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode - The received data are..,1: Snapshot mode (single frame) - Once activated.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P0CSCSTR,DCMIPP Pipe0 current stat/crop start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 words wide" line.long 0x8 "DCMIPP_P0CSCSZR,DCMIPP Pipe0 current stat/crop size register" bitfld.long 0x8 31. "ENABLE,Current value of the ENABLE bit" "0: Bypass. All data are computed if the statistics..,1: Enable: Depending on bit POSNEG value the.." bitfld.long 0x8 30. "POSNEG,Current value of the POSNEG bit" "0: Positive area. The rectangle defined by VSIZE..,1: Negative area. The active area is the area.." newline hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high." hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 word wide (data 32-bit)." rgroup.long 0x7C0++0xB line.long 0x0 "DCMIPP_P0CPPCR,DCMIPP Pipe0 current pixel packer configuration register" bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe0 is always..,1: Double buffer mode activated. Dump address.." bitfld.long 0x0 13.--15. "LINEMULT,Current amount of capture completed lines for LINE event and interrupt" "0: Event after every line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 11. "OELS,Current odd/even line select (ine select start)" "0: Interface captures the first line after the..,1: Interface captures the second line from the.." bitfld.long 0x0 10. "LSM,Current Line select mode" "0: Interface captures all received lines,1: Interface captures one line out of two" newline bitfld.long 0x0 9. "OEBS,Current odd/even byte select (byte select start)" "0: Interface captures the first data (byte or..,1: Interface captures the second data (byte or.." bitfld.long 0x0 7.--8. "BSM,Current Byte select mode" "0: Interface captures all received data,1: Interface captures one data out of two,2: Interface captures one byte out of four,3: Interface captures two bytes out of four" newline bitfld.long 0x0 6. "HEADEREN,Current CSI header dump enable" "0: CSI-2 headers are not dumped.,1: CSI-2 headers are dumped as a 32-bit words." bitfld.long 0x0 5. "PAD,Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment" "0: Aligns on LSB (and pads null bits on MSB) for..,1: Aligns on MSB (and pads null bits on LSB) for.." newline bitfld.long 0x0 0. "SWAPYUV,Swaps within a 32-bit word byte 0 vs. 1 and byte 2 vs. 3. It corresponds for YUV422 pixels formats to swap between UYVY and YUYV." "0: Outputs the provided words as described in..,1: Swaps the bytes from provided words byte 0 vs. 1.." line.long 0x4 "DCMIPP_P0CPPM0AR1,DCMIPP Pipe0 current pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P0CPPM0AR2,DCMIPP Pipe0 current pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" group.long 0x804++0x3 line.long 0x0 "DCMIPP_P1FSCR,DCMIPP Pipe1 flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Activation of PipeN" "0: Pipe disabled,1: Pipe enabled can start capturing with CPTMODE.." bitfld.long 0x0 30. "FDTFEN,Force Datatype format enable." "0: Disable force Datatype format. The Datatype..,?" newline hexmask.long.byte 0x0 24.--29. 1. "FDTF,Force Datatype format." bitfld.long 0x0 19.--20. "VC,Flow selection mode" "0,1,2,3" newline bitfld.long 0x0 18. "PIPEDIFF,Differentiates Pipe2 from Pipe1" "0: Pipe2 receives the same data as Pipe1 (Ie data..,1: Pipe1 gets pixels from only VC and DT configured.." bitfld.long 0x0 16.--17. "DTMODE,Flow selection mode" "0: Only flow DTIDA from the selected virtual..,1: Flows DTIDA and/or DTIDB from the selected..,?,?" newline hexmask.long.byte 0x0 8.--13. 1. "DTIDB,Data type selection ID B" hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Data type selection ID A" group.long 0x820++0x7 line.long 0x0 "DCMIPP_P1SRCR,DCMIPP Pipe1 stat removal configuration register" bitfld.long 0x0 15. "CROPEN,Crop line enable" "0: No crop (all pixels are fed through),1: Crop" bitfld.long 0x0 12.--14. "FIRSTLINEDEL,Amount of first lines to delete when CROPEN = 1" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--11. 1. "LASTLINE,Amount of following lines to keep when CROPEN = 1. If LASTLINE = 0 all pixels after FIRSTLINEDEL are fed through." line.long 0x4 "DCMIPP_P1BPRCR,DCMIPP Pipe1 bad pixel removal control register" bitfld.long 0x4 1.--3. "STRENGTH,Strength (aggressiveness) of the bad pixel detection" "0: The filter is fairly tolerant: only a few pixels..,?,?,?,?,?,?,?" bitfld.long 0x4 0. "ENABLE,Bad pixel detection must be enabled only for raw Bayer flows as it corrupts RGB flows." "0: Bypass: bad pixel removal is not active all..,1: Enable: if bad pixel are detected they are.." rgroup.long 0x828++0x3 line.long 0x0 "DCMIPP_P1BPRSR,DCMIPP Pipe1 bad pixel removal status register" hexmask.long.word 0x0 0.--11. 1. "BADCNT,Amount of detected bad pixels" group.long 0x830++0x3 line.long 0x0 "DCMIPP_P1DECR,DCMIPP Pipe1 decimation register" bitfld.long 0x0 3.--4. "VDEC,Vertical decimation ratio" "0: All pixels are transmitted no vertical decimation,1: One line out of two transmitted (for raw Bayer..,?,?" bitfld.long 0x0 1.--2. "HDEC,Horizontal decimation ratio" "0: All pixels are transmitted no horizontal..,1: One line out of two transmitted (for raw Bayer..,?,?" newline bitfld.long 0x0 0. "ENABLE,None" "0: Bypass: decimation is not active all pixels are..,1: Enable: one pixel every 1 2 4 or 8 in H and V is.." group.long 0x840++0xB line.long 0x0 "DCMIPP_P1BLCCR,DCMIPP Pipe1 black level calibration control register" hexmask.long.byte 0x0 24.--31. 1. "BLCR,Black level calibration - Red" hexmask.long.byte 0x0 16.--23. 1. "BLCG,Black level calibration - Green" newline hexmask.long.byte 0x0 8.--15. 1. "BLCB,Black level calibration - Blue" bitfld.long 0x0 0. "ENABLE,Black level calibration" "0: Bypass: black level calibration is not active..,1: Enable: the BLC R G B are subtracted." line.long 0x4 "DCMIPP_P1EXCR1,DCMIPP Pipe1 exposure control register 1" bitfld.long 0x4 28.--30. "SHFR,Exposure shift - Red" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 20.--27. 1. "MULTR,Exposure multiplier - Red" newline bitfld.long 0x4 0. "ENABLE,Exposure control (multiplication and shift) of all red green and blue" "0: Bypass: exposure multiplier and shift are not..,1: Enable: the exposure multiplication and shift is.." line.long 0x8 "DCMIPP_P1EXCR2,DCMIPP Pipe1 exposure control register 2" bitfld.long 0x8 28.--30. "SHFG,Exposure shift - Green" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 20.--27. 1. "MULTG,Exposure multiplier - Green" newline bitfld.long 0x8 12.--14. "SHFB,Exposure shift - Blue" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 4.--11. 1. "MULTB,Exposure multiplier - Blue" group.long 0x850++0x13 line.long 0x0 "DCMIPP_P1ST1CR,DCMIPP Pipe1 statistics1 control register" bitfld.long 0x0 7. "MODE,Statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." bitfld.long 0x0 4.--6. "SRC,Statistics source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "BINS,Current bin definition" "0: All Pixels: Accu is incremented of Component if..,1: NoExt16: Accu is incremented of Component if 16..,?,?" bitfld.long 0x0 0. "ENABLE,None" "0: Disabled: statistics are not accumulated.,1: Enable: statistics are accumulated" line.long 0x4 "DCMIPP_P1ST2CR,DCMIPP Pipe1 statistics 2 control register" bitfld.long 0x4 7. "MODE,Statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." bitfld.long 0x4 4.--6. "SRC,Statistics source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "BINS,Bin definition" "0: AllPixels: Accu is incremented of Component if 0..,1: NoExt16: Accu is incremented of Component if 16..,?,?" bitfld.long 0x4 0. "ENABLE,None" "0: Disabled: statistics are not accumulated,1: Enabled: statistics are accumulated" line.long 0x8 "DCMIPP_P1ST3CR,DCMIPP Pipe1 statistics 3 control register" bitfld.long 0x8 7. "MODE,Statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." bitfld.long 0x8 4.--6. "SRC,Statistics source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 2.--3. "BINS,Bin definition" "0: AllPixels: Accu is incremented of Component if 0..,1: NoExt16: Accu is incremented of Component if 16..,?,?" bitfld.long 0x8 0. "ENABLE,None" "0: Disabled: statistics are not accumulated,1: Enabled: statistics are accumulated" line.long 0xC "DCMIPP_P1STSTR,DCMIPP Pipe1 statistics window start register" hexmask.long.word 0xC 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" hexmask.long.word 0xC 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P1STSZR,DCMIPP Pipe1 statistics window size register" bitfld.long 0x10 31. "CROPEN,None" "0: Bypass all pixels are used to compute the..,1: Enable only the rectangle defined by VSTART.." hexmask.long.word 0x10 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" newline hexmask.long.word 0x10 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" rgroup.long 0x864++0xB line.long 0x0 "DCMIPP_P1ST1SR,DCMIPP Pipe1 statistics 1 status register" hexmask.long.tbyte 0x0 0.--23. 1. "ACCU,Accumulation result divided by 256." line.long 0x4 "DCMIPP_P1ST2SR,DCMIPP Pipe1 statistics 2 status register" hexmask.long.tbyte 0x4 0.--23. 1. "ACCU,accumulation result divided by 256." line.long 0x8 "DCMIPP_P1ST3SR,DCMIPP Pipe1 statistics 3 status register" hexmask.long.tbyte 0x8 0.--23. 1. "ACCU,accumulation result divided by 256." group.long 0x870++0x3 line.long 0x0 "DCMIPP_P1DMCR,DCMIPP Pipe1 demosaicing configuration register" bitfld.long 0x0 28.--30. "EDGE,Strength of the edge detection" "0: No edge detection pure linear interpolation,?,?,?,?,?,?,?" bitfld.long 0x0 24.--26. "LINEH,Strength of the horizontal line detection" "0: No horizontal line detection pure linear..,?,?,?,?,?,?,?" newline bitfld.long 0x0 20.--22. "LINEV,Strength of the vertical line detection" "0: No vertical line detection pure linear..,?,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "PEAK,Strength of the peak detection" "0: No peak detection pure linear interpolation,?,?,?,?,?,?,?" newline bitfld.long 0x0 1.--2. "TYPE,Raw Bayer type" "0: RGGB,1: GRBG,2: GBRG,3: BGGR" bitfld.long 0x0 0. "ENABLE,None" "0: Bypass,1: Enable demosaicing" group.long 0x880++0x1B line.long 0x0 "DCMIPP_P1CCCR,DCMIPP Pipe1 ColorConv configuration register" bitfld.long 0x0 2. "CLAMP,Clamp the output samples" "0: Not activated (clamped to [0;255] by default),1: Activated depending on TYPE" bitfld.long 0x0 1. "TYPE,output samples type used while CLAMP is activated" "0: Clamped to [16;235] for Y and to [16;240] for U..,1: Clamped to [16;235] for R G and B" newline bitfld.long 0x0 0. "ENABLE,None" "0: ColorConv is bypassed,1: ColorConv is enabled" line.long 0x4 "DCMIPP_P1CCRR1,DCMIPP Pipe1 ColorConv red coefficient register 1" hexmask.long.word 0x4 16.--26. 1. "RG,Coefficient row 1 column 2 of the matrix" hexmask.long.word 0x4 0.--10. 1. "RR,Coefficient row 1 column 1 of the matrix" line.long 0x8 "DCMIPP_P1CCRR2,DCMIPP Pipe1 ColorConv red coefficient register 2" hexmask.long.word 0x8 16.--25. 1. "RA,Coefficient row 1 of the added column (signed integer value)" hexmask.long.word 0x8 0.--10. 1. "RB,Coefficient row 1 column 3 of the matrix" line.long 0xC "DCMIPP_P1CCGR1,DCMIPP Pipe1 ColorConv green coefficient register 1" hexmask.long.word 0xC 16.--26. 1. "GG,Coefficient row 2 column 2 of the matrix" hexmask.long.word 0xC 0.--10. 1. "GR,Coefficient row 2 column 1 of the matrix" line.long 0x10 "DCMIPP_P1CCGR2,DCMIPP Pipe1 ColorConv green coefficient register 2" hexmask.long.word 0x10 16.--25. 1. "GA,Coefficient row 2 of the added column (signed integer value)" hexmask.long.word 0x10 0.--10. 1. "GB,Coefficient row 2 column 3 of the matrix" line.long 0x14 "DCMIPP_P1CCBR1,DCMIPP Pipex ColorConv blue coefficient register 1" hexmask.long.word 0x14 16.--26. 1. "BG,Coefficient row 3 column 2 of the matrix" hexmask.long.word 0x14 0.--10. 1. "BR,Coefficient row 3 column 1 of the matrix" line.long 0x18 "DCMIPP_P1CCBR2,DCMIPP Pipe1 ColorConv blue coefficient register 2" hexmask.long.word 0x18 16.--25. 1. "BA,Coefficient row 3 of the added column (signed integer value)" hexmask.long.word 0x18 0.--10. 1. "BB,Coefficient row 3 column 3 of the matrix" group.long 0x8A0++0xB line.long 0x0 "DCMIPP_P1CTCR1,DCMIPP Pipe1 contrast control register 1" hexmask.long.byte 0x0 9.--14. 1. "LUM0,Luminance increase for input luminance of 0 (increase is idle with LUMx = 16)" bitfld.long 0x0 0. "ENABLE,None" "0: Bypass pixels are forwarded idle.,1: Enable contrast enhancement is applied on pixels." line.long 0x4 "DCMIPP_P1CTCR2,DCMIPP Pipe1 contrast control register 2" hexmask.long.byte 0x4 25.--30. 1. "LUM1,Luminance increase for input luminance of 32 (increase is idle with LUMx = 16)" hexmask.long.byte 0x4 17.--22. 1. "LUM2,Luminance increase for input luminance of 64 (increase is idle with LUMx = 16)" newline hexmask.long.byte 0x4 9.--14. 1. "LUM3,Luminance increase for input luminance of 96 (increase is idle with LUMx = 16)" hexmask.long.byte 0x4 1.--6. 1. "LUM4,Luminance increase for input luminance of 128 (increase is idle with LUMx = 16)" line.long 0x8 "DCMIPP_P1CTCR3,DCMIPP Pipe1 contrast control register 3" hexmask.long.byte 0x8 25.--30. 1. "LUM5,Luminance increase for input luminance of 160 (increase is idle with LUMx = 16)" hexmask.long.byte 0x8 17.--22. 1. "LUM6,Luminance increase for input luminance of 192 (increase is idle with LUMx = 16)" newline hexmask.long.byte 0x8 9.--14. 1. "LUM7,Luminance increase for input luminance of 224 (increase is idle with LUMx = 16)" hexmask.long.byte 0x8 1.--6. 1. "LUM8,Luminance increase for input luminance of 256 (increase is idle with LUMx = 16)" group.long 0x900++0x1B line.long 0x0 "DCMIPP_P1FCTCR,DCMIPP Pipex flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame,1: Capture requested for next frame" bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode. The received data are..,1: Snapshot mode (single frame). Once activated the.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P1CRSTR,DCMIPP Pipex crop window start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P1CRSZR,DCMIPP Pipex crop window size register" bitfld.long 0x8 31. "ENABLE,None" "0: Bypass all pixels are transmitted through (no..,1: Enable only the rectangle defined by VSIZE HSIZE.." hexmask.long.word 0x8 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high. If the value is maintained at 0 when enabling the crop thanks to the ENABLE bit the value is forced internally at 0xFFE which is the maximum value." newline hexmask.long.word 0x8 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide. If the value is maintained at 0 when enabling the crop by means of the ENABLE bit the value is forced internally at 0xFFE which is the maximum value." line.long 0xC "DCMIPP_P1DCCR,DCMIPP Pipex decimation register" bitfld.long 0xC 3.--4. "VDEC,Vertical decimation ratio" "0: All pixels are transmitted no vertical decimation,1: One line out of two transmitted,?,?" bitfld.long 0xC 1.--2. "HDEC,Horizontal decimation ratio" "0: All pixels are transmitted no horizontal..,1: One line out of two transmitted,?,?" newline bitfld.long 0xC 0. "ENABLE,None" "0: Bypass: decimation is not active all pixels are..,1: Enable: one pixel every 1 2 4 or 8 in H and V is.." line.long 0x10 "DCMIPP_P1DSCR,DCMIPP Pipex downsize configuration register" bitfld.long 0x10 31. "ENABLE,None" "0: Down scaler is bypassed,1: Down scaler is enabled" hexmask.long.word 0x10 16.--25. 1. "VDIV,Vertical division factor from 128 (8x) to 1023 (1x)" newline hexmask.long.word 0x10 0.--9. 1. "HDIV,Horizontal division factor from 128 (8x) to 1023 (1x)" line.long 0x14 "DCMIPP_P1DSRTIOR,DCMIPP Pipex downsize ratio register" hexmask.long.word 0x14 16.--31. 1. "VRATIO,Vertical ratio from 8192 (1x) to 65535 (8x)" hexmask.long.word 0x14 0.--15. 1. "HRATIO,Horizontal ratio from 8192 (1x) to 65535 (8x)" line.long 0x18 "DCMIPP_P1DSSZR,DCMIPP Pipex downsize destination size register" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" group.long 0x920++0x43 line.long 0x0 "DCMIPP_P1CMRICR,DCMIPP Pipex common ROI configuration register" bitfld.long 0x0 23. "ROI8EN,Region of interest 8 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 22. "ROI7EN,Region of interest 7 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 21. "ROI6EN,Region of interest 6 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 20. "ROI5EN,Region of interest 5 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 19. "ROI4EN,Region of interest 4 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 18. "ROI3EN,Region of interest 3 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 17. "ROI2EN,Region of interest 2 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 16. "ROI1EN,Region of interest 1 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 0.--1. "ROILSZ,Region of interest line size width" "0: Line width 1 pixel,1: Line width 2 pixels,2: Line width 4 pixels,3: Line width 8 pixels" line.long 0x4 "DCMIPP_P1RI1CR1,DCMIPP Pipe1 ROI1 configuration register 1" bitfld.long 0x4 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x4 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x4 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P1RI1CR2,DCMIPP Pipe1 ROI1 configuration register 2" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0xC "DCMIPP_P1RI2CR1,DCMIPP Pipe1 ROI2 configuration register 1" bitfld.long 0xC 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0xC 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0xC 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0xC 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0xC 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P1RI2CR2,DCMIPP Pipe1 ROI2 configuration register 2" hexmask.long.word 0x10 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x10 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x14 "DCMIPP_P1RI3CR1,DCMIPP Pipe1 ROI3 configuration register 1" bitfld.long 0x14 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x14 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x14 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x14 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x18 "DCMIPP_P1RI3CR2,DCMIPP Pipe1 ROI3 configuration register 2" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x1C "DCMIPP_P1RI4CR1,DCMIPP Pipe1 ROI4 configuration register 1" bitfld.long 0x1C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x1C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x1C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x1C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x1C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x20 "DCMIPP_P1RI4CR2,DCMIPP Pipe1 ROI4 configuration register 2" hexmask.long.word 0x20 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x20 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x24 "DCMIPP_P1RI5CR1,DCMIPP Pipe1 ROI5 configuration register 1" bitfld.long 0x24 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x24 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x24 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x24 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x24 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x28 "DCMIPP_P1RI5CR2,DCMIPP Pipe1 ROI5 configuration register 2" hexmask.long.word 0x28 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x28 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x2C "DCMIPP_P1RI6CR1,DCMIPP Pipe1 ROI6 configuration register 1" bitfld.long 0x2C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x2C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x2C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x2C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x2C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x30 "DCMIPP_P1RI6CR2,DCMIPP Pipe1 ROI6 configuration register 2" hexmask.long.word 0x30 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x30 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x34 "DCMIPP_P1RI7CR1,DCMIPP Pipe1 ROI7 configuration register 1" bitfld.long 0x34 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x34 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x34 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x34 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x34 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x38 "DCMIPP_P1RI7CR2,DCMIPP Pipe1 ROI7 configuration register 2" hexmask.long.word 0x38 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x38 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x3C "DCMIPP_P1RI8CR1,DCMIPP Pipe1 ROI8 configuration register 1" bitfld.long 0x3C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x3C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x3C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x3C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x3C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x40 "DCMIPP_P1RI8CR2,DCMIPP Pipe1 ROI8 configuration register 2" hexmask.long.word 0x40 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x40 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" group.long 0x970++0x3 line.long 0x0 "DCMIPP_P1GMCR,DCMIPP Pipex gamma configuration register" bitfld.long 0x0 0. "ENABLE,None" "0: Gamma is bypassed,1: Gamma is enabled" group.long 0x980++0x1B line.long 0x0 "DCMIPP_P1YUVCR,DCMIPP Pipe1 YUVConv configuration register" bitfld.long 0x0 2. "CLAMP,Clamp the output samples" "0: Not activated (clamped to [0;255] by default),1: Activated depending on TYPE" bitfld.long 0x0 1. "TYPE,Output samples type used while CLAMP is activated" "0: Clamped to [16;235] for Y and to [16;240] for U..,1: Clamped to [16;235] for R G and B" newline bitfld.long 0x0 0. "ENABLE,None" "0: ColorConv is bypassed,1: ColorConv is enabled" line.long 0x4 "DCMIPP_P1YUVRR1,DCMIPP Pipe1 YUVConv red coefficient register 1" hexmask.long.word 0x4 16.--26. 1. "RG,Coefficient row 1 column 2 of the matrix" hexmask.long.word 0x4 0.--10. 1. "RR,Coefficient row 1 column 1 of the matrix" line.long 0x8 "DCMIPP_P1YUVRR2,DCMIPP Pipe1 YUVConv red coefficient register 2" hexmask.long.word 0x8 16.--25. 1. "RA,Coefficient row 1 of the added column (signed integer value)" hexmask.long.word 0x8 0.--10. 1. "RB,Coefficient row 1 column 3 of the matrix" line.long 0xC "DCMIPP_P1YUVGR1,DCMIPP Pipe1 YUVConv green coefficient register 1" hexmask.long.word 0xC 16.--26. 1. "GG,Coefficient row 2 column 2 of the matrix" hexmask.long.word 0xC 0.--10. 1. "GR,Coefficient row 2 column 1 of the matrix" line.long 0x10 "DCMIPP_P1YUVGR2,DCMIPP Pipe1 YUVConv green coefficient register 2" hexmask.long.word 0x10 16.--25. 1. "GA,Coefficient row 2 of the added column (signed integer value)" hexmask.long.word 0x10 0.--10. 1. "GB,Coefficient row 2 column 3 of the matrix" line.long 0x14 "DCMIPP_P1YUVBR1,DCMIPP Pipe1 YUVConv blue coefficient register 1" hexmask.long.word 0x14 16.--26. 1. "BG,Coefficient row 3 column 2 of the matrix" hexmask.long.word 0x14 0.--10. 1. "BR,Coefficient row 3 column 1 of the matrix" line.long 0x18 "DCMIPP_P1YUVBR2,DCMIPP Pipe1 YUV blue coefficient register 2" hexmask.long.word 0x18 16.--25. 1. "BA,Coefficient row 3 of the added column (signed integer value)" hexmask.long.word 0x18 0.--10. 1. "BB,Coefficient row 3 column 3 of the matrix" group.long 0x9C0++0xF line.long 0x0 "DCMIPP_P1PPCR,DCMIPP Pipe1 pixel packer configuration register" bitfld.long 0x0 20. "LMAWE,Line multi address wrapping enable bit." "0: Line multi address wrapping disabled.,1: Line multi address wrapping enabled." bitfld.long 0x0 17.--19. "LMAWM,Line multi address wrapping modulo." "0: Wraps address after every line,1: Wraps address after two lines,2: Wraps address after four lines,3: Wraps address after eight lines,4: Wraps address after sixteen lines,5: Wraps address after 32 lines,6: Wraps address after 64 lines,7: Wraps address after 128 lines" newline bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe1 always..,1: Double buffer mode activated. Output pixels.." bitfld.long 0x0 13.--15. "LINEMULT,Amount of capture completed lines for LINE Event and Interrupt" "0: Event after one line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 4. "SWAPRB,Swaps R-vs-B components if RGB and U-vs-V components if YUV" "0: No swap of R-vs-B (U-vs-V),1: Swap active" hexmask.long.byte 0x0 0.--3. 1. "FORMAT,Memory format" line.long 0x4 "DCMIPP_P1PPM0AR1,DCMIPP Pipe1 pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P1PPM0AR2,DCMIPP Pipe1 pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" line.long 0xC "DCMIPP_P1PPM0PR,DCMIPP Pipex pixel packer Memory0 pitch register" hexmask.long.word 0xC 0.--14. 1. "PITCH,Number of bytes between the address of two consecutive lines." rgroup.long 0x9D0++0x3 line.long 0x0 "DCMIPP_P1STM0AR,DCMIPP Pipex status Memory0 address register" hexmask.long 0x0 0.--31. 1. "M0A,Memory0 address" group.long 0x9D4++0xB line.long 0x0 "DCMIPP_P1PPM1AR1,DCMIPP Pipex pixel packer Memory1 address register 1" hexmask.long 0x0 0.--31. 1. "M1A,Memory1 address" line.long 0x4 "DCMIPP_P1PPM1AR2,DCMIPP Pipex pixel packer Memory1 address register 2" hexmask.long 0x4 0.--31. 1. "M1A,Memory1 address" line.long 0x8 "DCMIPP_P1PPM1PR,DCMIPP Pipex pixel packer Memory1 pitch register" hexmask.long.word 0x8 0.--14. 1. "PITCH,Number of bytes between the address of two consecutive lines." rgroup.long 0x9E0++0x3 line.long 0x0 "DCMIPP_P1STM1AR,DCMIPP Pipex status Memory1 address register" hexmask.long 0x0 0.--31. 1. "M1A,Memory1 address" group.long 0x9E4++0x7 line.long 0x0 "DCMIPP_P1PPM2AR1,DCMIPP Pipex pixel packer memory2 address register 1" hexmask.long 0x0 0.--31. 1. "M2A,Memory 2 address" line.long 0x4 "DCMIPP_P1PPM2AR2,DCMIPP Pipex pixel packer memory2 address register 2" hexmask.long 0x4 0.--31. 1. "M2A,Memory 2 address" rgroup.long 0x9F0++0x3 line.long 0x0 "DCMIPP_P1STM2AR,DCMIPP Pipex status Memory2 address register" hexmask.long 0x0 0.--31. 1. "M2A,Memory2 address" group.long 0x9F4++0x3 line.long 0x0 "DCMIPP_P1IER,DCMIPP Pipe1 interrupt enable register" bitfld.long 0x0 7. "OVRIE,Overrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the AXI master is.." bitfld.long 0x0 2. "VSYNCIE,VSYNC interrupt enable" "0: No interrupt generation,1: An interrupt is generated on each VSYNC.." newline bitfld.long 0x0 1. "FRAMEIE,Frame capture completed interrupt enable" "0: No interrupt generation,1: An interrupt is generated after the full capture.." bitfld.long 0x0 0. "LINEIE,Multi-line capture completed interrupt enable" "0: No interrupt generation when the line is received,1: An interrupt is generated after the full capture.." rgroup.long 0x9F8++0x3 line.long 0x0 "DCMIPP_P1SR,DCMIPP Pipe1 status register" bitfld.long 0x0 23. "CPTACT,Capture immediate status" "0: Capture currently inactive,1: Capture currently active" bitfld.long 0x0 17. "LSTFRM,Last frame LSB bit sampled at frame capture complete event. The information is extracted from the frame data number which can be delivered by the camera through the CSI2 interface." "0,1" newline bitfld.long 0x0 16. "LSTLINE,Last line LSB bit sampled at frame capture complete event." "0,1" bitfld.long 0x0 7. "OVRF,Overrun raw interrupt status" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.." newline bitfld.long 0x0 2. "VSYNCF,VSYNC raw interrupt status" "0,1" bitfld.long 0x0 1. "FRAMEF,Frame capture completed raw interrupt status" "0: No capture or ongoing capture,1: All data of a frame have been captured." newline bitfld.long 0x0 0. "LINEF,Multi-line capture completed raw interrupt status" "0,1" wgroup.long 0x9FC++0x3 line.long 0x0 "DCMIPP_P1FCR,DCMIPP Pipe1 interrupt clear register" bitfld.long 0x0 7. "COVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 2. "CVSYNCF,Vertical synchronization interrupt status clear" "0,1" newline bitfld.long 0x0 1. "CFRAMEF,Frame capture complete interrupt status clear" "0,1" bitfld.long 0x0 0. "CLINEF,Multi-line capture complete interrupt status clear" "0,1" rgroup.long 0xA04++0x3 line.long 0x0 "DCMIPP_P1CFSCR,DCMIPP Pipe1 current flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Current activation of PipeN" "0: Pipe disabled,1: Pipe enabled can start capturing with CPTMODE.." bitfld.long 0x0 30. "FDTFEN,Current force data type format enable" "0: Disable force data type format. The data type..,1: Enable force data type format. When the data.." newline hexmask.long.byte 0x0 24.--29. 1. "FDTF,Current force data type format" bitfld.long 0x0 19.--20. "VC,Current flow selection mode" "0,1,2,3" newline bitfld.long 0x0 18. "PIPEDIFF,Current differentiates Pipe2 vs. Pipe1" "0: Pipe2 gets Pipe1 pixels after their processing..,1: Pipe1 gets pixels from only VC/DTID configured.." bitfld.long 0x0 16.--17. "DTMODE,Flow selection mode" "0: Only flow DTID A from the selected virtual..,1: Flows DTIDA and DTIDB from the selected virtual..,?,?" newline hexmask.long.byte 0x0 8.--13. 1. "DTIDB,Current data type ID B" hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Current data type ID A" rgroup.long 0xA24++0x3 line.long 0x0 "DCMIPP_P1CBPRCR,DCMIPP Pipe1 current bad pixel removal register" bitfld.long 0x0 1.--3. "STRENGTH,Current strength (aggressiveness) of the bad pixel detection:" "0: the filter is fairly tolerant: only a few pixels..,?,?,?,?,?,?,?" bitfld.long 0x0 0. "ENABLE,Current status of enable bit" "0: Bypass: bad pixel removal is not active all..,1: Enable: if bad pixel are detected they are.." rgroup.long 0xA40++0xB line.long 0x0 "DCMIPP_P1CBLCCR,DCMIPP Pipe1 current black level calibration control register" hexmask.long.byte 0x0 24.--31. 1. "BLCR,Current black level calibration - Red" hexmask.long.byte 0x0 16.--23. 1. "BLCG,Current black level calibration - Green" newline hexmask.long.byte 0x0 8.--15. 1. "BLCB,Current black level calibration - Blue" bitfld.long 0x0 0. "ENABLE,For current black level calibration" "0: Bypass: black level calibration is not active..,1: Enable: the BLCR G B are subtracted." line.long 0x4 "DCMIPP_P1CEXCR1,DCMIPP Pipe1 current exposure control register 1" bitfld.long 0x4 28.--30. "SHFR,Current exposure shift - Red" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 20.--27. 1. "MULTR,Current exposure multiplier - Red" newline bitfld.long 0x4 0. "ENABLE,for exposure control (multiplication and shift)" "0: Bypass: exposure multiplier and shift are not..,1: Enable: the exposure multiplication and shift is.." line.long 0x8 "DCMIPP_P1CEXCR2,DCMIPP Pipe1 current exposure control register 2" bitfld.long 0x8 28.--30. "SHFG,Current exposure shift - Green" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 20.--27. 1. "MULTG,Current exposure multiplier - Green" newline bitfld.long 0x8 12.--14. "SHFB,Current exposure shift - Blue" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 4.--11. 1. "MULTB,Current exposure multiplier - Blue" rgroup.long 0xA50++0x13 line.long 0x0 "DCMIPP_P1CST1CR,DCMIPP Pipe1 current statistics 1 control register" hexmask.long.tbyte 0x0 8.--31. 1. "ACCU,Current accumulation result divided by 256." bitfld.long 0x0 7. "MODE,Current statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." newline bitfld.long 0x0 4.--6. "SRC,Current source of statistics" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "BINS,Current bin definition" "0: AllPixels: Accu is incremented of Component if 0..,1: NoExt16: Accu is incremented of Component if 16..,?,?" newline bitfld.long 0x0 0. "ENABLE,Current enable bit value" "0: Disabled: statistics are not accumulated.,1: Enable: statistics are accumulated" line.long 0x4 "DCMIPP_P1CST2CR,DCMIPP Pipe1 current statistics 2 control register" hexmask.long.tbyte 0x4 8.--31. 1. "ACCU,Accumulation result divided by 256." bitfld.long 0x4 7. "MODE,Statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." newline bitfld.long 0x4 4.--6. "SRC,Statistics source" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "BINS,Bin definition" "0: AllPixels: Accu is incremented of Component if 0..,1: NoExt16: Accu is incremented of Component if 16..,?,?" newline bitfld.long 0x4 0. "ENABLE,None" "0: Disabled: statistics are not accumulated.,1: Enable: statistics are accumulated" line.long 0x8 "DCMIPP_P1CST3CR,DCMIPP Pipe1 current statistics 3 control register" hexmask.long.tbyte 0x8 8.--31. 1. "ACCU,Accumulation result divided by 256." bitfld.long 0x8 7. "MODE,Statistics mode" "0: Average: accumulates the 8-bit component value..,1: Bins: accumulates 256 for each considered pixel.." newline bitfld.long 0x8 4.--6. "SRC,Statistics source" "0,1,2,3,4,5,6,7" bitfld.long 0x8 2.--3. "BINS,Current bin definition" "0: AllPixels: Accu is incremented of Component if 0..,1: NoExt16: Accu is incremented of Component if 16..,?,?" newline bitfld.long 0x8 0. "ENABLE,None" "0: Disabled: statistics are not accumulated.,1: Enable: statistics are accumulated" line.long 0xC "DCMIPP_P1CSTSTR,DCMIPP Pipe1 current statistics window start register" hexmask.long.word 0xC 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" hexmask.long.word 0xC 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P1CSTSZR,DCMIPP Pipe1 current statistics window size register" bitfld.long 0x10 31. "CROPEN,Current CROPEN bit value" "0: Bypass all pixels are used to compute the..,1: Enable only the rectangle defined by VSTART.." hexmask.long.word 0x10 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" newline hexmask.long.word 0x10 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" rgroup.long 0xA80++0x1B line.long 0x0 "DCMIPP_P1CCCCR,DCMIPP Pipe1 current ColorConv configuration register" bitfld.long 0x0 2. "CLAMP,Clamp the output samples" "0: Not activated (clamped to [0;255] by default),1: Activated depending on TYPE" bitfld.long 0x0 1. "TYPE,Output samples type used while CLAMP is activated" "0: clamped to [16;235] for Y and to [16;240] for U..,1: clamped to [16;235] for R G and B" newline bitfld.long 0x0 0. "ENABLE,Current value applied" "0: ColorConv is bypassed,1: ColorConv is enabled" line.long 0x4 "DCMIPP_P1CCCRR1,DCMIPP Pipe1 current ColorConv red coefficient register 1" hexmask.long.word 0x4 16.--26. 1. "RG,Current coefficient row 1 column 2 of the matrix" hexmask.long.word 0x4 0.--10. 1. "RR,Current coefficient row 1 column 1 of the matrix" line.long 0x8 "DCMIPP_P1CCCRR2,DCMIPP Pipe1 current ColorConv red coefficient register 2" hexmask.long.word 0x8 16.--25. 1. "RA,Current coefficient row 1 of the added column (signed integer value)" hexmask.long.word 0x8 0.--10. 1. "RB,Current coefficient row 1 column 3 of the matrix" line.long 0xC "DCMIPP_P1CCCGR1,DCMIPP Pipe1 current ColorConv green coefficient register 1" hexmask.long.word 0xC 16.--26. 1. "GG,Current coefficient row 2 column 2 of the matrix" hexmask.long.word 0xC 0.--10. 1. "GR,Current coefficient row 2 column 1 of the matrix" line.long 0x10 "DCMIPP_P1CCCGR2,DCMIPP Pipe1 current ColorConv green coefficient register 2" hexmask.long.word 0x10 16.--25. 1. "GA,Current coefficient row 2 of the added column (signed integer value)" hexmask.long.word 0x10 0.--10. 1. "GB,Current coefficient row 2 column 3 of the matrix" line.long 0x14 "DCMIPP_P1CCCBR1,DCMIPP Pipex current ColorConv blue coefficient register 1" hexmask.long.word 0x14 16.--26. 1. "BG,Current coefficient row 3 column 2 of the matrix" hexmask.long.word 0x14 0.--10. 1. "BR,Current coefficient row 3 column 1 of the matrix" line.long 0x18 "DCMIPP_P1CCCBR2,DCMIPP Pipe1 current ColorConv blue coefficient register 2" hexmask.long.word 0x18 16.--25. 1. "BA,Current coefficient row 3 of the added column (signed integer value)" hexmask.long.word 0x18 0.--10. 1. "BB,Current coefficient row 3 column 3 of the matrix" rgroup.long 0xAA0++0xB line.long 0x0 "DCMIPP_P1CCTCR1,DCMIPP Pipe1 current contrast control register 1" hexmask.long.byte 0x0 9.--14. 1. "LUM0,Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16)" bitfld.long 0x0 0. "ENABLE,Current ENABLE bit value" "0: Bypass pixels are forwarded idle.,1: Enable contrast enhancement is applied on pixels." line.long 0x4 "DCMIPP_P1CCTCR2,DCMIPP Pipe1 current contrast control register 2" hexmask.long.byte 0x4 25.--30. 1. "LUM1,Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16)" hexmask.long.byte 0x4 17.--22. 1. "LUM2,Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16)" newline hexmask.long.byte 0x4 9.--14. 1. "LUM3,Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16)" hexmask.long.byte 0x4 1.--6. 1. "LUM4,Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16)" line.long 0x8 "DCMIPP_P1CCTCR3,DCMIPP Pipe1 current contrast control register 3" hexmask.long.byte 0x8 25.--30. 1. "LUM5,Luminance increase for input luminance of 160 (increase is idle with LUMx = 16)" hexmask.long.byte 0x8 17.--22. 1. "LUM6,Luminance increase for input luminance of 192 (increase is idle with LUMx = 16)" newline hexmask.long.byte 0x8 9.--14. 1. "LUM7,Luminance increase for input luminance of 224 (increase is idle with LUMx = 16)" hexmask.long.byte 0x8 1.--6. 1. "LUM8,Luminance increase for input luminance of 256 (increase is idle with LUMx = 16)" rgroup.long 0xB00++0xB line.long 0x0 "DCMIPP_P1CFCTCR,DCMIPP Pipex current flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame.,1: Capture requested for next frame." bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode - Received data are..,1: Snapshot mode (single frame) - Once activated.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P1CCRSTR,DCMIPP Pipex current crop window start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P1CCRSZR,DCMIPP Pipex current crop window size register" bitfld.long 0x8 31. "ENABLE,Current ENABLE bit value." "0: Bypass all pixels are transmitted through (no..,1: Enable only the rectangle defined by VSIZE HSIZE.." hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" newline hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" group.long 0xB0C++0x3 line.long 0x0 "DCMIPP_P1CDCCR,DCMIPP Pipex current decimation register" bitfld.long 0x0 3.--4. "VDEC,Vertical decimation ratio" "0: All pixels are transmitted no vertical decimation,1: One line out of two transmitted,?,?" bitfld.long 0x0 1.--2. "HDEC,Horizontal decimation ratio" "0: All pixels are transmitted no horizontal..,1: One line out of two transmitted,?,?" newline bitfld.long 0x0 0. "ENABLE,None" "0: Bypass: decimation is not active all pixels are..,1: Enable: one pixel every 1 2 4 or 8 in H and V is.." rgroup.long 0xB10++0xB line.long 0x0 "DCMIPP_P1CDSCR,DCMIPP Pipex current downsize configuration register" bitfld.long 0x0 31. "ENABLE,Current value of bit ENABLE" "0: Down scaler is bypassed,1: Down scaler is enabled" hexmask.long.word 0x0 16.--25. 1. "VDIV,Current vertical division factor from 128 (8x) to 1023 (1x)" newline hexmask.long.word 0x0 0.--9. 1. "HDIV,Current horizontal division factor from 128 (8x) to 1023 (1x)" line.long 0x4 "DCMIPP_P1CDSRTIOR,DCMIPP Pipex current downsize ratio register" hexmask.long.word 0x4 16.--31. 1. "VRATIO,Current vertical ratio from 8192 (1x) to 65535 (8x)" hexmask.long.word 0x4 0.--15. 1. "HRATIO,Current horizontal ratio from 8192 (1x) to 65535 (8x)" line.long 0x8 "DCMIPP_P1CDSSZR,DCMIPP Pipex current downsize destination size register" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" rgroup.long 0xB20++0x43 line.long 0x0 "DCMIPP_P1CCMRICR,DCMIPP Pipex current common ROI configuration register" bitfld.long 0x0 23. "ROI8EN,Current region of interest 8 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 22. "ROI7EN,Current region of interest 7 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 21. "ROI6EN,Current region of interest 6 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 20. "ROI5EN,Current region of interest 5 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 19. "ROI4EN,Current region of interest 4 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 18. "ROI3EN,Current region of interest 3 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 17. "ROI2EN,Current region of interest 2 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 16. "ROI1EN,Current region of interest 1 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 0.--1. "ROILSZ,Current region of interest line size width" "0: Line width 1 pixel,1: Line width 2 pixels,2: Line width 4 pixels,3: Line width 8 pixels" line.long 0x4 "DCMIPP_P1CRI1CR1,DCMIPP Pipe1 current ROI1 configuration register 1" bitfld.long 0x4 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x4 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x4 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P1CRI1CR2,DCMIPP Pipe1 current ROI1 configuration register 2" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0xC "DCMIPP_P1CRI2CR1,DCMIPP Pipe1 current ROI2 configuration register 1" bitfld.long 0xC 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0xC 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0xC 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0xC 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0xC 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P1CRI2CR2,DCMIPP Pipe1 current ROI2 configuration register 2" hexmask.long.word 0x10 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x10 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x14 "DCMIPP_P1CRI3CR1,DCMIPP Pipe1 current ROI3 configuration register 1" bitfld.long 0x14 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x14 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x14 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x14 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x18 "DCMIPP_P1CRI3CR2,DCMIPP Pipe1 current ROI3 configuration register 2" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x1C "DCMIPP_P1CRI4CR1,DCMIPP Pipe1 current ROI4 configuration register 1" bitfld.long 0x1C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x1C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x1C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x1C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x1C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x20 "DCMIPP_P1CRI4CR2,DCMIPP Pipe1 current ROI4 configuration register 2" hexmask.long.word 0x20 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x20 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x24 "DCMIPP_P1CRI5CR1,DCMIPP Pipe1 current ROI5 configuration register 1" bitfld.long 0x24 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x24 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x24 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x24 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x24 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x28 "DCMIPP_P1CRI5CR2,DCMIPP Pipe1 current ROI5 configuration register 2" hexmask.long.word 0x28 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x28 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x2C "DCMIPP_P1CRI6CR1,DCMIPP Pipe1 current ROI6 configuration register 1" bitfld.long 0x2C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x2C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x2C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x2C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x2C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x30 "DCMIPP_P1CRI6CR2,DCMIPP Pipe1 current ROI6 configuration register 2" hexmask.long.word 0x30 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x30 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x34 "DCMIPP_P1CRI7CR1,DCMIPP Pipe1 current ROI7 configuration register 1" bitfld.long 0x34 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x34 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x34 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x34 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x34 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x38 "DCMIPP_P1CRI7CR2,DCMIPP Pipe1 current ROI7 configuration register 2" hexmask.long.word 0x38 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x38 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x3C "DCMIPP_P1CRI8CR1,DCMIPP Pipe1 current ROI8 configuration register 1" bitfld.long 0x3C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x3C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x3C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x3C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x3C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x40 "DCMIPP_P1CRI8CR2,DCMIPP Pipe1 current ROI8 configuration register 2" hexmask.long.word 0x40 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x40 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" rgroup.long 0xBC0++0xF line.long 0x0 "DCMIPP_P1CPPCR,DCMIPP Pipe1 current pixel packer configuration register" bitfld.long 0x0 20. "LMAWE,Line multi address wrapping enable bit" "0: Line multi address wrapping disabled.,1: Line multi address wrapping enabled." bitfld.long 0x0 17.--19. "LMAWM,Line multi address wrapping modulo" "0: Wraps address after every line,1: Wraps address after two lines,2: Wraps address after four lines,3: Wraps address after eight lines,4: Wraps address after sixteen lines,5: Wraps address after 32 lines,6: Wraps address after 64 lines,7: Wraps address after 128 lines" newline bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe1 always..,1: Double buffer mode activated. Output pixels.." bitfld.long 0x0 13.--15. "LINEMULT,Amount of capture completed lines for LINE Event and Interrupt" "0: Event after one line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 4. "SWAPRB,Swaps R-vs-B components if RGB and U-vs-V components if YUV" "0: No swap of R-vs-B (U-vs-V),1: Swap active" hexmask.long.byte 0x0 0.--3. 1. "FORMAT,Memory format" line.long 0x4 "DCMIPP_P1CPPM0AR1,DCMIPP Pipe1 current pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P1CPPM0AR2,DCMIPP Pipe1 current pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" line.long 0xC "DCMIPP_P1CPPM0PR,DCMIPP Pipex current pixel packer Memory0 pitch register" hexmask.long.word 0xC 0.--14. 1. "PITCH,Current number of bytes between the address of two consecutive lines." rgroup.long 0xBD4++0xB line.long 0x0 "DCMIPP_P1CPPM1AR1,DCMIPP Pipex current pixel packer Memory1 address register 1" hexmask.long 0x0 0.--31. 1. "M1A,Memory1 address" line.long 0x4 "DCMIPP_P1CPPM1AR2,DCMIPP Pipex current pixel packer Memory1 address register 2" hexmask.long 0x4 0.--31. 1. "M1A,Memory1 address" line.long 0x8 "DCMIPP_P1CPPM1PR,DCMIPP Pipex current pixel packer Memory1 pitch register" hexmask.long.word 0x8 0.--14. 1. "PITCH,Current number of bytes between the address of two consecutive lines" rgroup.long 0xBE4++0x7 line.long 0x0 "DCMIPP_P1CPPM2AR1,DCMIPP Pipex current pixel packer Memory2 address register 1" hexmask.long 0x0 0.--31. 1. "M2A,Memory 2 address" line.long 0x4 "DCMIPP_P1CPPM2AR2,DCMIPP Pipex current pixel packer Memory2 address register 1" hexmask.long 0x4 0.--31. 1. "M2A,Memory 2 address" group.long 0xC04++0x3 line.long 0x0 "DCMIPP_P2FSCR,DCMIPP Pipe2 flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Activation of PipeN" "0: PipeN disabled,1: PipeN enabled can start capturing with CPTMODE.." bitfld.long 0x0 30. "FDTFEN,Force data type format enable" "0: Disable force data type format. The data type..,1: Enable force data type format. When the data.." newline hexmask.long.byte 0x0 24.--29. 1. "FDTF,Force data type format" bitfld.long 0x0 19.--20. "VC,Flow selection mode" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Data type ID" group.long 0xD00++0x1B line.long 0x0 "DCMIPP_P2FCTCR,DCMIPP Pipex flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame,1: Capture requested for next frame" bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode. The received data are..,1: Snapshot mode (single frame). Once activated the.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P2CRSTR,DCMIPP Pipex crop window start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P2CRSZR,DCMIPP Pipex crop window size register" bitfld.long 0x8 31. "ENABLE,None" "0: Bypass all pixels are transmitted through (no..,1: Enable only the rectangle defined by VSIZE HSIZE.." hexmask.long.word 0x8 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high. If the value is maintained at 0 when enabling the crop thanks to the ENABLE bit the value is forced internally at 0xFFE which is the maximum value." newline hexmask.long.word 0x8 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide. If the value is maintained at 0 when enabling the crop by means of the ENABLE bit the value is forced internally at 0xFFE which is the maximum value." line.long 0xC "DCMIPP_P2DCCR,DCMIPP Pipex decimation register" bitfld.long 0xC 3.--4. "VDEC,Vertical decimation ratio" "0: All pixels are transmitted no vertical decimation,1: One line out of two transmitted,?,?" bitfld.long 0xC 1.--2. "HDEC,Horizontal decimation ratio" "0: All pixels are transmitted no horizontal..,1: One line out of two transmitted,?,?" newline bitfld.long 0xC 0. "ENABLE,None" "0: Bypass: decimation is not active all pixels are..,1: Enable: one pixel every 1 2 4 or 8 in H and V is.." line.long 0x10 "DCMIPP_P2DSCR,DCMIPP Pipex downsize configuration register" bitfld.long 0x10 31. "ENABLE,None" "0: Down scaler is bypassed,1: Down scaler is enabled" hexmask.long.word 0x10 16.--25. 1. "VDIV,Vertical division factor from 128 (8x) to 1023 (1x)" newline hexmask.long.word 0x10 0.--9. 1. "HDIV,Horizontal division factor from 128 (8x) to 1023 (1x)" line.long 0x14 "DCMIPP_P2DSRTIOR,DCMIPP Pipex downsize ratio register" hexmask.long.word 0x14 16.--31. 1. "VRATIO,Vertical ratio from 8192 (1x) to 65535 (8x)" hexmask.long.word 0x14 0.--15. 1. "HRATIO,Horizontal ratio from 8192 (1x) to 65535 (8x)" line.long 0x18 "DCMIPP_P2DSSZR,DCMIPP Pipex downsize destination size register" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" group.long 0xD20++0x43 line.long 0x0 "DCMIPP_P2CMRICR,DCMIPP Pipex common ROI configuration register" bitfld.long 0x0 23. "ROI8EN,Region of interest 8 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 22. "ROI7EN,Region of interest 7 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 21. "ROI6EN,Region of interest 6 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 20. "ROI5EN,Region of interest 5 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 19. "ROI4EN,Region of interest 4 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 18. "ROI3EN,Region of interest 3 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 17. "ROI2EN,Region of interest 2 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 16. "ROI1EN,Region of interest 1 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 0.--1. "ROILSZ,Region of interest line size width" "0: Line width 1 pixel,1: Line width 2 pixels,2: Line width 4 pixels,3: Line width 8 pixels" line.long 0x4 "DCMIPP_P2RI1CR1,DCMIPP Pipe2 ROI1 configuration register 1" bitfld.long 0x4 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x4 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x4 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P2RI1CR2,DCMIPP Pipe2 ROI1 configuration register 2" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0xC "DCMIPP_P2RI2CR1,DCMIPP Pipe2 ROI2 configuration register 1" bitfld.long 0xC 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0xC 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0xC 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0xC 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0xC 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P2RI2CR2,DCMIPP Pipe2 ROI2 configuration register 2" hexmask.long.word 0x10 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x10 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x14 "DCMIPP_P2RI3CR1,DCMIPP Pipe2 ROI3 configuration register 1" bitfld.long 0x14 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x14 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x14 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x14 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x18 "DCMIPP_P2RI3CR2,DCMIPP Pipe2 ROI3 configuration register 2" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x1C "DCMIPP_P2RI4CR1,DCMIPP Pipe2 ROI4 configuration register 1" bitfld.long 0x1C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x1C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x1C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x1C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x1C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x20 "DCMIPP_P2RI4CR2,DCMIPP Pipe2 ROI4 configuration register 2" hexmask.long.word 0x20 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x20 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x24 "DCMIPP_P2RI5CR1,DCMIPP Pipe2 ROI5 configuration register 1" bitfld.long 0x24 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x24 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x24 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x24 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x24 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x28 "DCMIPP_P2RI5CR2,DCMIPP Pipe2 ROI5 configuration register 2" hexmask.long.word 0x28 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x28 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x2C "DCMIPP_P2RI6CR1,DCMIPP Pipe2 ROI6 configuration register 1" bitfld.long 0x2C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x2C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x2C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x2C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x2C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x30 "DCMIPP_P2RI6CR2,DCMIPP Pipe2 ROI6 configuration register 2" hexmask.long.word 0x30 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x30 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x34 "DCMIPP_P2RI7CR1,DCMIPP Pipe2 ROI7 configuration register 1" bitfld.long 0x34 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x34 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x34 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x34 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x34 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x38 "DCMIPP_P2RI7CR2,DCMIPP Pipe2 ROI7 configuration register 2" hexmask.long.word 0x38 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x38 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" line.long 0x3C "DCMIPP_P2RI8CR1,DCMIPP Pipe2 ROI8 configuration register 1" bitfld.long 0x3C 28.--29. "CLR,Color line red" "0,1,2,3" hexmask.long.word 0x3C 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high" newline bitfld.long 0x3C 14.--15. "CLG,Color line green" "0,1,2,3" bitfld.long 0x3C 12.--13. "CLB,Color line blue" "0,1,2,3" newline hexmask.long.word 0x3C 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 pixels wide" line.long 0x40 "DCMIPP_P2RI8CR2,DCMIPP Pipe2 ROI8 configuration register 2" hexmask.long.word 0x40 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high" hexmask.long.word 0x40 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 pixels wide" group.long 0xD70++0x3 line.long 0x0 "DCMIPP_P2GMCR,DCMIPP Pipex gamma configuration register" bitfld.long 0x0 0. "ENABLE,None" "0: Gamma is bypassed,1: Gamma is enabled" group.long 0xDC0++0xF line.long 0x0 "DCMIPP_P2PPCR,DCMIPP Pipe2 pixel packer configuration register" bitfld.long 0x0 20. "LMAWE,Line multi address wrapping enable bit" "0: Line multi address wrapping disabled.,1: Line multi address wrapping enabled." bitfld.long 0x0 17.--19. "LMAWM,Line multi address wrapping modulo" "0: Wraps address after every line,1: Wraps address after two lines,2: Wraps address after four lines,3: Wraps address after eight lines,4: Wraps address after sixteen lines,5: Wraps address after 32 lines,6: Wraps address after 64 lines,7: Wraps address after 128 lines" newline bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe2 is always..,1: Double buffer mode activated. Dump address.." bitfld.long 0x0 13.--15. "LINEMULT,Amount of capture completed lines for LINE event and interrupt" "0: Event after every line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 4. "SWAPRB,Swaps R-vs-B components if RGB and if YUV swaps U-vs-V components" "0: No swap of R-vs-B (U-vs-V),1: Swap active." hexmask.long.byte 0x0 0.--3. 1. "FORMAT,Memory format (only coplanar formats are supported in Pipe2)" line.long 0x4 "DCMIPP_P2PPM0AR1,DCMIPP Pipe2 pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P2PPM0AR2,DCMIPP Pipe2 pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" line.long 0xC "DCMIPP_P2PPM0PR,DCMIPP Pipex pixel packer Memory0 pitch register" hexmask.long.word 0xC 0.--14. 1. "PITCH,Number of bytes between the address of two consecutive lines." rgroup.long 0xDD0++0x3 line.long 0x0 "DCMIPP_P2STM0AR,DCMIPP Pipex status Memory0 address register" hexmask.long 0x0 0.--31. 1. "M0A,Memory0 address" group.long 0xDF4++0x3 line.long 0x0 "DCMIPP_P2IER,DCMIPP Pipe2 interrupt enable register" bitfld.long 0x0 7. "OVRIE,Overrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the AXI master is.." bitfld.long 0x0 2. "VSYNCIE,VSYNC interrupt enable" "0: No interrupt generation,1: An interrupt is generated on each VSYNC.." newline bitfld.long 0x0 1. "FRAMEIE,Frame capture completed interrupt enable" "0: No interrupt generation,1: An interrupt is generated after the full capture.." bitfld.long 0x0 0. "LINEIE,Multi-line capture completed interrupt enable" "0: No interrupt generation when the line is received,1: An interrupt is generated after the full capture.." rgroup.long 0xDF8++0x3 line.long 0x0 "DCMIPP_P2SR,DCMIPP Pipe2 status register" bitfld.long 0x0 23. "CPTACT,Capture immediate status" "0: Capture currently inactive,1: Capture currently active" bitfld.long 0x0 17. "LSTFRM,Last frame LSB bit sampled at frame capture complete event. The information is extracted from the frame data number which can be delivered by the camera through the CSI2 interface." "0,1" newline bitfld.long 0x0 16. "LSTLINE,Last line LSB bit sampled at frame capture complete event." "0,1" bitfld.long 0x0 7. "OVRF,Overrun raw interrupt status" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and data of this.." newline bitfld.long 0x0 2. "VSYNCF,VSYNC raw interrupt status" "0,1" bitfld.long 0x0 1. "FRAMEF,Frame capture completed raw interrupt status" "0: No capture or ongoing capture,1: All data of a frame have been captured" newline bitfld.long 0x0 0. "LINEF,Multi-line capture completed raw interrupt status" "0,1" wgroup.long 0xDFC++0x3 line.long 0x0 "DCMIPP_P2FCR,DCMIPP Pipe2 interrupt clear register" bitfld.long 0x0 7. "COVRF,Overrun interrupt status clear" "0,1" bitfld.long 0x0 2. "CVSYNCF,Vertical synchronization interrupt status clear" "0,1" newline bitfld.long 0x0 1. "CFRAMEF,Frame capture complete interrupt status clear" "0,1" bitfld.long 0x0 0. "CLINEF,Multi-line capture complete interrupt status clear" "0,1" rgroup.long 0xE04++0x3 line.long 0x0 "DCMIPP_P2CFSCR,DCMIPP Pipe2 current flow selection configuration register" bitfld.long 0x0 31. "PIPEN,Current activation of PipeN" "0: Pipe disabled,1: Pipe enabled can start capturing with CPTMODE.." bitfld.long 0x0 30. "FDTFEN,Current force data type format enable" "0: Disable force data type format. The data type..,1: Enable force data type format. When data type.." newline hexmask.long.byte 0x0 24.--29. 1. "FDTF,Current force data type format" bitfld.long 0x0 19.--20. "VC,Current flow selection mode" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DTIDA,Current data type ID" rgroup.long 0xF00++0xB line.long 0x0 "DCMIPP_P2CFCTCR,DCMIPP Pipex current flow control configuration register" bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame.,1: Capture requested for next frame." bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode - Received data are..,1: Snapshot mode (single frame) - Once activated.." newline bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.." line.long 0x4 "DCMIPP_P2CCRSTR,DCMIPP Pipex current crop window start register" hexmask.long.word 0x4 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" hexmask.long.word 0x4 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P2CCRSZR,DCMIPP Pipex current crop window size register" bitfld.long 0x8 31. "ENABLE,Current ENABLE bit value." "0: Bypass all pixels are transmitted through (no..,1: Enable only the rectangle defined by VSIZE HSIZE.." hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" newline hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" group.long 0xF0C++0x3 line.long 0x0 "DCMIPP_P2CDCCR,DCMIPP Pipex current decimation register" bitfld.long 0x0 3.--4. "VDEC,Vertical decimation ratio" "0: All pixels are transmitted no vertical decimation,1: One line out of two transmitted,?,?" bitfld.long 0x0 1.--2. "HDEC,Horizontal decimation ratio" "0: All pixels are transmitted no horizontal..,1: One line out of two transmitted,?,?" newline bitfld.long 0x0 0. "ENABLE,None" "0: Bypass: decimation is not active all pixels are..,1: Enable: one pixel every 1 2 4 or 8 in H and V is.." rgroup.long 0xF10++0xB line.long 0x0 "DCMIPP_P2CDSCR,DCMIPP Pipex current downsize configuration register" bitfld.long 0x0 31. "ENABLE,Current value of bit ENABLE" "0: Down scaler is bypassed,1: Down scaler is enabled" hexmask.long.word 0x0 16.--25. 1. "VDIV,Current vertical division factor from 128 (8x) to 1023 (1x)" newline hexmask.long.word 0x0 0.--9. 1. "HDIV,Current horizontal division factor from 128 (8x) to 1023 (1x)" line.long 0x4 "DCMIPP_P2CDSRTIOR,DCMIPP Pipex current downsize ratio register" hexmask.long.word 0x4 16.--31. 1. "VRATIO,Current vertical ratio from 8192 (1x) to 65535 (8x)" hexmask.long.word 0x4 0.--15. 1. "HRATIO,Current horizontal ratio from 8192 (1x) to 65535 (8x)" line.long 0x8 "DCMIPP_P2CDSSZR,DCMIPP Pipex current downsize destination size register" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" rgroup.long 0xF20++0x43 line.long 0x0 "DCMIPP_P2CCMRICR,DCMIPP Pipex current common ROI configuration register" bitfld.long 0x0 23. "ROI8EN,Current region of interest 8 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 22. "ROI7EN,Current region of interest 7 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 21. "ROI6EN,Current region of interest 6 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 20. "ROI5EN,Current region of interest 5 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 19. "ROI4EN,Current region of interest 4 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 18. "ROI3EN,Current region of interest 3 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 17. "ROI2EN,Current region of interest 2 enable" "0: Disable ROI,1: Enable ROI" bitfld.long 0x0 16. "ROI1EN,Current region of interest 1 enable" "0: Disable ROI,1: Enable ROI" newline bitfld.long 0x0 0.--1. "ROILSZ,Current region of interest line size width" "0: Line width 1 pixel,1: Line width 2 pixels,2: Line width 4 pixels,3: Line width 8 pixels" line.long 0x4 "DCMIPP_P2CRI1CR1,DCMIPP Pipe2 current ROI1 configuration register 1" bitfld.long 0x4 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x4 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x4 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x8 "DCMIPP_P2CRI1CR2,DCMIPP Pipe2 current ROI1 configuration register 2" hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0xC "DCMIPP_P2CRI2CR1,DCMIPP Pipe2 current ROI2 configuration register 1" bitfld.long 0xC 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0xC 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0xC 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0xC 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0xC 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x10 "DCMIPP_P2CRI2CR2,DCMIPP Pipe2 current ROI2 configuration register 2" hexmask.long.word 0x10 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x10 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x14 "DCMIPP_P2CRI3CR1,DCMIPP Pipe2 current ROI3 configuration register 1" bitfld.long 0x14 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x14 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x14 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x14 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x18 "DCMIPP_P2CRI3CR2,DCMIPP Pipe2 current ROI3 configuration register 2" hexmask.long.word 0x18 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x18 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x1C "DCMIPP_P2CRI4CR1,DCMIPP Pipe2 current ROI4 configuration register 1" bitfld.long 0x1C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x1C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x1C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x1C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x1C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x20 "DCMIPP_P2CRI4CR2,DCMIPP Pipe2 current ROI4 configuration register 2" hexmask.long.word 0x20 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x20 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x24 "DCMIPP_P2CRI5CR1,DCMIPP Pipe2 current ROI5 configuration register 1" bitfld.long 0x24 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x24 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x24 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x24 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x24 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x28 "DCMIPP_P2CRI5CR2,DCMIPP Pipe2 current ROI5 configuration register 2" hexmask.long.word 0x28 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x28 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x2C "DCMIPP_P2CRI6CR1,DCMIPP Pipe2 current ROI6 configuration register 1" bitfld.long 0x2C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x2C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x2C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x2C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x2C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x30 "DCMIPP_P2CRI6CR2,DCMIPP Pipe2 current ROI6 configuration register 2" hexmask.long.word 0x30 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x30 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x34 "DCMIPP_P2CRI7CR1,DCMIPP Pipe2 current ROI7 configuration register 1" bitfld.long 0x34 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x34 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x34 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x34 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x34 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x38 "DCMIPP_P2CRI7CR2,DCMIPP Pipe2 current ROI7 configuration register 2" hexmask.long.word 0x38 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x38 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" line.long 0x3C "DCMIPP_P2CRI8CR1,DCMIPP Pipe2 current ROI8 configuration register 1" bitfld.long 0x3C 28.--29. "CLR,Current color line red" "0,1,2,3" hexmask.long.word 0x3C 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high" newline bitfld.long 0x3C 14.--15. "CLG,Current color line green" "0,1,2,3" bitfld.long 0x3C 12.--13. "CLB,Current color line blue" "0,1,2,3" newline hexmask.long.word 0x3C 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 pixels wide" line.long 0x40 "DCMIPP_P2CRI8CR2,DCMIPP Pipe2 current ROI8 configuration register 2" hexmask.long.word 0x40 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high" hexmask.long.word 0x40 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 pixels wide" rgroup.long 0xFC0++0xB line.long 0x0 "DCMIPP_P2CPPCR,DCMIPP Pipe2 current pixel packer configuration register" bitfld.long 0x0 20. "LMAWE,Line multi address wrapping enable bit" "0: Line multi address wrapping disabled.,1: Line multi address wrapping enabled." bitfld.long 0x0 17.--19. "LMAWM,Line multi address wrapping modulo" "0: Wraps address after every line,1: Wraps address after two lines,2: Wraps address after four lines,3: Wraps address after eight lines,4: Wraps address after sixteen lines,5: Wraps address after 32 lines,6: Wraps address after 64 lines,7: Wraps address after 128 lines" newline bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe2 is always..,1: Double buffer mode activated. Dump address.." bitfld.long 0x0 13.--15. "LINEMULT,Amount of capture completed lines for LINE event and interrupt" "0: Event after every line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines" newline bitfld.long 0x0 4. "SWAPRB,Swaps R-vs-B components if RGB and if YUV swaps U-vs-V components" "0: No swap of R-vs-B (U-vs-V),1: Swap active." hexmask.long.byte 0x0 0.--3. 1. "FORMAT,Memory format (only coplanar formats are supported in Pipe2)" line.long 0x4 "DCMIPP_P2CPPM0AR1,DCMIPP Pipe2 current pixel packer Memory0 address register 1" hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address" line.long 0x8 "DCMIPP_P2CPPM0AR2,DCMIPP Pipe2 current pixel packer Memory0 address register 2" hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address" tree.end tree.end tree "DLYB (Delay Block)" base ad:0x0 tree "DLYBSD" base ad:0x48028000 group.long 0x0++0x7 line.long 0x0 "DLYBSD_CFG,Delay block SDMMC DLL configuration" bitfld.long 0x0 22. "SDMMC_DLL_ANTIGLITCH_EN,Antiglitch logic enabled when 1" "0,1" hexmask.long.byte 0x0 17.--21. 1. "SDMMC_DLL_BYP_CMD,Bypass command" bitfld.long 0x0 16. "SDMMC_DLL_BYP_EN,DLL configuration" "0: Lock mode,1: Pure delay" hexmask.long.byte 0x0 1.--6. 1. "SDMMC_RX_TAP_SEL,selection of RX delay" newline bitfld.long 0x0 0. "SDMMC_DLL_EN,DLL enable" "0,1" line.long 0x4 "DLYBSD_STATUS,Delay block SDMMC DLL status" bitfld.long 0x4 1. "SDMMC_RX_TAP_SEL_ACK,SDMMC RX delay selection acknowledge" "0,1" bitfld.long 0x4 0. "SDMMC_DLL_LOCK,SDMMC DLL lock" "0,1" tree.end tree "DLYBSD2" base ad:0x48026C00 group.long 0x0++0x7 line.long 0x0 "DLYBSD_CFG,Delay block SDMMC DLL configuration" bitfld.long 0x0 22. "SDMMC_DLL_ANTIGLITCH_EN,Antiglitch logic enabled when 1" "0,1" hexmask.long.byte 0x0 17.--21. 1. "SDMMC_DLL_BYP_CMD,Bypass command" bitfld.long 0x0 16. "SDMMC_DLL_BYP_EN,DLL configuration" "0: Lock mode,1: Pure delay" hexmask.long.byte 0x0 1.--6. 1. "SDMMC_RX_TAP_SEL,selection of RX delay" newline bitfld.long 0x0 0. "SDMMC_DLL_EN,DLL enable" "0,1" line.long 0x4 "DLYBSD_STATUS,Delay block SDMMC DLL status" bitfld.long 0x4 1. "SDMMC_RX_TAP_SEL_ACK,SDMMC RX delay selection acknowledge" "0,1" bitfld.long 0x4 0. "SDMMC_DLL_LOCK,SDMMC DLL lock" "0,1" tree.end tree "DLYBSD2_S" base ad:0x58026C00 group.long 0x0++0x7 line.long 0x0 "DLYBSD_CFG,Delay block SDMMC DLL configuration" bitfld.long 0x0 22. "SDMMC_DLL_ANTIGLITCH_EN,Antiglitch logic enabled when 1" "0,1" hexmask.long.byte 0x0 17.--21. 1. "SDMMC_DLL_BYP_CMD,Bypass command" bitfld.long 0x0 16. "SDMMC_DLL_BYP_EN,DLL configuration" "0: Lock mode,1: Pure delay" hexmask.long.byte 0x0 1.--6. 1. "SDMMC_RX_TAP_SEL,selection of RX delay" newline bitfld.long 0x0 0. "SDMMC_DLL_EN,DLL enable" "0,1" line.long 0x4 "DLYBSD_STATUS,Delay block SDMMC DLL status" bitfld.long 0x4 1. "SDMMC_RX_TAP_SEL_ACK,SDMMC RX delay selection acknowledge" "0,1" bitfld.long 0x4 0. "SDMMC_DLL_LOCK,SDMMC DLL lock" "0,1" tree.end tree "DLYBSD_S" base ad:0x58028000 group.long 0x0++0x7 line.long 0x0 "DLYBSD_CFG,Delay block SDMMC DLL configuration" bitfld.long 0x0 22. "SDMMC_DLL_ANTIGLITCH_EN,Antiglitch logic enabled when 1" "0,1" hexmask.long.byte 0x0 17.--21. 1. "SDMMC_DLL_BYP_CMD,Bypass command" bitfld.long 0x0 16. "SDMMC_DLL_BYP_EN,DLL configuration" "0: Lock mode,1: Pure delay" hexmask.long.byte 0x0 1.--6. 1. "SDMMC_RX_TAP_SEL,selection of RX delay" newline bitfld.long 0x0 0. "SDMMC_DLL_EN,DLL enable" "0,1" line.long 0x4 "DLYBSD_STATUS,Delay block SDMMC DLL status" bitfld.long 0x4 1. "SDMMC_RX_TAP_SEL_ACK,SDMMC RX delay selection acknowledge" "0,1" bitfld.long 0x4 0. "SDMMC_DLL_LOCK,SDMMC DLL lock" "0,1" tree.end tree.end tree "DMA2D (Chrom-ART Accelerator Controller)" base ad:0x0 tree "DMA2D" base ad:0x48021000 group.long 0x0++0x3 line.long 0x0 "DMA2D_CR,DMA2D control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0: Memory-to-memory (FG fetch only),1: Memory-to-memory with PFC (FG fetch only with FG..,2: Memory-to-memory with blending (FG and BG fetch..,3: Register-to-memory (no FG nor BG only output..,4: Memory-to-memory with blending and fixed color..,5: Memory-to-memory with blending and fixed color..,?,?" bitfld.long 0x0 13. "CEIE,Configuration error (CE) interrupt enable" "0: CE interrupt disabled,1: CE interrupt enabled" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete (CTC) interrupt enable" "0: CTC interrupt disabled,1: CTC interrupt enabled" bitfld.long 0x0 11. "CAEIE,CLUT access error (CAE) interrupt enable" "0: CAE interrupt disabled,1: CAE interrupt enabled" newline bitfld.long 0x0 10. "TWIE,Transfer watermark (TW) interrupt enable" "0: TW interrupt disabled,1: TW interrupt enabled" bitfld.long 0x0 9. "TCIE,Transfer complete (TC) interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" newline bitfld.long 0x0 8. "TEIE,Transfer error (TE) interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x0 6. "LOM,Line offset mode" "0: Line offsets expressed in pixels,1: Line offsets expressed in bytes" newline bitfld.long 0x0 2. "ABORT,Abort" "0: No transfer abort requested,1: Transfer abort requested" bitfld.long 0x0 1. "SUSP,Suspend" "0: Transfer not suspended,1: Transfer suspended" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DMA2D_ISR,DMA2D interrupt status register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "DMA2D_IFCR,DMA2D interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear transfer error interrupt flag" "0,1" line.long 0x4 "DMA2D_FGMAR,DMA2D foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address address of the data used for the foreground image" line.long 0x8 "DMA2D_FGOR,DMA2D foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "DMA2D_BGMAR,DMA2D background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address address of the data used for the background image" line.long 0x10 "DMA2D_BGOR,DMA2D background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "DMA2D_FGPFCCR,DMA2D foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red/Blue swap" "0: Regular mode (RGB or ARGB),1: Swap mode (BGR or ABGR)" newline bitfld.long 0x14 20. "AI,Alpha inverted" "0: Regular alpha,1: Inverted alpha" bitfld.long 0x14 18.--19. "CSS,Chroma subsampling" "0: 4:4:4 (no chroma subsampling),1: 4:2:2,2: 4:2:0,?" newline bitfld.long 0x14 16.--17. "AM,Alpha mode" "0: No modification of the foreground image alpha..,1: Replace original foreground image alpha channel..,2: Replace original foreground image alpha channel..,?" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" newline bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0: ARGB8888,1: RGB888" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "DMA2D_FGCOLR,DMA2D foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red value for the A4 or A8 mode of the foreground image" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green value for the A4 or A8 mode of the foreground image" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue value for the A4 or A8 mode of the foreground image" line.long 0x1C "DMA2D_BGPFCCR,DMA2D background PFC control register" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red/Blue swap" "0: Regular mode (RGB or ARGB),1: Swap mode (BGR or ABGR)" newline bitfld.long 0x1C 20. "AI,Alpha Inverted" "0: Regular alpha,1: Inverted alpha" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0: No modification of the foreground image alpha..,1: Replace original background image alpha channel..,2: Replace original background image alpha channel..,?" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT color mode" "0: ARGB8888,1: RGB888" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "DMA2D_BGCOLR,DMA2D background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red value for the A4 or A8 mode of the background" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green value for the A4 or A8 mode of the background" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue value for the A4 or A8 mode of the background" line.long 0x24 "DMA2D_FGCMAR,DMA2D foreground CLUT memory address register" hexmask.long 0x24 0.--31. 1. "MA,Memory address" line.long 0x28 "DMA2D_BGCMAR,DMA2D background CLUT memory address register" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "DMA2D_OPFCCR,DMA2D output PFC control register" bitfld.long 0x2C 21. "RBS,Red/Blue swap" "0: Regular mode (RGB or ARGB),1: Swap mode (BGR or ABGR)" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0: Regular alpha,1: Inverted alpha" newline bitfld.long 0x2C 8. "SB,Swap bytes" "0: Bytes in regular order in the output FIFO,1: Bytes swapped two by two in the output FIFO" bitfld.long 0x2C 0.--2. "CM,Color mode" "0: ARGB8888,1: RGB888,2: RGB565,3: ARGB1555,4: ARGB4444,?,?,?" line.long 0x30 "DMA2D_OCOLR_RGB888,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha channel value of the output color in ARGB8888 mode (otherwise reserved)" hexmask.long.byte 0x30 16.--23. 1. "RED,Red value of the output image in ARGB8888 or RGB888 mode" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green value of the output image in ARGB8888 or RGB888" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue value of the output image in ARGB8888 or RGB888" group.long 0x38++0x3 line.long 0x0 "DMA2D_OCOLR_RGB565,DMA2D output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value of the output image in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value of the output image in RGB565 mode" newline hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value of the output image in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "DMA2D_OCOLR_ARGB1555,DMA2D output color register" bitfld.long 0x0 15. "A,Alpha channel value of the output color in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value of the output image in ARGB1555 mode" newline hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value of the output image in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value of the output image in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "DMA2D_OCOLR_ARGB4444,DMA2D output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel of the output color value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value of the output image in ARGB4444 mode" newline hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value of the output image in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value of the output image in ARGB4444 mode" line.long 0x4 "DMA2D_OMAR,DMA2D output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "DMA2D_OOR,DMA2D output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "DMA2D_NLR,DMA2D number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines per lines of the area to be transferred" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines of the area to be transferred." line.long 0x10 "DMA2D_LWR,DMA2D line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark for interrupt generation" line.long 0x14 "DMA2D_AMTCR,DMA2D AXI master timer configuration register" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead time" bitfld.long 0x14 0. "EN,Dead-time functionality enable" "0,1" group.long 0x400++0x7FF line.long 0x0 "DMA2D_FGCLUT0,DMA2D foreground CLUT" hexmask.long.byte 0x0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x0 0.--7. 1. "BLUE,Blue" line.long 0x4 "DMA2D_FGCLUT1,DMA2D foreground CLUT" hexmask.long.byte 0x4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4 0.--7. 1. "BLUE,Blue" line.long 0x8 "DMA2D_FGCLUT2,DMA2D foreground CLUT" hexmask.long.byte 0x8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x8 0.--7. 1. "BLUE,Blue" line.long 0xC "DMA2D_FGCLUT3,DMA2D foreground CLUT" hexmask.long.byte 0xC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xC 0.--7. 1. "BLUE,Blue" line.long 0x10 "DMA2D_FGCLUT4,DMA2D foreground CLUT" hexmask.long.byte 0x10 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x10 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x10 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x10 0.--7. 1. "BLUE,Blue" line.long 0x14 "DMA2D_FGCLUT5,DMA2D foreground CLUT" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x14 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x14 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x14 0.--7. 1. "BLUE,Blue" line.long 0x18 "DMA2D_FGCLUT6,DMA2D foreground CLUT" hexmask.long.byte 0x18 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x18 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue" line.long 0x1C "DMA2D_FGCLUT7,DMA2D foreground CLUT" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1C 0.--7. 1. "BLUE,Blue" line.long 0x20 "DMA2D_FGCLUT8,DMA2D foreground CLUT" hexmask.long.byte 0x20 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x20 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue" line.long 0x24 "DMA2D_FGCLUT9,DMA2D foreground CLUT" hexmask.long.byte 0x24 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x24 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x24 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x24 0.--7. 1. "BLUE,Blue" line.long 0x28 "DMA2D_FGCLUT10,DMA2D foreground CLUT" hexmask.long.byte 0x28 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x28 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x28 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x28 0.--7. 1. "BLUE,Blue" line.long 0x2C "DMA2D_FGCLUT11,DMA2D foreground CLUT" hexmask.long.byte 0x2C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2C 0.--7. 1. "BLUE,Blue" line.long 0x30 "DMA2D_FGCLUT12,DMA2D foreground CLUT" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x30 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue" line.long 0x34 "DMA2D_FGCLUT13,DMA2D foreground CLUT" hexmask.long.byte 0x34 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x34 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x34 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x34 0.--7. 1. "BLUE,Blue" line.long 0x38 "DMA2D_FGCLUT14,DMA2D foreground CLUT" hexmask.long.byte 0x38 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x38 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x38 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x38 0.--7. 1. "BLUE,Blue" line.long 0x3C "DMA2D_FGCLUT15,DMA2D foreground CLUT" hexmask.long.byte 0x3C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3C 0.--7. 1. "BLUE,Blue" line.long 0x40 "DMA2D_FGCLUT16,DMA2D foreground CLUT" hexmask.long.byte 0x40 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x40 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x40 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x40 0.--7. 1. "BLUE,Blue" line.long 0x44 "DMA2D_FGCLUT17,DMA2D foreground CLUT" hexmask.long.byte 0x44 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x44 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x44 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x44 0.--7. 1. "BLUE,Blue" line.long 0x48 "DMA2D_FGCLUT18,DMA2D foreground CLUT" hexmask.long.byte 0x48 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x48 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x48 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x48 0.--7. 1. "BLUE,Blue" line.long 0x4C "DMA2D_FGCLUT19,DMA2D foreground CLUT" hexmask.long.byte 0x4C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4C 0.--7. 1. "BLUE,Blue" line.long 0x50 "DMA2D_FGCLUT20,DMA2D foreground CLUT" hexmask.long.byte 0x50 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x50 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x50 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x50 0.--7. 1. "BLUE,Blue" line.long 0x54 "DMA2D_FGCLUT21,DMA2D foreground CLUT" hexmask.long.byte 0x54 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x54 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x54 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x54 0.--7. 1. "BLUE,Blue" line.long 0x58 "DMA2D_FGCLUT22,DMA2D foreground CLUT" hexmask.long.byte 0x58 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x58 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x58 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x58 0.--7. 1. "BLUE,Blue" line.long 0x5C "DMA2D_FGCLUT23,DMA2D foreground CLUT" hexmask.long.byte 0x5C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5C 0.--7. 1. "BLUE,Blue" line.long 0x60 "DMA2D_FGCLUT24,DMA2D foreground CLUT" hexmask.long.byte 0x60 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x60 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x60 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x60 0.--7. 1. "BLUE,Blue" line.long 0x64 "DMA2D_FGCLUT25,DMA2D foreground CLUT" hexmask.long.byte 0x64 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x64 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x64 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x64 0.--7. 1. "BLUE,Blue" line.long 0x68 "DMA2D_FGCLUT26,DMA2D foreground CLUT" hexmask.long.byte 0x68 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x68 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x68 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x68 0.--7. 1. "BLUE,Blue" line.long 0x6C "DMA2D_FGCLUT27,DMA2D foreground CLUT" hexmask.long.byte 0x6C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6C 0.--7. 1. "BLUE,Blue" line.long 0x70 "DMA2D_FGCLUT28,DMA2D foreground CLUT" hexmask.long.byte 0x70 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x70 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x70 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x70 0.--7. 1. "BLUE,Blue" line.long 0x74 "DMA2D_FGCLUT29,DMA2D foreground CLUT" hexmask.long.byte 0x74 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x74 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x74 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x74 0.--7. 1. "BLUE,Blue" line.long 0x78 "DMA2D_FGCLUT30,DMA2D foreground CLUT" hexmask.long.byte 0x78 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x78 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x78 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x78 0.--7. 1. "BLUE,Blue" line.long 0x7C "DMA2D_FGCLUT31,DMA2D foreground CLUT" hexmask.long.byte 0x7C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7C 0.--7. 1. "BLUE,Blue" line.long 0x80 "DMA2D_FGCLUT32,DMA2D foreground CLUT" hexmask.long.byte 0x80 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x80 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x80 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x80 0.--7. 1. "BLUE,Blue" line.long 0x84 "DMA2D_FGCLUT33,DMA2D foreground CLUT" hexmask.long.byte 0x84 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x84 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x84 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x84 0.--7. 1. "BLUE,Blue" line.long 0x88 "DMA2D_FGCLUT34,DMA2D foreground CLUT" hexmask.long.byte 0x88 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x88 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x88 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x88 0.--7. 1. "BLUE,Blue" line.long 0x8C "DMA2D_FGCLUT35,DMA2D foreground CLUT" hexmask.long.byte 0x8C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x8C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x8C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x8C 0.--7. 1. "BLUE,Blue" line.long 0x90 "DMA2D_FGCLUT36,DMA2D foreground CLUT" hexmask.long.byte 0x90 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x90 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x90 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x90 0.--7. 1. "BLUE,Blue" line.long 0x94 "DMA2D_FGCLUT37,DMA2D foreground CLUT" hexmask.long.byte 0x94 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x94 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x94 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x94 0.--7. 1. "BLUE,Blue" line.long 0x98 "DMA2D_FGCLUT38,DMA2D foreground CLUT" hexmask.long.byte 0x98 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x98 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x98 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x98 0.--7. 1. "BLUE,Blue" line.long 0x9C "DMA2D_FGCLUT39,DMA2D foreground CLUT" hexmask.long.byte 0x9C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x9C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x9C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x9C 0.--7. 1. "BLUE,Blue" line.long 0xA0 "DMA2D_FGCLUT40,DMA2D foreground CLUT" hexmask.long.byte 0xA0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xA0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xA0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xA0 0.--7. 1. "BLUE,Blue" line.long 0xA4 "DMA2D_FGCLUT41,DMA2D foreground CLUT" hexmask.long.byte 0xA4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xA4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xA4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xA4 0.--7. 1. "BLUE,Blue" line.long 0xA8 "DMA2D_FGCLUT42,DMA2D foreground CLUT" hexmask.long.byte 0xA8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xA8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xA8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xA8 0.--7. 1. "BLUE,Blue" line.long 0xAC "DMA2D_FGCLUT43,DMA2D foreground CLUT" hexmask.long.byte 0xAC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xAC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xAC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xAC 0.--7. 1. "BLUE,Blue" line.long 0xB0 "DMA2D_FGCLUT44,DMA2D foreground CLUT" hexmask.long.byte 0xB0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xB0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xB0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xB0 0.--7. 1. "BLUE,Blue" line.long 0xB4 "DMA2D_FGCLUT45,DMA2D foreground CLUT" hexmask.long.byte 0xB4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xB4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xB4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xB4 0.--7. 1. "BLUE,Blue" line.long 0xB8 "DMA2D_FGCLUT46,DMA2D foreground CLUT" hexmask.long.byte 0xB8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xB8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xB8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xB8 0.--7. 1. "BLUE,Blue" line.long 0xBC "DMA2D_FGCLUT47,DMA2D foreground CLUT" hexmask.long.byte 0xBC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xBC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xBC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xBC 0.--7. 1. "BLUE,Blue" line.long 0xC0 "DMA2D_FGCLUT48,DMA2D foreground CLUT" hexmask.long.byte 0xC0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xC0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xC0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xC0 0.--7. 1. "BLUE,Blue" line.long 0xC4 "DMA2D_FGCLUT49,DMA2D foreground CLUT" hexmask.long.byte 0xC4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xC4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xC4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xC4 0.--7. 1. "BLUE,Blue" line.long 0xC8 "DMA2D_FGCLUT50,DMA2D foreground CLUT" hexmask.long.byte 0xC8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xC8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xC8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xC8 0.--7. 1. "BLUE,Blue" line.long 0xCC "DMA2D_FGCLUT51,DMA2D foreground CLUT" hexmask.long.byte 0xCC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xCC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xCC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xCC 0.--7. 1. "BLUE,Blue" line.long 0xD0 "DMA2D_FGCLUT52,DMA2D foreground CLUT" hexmask.long.byte 0xD0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xD0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xD0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xD0 0.--7. 1. "BLUE,Blue" line.long 0xD4 "DMA2D_FGCLUT53,DMA2D foreground CLUT" hexmask.long.byte 0xD4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xD4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xD4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xD4 0.--7. 1. "BLUE,Blue" line.long 0xD8 "DMA2D_FGCLUT54,DMA2D foreground CLUT" hexmask.long.byte 0xD8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xD8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xD8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xD8 0.--7. 1. "BLUE,Blue" line.long 0xDC "DMA2D_FGCLUT55,DMA2D foreground CLUT" hexmask.long.byte 0xDC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xDC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xDC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xDC 0.--7. 1. "BLUE,Blue" line.long 0xE0 "DMA2D_FGCLUT56,DMA2D foreground CLUT" hexmask.long.byte 0xE0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xE0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xE0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xE0 0.--7. 1. "BLUE,Blue" line.long 0xE4 "DMA2D_FGCLUT57,DMA2D foreground CLUT" hexmask.long.byte 0xE4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xE4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xE4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xE4 0.--7. 1. "BLUE,Blue" line.long 0xE8 "DMA2D_FGCLUT58,DMA2D foreground CLUT" hexmask.long.byte 0xE8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xE8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xE8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xE8 0.--7. 1. "BLUE,Blue" line.long 0xEC "DMA2D_FGCLUT59,DMA2D foreground CLUT" hexmask.long.byte 0xEC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xEC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xEC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xEC 0.--7. 1. "BLUE,Blue" line.long 0xF0 "DMA2D_FGCLUT60,DMA2D foreground CLUT" hexmask.long.byte 0xF0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xF0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xF0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xF0 0.--7. 1. "BLUE,Blue" line.long 0xF4 "DMA2D_FGCLUT61,DMA2D foreground CLUT" hexmask.long.byte 0xF4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xF4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xF4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xF4 0.--7. 1. "BLUE,Blue" line.long 0xF8 "DMA2D_FGCLUT62,DMA2D foreground CLUT" hexmask.long.byte 0xF8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xF8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xF8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xF8 0.--7. 1. "BLUE,Blue" line.long 0xFC "DMA2D_FGCLUT63,DMA2D foreground CLUT" hexmask.long.byte 0xFC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xFC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xFC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xFC 0.--7. 1. "BLUE,Blue" line.long 0x100 "DMA2D_FGCLUT64,DMA2D foreground CLUT" hexmask.long.byte 0x100 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x100 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x100 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x100 0.--7. 1. "BLUE,Blue" line.long 0x104 "DMA2D_FGCLUT65,DMA2D foreground CLUT" hexmask.long.byte 0x104 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x104 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x104 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x104 0.--7. 1. "BLUE,Blue" line.long 0x108 "DMA2D_FGCLUT66,DMA2D foreground CLUT" hexmask.long.byte 0x108 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x108 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x108 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x108 0.--7. 1. "BLUE,Blue" line.long 0x10C "DMA2D_FGCLUT67,DMA2D foreground CLUT" hexmask.long.byte 0x10C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x10C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x10C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x10C 0.--7. 1. "BLUE,Blue" line.long 0x110 "DMA2D_FGCLUT68,DMA2D foreground CLUT" hexmask.long.byte 0x110 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x110 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x110 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x110 0.--7. 1. "BLUE,Blue" line.long 0x114 "DMA2D_FGCLUT69,DMA2D foreground CLUT" hexmask.long.byte 0x114 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x114 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x114 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x114 0.--7. 1. "BLUE,Blue" line.long 0x118 "DMA2D_FGCLUT70,DMA2D foreground CLUT" hexmask.long.byte 0x118 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x118 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x118 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x118 0.--7. 1. "BLUE,Blue" line.long 0x11C "DMA2D_FGCLUT71,DMA2D foreground CLUT" hexmask.long.byte 0x11C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x11C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x11C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x11C 0.--7. 1. "BLUE,Blue" line.long 0x120 "DMA2D_FGCLUT72,DMA2D foreground CLUT" hexmask.long.byte 0x120 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x120 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x120 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x120 0.--7. 1. "BLUE,Blue" line.long 0x124 "DMA2D_FGCLUT73,DMA2D foreground CLUT" hexmask.long.byte 0x124 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x124 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x124 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x124 0.--7. 1. "BLUE,Blue" line.long 0x128 "DMA2D_FGCLUT74,DMA2D foreground CLUT" hexmask.long.byte 0x128 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x128 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x128 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x128 0.--7. 1. "BLUE,Blue" line.long 0x12C "DMA2D_FGCLUT75,DMA2D foreground CLUT" hexmask.long.byte 0x12C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x12C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x12C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x12C 0.--7. 1. "BLUE,Blue" line.long 0x130 "DMA2D_FGCLUT76,DMA2D foreground CLUT" hexmask.long.byte 0x130 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x130 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x130 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x130 0.--7. 1. "BLUE,Blue" line.long 0x134 "DMA2D_FGCLUT77,DMA2D foreground CLUT" hexmask.long.byte 0x134 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x134 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x134 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x134 0.--7. 1. "BLUE,Blue" line.long 0x138 "DMA2D_FGCLUT78,DMA2D foreground CLUT" hexmask.long.byte 0x138 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x138 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x138 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x138 0.--7. 1. "BLUE,Blue" line.long 0x13C "DMA2D_FGCLUT79,DMA2D foreground CLUT" hexmask.long.byte 0x13C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x13C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x13C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x13C 0.--7. 1. "BLUE,Blue" line.long 0x140 "DMA2D_FGCLUT80,DMA2D foreground CLUT" hexmask.long.byte 0x140 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x140 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x140 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x140 0.--7. 1. "BLUE,Blue" line.long 0x144 "DMA2D_FGCLUT81,DMA2D foreground CLUT" hexmask.long.byte 0x144 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x144 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x144 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x144 0.--7. 1. "BLUE,Blue" line.long 0x148 "DMA2D_FGCLUT82,DMA2D foreground CLUT" hexmask.long.byte 0x148 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x148 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x148 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x148 0.--7. 1. "BLUE,Blue" line.long 0x14C "DMA2D_FGCLUT83,DMA2D foreground CLUT" hexmask.long.byte 0x14C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x14C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x14C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x14C 0.--7. 1. "BLUE,Blue" line.long 0x150 "DMA2D_FGCLUT84,DMA2D foreground CLUT" hexmask.long.byte 0x150 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x150 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x150 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x150 0.--7. 1. "BLUE,Blue" line.long 0x154 "DMA2D_FGCLUT85,DMA2D foreground CLUT" hexmask.long.byte 0x154 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x154 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x154 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x154 0.--7. 1. "BLUE,Blue" line.long 0x158 "DMA2D_FGCLUT86,DMA2D foreground CLUT" hexmask.long.byte 0x158 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x158 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x158 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x158 0.--7. 1. "BLUE,Blue" line.long 0x15C "DMA2D_FGCLUT87,DMA2D foreground CLUT" hexmask.long.byte 0x15C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x15C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x15C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x15C 0.--7. 1. "BLUE,Blue" line.long 0x160 "DMA2D_FGCLUT88,DMA2D foreground CLUT" hexmask.long.byte 0x160 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x160 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x160 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x160 0.--7. 1. "BLUE,Blue" line.long 0x164 "DMA2D_FGCLUT89,DMA2D foreground CLUT" hexmask.long.byte 0x164 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x164 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x164 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x164 0.--7. 1. "BLUE,Blue" line.long 0x168 "DMA2D_FGCLUT90,DMA2D foreground CLUT" hexmask.long.byte 0x168 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x168 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x168 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x168 0.--7. 1. "BLUE,Blue" line.long 0x16C "DMA2D_FGCLUT91,DMA2D foreground CLUT" hexmask.long.byte 0x16C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x16C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x16C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x16C 0.--7. 1. "BLUE,Blue" line.long 0x170 "DMA2D_FGCLUT92,DMA2D foreground CLUT" hexmask.long.byte 0x170 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x170 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x170 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x170 0.--7. 1. "BLUE,Blue" line.long 0x174 "DMA2D_FGCLUT93,DMA2D foreground CLUT" hexmask.long.byte 0x174 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x174 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x174 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x174 0.--7. 1. "BLUE,Blue" line.long 0x178 "DMA2D_FGCLUT94,DMA2D foreground CLUT" hexmask.long.byte 0x178 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x178 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x178 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x178 0.--7. 1. "BLUE,Blue" line.long 0x17C "DMA2D_FGCLUT95,DMA2D foreground CLUT" hexmask.long.byte 0x17C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x17C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x17C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x17C 0.--7. 1. "BLUE,Blue" line.long 0x180 "DMA2D_FGCLUT96,DMA2D foreground CLUT" hexmask.long.byte 0x180 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x180 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x180 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x180 0.--7. 1. "BLUE,Blue" line.long 0x184 "DMA2D_FGCLUT97,DMA2D foreground CLUT" hexmask.long.byte 0x184 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x184 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x184 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x184 0.--7. 1. "BLUE,Blue" line.long 0x188 "DMA2D_FGCLUT98,DMA2D foreground CLUT" hexmask.long.byte 0x188 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x188 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x188 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x188 0.--7. 1. "BLUE,Blue" line.long 0x18C "DMA2D_FGCLUT99,DMA2D foreground CLUT" hexmask.long.byte 0x18C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x18C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x18C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x18C 0.--7. 1. "BLUE,Blue" line.long 0x190 "DMA2D_FGCLUT100,DMA2D foreground CLUT" hexmask.long.byte 0x190 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x190 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x190 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x190 0.--7. 1. "BLUE,Blue" line.long 0x194 "DMA2D_FGCLUT101,DMA2D foreground CLUT" hexmask.long.byte 0x194 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x194 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x194 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x194 0.--7. 1. "BLUE,Blue" line.long 0x198 "DMA2D_FGCLUT102,DMA2D foreground CLUT" hexmask.long.byte 0x198 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x198 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x198 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x198 0.--7. 1. "BLUE,Blue" line.long 0x19C "DMA2D_FGCLUT103,DMA2D foreground CLUT" hexmask.long.byte 0x19C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x19C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x19C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x19C 0.--7. 1. "BLUE,Blue" line.long 0x1A0 "DMA2D_FGCLUT104,DMA2D foreground CLUT" hexmask.long.byte 0x1A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1A0 0.--7. 1. "BLUE,Blue" line.long 0x1A4 "DMA2D_FGCLUT105,DMA2D foreground CLUT" hexmask.long.byte 0x1A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1A4 0.--7. 1. "BLUE,Blue" line.long 0x1A8 "DMA2D_FGCLUT106,DMA2D foreground CLUT" hexmask.long.byte 0x1A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1A8 0.--7. 1. "BLUE,Blue" line.long 0x1AC "DMA2D_FGCLUT107,DMA2D foreground CLUT" hexmask.long.byte 0x1AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1AC 0.--7. 1. "BLUE,Blue" line.long 0x1B0 "DMA2D_FGCLUT108,DMA2D foreground CLUT" hexmask.long.byte 0x1B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1B0 0.--7. 1. "BLUE,Blue" line.long 0x1B4 "DMA2D_FGCLUT109,DMA2D foreground CLUT" hexmask.long.byte 0x1B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1B4 0.--7. 1. "BLUE,Blue" line.long 0x1B8 "DMA2D_FGCLUT110,DMA2D foreground CLUT" hexmask.long.byte 0x1B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1B8 0.--7. 1. "BLUE,Blue" line.long 0x1BC "DMA2D_FGCLUT111,DMA2D foreground CLUT" hexmask.long.byte 0x1BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1BC 0.--7. 1. "BLUE,Blue" line.long 0x1C0 "DMA2D_FGCLUT112,DMA2D foreground CLUT" hexmask.long.byte 0x1C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1C0 0.--7. 1. "BLUE,Blue" line.long 0x1C4 "DMA2D_FGCLUT113,DMA2D foreground CLUT" hexmask.long.byte 0x1C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1C4 0.--7. 1. "BLUE,Blue" line.long 0x1C8 "DMA2D_FGCLUT114,DMA2D foreground CLUT" hexmask.long.byte 0x1C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1C8 0.--7. 1. "BLUE,Blue" line.long 0x1CC "DMA2D_FGCLUT115,DMA2D foreground CLUT" hexmask.long.byte 0x1CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1CC 0.--7. 1. "BLUE,Blue" line.long 0x1D0 "DMA2D_FGCLUT116,DMA2D foreground CLUT" hexmask.long.byte 0x1D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1D0 0.--7. 1. "BLUE,Blue" line.long 0x1D4 "DMA2D_FGCLUT117,DMA2D foreground CLUT" hexmask.long.byte 0x1D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1D4 0.--7. 1. "BLUE,Blue" line.long 0x1D8 "DMA2D_FGCLUT118,DMA2D foreground CLUT" hexmask.long.byte 0x1D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1D8 0.--7. 1. "BLUE,Blue" line.long 0x1DC "DMA2D_FGCLUT119,DMA2D foreground CLUT" hexmask.long.byte 0x1DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1DC 0.--7. 1. "BLUE,Blue" line.long 0x1E0 "DMA2D_FGCLUT120,DMA2D foreground CLUT" hexmask.long.byte 0x1E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1E0 0.--7. 1. "BLUE,Blue" line.long 0x1E4 "DMA2D_FGCLUT121,DMA2D foreground CLUT" hexmask.long.byte 0x1E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1E4 0.--7. 1. "BLUE,Blue" line.long 0x1E8 "DMA2D_FGCLUT122,DMA2D foreground CLUT" hexmask.long.byte 0x1E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1E8 0.--7. 1. "BLUE,Blue" line.long 0x1EC "DMA2D_FGCLUT123,DMA2D foreground CLUT" hexmask.long.byte 0x1EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1EC 0.--7. 1. "BLUE,Blue" line.long 0x1F0 "DMA2D_FGCLUT124,DMA2D foreground CLUT" hexmask.long.byte 0x1F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1F0 0.--7. 1. "BLUE,Blue" line.long 0x1F4 "DMA2D_FGCLUT125,DMA2D foreground CLUT" hexmask.long.byte 0x1F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1F4 0.--7. 1. "BLUE,Blue" line.long 0x1F8 "DMA2D_FGCLUT126,DMA2D foreground CLUT" hexmask.long.byte 0x1F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1F8 0.--7. 1. "BLUE,Blue" line.long 0x1FC "DMA2D_FGCLUT127,DMA2D foreground CLUT" hexmask.long.byte 0x1FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1FC 0.--7. 1. "BLUE,Blue" line.long 0x200 "DMA2D_FGCLUT128,DMA2D foreground CLUT" hexmask.long.byte 0x200 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x200 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x200 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x200 0.--7. 1. "BLUE,Blue" line.long 0x204 "DMA2D_FGCLUT129,DMA2D foreground CLUT" hexmask.long.byte 0x204 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x204 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x204 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x204 0.--7. 1. "BLUE,Blue" line.long 0x208 "DMA2D_FGCLUT130,DMA2D foreground CLUT" hexmask.long.byte 0x208 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x208 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x208 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x208 0.--7. 1. "BLUE,Blue" line.long 0x20C "DMA2D_FGCLUT131,DMA2D foreground CLUT" hexmask.long.byte 0x20C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x20C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x20C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x20C 0.--7. 1. "BLUE,Blue" line.long 0x210 "DMA2D_FGCLUT132,DMA2D foreground CLUT" hexmask.long.byte 0x210 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x210 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x210 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x210 0.--7. 1. "BLUE,Blue" line.long 0x214 "DMA2D_FGCLUT133,DMA2D foreground CLUT" hexmask.long.byte 0x214 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x214 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x214 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x214 0.--7. 1. "BLUE,Blue" line.long 0x218 "DMA2D_FGCLUT134,DMA2D foreground CLUT" hexmask.long.byte 0x218 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x218 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x218 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x218 0.--7. 1. "BLUE,Blue" line.long 0x21C "DMA2D_FGCLUT135,DMA2D foreground CLUT" hexmask.long.byte 0x21C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x21C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x21C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x21C 0.--7. 1. "BLUE,Blue" line.long 0x220 "DMA2D_FGCLUT136,DMA2D foreground CLUT" hexmask.long.byte 0x220 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x220 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x220 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x220 0.--7. 1. "BLUE,Blue" line.long 0x224 "DMA2D_FGCLUT137,DMA2D foreground CLUT" hexmask.long.byte 0x224 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x224 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x224 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x224 0.--7. 1. "BLUE,Blue" line.long 0x228 "DMA2D_FGCLUT138,DMA2D foreground CLUT" hexmask.long.byte 0x228 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x228 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x228 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x228 0.--7. 1. "BLUE,Blue" line.long 0x22C "DMA2D_FGCLUT139,DMA2D foreground CLUT" hexmask.long.byte 0x22C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x22C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x22C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x22C 0.--7. 1. "BLUE,Blue" line.long 0x230 "DMA2D_FGCLUT140,DMA2D foreground CLUT" hexmask.long.byte 0x230 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x230 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x230 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x230 0.--7. 1. "BLUE,Blue" line.long 0x234 "DMA2D_FGCLUT141,DMA2D foreground CLUT" hexmask.long.byte 0x234 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x234 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x234 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x234 0.--7. 1. "BLUE,Blue" line.long 0x238 "DMA2D_FGCLUT142,DMA2D foreground CLUT" hexmask.long.byte 0x238 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x238 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x238 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x238 0.--7. 1. "BLUE,Blue" line.long 0x23C "DMA2D_FGCLUT143,DMA2D foreground CLUT" hexmask.long.byte 0x23C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x23C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x23C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x23C 0.--7. 1. "BLUE,Blue" line.long 0x240 "DMA2D_FGCLUT144,DMA2D foreground CLUT" hexmask.long.byte 0x240 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x240 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x240 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x240 0.--7. 1. "BLUE,Blue" line.long 0x244 "DMA2D_FGCLUT145,DMA2D foreground CLUT" hexmask.long.byte 0x244 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x244 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x244 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x244 0.--7. 1. "BLUE,Blue" line.long 0x248 "DMA2D_FGCLUT146,DMA2D foreground CLUT" hexmask.long.byte 0x248 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x248 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x248 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x248 0.--7. 1. "BLUE,Blue" line.long 0x24C "DMA2D_FGCLUT147,DMA2D foreground CLUT" hexmask.long.byte 0x24C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x24C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x24C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x24C 0.--7. 1. "BLUE,Blue" line.long 0x250 "DMA2D_FGCLUT148,DMA2D foreground CLUT" hexmask.long.byte 0x250 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x250 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x250 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x250 0.--7. 1. "BLUE,Blue" line.long 0x254 "DMA2D_FGCLUT149,DMA2D foreground CLUT" hexmask.long.byte 0x254 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x254 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x254 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x254 0.--7. 1. "BLUE,Blue" line.long 0x258 "DMA2D_FGCLUT150,DMA2D foreground CLUT" hexmask.long.byte 0x258 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x258 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x258 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x258 0.--7. 1. "BLUE,Blue" line.long 0x25C "DMA2D_FGCLUT151,DMA2D foreground CLUT" hexmask.long.byte 0x25C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x25C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x25C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x25C 0.--7. 1. "BLUE,Blue" line.long 0x260 "DMA2D_FGCLUT152,DMA2D foreground CLUT" hexmask.long.byte 0x260 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x260 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x260 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x260 0.--7. 1. "BLUE,Blue" line.long 0x264 "DMA2D_FGCLUT153,DMA2D foreground CLUT" hexmask.long.byte 0x264 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x264 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x264 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x264 0.--7. 1. "BLUE,Blue" line.long 0x268 "DMA2D_FGCLUT154,DMA2D foreground CLUT" hexmask.long.byte 0x268 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x268 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x268 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x268 0.--7. 1. "BLUE,Blue" line.long 0x26C "DMA2D_FGCLUT155,DMA2D foreground CLUT" hexmask.long.byte 0x26C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x26C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x26C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x26C 0.--7. 1. "BLUE,Blue" line.long 0x270 "DMA2D_FGCLUT156,DMA2D foreground CLUT" hexmask.long.byte 0x270 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x270 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x270 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x270 0.--7. 1. "BLUE,Blue" line.long 0x274 "DMA2D_FGCLUT157,DMA2D foreground CLUT" hexmask.long.byte 0x274 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x274 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x274 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x274 0.--7. 1. "BLUE,Blue" line.long 0x278 "DMA2D_FGCLUT158,DMA2D foreground CLUT" hexmask.long.byte 0x278 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x278 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x278 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x278 0.--7. 1. "BLUE,Blue" line.long 0x27C "DMA2D_FGCLUT159,DMA2D foreground CLUT" hexmask.long.byte 0x27C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x27C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x27C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x27C 0.--7. 1. "BLUE,Blue" line.long 0x280 "DMA2D_FGCLUT160,DMA2D foreground CLUT" hexmask.long.byte 0x280 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x280 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x280 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x280 0.--7. 1. "BLUE,Blue" line.long 0x284 "DMA2D_FGCLUT161,DMA2D foreground CLUT" hexmask.long.byte 0x284 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x284 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x284 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x284 0.--7. 1. "BLUE,Blue" line.long 0x288 "DMA2D_FGCLUT162,DMA2D foreground CLUT" hexmask.long.byte 0x288 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x288 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x288 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x288 0.--7. 1. "BLUE,Blue" line.long 0x28C "DMA2D_FGCLUT163,DMA2D foreground CLUT" hexmask.long.byte 0x28C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x28C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x28C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x28C 0.--7. 1. "BLUE,Blue" line.long 0x290 "DMA2D_FGCLUT164,DMA2D foreground CLUT" hexmask.long.byte 0x290 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x290 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x290 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x290 0.--7. 1. "BLUE,Blue" line.long 0x294 "DMA2D_FGCLUT165,DMA2D foreground CLUT" hexmask.long.byte 0x294 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x294 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x294 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x294 0.--7. 1. "BLUE,Blue" line.long 0x298 "DMA2D_FGCLUT166,DMA2D foreground CLUT" hexmask.long.byte 0x298 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x298 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x298 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x298 0.--7. 1. "BLUE,Blue" line.long 0x29C "DMA2D_FGCLUT167,DMA2D foreground CLUT" hexmask.long.byte 0x29C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x29C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x29C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x29C 0.--7. 1. "BLUE,Blue" line.long 0x2A0 "DMA2D_FGCLUT168,DMA2D foreground CLUT" hexmask.long.byte 0x2A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2A0 0.--7. 1. "BLUE,Blue" line.long 0x2A4 "DMA2D_FGCLUT169,DMA2D foreground CLUT" hexmask.long.byte 0x2A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2A4 0.--7. 1. "BLUE,Blue" line.long 0x2A8 "DMA2D_FGCLUT170,DMA2D foreground CLUT" hexmask.long.byte 0x2A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2A8 0.--7. 1. "BLUE,Blue" line.long 0x2AC "DMA2D_FGCLUT171,DMA2D foreground CLUT" hexmask.long.byte 0x2AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2AC 0.--7. 1. "BLUE,Blue" line.long 0x2B0 "DMA2D_FGCLUT172,DMA2D foreground CLUT" hexmask.long.byte 0x2B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2B0 0.--7. 1. "BLUE,Blue" line.long 0x2B4 "DMA2D_FGCLUT173,DMA2D foreground CLUT" hexmask.long.byte 0x2B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2B4 0.--7. 1. "BLUE,Blue" line.long 0x2B8 "DMA2D_FGCLUT174,DMA2D foreground CLUT" hexmask.long.byte 0x2B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2B8 0.--7. 1. "BLUE,Blue" line.long 0x2BC "DMA2D_FGCLUT175,DMA2D foreground CLUT" hexmask.long.byte 0x2BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2BC 0.--7. 1. "BLUE,Blue" line.long 0x2C0 "DMA2D_FGCLUT176,DMA2D foreground CLUT" hexmask.long.byte 0x2C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2C0 0.--7. 1. "BLUE,Blue" line.long 0x2C4 "DMA2D_FGCLUT177,DMA2D foreground CLUT" hexmask.long.byte 0x2C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2C4 0.--7. 1. "BLUE,Blue" line.long 0x2C8 "DMA2D_FGCLUT178,DMA2D foreground CLUT" hexmask.long.byte 0x2C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2C8 0.--7. 1. "BLUE,Blue" line.long 0x2CC "DMA2D_FGCLUT179,DMA2D foreground CLUT" hexmask.long.byte 0x2CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2CC 0.--7. 1. "BLUE,Blue" line.long 0x2D0 "DMA2D_FGCLUT180,DMA2D foreground CLUT" hexmask.long.byte 0x2D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2D0 0.--7. 1. "BLUE,Blue" line.long 0x2D4 "DMA2D_FGCLUT181,DMA2D foreground CLUT" hexmask.long.byte 0x2D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2D4 0.--7. 1. "BLUE,Blue" line.long 0x2D8 "DMA2D_FGCLUT182,DMA2D foreground CLUT" hexmask.long.byte 0x2D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2D8 0.--7. 1. "BLUE,Blue" line.long 0x2DC "DMA2D_FGCLUT183,DMA2D foreground CLUT" hexmask.long.byte 0x2DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2DC 0.--7. 1. "BLUE,Blue" line.long 0x2E0 "DMA2D_FGCLUT184,DMA2D foreground CLUT" hexmask.long.byte 0x2E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2E0 0.--7. 1. "BLUE,Blue" line.long 0x2E4 "DMA2D_FGCLUT185,DMA2D foreground CLUT" hexmask.long.byte 0x2E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2E4 0.--7. 1. "BLUE,Blue" line.long 0x2E8 "DMA2D_FGCLUT186,DMA2D foreground CLUT" hexmask.long.byte 0x2E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2E8 0.--7. 1. "BLUE,Blue" line.long 0x2EC "DMA2D_FGCLUT187,DMA2D foreground CLUT" hexmask.long.byte 0x2EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2EC 0.--7. 1. "BLUE,Blue" line.long 0x2F0 "DMA2D_FGCLUT188,DMA2D foreground CLUT" hexmask.long.byte 0x2F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2F0 0.--7. 1. "BLUE,Blue" line.long 0x2F4 "DMA2D_FGCLUT189,DMA2D foreground CLUT" hexmask.long.byte 0x2F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2F4 0.--7. 1. "BLUE,Blue" line.long 0x2F8 "DMA2D_FGCLUT190,DMA2D foreground CLUT" hexmask.long.byte 0x2F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2F8 0.--7. 1. "BLUE,Blue" line.long 0x2FC "DMA2D_FGCLUT191,DMA2D foreground CLUT" hexmask.long.byte 0x2FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2FC 0.--7. 1. "BLUE,Blue" line.long 0x300 "DMA2D_FGCLUT192,DMA2D foreground CLUT" hexmask.long.byte 0x300 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x300 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x300 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x300 0.--7. 1. "BLUE,Blue" line.long 0x304 "DMA2D_FGCLUT193,DMA2D foreground CLUT" hexmask.long.byte 0x304 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x304 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x304 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x304 0.--7. 1. "BLUE,Blue" line.long 0x308 "DMA2D_FGCLUT194,DMA2D foreground CLUT" hexmask.long.byte 0x308 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x308 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x308 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x308 0.--7. 1. "BLUE,Blue" line.long 0x30C "DMA2D_FGCLUT195,DMA2D foreground CLUT" hexmask.long.byte 0x30C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x30C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x30C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x30C 0.--7. 1. "BLUE,Blue" line.long 0x310 "DMA2D_FGCLUT196,DMA2D foreground CLUT" hexmask.long.byte 0x310 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x310 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x310 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x310 0.--7. 1. "BLUE,Blue" line.long 0x314 "DMA2D_FGCLUT197,DMA2D foreground CLUT" hexmask.long.byte 0x314 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x314 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x314 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x314 0.--7. 1. "BLUE,Blue" line.long 0x318 "DMA2D_FGCLUT198,DMA2D foreground CLUT" hexmask.long.byte 0x318 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x318 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x318 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x318 0.--7. 1. "BLUE,Blue" line.long 0x31C "DMA2D_FGCLUT199,DMA2D foreground CLUT" hexmask.long.byte 0x31C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x31C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x31C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x31C 0.--7. 1. "BLUE,Blue" line.long 0x320 "DMA2D_FGCLUT200,DMA2D foreground CLUT" hexmask.long.byte 0x320 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x320 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x320 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x320 0.--7. 1. "BLUE,Blue" line.long 0x324 "DMA2D_FGCLUT201,DMA2D foreground CLUT" hexmask.long.byte 0x324 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x324 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x324 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x324 0.--7. 1. "BLUE,Blue" line.long 0x328 "DMA2D_FGCLUT202,DMA2D foreground CLUT" hexmask.long.byte 0x328 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x328 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x328 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x328 0.--7. 1. "BLUE,Blue" line.long 0x32C "DMA2D_FGCLUT203,DMA2D foreground CLUT" hexmask.long.byte 0x32C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x32C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x32C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x32C 0.--7. 1. "BLUE,Blue" line.long 0x330 "DMA2D_FGCLUT204,DMA2D foreground CLUT" hexmask.long.byte 0x330 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x330 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x330 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x330 0.--7. 1. "BLUE,Blue" line.long 0x334 "DMA2D_FGCLUT205,DMA2D foreground CLUT" hexmask.long.byte 0x334 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x334 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x334 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x334 0.--7. 1. "BLUE,Blue" line.long 0x338 "DMA2D_FGCLUT206,DMA2D foreground CLUT" hexmask.long.byte 0x338 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x338 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x338 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x338 0.--7. 1. "BLUE,Blue" line.long 0x33C "DMA2D_FGCLUT207,DMA2D foreground CLUT" hexmask.long.byte 0x33C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x33C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x33C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x33C 0.--7. 1. "BLUE,Blue" line.long 0x340 "DMA2D_FGCLUT208,DMA2D foreground CLUT" hexmask.long.byte 0x340 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x340 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x340 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x340 0.--7. 1. "BLUE,Blue" line.long 0x344 "DMA2D_FGCLUT209,DMA2D foreground CLUT" hexmask.long.byte 0x344 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x344 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x344 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x344 0.--7. 1. "BLUE,Blue" line.long 0x348 "DMA2D_FGCLUT210,DMA2D foreground CLUT" hexmask.long.byte 0x348 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x348 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x348 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x348 0.--7. 1. "BLUE,Blue" line.long 0x34C "DMA2D_FGCLUT211,DMA2D foreground CLUT" hexmask.long.byte 0x34C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x34C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x34C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x34C 0.--7. 1. "BLUE,Blue" line.long 0x350 "DMA2D_FGCLUT212,DMA2D foreground CLUT" hexmask.long.byte 0x350 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x350 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x350 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x350 0.--7. 1. "BLUE,Blue" line.long 0x354 "DMA2D_FGCLUT213,DMA2D foreground CLUT" hexmask.long.byte 0x354 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x354 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x354 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x354 0.--7. 1. "BLUE,Blue" line.long 0x358 "DMA2D_FGCLUT214,DMA2D foreground CLUT" hexmask.long.byte 0x358 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x358 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x358 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x358 0.--7. 1. "BLUE,Blue" line.long 0x35C "DMA2D_FGCLUT215,DMA2D foreground CLUT" hexmask.long.byte 0x35C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x35C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x35C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x35C 0.--7. 1. "BLUE,Blue" line.long 0x360 "DMA2D_FGCLUT216,DMA2D foreground CLUT" hexmask.long.byte 0x360 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x360 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x360 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x360 0.--7. 1. "BLUE,Blue" line.long 0x364 "DMA2D_FGCLUT217,DMA2D foreground CLUT" hexmask.long.byte 0x364 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x364 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x364 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x364 0.--7. 1. "BLUE,Blue" line.long 0x368 "DMA2D_FGCLUT218,DMA2D foreground CLUT" hexmask.long.byte 0x368 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x368 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x368 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x368 0.--7. 1. "BLUE,Blue" line.long 0x36C "DMA2D_FGCLUT219,DMA2D foreground CLUT" hexmask.long.byte 0x36C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x36C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x36C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x36C 0.--7. 1. "BLUE,Blue" line.long 0x370 "DMA2D_FGCLUT220,DMA2D foreground CLUT" hexmask.long.byte 0x370 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x370 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x370 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x370 0.--7. 1. "BLUE,Blue" line.long 0x374 "DMA2D_FGCLUT221,DMA2D foreground CLUT" hexmask.long.byte 0x374 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x374 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x374 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x374 0.--7. 1. "BLUE,Blue" line.long 0x378 "DMA2D_FGCLUT222,DMA2D foreground CLUT" hexmask.long.byte 0x378 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x378 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x378 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x378 0.--7. 1. "BLUE,Blue" line.long 0x37C "DMA2D_FGCLUT223,DMA2D foreground CLUT" hexmask.long.byte 0x37C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x37C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x37C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x37C 0.--7. 1. "BLUE,Blue" line.long 0x380 "DMA2D_FGCLUT224,DMA2D foreground CLUT" hexmask.long.byte 0x380 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x380 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x380 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x380 0.--7. 1. "BLUE,Blue" line.long 0x384 "DMA2D_FGCLUT225,DMA2D foreground CLUT" hexmask.long.byte 0x384 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x384 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x384 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x384 0.--7. 1. "BLUE,Blue" line.long 0x388 "DMA2D_FGCLUT226,DMA2D foreground CLUT" hexmask.long.byte 0x388 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x388 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x388 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x388 0.--7. 1. "BLUE,Blue" line.long 0x38C "DMA2D_FGCLUT227,DMA2D foreground CLUT" hexmask.long.byte 0x38C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x38C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x38C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x38C 0.--7. 1. "BLUE,Blue" line.long 0x390 "DMA2D_FGCLUT228,DMA2D foreground CLUT" hexmask.long.byte 0x390 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x390 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x390 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x390 0.--7. 1. "BLUE,Blue" line.long 0x394 "DMA2D_FGCLUT229,DMA2D foreground CLUT" hexmask.long.byte 0x394 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x394 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x394 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x394 0.--7. 1. "BLUE,Blue" line.long 0x398 "DMA2D_FGCLUT230,DMA2D foreground CLUT" hexmask.long.byte 0x398 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x398 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x398 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x398 0.--7. 1. "BLUE,Blue" line.long 0x39C "DMA2D_FGCLUT231,DMA2D foreground CLUT" hexmask.long.byte 0x39C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x39C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x39C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x39C 0.--7. 1. "BLUE,Blue" line.long 0x3A0 "DMA2D_FGCLUT232,DMA2D foreground CLUT" hexmask.long.byte 0x3A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3A0 0.--7. 1. "BLUE,Blue" line.long 0x3A4 "DMA2D_FGCLUT233,DMA2D foreground CLUT" hexmask.long.byte 0x3A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3A4 0.--7. 1. "BLUE,Blue" line.long 0x3A8 "DMA2D_FGCLUT234,DMA2D foreground CLUT" hexmask.long.byte 0x3A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3A8 0.--7. 1. "BLUE,Blue" line.long 0x3AC "DMA2D_FGCLUT235,DMA2D foreground CLUT" hexmask.long.byte 0x3AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3AC 0.--7. 1. "BLUE,Blue" line.long 0x3B0 "DMA2D_FGCLUT236,DMA2D foreground CLUT" hexmask.long.byte 0x3B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3B0 0.--7. 1. "BLUE,Blue" line.long 0x3B4 "DMA2D_FGCLUT237,DMA2D foreground CLUT" hexmask.long.byte 0x3B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3B4 0.--7. 1. "BLUE,Blue" line.long 0x3B8 "DMA2D_FGCLUT238,DMA2D foreground CLUT" hexmask.long.byte 0x3B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3B8 0.--7. 1. "BLUE,Blue" line.long 0x3BC "DMA2D_FGCLUT239,DMA2D foreground CLUT" hexmask.long.byte 0x3BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3BC 0.--7. 1. "BLUE,Blue" line.long 0x3C0 "DMA2D_FGCLUT240,DMA2D foreground CLUT" hexmask.long.byte 0x3C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3C0 0.--7. 1. "BLUE,Blue" line.long 0x3C4 "DMA2D_FGCLUT241,DMA2D foreground CLUT" hexmask.long.byte 0x3C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3C4 0.--7. 1. "BLUE,Blue" line.long 0x3C8 "DMA2D_FGCLUT242,DMA2D foreground CLUT" hexmask.long.byte 0x3C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3C8 0.--7. 1. "BLUE,Blue" line.long 0x3CC "DMA2D_FGCLUT243,DMA2D foreground CLUT" hexmask.long.byte 0x3CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3CC 0.--7. 1. "BLUE,Blue" line.long 0x3D0 "DMA2D_FGCLUT244,DMA2D foreground CLUT" hexmask.long.byte 0x3D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3D0 0.--7. 1. "BLUE,Blue" line.long 0x3D4 "DMA2D_FGCLUT245,DMA2D foreground CLUT" hexmask.long.byte 0x3D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3D4 0.--7. 1. "BLUE,Blue" line.long 0x3D8 "DMA2D_FGCLUT246,DMA2D foreground CLUT" hexmask.long.byte 0x3D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3D8 0.--7. 1. "BLUE,Blue" line.long 0x3DC "DMA2D_FGCLUT247,DMA2D foreground CLUT" hexmask.long.byte 0x3DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3DC 0.--7. 1. "BLUE,Blue" line.long 0x3E0 "DMA2D_FGCLUT248,DMA2D foreground CLUT" hexmask.long.byte 0x3E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3E0 0.--7. 1. "BLUE,Blue" line.long 0x3E4 "DMA2D_FGCLUT249,DMA2D foreground CLUT" hexmask.long.byte 0x3E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3E4 0.--7. 1. "BLUE,Blue" line.long 0x3E8 "DMA2D_FGCLUT250,DMA2D foreground CLUT" hexmask.long.byte 0x3E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3E8 0.--7. 1. "BLUE,Blue" line.long 0x3EC "DMA2D_FGCLUT251,DMA2D foreground CLUT" hexmask.long.byte 0x3EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3EC 0.--7. 1. "BLUE,Blue" line.long 0x3F0 "DMA2D_FGCLUT252,DMA2D foreground CLUT" hexmask.long.byte 0x3F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3F0 0.--7. 1. "BLUE,Blue" line.long 0x3F4 "DMA2D_FGCLUT253,DMA2D foreground CLUT" hexmask.long.byte 0x3F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3F4 0.--7. 1. "BLUE,Blue" line.long 0x3F8 "DMA2D_FGCLUT254,DMA2D foreground CLUT" hexmask.long.byte 0x3F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3F8 0.--7. 1. "BLUE,Blue" line.long 0x3FC "DMA2D_FGCLUT255,DMA2D foreground CLUT" hexmask.long.byte 0x3FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3FC 0.--7. 1. "BLUE,Blue" line.long 0x400 "DMA2D_BGCLUT0,DMA2D background CLUT" hexmask.long.byte 0x400 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x400 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x400 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x400 0.--7. 1. "BLUE,Blue" line.long 0x404 "DMA2D_BGCLUT1,DMA2D background CLUT" hexmask.long.byte 0x404 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x404 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x404 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x404 0.--7. 1. "BLUE,Blue" line.long 0x408 "DMA2D_BGCLUT2,DMA2D background CLUT" hexmask.long.byte 0x408 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x408 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x408 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x408 0.--7. 1. "BLUE,Blue" line.long 0x40C "DMA2D_BGCLUT3,DMA2D background CLUT" hexmask.long.byte 0x40C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x40C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x40C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x40C 0.--7. 1. "BLUE,Blue" line.long 0x410 "DMA2D_BGCLUT4,DMA2D background CLUT" hexmask.long.byte 0x410 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x410 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x410 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x410 0.--7. 1. "BLUE,Blue" line.long 0x414 "DMA2D_BGCLUT5,DMA2D background CLUT" hexmask.long.byte 0x414 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x414 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x414 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x414 0.--7. 1. "BLUE,Blue" line.long 0x418 "DMA2D_BGCLUT6,DMA2D background CLUT" hexmask.long.byte 0x418 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x418 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x418 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x418 0.--7. 1. "BLUE,Blue" line.long 0x41C "DMA2D_BGCLUT7,DMA2D background CLUT" hexmask.long.byte 0x41C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x41C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x41C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x41C 0.--7. 1. "BLUE,Blue" line.long 0x420 "DMA2D_BGCLUT8,DMA2D background CLUT" hexmask.long.byte 0x420 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x420 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x420 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x420 0.--7. 1. "BLUE,Blue" line.long 0x424 "DMA2D_BGCLUT9,DMA2D background CLUT" hexmask.long.byte 0x424 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x424 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x424 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x424 0.--7. 1. "BLUE,Blue" line.long 0x428 "DMA2D_BGCLUT10,DMA2D background CLUT" hexmask.long.byte 0x428 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x428 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x428 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x428 0.--7. 1. "BLUE,Blue" line.long 0x42C "DMA2D_BGCLUT11,DMA2D background CLUT" hexmask.long.byte 0x42C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x42C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x42C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x42C 0.--7. 1. "BLUE,Blue" line.long 0x430 "DMA2D_BGCLUT12,DMA2D background CLUT" hexmask.long.byte 0x430 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x430 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x430 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x430 0.--7. 1. "BLUE,Blue" line.long 0x434 "DMA2D_BGCLUT13,DMA2D background CLUT" hexmask.long.byte 0x434 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x434 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x434 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x434 0.--7. 1. "BLUE,Blue" line.long 0x438 "DMA2D_BGCLUT14,DMA2D background CLUT" hexmask.long.byte 0x438 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x438 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x438 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x438 0.--7. 1. "BLUE,Blue" line.long 0x43C "DMA2D_BGCLUT15,DMA2D background CLUT" hexmask.long.byte 0x43C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x43C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x43C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x43C 0.--7. 1. "BLUE,Blue" line.long 0x440 "DMA2D_BGCLUT16,DMA2D background CLUT" hexmask.long.byte 0x440 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x440 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x440 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x440 0.--7. 1. "BLUE,Blue" line.long 0x444 "DMA2D_BGCLUT17,DMA2D background CLUT" hexmask.long.byte 0x444 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x444 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x444 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x444 0.--7. 1. "BLUE,Blue" line.long 0x448 "DMA2D_BGCLUT18,DMA2D background CLUT" hexmask.long.byte 0x448 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x448 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x448 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x448 0.--7. 1. "BLUE,Blue" line.long 0x44C "DMA2D_BGCLUT19,DMA2D background CLUT" hexmask.long.byte 0x44C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x44C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x44C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x44C 0.--7. 1. "BLUE,Blue" line.long 0x450 "DMA2D_BGCLUT20,DMA2D background CLUT" hexmask.long.byte 0x450 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x450 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x450 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x450 0.--7. 1. "BLUE,Blue" line.long 0x454 "DMA2D_BGCLUT21,DMA2D background CLUT" hexmask.long.byte 0x454 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x454 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x454 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x454 0.--7. 1. "BLUE,Blue" line.long 0x458 "DMA2D_BGCLUT22,DMA2D background CLUT" hexmask.long.byte 0x458 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x458 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x458 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x458 0.--7. 1. "BLUE,Blue" line.long 0x45C "DMA2D_BGCLUT23,DMA2D background CLUT" hexmask.long.byte 0x45C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x45C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x45C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x45C 0.--7. 1. "BLUE,Blue" line.long 0x460 "DMA2D_BGCLUT24,DMA2D background CLUT" hexmask.long.byte 0x460 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x460 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x460 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x460 0.--7. 1. "BLUE,Blue" line.long 0x464 "DMA2D_BGCLUT25,DMA2D background CLUT" hexmask.long.byte 0x464 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x464 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x464 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x464 0.--7. 1. "BLUE,Blue" line.long 0x468 "DMA2D_BGCLUT26,DMA2D background CLUT" hexmask.long.byte 0x468 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x468 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x468 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x468 0.--7. 1. "BLUE,Blue" line.long 0x46C "DMA2D_BGCLUT27,DMA2D background CLUT" hexmask.long.byte 0x46C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x46C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x46C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x46C 0.--7. 1. "BLUE,Blue" line.long 0x470 "DMA2D_BGCLUT28,DMA2D background CLUT" hexmask.long.byte 0x470 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x470 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x470 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x470 0.--7. 1. "BLUE,Blue" line.long 0x474 "DMA2D_BGCLUT29,DMA2D background CLUT" hexmask.long.byte 0x474 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x474 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x474 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x474 0.--7. 1. "BLUE,Blue" line.long 0x478 "DMA2D_BGCLUT30,DMA2D background CLUT" hexmask.long.byte 0x478 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x478 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x478 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x478 0.--7. 1. "BLUE,Blue" line.long 0x47C "DMA2D_BGCLUT31,DMA2D background CLUT" hexmask.long.byte 0x47C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x47C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x47C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x47C 0.--7. 1. "BLUE,Blue" line.long 0x480 "DMA2D_BGCLUT32,DMA2D background CLUT" hexmask.long.byte 0x480 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x480 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x480 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x480 0.--7. 1. "BLUE,Blue" line.long 0x484 "DMA2D_BGCLUT33,DMA2D background CLUT" hexmask.long.byte 0x484 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x484 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x484 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x484 0.--7. 1. "BLUE,Blue" line.long 0x488 "DMA2D_BGCLUT34,DMA2D background CLUT" hexmask.long.byte 0x488 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x488 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x488 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x488 0.--7. 1. "BLUE,Blue" line.long 0x48C "DMA2D_BGCLUT35,DMA2D background CLUT" hexmask.long.byte 0x48C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x48C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x48C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x48C 0.--7. 1. "BLUE,Blue" line.long 0x490 "DMA2D_BGCLUT36,DMA2D background CLUT" hexmask.long.byte 0x490 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x490 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x490 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x490 0.--7. 1. "BLUE,Blue" line.long 0x494 "DMA2D_BGCLUT37,DMA2D background CLUT" hexmask.long.byte 0x494 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x494 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x494 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x494 0.--7. 1. "BLUE,Blue" line.long 0x498 "DMA2D_BGCLUT38,DMA2D background CLUT" hexmask.long.byte 0x498 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x498 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x498 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x498 0.--7. 1. "BLUE,Blue" line.long 0x49C "DMA2D_BGCLUT39,DMA2D background CLUT" hexmask.long.byte 0x49C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x49C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x49C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x49C 0.--7. 1. "BLUE,Blue" line.long 0x4A0 "DMA2D_BGCLUT40,DMA2D background CLUT" hexmask.long.byte 0x4A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4A0 0.--7. 1. "BLUE,Blue" line.long 0x4A4 "DMA2D_BGCLUT41,DMA2D background CLUT" hexmask.long.byte 0x4A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4A4 0.--7. 1. "BLUE,Blue" line.long 0x4A8 "DMA2D_BGCLUT42,DMA2D background CLUT" hexmask.long.byte 0x4A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4A8 0.--7. 1. "BLUE,Blue" line.long 0x4AC "DMA2D_BGCLUT43,DMA2D background CLUT" hexmask.long.byte 0x4AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4AC 0.--7. 1. "BLUE,Blue" line.long 0x4B0 "DMA2D_BGCLUT44,DMA2D background CLUT" hexmask.long.byte 0x4B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4B0 0.--7. 1. "BLUE,Blue" line.long 0x4B4 "DMA2D_BGCLUT45,DMA2D background CLUT" hexmask.long.byte 0x4B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4B4 0.--7. 1. "BLUE,Blue" line.long 0x4B8 "DMA2D_BGCLUT46,DMA2D background CLUT" hexmask.long.byte 0x4B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4B8 0.--7. 1. "BLUE,Blue" line.long 0x4BC "DMA2D_BGCLUT47,DMA2D background CLUT" hexmask.long.byte 0x4BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4BC 0.--7. 1. "BLUE,Blue" line.long 0x4C0 "DMA2D_BGCLUT48,DMA2D background CLUT" hexmask.long.byte 0x4C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4C0 0.--7. 1. "BLUE,Blue" line.long 0x4C4 "DMA2D_BGCLUT49,DMA2D background CLUT" hexmask.long.byte 0x4C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4C4 0.--7. 1. "BLUE,Blue" line.long 0x4C8 "DMA2D_BGCLUT50,DMA2D background CLUT" hexmask.long.byte 0x4C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4C8 0.--7. 1. "BLUE,Blue" line.long 0x4CC "DMA2D_BGCLUT51,DMA2D background CLUT" hexmask.long.byte 0x4CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4CC 0.--7. 1. "BLUE,Blue" line.long 0x4D0 "DMA2D_BGCLUT52,DMA2D background CLUT" hexmask.long.byte 0x4D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4D0 0.--7. 1. "BLUE,Blue" line.long 0x4D4 "DMA2D_BGCLUT53,DMA2D background CLUT" hexmask.long.byte 0x4D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4D4 0.--7. 1. "BLUE,Blue" line.long 0x4D8 "DMA2D_BGCLUT54,DMA2D background CLUT" hexmask.long.byte 0x4D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4D8 0.--7. 1. "BLUE,Blue" line.long 0x4DC "DMA2D_BGCLUT55,DMA2D background CLUT" hexmask.long.byte 0x4DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4DC 0.--7. 1. "BLUE,Blue" line.long 0x4E0 "DMA2D_BGCLUT56,DMA2D background CLUT" hexmask.long.byte 0x4E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4E0 0.--7. 1. "BLUE,Blue" line.long 0x4E4 "DMA2D_BGCLUT57,DMA2D background CLUT" hexmask.long.byte 0x4E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4E4 0.--7. 1. "BLUE,Blue" line.long 0x4E8 "DMA2D_BGCLUT58,DMA2D background CLUT" hexmask.long.byte 0x4E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4E8 0.--7. 1. "BLUE,Blue" line.long 0x4EC "DMA2D_BGCLUT59,DMA2D background CLUT" hexmask.long.byte 0x4EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4EC 0.--7. 1. "BLUE,Blue" line.long 0x4F0 "DMA2D_BGCLUT60,DMA2D background CLUT" hexmask.long.byte 0x4F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4F0 0.--7. 1. "BLUE,Blue" line.long 0x4F4 "DMA2D_BGCLUT61,DMA2D background CLUT" hexmask.long.byte 0x4F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4F4 0.--7. 1. "BLUE,Blue" line.long 0x4F8 "DMA2D_BGCLUT62,DMA2D background CLUT" hexmask.long.byte 0x4F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4F8 0.--7. 1. "BLUE,Blue" line.long 0x4FC "DMA2D_BGCLUT63,DMA2D background CLUT" hexmask.long.byte 0x4FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4FC 0.--7. 1. "BLUE,Blue" line.long 0x500 "DMA2D_BGCLUT64,DMA2D background CLUT" hexmask.long.byte 0x500 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x500 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x500 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x500 0.--7. 1. "BLUE,Blue" line.long 0x504 "DMA2D_BGCLUT65,DMA2D background CLUT" hexmask.long.byte 0x504 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x504 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x504 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x504 0.--7. 1. "BLUE,Blue" line.long 0x508 "DMA2D_BGCLUT66,DMA2D background CLUT" hexmask.long.byte 0x508 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x508 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x508 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x508 0.--7. 1. "BLUE,Blue" line.long 0x50C "DMA2D_BGCLUT67,DMA2D background CLUT" hexmask.long.byte 0x50C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x50C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x50C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x50C 0.--7. 1. "BLUE,Blue" line.long 0x510 "DMA2D_BGCLUT68,DMA2D background CLUT" hexmask.long.byte 0x510 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x510 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x510 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x510 0.--7. 1. "BLUE,Blue" line.long 0x514 "DMA2D_BGCLUT69,DMA2D background CLUT" hexmask.long.byte 0x514 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x514 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x514 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x514 0.--7. 1. "BLUE,Blue" line.long 0x518 "DMA2D_BGCLUT70,DMA2D background CLUT" hexmask.long.byte 0x518 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x518 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x518 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x518 0.--7. 1. "BLUE,Blue" line.long 0x51C "DMA2D_BGCLUT71,DMA2D background CLUT" hexmask.long.byte 0x51C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x51C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x51C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x51C 0.--7. 1. "BLUE,Blue" line.long 0x520 "DMA2D_BGCLUT72,DMA2D background CLUT" hexmask.long.byte 0x520 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x520 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x520 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x520 0.--7. 1. "BLUE,Blue" line.long 0x524 "DMA2D_BGCLUT73,DMA2D background CLUT" hexmask.long.byte 0x524 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x524 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x524 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x524 0.--7. 1. "BLUE,Blue" line.long 0x528 "DMA2D_BGCLUT74,DMA2D background CLUT" hexmask.long.byte 0x528 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x528 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x528 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x528 0.--7. 1. "BLUE,Blue" line.long 0x52C "DMA2D_BGCLUT75,DMA2D background CLUT" hexmask.long.byte 0x52C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x52C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x52C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x52C 0.--7. 1. "BLUE,Blue" line.long 0x530 "DMA2D_BGCLUT76,DMA2D background CLUT" hexmask.long.byte 0x530 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x530 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x530 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x530 0.--7. 1. "BLUE,Blue" line.long 0x534 "DMA2D_BGCLUT77,DMA2D background CLUT" hexmask.long.byte 0x534 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x534 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x534 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x534 0.--7. 1. "BLUE,Blue" line.long 0x538 "DMA2D_BGCLUT78,DMA2D background CLUT" hexmask.long.byte 0x538 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x538 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x538 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x538 0.--7. 1. "BLUE,Blue" line.long 0x53C "DMA2D_BGCLUT79,DMA2D background CLUT" hexmask.long.byte 0x53C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x53C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x53C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x53C 0.--7. 1. "BLUE,Blue" line.long 0x540 "DMA2D_BGCLUT80,DMA2D background CLUT" hexmask.long.byte 0x540 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x540 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x540 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x540 0.--7. 1. "BLUE,Blue" line.long 0x544 "DMA2D_BGCLUT81,DMA2D background CLUT" hexmask.long.byte 0x544 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x544 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x544 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x544 0.--7. 1. "BLUE,Blue" line.long 0x548 "DMA2D_BGCLUT82,DMA2D background CLUT" hexmask.long.byte 0x548 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x548 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x548 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x548 0.--7. 1. "BLUE,Blue" line.long 0x54C "DMA2D_BGCLUT83,DMA2D background CLUT" hexmask.long.byte 0x54C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x54C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x54C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x54C 0.--7. 1. "BLUE,Blue" line.long 0x550 "DMA2D_BGCLUT84,DMA2D background CLUT" hexmask.long.byte 0x550 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x550 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x550 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x550 0.--7. 1. "BLUE,Blue" line.long 0x554 "DMA2D_BGCLUT85,DMA2D background CLUT" hexmask.long.byte 0x554 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x554 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x554 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x554 0.--7. 1. "BLUE,Blue" line.long 0x558 "DMA2D_BGCLUT86,DMA2D background CLUT" hexmask.long.byte 0x558 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x558 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x558 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x558 0.--7. 1. "BLUE,Blue" line.long 0x55C "DMA2D_BGCLUT87,DMA2D background CLUT" hexmask.long.byte 0x55C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x55C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x55C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x55C 0.--7. 1. "BLUE,Blue" line.long 0x560 "DMA2D_BGCLUT88,DMA2D background CLUT" hexmask.long.byte 0x560 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x560 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x560 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x560 0.--7. 1. "BLUE,Blue" line.long 0x564 "DMA2D_BGCLUT89,DMA2D background CLUT" hexmask.long.byte 0x564 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x564 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x564 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x564 0.--7. 1. "BLUE,Blue" line.long 0x568 "DMA2D_BGCLUT90,DMA2D background CLUT" hexmask.long.byte 0x568 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x568 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x568 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x568 0.--7. 1. "BLUE,Blue" line.long 0x56C "DMA2D_BGCLUT91,DMA2D background CLUT" hexmask.long.byte 0x56C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x56C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x56C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x56C 0.--7. 1. "BLUE,Blue" line.long 0x570 "DMA2D_BGCLUT92,DMA2D background CLUT" hexmask.long.byte 0x570 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x570 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x570 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x570 0.--7. 1. "BLUE,Blue" line.long 0x574 "DMA2D_BGCLUT93,DMA2D background CLUT" hexmask.long.byte 0x574 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x574 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x574 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x574 0.--7. 1. "BLUE,Blue" line.long 0x578 "DMA2D_BGCLUT94,DMA2D background CLUT" hexmask.long.byte 0x578 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x578 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x578 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x578 0.--7. 1. "BLUE,Blue" line.long 0x57C "DMA2D_BGCLUT95,DMA2D background CLUT" hexmask.long.byte 0x57C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x57C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x57C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x57C 0.--7. 1. "BLUE,Blue" line.long 0x580 "DMA2D_BGCLUT96,DMA2D background CLUT" hexmask.long.byte 0x580 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x580 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x580 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x580 0.--7. 1. "BLUE,Blue" line.long 0x584 "DMA2D_BGCLUT97,DMA2D background CLUT" hexmask.long.byte 0x584 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x584 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x584 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x584 0.--7. 1. "BLUE,Blue" line.long 0x588 "DMA2D_BGCLUT98,DMA2D background CLUT" hexmask.long.byte 0x588 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x588 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x588 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x588 0.--7. 1. "BLUE,Blue" line.long 0x58C "DMA2D_BGCLUT99,DMA2D background CLUT" hexmask.long.byte 0x58C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x58C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x58C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x58C 0.--7. 1. "BLUE,Blue" line.long 0x590 "DMA2D_BGCLUT100,DMA2D background CLUT" hexmask.long.byte 0x590 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x590 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x590 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x590 0.--7. 1. "BLUE,Blue" line.long 0x594 "DMA2D_BGCLUT101,DMA2D background CLUT" hexmask.long.byte 0x594 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x594 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x594 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x594 0.--7. 1. "BLUE,Blue" line.long 0x598 "DMA2D_BGCLUT102,DMA2D background CLUT" hexmask.long.byte 0x598 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x598 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x598 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x598 0.--7. 1. "BLUE,Blue" line.long 0x59C "DMA2D_BGCLUT103,DMA2D background CLUT" hexmask.long.byte 0x59C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x59C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x59C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x59C 0.--7. 1. "BLUE,Blue" line.long 0x5A0 "DMA2D_BGCLUT104,DMA2D background CLUT" hexmask.long.byte 0x5A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5A0 0.--7. 1. "BLUE,Blue" line.long 0x5A4 "DMA2D_BGCLUT105,DMA2D background CLUT" hexmask.long.byte 0x5A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5A4 0.--7. 1. "BLUE,Blue" line.long 0x5A8 "DMA2D_BGCLUT106,DMA2D background CLUT" hexmask.long.byte 0x5A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5A8 0.--7. 1. "BLUE,Blue" line.long 0x5AC "DMA2D_BGCLUT107,DMA2D background CLUT" hexmask.long.byte 0x5AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5AC 0.--7. 1. "BLUE,Blue" line.long 0x5B0 "DMA2D_BGCLUT108,DMA2D background CLUT" hexmask.long.byte 0x5B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5B0 0.--7. 1. "BLUE,Blue" line.long 0x5B4 "DMA2D_BGCLUT109,DMA2D background CLUT" hexmask.long.byte 0x5B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5B4 0.--7. 1. "BLUE,Blue" line.long 0x5B8 "DMA2D_BGCLUT110,DMA2D background CLUT" hexmask.long.byte 0x5B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5B8 0.--7. 1. "BLUE,Blue" line.long 0x5BC "DMA2D_BGCLUT111,DMA2D background CLUT" hexmask.long.byte 0x5BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5BC 0.--7. 1. "BLUE,Blue" line.long 0x5C0 "DMA2D_BGCLUT112,DMA2D background CLUT" hexmask.long.byte 0x5C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5C0 0.--7. 1. "BLUE,Blue" line.long 0x5C4 "DMA2D_BGCLUT113,DMA2D background CLUT" hexmask.long.byte 0x5C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5C4 0.--7. 1. "BLUE,Blue" line.long 0x5C8 "DMA2D_BGCLUT114,DMA2D background CLUT" hexmask.long.byte 0x5C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5C8 0.--7. 1. "BLUE,Blue" line.long 0x5CC "DMA2D_BGCLUT115,DMA2D background CLUT" hexmask.long.byte 0x5CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5CC 0.--7. 1. "BLUE,Blue" line.long 0x5D0 "DMA2D_BGCLUT116,DMA2D background CLUT" hexmask.long.byte 0x5D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5D0 0.--7. 1. "BLUE,Blue" line.long 0x5D4 "DMA2D_BGCLUT117,DMA2D background CLUT" hexmask.long.byte 0x5D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5D4 0.--7. 1. "BLUE,Blue" line.long 0x5D8 "DMA2D_BGCLUT118,DMA2D background CLUT" hexmask.long.byte 0x5D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5D8 0.--7. 1. "BLUE,Blue" line.long 0x5DC "DMA2D_BGCLUT119,DMA2D background CLUT" hexmask.long.byte 0x5DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5DC 0.--7. 1. "BLUE,Blue" line.long 0x5E0 "DMA2D_BGCLUT120,DMA2D background CLUT" hexmask.long.byte 0x5E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5E0 0.--7. 1. "BLUE,Blue" line.long 0x5E4 "DMA2D_BGCLUT121,DMA2D background CLUT" hexmask.long.byte 0x5E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5E4 0.--7. 1. "BLUE,Blue" line.long 0x5E8 "DMA2D_BGCLUT122,DMA2D background CLUT" hexmask.long.byte 0x5E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5E8 0.--7. 1. "BLUE,Blue" line.long 0x5EC "DMA2D_BGCLUT123,DMA2D background CLUT" hexmask.long.byte 0x5EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5EC 0.--7. 1. "BLUE,Blue" line.long 0x5F0 "DMA2D_BGCLUT124,DMA2D background CLUT" hexmask.long.byte 0x5F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5F0 0.--7. 1. "BLUE,Blue" line.long 0x5F4 "DMA2D_BGCLUT125,DMA2D background CLUT" hexmask.long.byte 0x5F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5F4 0.--7. 1. "BLUE,Blue" line.long 0x5F8 "DMA2D_BGCLUT126,DMA2D background CLUT" hexmask.long.byte 0x5F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5F8 0.--7. 1. "BLUE,Blue" line.long 0x5FC "DMA2D_BGCLUT127,DMA2D background CLUT" hexmask.long.byte 0x5FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5FC 0.--7. 1. "BLUE,Blue" line.long 0x600 "DMA2D_BGCLUT128,DMA2D background CLUT" hexmask.long.byte 0x600 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x600 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x600 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x600 0.--7. 1. "BLUE,Blue" line.long 0x604 "DMA2D_BGCLUT129,DMA2D background CLUT" hexmask.long.byte 0x604 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x604 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x604 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x604 0.--7. 1. "BLUE,Blue" line.long 0x608 "DMA2D_BGCLUT130,DMA2D background CLUT" hexmask.long.byte 0x608 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x608 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x608 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x608 0.--7. 1. "BLUE,Blue" line.long 0x60C "DMA2D_BGCLUT131,DMA2D background CLUT" hexmask.long.byte 0x60C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x60C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x60C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x60C 0.--7. 1. "BLUE,Blue" line.long 0x610 "DMA2D_BGCLUT132,DMA2D background CLUT" hexmask.long.byte 0x610 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x610 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x610 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x610 0.--7. 1. "BLUE,Blue" line.long 0x614 "DMA2D_BGCLUT133,DMA2D background CLUT" hexmask.long.byte 0x614 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x614 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x614 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x614 0.--7. 1. "BLUE,Blue" line.long 0x618 "DMA2D_BGCLUT134,DMA2D background CLUT" hexmask.long.byte 0x618 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x618 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x618 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x618 0.--7. 1. "BLUE,Blue" line.long 0x61C "DMA2D_BGCLUT135,DMA2D background CLUT" hexmask.long.byte 0x61C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x61C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x61C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x61C 0.--7. 1. "BLUE,Blue" line.long 0x620 "DMA2D_BGCLUT136,DMA2D background CLUT" hexmask.long.byte 0x620 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x620 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x620 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x620 0.--7. 1. "BLUE,Blue" line.long 0x624 "DMA2D_BGCLUT137,DMA2D background CLUT" hexmask.long.byte 0x624 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x624 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x624 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x624 0.--7. 1. "BLUE,Blue" line.long 0x628 "DMA2D_BGCLUT138,DMA2D background CLUT" hexmask.long.byte 0x628 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x628 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x628 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x628 0.--7. 1. "BLUE,Blue" line.long 0x62C "DMA2D_BGCLUT139,DMA2D background CLUT" hexmask.long.byte 0x62C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x62C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x62C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x62C 0.--7. 1. "BLUE,Blue" line.long 0x630 "DMA2D_BGCLUT140,DMA2D background CLUT" hexmask.long.byte 0x630 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x630 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x630 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x630 0.--7. 1. "BLUE,Blue" line.long 0x634 "DMA2D_BGCLUT141,DMA2D background CLUT" hexmask.long.byte 0x634 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x634 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x634 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x634 0.--7. 1. "BLUE,Blue" line.long 0x638 "DMA2D_BGCLUT142,DMA2D background CLUT" hexmask.long.byte 0x638 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x638 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x638 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x638 0.--7. 1. "BLUE,Blue" line.long 0x63C "DMA2D_BGCLUT143,DMA2D background CLUT" hexmask.long.byte 0x63C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x63C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x63C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x63C 0.--7. 1. "BLUE,Blue" line.long 0x640 "DMA2D_BGCLUT144,DMA2D background CLUT" hexmask.long.byte 0x640 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x640 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x640 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x640 0.--7. 1. "BLUE,Blue" line.long 0x644 "DMA2D_BGCLUT145,DMA2D background CLUT" hexmask.long.byte 0x644 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x644 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x644 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x644 0.--7. 1. "BLUE,Blue" line.long 0x648 "DMA2D_BGCLUT146,DMA2D background CLUT" hexmask.long.byte 0x648 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x648 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x648 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x648 0.--7. 1. "BLUE,Blue" line.long 0x64C "DMA2D_BGCLUT147,DMA2D background CLUT" hexmask.long.byte 0x64C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x64C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x64C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x64C 0.--7. 1. "BLUE,Blue" line.long 0x650 "DMA2D_BGCLUT148,DMA2D background CLUT" hexmask.long.byte 0x650 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x650 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x650 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x650 0.--7. 1. "BLUE,Blue" line.long 0x654 "DMA2D_BGCLUT149,DMA2D background CLUT" hexmask.long.byte 0x654 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x654 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x654 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x654 0.--7. 1. "BLUE,Blue" line.long 0x658 "DMA2D_BGCLUT150,DMA2D background CLUT" hexmask.long.byte 0x658 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x658 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x658 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x658 0.--7. 1. "BLUE,Blue" line.long 0x65C "DMA2D_BGCLUT151,DMA2D background CLUT" hexmask.long.byte 0x65C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x65C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x65C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x65C 0.--7. 1. "BLUE,Blue" line.long 0x660 "DMA2D_BGCLUT152,DMA2D background CLUT" hexmask.long.byte 0x660 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x660 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x660 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x660 0.--7. 1. "BLUE,Blue" line.long 0x664 "DMA2D_BGCLUT153,DMA2D background CLUT" hexmask.long.byte 0x664 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x664 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x664 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x664 0.--7. 1. "BLUE,Blue" line.long 0x668 "DMA2D_BGCLUT154,DMA2D background CLUT" hexmask.long.byte 0x668 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x668 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x668 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x668 0.--7. 1. "BLUE,Blue" line.long 0x66C "DMA2D_BGCLUT155,DMA2D background CLUT" hexmask.long.byte 0x66C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x66C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x66C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x66C 0.--7. 1. "BLUE,Blue" line.long 0x670 "DMA2D_BGCLUT156,DMA2D background CLUT" hexmask.long.byte 0x670 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x670 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x670 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x670 0.--7. 1. "BLUE,Blue" line.long 0x674 "DMA2D_BGCLUT157,DMA2D background CLUT" hexmask.long.byte 0x674 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x674 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x674 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x674 0.--7. 1. "BLUE,Blue" line.long 0x678 "DMA2D_BGCLUT158,DMA2D background CLUT" hexmask.long.byte 0x678 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x678 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x678 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x678 0.--7. 1. "BLUE,Blue" line.long 0x67C "DMA2D_BGCLUT159,DMA2D background CLUT" hexmask.long.byte 0x67C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x67C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x67C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x67C 0.--7. 1. "BLUE,Blue" line.long 0x680 "DMA2D_BGCLUT160,DMA2D background CLUT" hexmask.long.byte 0x680 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x680 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x680 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x680 0.--7. 1. "BLUE,Blue" line.long 0x684 "DMA2D_BGCLUT161,DMA2D background CLUT" hexmask.long.byte 0x684 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x684 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x684 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x684 0.--7. 1. "BLUE,Blue" line.long 0x688 "DMA2D_BGCLUT162,DMA2D background CLUT" hexmask.long.byte 0x688 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x688 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x688 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x688 0.--7. 1. "BLUE,Blue" line.long 0x68C "DMA2D_BGCLUT163,DMA2D background CLUT" hexmask.long.byte 0x68C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x68C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x68C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x68C 0.--7. 1. "BLUE,Blue" line.long 0x690 "DMA2D_BGCLUT164,DMA2D background CLUT" hexmask.long.byte 0x690 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x690 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x690 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x690 0.--7. 1. "BLUE,Blue" line.long 0x694 "DMA2D_BGCLUT165,DMA2D background CLUT" hexmask.long.byte 0x694 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x694 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x694 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x694 0.--7. 1. "BLUE,Blue" line.long 0x698 "DMA2D_BGCLUT166,DMA2D background CLUT" hexmask.long.byte 0x698 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x698 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x698 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x698 0.--7. 1. "BLUE,Blue" line.long 0x69C "DMA2D_BGCLUT167,DMA2D background CLUT" hexmask.long.byte 0x69C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x69C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x69C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x69C 0.--7. 1. "BLUE,Blue" line.long 0x6A0 "DMA2D_BGCLUT168,DMA2D background CLUT" hexmask.long.byte 0x6A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6A0 0.--7. 1. "BLUE,Blue" line.long 0x6A4 "DMA2D_BGCLUT169,DMA2D background CLUT" hexmask.long.byte 0x6A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6A4 0.--7. 1. "BLUE,Blue" line.long 0x6A8 "DMA2D_BGCLUT170,DMA2D background CLUT" hexmask.long.byte 0x6A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6A8 0.--7. 1. "BLUE,Blue" line.long 0x6AC "DMA2D_BGCLUT171,DMA2D background CLUT" hexmask.long.byte 0x6AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6AC 0.--7. 1. "BLUE,Blue" line.long 0x6B0 "DMA2D_BGCLUT172,DMA2D background CLUT" hexmask.long.byte 0x6B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6B0 0.--7. 1. "BLUE,Blue" line.long 0x6B4 "DMA2D_BGCLUT173,DMA2D background CLUT" hexmask.long.byte 0x6B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6B4 0.--7. 1. "BLUE,Blue" line.long 0x6B8 "DMA2D_BGCLUT174,DMA2D background CLUT" hexmask.long.byte 0x6B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6B8 0.--7. 1. "BLUE,Blue" line.long 0x6BC "DMA2D_BGCLUT175,DMA2D background CLUT" hexmask.long.byte 0x6BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6BC 0.--7. 1. "BLUE,Blue" line.long 0x6C0 "DMA2D_BGCLUT176,DMA2D background CLUT" hexmask.long.byte 0x6C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6C0 0.--7. 1. "BLUE,Blue" line.long 0x6C4 "DMA2D_BGCLUT177,DMA2D background CLUT" hexmask.long.byte 0x6C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6C4 0.--7. 1. "BLUE,Blue" line.long 0x6C8 "DMA2D_BGCLUT178,DMA2D background CLUT" hexmask.long.byte 0x6C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6C8 0.--7. 1. "BLUE,Blue" line.long 0x6CC "DMA2D_BGCLUT179,DMA2D background CLUT" hexmask.long.byte 0x6CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6CC 0.--7. 1. "BLUE,Blue" line.long 0x6D0 "DMA2D_BGCLUT180,DMA2D background CLUT" hexmask.long.byte 0x6D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6D0 0.--7. 1. "BLUE,Blue" line.long 0x6D4 "DMA2D_BGCLUT181,DMA2D background CLUT" hexmask.long.byte 0x6D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6D4 0.--7. 1. "BLUE,Blue" line.long 0x6D8 "DMA2D_BGCLUT182,DMA2D background CLUT" hexmask.long.byte 0x6D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6D8 0.--7. 1. "BLUE,Blue" line.long 0x6DC "DMA2D_BGCLUT183,DMA2D background CLUT" hexmask.long.byte 0x6DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6DC 0.--7. 1. "BLUE,Blue" line.long 0x6E0 "DMA2D_BGCLUT184,DMA2D background CLUT" hexmask.long.byte 0x6E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6E0 0.--7. 1. "BLUE,Blue" line.long 0x6E4 "DMA2D_BGCLUT185,DMA2D background CLUT" hexmask.long.byte 0x6E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6E4 0.--7. 1. "BLUE,Blue" line.long 0x6E8 "DMA2D_BGCLUT186,DMA2D background CLUT" hexmask.long.byte 0x6E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6E8 0.--7. 1. "BLUE,Blue" line.long 0x6EC "DMA2D_BGCLUT187,DMA2D background CLUT" hexmask.long.byte 0x6EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6EC 0.--7. 1. "BLUE,Blue" line.long 0x6F0 "DMA2D_BGCLUT188,DMA2D background CLUT" hexmask.long.byte 0x6F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6F0 0.--7. 1. "BLUE,Blue" line.long 0x6F4 "DMA2D_BGCLUT189,DMA2D background CLUT" hexmask.long.byte 0x6F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6F4 0.--7. 1. "BLUE,Blue" line.long 0x6F8 "DMA2D_BGCLUT190,DMA2D background CLUT" hexmask.long.byte 0x6F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6F8 0.--7. 1. "BLUE,Blue" line.long 0x6FC "DMA2D_BGCLUT191,DMA2D background CLUT" hexmask.long.byte 0x6FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6FC 0.--7. 1. "BLUE,Blue" line.long 0x700 "DMA2D_BGCLUT192,DMA2D background CLUT" hexmask.long.byte 0x700 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x700 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x700 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x700 0.--7. 1. "BLUE,Blue" line.long 0x704 "DMA2D_BGCLUT193,DMA2D background CLUT" hexmask.long.byte 0x704 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x704 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x704 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x704 0.--7. 1. "BLUE,Blue" line.long 0x708 "DMA2D_BGCLUT194,DMA2D background CLUT" hexmask.long.byte 0x708 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x708 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x708 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x708 0.--7. 1. "BLUE,Blue" line.long 0x70C "DMA2D_BGCLUT195,DMA2D background CLUT" hexmask.long.byte 0x70C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x70C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x70C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x70C 0.--7. 1. "BLUE,Blue" line.long 0x710 "DMA2D_BGCLUT196,DMA2D background CLUT" hexmask.long.byte 0x710 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x710 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x710 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x710 0.--7. 1. "BLUE,Blue" line.long 0x714 "DMA2D_BGCLUT197,DMA2D background CLUT" hexmask.long.byte 0x714 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x714 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x714 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x714 0.--7. 1. "BLUE,Blue" line.long 0x718 "DMA2D_BGCLUT198,DMA2D background CLUT" hexmask.long.byte 0x718 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x718 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x718 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x718 0.--7. 1. "BLUE,Blue" line.long 0x71C "DMA2D_BGCLUT199,DMA2D background CLUT" hexmask.long.byte 0x71C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x71C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x71C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x71C 0.--7. 1. "BLUE,Blue" line.long 0x720 "DMA2D_BGCLUT200,DMA2D background CLUT" hexmask.long.byte 0x720 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x720 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x720 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x720 0.--7. 1. "BLUE,Blue" line.long 0x724 "DMA2D_BGCLUT201,DMA2D background CLUT" hexmask.long.byte 0x724 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x724 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x724 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x724 0.--7. 1. "BLUE,Blue" line.long 0x728 "DMA2D_BGCLUT202,DMA2D background CLUT" hexmask.long.byte 0x728 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x728 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x728 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x728 0.--7. 1. "BLUE,Blue" line.long 0x72C "DMA2D_BGCLUT203,DMA2D background CLUT" hexmask.long.byte 0x72C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x72C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x72C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x72C 0.--7. 1. "BLUE,Blue" line.long 0x730 "DMA2D_BGCLUT204,DMA2D background CLUT" hexmask.long.byte 0x730 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x730 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x730 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x730 0.--7. 1. "BLUE,Blue" line.long 0x734 "DMA2D_BGCLUT205,DMA2D background CLUT" hexmask.long.byte 0x734 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x734 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x734 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x734 0.--7. 1. "BLUE,Blue" line.long 0x738 "DMA2D_BGCLUT206,DMA2D background CLUT" hexmask.long.byte 0x738 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x738 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x738 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x738 0.--7. 1. "BLUE,Blue" line.long 0x73C "DMA2D_BGCLUT207,DMA2D background CLUT" hexmask.long.byte 0x73C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x73C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x73C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x73C 0.--7. 1. "BLUE,Blue" line.long 0x740 "DMA2D_BGCLUT208,DMA2D background CLUT" hexmask.long.byte 0x740 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x740 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x740 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x740 0.--7. 1. "BLUE,Blue" line.long 0x744 "DMA2D_BGCLUT209,DMA2D background CLUT" hexmask.long.byte 0x744 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x744 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x744 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x744 0.--7. 1. "BLUE,Blue" line.long 0x748 "DMA2D_BGCLUT210,DMA2D background CLUT" hexmask.long.byte 0x748 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x748 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x748 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x748 0.--7. 1. "BLUE,Blue" line.long 0x74C "DMA2D_BGCLUT211,DMA2D background CLUT" hexmask.long.byte 0x74C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x74C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x74C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x74C 0.--7. 1. "BLUE,Blue" line.long 0x750 "DMA2D_BGCLUT212,DMA2D background CLUT" hexmask.long.byte 0x750 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x750 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x750 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x750 0.--7. 1. "BLUE,Blue" line.long 0x754 "DMA2D_BGCLUT213,DMA2D background CLUT" hexmask.long.byte 0x754 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x754 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x754 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x754 0.--7. 1. "BLUE,Blue" line.long 0x758 "DMA2D_BGCLUT214,DMA2D background CLUT" hexmask.long.byte 0x758 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x758 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x758 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x758 0.--7. 1. "BLUE,Blue" line.long 0x75C "DMA2D_BGCLUT215,DMA2D background CLUT" hexmask.long.byte 0x75C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x75C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x75C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x75C 0.--7. 1. "BLUE,Blue" line.long 0x760 "DMA2D_BGCLUT216,DMA2D background CLUT" hexmask.long.byte 0x760 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x760 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x760 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x760 0.--7. 1. "BLUE,Blue" line.long 0x764 "DMA2D_BGCLUT217,DMA2D background CLUT" hexmask.long.byte 0x764 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x764 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x764 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x764 0.--7. 1. "BLUE,Blue" line.long 0x768 "DMA2D_BGCLUT218,DMA2D background CLUT" hexmask.long.byte 0x768 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x768 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x768 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x768 0.--7. 1. "BLUE,Blue" line.long 0x76C "DMA2D_BGCLUT219,DMA2D background CLUT" hexmask.long.byte 0x76C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x76C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x76C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x76C 0.--7. 1. "BLUE,Blue" line.long 0x770 "DMA2D_BGCLUT220,DMA2D background CLUT" hexmask.long.byte 0x770 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x770 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x770 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x770 0.--7. 1. "BLUE,Blue" line.long 0x774 "DMA2D_BGCLUT221,DMA2D background CLUT" hexmask.long.byte 0x774 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x774 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x774 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x774 0.--7. 1. "BLUE,Blue" line.long 0x778 "DMA2D_BGCLUT222,DMA2D background CLUT" hexmask.long.byte 0x778 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x778 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x778 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x778 0.--7. 1. "BLUE,Blue" line.long 0x77C "DMA2D_BGCLUT223,DMA2D background CLUT" hexmask.long.byte 0x77C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x77C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x77C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x77C 0.--7. 1. "BLUE,Blue" line.long 0x780 "DMA2D_BGCLUT224,DMA2D background CLUT" hexmask.long.byte 0x780 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x780 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x780 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x780 0.--7. 1. "BLUE,Blue" line.long 0x784 "DMA2D_BGCLUT225,DMA2D background CLUT" hexmask.long.byte 0x784 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x784 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x784 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x784 0.--7. 1. "BLUE,Blue" line.long 0x788 "DMA2D_BGCLUT226,DMA2D background CLUT" hexmask.long.byte 0x788 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x788 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x788 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x788 0.--7. 1. "BLUE,Blue" line.long 0x78C "DMA2D_BGCLUT227,DMA2D background CLUT" hexmask.long.byte 0x78C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x78C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x78C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x78C 0.--7. 1. "BLUE,Blue" line.long 0x790 "DMA2D_BGCLUT228,DMA2D background CLUT" hexmask.long.byte 0x790 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x790 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x790 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x790 0.--7. 1. "BLUE,Blue" line.long 0x794 "DMA2D_BGCLUT229,DMA2D background CLUT" hexmask.long.byte 0x794 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x794 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x794 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x794 0.--7. 1. "BLUE,Blue" line.long 0x798 "DMA2D_BGCLUT230,DMA2D background CLUT" hexmask.long.byte 0x798 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x798 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x798 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x798 0.--7. 1. "BLUE,Blue" line.long 0x79C "DMA2D_BGCLUT231,DMA2D background CLUT" hexmask.long.byte 0x79C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x79C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x79C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x79C 0.--7. 1. "BLUE,Blue" line.long 0x7A0 "DMA2D_BGCLUT232,DMA2D background CLUT" hexmask.long.byte 0x7A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7A0 0.--7. 1. "BLUE,Blue" line.long 0x7A4 "DMA2D_BGCLUT233,DMA2D background CLUT" hexmask.long.byte 0x7A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7A4 0.--7. 1. "BLUE,Blue" line.long 0x7A8 "DMA2D_BGCLUT234,DMA2D background CLUT" hexmask.long.byte 0x7A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7A8 0.--7. 1. "BLUE,Blue" line.long 0x7AC "DMA2D_BGCLUT235,DMA2D background CLUT" hexmask.long.byte 0x7AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7AC 0.--7. 1. "BLUE,Blue" line.long 0x7B0 "DMA2D_BGCLUT236,DMA2D background CLUT" hexmask.long.byte 0x7B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7B0 0.--7. 1. "BLUE,Blue" line.long 0x7B4 "DMA2D_BGCLUT237,DMA2D background CLUT" hexmask.long.byte 0x7B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7B4 0.--7. 1. "BLUE,Blue" line.long 0x7B8 "DMA2D_BGCLUT238,DMA2D background CLUT" hexmask.long.byte 0x7B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7B8 0.--7. 1. "BLUE,Blue" line.long 0x7BC "DMA2D_BGCLUT239,DMA2D background CLUT" hexmask.long.byte 0x7BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7BC 0.--7. 1. "BLUE,Blue" line.long 0x7C0 "DMA2D_BGCLUT240,DMA2D background CLUT" hexmask.long.byte 0x7C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7C0 0.--7. 1. "BLUE,Blue" line.long 0x7C4 "DMA2D_BGCLUT241,DMA2D background CLUT" hexmask.long.byte 0x7C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7C4 0.--7. 1. "BLUE,Blue" line.long 0x7C8 "DMA2D_BGCLUT242,DMA2D background CLUT" hexmask.long.byte 0x7C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7C8 0.--7. 1. "BLUE,Blue" line.long 0x7CC "DMA2D_BGCLUT243,DMA2D background CLUT" hexmask.long.byte 0x7CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7CC 0.--7. 1. "BLUE,Blue" line.long 0x7D0 "DMA2D_BGCLUT244,DMA2D background CLUT" hexmask.long.byte 0x7D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7D0 0.--7. 1. "BLUE,Blue" line.long 0x7D4 "DMA2D_BGCLUT245,DMA2D background CLUT" hexmask.long.byte 0x7D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7D4 0.--7. 1. "BLUE,Blue" line.long 0x7D8 "DMA2D_BGCLUT246,DMA2D background CLUT" hexmask.long.byte 0x7D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7D8 0.--7. 1. "BLUE,Blue" line.long 0x7DC "DMA2D_BGCLUT247,DMA2D background CLUT" hexmask.long.byte 0x7DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7DC 0.--7. 1. "BLUE,Blue" line.long 0x7E0 "DMA2D_BGCLUT248,DMA2D background CLUT" hexmask.long.byte 0x7E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7E0 0.--7. 1. "BLUE,Blue" line.long 0x7E4 "DMA2D_BGCLUT249,DMA2D background CLUT" hexmask.long.byte 0x7E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7E4 0.--7. 1. "BLUE,Blue" line.long 0x7E8 "DMA2D_BGCLUT250,DMA2D background CLUT" hexmask.long.byte 0x7E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7E8 0.--7. 1. "BLUE,Blue" line.long 0x7EC "DMA2D_BGCLUT251,DMA2D background CLUT" hexmask.long.byte 0x7EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7EC 0.--7. 1. "BLUE,Blue" line.long 0x7F0 "DMA2D_BGCLUT252,DMA2D background CLUT" hexmask.long.byte 0x7F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7F0 0.--7. 1. "BLUE,Blue" line.long 0x7F4 "DMA2D_BGCLUT253,DMA2D background CLUT" hexmask.long.byte 0x7F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7F4 0.--7. 1. "BLUE,Blue" line.long 0x7F8 "DMA2D_BGCLUT254,DMA2D background CLUT" hexmask.long.byte 0x7F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7F8 0.--7. 1. "BLUE,Blue" line.long 0x7FC "DMA2D_BGCLUT255,DMA2D background CLUT" hexmask.long.byte 0x7FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7FC 0.--7. 1. "BLUE,Blue" tree.end tree "DMA2D_S" base ad:0x58021000 group.long 0x0++0x3 line.long 0x0 "DMA2D_CR,DMA2D control register" bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0: Memory-to-memory (FG fetch only),1: Memory-to-memory with PFC (FG fetch only with FG..,2: Memory-to-memory with blending (FG and BG fetch..,3: Register-to-memory (no FG nor BG only output..,4: Memory-to-memory with blending and fixed color..,5: Memory-to-memory with blending and fixed color..,?,?" bitfld.long 0x0 13. "CEIE,Configuration error (CE) interrupt enable" "0: CE interrupt disabled,1: CE interrupt enabled" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete (CTC) interrupt enable" "0: CTC interrupt disabled,1: CTC interrupt enabled" bitfld.long 0x0 11. "CAEIE,CLUT access error (CAE) interrupt enable" "0: CAE interrupt disabled,1: CAE interrupt enabled" newline bitfld.long 0x0 10. "TWIE,Transfer watermark (TW) interrupt enable" "0: TW interrupt disabled,1: TW interrupt enabled" bitfld.long 0x0 9. "TCIE,Transfer complete (TC) interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" newline bitfld.long 0x0 8. "TEIE,Transfer error (TE) interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x0 6. "LOM,Line offset mode" "0: Line offsets expressed in pixels,1: Line offsets expressed in bytes" newline bitfld.long 0x0 2. "ABORT,Abort" "0: No transfer abort requested,1: Transfer abort requested" bitfld.long 0x0 1. "SUSP,Suspend" "0: Transfer not suspended,1: Transfer suspended" newline bitfld.long 0x0 0. "START,Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DMA2D_ISR,DMA2D interrupt status register" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1" group.long 0x8++0x33 line.long 0x0 "DMA2D_IFCR,DMA2D interrupt flag clear register" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear transfer error interrupt flag" "0,1" line.long 0x4 "DMA2D_FGMAR,DMA2D foreground memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address address of the data used for the foreground image" line.long 0x8 "DMA2D_FGOR,DMA2D foreground offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "DMA2D_BGMAR,DMA2D background memory address register" hexmask.long 0xC 0.--31. 1. "MA,Memory address address of the data used for the background image" line.long 0x10 "DMA2D_BGOR,DMA2D background offset register" hexmask.long.word 0x10 0.--15. 1. "LO,Line offset" line.long 0x14 "DMA2D_FGPFCCR,DMA2D foreground PFC control register" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x14 21. "RBS,Red/Blue swap" "0: Regular mode (RGB or ARGB),1: Swap mode (BGR or ABGR)" newline bitfld.long 0x14 20. "AI,Alpha inverted" "0: Regular alpha,1: Inverted alpha" bitfld.long 0x14 18.--19. "CSS,Chroma subsampling" "0: 4:4:4 (no chroma subsampling),1: 4:2:2,2: 4:2:0,?" newline bitfld.long 0x14 16.--17. "AM,Alpha mode" "0: No modification of the foreground image alpha..,1: Replace original foreground image alpha channel..,2: Replace original foreground image alpha channel..,?" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size" newline bitfld.long 0x14 5. "START,Start" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode" "0: ARGB8888,1: RGB888" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode" line.long 0x18 "DMA2D_FGCOLR,DMA2D foreground color register" hexmask.long.byte 0x18 16.--23. 1. "RED,Red value for the A4 or A8 mode of the foreground image" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green value for the A4 or A8 mode of the foreground image" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue value for the A4 or A8 mode of the foreground image" line.long 0x1C "DMA2D_BGPFCCR,DMA2D background PFC control register" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value" bitfld.long 0x1C 21. "RBS,Red/Blue swap" "0: Regular mode (RGB or ARGB),1: Swap mode (BGR or ABGR)" newline bitfld.long 0x1C 20. "AI,Alpha Inverted" "0: Regular alpha,1: Inverted alpha" bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0: No modification of the foreground image alpha..,1: Replace original background image alpha channel..,2: Replace original background image alpha channel..,?" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size" bitfld.long 0x1C 5. "START,Start" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT color mode" "0: ARGB8888,1: RGB888" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode" line.long 0x20 "DMA2D_BGCOLR,DMA2D background color register" hexmask.long.byte 0x20 16.--23. 1. "RED,Red value for the A4 or A8 mode of the background" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green value for the A4 or A8 mode of the background" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue value for the A4 or A8 mode of the background" line.long 0x24 "DMA2D_FGCMAR,DMA2D foreground CLUT memory address register" hexmask.long 0x24 0.--31. 1. "MA,Memory address" line.long 0x28 "DMA2D_BGCMAR,DMA2D background CLUT memory address register" hexmask.long 0x28 0.--31. 1. "MA,Memory address" line.long 0x2C "DMA2D_OPFCCR,DMA2D output PFC control register" bitfld.long 0x2C 21. "RBS,Red/Blue swap" "0: Regular mode (RGB or ARGB),1: Swap mode (BGR or ABGR)" bitfld.long 0x2C 20. "AI,Alpha Inverted" "0: Regular alpha,1: Inverted alpha" newline bitfld.long 0x2C 8. "SB,Swap bytes" "0: Bytes in regular order in the output FIFO,1: Bytes swapped two by two in the output FIFO" bitfld.long 0x2C 0.--2. "CM,Color mode" "0: ARGB8888,1: RGB888,2: RGB565,3: ARGB1555,4: ARGB4444,?,?,?" line.long 0x30 "DMA2D_OCOLR_RGB888,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha channel value of the output color in ARGB8888 mode (otherwise reserved)" hexmask.long.byte 0x30 16.--23. 1. "RED,Red value of the output image in ARGB8888 or RGB888 mode" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green value of the output image in ARGB8888 or RGB888" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue value of the output image in ARGB8888 or RGB888" group.long 0x38++0x3 line.long 0x0 "DMA2D_OCOLR_RGB565,DMA2D output color register" hexmask.long.byte 0x0 11.--15. 1. "RED,Red value of the output image in RGB565 mode" hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value of the output image in RGB565 mode" newline hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value of the output image in RGB565 mode" group.long 0x38++0x3 line.long 0x0 "DMA2D_OCOLR_ARGB1555,DMA2D output color register" bitfld.long 0x0 15. "A,Alpha channel value of the output color in ARGB1555 mode" "0,1" hexmask.long.byte 0x0 10.--14. 1. "RED,Red value of the output image in ARGB1555 mode" newline hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value of the output image in ARGB1555 mode" hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value of the output image in ARGB1555 mode" group.long 0x38++0x17 line.long 0x0 "DMA2D_OCOLR_ARGB4444,DMA2D output color register" hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel of the output color value in ARGB4444" hexmask.long.byte 0x0 8.--11. 1. "RED,Red value of the output image in ARGB4444 mode" newline hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value of the output image in ARGB4444 mode" hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value of the output image in ARGB4444 mode" line.long 0x4 "DMA2D_OMAR,DMA2D output memory address register" hexmask.long 0x4 0.--31. 1. "MA,Memory address" line.long 0x8 "DMA2D_OOR,DMA2D output offset register" hexmask.long.word 0x8 0.--15. 1. "LO,Line offset" line.long 0xC "DMA2D_NLR,DMA2D number of line register" hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines per lines of the area to be transferred" hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines of the area to be transferred." line.long 0x10 "DMA2D_LWR,DMA2D line watermark register" hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark for interrupt generation" line.long 0x14 "DMA2D_AMTCR,DMA2D AXI master timer configuration register" hexmask.long.byte 0x14 8.--15. 1. "DT,Dead time" bitfld.long 0x14 0. "EN,Dead-time functionality enable" "0,1" group.long 0x400++0x7FF line.long 0x0 "DMA2D_FGCLUT0,DMA2D foreground CLUT" hexmask.long.byte 0x0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x0 0.--7. 1. "BLUE,Blue" line.long 0x4 "DMA2D_FGCLUT1,DMA2D foreground CLUT" hexmask.long.byte 0x4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4 0.--7. 1. "BLUE,Blue" line.long 0x8 "DMA2D_FGCLUT2,DMA2D foreground CLUT" hexmask.long.byte 0x8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x8 0.--7. 1. "BLUE,Blue" line.long 0xC "DMA2D_FGCLUT3,DMA2D foreground CLUT" hexmask.long.byte 0xC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xC 0.--7. 1. "BLUE,Blue" line.long 0x10 "DMA2D_FGCLUT4,DMA2D foreground CLUT" hexmask.long.byte 0x10 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x10 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x10 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x10 0.--7. 1. "BLUE,Blue" line.long 0x14 "DMA2D_FGCLUT5,DMA2D foreground CLUT" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x14 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x14 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x14 0.--7. 1. "BLUE,Blue" line.long 0x18 "DMA2D_FGCLUT6,DMA2D foreground CLUT" hexmask.long.byte 0x18 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x18 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue" line.long 0x1C "DMA2D_FGCLUT7,DMA2D foreground CLUT" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1C 0.--7. 1. "BLUE,Blue" line.long 0x20 "DMA2D_FGCLUT8,DMA2D foreground CLUT" hexmask.long.byte 0x20 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x20 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue" line.long 0x24 "DMA2D_FGCLUT9,DMA2D foreground CLUT" hexmask.long.byte 0x24 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x24 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x24 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x24 0.--7. 1. "BLUE,Blue" line.long 0x28 "DMA2D_FGCLUT10,DMA2D foreground CLUT" hexmask.long.byte 0x28 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x28 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x28 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x28 0.--7. 1. "BLUE,Blue" line.long 0x2C "DMA2D_FGCLUT11,DMA2D foreground CLUT" hexmask.long.byte 0x2C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2C 0.--7. 1. "BLUE,Blue" line.long 0x30 "DMA2D_FGCLUT12,DMA2D foreground CLUT" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x30 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue" line.long 0x34 "DMA2D_FGCLUT13,DMA2D foreground CLUT" hexmask.long.byte 0x34 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x34 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x34 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x34 0.--7. 1. "BLUE,Blue" line.long 0x38 "DMA2D_FGCLUT14,DMA2D foreground CLUT" hexmask.long.byte 0x38 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x38 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x38 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x38 0.--7. 1. "BLUE,Blue" line.long 0x3C "DMA2D_FGCLUT15,DMA2D foreground CLUT" hexmask.long.byte 0x3C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3C 0.--7. 1. "BLUE,Blue" line.long 0x40 "DMA2D_FGCLUT16,DMA2D foreground CLUT" hexmask.long.byte 0x40 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x40 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x40 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x40 0.--7. 1. "BLUE,Blue" line.long 0x44 "DMA2D_FGCLUT17,DMA2D foreground CLUT" hexmask.long.byte 0x44 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x44 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x44 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x44 0.--7. 1. "BLUE,Blue" line.long 0x48 "DMA2D_FGCLUT18,DMA2D foreground CLUT" hexmask.long.byte 0x48 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x48 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x48 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x48 0.--7. 1. "BLUE,Blue" line.long 0x4C "DMA2D_FGCLUT19,DMA2D foreground CLUT" hexmask.long.byte 0x4C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4C 0.--7. 1. "BLUE,Blue" line.long 0x50 "DMA2D_FGCLUT20,DMA2D foreground CLUT" hexmask.long.byte 0x50 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x50 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x50 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x50 0.--7. 1. "BLUE,Blue" line.long 0x54 "DMA2D_FGCLUT21,DMA2D foreground CLUT" hexmask.long.byte 0x54 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x54 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x54 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x54 0.--7. 1. "BLUE,Blue" line.long 0x58 "DMA2D_FGCLUT22,DMA2D foreground CLUT" hexmask.long.byte 0x58 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x58 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x58 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x58 0.--7. 1. "BLUE,Blue" line.long 0x5C "DMA2D_FGCLUT23,DMA2D foreground CLUT" hexmask.long.byte 0x5C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5C 0.--7. 1. "BLUE,Blue" line.long 0x60 "DMA2D_FGCLUT24,DMA2D foreground CLUT" hexmask.long.byte 0x60 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x60 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x60 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x60 0.--7. 1. "BLUE,Blue" line.long 0x64 "DMA2D_FGCLUT25,DMA2D foreground CLUT" hexmask.long.byte 0x64 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x64 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x64 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x64 0.--7. 1. "BLUE,Blue" line.long 0x68 "DMA2D_FGCLUT26,DMA2D foreground CLUT" hexmask.long.byte 0x68 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x68 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x68 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x68 0.--7. 1. "BLUE,Blue" line.long 0x6C "DMA2D_FGCLUT27,DMA2D foreground CLUT" hexmask.long.byte 0x6C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6C 0.--7. 1. "BLUE,Blue" line.long 0x70 "DMA2D_FGCLUT28,DMA2D foreground CLUT" hexmask.long.byte 0x70 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x70 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x70 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x70 0.--7. 1. "BLUE,Blue" line.long 0x74 "DMA2D_FGCLUT29,DMA2D foreground CLUT" hexmask.long.byte 0x74 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x74 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x74 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x74 0.--7. 1. "BLUE,Blue" line.long 0x78 "DMA2D_FGCLUT30,DMA2D foreground CLUT" hexmask.long.byte 0x78 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x78 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x78 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x78 0.--7. 1. "BLUE,Blue" line.long 0x7C "DMA2D_FGCLUT31,DMA2D foreground CLUT" hexmask.long.byte 0x7C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7C 0.--7. 1. "BLUE,Blue" line.long 0x80 "DMA2D_FGCLUT32,DMA2D foreground CLUT" hexmask.long.byte 0x80 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x80 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x80 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x80 0.--7. 1. "BLUE,Blue" line.long 0x84 "DMA2D_FGCLUT33,DMA2D foreground CLUT" hexmask.long.byte 0x84 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x84 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x84 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x84 0.--7. 1. "BLUE,Blue" line.long 0x88 "DMA2D_FGCLUT34,DMA2D foreground CLUT" hexmask.long.byte 0x88 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x88 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x88 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x88 0.--7. 1. "BLUE,Blue" line.long 0x8C "DMA2D_FGCLUT35,DMA2D foreground CLUT" hexmask.long.byte 0x8C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x8C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x8C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x8C 0.--7. 1. "BLUE,Blue" line.long 0x90 "DMA2D_FGCLUT36,DMA2D foreground CLUT" hexmask.long.byte 0x90 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x90 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x90 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x90 0.--7. 1. "BLUE,Blue" line.long 0x94 "DMA2D_FGCLUT37,DMA2D foreground CLUT" hexmask.long.byte 0x94 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x94 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x94 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x94 0.--7. 1. "BLUE,Blue" line.long 0x98 "DMA2D_FGCLUT38,DMA2D foreground CLUT" hexmask.long.byte 0x98 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x98 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x98 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x98 0.--7. 1. "BLUE,Blue" line.long 0x9C "DMA2D_FGCLUT39,DMA2D foreground CLUT" hexmask.long.byte 0x9C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x9C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x9C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x9C 0.--7. 1. "BLUE,Blue" line.long 0xA0 "DMA2D_FGCLUT40,DMA2D foreground CLUT" hexmask.long.byte 0xA0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xA0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xA0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xA0 0.--7. 1. "BLUE,Blue" line.long 0xA4 "DMA2D_FGCLUT41,DMA2D foreground CLUT" hexmask.long.byte 0xA4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xA4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xA4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xA4 0.--7. 1. "BLUE,Blue" line.long 0xA8 "DMA2D_FGCLUT42,DMA2D foreground CLUT" hexmask.long.byte 0xA8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xA8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xA8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xA8 0.--7. 1. "BLUE,Blue" line.long 0xAC "DMA2D_FGCLUT43,DMA2D foreground CLUT" hexmask.long.byte 0xAC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xAC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xAC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xAC 0.--7. 1. "BLUE,Blue" line.long 0xB0 "DMA2D_FGCLUT44,DMA2D foreground CLUT" hexmask.long.byte 0xB0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xB0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xB0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xB0 0.--7. 1. "BLUE,Blue" line.long 0xB4 "DMA2D_FGCLUT45,DMA2D foreground CLUT" hexmask.long.byte 0xB4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xB4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xB4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xB4 0.--7. 1. "BLUE,Blue" line.long 0xB8 "DMA2D_FGCLUT46,DMA2D foreground CLUT" hexmask.long.byte 0xB8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xB8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xB8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xB8 0.--7. 1. "BLUE,Blue" line.long 0xBC "DMA2D_FGCLUT47,DMA2D foreground CLUT" hexmask.long.byte 0xBC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xBC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xBC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xBC 0.--7. 1. "BLUE,Blue" line.long 0xC0 "DMA2D_FGCLUT48,DMA2D foreground CLUT" hexmask.long.byte 0xC0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xC0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xC0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xC0 0.--7. 1. "BLUE,Blue" line.long 0xC4 "DMA2D_FGCLUT49,DMA2D foreground CLUT" hexmask.long.byte 0xC4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xC4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xC4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xC4 0.--7. 1. "BLUE,Blue" line.long 0xC8 "DMA2D_FGCLUT50,DMA2D foreground CLUT" hexmask.long.byte 0xC8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xC8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xC8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xC8 0.--7. 1. "BLUE,Blue" line.long 0xCC "DMA2D_FGCLUT51,DMA2D foreground CLUT" hexmask.long.byte 0xCC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xCC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xCC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xCC 0.--7. 1. "BLUE,Blue" line.long 0xD0 "DMA2D_FGCLUT52,DMA2D foreground CLUT" hexmask.long.byte 0xD0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xD0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xD0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xD0 0.--7. 1. "BLUE,Blue" line.long 0xD4 "DMA2D_FGCLUT53,DMA2D foreground CLUT" hexmask.long.byte 0xD4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xD4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xD4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xD4 0.--7. 1. "BLUE,Blue" line.long 0xD8 "DMA2D_FGCLUT54,DMA2D foreground CLUT" hexmask.long.byte 0xD8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xD8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xD8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xD8 0.--7. 1. "BLUE,Blue" line.long 0xDC "DMA2D_FGCLUT55,DMA2D foreground CLUT" hexmask.long.byte 0xDC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xDC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xDC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xDC 0.--7. 1. "BLUE,Blue" line.long 0xE0 "DMA2D_FGCLUT56,DMA2D foreground CLUT" hexmask.long.byte 0xE0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xE0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xE0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xE0 0.--7. 1. "BLUE,Blue" line.long 0xE4 "DMA2D_FGCLUT57,DMA2D foreground CLUT" hexmask.long.byte 0xE4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xE4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xE4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xE4 0.--7. 1. "BLUE,Blue" line.long 0xE8 "DMA2D_FGCLUT58,DMA2D foreground CLUT" hexmask.long.byte 0xE8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xE8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xE8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xE8 0.--7. 1. "BLUE,Blue" line.long 0xEC "DMA2D_FGCLUT59,DMA2D foreground CLUT" hexmask.long.byte 0xEC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xEC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xEC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xEC 0.--7. 1. "BLUE,Blue" line.long 0xF0 "DMA2D_FGCLUT60,DMA2D foreground CLUT" hexmask.long.byte 0xF0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xF0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xF0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xF0 0.--7. 1. "BLUE,Blue" line.long 0xF4 "DMA2D_FGCLUT61,DMA2D foreground CLUT" hexmask.long.byte 0xF4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xF4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xF4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xF4 0.--7. 1. "BLUE,Blue" line.long 0xF8 "DMA2D_FGCLUT62,DMA2D foreground CLUT" hexmask.long.byte 0xF8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xF8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xF8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xF8 0.--7. 1. "BLUE,Blue" line.long 0xFC "DMA2D_FGCLUT63,DMA2D foreground CLUT" hexmask.long.byte 0xFC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0xFC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0xFC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0xFC 0.--7. 1. "BLUE,Blue" line.long 0x100 "DMA2D_FGCLUT64,DMA2D foreground CLUT" hexmask.long.byte 0x100 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x100 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x100 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x100 0.--7. 1. "BLUE,Blue" line.long 0x104 "DMA2D_FGCLUT65,DMA2D foreground CLUT" hexmask.long.byte 0x104 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x104 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x104 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x104 0.--7. 1. "BLUE,Blue" line.long 0x108 "DMA2D_FGCLUT66,DMA2D foreground CLUT" hexmask.long.byte 0x108 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x108 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x108 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x108 0.--7. 1. "BLUE,Blue" line.long 0x10C "DMA2D_FGCLUT67,DMA2D foreground CLUT" hexmask.long.byte 0x10C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x10C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x10C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x10C 0.--7. 1. "BLUE,Blue" line.long 0x110 "DMA2D_FGCLUT68,DMA2D foreground CLUT" hexmask.long.byte 0x110 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x110 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x110 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x110 0.--7. 1. "BLUE,Blue" line.long 0x114 "DMA2D_FGCLUT69,DMA2D foreground CLUT" hexmask.long.byte 0x114 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x114 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x114 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x114 0.--7. 1. "BLUE,Blue" line.long 0x118 "DMA2D_FGCLUT70,DMA2D foreground CLUT" hexmask.long.byte 0x118 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x118 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x118 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x118 0.--7. 1. "BLUE,Blue" line.long 0x11C "DMA2D_FGCLUT71,DMA2D foreground CLUT" hexmask.long.byte 0x11C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x11C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x11C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x11C 0.--7. 1. "BLUE,Blue" line.long 0x120 "DMA2D_FGCLUT72,DMA2D foreground CLUT" hexmask.long.byte 0x120 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x120 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x120 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x120 0.--7. 1. "BLUE,Blue" line.long 0x124 "DMA2D_FGCLUT73,DMA2D foreground CLUT" hexmask.long.byte 0x124 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x124 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x124 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x124 0.--7. 1. "BLUE,Blue" line.long 0x128 "DMA2D_FGCLUT74,DMA2D foreground CLUT" hexmask.long.byte 0x128 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x128 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x128 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x128 0.--7. 1. "BLUE,Blue" line.long 0x12C "DMA2D_FGCLUT75,DMA2D foreground CLUT" hexmask.long.byte 0x12C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x12C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x12C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x12C 0.--7. 1. "BLUE,Blue" line.long 0x130 "DMA2D_FGCLUT76,DMA2D foreground CLUT" hexmask.long.byte 0x130 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x130 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x130 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x130 0.--7. 1. "BLUE,Blue" line.long 0x134 "DMA2D_FGCLUT77,DMA2D foreground CLUT" hexmask.long.byte 0x134 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x134 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x134 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x134 0.--7. 1. "BLUE,Blue" line.long 0x138 "DMA2D_FGCLUT78,DMA2D foreground CLUT" hexmask.long.byte 0x138 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x138 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x138 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x138 0.--7. 1. "BLUE,Blue" line.long 0x13C "DMA2D_FGCLUT79,DMA2D foreground CLUT" hexmask.long.byte 0x13C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x13C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x13C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x13C 0.--7. 1. "BLUE,Blue" line.long 0x140 "DMA2D_FGCLUT80,DMA2D foreground CLUT" hexmask.long.byte 0x140 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x140 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x140 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x140 0.--7. 1. "BLUE,Blue" line.long 0x144 "DMA2D_FGCLUT81,DMA2D foreground CLUT" hexmask.long.byte 0x144 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x144 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x144 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x144 0.--7. 1. "BLUE,Blue" line.long 0x148 "DMA2D_FGCLUT82,DMA2D foreground CLUT" hexmask.long.byte 0x148 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x148 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x148 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x148 0.--7. 1. "BLUE,Blue" line.long 0x14C "DMA2D_FGCLUT83,DMA2D foreground CLUT" hexmask.long.byte 0x14C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x14C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x14C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x14C 0.--7. 1. "BLUE,Blue" line.long 0x150 "DMA2D_FGCLUT84,DMA2D foreground CLUT" hexmask.long.byte 0x150 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x150 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x150 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x150 0.--7. 1. "BLUE,Blue" line.long 0x154 "DMA2D_FGCLUT85,DMA2D foreground CLUT" hexmask.long.byte 0x154 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x154 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x154 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x154 0.--7. 1. "BLUE,Blue" line.long 0x158 "DMA2D_FGCLUT86,DMA2D foreground CLUT" hexmask.long.byte 0x158 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x158 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x158 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x158 0.--7. 1. "BLUE,Blue" line.long 0x15C "DMA2D_FGCLUT87,DMA2D foreground CLUT" hexmask.long.byte 0x15C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x15C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x15C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x15C 0.--7. 1. "BLUE,Blue" line.long 0x160 "DMA2D_FGCLUT88,DMA2D foreground CLUT" hexmask.long.byte 0x160 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x160 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x160 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x160 0.--7. 1. "BLUE,Blue" line.long 0x164 "DMA2D_FGCLUT89,DMA2D foreground CLUT" hexmask.long.byte 0x164 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x164 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x164 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x164 0.--7. 1. "BLUE,Blue" line.long 0x168 "DMA2D_FGCLUT90,DMA2D foreground CLUT" hexmask.long.byte 0x168 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x168 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x168 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x168 0.--7. 1. "BLUE,Blue" line.long 0x16C "DMA2D_FGCLUT91,DMA2D foreground CLUT" hexmask.long.byte 0x16C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x16C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x16C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x16C 0.--7. 1. "BLUE,Blue" line.long 0x170 "DMA2D_FGCLUT92,DMA2D foreground CLUT" hexmask.long.byte 0x170 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x170 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x170 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x170 0.--7. 1. "BLUE,Blue" line.long 0x174 "DMA2D_FGCLUT93,DMA2D foreground CLUT" hexmask.long.byte 0x174 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x174 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x174 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x174 0.--7. 1. "BLUE,Blue" line.long 0x178 "DMA2D_FGCLUT94,DMA2D foreground CLUT" hexmask.long.byte 0x178 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x178 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x178 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x178 0.--7. 1. "BLUE,Blue" line.long 0x17C "DMA2D_FGCLUT95,DMA2D foreground CLUT" hexmask.long.byte 0x17C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x17C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x17C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x17C 0.--7. 1. "BLUE,Blue" line.long 0x180 "DMA2D_FGCLUT96,DMA2D foreground CLUT" hexmask.long.byte 0x180 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x180 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x180 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x180 0.--7. 1. "BLUE,Blue" line.long 0x184 "DMA2D_FGCLUT97,DMA2D foreground CLUT" hexmask.long.byte 0x184 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x184 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x184 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x184 0.--7. 1. "BLUE,Blue" line.long 0x188 "DMA2D_FGCLUT98,DMA2D foreground CLUT" hexmask.long.byte 0x188 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x188 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x188 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x188 0.--7. 1. "BLUE,Blue" line.long 0x18C "DMA2D_FGCLUT99,DMA2D foreground CLUT" hexmask.long.byte 0x18C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x18C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x18C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x18C 0.--7. 1. "BLUE,Blue" line.long 0x190 "DMA2D_FGCLUT100,DMA2D foreground CLUT" hexmask.long.byte 0x190 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x190 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x190 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x190 0.--7. 1. "BLUE,Blue" line.long 0x194 "DMA2D_FGCLUT101,DMA2D foreground CLUT" hexmask.long.byte 0x194 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x194 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x194 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x194 0.--7. 1. "BLUE,Blue" line.long 0x198 "DMA2D_FGCLUT102,DMA2D foreground CLUT" hexmask.long.byte 0x198 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x198 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x198 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x198 0.--7. 1. "BLUE,Blue" line.long 0x19C "DMA2D_FGCLUT103,DMA2D foreground CLUT" hexmask.long.byte 0x19C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x19C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x19C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x19C 0.--7. 1. "BLUE,Blue" line.long 0x1A0 "DMA2D_FGCLUT104,DMA2D foreground CLUT" hexmask.long.byte 0x1A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1A0 0.--7. 1. "BLUE,Blue" line.long 0x1A4 "DMA2D_FGCLUT105,DMA2D foreground CLUT" hexmask.long.byte 0x1A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1A4 0.--7. 1. "BLUE,Blue" line.long 0x1A8 "DMA2D_FGCLUT106,DMA2D foreground CLUT" hexmask.long.byte 0x1A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1A8 0.--7. 1. "BLUE,Blue" line.long 0x1AC "DMA2D_FGCLUT107,DMA2D foreground CLUT" hexmask.long.byte 0x1AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1AC 0.--7. 1. "BLUE,Blue" line.long 0x1B0 "DMA2D_FGCLUT108,DMA2D foreground CLUT" hexmask.long.byte 0x1B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1B0 0.--7. 1. "BLUE,Blue" line.long 0x1B4 "DMA2D_FGCLUT109,DMA2D foreground CLUT" hexmask.long.byte 0x1B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1B4 0.--7. 1. "BLUE,Blue" line.long 0x1B8 "DMA2D_FGCLUT110,DMA2D foreground CLUT" hexmask.long.byte 0x1B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1B8 0.--7. 1. "BLUE,Blue" line.long 0x1BC "DMA2D_FGCLUT111,DMA2D foreground CLUT" hexmask.long.byte 0x1BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1BC 0.--7. 1. "BLUE,Blue" line.long 0x1C0 "DMA2D_FGCLUT112,DMA2D foreground CLUT" hexmask.long.byte 0x1C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1C0 0.--7. 1. "BLUE,Blue" line.long 0x1C4 "DMA2D_FGCLUT113,DMA2D foreground CLUT" hexmask.long.byte 0x1C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1C4 0.--7. 1. "BLUE,Blue" line.long 0x1C8 "DMA2D_FGCLUT114,DMA2D foreground CLUT" hexmask.long.byte 0x1C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1C8 0.--7. 1. "BLUE,Blue" line.long 0x1CC "DMA2D_FGCLUT115,DMA2D foreground CLUT" hexmask.long.byte 0x1CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1CC 0.--7. 1. "BLUE,Blue" line.long 0x1D0 "DMA2D_FGCLUT116,DMA2D foreground CLUT" hexmask.long.byte 0x1D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1D0 0.--7. 1. "BLUE,Blue" line.long 0x1D4 "DMA2D_FGCLUT117,DMA2D foreground CLUT" hexmask.long.byte 0x1D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1D4 0.--7. 1. "BLUE,Blue" line.long 0x1D8 "DMA2D_FGCLUT118,DMA2D foreground CLUT" hexmask.long.byte 0x1D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1D8 0.--7. 1. "BLUE,Blue" line.long 0x1DC "DMA2D_FGCLUT119,DMA2D foreground CLUT" hexmask.long.byte 0x1DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1DC 0.--7. 1. "BLUE,Blue" line.long 0x1E0 "DMA2D_FGCLUT120,DMA2D foreground CLUT" hexmask.long.byte 0x1E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1E0 0.--7. 1. "BLUE,Blue" line.long 0x1E4 "DMA2D_FGCLUT121,DMA2D foreground CLUT" hexmask.long.byte 0x1E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1E4 0.--7. 1. "BLUE,Blue" line.long 0x1E8 "DMA2D_FGCLUT122,DMA2D foreground CLUT" hexmask.long.byte 0x1E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1E8 0.--7. 1. "BLUE,Blue" line.long 0x1EC "DMA2D_FGCLUT123,DMA2D foreground CLUT" hexmask.long.byte 0x1EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1EC 0.--7. 1. "BLUE,Blue" line.long 0x1F0 "DMA2D_FGCLUT124,DMA2D foreground CLUT" hexmask.long.byte 0x1F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1F0 0.--7. 1. "BLUE,Blue" line.long 0x1F4 "DMA2D_FGCLUT125,DMA2D foreground CLUT" hexmask.long.byte 0x1F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1F4 0.--7. 1. "BLUE,Blue" line.long 0x1F8 "DMA2D_FGCLUT126,DMA2D foreground CLUT" hexmask.long.byte 0x1F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1F8 0.--7. 1. "BLUE,Blue" line.long 0x1FC "DMA2D_FGCLUT127,DMA2D foreground CLUT" hexmask.long.byte 0x1FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x1FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x1FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x1FC 0.--7. 1. "BLUE,Blue" line.long 0x200 "DMA2D_FGCLUT128,DMA2D foreground CLUT" hexmask.long.byte 0x200 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x200 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x200 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x200 0.--7. 1. "BLUE,Blue" line.long 0x204 "DMA2D_FGCLUT129,DMA2D foreground CLUT" hexmask.long.byte 0x204 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x204 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x204 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x204 0.--7. 1. "BLUE,Blue" line.long 0x208 "DMA2D_FGCLUT130,DMA2D foreground CLUT" hexmask.long.byte 0x208 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x208 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x208 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x208 0.--7. 1. "BLUE,Blue" line.long 0x20C "DMA2D_FGCLUT131,DMA2D foreground CLUT" hexmask.long.byte 0x20C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x20C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x20C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x20C 0.--7. 1. "BLUE,Blue" line.long 0x210 "DMA2D_FGCLUT132,DMA2D foreground CLUT" hexmask.long.byte 0x210 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x210 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x210 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x210 0.--7. 1. "BLUE,Blue" line.long 0x214 "DMA2D_FGCLUT133,DMA2D foreground CLUT" hexmask.long.byte 0x214 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x214 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x214 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x214 0.--7. 1. "BLUE,Blue" line.long 0x218 "DMA2D_FGCLUT134,DMA2D foreground CLUT" hexmask.long.byte 0x218 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x218 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x218 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x218 0.--7. 1. "BLUE,Blue" line.long 0x21C "DMA2D_FGCLUT135,DMA2D foreground CLUT" hexmask.long.byte 0x21C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x21C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x21C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x21C 0.--7. 1. "BLUE,Blue" line.long 0x220 "DMA2D_FGCLUT136,DMA2D foreground CLUT" hexmask.long.byte 0x220 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x220 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x220 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x220 0.--7. 1. "BLUE,Blue" line.long 0x224 "DMA2D_FGCLUT137,DMA2D foreground CLUT" hexmask.long.byte 0x224 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x224 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x224 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x224 0.--7. 1. "BLUE,Blue" line.long 0x228 "DMA2D_FGCLUT138,DMA2D foreground CLUT" hexmask.long.byte 0x228 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x228 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x228 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x228 0.--7. 1. "BLUE,Blue" line.long 0x22C "DMA2D_FGCLUT139,DMA2D foreground CLUT" hexmask.long.byte 0x22C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x22C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x22C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x22C 0.--7. 1. "BLUE,Blue" line.long 0x230 "DMA2D_FGCLUT140,DMA2D foreground CLUT" hexmask.long.byte 0x230 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x230 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x230 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x230 0.--7. 1. "BLUE,Blue" line.long 0x234 "DMA2D_FGCLUT141,DMA2D foreground CLUT" hexmask.long.byte 0x234 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x234 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x234 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x234 0.--7. 1. "BLUE,Blue" line.long 0x238 "DMA2D_FGCLUT142,DMA2D foreground CLUT" hexmask.long.byte 0x238 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x238 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x238 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x238 0.--7. 1. "BLUE,Blue" line.long 0x23C "DMA2D_FGCLUT143,DMA2D foreground CLUT" hexmask.long.byte 0x23C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x23C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x23C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x23C 0.--7. 1. "BLUE,Blue" line.long 0x240 "DMA2D_FGCLUT144,DMA2D foreground CLUT" hexmask.long.byte 0x240 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x240 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x240 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x240 0.--7. 1. "BLUE,Blue" line.long 0x244 "DMA2D_FGCLUT145,DMA2D foreground CLUT" hexmask.long.byte 0x244 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x244 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x244 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x244 0.--7. 1. "BLUE,Blue" line.long 0x248 "DMA2D_FGCLUT146,DMA2D foreground CLUT" hexmask.long.byte 0x248 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x248 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x248 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x248 0.--7. 1. "BLUE,Blue" line.long 0x24C "DMA2D_FGCLUT147,DMA2D foreground CLUT" hexmask.long.byte 0x24C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x24C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x24C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x24C 0.--7. 1. "BLUE,Blue" line.long 0x250 "DMA2D_FGCLUT148,DMA2D foreground CLUT" hexmask.long.byte 0x250 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x250 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x250 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x250 0.--7. 1. "BLUE,Blue" line.long 0x254 "DMA2D_FGCLUT149,DMA2D foreground CLUT" hexmask.long.byte 0x254 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x254 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x254 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x254 0.--7. 1. "BLUE,Blue" line.long 0x258 "DMA2D_FGCLUT150,DMA2D foreground CLUT" hexmask.long.byte 0x258 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x258 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x258 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x258 0.--7. 1. "BLUE,Blue" line.long 0x25C "DMA2D_FGCLUT151,DMA2D foreground CLUT" hexmask.long.byte 0x25C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x25C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x25C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x25C 0.--7. 1. "BLUE,Blue" line.long 0x260 "DMA2D_FGCLUT152,DMA2D foreground CLUT" hexmask.long.byte 0x260 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x260 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x260 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x260 0.--7. 1. "BLUE,Blue" line.long 0x264 "DMA2D_FGCLUT153,DMA2D foreground CLUT" hexmask.long.byte 0x264 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x264 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x264 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x264 0.--7. 1. "BLUE,Blue" line.long 0x268 "DMA2D_FGCLUT154,DMA2D foreground CLUT" hexmask.long.byte 0x268 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x268 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x268 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x268 0.--7. 1. "BLUE,Blue" line.long 0x26C "DMA2D_FGCLUT155,DMA2D foreground CLUT" hexmask.long.byte 0x26C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x26C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x26C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x26C 0.--7. 1. "BLUE,Blue" line.long 0x270 "DMA2D_FGCLUT156,DMA2D foreground CLUT" hexmask.long.byte 0x270 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x270 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x270 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x270 0.--7. 1. "BLUE,Blue" line.long 0x274 "DMA2D_FGCLUT157,DMA2D foreground CLUT" hexmask.long.byte 0x274 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x274 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x274 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x274 0.--7. 1. "BLUE,Blue" line.long 0x278 "DMA2D_FGCLUT158,DMA2D foreground CLUT" hexmask.long.byte 0x278 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x278 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x278 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x278 0.--7. 1. "BLUE,Blue" line.long 0x27C "DMA2D_FGCLUT159,DMA2D foreground CLUT" hexmask.long.byte 0x27C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x27C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x27C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x27C 0.--7. 1. "BLUE,Blue" line.long 0x280 "DMA2D_FGCLUT160,DMA2D foreground CLUT" hexmask.long.byte 0x280 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x280 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x280 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x280 0.--7. 1. "BLUE,Blue" line.long 0x284 "DMA2D_FGCLUT161,DMA2D foreground CLUT" hexmask.long.byte 0x284 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x284 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x284 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x284 0.--7. 1. "BLUE,Blue" line.long 0x288 "DMA2D_FGCLUT162,DMA2D foreground CLUT" hexmask.long.byte 0x288 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x288 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x288 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x288 0.--7. 1. "BLUE,Blue" line.long 0x28C "DMA2D_FGCLUT163,DMA2D foreground CLUT" hexmask.long.byte 0x28C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x28C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x28C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x28C 0.--7. 1. "BLUE,Blue" line.long 0x290 "DMA2D_FGCLUT164,DMA2D foreground CLUT" hexmask.long.byte 0x290 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x290 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x290 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x290 0.--7. 1. "BLUE,Blue" line.long 0x294 "DMA2D_FGCLUT165,DMA2D foreground CLUT" hexmask.long.byte 0x294 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x294 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x294 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x294 0.--7. 1. "BLUE,Blue" line.long 0x298 "DMA2D_FGCLUT166,DMA2D foreground CLUT" hexmask.long.byte 0x298 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x298 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x298 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x298 0.--7. 1. "BLUE,Blue" line.long 0x29C "DMA2D_FGCLUT167,DMA2D foreground CLUT" hexmask.long.byte 0x29C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x29C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x29C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x29C 0.--7. 1. "BLUE,Blue" line.long 0x2A0 "DMA2D_FGCLUT168,DMA2D foreground CLUT" hexmask.long.byte 0x2A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2A0 0.--7. 1. "BLUE,Blue" line.long 0x2A4 "DMA2D_FGCLUT169,DMA2D foreground CLUT" hexmask.long.byte 0x2A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2A4 0.--7. 1. "BLUE,Blue" line.long 0x2A8 "DMA2D_FGCLUT170,DMA2D foreground CLUT" hexmask.long.byte 0x2A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2A8 0.--7. 1. "BLUE,Blue" line.long 0x2AC "DMA2D_FGCLUT171,DMA2D foreground CLUT" hexmask.long.byte 0x2AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2AC 0.--7. 1. "BLUE,Blue" line.long 0x2B0 "DMA2D_FGCLUT172,DMA2D foreground CLUT" hexmask.long.byte 0x2B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2B0 0.--7. 1. "BLUE,Blue" line.long 0x2B4 "DMA2D_FGCLUT173,DMA2D foreground CLUT" hexmask.long.byte 0x2B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2B4 0.--7. 1. "BLUE,Blue" line.long 0x2B8 "DMA2D_FGCLUT174,DMA2D foreground CLUT" hexmask.long.byte 0x2B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2B8 0.--7. 1. "BLUE,Blue" line.long 0x2BC "DMA2D_FGCLUT175,DMA2D foreground CLUT" hexmask.long.byte 0x2BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2BC 0.--7. 1. "BLUE,Blue" line.long 0x2C0 "DMA2D_FGCLUT176,DMA2D foreground CLUT" hexmask.long.byte 0x2C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2C0 0.--7. 1. "BLUE,Blue" line.long 0x2C4 "DMA2D_FGCLUT177,DMA2D foreground CLUT" hexmask.long.byte 0x2C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2C4 0.--7. 1. "BLUE,Blue" line.long 0x2C8 "DMA2D_FGCLUT178,DMA2D foreground CLUT" hexmask.long.byte 0x2C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2C8 0.--7. 1. "BLUE,Blue" line.long 0x2CC "DMA2D_FGCLUT179,DMA2D foreground CLUT" hexmask.long.byte 0x2CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2CC 0.--7. 1. "BLUE,Blue" line.long 0x2D0 "DMA2D_FGCLUT180,DMA2D foreground CLUT" hexmask.long.byte 0x2D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2D0 0.--7. 1. "BLUE,Blue" line.long 0x2D4 "DMA2D_FGCLUT181,DMA2D foreground CLUT" hexmask.long.byte 0x2D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2D4 0.--7. 1. "BLUE,Blue" line.long 0x2D8 "DMA2D_FGCLUT182,DMA2D foreground CLUT" hexmask.long.byte 0x2D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2D8 0.--7. 1. "BLUE,Blue" line.long 0x2DC "DMA2D_FGCLUT183,DMA2D foreground CLUT" hexmask.long.byte 0x2DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2DC 0.--7. 1. "BLUE,Blue" line.long 0x2E0 "DMA2D_FGCLUT184,DMA2D foreground CLUT" hexmask.long.byte 0x2E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2E0 0.--7. 1. "BLUE,Blue" line.long 0x2E4 "DMA2D_FGCLUT185,DMA2D foreground CLUT" hexmask.long.byte 0x2E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2E4 0.--7. 1. "BLUE,Blue" line.long 0x2E8 "DMA2D_FGCLUT186,DMA2D foreground CLUT" hexmask.long.byte 0x2E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2E8 0.--7. 1. "BLUE,Blue" line.long 0x2EC "DMA2D_FGCLUT187,DMA2D foreground CLUT" hexmask.long.byte 0x2EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2EC 0.--7. 1. "BLUE,Blue" line.long 0x2F0 "DMA2D_FGCLUT188,DMA2D foreground CLUT" hexmask.long.byte 0x2F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2F0 0.--7. 1. "BLUE,Blue" line.long 0x2F4 "DMA2D_FGCLUT189,DMA2D foreground CLUT" hexmask.long.byte 0x2F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2F4 0.--7. 1. "BLUE,Blue" line.long 0x2F8 "DMA2D_FGCLUT190,DMA2D foreground CLUT" hexmask.long.byte 0x2F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2F8 0.--7. 1. "BLUE,Blue" line.long 0x2FC "DMA2D_FGCLUT191,DMA2D foreground CLUT" hexmask.long.byte 0x2FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x2FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x2FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x2FC 0.--7. 1. "BLUE,Blue" line.long 0x300 "DMA2D_FGCLUT192,DMA2D foreground CLUT" hexmask.long.byte 0x300 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x300 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x300 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x300 0.--7. 1. "BLUE,Blue" line.long 0x304 "DMA2D_FGCLUT193,DMA2D foreground CLUT" hexmask.long.byte 0x304 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x304 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x304 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x304 0.--7. 1. "BLUE,Blue" line.long 0x308 "DMA2D_FGCLUT194,DMA2D foreground CLUT" hexmask.long.byte 0x308 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x308 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x308 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x308 0.--7. 1. "BLUE,Blue" line.long 0x30C "DMA2D_FGCLUT195,DMA2D foreground CLUT" hexmask.long.byte 0x30C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x30C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x30C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x30C 0.--7. 1. "BLUE,Blue" line.long 0x310 "DMA2D_FGCLUT196,DMA2D foreground CLUT" hexmask.long.byte 0x310 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x310 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x310 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x310 0.--7. 1. "BLUE,Blue" line.long 0x314 "DMA2D_FGCLUT197,DMA2D foreground CLUT" hexmask.long.byte 0x314 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x314 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x314 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x314 0.--7. 1. "BLUE,Blue" line.long 0x318 "DMA2D_FGCLUT198,DMA2D foreground CLUT" hexmask.long.byte 0x318 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x318 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x318 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x318 0.--7. 1. "BLUE,Blue" line.long 0x31C "DMA2D_FGCLUT199,DMA2D foreground CLUT" hexmask.long.byte 0x31C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x31C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x31C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x31C 0.--7. 1. "BLUE,Blue" line.long 0x320 "DMA2D_FGCLUT200,DMA2D foreground CLUT" hexmask.long.byte 0x320 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x320 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x320 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x320 0.--7. 1. "BLUE,Blue" line.long 0x324 "DMA2D_FGCLUT201,DMA2D foreground CLUT" hexmask.long.byte 0x324 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x324 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x324 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x324 0.--7. 1. "BLUE,Blue" line.long 0x328 "DMA2D_FGCLUT202,DMA2D foreground CLUT" hexmask.long.byte 0x328 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x328 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x328 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x328 0.--7. 1. "BLUE,Blue" line.long 0x32C "DMA2D_FGCLUT203,DMA2D foreground CLUT" hexmask.long.byte 0x32C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x32C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x32C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x32C 0.--7. 1. "BLUE,Blue" line.long 0x330 "DMA2D_FGCLUT204,DMA2D foreground CLUT" hexmask.long.byte 0x330 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x330 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x330 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x330 0.--7. 1. "BLUE,Blue" line.long 0x334 "DMA2D_FGCLUT205,DMA2D foreground CLUT" hexmask.long.byte 0x334 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x334 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x334 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x334 0.--7. 1. "BLUE,Blue" line.long 0x338 "DMA2D_FGCLUT206,DMA2D foreground CLUT" hexmask.long.byte 0x338 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x338 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x338 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x338 0.--7. 1. "BLUE,Blue" line.long 0x33C "DMA2D_FGCLUT207,DMA2D foreground CLUT" hexmask.long.byte 0x33C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x33C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x33C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x33C 0.--7. 1. "BLUE,Blue" line.long 0x340 "DMA2D_FGCLUT208,DMA2D foreground CLUT" hexmask.long.byte 0x340 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x340 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x340 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x340 0.--7. 1. "BLUE,Blue" line.long 0x344 "DMA2D_FGCLUT209,DMA2D foreground CLUT" hexmask.long.byte 0x344 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x344 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x344 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x344 0.--7. 1. "BLUE,Blue" line.long 0x348 "DMA2D_FGCLUT210,DMA2D foreground CLUT" hexmask.long.byte 0x348 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x348 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x348 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x348 0.--7. 1. "BLUE,Blue" line.long 0x34C "DMA2D_FGCLUT211,DMA2D foreground CLUT" hexmask.long.byte 0x34C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x34C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x34C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x34C 0.--7. 1. "BLUE,Blue" line.long 0x350 "DMA2D_FGCLUT212,DMA2D foreground CLUT" hexmask.long.byte 0x350 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x350 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x350 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x350 0.--7. 1. "BLUE,Blue" line.long 0x354 "DMA2D_FGCLUT213,DMA2D foreground CLUT" hexmask.long.byte 0x354 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x354 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x354 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x354 0.--7. 1. "BLUE,Blue" line.long 0x358 "DMA2D_FGCLUT214,DMA2D foreground CLUT" hexmask.long.byte 0x358 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x358 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x358 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x358 0.--7. 1. "BLUE,Blue" line.long 0x35C "DMA2D_FGCLUT215,DMA2D foreground CLUT" hexmask.long.byte 0x35C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x35C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x35C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x35C 0.--7. 1. "BLUE,Blue" line.long 0x360 "DMA2D_FGCLUT216,DMA2D foreground CLUT" hexmask.long.byte 0x360 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x360 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x360 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x360 0.--7. 1. "BLUE,Blue" line.long 0x364 "DMA2D_FGCLUT217,DMA2D foreground CLUT" hexmask.long.byte 0x364 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x364 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x364 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x364 0.--7. 1. "BLUE,Blue" line.long 0x368 "DMA2D_FGCLUT218,DMA2D foreground CLUT" hexmask.long.byte 0x368 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x368 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x368 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x368 0.--7. 1. "BLUE,Blue" line.long 0x36C "DMA2D_FGCLUT219,DMA2D foreground CLUT" hexmask.long.byte 0x36C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x36C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x36C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x36C 0.--7. 1. "BLUE,Blue" line.long 0x370 "DMA2D_FGCLUT220,DMA2D foreground CLUT" hexmask.long.byte 0x370 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x370 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x370 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x370 0.--7. 1. "BLUE,Blue" line.long 0x374 "DMA2D_FGCLUT221,DMA2D foreground CLUT" hexmask.long.byte 0x374 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x374 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x374 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x374 0.--7. 1. "BLUE,Blue" line.long 0x378 "DMA2D_FGCLUT222,DMA2D foreground CLUT" hexmask.long.byte 0x378 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x378 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x378 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x378 0.--7. 1. "BLUE,Blue" line.long 0x37C "DMA2D_FGCLUT223,DMA2D foreground CLUT" hexmask.long.byte 0x37C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x37C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x37C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x37C 0.--7. 1. "BLUE,Blue" line.long 0x380 "DMA2D_FGCLUT224,DMA2D foreground CLUT" hexmask.long.byte 0x380 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x380 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x380 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x380 0.--7. 1. "BLUE,Blue" line.long 0x384 "DMA2D_FGCLUT225,DMA2D foreground CLUT" hexmask.long.byte 0x384 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x384 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x384 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x384 0.--7. 1. "BLUE,Blue" line.long 0x388 "DMA2D_FGCLUT226,DMA2D foreground CLUT" hexmask.long.byte 0x388 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x388 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x388 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x388 0.--7. 1. "BLUE,Blue" line.long 0x38C "DMA2D_FGCLUT227,DMA2D foreground CLUT" hexmask.long.byte 0x38C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x38C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x38C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x38C 0.--7. 1. "BLUE,Blue" line.long 0x390 "DMA2D_FGCLUT228,DMA2D foreground CLUT" hexmask.long.byte 0x390 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x390 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x390 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x390 0.--7. 1. "BLUE,Blue" line.long 0x394 "DMA2D_FGCLUT229,DMA2D foreground CLUT" hexmask.long.byte 0x394 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x394 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x394 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x394 0.--7. 1. "BLUE,Blue" line.long 0x398 "DMA2D_FGCLUT230,DMA2D foreground CLUT" hexmask.long.byte 0x398 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x398 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x398 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x398 0.--7. 1. "BLUE,Blue" line.long 0x39C "DMA2D_FGCLUT231,DMA2D foreground CLUT" hexmask.long.byte 0x39C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x39C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x39C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x39C 0.--7. 1. "BLUE,Blue" line.long 0x3A0 "DMA2D_FGCLUT232,DMA2D foreground CLUT" hexmask.long.byte 0x3A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3A0 0.--7. 1. "BLUE,Blue" line.long 0x3A4 "DMA2D_FGCLUT233,DMA2D foreground CLUT" hexmask.long.byte 0x3A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3A4 0.--7. 1. "BLUE,Blue" line.long 0x3A8 "DMA2D_FGCLUT234,DMA2D foreground CLUT" hexmask.long.byte 0x3A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3A8 0.--7. 1. "BLUE,Blue" line.long 0x3AC "DMA2D_FGCLUT235,DMA2D foreground CLUT" hexmask.long.byte 0x3AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3AC 0.--7. 1. "BLUE,Blue" line.long 0x3B0 "DMA2D_FGCLUT236,DMA2D foreground CLUT" hexmask.long.byte 0x3B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3B0 0.--7. 1. "BLUE,Blue" line.long 0x3B4 "DMA2D_FGCLUT237,DMA2D foreground CLUT" hexmask.long.byte 0x3B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3B4 0.--7. 1. "BLUE,Blue" line.long 0x3B8 "DMA2D_FGCLUT238,DMA2D foreground CLUT" hexmask.long.byte 0x3B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3B8 0.--7. 1. "BLUE,Blue" line.long 0x3BC "DMA2D_FGCLUT239,DMA2D foreground CLUT" hexmask.long.byte 0x3BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3BC 0.--7. 1. "BLUE,Blue" line.long 0x3C0 "DMA2D_FGCLUT240,DMA2D foreground CLUT" hexmask.long.byte 0x3C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3C0 0.--7. 1. "BLUE,Blue" line.long 0x3C4 "DMA2D_FGCLUT241,DMA2D foreground CLUT" hexmask.long.byte 0x3C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3C4 0.--7. 1. "BLUE,Blue" line.long 0x3C8 "DMA2D_FGCLUT242,DMA2D foreground CLUT" hexmask.long.byte 0x3C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3C8 0.--7. 1. "BLUE,Blue" line.long 0x3CC "DMA2D_FGCLUT243,DMA2D foreground CLUT" hexmask.long.byte 0x3CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3CC 0.--7. 1. "BLUE,Blue" line.long 0x3D0 "DMA2D_FGCLUT244,DMA2D foreground CLUT" hexmask.long.byte 0x3D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3D0 0.--7. 1. "BLUE,Blue" line.long 0x3D4 "DMA2D_FGCLUT245,DMA2D foreground CLUT" hexmask.long.byte 0x3D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3D4 0.--7. 1. "BLUE,Blue" line.long 0x3D8 "DMA2D_FGCLUT246,DMA2D foreground CLUT" hexmask.long.byte 0x3D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3D8 0.--7. 1. "BLUE,Blue" line.long 0x3DC "DMA2D_FGCLUT247,DMA2D foreground CLUT" hexmask.long.byte 0x3DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3DC 0.--7. 1. "BLUE,Blue" line.long 0x3E0 "DMA2D_FGCLUT248,DMA2D foreground CLUT" hexmask.long.byte 0x3E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3E0 0.--7. 1. "BLUE,Blue" line.long 0x3E4 "DMA2D_FGCLUT249,DMA2D foreground CLUT" hexmask.long.byte 0x3E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3E4 0.--7. 1. "BLUE,Blue" line.long 0x3E8 "DMA2D_FGCLUT250,DMA2D foreground CLUT" hexmask.long.byte 0x3E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3E8 0.--7. 1. "BLUE,Blue" line.long 0x3EC "DMA2D_FGCLUT251,DMA2D foreground CLUT" hexmask.long.byte 0x3EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3EC 0.--7. 1. "BLUE,Blue" line.long 0x3F0 "DMA2D_FGCLUT252,DMA2D foreground CLUT" hexmask.long.byte 0x3F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3F0 0.--7. 1. "BLUE,Blue" line.long 0x3F4 "DMA2D_FGCLUT253,DMA2D foreground CLUT" hexmask.long.byte 0x3F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3F4 0.--7. 1. "BLUE,Blue" line.long 0x3F8 "DMA2D_FGCLUT254,DMA2D foreground CLUT" hexmask.long.byte 0x3F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3F8 0.--7. 1. "BLUE,Blue" line.long 0x3FC "DMA2D_FGCLUT255,DMA2D foreground CLUT" hexmask.long.byte 0x3FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x3FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x3FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x3FC 0.--7. 1. "BLUE,Blue" line.long 0x400 "DMA2D_BGCLUT0,DMA2D background CLUT" hexmask.long.byte 0x400 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x400 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x400 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x400 0.--7. 1. "BLUE,Blue" line.long 0x404 "DMA2D_BGCLUT1,DMA2D background CLUT" hexmask.long.byte 0x404 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x404 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x404 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x404 0.--7. 1. "BLUE,Blue" line.long 0x408 "DMA2D_BGCLUT2,DMA2D background CLUT" hexmask.long.byte 0x408 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x408 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x408 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x408 0.--7. 1. "BLUE,Blue" line.long 0x40C "DMA2D_BGCLUT3,DMA2D background CLUT" hexmask.long.byte 0x40C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x40C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x40C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x40C 0.--7. 1. "BLUE,Blue" line.long 0x410 "DMA2D_BGCLUT4,DMA2D background CLUT" hexmask.long.byte 0x410 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x410 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x410 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x410 0.--7. 1. "BLUE,Blue" line.long 0x414 "DMA2D_BGCLUT5,DMA2D background CLUT" hexmask.long.byte 0x414 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x414 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x414 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x414 0.--7. 1. "BLUE,Blue" line.long 0x418 "DMA2D_BGCLUT6,DMA2D background CLUT" hexmask.long.byte 0x418 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x418 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x418 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x418 0.--7. 1. "BLUE,Blue" line.long 0x41C "DMA2D_BGCLUT7,DMA2D background CLUT" hexmask.long.byte 0x41C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x41C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x41C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x41C 0.--7. 1. "BLUE,Blue" line.long 0x420 "DMA2D_BGCLUT8,DMA2D background CLUT" hexmask.long.byte 0x420 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x420 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x420 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x420 0.--7. 1. "BLUE,Blue" line.long 0x424 "DMA2D_BGCLUT9,DMA2D background CLUT" hexmask.long.byte 0x424 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x424 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x424 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x424 0.--7. 1. "BLUE,Blue" line.long 0x428 "DMA2D_BGCLUT10,DMA2D background CLUT" hexmask.long.byte 0x428 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x428 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x428 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x428 0.--7. 1. "BLUE,Blue" line.long 0x42C "DMA2D_BGCLUT11,DMA2D background CLUT" hexmask.long.byte 0x42C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x42C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x42C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x42C 0.--7. 1. "BLUE,Blue" line.long 0x430 "DMA2D_BGCLUT12,DMA2D background CLUT" hexmask.long.byte 0x430 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x430 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x430 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x430 0.--7. 1. "BLUE,Blue" line.long 0x434 "DMA2D_BGCLUT13,DMA2D background CLUT" hexmask.long.byte 0x434 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x434 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x434 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x434 0.--7. 1. "BLUE,Blue" line.long 0x438 "DMA2D_BGCLUT14,DMA2D background CLUT" hexmask.long.byte 0x438 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x438 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x438 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x438 0.--7. 1. "BLUE,Blue" line.long 0x43C "DMA2D_BGCLUT15,DMA2D background CLUT" hexmask.long.byte 0x43C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x43C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x43C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x43C 0.--7. 1. "BLUE,Blue" line.long 0x440 "DMA2D_BGCLUT16,DMA2D background CLUT" hexmask.long.byte 0x440 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x440 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x440 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x440 0.--7. 1. "BLUE,Blue" line.long 0x444 "DMA2D_BGCLUT17,DMA2D background CLUT" hexmask.long.byte 0x444 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x444 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x444 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x444 0.--7. 1. "BLUE,Blue" line.long 0x448 "DMA2D_BGCLUT18,DMA2D background CLUT" hexmask.long.byte 0x448 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x448 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x448 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x448 0.--7. 1. "BLUE,Blue" line.long 0x44C "DMA2D_BGCLUT19,DMA2D background CLUT" hexmask.long.byte 0x44C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x44C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x44C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x44C 0.--7. 1. "BLUE,Blue" line.long 0x450 "DMA2D_BGCLUT20,DMA2D background CLUT" hexmask.long.byte 0x450 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x450 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x450 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x450 0.--7. 1. "BLUE,Blue" line.long 0x454 "DMA2D_BGCLUT21,DMA2D background CLUT" hexmask.long.byte 0x454 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x454 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x454 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x454 0.--7. 1. "BLUE,Blue" line.long 0x458 "DMA2D_BGCLUT22,DMA2D background CLUT" hexmask.long.byte 0x458 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x458 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x458 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x458 0.--7. 1. "BLUE,Blue" line.long 0x45C "DMA2D_BGCLUT23,DMA2D background CLUT" hexmask.long.byte 0x45C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x45C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x45C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x45C 0.--7. 1. "BLUE,Blue" line.long 0x460 "DMA2D_BGCLUT24,DMA2D background CLUT" hexmask.long.byte 0x460 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x460 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x460 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x460 0.--7. 1. "BLUE,Blue" line.long 0x464 "DMA2D_BGCLUT25,DMA2D background CLUT" hexmask.long.byte 0x464 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x464 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x464 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x464 0.--7. 1. "BLUE,Blue" line.long 0x468 "DMA2D_BGCLUT26,DMA2D background CLUT" hexmask.long.byte 0x468 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x468 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x468 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x468 0.--7. 1. "BLUE,Blue" line.long 0x46C "DMA2D_BGCLUT27,DMA2D background CLUT" hexmask.long.byte 0x46C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x46C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x46C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x46C 0.--7. 1. "BLUE,Blue" line.long 0x470 "DMA2D_BGCLUT28,DMA2D background CLUT" hexmask.long.byte 0x470 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x470 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x470 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x470 0.--7. 1. "BLUE,Blue" line.long 0x474 "DMA2D_BGCLUT29,DMA2D background CLUT" hexmask.long.byte 0x474 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x474 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x474 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x474 0.--7. 1. "BLUE,Blue" line.long 0x478 "DMA2D_BGCLUT30,DMA2D background CLUT" hexmask.long.byte 0x478 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x478 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x478 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x478 0.--7. 1. "BLUE,Blue" line.long 0x47C "DMA2D_BGCLUT31,DMA2D background CLUT" hexmask.long.byte 0x47C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x47C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x47C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x47C 0.--7. 1. "BLUE,Blue" line.long 0x480 "DMA2D_BGCLUT32,DMA2D background CLUT" hexmask.long.byte 0x480 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x480 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x480 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x480 0.--7. 1. "BLUE,Blue" line.long 0x484 "DMA2D_BGCLUT33,DMA2D background CLUT" hexmask.long.byte 0x484 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x484 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x484 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x484 0.--7. 1. "BLUE,Blue" line.long 0x488 "DMA2D_BGCLUT34,DMA2D background CLUT" hexmask.long.byte 0x488 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x488 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x488 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x488 0.--7. 1. "BLUE,Blue" line.long 0x48C "DMA2D_BGCLUT35,DMA2D background CLUT" hexmask.long.byte 0x48C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x48C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x48C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x48C 0.--7. 1. "BLUE,Blue" line.long 0x490 "DMA2D_BGCLUT36,DMA2D background CLUT" hexmask.long.byte 0x490 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x490 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x490 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x490 0.--7. 1. "BLUE,Blue" line.long 0x494 "DMA2D_BGCLUT37,DMA2D background CLUT" hexmask.long.byte 0x494 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x494 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x494 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x494 0.--7. 1. "BLUE,Blue" line.long 0x498 "DMA2D_BGCLUT38,DMA2D background CLUT" hexmask.long.byte 0x498 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x498 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x498 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x498 0.--7. 1. "BLUE,Blue" line.long 0x49C "DMA2D_BGCLUT39,DMA2D background CLUT" hexmask.long.byte 0x49C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x49C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x49C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x49C 0.--7. 1. "BLUE,Blue" line.long 0x4A0 "DMA2D_BGCLUT40,DMA2D background CLUT" hexmask.long.byte 0x4A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4A0 0.--7. 1. "BLUE,Blue" line.long 0x4A4 "DMA2D_BGCLUT41,DMA2D background CLUT" hexmask.long.byte 0x4A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4A4 0.--7. 1. "BLUE,Blue" line.long 0x4A8 "DMA2D_BGCLUT42,DMA2D background CLUT" hexmask.long.byte 0x4A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4A8 0.--7. 1. "BLUE,Blue" line.long 0x4AC "DMA2D_BGCLUT43,DMA2D background CLUT" hexmask.long.byte 0x4AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4AC 0.--7. 1. "BLUE,Blue" line.long 0x4B0 "DMA2D_BGCLUT44,DMA2D background CLUT" hexmask.long.byte 0x4B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4B0 0.--7. 1. "BLUE,Blue" line.long 0x4B4 "DMA2D_BGCLUT45,DMA2D background CLUT" hexmask.long.byte 0x4B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4B4 0.--7. 1. "BLUE,Blue" line.long 0x4B8 "DMA2D_BGCLUT46,DMA2D background CLUT" hexmask.long.byte 0x4B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4B8 0.--7. 1. "BLUE,Blue" line.long 0x4BC "DMA2D_BGCLUT47,DMA2D background CLUT" hexmask.long.byte 0x4BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4BC 0.--7. 1. "BLUE,Blue" line.long 0x4C0 "DMA2D_BGCLUT48,DMA2D background CLUT" hexmask.long.byte 0x4C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4C0 0.--7. 1. "BLUE,Blue" line.long 0x4C4 "DMA2D_BGCLUT49,DMA2D background CLUT" hexmask.long.byte 0x4C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4C4 0.--7. 1. "BLUE,Blue" line.long 0x4C8 "DMA2D_BGCLUT50,DMA2D background CLUT" hexmask.long.byte 0x4C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4C8 0.--7. 1. "BLUE,Blue" line.long 0x4CC "DMA2D_BGCLUT51,DMA2D background CLUT" hexmask.long.byte 0x4CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4CC 0.--7. 1. "BLUE,Blue" line.long 0x4D0 "DMA2D_BGCLUT52,DMA2D background CLUT" hexmask.long.byte 0x4D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4D0 0.--7. 1. "BLUE,Blue" line.long 0x4D4 "DMA2D_BGCLUT53,DMA2D background CLUT" hexmask.long.byte 0x4D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4D4 0.--7. 1. "BLUE,Blue" line.long 0x4D8 "DMA2D_BGCLUT54,DMA2D background CLUT" hexmask.long.byte 0x4D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4D8 0.--7. 1. "BLUE,Blue" line.long 0x4DC "DMA2D_BGCLUT55,DMA2D background CLUT" hexmask.long.byte 0x4DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4DC 0.--7. 1. "BLUE,Blue" line.long 0x4E0 "DMA2D_BGCLUT56,DMA2D background CLUT" hexmask.long.byte 0x4E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4E0 0.--7. 1. "BLUE,Blue" line.long 0x4E4 "DMA2D_BGCLUT57,DMA2D background CLUT" hexmask.long.byte 0x4E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4E4 0.--7. 1. "BLUE,Blue" line.long 0x4E8 "DMA2D_BGCLUT58,DMA2D background CLUT" hexmask.long.byte 0x4E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4E8 0.--7. 1. "BLUE,Blue" line.long 0x4EC "DMA2D_BGCLUT59,DMA2D background CLUT" hexmask.long.byte 0x4EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4EC 0.--7. 1. "BLUE,Blue" line.long 0x4F0 "DMA2D_BGCLUT60,DMA2D background CLUT" hexmask.long.byte 0x4F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4F0 0.--7. 1. "BLUE,Blue" line.long 0x4F4 "DMA2D_BGCLUT61,DMA2D background CLUT" hexmask.long.byte 0x4F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4F4 0.--7. 1. "BLUE,Blue" line.long 0x4F8 "DMA2D_BGCLUT62,DMA2D background CLUT" hexmask.long.byte 0x4F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4F8 0.--7. 1. "BLUE,Blue" line.long 0x4FC "DMA2D_BGCLUT63,DMA2D background CLUT" hexmask.long.byte 0x4FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x4FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x4FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x4FC 0.--7. 1. "BLUE,Blue" line.long 0x500 "DMA2D_BGCLUT64,DMA2D background CLUT" hexmask.long.byte 0x500 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x500 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x500 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x500 0.--7. 1. "BLUE,Blue" line.long 0x504 "DMA2D_BGCLUT65,DMA2D background CLUT" hexmask.long.byte 0x504 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x504 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x504 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x504 0.--7. 1. "BLUE,Blue" line.long 0x508 "DMA2D_BGCLUT66,DMA2D background CLUT" hexmask.long.byte 0x508 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x508 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x508 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x508 0.--7. 1. "BLUE,Blue" line.long 0x50C "DMA2D_BGCLUT67,DMA2D background CLUT" hexmask.long.byte 0x50C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x50C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x50C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x50C 0.--7. 1. "BLUE,Blue" line.long 0x510 "DMA2D_BGCLUT68,DMA2D background CLUT" hexmask.long.byte 0x510 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x510 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x510 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x510 0.--7. 1. "BLUE,Blue" line.long 0x514 "DMA2D_BGCLUT69,DMA2D background CLUT" hexmask.long.byte 0x514 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x514 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x514 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x514 0.--7. 1. "BLUE,Blue" line.long 0x518 "DMA2D_BGCLUT70,DMA2D background CLUT" hexmask.long.byte 0x518 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x518 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x518 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x518 0.--7. 1. "BLUE,Blue" line.long 0x51C "DMA2D_BGCLUT71,DMA2D background CLUT" hexmask.long.byte 0x51C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x51C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x51C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x51C 0.--7. 1. "BLUE,Blue" line.long 0x520 "DMA2D_BGCLUT72,DMA2D background CLUT" hexmask.long.byte 0x520 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x520 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x520 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x520 0.--7. 1. "BLUE,Blue" line.long 0x524 "DMA2D_BGCLUT73,DMA2D background CLUT" hexmask.long.byte 0x524 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x524 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x524 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x524 0.--7. 1. "BLUE,Blue" line.long 0x528 "DMA2D_BGCLUT74,DMA2D background CLUT" hexmask.long.byte 0x528 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x528 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x528 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x528 0.--7. 1. "BLUE,Blue" line.long 0x52C "DMA2D_BGCLUT75,DMA2D background CLUT" hexmask.long.byte 0x52C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x52C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x52C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x52C 0.--7. 1. "BLUE,Blue" line.long 0x530 "DMA2D_BGCLUT76,DMA2D background CLUT" hexmask.long.byte 0x530 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x530 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x530 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x530 0.--7. 1. "BLUE,Blue" line.long 0x534 "DMA2D_BGCLUT77,DMA2D background CLUT" hexmask.long.byte 0x534 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x534 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x534 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x534 0.--7. 1. "BLUE,Blue" line.long 0x538 "DMA2D_BGCLUT78,DMA2D background CLUT" hexmask.long.byte 0x538 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x538 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x538 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x538 0.--7. 1. "BLUE,Blue" line.long 0x53C "DMA2D_BGCLUT79,DMA2D background CLUT" hexmask.long.byte 0x53C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x53C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x53C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x53C 0.--7. 1. "BLUE,Blue" line.long 0x540 "DMA2D_BGCLUT80,DMA2D background CLUT" hexmask.long.byte 0x540 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x540 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x540 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x540 0.--7. 1. "BLUE,Blue" line.long 0x544 "DMA2D_BGCLUT81,DMA2D background CLUT" hexmask.long.byte 0x544 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x544 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x544 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x544 0.--7. 1. "BLUE,Blue" line.long 0x548 "DMA2D_BGCLUT82,DMA2D background CLUT" hexmask.long.byte 0x548 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x548 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x548 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x548 0.--7. 1. "BLUE,Blue" line.long 0x54C "DMA2D_BGCLUT83,DMA2D background CLUT" hexmask.long.byte 0x54C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x54C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x54C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x54C 0.--7. 1. "BLUE,Blue" line.long 0x550 "DMA2D_BGCLUT84,DMA2D background CLUT" hexmask.long.byte 0x550 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x550 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x550 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x550 0.--7. 1. "BLUE,Blue" line.long 0x554 "DMA2D_BGCLUT85,DMA2D background CLUT" hexmask.long.byte 0x554 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x554 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x554 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x554 0.--7. 1. "BLUE,Blue" line.long 0x558 "DMA2D_BGCLUT86,DMA2D background CLUT" hexmask.long.byte 0x558 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x558 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x558 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x558 0.--7. 1. "BLUE,Blue" line.long 0x55C "DMA2D_BGCLUT87,DMA2D background CLUT" hexmask.long.byte 0x55C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x55C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x55C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x55C 0.--7. 1. "BLUE,Blue" line.long 0x560 "DMA2D_BGCLUT88,DMA2D background CLUT" hexmask.long.byte 0x560 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x560 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x560 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x560 0.--7. 1. "BLUE,Blue" line.long 0x564 "DMA2D_BGCLUT89,DMA2D background CLUT" hexmask.long.byte 0x564 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x564 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x564 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x564 0.--7. 1. "BLUE,Blue" line.long 0x568 "DMA2D_BGCLUT90,DMA2D background CLUT" hexmask.long.byte 0x568 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x568 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x568 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x568 0.--7. 1. "BLUE,Blue" line.long 0x56C "DMA2D_BGCLUT91,DMA2D background CLUT" hexmask.long.byte 0x56C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x56C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x56C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x56C 0.--7. 1. "BLUE,Blue" line.long 0x570 "DMA2D_BGCLUT92,DMA2D background CLUT" hexmask.long.byte 0x570 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x570 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x570 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x570 0.--7. 1. "BLUE,Blue" line.long 0x574 "DMA2D_BGCLUT93,DMA2D background CLUT" hexmask.long.byte 0x574 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x574 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x574 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x574 0.--7. 1. "BLUE,Blue" line.long 0x578 "DMA2D_BGCLUT94,DMA2D background CLUT" hexmask.long.byte 0x578 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x578 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x578 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x578 0.--7. 1. "BLUE,Blue" line.long 0x57C "DMA2D_BGCLUT95,DMA2D background CLUT" hexmask.long.byte 0x57C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x57C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x57C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x57C 0.--7. 1. "BLUE,Blue" line.long 0x580 "DMA2D_BGCLUT96,DMA2D background CLUT" hexmask.long.byte 0x580 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x580 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x580 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x580 0.--7. 1. "BLUE,Blue" line.long 0x584 "DMA2D_BGCLUT97,DMA2D background CLUT" hexmask.long.byte 0x584 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x584 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x584 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x584 0.--7. 1. "BLUE,Blue" line.long 0x588 "DMA2D_BGCLUT98,DMA2D background CLUT" hexmask.long.byte 0x588 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x588 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x588 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x588 0.--7. 1. "BLUE,Blue" line.long 0x58C "DMA2D_BGCLUT99,DMA2D background CLUT" hexmask.long.byte 0x58C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x58C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x58C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x58C 0.--7. 1. "BLUE,Blue" line.long 0x590 "DMA2D_BGCLUT100,DMA2D background CLUT" hexmask.long.byte 0x590 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x590 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x590 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x590 0.--7. 1. "BLUE,Blue" line.long 0x594 "DMA2D_BGCLUT101,DMA2D background CLUT" hexmask.long.byte 0x594 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x594 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x594 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x594 0.--7. 1. "BLUE,Blue" line.long 0x598 "DMA2D_BGCLUT102,DMA2D background CLUT" hexmask.long.byte 0x598 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x598 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x598 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x598 0.--7. 1. "BLUE,Blue" line.long 0x59C "DMA2D_BGCLUT103,DMA2D background CLUT" hexmask.long.byte 0x59C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x59C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x59C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x59C 0.--7. 1. "BLUE,Blue" line.long 0x5A0 "DMA2D_BGCLUT104,DMA2D background CLUT" hexmask.long.byte 0x5A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5A0 0.--7. 1. "BLUE,Blue" line.long 0x5A4 "DMA2D_BGCLUT105,DMA2D background CLUT" hexmask.long.byte 0x5A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5A4 0.--7. 1. "BLUE,Blue" line.long 0x5A8 "DMA2D_BGCLUT106,DMA2D background CLUT" hexmask.long.byte 0x5A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5A8 0.--7. 1. "BLUE,Blue" line.long 0x5AC "DMA2D_BGCLUT107,DMA2D background CLUT" hexmask.long.byte 0x5AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5AC 0.--7. 1. "BLUE,Blue" line.long 0x5B0 "DMA2D_BGCLUT108,DMA2D background CLUT" hexmask.long.byte 0x5B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5B0 0.--7. 1. "BLUE,Blue" line.long 0x5B4 "DMA2D_BGCLUT109,DMA2D background CLUT" hexmask.long.byte 0x5B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5B4 0.--7. 1. "BLUE,Blue" line.long 0x5B8 "DMA2D_BGCLUT110,DMA2D background CLUT" hexmask.long.byte 0x5B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5B8 0.--7. 1. "BLUE,Blue" line.long 0x5BC "DMA2D_BGCLUT111,DMA2D background CLUT" hexmask.long.byte 0x5BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5BC 0.--7. 1. "BLUE,Blue" line.long 0x5C0 "DMA2D_BGCLUT112,DMA2D background CLUT" hexmask.long.byte 0x5C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5C0 0.--7. 1. "BLUE,Blue" line.long 0x5C4 "DMA2D_BGCLUT113,DMA2D background CLUT" hexmask.long.byte 0x5C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5C4 0.--7. 1. "BLUE,Blue" line.long 0x5C8 "DMA2D_BGCLUT114,DMA2D background CLUT" hexmask.long.byte 0x5C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5C8 0.--7. 1. "BLUE,Blue" line.long 0x5CC "DMA2D_BGCLUT115,DMA2D background CLUT" hexmask.long.byte 0x5CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5CC 0.--7. 1. "BLUE,Blue" line.long 0x5D0 "DMA2D_BGCLUT116,DMA2D background CLUT" hexmask.long.byte 0x5D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5D0 0.--7. 1. "BLUE,Blue" line.long 0x5D4 "DMA2D_BGCLUT117,DMA2D background CLUT" hexmask.long.byte 0x5D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5D4 0.--7. 1. "BLUE,Blue" line.long 0x5D8 "DMA2D_BGCLUT118,DMA2D background CLUT" hexmask.long.byte 0x5D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5D8 0.--7. 1. "BLUE,Blue" line.long 0x5DC "DMA2D_BGCLUT119,DMA2D background CLUT" hexmask.long.byte 0x5DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5DC 0.--7. 1. "BLUE,Blue" line.long 0x5E0 "DMA2D_BGCLUT120,DMA2D background CLUT" hexmask.long.byte 0x5E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5E0 0.--7. 1. "BLUE,Blue" line.long 0x5E4 "DMA2D_BGCLUT121,DMA2D background CLUT" hexmask.long.byte 0x5E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5E4 0.--7. 1. "BLUE,Blue" line.long 0x5E8 "DMA2D_BGCLUT122,DMA2D background CLUT" hexmask.long.byte 0x5E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5E8 0.--7. 1. "BLUE,Blue" line.long 0x5EC "DMA2D_BGCLUT123,DMA2D background CLUT" hexmask.long.byte 0x5EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5EC 0.--7. 1. "BLUE,Blue" line.long 0x5F0 "DMA2D_BGCLUT124,DMA2D background CLUT" hexmask.long.byte 0x5F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5F0 0.--7. 1. "BLUE,Blue" line.long 0x5F4 "DMA2D_BGCLUT125,DMA2D background CLUT" hexmask.long.byte 0x5F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5F4 0.--7. 1. "BLUE,Blue" line.long 0x5F8 "DMA2D_BGCLUT126,DMA2D background CLUT" hexmask.long.byte 0x5F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5F8 0.--7. 1. "BLUE,Blue" line.long 0x5FC "DMA2D_BGCLUT127,DMA2D background CLUT" hexmask.long.byte 0x5FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x5FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x5FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x5FC 0.--7. 1. "BLUE,Blue" line.long 0x600 "DMA2D_BGCLUT128,DMA2D background CLUT" hexmask.long.byte 0x600 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x600 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x600 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x600 0.--7. 1. "BLUE,Blue" line.long 0x604 "DMA2D_BGCLUT129,DMA2D background CLUT" hexmask.long.byte 0x604 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x604 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x604 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x604 0.--7. 1. "BLUE,Blue" line.long 0x608 "DMA2D_BGCLUT130,DMA2D background CLUT" hexmask.long.byte 0x608 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x608 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x608 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x608 0.--7. 1. "BLUE,Blue" line.long 0x60C "DMA2D_BGCLUT131,DMA2D background CLUT" hexmask.long.byte 0x60C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x60C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x60C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x60C 0.--7. 1. "BLUE,Blue" line.long 0x610 "DMA2D_BGCLUT132,DMA2D background CLUT" hexmask.long.byte 0x610 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x610 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x610 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x610 0.--7. 1. "BLUE,Blue" line.long 0x614 "DMA2D_BGCLUT133,DMA2D background CLUT" hexmask.long.byte 0x614 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x614 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x614 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x614 0.--7. 1. "BLUE,Blue" line.long 0x618 "DMA2D_BGCLUT134,DMA2D background CLUT" hexmask.long.byte 0x618 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x618 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x618 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x618 0.--7. 1. "BLUE,Blue" line.long 0x61C "DMA2D_BGCLUT135,DMA2D background CLUT" hexmask.long.byte 0x61C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x61C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x61C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x61C 0.--7. 1. "BLUE,Blue" line.long 0x620 "DMA2D_BGCLUT136,DMA2D background CLUT" hexmask.long.byte 0x620 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x620 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x620 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x620 0.--7. 1. "BLUE,Blue" line.long 0x624 "DMA2D_BGCLUT137,DMA2D background CLUT" hexmask.long.byte 0x624 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x624 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x624 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x624 0.--7. 1. "BLUE,Blue" line.long 0x628 "DMA2D_BGCLUT138,DMA2D background CLUT" hexmask.long.byte 0x628 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x628 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x628 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x628 0.--7. 1. "BLUE,Blue" line.long 0x62C "DMA2D_BGCLUT139,DMA2D background CLUT" hexmask.long.byte 0x62C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x62C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x62C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x62C 0.--7. 1. "BLUE,Blue" line.long 0x630 "DMA2D_BGCLUT140,DMA2D background CLUT" hexmask.long.byte 0x630 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x630 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x630 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x630 0.--7. 1. "BLUE,Blue" line.long 0x634 "DMA2D_BGCLUT141,DMA2D background CLUT" hexmask.long.byte 0x634 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x634 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x634 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x634 0.--7. 1. "BLUE,Blue" line.long 0x638 "DMA2D_BGCLUT142,DMA2D background CLUT" hexmask.long.byte 0x638 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x638 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x638 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x638 0.--7. 1. "BLUE,Blue" line.long 0x63C "DMA2D_BGCLUT143,DMA2D background CLUT" hexmask.long.byte 0x63C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x63C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x63C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x63C 0.--7. 1. "BLUE,Blue" line.long 0x640 "DMA2D_BGCLUT144,DMA2D background CLUT" hexmask.long.byte 0x640 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x640 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x640 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x640 0.--7. 1. "BLUE,Blue" line.long 0x644 "DMA2D_BGCLUT145,DMA2D background CLUT" hexmask.long.byte 0x644 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x644 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x644 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x644 0.--7. 1. "BLUE,Blue" line.long 0x648 "DMA2D_BGCLUT146,DMA2D background CLUT" hexmask.long.byte 0x648 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x648 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x648 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x648 0.--7. 1. "BLUE,Blue" line.long 0x64C "DMA2D_BGCLUT147,DMA2D background CLUT" hexmask.long.byte 0x64C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x64C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x64C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x64C 0.--7. 1. "BLUE,Blue" line.long 0x650 "DMA2D_BGCLUT148,DMA2D background CLUT" hexmask.long.byte 0x650 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x650 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x650 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x650 0.--7. 1. "BLUE,Blue" line.long 0x654 "DMA2D_BGCLUT149,DMA2D background CLUT" hexmask.long.byte 0x654 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x654 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x654 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x654 0.--7. 1. "BLUE,Blue" line.long 0x658 "DMA2D_BGCLUT150,DMA2D background CLUT" hexmask.long.byte 0x658 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x658 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x658 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x658 0.--7. 1. "BLUE,Blue" line.long 0x65C "DMA2D_BGCLUT151,DMA2D background CLUT" hexmask.long.byte 0x65C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x65C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x65C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x65C 0.--7. 1. "BLUE,Blue" line.long 0x660 "DMA2D_BGCLUT152,DMA2D background CLUT" hexmask.long.byte 0x660 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x660 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x660 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x660 0.--7. 1. "BLUE,Blue" line.long 0x664 "DMA2D_BGCLUT153,DMA2D background CLUT" hexmask.long.byte 0x664 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x664 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x664 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x664 0.--7. 1. "BLUE,Blue" line.long 0x668 "DMA2D_BGCLUT154,DMA2D background CLUT" hexmask.long.byte 0x668 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x668 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x668 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x668 0.--7. 1. "BLUE,Blue" line.long 0x66C "DMA2D_BGCLUT155,DMA2D background CLUT" hexmask.long.byte 0x66C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x66C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x66C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x66C 0.--7. 1. "BLUE,Blue" line.long 0x670 "DMA2D_BGCLUT156,DMA2D background CLUT" hexmask.long.byte 0x670 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x670 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x670 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x670 0.--7. 1. "BLUE,Blue" line.long 0x674 "DMA2D_BGCLUT157,DMA2D background CLUT" hexmask.long.byte 0x674 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x674 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x674 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x674 0.--7. 1. "BLUE,Blue" line.long 0x678 "DMA2D_BGCLUT158,DMA2D background CLUT" hexmask.long.byte 0x678 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x678 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x678 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x678 0.--7. 1. "BLUE,Blue" line.long 0x67C "DMA2D_BGCLUT159,DMA2D background CLUT" hexmask.long.byte 0x67C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x67C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x67C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x67C 0.--7. 1. "BLUE,Blue" line.long 0x680 "DMA2D_BGCLUT160,DMA2D background CLUT" hexmask.long.byte 0x680 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x680 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x680 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x680 0.--7. 1. "BLUE,Blue" line.long 0x684 "DMA2D_BGCLUT161,DMA2D background CLUT" hexmask.long.byte 0x684 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x684 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x684 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x684 0.--7. 1. "BLUE,Blue" line.long 0x688 "DMA2D_BGCLUT162,DMA2D background CLUT" hexmask.long.byte 0x688 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x688 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x688 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x688 0.--7. 1. "BLUE,Blue" line.long 0x68C "DMA2D_BGCLUT163,DMA2D background CLUT" hexmask.long.byte 0x68C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x68C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x68C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x68C 0.--7. 1. "BLUE,Blue" line.long 0x690 "DMA2D_BGCLUT164,DMA2D background CLUT" hexmask.long.byte 0x690 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x690 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x690 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x690 0.--7. 1. "BLUE,Blue" line.long 0x694 "DMA2D_BGCLUT165,DMA2D background CLUT" hexmask.long.byte 0x694 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x694 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x694 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x694 0.--7. 1. "BLUE,Blue" line.long 0x698 "DMA2D_BGCLUT166,DMA2D background CLUT" hexmask.long.byte 0x698 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x698 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x698 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x698 0.--7. 1. "BLUE,Blue" line.long 0x69C "DMA2D_BGCLUT167,DMA2D background CLUT" hexmask.long.byte 0x69C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x69C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x69C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x69C 0.--7. 1. "BLUE,Blue" line.long 0x6A0 "DMA2D_BGCLUT168,DMA2D background CLUT" hexmask.long.byte 0x6A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6A0 0.--7. 1. "BLUE,Blue" line.long 0x6A4 "DMA2D_BGCLUT169,DMA2D background CLUT" hexmask.long.byte 0x6A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6A4 0.--7. 1. "BLUE,Blue" line.long 0x6A8 "DMA2D_BGCLUT170,DMA2D background CLUT" hexmask.long.byte 0x6A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6A8 0.--7. 1. "BLUE,Blue" line.long 0x6AC "DMA2D_BGCLUT171,DMA2D background CLUT" hexmask.long.byte 0x6AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6AC 0.--7. 1. "BLUE,Blue" line.long 0x6B0 "DMA2D_BGCLUT172,DMA2D background CLUT" hexmask.long.byte 0x6B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6B0 0.--7. 1. "BLUE,Blue" line.long 0x6B4 "DMA2D_BGCLUT173,DMA2D background CLUT" hexmask.long.byte 0x6B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6B4 0.--7. 1. "BLUE,Blue" line.long 0x6B8 "DMA2D_BGCLUT174,DMA2D background CLUT" hexmask.long.byte 0x6B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6B8 0.--7. 1. "BLUE,Blue" line.long 0x6BC "DMA2D_BGCLUT175,DMA2D background CLUT" hexmask.long.byte 0x6BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6BC 0.--7. 1. "BLUE,Blue" line.long 0x6C0 "DMA2D_BGCLUT176,DMA2D background CLUT" hexmask.long.byte 0x6C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6C0 0.--7. 1. "BLUE,Blue" line.long 0x6C4 "DMA2D_BGCLUT177,DMA2D background CLUT" hexmask.long.byte 0x6C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6C4 0.--7. 1. "BLUE,Blue" line.long 0x6C8 "DMA2D_BGCLUT178,DMA2D background CLUT" hexmask.long.byte 0x6C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6C8 0.--7. 1. "BLUE,Blue" line.long 0x6CC "DMA2D_BGCLUT179,DMA2D background CLUT" hexmask.long.byte 0x6CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6CC 0.--7. 1. "BLUE,Blue" line.long 0x6D0 "DMA2D_BGCLUT180,DMA2D background CLUT" hexmask.long.byte 0x6D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6D0 0.--7. 1. "BLUE,Blue" line.long 0x6D4 "DMA2D_BGCLUT181,DMA2D background CLUT" hexmask.long.byte 0x6D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6D4 0.--7. 1. "BLUE,Blue" line.long 0x6D8 "DMA2D_BGCLUT182,DMA2D background CLUT" hexmask.long.byte 0x6D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6D8 0.--7. 1. "BLUE,Blue" line.long 0x6DC "DMA2D_BGCLUT183,DMA2D background CLUT" hexmask.long.byte 0x6DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6DC 0.--7. 1. "BLUE,Blue" line.long 0x6E0 "DMA2D_BGCLUT184,DMA2D background CLUT" hexmask.long.byte 0x6E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6E0 0.--7. 1. "BLUE,Blue" line.long 0x6E4 "DMA2D_BGCLUT185,DMA2D background CLUT" hexmask.long.byte 0x6E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6E4 0.--7. 1. "BLUE,Blue" line.long 0x6E8 "DMA2D_BGCLUT186,DMA2D background CLUT" hexmask.long.byte 0x6E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6E8 0.--7. 1. "BLUE,Blue" line.long 0x6EC "DMA2D_BGCLUT187,DMA2D background CLUT" hexmask.long.byte 0x6EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6EC 0.--7. 1. "BLUE,Blue" line.long 0x6F0 "DMA2D_BGCLUT188,DMA2D background CLUT" hexmask.long.byte 0x6F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6F0 0.--7. 1. "BLUE,Blue" line.long 0x6F4 "DMA2D_BGCLUT189,DMA2D background CLUT" hexmask.long.byte 0x6F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6F4 0.--7. 1. "BLUE,Blue" line.long 0x6F8 "DMA2D_BGCLUT190,DMA2D background CLUT" hexmask.long.byte 0x6F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6F8 0.--7. 1. "BLUE,Blue" line.long 0x6FC "DMA2D_BGCLUT191,DMA2D background CLUT" hexmask.long.byte 0x6FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x6FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x6FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x6FC 0.--7. 1. "BLUE,Blue" line.long 0x700 "DMA2D_BGCLUT192,DMA2D background CLUT" hexmask.long.byte 0x700 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x700 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x700 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x700 0.--7. 1. "BLUE,Blue" line.long 0x704 "DMA2D_BGCLUT193,DMA2D background CLUT" hexmask.long.byte 0x704 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x704 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x704 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x704 0.--7. 1. "BLUE,Blue" line.long 0x708 "DMA2D_BGCLUT194,DMA2D background CLUT" hexmask.long.byte 0x708 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x708 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x708 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x708 0.--7. 1. "BLUE,Blue" line.long 0x70C "DMA2D_BGCLUT195,DMA2D background CLUT" hexmask.long.byte 0x70C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x70C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x70C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x70C 0.--7. 1. "BLUE,Blue" line.long 0x710 "DMA2D_BGCLUT196,DMA2D background CLUT" hexmask.long.byte 0x710 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x710 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x710 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x710 0.--7. 1. "BLUE,Blue" line.long 0x714 "DMA2D_BGCLUT197,DMA2D background CLUT" hexmask.long.byte 0x714 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x714 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x714 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x714 0.--7. 1. "BLUE,Blue" line.long 0x718 "DMA2D_BGCLUT198,DMA2D background CLUT" hexmask.long.byte 0x718 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x718 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x718 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x718 0.--7. 1. "BLUE,Blue" line.long 0x71C "DMA2D_BGCLUT199,DMA2D background CLUT" hexmask.long.byte 0x71C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x71C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x71C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x71C 0.--7. 1. "BLUE,Blue" line.long 0x720 "DMA2D_BGCLUT200,DMA2D background CLUT" hexmask.long.byte 0x720 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x720 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x720 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x720 0.--7. 1. "BLUE,Blue" line.long 0x724 "DMA2D_BGCLUT201,DMA2D background CLUT" hexmask.long.byte 0x724 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x724 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x724 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x724 0.--7. 1. "BLUE,Blue" line.long 0x728 "DMA2D_BGCLUT202,DMA2D background CLUT" hexmask.long.byte 0x728 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x728 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x728 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x728 0.--7. 1. "BLUE,Blue" line.long 0x72C "DMA2D_BGCLUT203,DMA2D background CLUT" hexmask.long.byte 0x72C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x72C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x72C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x72C 0.--7. 1. "BLUE,Blue" line.long 0x730 "DMA2D_BGCLUT204,DMA2D background CLUT" hexmask.long.byte 0x730 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x730 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x730 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x730 0.--7. 1. "BLUE,Blue" line.long 0x734 "DMA2D_BGCLUT205,DMA2D background CLUT" hexmask.long.byte 0x734 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x734 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x734 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x734 0.--7. 1. "BLUE,Blue" line.long 0x738 "DMA2D_BGCLUT206,DMA2D background CLUT" hexmask.long.byte 0x738 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x738 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x738 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x738 0.--7. 1. "BLUE,Blue" line.long 0x73C "DMA2D_BGCLUT207,DMA2D background CLUT" hexmask.long.byte 0x73C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x73C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x73C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x73C 0.--7. 1. "BLUE,Blue" line.long 0x740 "DMA2D_BGCLUT208,DMA2D background CLUT" hexmask.long.byte 0x740 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x740 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x740 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x740 0.--7. 1. "BLUE,Blue" line.long 0x744 "DMA2D_BGCLUT209,DMA2D background CLUT" hexmask.long.byte 0x744 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x744 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x744 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x744 0.--7. 1. "BLUE,Blue" line.long 0x748 "DMA2D_BGCLUT210,DMA2D background CLUT" hexmask.long.byte 0x748 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x748 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x748 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x748 0.--7. 1. "BLUE,Blue" line.long 0x74C "DMA2D_BGCLUT211,DMA2D background CLUT" hexmask.long.byte 0x74C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x74C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x74C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x74C 0.--7. 1. "BLUE,Blue" line.long 0x750 "DMA2D_BGCLUT212,DMA2D background CLUT" hexmask.long.byte 0x750 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x750 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x750 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x750 0.--7. 1. "BLUE,Blue" line.long 0x754 "DMA2D_BGCLUT213,DMA2D background CLUT" hexmask.long.byte 0x754 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x754 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x754 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x754 0.--7. 1. "BLUE,Blue" line.long 0x758 "DMA2D_BGCLUT214,DMA2D background CLUT" hexmask.long.byte 0x758 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x758 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x758 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x758 0.--7. 1. "BLUE,Blue" line.long 0x75C "DMA2D_BGCLUT215,DMA2D background CLUT" hexmask.long.byte 0x75C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x75C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x75C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x75C 0.--7. 1. "BLUE,Blue" line.long 0x760 "DMA2D_BGCLUT216,DMA2D background CLUT" hexmask.long.byte 0x760 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x760 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x760 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x760 0.--7. 1. "BLUE,Blue" line.long 0x764 "DMA2D_BGCLUT217,DMA2D background CLUT" hexmask.long.byte 0x764 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x764 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x764 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x764 0.--7. 1. "BLUE,Blue" line.long 0x768 "DMA2D_BGCLUT218,DMA2D background CLUT" hexmask.long.byte 0x768 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x768 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x768 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x768 0.--7. 1. "BLUE,Blue" line.long 0x76C "DMA2D_BGCLUT219,DMA2D background CLUT" hexmask.long.byte 0x76C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x76C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x76C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x76C 0.--7. 1. "BLUE,Blue" line.long 0x770 "DMA2D_BGCLUT220,DMA2D background CLUT" hexmask.long.byte 0x770 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x770 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x770 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x770 0.--7. 1. "BLUE,Blue" line.long 0x774 "DMA2D_BGCLUT221,DMA2D background CLUT" hexmask.long.byte 0x774 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x774 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x774 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x774 0.--7. 1. "BLUE,Blue" line.long 0x778 "DMA2D_BGCLUT222,DMA2D background CLUT" hexmask.long.byte 0x778 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x778 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x778 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x778 0.--7. 1. "BLUE,Blue" line.long 0x77C "DMA2D_BGCLUT223,DMA2D background CLUT" hexmask.long.byte 0x77C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x77C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x77C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x77C 0.--7. 1. "BLUE,Blue" line.long 0x780 "DMA2D_BGCLUT224,DMA2D background CLUT" hexmask.long.byte 0x780 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x780 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x780 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x780 0.--7. 1. "BLUE,Blue" line.long 0x784 "DMA2D_BGCLUT225,DMA2D background CLUT" hexmask.long.byte 0x784 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x784 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x784 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x784 0.--7. 1. "BLUE,Blue" line.long 0x788 "DMA2D_BGCLUT226,DMA2D background CLUT" hexmask.long.byte 0x788 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x788 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x788 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x788 0.--7. 1. "BLUE,Blue" line.long 0x78C "DMA2D_BGCLUT227,DMA2D background CLUT" hexmask.long.byte 0x78C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x78C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x78C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x78C 0.--7. 1. "BLUE,Blue" line.long 0x790 "DMA2D_BGCLUT228,DMA2D background CLUT" hexmask.long.byte 0x790 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x790 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x790 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x790 0.--7. 1. "BLUE,Blue" line.long 0x794 "DMA2D_BGCLUT229,DMA2D background CLUT" hexmask.long.byte 0x794 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x794 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x794 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x794 0.--7. 1. "BLUE,Blue" line.long 0x798 "DMA2D_BGCLUT230,DMA2D background CLUT" hexmask.long.byte 0x798 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x798 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x798 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x798 0.--7. 1. "BLUE,Blue" line.long 0x79C "DMA2D_BGCLUT231,DMA2D background CLUT" hexmask.long.byte 0x79C 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x79C 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x79C 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x79C 0.--7. 1. "BLUE,Blue" line.long 0x7A0 "DMA2D_BGCLUT232,DMA2D background CLUT" hexmask.long.byte 0x7A0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7A0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7A0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7A0 0.--7. 1. "BLUE,Blue" line.long 0x7A4 "DMA2D_BGCLUT233,DMA2D background CLUT" hexmask.long.byte 0x7A4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7A4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7A4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7A4 0.--7. 1. "BLUE,Blue" line.long 0x7A8 "DMA2D_BGCLUT234,DMA2D background CLUT" hexmask.long.byte 0x7A8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7A8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7A8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7A8 0.--7. 1. "BLUE,Blue" line.long 0x7AC "DMA2D_BGCLUT235,DMA2D background CLUT" hexmask.long.byte 0x7AC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7AC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7AC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7AC 0.--7. 1. "BLUE,Blue" line.long 0x7B0 "DMA2D_BGCLUT236,DMA2D background CLUT" hexmask.long.byte 0x7B0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7B0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7B0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7B0 0.--7. 1. "BLUE,Blue" line.long 0x7B4 "DMA2D_BGCLUT237,DMA2D background CLUT" hexmask.long.byte 0x7B4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7B4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7B4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7B4 0.--7. 1. "BLUE,Blue" line.long 0x7B8 "DMA2D_BGCLUT238,DMA2D background CLUT" hexmask.long.byte 0x7B8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7B8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7B8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7B8 0.--7. 1. "BLUE,Blue" line.long 0x7BC "DMA2D_BGCLUT239,DMA2D background CLUT" hexmask.long.byte 0x7BC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7BC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7BC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7BC 0.--7. 1. "BLUE,Blue" line.long 0x7C0 "DMA2D_BGCLUT240,DMA2D background CLUT" hexmask.long.byte 0x7C0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7C0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7C0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7C0 0.--7. 1. "BLUE,Blue" line.long 0x7C4 "DMA2D_BGCLUT241,DMA2D background CLUT" hexmask.long.byte 0x7C4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7C4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7C4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7C4 0.--7. 1. "BLUE,Blue" line.long 0x7C8 "DMA2D_BGCLUT242,DMA2D background CLUT" hexmask.long.byte 0x7C8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7C8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7C8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7C8 0.--7. 1. "BLUE,Blue" line.long 0x7CC "DMA2D_BGCLUT243,DMA2D background CLUT" hexmask.long.byte 0x7CC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7CC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7CC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7CC 0.--7. 1. "BLUE,Blue" line.long 0x7D0 "DMA2D_BGCLUT244,DMA2D background CLUT" hexmask.long.byte 0x7D0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7D0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7D0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7D0 0.--7. 1. "BLUE,Blue" line.long 0x7D4 "DMA2D_BGCLUT245,DMA2D background CLUT" hexmask.long.byte 0x7D4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7D4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7D4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7D4 0.--7. 1. "BLUE,Blue" line.long 0x7D8 "DMA2D_BGCLUT246,DMA2D background CLUT" hexmask.long.byte 0x7D8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7D8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7D8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7D8 0.--7. 1. "BLUE,Blue" line.long 0x7DC "DMA2D_BGCLUT247,DMA2D background CLUT" hexmask.long.byte 0x7DC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7DC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7DC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7DC 0.--7. 1. "BLUE,Blue" line.long 0x7E0 "DMA2D_BGCLUT248,DMA2D background CLUT" hexmask.long.byte 0x7E0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7E0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7E0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7E0 0.--7. 1. "BLUE,Blue" line.long 0x7E4 "DMA2D_BGCLUT249,DMA2D background CLUT" hexmask.long.byte 0x7E4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7E4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7E4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7E4 0.--7. 1. "BLUE,Blue" line.long 0x7E8 "DMA2D_BGCLUT250,DMA2D background CLUT" hexmask.long.byte 0x7E8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7E8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7E8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7E8 0.--7. 1. "BLUE,Blue" line.long 0x7EC "DMA2D_BGCLUT251,DMA2D background CLUT" hexmask.long.byte 0x7EC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7EC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7EC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7EC 0.--7. 1. "BLUE,Blue" line.long 0x7F0 "DMA2D_BGCLUT252,DMA2D background CLUT" hexmask.long.byte 0x7F0 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7F0 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7F0 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7F0 0.--7. 1. "BLUE,Blue" line.long 0x7F4 "DMA2D_BGCLUT253,DMA2D background CLUT" hexmask.long.byte 0x7F4 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7F4 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7F4 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7F4 0.--7. 1. "BLUE,Blue" line.long 0x7F8 "DMA2D_BGCLUT254,DMA2D background CLUT" hexmask.long.byte 0x7F8 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7F8 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7F8 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7F8 0.--7. 1. "BLUE,Blue" line.long 0x7FC "DMA2D_BGCLUT255,DMA2D background CLUT" hexmask.long.byte 0x7FC 24.--31. 1. "ALPHA,Alpha" hexmask.long.byte 0x7FC 16.--23. 1. "RED,Red" newline hexmask.long.byte 0x7FC 8.--15. 1. "GREEN,Green" hexmask.long.byte 0x7FC 0.--7. 1. "BLUE,Blue" tree.end tree.end tree "DTS (Digital Temperature Sensor)" base ad:0x0 tree "DTS" base ad:0x4600A000 group.long 0x10++0x3 line.long 0x0 "DTS_PVTREG_LOCKR,DTS PVT register lock register" hexmask.long 0x0 0.--31. 1. "LOCK,PVT software lock register" rgroup.long 0x14++0x3 line.long 0x0 "DTS_PVTLOCK_SR,DTS PVT lock status register" bitfld.long 0x0 1. "HW_LOCK_STATUS,Hardware lock input status" "0,1" newline bitfld.long 0x0 0. "SW_LOCK_STATUS,Software lock input status" "0,1" group.long 0x20++0x3 line.long 0x0 "DTS_PVTTMR_CR,DTS PVT timer control register" bitfld.long 0x0 16. "TMR_RUN,Timer count enable bit" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "TMR_DELAY,Timer delay" rgroup.long 0x24++0x3 line.long 0x0 "DTS_PVTTMR_SR,DTS PVT timer status register" bitfld.long 0x0 1. "TMR_DONE,Counter delay expiration flag" "0,1" newline bitfld.long 0x0 0. "TMR_BUSY,Counter busy flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DTS_PVT_IER,DTS PVT IRQ enable register" bitfld.long 0x0 1. "TS_IRQ_ENABLE,TS IRQ source enable bit" "0,1" newline bitfld.long 0x0 0. "TMR_IRQ_ENABLE,Timer IRQ source enable bit" "0,1" group.long 0x50++0x7 line.long 0x0 "DTS_PVTIRQTRMASKR,DTS PVT IRQ timer mask register" bitfld.long 0x0 0. "TMR_IRQ_MASK,Timer IRQ source mask bit" "0,1" line.long 0x4 "DTS_TS_MR,DTS PVT IRQ TS mask register" bitfld.long 0x4 1. "TS1_IRQ_MASK,TS1 IRQ source mask bit" "0,1" newline bitfld.long 0x4 0. "TS0_IRQ_MASK,TS0 IRQ source mask bit" "0,1" rgroup.long 0x60++0x7 line.long 0x0 "DTS_PVTTR_SR,DTS PVT IRQ timer status register" bitfld.long 0x0 0. "TMR_IRQ_STATUS,Timer IRQ status bit after masking" "0,1" line.long 0x4 "DTS_TS_ISR,DTS PVT IRQ TS status register" bitfld.long 0x4 1. "TS1_IRQ_STATUS,TS1 IRQ status bit after masking" "0,1" newline bitfld.long 0x4 0. "TS0_IRQ_STATUS,TS0 IRQ status bit after masking" "0,1" rgroup.long 0x70++0x7 line.long 0x0 "DTS_PVTTMRRAW_ISR,DTS PVT IRQ timer raw status register" bitfld.long 0x0 0. "TMR_IRQ_RAW_STATUS,TMR IRQ status bit before masking" "0,1" line.long 0x4 "DTS_TSRAW_ISR,DTS PVT IRQ TS raw status register" bitfld.long 0x4 1. "TS1_IRQ_RAW_STATUS,TS1 IRQ status bit before masking" "0,1" newline bitfld.long 0x4 0. "TS0_IRQ_RAW_STATUS,TS0 IRQ status bit before masking" "0,1" group.long 0x80++0x7 line.long 0x0 "DTS_TSCCLKSYNTHR,DTS TSC clock synthesizer register" bitfld.long 0x0 24. "CLK_SYTH_EN,Synthesized clk_ts enable bit" "0: Disabled,1: Enabled" newline hexmask.long.byte 0x0 16.--19. 1. "CLK_SYNTH_HOLD,SDA master-to-SDA slave output hold delay/SDA slave-to-SDA master input setup delay" newline hexmask.long.byte 0x0 8.--15. 1. "CLK_SYNTH_HI,Synthesized clk_ts high period" newline hexmask.long.byte 0x0 0.--7. 1. "CLK_SYNTH_LO,Synthesized clk_ts low period" line.long 0x4 "DTS_TSCSDIFDISABLER,DTS TSC SDIF interface disable register" bitfld.long 0x4 1. "TS1_SDIF_DISABLE,TS1 serial data interface (SDIF) disable bit" "0: Enabled,1: Disabled" newline bitfld.long 0x4 0. "TS0_SDIF_DISABLE,TS0 serial data interface (SDIF) disable bit" "0: Enabled,1: Disabled" rgroup.long 0x88++0x3 line.long 0x0 "DTS_TSCSDIF_SR,DTS TSC SDIF status register" bitfld.long 0x0 1. "SDIF_LOCK,SDIF locked flag" "0: Unlocked,1: Locked" newline bitfld.long 0x0 0. "SDIF_BUSY,SDIF busy flag" "0: SDIF not busy/no clock synthesizer/disable SDIF..,1: SDIF busy/clock synthesizer/disable SDIF state.." group.long 0x8C++0x3 line.long 0x0 "DTS_TSCSDIF_CR,DTS TSC SDIF register" bitfld.long 0x0 31. "SDIF_PROG,Serial interface program request" "0: No SDIF program request,1: SDIF program requested" newline bitfld.long 0x0 27. "SDIF_WRN,Serial interface write/no read control bit" "0: SDIF read,1: SDIF write" newline bitfld.long 0x0 24.--26. "SDIF_ADDR,Serial interface register address" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x0 0.--23. 1. "SDIF_WDATA,Serial interface write data" wgroup.long 0x90++0x3 line.long 0x0 "DTS_TSCSDIFHALTR,DTS TSC SDIF halt register" bitfld.long 0x0 0. "SDIF_STOP,Serial data interface (SDIF) stop" "0: Not stopped,1: Stopped" group.long 0x94++0x3 line.long 0x0 "DTS_TSCSDIF_CFGR,DTS TSC SDIF control register" bitfld.long 0x0 0.--1. "SDIF_INHIBIT,Serial data interface (SDIF) programming inhibit" "0: No Inhibition,1: TS0 inhibited/TS1 serial programming activated..,2: TS1 inhibited/TS0 serial programming activated..,3: TS1 and TS0 inhibited" group.long 0xA0++0x3 line.long 0x0 "DTS_TSCSMPL_CR,DTS TSC sample control register" bitfld.long 0x0 2. "SMPL_DISCARD,Sample discard bit" "0: Data samples not discarded,1: Data samples discarded" newline bitfld.long 0x0 1. "SMPL_CTR_HOLD,Sample counter hold bit" "0: Counter not on hold,1: Counter on hold" newline bitfld.long 0x0 0. "SMPL_CTR_DISABLE,Sample counter disable bit" "0: Sample counter enabled,1: Sample counter disabled" wgroup.long 0xA4++0x3 line.long 0x0 "DTS_TSCSDIFSMPLCLRR,DTS TSC sample clear register" bitfld.long 0x0 0. "SMPL_CNTER_CLEAR,Sample counter clear bit" "0: Counter value not cleared,1: Counter value cleared" rgroup.long 0xA8++0x3 line.long 0x0 "DTS_TSCSMPLCNTR,DTS TSC sample count register" hexmask.long.word 0x0 0.--15. 1. "SMPL_COUNT,Sample counter" group.long 0xC0++0x3 line.long 0x0 "DTS_TS0_IER,DTS TS0 IRQ enable register" bitfld.long 0x0 4. "IRQ_EN_ALARMB,Alarm B IRQ enable bit" "0,1" newline bitfld.long 0x0 3. "IRQ_EN_ALARMA,Alarm A IRQ enable bit" "0,1" newline bitfld.long 0x0 1. "IRQ_EN_DONE,Sample done IRQ enable bit" "0,1" newline bitfld.long 0x0 0. "IRQ_EN_FAULT,Fault IRQ enable bit" "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "DTS_TS0_ISR,DTS TS0 IRQ status register" bitfld.long 0x0 4. "IRQ_STATUS_ALARMB,Alarm B IRQ status bit" "0,1" newline bitfld.long 0x0 3. "IRQ_STATUS_ALARMA,Alarm A IRQ status bit" "0,1" newline bitfld.long 0x0 1. "IRQ_STATUS_DONE,Sample done IRQ status bit" "0,1" newline bitfld.long 0x0 0. "IRQ_STATUS_FAULT,Fault IRQ status bit" "0,1" wgroup.long 0xC8++0x3 line.long 0x0 "DTS_TS0_ICR,DTS TS0 IRQ clear register" bitfld.long 0x0 4. "IRQ_CLEAR_ALARMB,Alarm B IRQ clear bit" "0,1" newline bitfld.long 0x0 3. "IRQ_CLEAR_ALARMA,Alarm A IRQ clear bit" "0,1" newline bitfld.long 0x0 1. "IRQ_CLEAR_DONE,Sample done IRQ clear bit" "0,1" newline bitfld.long 0x0 0. "IRQ_CLEAR_FAULT,Fault IRQ clear bit" "0,1" group.long 0xCC++0x3 line.long 0x0 "DTS_TS0IRQTESTR,DTS TS0 IRQ test register" bitfld.long 0x0 4. "IRQ_TEST_ALARMB,Alarm B IRQ test bit" "0,1" newline bitfld.long 0x0 3. "IRQ_TEST_ALARMA,Alarm A IRQ test bit" "0,1" newline bitfld.long 0x0 1. "IRQ_TEST_DONE,Sample done IRQ test bit" "0,1" newline bitfld.long 0x0 0. "IRQ_TEST_FAULT,Fault IRQ test bit" "0,1" rgroup.long 0xD0++0xB line.long 0x0 "DTS_TS0SDIFRDATAR,DTS TS0 SDIF RDATA register" hexmask.long.tbyte 0x0 0.--23. 1. "SDIF_RDATA,SDIF read data" line.long 0x4 "DTS_TS0SDIFDONER,DTS TS0 SDIF done register" bitfld.long 0x4 0. "SDIF_SMPL_DONE,Sample done flag" "0: No new data sample available,1: New data sample available" line.long 0x8 "DTS_TS0SDIFDATAR,DTS TS0 SDIF data register" bitfld.long 0x8 17. "SAMPLE_FAULT,Sample fault" "0,1" newline bitfld.long 0x8 16. "SAMPLE_TYPE,TS sample type" "0: Indicates valid data,1: Indicates either analog access signature select.." newline hexmask.long.word 0x8 0.--15. 1. "SAMPLE_DATA,Sample data." group.long 0xE0++0x7 line.long 0x0 "DTS_TS0ALARMA_CFGR,DTS TS0 alarm A configuration register" hexmask.long.word 0x0 16.--31. 1. "ALARMA_THRESH,Alarm A threshold" newline hexmask.long.word 0x0 0.--15. 1. "HYSTA_THRESH,Alarm A hysteresis threshold" line.long 0x4 "DTS_TS0ALARMB_CFGR,DTS TS0 alarm B configuration register" hexmask.long.word 0x4 16.--31. 1. "ALARMB_THRESH,Alarm B threshold" newline hexmask.long.word 0x4 0.--15. 1. "HYSTB_THRESH,Alarm B hysteresis threshold" rgroup.long 0xE8++0x3 line.long 0x0 "DTS_TS0HLSAMPLER,DTS TS0 high/low sample register" hexmask.long.word 0x0 16.--31. 1. "SMPL_HI,Highest valid data sample value received" newline hexmask.long.word 0x0 0.--15. 1. "SMPL_LO,Lowest valid data sample value received" wgroup.long 0xEC++0x3 line.long 0x0 "DTS_TS0HILORESETR,DTS TS0 high/low reset register" bitfld.long 0x0 1. "SMPL_HI_CLR,Sample high clear 0" "0,1" newline bitfld.long 0x0 0. "SMPL_LO_SET,Sample Low Set" "0,1" group.long 0x100++0x3 line.long 0x0 "DTS_TS1_IER,DTS TS1 IRQ enable register" bitfld.long 0x0 4. "IRQ_EN_ALARMB,Alarm B IRQ enable bit" "0,1" newline bitfld.long 0x0 3. "IRQ_EN_ALARMA,Alarm A IRQ enable bit" "0,1" newline bitfld.long 0x0 1. "IRQ_EN_DONE,Sample done IRQ enable bit" "0,1" newline bitfld.long 0x0 0. "IRQ_EN_FAULT,Fault IRQ enable bit" "0,1" rgroup.long 0x104++0x3 line.long 0x0 "DTS_TS1_ISR,DTS TS1 IRQ status register" bitfld.long 0x0 4. "IRQ_STATUS_ALARMB,Alarm B IRQ status bit" "0,1" newline bitfld.long 0x0 3. "IRQ_STATUS_ALARMA,Alarm A IRQ status bit" "0,1" newline bitfld.long 0x0 1. "IRQ_STATUS_DONE,Sample done IRQ status bit" "0,1" newline bitfld.long 0x0 0. "IRQ_STATUS_FAULT,Fault IRQ status bit" "0,1" wgroup.long 0x108++0x3 line.long 0x0 "DTS_TS1_ICR,DTS TS1 IRQ clear register" bitfld.long 0x0 4. "IRQ_CLEAR_ALARMB,Alarm B IRQ clear bit" "0,1" newline bitfld.long 0x0 3. "IRQ_CLEAR_ALARMA,Alarm A IRQ clear bit" "0,1" newline bitfld.long 0x0 1. "IRQ_CLEAR_DONE,Sample done IRQ clear bit" "0,1" newline bitfld.long 0x0 0. "IRQ_CLEAR_FAULT,Fault IRQ clear bit" "0,1" group.long 0x10C++0x3 line.long 0x0 "DTS_TS1IRQTESTR,DTS TS1 IRQ test register" bitfld.long 0x0 4. "IRQ_TEST_ALARMB,Alarm B IRQ test bit" "0,1" newline bitfld.long 0x0 3. "IRQ_TEST_ALARMA,Alarm A IRQ test bit" "0,1" newline bitfld.long 0x0 1. "IRQ_TEST_DONE,Sample done IRQ test bit" "0,1" newline bitfld.long 0x0 0. "IRQ_TEST_FAULT,Fault IRQ test bit" "0,1" rgroup.long 0x110++0xB line.long 0x0 "DTS_TS1SDIFRDATAR,DTS TS1 SDIF RDATA register" hexmask.long.tbyte 0x0 0.--23. 1. "SDIF_RDATA,SDIF read data" line.long 0x4 "DTS_TS1SDIFDONER,DTS TS1 SDIF done register" bitfld.long 0x4 0. "SDIF_SMPL_DONE,Sample done flag" "0: No new data sample available,1: New data sample available" line.long 0x8 "DTS_TS1SDIFDATAR,DTS TS1 SDIF data register" bitfld.long 0x8 17. "SAMPLE_FAULT,Sample fault" "0,1" newline bitfld.long 0x8 16. "SAMPLE_TYPE,TS sample type" "0: Indicates valid data,1: Indicates either analog access signature select.." newline hexmask.long.word 0x8 0.--15. 1. "SAMPLE_DATA,Sample data." group.long 0x120++0x7 line.long 0x0 "DTS_TS1ALARMA_CFGR,DTS TS1 alarm A configuration register" hexmask.long.word 0x0 16.--31. 1. "ALARMA_THRESH,Alarm A threshold" newline hexmask.long.word 0x0 0.--15. 1. "HYSTA_THRESH,Alarm A hysteresis threshold" line.long 0x4 "DTS_TS1ALARMB_CFGR,DTS TS1 alarm B configuration register" hexmask.long.word 0x4 16.--31. 1. "ALARMB_THRESH,Alarm B threshold" newline hexmask.long.word 0x4 0.--15. 1. "HYSTB_THRESH,Alarm B hysteresis threshold" rgroup.long 0x128++0x3 line.long 0x0 "DTS_TS1HLSAMPLER,DTS TS1 high/low sample register" hexmask.long.word 0x0 16.--31. 1. "SMPL_HI,Highest valid data sample value received" newline hexmask.long.word 0x0 0.--15. 1. "SMPL_LO,Lowest valid data sample value received" wgroup.long 0x12C++0x3 line.long 0x0 "DTS_TS1HILORESETR,DTS TS1 high/low reset register" bitfld.long 0x0 1. "SMPL_HI_CLR,Sample high clear 0" "0,1" newline bitfld.long 0x0 0. "SMPL_LO_SET,Sample Low Set" "0,1" tree.end tree "DTS_S" base ad:0x5600A000 group.long 0x10++0x3 line.long 0x0 "DTS_PVTREG_LOCKR,DTS PVT register lock register" hexmask.long 0x0 0.--31. 1. "LOCK,PVT software lock register" rgroup.long 0x14++0x3 line.long 0x0 "DTS_PVTLOCK_SR,DTS PVT lock status register" bitfld.long 0x0 1. "HW_LOCK_STATUS,Hardware lock input status" "0,1" newline bitfld.long 0x0 0. "SW_LOCK_STATUS,Software lock input status" "0,1" group.long 0x20++0x3 line.long 0x0 "DTS_PVTTMR_CR,DTS PVT timer control register" bitfld.long 0x0 16. "TMR_RUN,Timer count enable bit" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "TMR_DELAY,Timer delay" rgroup.long 0x24++0x3 line.long 0x0 "DTS_PVTTMR_SR,DTS PVT timer status register" bitfld.long 0x0 1. "TMR_DONE,Counter delay expiration flag" "0,1" newline bitfld.long 0x0 0. "TMR_BUSY,Counter busy flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DTS_PVT_IER,DTS PVT IRQ enable register" bitfld.long 0x0 1. "TS_IRQ_ENABLE,TS IRQ source enable bit" "0,1" newline bitfld.long 0x0 0. "TMR_IRQ_ENABLE,Timer IRQ source enable bit" "0,1" group.long 0x50++0x7 line.long 0x0 "DTS_PVTIRQTRMASKR,DTS PVT IRQ timer mask register" bitfld.long 0x0 0. "TMR_IRQ_MASK,Timer IRQ source mask bit" "0,1" line.long 0x4 "DTS_TS_MR,DTS PVT IRQ TS mask register" bitfld.long 0x4 1. "TS1_IRQ_MASK,TS1 IRQ source mask bit" "0,1" newline bitfld.long 0x4 0. "TS0_IRQ_MASK,TS0 IRQ source mask bit" "0,1" rgroup.long 0x60++0x7 line.long 0x0 "DTS_PVTTR_SR,DTS PVT IRQ timer status register" bitfld.long 0x0 0. "TMR_IRQ_STATUS,Timer IRQ status bit after masking" "0,1" line.long 0x4 "DTS_TS_ISR,DTS PVT IRQ TS status register" bitfld.long 0x4 1. "TS1_IRQ_STATUS,TS1 IRQ status bit after masking" "0,1" newline bitfld.long 0x4 0. "TS0_IRQ_STATUS,TS0 IRQ status bit after masking" "0,1" rgroup.long 0x70++0x7 line.long 0x0 "DTS_PVTTMRRAW_ISR,DTS PVT IRQ timer raw status register" bitfld.long 0x0 0. "TMR_IRQ_RAW_STATUS,TMR IRQ status bit before masking" "0,1" line.long 0x4 "DTS_TSRAW_ISR,DTS PVT IRQ TS raw status register" bitfld.long 0x4 1. "TS1_IRQ_RAW_STATUS,TS1 IRQ status bit before masking" "0,1" newline bitfld.long 0x4 0. "TS0_IRQ_RAW_STATUS,TS0 IRQ status bit before masking" "0,1" group.long 0x80++0x7 line.long 0x0 "DTS_TSCCLKSYNTHR,DTS TSC clock synthesizer register" bitfld.long 0x0 24. "CLK_SYTH_EN,Synthesized clk_ts enable bit" "0: Disabled,1: Enabled" newline hexmask.long.byte 0x0 16.--19. 1. "CLK_SYNTH_HOLD,SDA master-to-SDA slave output hold delay/SDA slave-to-SDA master input setup delay" newline hexmask.long.byte 0x0 8.--15. 1. "CLK_SYNTH_HI,Synthesized clk_ts high period" newline hexmask.long.byte 0x0 0.--7. 1. "CLK_SYNTH_LO,Synthesized clk_ts low period" line.long 0x4 "DTS_TSCSDIFDISABLER,DTS TSC SDIF interface disable register" bitfld.long 0x4 1. "TS1_SDIF_DISABLE,TS1 serial data interface (SDIF) disable bit" "0: Enabled,1: Disabled" newline bitfld.long 0x4 0. "TS0_SDIF_DISABLE,TS0 serial data interface (SDIF) disable bit" "0: Enabled,1: Disabled" rgroup.long 0x88++0x3 line.long 0x0 "DTS_TSCSDIF_SR,DTS TSC SDIF status register" bitfld.long 0x0 1. "SDIF_LOCK,SDIF locked flag" "0: Unlocked,1: Locked" newline bitfld.long 0x0 0. "SDIF_BUSY,SDIF busy flag" "0: SDIF not busy/no clock synthesizer/disable SDIF..,1: SDIF busy/clock synthesizer/disable SDIF state.." group.long 0x8C++0x3 line.long 0x0 "DTS_TSCSDIF_CR,DTS TSC SDIF register" bitfld.long 0x0 31. "SDIF_PROG,Serial interface program request" "0: No SDIF program request,1: SDIF program requested" newline bitfld.long 0x0 27. "SDIF_WRN,Serial interface write/no read control bit" "0: SDIF read,1: SDIF write" newline bitfld.long 0x0 24.--26. "SDIF_ADDR,Serial interface register address" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x0 0.--23. 1. "SDIF_WDATA,Serial interface write data" wgroup.long 0x90++0x3 line.long 0x0 "DTS_TSCSDIFHALTR,DTS TSC SDIF halt register" bitfld.long 0x0 0. "SDIF_STOP,Serial data interface (SDIF) stop" "0: Not stopped,1: Stopped" group.long 0x94++0x3 line.long 0x0 "DTS_TSCSDIF_CFGR,DTS TSC SDIF control register" bitfld.long 0x0 0.--1. "SDIF_INHIBIT,Serial data interface (SDIF) programming inhibit" "0: No Inhibition,1: TS0 inhibited/TS1 serial programming activated..,2: TS1 inhibited/TS0 serial programming activated..,3: TS1 and TS0 inhibited" group.long 0xA0++0x3 line.long 0x0 "DTS_TSCSMPL_CR,DTS TSC sample control register" bitfld.long 0x0 2. "SMPL_DISCARD,Sample discard bit" "0: Data samples not discarded,1: Data samples discarded" newline bitfld.long 0x0 1. "SMPL_CTR_HOLD,Sample counter hold bit" "0: Counter not on hold,1: Counter on hold" newline bitfld.long 0x0 0. "SMPL_CTR_DISABLE,Sample counter disable bit" "0: Sample counter enabled,1: Sample counter disabled" wgroup.long 0xA4++0x3 line.long 0x0 "DTS_TSCSDIFSMPLCLRR,DTS TSC sample clear register" bitfld.long 0x0 0. "SMPL_CNTER_CLEAR,Sample counter clear bit" "0: Counter value not cleared,1: Counter value cleared" rgroup.long 0xA8++0x3 line.long 0x0 "DTS_TSCSMPLCNTR,DTS TSC sample count register" hexmask.long.word 0x0 0.--15. 1. "SMPL_COUNT,Sample counter" group.long 0xC0++0x3 line.long 0x0 "DTS_TS0_IER,DTS TS0 IRQ enable register" bitfld.long 0x0 4. "IRQ_EN_ALARMB,Alarm B IRQ enable bit" "0,1" newline bitfld.long 0x0 3. "IRQ_EN_ALARMA,Alarm A IRQ enable bit" "0,1" newline bitfld.long 0x0 1. "IRQ_EN_DONE,Sample done IRQ enable bit" "0,1" newline bitfld.long 0x0 0. "IRQ_EN_FAULT,Fault IRQ enable bit" "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "DTS_TS0_ISR,DTS TS0 IRQ status register" bitfld.long 0x0 4. "IRQ_STATUS_ALARMB,Alarm B IRQ status bit" "0,1" newline bitfld.long 0x0 3. "IRQ_STATUS_ALARMA,Alarm A IRQ status bit" "0,1" newline bitfld.long 0x0 1. "IRQ_STATUS_DONE,Sample done IRQ status bit" "0,1" newline bitfld.long 0x0 0. "IRQ_STATUS_FAULT,Fault IRQ status bit" "0,1" wgroup.long 0xC8++0x3 line.long 0x0 "DTS_TS0_ICR,DTS TS0 IRQ clear register" bitfld.long 0x0 4. "IRQ_CLEAR_ALARMB,Alarm B IRQ clear bit" "0,1" newline bitfld.long 0x0 3. "IRQ_CLEAR_ALARMA,Alarm A IRQ clear bit" "0,1" newline bitfld.long 0x0 1. "IRQ_CLEAR_DONE,Sample done IRQ clear bit" "0,1" newline bitfld.long 0x0 0. "IRQ_CLEAR_FAULT,Fault IRQ clear bit" "0,1" group.long 0xCC++0x3 line.long 0x0 "DTS_TS0IRQTESTR,DTS TS0 IRQ test register" bitfld.long 0x0 4. "IRQ_TEST_ALARMB,Alarm B IRQ test bit" "0,1" newline bitfld.long 0x0 3. "IRQ_TEST_ALARMA,Alarm A IRQ test bit" "0,1" newline bitfld.long 0x0 1. "IRQ_TEST_DONE,Sample done IRQ test bit" "0,1" newline bitfld.long 0x0 0. "IRQ_TEST_FAULT,Fault IRQ test bit" "0,1" rgroup.long 0xD0++0xB line.long 0x0 "DTS_TS0SDIFRDATAR,DTS TS0 SDIF RDATA register" hexmask.long.tbyte 0x0 0.--23. 1. "SDIF_RDATA,SDIF read data" line.long 0x4 "DTS_TS0SDIFDONER,DTS TS0 SDIF done register" bitfld.long 0x4 0. "SDIF_SMPL_DONE,Sample done flag" "0: No new data sample available,1: New data sample available" line.long 0x8 "DTS_TS0SDIFDATAR,DTS TS0 SDIF data register" bitfld.long 0x8 17. "SAMPLE_FAULT,Sample fault" "0,1" newline bitfld.long 0x8 16. "SAMPLE_TYPE,TS sample type" "0: Indicates valid data,1: Indicates either analog access signature select.." newline hexmask.long.word 0x8 0.--15. 1. "SAMPLE_DATA,Sample data." group.long 0xE0++0x7 line.long 0x0 "DTS_TS0ALARMA_CFGR,DTS TS0 alarm A configuration register" hexmask.long.word 0x0 16.--31. 1. "ALARMA_THRESH,Alarm A threshold" newline hexmask.long.word 0x0 0.--15. 1. "HYSTA_THRESH,Alarm A hysteresis threshold" line.long 0x4 "DTS_TS0ALARMB_CFGR,DTS TS0 alarm B configuration register" hexmask.long.word 0x4 16.--31. 1. "ALARMB_THRESH,Alarm B threshold" newline hexmask.long.word 0x4 0.--15. 1. "HYSTB_THRESH,Alarm B hysteresis threshold" rgroup.long 0xE8++0x3 line.long 0x0 "DTS_TS0HLSAMPLER,DTS TS0 high/low sample register" hexmask.long.word 0x0 16.--31. 1. "SMPL_HI,Highest valid data sample value received" newline hexmask.long.word 0x0 0.--15. 1. "SMPL_LO,Lowest valid data sample value received" wgroup.long 0xEC++0x3 line.long 0x0 "DTS_TS0HILORESETR,DTS TS0 high/low reset register" bitfld.long 0x0 1. "SMPL_HI_CLR,Sample high clear 0" "0,1" newline bitfld.long 0x0 0. "SMPL_LO_SET,Sample Low Set" "0,1" group.long 0x100++0x3 line.long 0x0 "DTS_TS1_IER,DTS TS1 IRQ enable register" bitfld.long 0x0 4. "IRQ_EN_ALARMB,Alarm B IRQ enable bit" "0,1" newline bitfld.long 0x0 3. "IRQ_EN_ALARMA,Alarm A IRQ enable bit" "0,1" newline bitfld.long 0x0 1. "IRQ_EN_DONE,Sample done IRQ enable bit" "0,1" newline bitfld.long 0x0 0. "IRQ_EN_FAULT,Fault IRQ enable bit" "0,1" rgroup.long 0x104++0x3 line.long 0x0 "DTS_TS1_ISR,DTS TS1 IRQ status register" bitfld.long 0x0 4. "IRQ_STATUS_ALARMB,Alarm B IRQ status bit" "0,1" newline bitfld.long 0x0 3. "IRQ_STATUS_ALARMA,Alarm A IRQ status bit" "0,1" newline bitfld.long 0x0 1. "IRQ_STATUS_DONE,Sample done IRQ status bit" "0,1" newline bitfld.long 0x0 0. "IRQ_STATUS_FAULT,Fault IRQ status bit" "0,1" wgroup.long 0x108++0x3 line.long 0x0 "DTS_TS1_ICR,DTS TS1 IRQ clear register" bitfld.long 0x0 4. "IRQ_CLEAR_ALARMB,Alarm B IRQ clear bit" "0,1" newline bitfld.long 0x0 3. "IRQ_CLEAR_ALARMA,Alarm A IRQ clear bit" "0,1" newline bitfld.long 0x0 1. "IRQ_CLEAR_DONE,Sample done IRQ clear bit" "0,1" newline bitfld.long 0x0 0. "IRQ_CLEAR_FAULT,Fault IRQ clear bit" "0,1" group.long 0x10C++0x3 line.long 0x0 "DTS_TS1IRQTESTR,DTS TS1 IRQ test register" bitfld.long 0x0 4. "IRQ_TEST_ALARMB,Alarm B IRQ test bit" "0,1" newline bitfld.long 0x0 3. "IRQ_TEST_ALARMA,Alarm A IRQ test bit" "0,1" newline bitfld.long 0x0 1. "IRQ_TEST_DONE,Sample done IRQ test bit" "0,1" newline bitfld.long 0x0 0. "IRQ_TEST_FAULT,Fault IRQ test bit" "0,1" rgroup.long 0x110++0xB line.long 0x0 "DTS_TS1SDIFRDATAR,DTS TS1 SDIF RDATA register" hexmask.long.tbyte 0x0 0.--23. 1. "SDIF_RDATA,SDIF read data" line.long 0x4 "DTS_TS1SDIFDONER,DTS TS1 SDIF done register" bitfld.long 0x4 0. "SDIF_SMPL_DONE,Sample done flag" "0: No new data sample available,1: New data sample available" line.long 0x8 "DTS_TS1SDIFDATAR,DTS TS1 SDIF data register" bitfld.long 0x8 17. "SAMPLE_FAULT,Sample fault" "0,1" newline bitfld.long 0x8 16. "SAMPLE_TYPE,TS sample type" "0: Indicates valid data,1: Indicates either analog access signature select.." newline hexmask.long.word 0x8 0.--15. 1. "SAMPLE_DATA,Sample data." group.long 0x120++0x7 line.long 0x0 "DTS_TS1ALARMA_CFGR,DTS TS1 alarm A configuration register" hexmask.long.word 0x0 16.--31. 1. "ALARMA_THRESH,Alarm A threshold" newline hexmask.long.word 0x0 0.--15. 1. "HYSTA_THRESH,Alarm A hysteresis threshold" line.long 0x4 "DTS_TS1ALARMB_CFGR,DTS TS1 alarm B configuration register" hexmask.long.word 0x4 16.--31. 1. "ALARMB_THRESH,Alarm B threshold" newline hexmask.long.word 0x4 0.--15. 1. "HYSTB_THRESH,Alarm B hysteresis threshold" rgroup.long 0x128++0x3 line.long 0x0 "DTS_TS1HLSAMPLER,DTS TS1 high/low sample register" hexmask.long.word 0x0 16.--31. 1. "SMPL_HI,Highest valid data sample value received" newline hexmask.long.word 0x0 0.--15. 1. "SMPL_LO,Lowest valid data sample value received" wgroup.long 0x12C++0x3 line.long 0x0 "DTS_TS1HILORESETR,DTS TS1 high/low reset register" bitfld.long 0x0 1. "SMPL_HI_CLR,Sample high clear 0" "0,1" newline bitfld.long 0x0 0. "SMPL_LO_SET,Sample Low Set" "0,1" tree.end tree.end tree "ETH (Ethernet)" base ad:0x0 tree "ETH" base ad:0x48036000 group.long 0x0++0x17 line.long 0x0 "ETH_MACCR,Operating mode configuration register" bitfld.long 0x0 31. "ARPEN,ARP Offload Enable" "0,1" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control" "?,?,2: the MAC inserts the content of the MAC Address 0..,3: the MAC replaces the content of the MAC Address..,?,?,6: the MAC inserts the content of the MAC Address 1..,7: the MAC replaces the content of the MAC Address.." newline bitfld.long 0x0 27. "IPC,Checksum Offload" "0,1" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap" "0: 96 bit times,1: 88 bit times,2: 80 bit times,?,?,?,?,7: 40 bit times" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable" "0,1" newline bitfld.long 0x0 22. "S2KP,IEEE 802.3as Support for 2K Packets" "0,1" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets" "0,1" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping" "0,1" newline bitfld.long 0x0 19. "WD,Watchdog Disable" "0,1" newline bitfld.long 0x0 18. "BE,Packet Burst Enable" "0,1" newline bitfld.long 0x0 17. "JD,Jabber Disable" "0,1" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable" "0,1" newline bitfld.long 0x0 15. "PS,Port Select" "0: For 1000 Mbps operations,1: For 10 or 100 Mbps operations" newline bitfld.long 0x0 14. "FES,MAC Speed" "0: 10 Mbps,1: 100 Mbps" newline bitfld.long 0x0 13. "DM,Duplex Mode" "0,1" newline bitfld.long 0x0 12. "LM,Loopback Mode" "0,1" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-duplex mode" "0,1" newline bitfld.long 0x0 10. "DO,Disable Receive Own" "0,1" newline bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission" "0,1" newline bitfld.long 0x0 8. "DR,Disable Retry" "0,1" newline bitfld.long 0x0 5.--6. "BL,Back-Off Limit" "0: k= min (n 10),1: k = min (n 8),2: k = min (n 4),3: k = min (n 1)" newline bitfld.long 0x0 4. "DC,Deferral Check" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,?" newline bitfld.long 0x0 1. "TE,Transmitter Enable" "0,1" newline bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "ETH_MACECR,Extended operating mode configuration register" bitfld.long 0x4 30. "APDIM,ARP Packet Drop if IP Address Mismatch" "0,1" newline hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap" newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable" "0,1" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect" "0,1" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable" "0,1" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets" "0,1" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit" line.long 0x8 "ETH_MACPFR,Packet filtering control register" bitfld.long 0x8 31. "RA,Receive All" "0,1" newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets" "0,1" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable" "0,1" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable" "0,1" newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter" "0,1" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable" "0,1" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering" "0,1" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets" "0: The MAC filters all control packets from..,1: The MAC forwards all control packets except..,2: The MAC forwards all control packets to the..,3: The MAC forwards the control packets that pass.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets" "0,1" newline bitfld.long 0x8 4. "PM,Pass All Multicast" "0,1" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering" "0,1" newline bitfld.long 0x8 2. "HMC,Hash Multicast" "0,1" newline bitfld.long 0x8 1. "HUC,Hash Unicast" "0,1" newline bitfld.long 0x8 0. "PR,Promiscuous Mode" "0,1" line.long 0xC "ETH_MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable" "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout" line.long 0x10 "ETH_MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits" line.long 0x14 "ETH_MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits" group.long 0x50++0xB line.long 0x0 "ETH_MACVTCR,VLAN tag Control register" bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status" "0,1" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag" "0,1" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing" "0,1" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable" "0,1" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status" "0,1" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match" "0,1" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN" "0,1" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable" "0,1" newline bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 2.--3. "OFS,Offset" "0: ETH_MACVTDR holds MAC VLAN Tag Filter0 content,1: ETH_MACVTDR holds MAC VLAN Tag Filter1 content,2: ETH_MACVTDR holds MAC VLAN Tag Filter2 content,3: ETH_MACVTDR holds MAC VLAN Tag Filter3 content" newline bitfld.long 0x0 1. "CT,Command Type" "0,1" newline bitfld.long 0x0 0. "OB,Operation Busy" "0,1" line.long 0x4 "ETH_MACVTDR,VLAN tag data register" bitfld.long 0x4 25. "DMACHN,DMA Channel Number" "0,1" newline bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x4 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x4 17. "ETV,12-bit or 16-bit VLAN comparison" "0: 16-bit VLAN,1: 12-bit VLAN" newline bitfld.long 0x4 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag ID" line.long 0x8 "ETH_MACVHTR,VLAN Hash table register" hexmask.long.word 0x8 0.--15. 1. "VLHT,VLAN Hash Table" group.long 0x60++0x3 line.long 0x0 "ETH_MACVIR,VLAN inclusion register" rbitfld.long 0x0 31. "BUSY,Busy" "0,1" newline bitfld.long 0x0 30. "RDWR,Read write control" "0,1" newline bitfld.long 0x0 24. "ADDR,Address" "0: VLAN tag for insertion in the Transmit packets..,1: VLAN tag for insertion in the Transmit packets.." newline bitfld.long 0x0 21. "CBTI,Channel based tag insertion" "0,1" newline bitfld.long 0x0 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0: C-LAN,1: S-LAN" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion. The MAC removes the VLAN type..,2: VLAN tag insertion. The MAC inserts VLT in bytes..,3: VLAN tag replacement. The MAC replaces VLT in.." newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x60++0x7 line.long 0x0 "ETH_MACVIR_alternate,VLAN inclusion register" bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0: C-LAN,1: S-LAN" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" line.long 0x4 "ETH_MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN" "0: C-LAN,1: S-LAN" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x70++0x3 line.long 0x0 "ETH_MACQ0TXFCR,Tx Queue 0 flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time" newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause" "0,1" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate" "0,1" group.long 0x90++0x7 line.long 0x0 "ETH_MACRXFCR,Rx flow control register" bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect" "0,1" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable" "0,1" line.long 0x4 "ETH_MACRXQCR,Rx Queue control register" bitfld.long 0x4 17. "VFFQ,VLAN Tag Filter Fail Packets Queue" "0: Queue 0,1: Queue 1" newline bitfld.long 0x4 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 9. "MFFQ,Multicast Address Filter Fail Packets Queue." "0: Queue 0,1: Queue 1" newline bitfld.long 0x4 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable." "0,1" newline bitfld.long 0x4 1. "UFFQ,Unicast Address Filter Fail Packets Queue." "0: Queue 0,1: Queue 1" newline bitfld.long 0x4 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable." "0,1" group.long 0xA0++0xB line.long 0x0 "ETH_MACRXQC0R,Rx queue control 0 register" bitfld.long 0x0 2.--3. "RXQ1EN,Receive Queue 1 Enable" "0: Not enabled,1: Queue 1 enabled for AV,2: Queue 1 enabled for Generic traffic,?" newline bitfld.long 0x0 0.--1. "RXQ0EN,Receive Queue 0 Enable" "0: Not enabled,1: Queue 0 enabled for AV,2: Queue 0 enabled for Generic traffic,?" line.long 0x4 "ETH_MACRXQC1R,Rx queue control 1 register" bitfld.long 0x4 29. "TBRQE,Type Field Based Rx Queuing Enable" "0,1" newline bitfld.long 0x4 28. "OMCBCQ,Overriding MC-BC queue priority select" "0: Received Multicast/Broadcast packet is routed to..,1: Priority of MCBCQ is reduced and the received.." newline bitfld.long 0x4 26. "FPRQ2,Frame Preemption Residue Queue" "?,1: Rx queue 1" newline bitfld.long 0x4 25. "FPRQ1,Frame Preemption Residue Queue" "?,1: Rx queue 1" newline bitfld.long 0x4 24. "FPRQ0,Frame Preemption Residue Queue" "?,1: Rx queue 1" newline bitfld.long 0x4 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control" "0: VLAN tagged PTPoE packets are routed as generic..,1: VLAN tagged PTPoE packets are routed to Rx Queue..,2: VLAN tagged PTPoE packets are routed to only AV..,?" newline bitfld.long 0x4 21. "TACPQE,Tagged AV Control Packets Queuing Enable" "0,1" newline bitfld.long 0x4 20. "MCBCQEN,Multicast and Broadcast Queue Enable" "0,1" newline bitfld.long 0x4 16.--18. "MCBCQ,Multicast and Broadcast Queue" "0: Rx queue 0,1: Rx queue 1,?,?,?,?,?,?" newline bitfld.long 0x4 12.--14. "UPQ,Untagged Packet Queue" "0: Rx queue 0,1: Rx queue 1,?,?,?,?,?,?" newline bitfld.long 0x4 4.--6. "PTPQ,PTP Packets Queue" "0: Rx queue 0,1: Rx queue 1,?,?,?,?,?,?" newline bitfld.long 0x4 2. "AVCPQ2,AV Untagged Control Packets Queue" "0: Receive Queue 0,1: Receive Queue 1" newline bitfld.long 0x4 1. "AVCPQ1,AV Untagged Control Packets Queue" "0: Receive Queue 0,1: Receive Queue 1" newline bitfld.long 0x4 0. "AVCPQ0,AV Untagged Control Packets Queue" "0: Receive Queue 0,1: Receive Queue 1" line.long 0x8 "ETH_MACRXQC2R,Rx queue control 2 register" hexmask.long.byte 0x8 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1" newline hexmask.long.byte 0x8 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0" group.long 0xB0++0xB line.long 0x0 "ETH_MACISR,Interrupt status register" rbitfld.long 0x0 20. "MFRIS,MMC FPE Receive Interrupt Status" "0,1" newline rbitfld.long 0x0 19. "MFTIS,MMC FPE Transmit Interrupt Status" "0,1" newline bitfld.long 0x0 18. "MDIOIS,MDIO Interrupt Status" "0,1" newline rbitfld.long 0x0 17. "FPEIS,Frame Preemption Interrupt Status" "0,1" newline bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt" "0,1" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt" "0,1" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status" "0,1" newline rbitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status" "0,1" newline rbitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status" "0,1" newline rbitfld.long 0x0 8. "MMCIS,MMC Interrupt Status" "0,1" newline rbitfld.long 0x0 5. "LPIIS,LPI Interrupt Status" "0,1" newline rbitfld.long 0x0 4. "PMTIS,PMT Interrupt Status" "0,1" newline rbitfld.long 0x0 3. "PHYIS,PHY Interrupt" "0,1" newline rbitfld.long 0x0 0. "RGSMIIIS,RGMII Interrupt Status" "0,1" line.long 0x4 "ETH_MACIER,Interrupt enable register" bitfld.long 0x4 18. "MDIOIE,MDIO Interrupt Enable" "0,1" newline bitfld.long 0x4 17. "FPEIE,Frame Preemption Interrupt Enable" "0,1" newline bitfld.long 0x4 14. "RXSTSIE,Receive Status Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "TXSTSIE,Transmit Status Interrupt Enable" "0,1" newline bitfld.long 0x4 12. "TSIE,Timestamp Interrupt Enable" "0,1" newline bitfld.long 0x4 5. "LPIIE,LPI Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "PMTIE,PMT Interrupt Enable" "0,1" newline bitfld.long 0x4 3. "PHYIE,PHY Interrupt Enable" "0,1" newline bitfld.long 0x4 0. "RGSMIIIE,RGMII Interrupt Enable" "0,1" line.long 0x8 "ETH_MACRXTXSR,Rx Tx status register" bitfld.long 0x8 8. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x8 5. "EXCOL,Excessive Collisions" "0,1" newline bitfld.long 0x8 4. "LCOL,Late Collision" "0,1" newline bitfld.long 0x8 3. "EXDEF,Excessive Deferral" "0,1" newline bitfld.long 0x8 2. "LCARR,Loss of Carrier" "0,1" newline bitfld.long 0x8 1. "NCARR,No Carrier" "0,1" newline bitfld.long 0x8 0. "TJT,Transmit Jabber Timeout" "0,1" group.long 0xC0++0x7 line.long 0x0 "ETH_MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,Remote wake-up Packet Filter Register Pointer Reset" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote wake-up FIFO Pointer" newline bitfld.long 0x0 10. "RWKPFE,Remote wake-up Packet Forwarding Enable" "0,1" newline bitfld.long 0x0 9. "GLBLUCAST,Global Unicast" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,Remote wake-up Packet Received" "0,1" newline bitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received" "0,1" newline bitfld.long 0x0 2. "RWKPKTEN,Remote wake-up Packet Enable" "0,1" newline bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable" "0,1" newline bitfld.long 0x0 0. "PWRDWN,Power Down" "0,1" line.long 0x4 "ETH_MACRWKPFR,Remote wake-up packet filter register" hexmask.long 0x4 0.--31. 1. "MACRWKPFR,Remote wake-up packet filter" group.long 0xD0++0xF line.long 0x0 "ETH_MACLCSR,LPI control and status register" bitfld.long 0x0 21. "LPITCSE,LPI Tx Clock Stop Enable" "0,1" newline bitfld.long 0x0 20. "LPITE,LPI Timer Enable" "0,1" newline bitfld.long 0x0 19. "LPITXA,LPI Tx Automate" "0,1" newline bitfld.long 0x0 18. "PLSEN,PHY Link Status Enable" "0,1" newline bitfld.long 0x0 17. "PLS,PHY Link Status" "0,1" newline bitfld.long 0x0 16. "LPIEN,LPI Enable" "0,1" newline rbitfld.long 0x0 9. "RLPIST,Receive LPI State" "0,1" newline rbitfld.long 0x0 8. "TLPIST,Transmit LPI State" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,Receive LPI Exit" "0,1" newline rbitfld.long 0x0 2. "RLPIEN,Receive LPI Entry" "0,1" newline rbitfld.long 0x0 1. "TLPIEX,Transmit LPI Exit" "0,1" newline rbitfld.long 0x0 0. "TLPIEN,Transmit LPI Entry" "0,1" line.long 0x4 "ETH_MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LPI LS Timer" newline hexmask.long.word 0x4 0.--15. 1. "TWT,LPI TW Timer" line.long 0x8 "ETH_MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--19. 1. "LPIET,LPI Entry Timer" line.long 0xC "ETH_MAC1USTCR,One-microsecond-tick counter register" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,1 s tick Counter" group.long 0xF8++0x3 line.long 0x0 "ETH_MACPHYCSR,PHYIF control status register" rbitfld.long 0x0 19. "LNKSTS,Link Status" "0: Link down,1: Link up" newline rbitfld.long 0x0 17.--18. "LNKSPEED,Link Speed" "0: 2.5 MHz,1: 25 MHz,2: 125 MHz,?" newline rbitfld.long 0x0 16. "LNKMOD,Link Mode" "0: Half-duplex mode,1: Full-duplex mode" newline bitfld.long 0x0 1. "LUD,Link Up or Down" "0: Link Down,1: Link Up" newline bitfld.long 0x0 0. "TC,Transmit Configuration in RGMII" "0,1" rgroup.long 0x110++0x7 line.long 0x0 "ETH_MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,ST-defined version" newline hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,IP version" line.long 0x4 "ETH_MACDR,Debug register" bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status" "0: Idle state,1: Waiting for one of the following:,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status" "0,1" newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status" "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status" "0,1" rgroup.long 0x11C++0xF line.long 0x0 "ETH_MACHWF0R,HW feature 0 register" bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,?" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable" "0,1" newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source" "?,1: Internal,2: External,3: Both" newline bitfld.long 0x0 24. "MACADR64SEL,MAC Addresses 64-127 Selected" "0,1" newline bitfld.long 0x0 23. "MACADR32SEL,MAC Addresses 32-63 Selected" "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled" "0,1" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled" "0,1" newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled" "0,1" newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled" "0,1" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled" "0,1" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Enable" "0,1" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable" "0,1" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote wake-up Packet Enable" "0,1" newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface" "0,1" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected" "0,1" newline bitfld.long 0x0 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface)" "0,1" newline bitfld.long 0x0 2. "HDSEL,Half-duplex Support" "0,1" newline bitfld.long 0x0 1. "GMIISEL,1000 Mbps Support" "0,1" newline bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support" "0,1" line.long 0x4 "ETH_MACHWF1R,HW feature 1 register" hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size" "0: No Hash table,1: 64,2: 128,3: 256" newline bitfld.long 0x4 23. "POUOST,One Step for PTP over UDP/IP Feature Enable" "0,1" newline bitfld.long 0x4 21. "RAVSEL,Rx Side Only AV Feature Enable" "0,1" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enable" "0,1" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enable" "0,1" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable" "0,1" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable" "0,1" newline bitfld.long 0x4 16. "DCBEN,DCB Feature Enable" "0,1" newline bitfld.long 0x4 14.--15. "ADDR64,Address width" "0: 32 bits,?,?,?" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable" "0,1" newline bitfld.long 0x4 12. "PTOEN,PTP Offload Enable" "0,1" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable" "0,1" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size" newline bitfld.long 0x4 5. "SPRAM,Single Port RAM Enable" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size" line.long 0x8 "ETH_MACHWF2R,HW feature 2 register" bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary inputs,3: 3 auxiliary inputs,4: 4 auxiliary inputs,?,?,?" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs" "0: No PPS output,1: 1 PPS output,2: 2 PPS outputs,3: 3 PPS outputs,4: 4 PPS outputs,?,?,?" newline bitfld.long 0x8 22.--23. "TDCSZ,Tx DMA Descriptor Cache Size in terms of 16-byte descriptors" "0: Cache not configured,1: Four 16-byte descriptors,2: Eight 16-byte descriptors,3: Sixteen 16-byte descriptors" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels" newline bitfld.long 0x8 16.--17. "RDCSZ,Rx DMA Descriptor Cache Size in terms of 16-byte descriptors" "0: Cache not configured,1: Four 16-byte descriptors,2: Eight 16-byte descriptors,3: Sixteen 16-byte descriptors" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues" line.long 0xC "ETH_MACHWF3R,HW feature 3 register" bitfld.long 0xC 28.--29. "ASP,Automotive Safety Package" "0: None,1: ECC only,2: AS_NPPE,3: AS_PPE" newline bitfld.long 0xC 27. "TBSSEL,Time-based scheduling Enable" "0,1" newline bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable" "0,1" newline bitfld.long 0xC 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List" "0: No width,1: 16,2: 20,3: 24" newline bitfld.long 0xC 17.--19. "ESTDEP,Depth of the Gate Control List" "0: No depth,1: 64,2: 128,3: 256,4: 512,5: 1024,?,?" newline bitfld.long 0xC 16. "ESTSEL,Enhancements to Scheduled Traffic Enable" "0,1" newline bitfld.long 0xC 13.--14. "FRPES,Flexible Receive Parser Table Entries size" "0: 64 entries,1: 128 entries,2: 256 entries,?" newline bitfld.long 0xC 11.--12. "FRPBS,Flexible Receive Parser Buffer size" "0: 64 bytes,1: 128 bytes,2: 256 bytes,?" newline bitfld.long 0xC 10. "FRPSEL,Flexible Receive Parser Selected" "0,1" newline bitfld.long 0xC 9. "PDUPSEL,Broadcast/Multicast Packet Duplication" "0,1" newline bitfld.long 0xC 5. "DVLAN,Double VLAN processing enable" "0,1" newline bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx enable" "0,1" newline bitfld.long 0xC 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,?,?" group.long 0x200++0x7 line.long 0x0 "ETH_MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,Preamble Suppression Enable" "0,1" newline bitfld.long 0x0 26. "BTB,Back to Back transactions" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address" newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address" newline bitfld.long 0x0 12.--14. "NTC,Number of Training Clocks" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range" newline bitfld.long 0x0 4. "SKAP,Skip Address Packet" "0,1" newline bitfld.long 0x0 2.--3. "GOC,GMII Operation Command" "?,1: Write,2: Post Read Increment Address for Clause 45 PHY,3: Read" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable" "0,1" newline bitfld.long 0x0 0. "GB,GMII Busy" "0,1" line.long 0x4 "ETH_MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,Register Address" newline hexmask.long.word 0x4 0.--15. 1. "GD,GMII Data" group.long 0x210++0x3 line.long 0x0 "ETH_MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address" group.long 0x230++0x7 line.long 0x0 "ETH_MACCSRSWCR,CSR software control register" bitfld.long 0x0 8. "SEEN,Slave Error Response Enable" "0,1" newline bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable" "0,1" line.long 0x4 "ETH_MACFPECSR,FPE control and status register" bitfld.long 0x4 19. "TRSP,Transmitted Respond Frame" "0,1" newline bitfld.long 0x4 18. "TVER,Transmitted Verify Frame" "0,1" newline bitfld.long 0x4 17. "RRSP,Received Respond Frame" "0,1" newline bitfld.long 0x4 16. "RVER,Received Verify Frame" "0,1" newline bitfld.long 0x4 2. "SRSP,Send Respond mPacket" "0,1" newline bitfld.long 0x4 1. "SVER,Send Verify mPacket" "0,1" newline bitfld.long 0x4 0. "EFPE,Enable Tx Frame Preemption" "0,1" group.long 0x240++0x7 line.long 0x0 "ETH_MACPRSTIMR,MAC presentation time register" hexmask.long 0x0 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns" line.long 0x4 "ETH_MACPRSTIMUR,MAC presentation time update register" hexmask.long 0x4 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update" group.long 0x300++0x1F line.long 0x0 "ETH_MACA0HR,MAC Address 0 high register" rbitfld.long 0x0 31. "AE,Address Enable" "0,1" newline bitfld.long 0x0 16. "DCS,DMA Channel Select" "0: DMA Rx channel 0,1: DMA Rx channel 1" newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32]" line.long 0x4 "ETH_MACA0LR,MAC Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address x [31:0]" line.long 0x8 "ETH_MACA1HR,MAC Address 1 high register" bitfld.long 0x8 31. "AE,Address Enable" "0,1" newline bitfld.long 0x8 30. "SA,Source Address" "0: DA,1: SA" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x8 16. "DCS,DMA Channel Select" "0: DMA Rx channel 0,1: DMA Rx channel 1" newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0xC "ETH_MACA1LR,MAC Address 1 low register" hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address x [31:0]" line.long 0x10 "ETH_MACA2HR,MAC Address 2 high register" bitfld.long 0x10 31. "AE,Address Enable" "0,1" newline bitfld.long 0x10 30. "SA,Source Address" "0: DA,1: SA" newline hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x10 16. "DCS,DMA Channel Select" "0: DMA Rx channel 0,1: DMA Rx channel 1" newline hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0x14 "ETH_MACA2LR,MAC Address 2 low register" hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address x [31:0]" line.long 0x18 "ETH_MACA3HR,MAC Address 3 high register" bitfld.long 0x18 31. "AE,Address Enable" "0,1" newline bitfld.long 0x18 30. "SA,Source Address" "0: DA,1: SA" newline hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x18 16. "DCS,DMA Channel Select" "0: DMA Rx channel 0,1: DMA Rx channel 1" newline hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0x1C "ETH_MACA3LR,MAC Address 3 low register" hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address x [31:0]" group.long 0x700++0x13 line.long 0x0 "ETH_MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets" "0,1" newline bitfld.long 0x0 5. "CNTPRSTLVL,Full-Half Preset" "0,1" newline bitfld.long 0x0 4. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 3. "CNTFREEZ,MMC Counter Freeze" "0,1" newline bitfld.long 0x0 2. "RSTONRD,Reset on Read" "0,1" newline bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover" "0,1" newline bitfld.long 0x0 0. "CNTRST,Counters Reset" "0,1" line.long 0x4 "ETH_MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x4 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status" "0,1" newline bitfld.long 0x4 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status" "0,1" newline bitfld.long 0x4 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status" "0,1" line.long 0x8 "ETH_MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x8 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status" "0,1" newline bitfld.long 0x8 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status" "0,1" newline bitfld.long 0x8 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x8 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x8 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status" "0,1" line.long 0xC "ETH_MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" bitfld.long 0xC 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask" "0,1" newline bitfld.long 0xC 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask" "0,1" newline bitfld.long 0xC 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0xC 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0xC 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask" "0,1" line.long 0x10 "ETH_MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" bitfld.long 0x10 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask" "0,1" newline bitfld.long 0x10 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask" "0,1" newline bitfld.long 0x10 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x10 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x10 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "ETH_TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets register" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets" line.long 0x4 "ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets register" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets" rgroup.long 0x768++0x3 line.long 0x0 "ETH_TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,Tx Packet Count Good" rgroup.long 0x794++0x7 line.long 0x0 "ETH_RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,Rx CRC Error Packets" line.long 0x4 "ETH_RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets register" hexmask.long 0x4 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets" rgroup.long 0x7C4++0x3 line.long 0x0 "ETH_RX_UNICAST_PACKETS_GOOD,Rx unicast packets good register" hexmask.long 0x0 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good" rgroup.long 0x7EC++0xF line.long 0x0 "ETH_TX_LPI_USEC_CNTR,Tx LPI microsecond timer register" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter" line.long 0x4 "ETH_TX_LPI_TRAN_CNTR,Tx LPI transition counter register" hexmask.long 0x4 0.--31. 1. "TXLPITRC,Tx LPI Transition counter" line.long 0x8 "ETH_RX_LPI_USEC_CNTR,Rx LPI microsecond counter register" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter" line.long 0xC "ETH_RX_LPI_TRAN_CNTR,Rx LPI transition counter register" hexmask.long 0xC 0.--31. 1. "RXLPITRC,Rx LPI Transition counter" group.long 0x8A0++0x7 line.long 0x0 "ETH_MMC_FPE_TX_ISR,MMC FPE Tx interrupt status register" bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status" "0,1" line.long 0x4 "ETH_MMC_FPE_TX_IMR,MMC FPE Tx interrupt mask register" bitfld.long 0x4 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask" "0,1" rgroup.long 0x8A8++0x7 line.long 0x0 "ETH_MMC_FPE_TX_FCR,MMC FPE Tx fragment counter register" hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter" line.long 0x4 "ETH_MMC_TX_HRCR,MMC Tx hold request counter register" hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter" rgroup.long 0x8C0++0x3 line.long 0x0 "ETH_MMC_FPE_RX_ISR,MMC FPE Rx interrupt status register" bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status" "0,1" newline bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status" "0,1" newline bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status" "0,1" group.long 0x8C4++0x3 line.long 0x0 "ETH_MMC_FPE_RX_IMR,MMC FPE Rx interrupt mask register" bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask" "0,1" rgroup.long 0x8C8++0xF line.long 0x0 "ETH_RX_PACKET_ASM_ERR,MMC Rx packet assembly error register" hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter" line.long 0x4 "ETH_RX_PACKET_SMD_ERR,MMC Rx packet SMD error register" hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter" line.long 0x8 "ETH_RX_PACKET_ASM_OKR,MMC Rx packet assembly OK register" hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter" line.long 0xC "ETH_RX_FPE_FRAG_CR,MMC Rx FPE fragments counter register" hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter" group.long 0x900++0x7 line.long 0x0 "ETH_MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 28. "DMCHEN0,DMA Channel Select Enable" "0,1" newline bitfld.long 0x0 24. "DMCHN0,DMA Channel Number" "0: DMA channel 0,1: DMA channel 1" newline bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA higher bits match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA higher bits match" newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable" "0,1" line.long 0x4 "ETH_MACL4A0R,Layer4 Address filter 0 register" hexmask.long.word 0x4 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field" group.long 0x910++0xF line.long 0x0 "ETH_MACL3A00R,Layer3 Address 0 filter 0 register" hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field" line.long 0x4 "ETH_MACL3A10R,Layer3 Address 1 filter 0 register" hexmask.long 0x4 0.--31. 1. "L3A10,Layer 3 Address 1 Field" line.long 0x8 "ETH_MACL3A20R,Layer3 Address 2 filter 0 register" hexmask.long 0x8 0.--31. 1. "L3A20,Layer 3 Address 2 Field" line.long 0xC "ETH_MACL3A30R,Layer3 Address 3 filter 0 register" hexmask.long 0xC 0.--31. 1. "L3A30,Layer 3 Address 3 Field" group.long 0x930++0x7 line.long 0x0 "ETH_MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 28. "DMCHEN1,DMA Channel Select Enable" "0,1" newline bitfld.long 0x0 24. "DMCHN1,DMA Channel Number" "0,1" newline bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA higher bits match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match" newline bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable" "0,1" line.long 0x4 "ETH_MACL4A1R,Layer 4 address filter 1 register" hexmask.long.word 0x4 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field" group.long 0x940++0xF line.long 0x0 "ETH_MACL3A01R,Layer3 address 0 filter 1 Register" hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field" line.long 0x4 "ETH_MACL3A11R,Layer3 address 1 filter 1 register" hexmask.long 0x4 0.--31. 1. "L3A11,Layer 3 Address 1 Field" line.long 0x8 "ETH_MACL3A21R,Layer3 address 2 filter 1 Register" hexmask.long 0x8 0.--31. 1. "L3A21,Layer 3 Address 2 Field" line.long 0xC "ETH_MACL3A31R,Layer3 address 3 filter 1 register" hexmask.long 0xC 0.--31. 1. "L3A31,Layer 3 Address 3 Field" group.long 0xA70++0x7 line.long 0x0 "ETH_MAC_IACR,MAC Indirect Access Control register" hexmask.long.byte 0x0 16.--19. 1. "MSEL,Mode Select" newline hexmask.long.byte 0x0 8.--15. 1. "AOFF,Address Offset" newline bitfld.long 0x0 5. "AUTO,Auto-increment" "0: AOFF is not automatically incremented. The..,1: AOFF is incremented by 1. The software should.." newline bitfld.long 0x0 1. "COM,Command type" "0: Indicates a write operation.,1: Indicates a read operation." newline bitfld.long 0x0 0. "OB,Operation Busy." "0,1" line.long 0x4 "ETH_MAC_TMRQR,MAC type-based Rx Queue mapping register" bitfld.long 0x4 20. "PFEX,Preemption or Express Packet" "0: Express packet,1: Preemption packet" newline bitfld.long 0x4 16.--18. "TMRQ,Type Match Rx Queue Number" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 0.--15. 1. "TYP,Type field Value" group.long 0xB00++0x7 line.long 0x0 "ETH_MACTSCR,Timestamp control Register" bitfld.long 0x0 28. "AV8021ASMEN,AV 802.1AS Mode Enable" "0,1" newline bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode" "0,1" newline bitfld.long 0x0 20. "ESTI,External System Time Input" "0,1" newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering" "0,1" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master" "0,1" newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages" "0,1" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP" "0,1" newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP" "0,1" newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets" "0,1" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format" "0,1" newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control" "0,1" newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets" "0,1" newline bitfld.long 0x0 6. "PTGE,Presentation Time Generation Enable" "0,1" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register" "0,1" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp" "0,1" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp" "0,1" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update" "0,1" newline bitfld.long 0x0 0. "TSENA,Enable Timestamp" "0,1" line.long 0x4 "ETH_MACSSIR,Subsecond increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,Subsecond Increment Value" rgroup.long 0xB08++0x7 line.long 0x0 "ETH_MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second" line.long 0x4 "ETH_MACSTNR,System time nanoseconds register" hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp subseconds" group.long 0xB10++0xB line.long 0x0 "ETH_MACSTSUR,System time seconds update register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds" line.long 0x4 "ETH_MACSTNUR,System time nanoseconds update register" bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time" "0,1" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp subseconds" line.long 0x8 "ETH_MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register" group.long 0xB20++0x3 line.long 0x0 "ETH_MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots" newline bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier" newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status" "0,1" newline bitfld.long 0x0 5. "TSTRGTERR1,Timestamp Target Time Error" "0,1" newline bitfld.long 0x0 4. "TSTARGT1,Timestamp Target Time Reached" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error" "0,1" newline bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot" "0,1" newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached" "0,1" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow" "0,1" group.long 0xB30++0x3 line.long 0x0 "ETH_MACTXTSSNR,Tx timestamp status nanoseconds register" rbitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed" "0,1" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low" rgroup.long 0xB34++0x3 line.long 0x0 "ETH_MACTXTSSSR,Tx timestamp status seconds register" hexmask.long 0x0 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High" group.long 0xB40++0x3 line.long 0x0 "ETH_MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,Auxiliary Snapshot 3 Enable" "0,1" newline bitfld.long 0x0 6. "ATSEN2,Auxiliary Snapshot 2 Enable" "0,1" newline bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable" "0,1" newline bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable" "0,1" newline bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "ETH_MACATSNR,Auxiliary timestamp nanoseconds register" hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp" line.long 0x4 "ETH_MACATSSR,Auxiliary timestamp seconds register" hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp" group.long 0xB50++0xF line.long 0x0 "ETH_MACTSIACR,Timestamp Ingress asymmetric correction register" hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction" line.long 0x4 "ETH_MACTSEACR,Timestamp Egress asymmetric correction register" hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction" line.long 0x8 "ETH_MACTSICNR,Timestamp Ingress correction nanosecond register" hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction" line.long 0xC "ETH_MACTSECNR,Timestamp Egress correction nanosecond register" hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction" rgroup.long 0xB68++0x7 line.long 0x0 "ETH_MACTSILR,Timestamp Ingress Latency register" hexmask.long.word 0x0 16.--27. 1. "ITLNS,Ingress Timestamp Latency in nanoseconds" newline hexmask.long.byte 0x0 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in subnanoseconds" line.long 0x4 "ETH_MACTSELR,Timestamp Egress Latency register" hexmask.long.word 0x4 16.--27. 1. "ETLNS,Egress Timestamp Latency in nanoseconds" newline hexmask.long.byte 0x4 8.--15. 1. "ETLSNS,Egress Timestamp Latency in subnanoseconds" group.long 0xB70++0x3 line.long 0x0 "ETH_MACPPSCR,PPS control register" bitfld.long 0x0 28. "TIMESEL,Time Select" "0,1" newline bitfld.long 0x0 7. "MCGREN0,MCGR Mode Enable for PPS0 Output" "0: PPS mode,1: MCGR mode" newline bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPS Output Frequency Control" group.long 0xB70++0x3 line.long 0x0 "ETH_MACPPSCR_alternate,PPS control register" bitfld.long 0x0 28. "TIMESEL,Time Select" "0,1" newline bitfld.long 0x0 15. "MCGREN1,MCGR Mode Enable for PPS Output 1" "0: PPS mode,1: MCGR mode" newline bitfld.long 0x0 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS Output 1" "0: Target time registers are programmed only for..,1: Enabled MCGR Interrupt whose status bit is..,2: Target time registers are programmed for..,3: Target time registers are programmed only for.." newline hexmask.long.byte 0x0 8.--11. 1. "PPSCMD1,Flexible PPS Output 1 Control" newline bitfld.long 0x0 7. "MCGREN0,MCGR Mode Enable for PPS Output 0" "0: PPS mode,1: MCGR mode" newline bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output 0" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output 0 Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCMD,Flexible PPS Output 0 (eth_ptp_pps_out) Control" group.long 0xB80++0x1F line.long 0x0 "ETH_MACPPSTTS0R,PPS 0 target time seconds register" hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register" line.long 0x4 "ETH_MACPPSTTN0R,PPS 0 target time nanoseconds register" bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy" "0,1" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register" line.long 0x8 "ETH_MACPPSI0R,PPS 0 interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval" line.long 0xC "ETH_MACPPSW0R,PPS 0 width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width" line.long 0x10 "ETH_MACPPSTTS1R,PPS 1 target time seconds register" hexmask.long 0x10 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register" line.long 0x14 "ETH_MACPPSTTN1R,PPS 1 target time nanoseconds register" bitfld.long 0x14 31. "TRGTBUSY0,PPS Target Time Register Busy" "0,1" newline hexmask.long 0x14 0.--30. 1. "TTSL0,Target Time Low for PPS Register" line.long 0x18 "ETH_MACPPSI1R,PPS 1 interval register" hexmask.long 0x18 0.--31. 1. "PPSINT0,PPS Output Signal Interval" line.long 0x1C "ETH_MACPPSW1R,PPS 1 width register" hexmask.long 0x1C 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width" group.long 0xBC0++0x13 line.long 0x0 "ETH_MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,Domain Number" newline bitfld.long 0x0 7. "PDRDIS,Disable Peer Delay Response response generation" "0,1" newline bitfld.long 0x0 6. "DRRDIS,Disable PTO Delay Request/Response response generation" "0,1" newline bitfld.long 0x0 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger" "0,1" newline bitfld.long 0x0 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger" "0,1" newline bitfld.long 0x0 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable" "0,1" newline bitfld.long 0x0 1. "ASYNCEN,Automatic PTP SYNC message Enable" "0,1" newline bitfld.long 0x0 0. "PTOEN,PTP Offload Enable" "0,1" line.long 0x4 "ETH_MACSPI0R,PTP Source Port Identity 0 Register" hexmask.long 0x4 0.--31. 1. "SPI0,Source Port Identity 0" line.long 0x8 "ETH_MACSPI1R,PTP Source port identity 1 register" hexmask.long 0x8 0.--31. 1. "SPI1,Source Port Identity 1" line.long 0xC "ETH_MACSPI2R,PTP Source port identity 2 register" hexmask.long.word 0xC 0.--15. 1. "SPI2,Source Port Identity 2" line.long 0x10 "ETH_MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval" newline bitfld.long 0x10 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio" "0: DelayReq generated for every received SYNC,1: DelayReq generated every alternate reception of..,?,?,?,?,?,?" newline hexmask.long.byte 0x10 0.--7. 1. "LSI,Log Sync Interval" group.long 0xC00++0x3 line.long 0x0 "ETH_MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,Counters Reset" "0,1" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm" "0: Weighted round robin (WRR) algorithm,?,?,3: Strict priority (SP) algorithm." newline bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm" "0: Strict priority (SP). Queue 0 has the lowest..,1: Weighted Strict priority (WSP)" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "ETH_MTLISR,Interrupt status Register" bitfld.long 0x0 18. "ESTIS,EST (TAS- 802.1Qbv) Interrupt Status" "0,1" newline bitfld.long 0x0 1. "Q1IS,Queue 1 interrupt status" "0,1" newline bitfld.long 0x0 0. "Q0IS,Queue 0 interrupt status" "0,1" group.long 0xC30++0x3 line.long 0x0 "ETH_MTLRXQDMAMR,Rx Queue and DMA Channel Mapping Register" bitfld.long 0x0 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection" "0,1" newline bitfld.long 0x0 8. "Q1MDMACH,Queue 1 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1" newline bitfld.long 0x0 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection" "0,1" newline bitfld.long 0x0 0. "Q0MDMACH,Queue 0 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1" group.long 0xC40++0x3 line.long 0x0 "ETH_MTLTBSCR,TBS control register" hexmask.long.tbyte 0x0 8.--31. 1. "LEOS,Launch Expiry Offset" newline bitfld.long 0x0 4.--6. "LEGOS,Launch Expiry GSN Offset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "LEOV,Launch expiry offset valid" "0: LEOS field invalid,1: LEOS field valid" newline bitfld.long 0x0 0. "ESTM,EST offset mode" "0: EST offset mode disabled,1: EST offset mode enabled" group.long 0xC50++0xB line.long 0x0 "ETH_MTLESTCR,EST Control Register" hexmask.long.byte 0x0 24.--31. 1. "PTOV,PTP Time Offset Value" newline hexmask.long.word 0x0 12.--23. 1. "CTOV,Current Time Offset Value" newline bitfld.long 0x0 8.--10. "TILS,Time Interval Left Shift Amount" "0: No left shift needed (equal to x1ns),1: Left shift TI by 1 bit (equal to x2ns),2: Left shift TI by 2 bits (equal to x4ns),?,4: Left shift TI by 7 bits (equal to x128ns),?,?,?" newline bitfld.long 0x0 6.--7. "LCSE,Loop Count to report Scheduling Error" "0: 4 iterations,1: 8 iterations,2: 16 iterations,3: 32 iterations" newline bitfld.long 0x0 5. "DFBS,Drop Frames causing Scheduling Error" "0: Don't drop,1: Drop" newline bitfld.long 0x0 4. "DDBF,Do not Drop frames during Frame Size Error" "0: Drop,1: Don't drop" newline bitfld.long 0x0 1. "SSWL,Switch to S/W owned list" "0,1" newline bitfld.long 0x0 0. "EEST,Enable EST" "0: EST disabled,1: EST enabled" line.long 0x4 "ETH_MTLESTECR,EST Extended Control Register" hexmask.long.byte 0x4 0.--5. 1. "OVHD,Overhead Bytes Value" line.long 0x8 "ETH_MTLESTSR,EST Status Register" hexmask.long.byte 0x8 16.--19. 1. "CGSN,Current GCL slot number" newline hexmask.long.byte 0x8 8.--15. 1. "BTRL,BTR Error Loop Count" newline rbitfld.long 0x8 7. "SWOL,S/W owned list" "0: Inactive,1: Active" newline bitfld.long 0x8 4. "CGCE,Constant Gate Control Error" "0: Inactive,1: Active" newline rbitfld.long 0x8 3. "HLBS,Head-Of-Line Blocking due to Scheduling" "0: Inactive,1: Active" newline rbitfld.long 0x8 2. "HLBF,Head-Of-Line Blocking due to Frame Size" "0,1" newline bitfld.long 0x8 1. "BTRE,BTR Error" "0: Inactive,1: Active" newline bitfld.long 0x8 0. "SWLC,Switch to S/W owned list Complete" "0: Inactive,1: Active" group.long 0xC60++0x7 line.long 0x0 "ETH_MTLESTSCHER,EST Schedule Error Register" bitfld.long 0x0 0.--1. "SEQN,Schedule Error Queue Number" "0,1,2,3" line.long 0x4 "ETH_MTLESTFSER,EST Frame size Error Register" bitfld.long 0x4 0.--1. "FEQN,Frame Size Error Queue Number" "0,1,2,3" rgroup.long 0xC68++0x3 line.long 0x0 "ETH_MTLESTFSCR,EST Frame size Capture Register" bitfld.long 0x0 16. "HBFQ,Queue Number of HLBF" "0,1" newline hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF" group.long 0xC70++0x3 line.long 0x0 "ETH_MTLESTIER,EST Interrupt Enable Register" bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE" "0,1" newline bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS" "0,1" newline bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF" "0,1" newline bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error" "0,1" newline bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List" "0,1" group.long 0xC80++0x7 line.long 0x0 "ETH_MTLESTGCLCR,EST Gate Control List Register" hexmask.long.byte 0x0 8.--13. 1. "ADDR,Gate Control List Address:" newline bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select" "0: Bank 0,1: Bank 1" newline bitfld.long 0x0 4. "DBGM,Debug Mode" "0,1" newline bitfld.long 0x0 2. "GCRR,Gate Control Related Registers" "0,1" newline bitfld.long 0x0 1. "R1W0,Read 1 Write 0" "0: Write operation.,1: Read operation" newline bitfld.long 0x0 0. "SRWO,Start Read/Write Operation" "?,1: Indicates the start/progress of a Read/Write.." line.long 0x4 "ETH_MTLESTGCLDR,EST Gate Control List Data Register" hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data" group.long 0xC90++0x7 line.long 0x0 "ETH_MTLFPECSR,FPE Frame Preemption Control Status Register" bitfld.long 0x0 28. "HRS,Hold/Release Status" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was last.." newline bitfld.long 0x0 8.--9. "PEC,Preemption Classification" "0,1,2,3" newline bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size" "0,1,2,3" line.long 0x4 "ETH_MTLFPEAR,FPE Frame Preemption Advance Register" hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance" newline hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance" group.long 0xD00++0x7 line.long 0x0 "ETH_MTLTXQ0OMR,T0 queue 0 operating mode Register" hexmask.long.byte 0x0 16.--19. 1. "TQS,Transmit queue size" newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,1: Enable in AV mode,2: Enabled,?" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" line.long 0x4 "ETH_MTLTXQ0UR,T0 queue 0 underflow register" bitfld.long 0x4 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" rgroup.long 0xD08++0x3 line.long 0x0 "ETH_MTLTXQ0DR,T0 queue 0 debug register" bitfld.long 0x0 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x0 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x0 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x0 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x0 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" rgroup.long 0xD14++0x3 line.long 0x0 "ETH_MTLTXQ0ESR,T0 queue 0 ETS status Register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD18++0x3 line.long 0x0 "ETH_MTLTXQ0QWR,Tx queue 0 quantum weight register" hexmask.long.byte 0x0 0.--6. 1. "ISCQW,Weights" group.long 0xD2C++0xB line.long 0x0 "ETH_MTLQ0ICSR,Queue 0 interrupt control status Register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "ETH_MTLRXQ0OMR,R0 queue 0 operating mode register" hexmask.long.byte 0x4 20.--23. 1. "RQS,Receive Queue Size" newline bitfld.long 0x4 14.--16. "RFD,Threshold for Deactivating Flow Control (in Half-duplex and Full-duplex modes)" "0: Full minus 1 Kbyte,1: Full minus 1.5 Kbyte,?,?,?,?,?,?" newline bitfld.long 0x4 8.--10. "RFA,Threshold for Activating Flow Control (in Half-duplex and Full-duplex)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" line.long 0x8 "ETH_MTLRXQ0MPOCR,R0 queue 0 missed packet and overflow counter register" bitfld.long 0x8 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x8 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x8 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x8 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" rgroup.long 0xD38++0x3 line.long 0x0 "ETH_MTLRXQ0DR,R0 queue 0 debug register" hexmask.long.word 0x0 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x0 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx queue empty,1: Rx queue fill-level below flow-control..,2: Rx queue fill-level above flow-control activate..,3: Rx queue full" newline bitfld.long 0x0 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x0 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD3C++0xB line.long 0x0 "ETH_MTLRXQ0CR,R0 queue 0 control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" line.long 0x4 "ETH_MTLTXQ1OMR,T1 queue 1 operating mode Register" hexmask.long.byte 0x4 16.--19. 1. "TQS,Transmit queue size" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,1: Enable in AV mode,2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue" "0,1" line.long 0x8 "ETH_MTLTXQ1UR,T1 queue 1 underflow register" bitfld.long 0x8 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x8 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" rgroup.long 0xD48++0x3 line.long 0x0 "ETH_MTLTXQ1DR,T1 queue 1 debug register" bitfld.long 0x0 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x0 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x0 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x0 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x0 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" group.long 0xD50++0x3 line.long 0x0 "ETH_MTLTXQ1ECR,Tx queue 1 ETS control Register" bitfld.long 0x0 4.--6. "SLC,Slot Count" "0: 1 Slot,1: 2 Slots,2: 4 Slots,3: 8 Slots,4: 16 Slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control" "0,1" newline bitfld.long 0x0 2. "AVALG,AV Algorithm" "0,1" rgroup.long 0xD54++0x3 line.long 0x0 "ETH_MTLTXQ1ESR,T1 queue 1 ETS status Register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD58++0xF line.long 0x0 "ETH_MTLTXQ1QWR,Tx queue 1 quantum weight register" hexmask.long.word 0x0 0.--13. 1. "ISCQW,IdleSlopeCredit or Weights" line.long 0x4 "ETH_MTLTXQ1SSCR,Tx queue 1 send slope credit Register" hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value" line.long 0x8 "ETH_MTLTXQ1HCR,Tx Queue 1 hiCredit register" hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value" line.long 0xC "ETH_MTLTXQ1LCR,Tx queue 1 loCredit register" hexmask.long 0xC 0.--28. 1. "LC,loCredit Value" group.long 0xD6C++0xB line.long 0x0 "ETH_MTLQ1ICSR,Queue 1 interrupt control status Register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "ETH_MTLRXQ1OMR,R1 queue 1 operating mode register" hexmask.long.byte 0x4 20.--23. 1. "RQS,Receive Queue Size" newline bitfld.long 0x4 14.--16. "RFD,Threshold for Deactivating Flow Control (in Half-duplex and Full-duplex modes)" "0: Full minus 1 Kbyte,1: Full minus 1.5 Kbyte,?,?,?,?,?,?" newline bitfld.long 0x4 8.--10. "RFA,Threshold for Activating Flow Control (in Half-duplex and Full-duplex)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" line.long 0x8 "ETH_MTLRXQ1MPOCR,R1 queue 1 missed packet and overflow counter register" bitfld.long 0x8 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x8 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x8 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x8 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" rgroup.long 0xD78++0x3 line.long 0x0 "ETH_MTLRXQ1DR,R1 queue 1 debug register" hexmask.long.word 0x0 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x0 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx queue empty,1: Rx queue fill-level below flow-control..,2: Rx queue fill-level above flow-control activate..,3: Rx queue full" newline bitfld.long 0x0 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x0 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD7C++0x3 line.long 0x0 "ETH_MTLRXQ1CR,R1 queue 1 control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" group.long 0x1000++0x7 line.long 0x0 "ETH_DMAMR,DMA mode register" bitfld.long 0x0 16.--17. "INTM,Interrupt Mode" "0,1,2,3" newline bitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" newline bitfld.long 0x0 8. "DSPW,Descriptor Posted Write" "0: The descriptor writes are always non-posted.,1: The descriptor writes are non-posted only when.." newline rbitfld.long 0x0 2.--4. "TAA,Transmit Arbitration Algorithm" "0: Fixed priority. In fixed priority Channel 0 has..,1: Weighted Strict priority (WSP),2: Weighted Round-Robin (WRR),?,?,?,?,?" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "ETH_DMASBMR,System bus mode register" bitfld.long 0x4 31. "EN_LPI,Enable Low Power Interface (LPI)" "0,1" newline bitfld.long 0x4 30. "LPI_XIT_PKT,Unlock on Magic Packet or Remote wake-up packet" "0,1" newline bitfld.long 0x4 24.--25. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit" "0,1,2,3" newline bitfld.long 0x4 16.--17. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit" "0,1,2,3" newline bitfld.long 0x4 13. "ONEKBBE,1 Kbyte Boundary Crossing Enable for the AXI Master" "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" newline bitfld.long 0x4 10. "AALE,Automatic AXI LPI enable" "0,1" newline bitfld.long 0x4 7. "BLEN256,AXI Burst Length 256" "0,1" newline bitfld.long 0x4 6. "BLEN128,AXI Burst Length 128" "0,1" newline bitfld.long 0x4 5. "BLEN64,AXI Burst Length 64" "0,1" newline bitfld.long 0x4 4. "BLEN32,AXI Burst Length 32" "0,1" newline bitfld.long 0x4 3. "BLEN16,AXI Burst Length 16" "0,1" newline bitfld.long 0x4 2. "BLEN8,AXI Burst Length 8" "0,1" newline bitfld.long 0x4 1. "BLEN4,AXI Burst Length 4" "0,1" newline bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "ETH_DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" newline bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status" "0,1" newline bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status" "0,1" line.long 0x4 "ETH_DMADSR,Debug status register" hexmask.long.byte 0x4 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State" newline hexmask.long.byte 0x4 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State" newline hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State" newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State" newline bitfld.long 0x4 1. "AXRHSTS,AXI Master Read Channel Status" "0,1" newline bitfld.long 0x4 0. "AXWHSTS,AXI Master Write Channel" "0,1" group.long 0x1020++0xB line.long 0x0 "ETH_DMAA4TXACR,AXI4 transmit channel ACE control register" hexmask.long.byte 0x0 16.--19. 1. "THC,Transmit DMA First Packet Buffer or TSO Header Cache Control" newline hexmask.long.byte 0x0 8.--11. 1. "TEC,Transmit DMA Extended Packet Buffer or TSO Payload Cache Control" newline hexmask.long.byte 0x0 0.--3. 1. "TDRC,Transmit DMA Read Descriptor Cache Control" line.long 0x4 "ETH_DMAA4RXACR,AXI4 receive channel ACE control register" hexmask.long.byte 0x4 24.--27. 1. "RDC,Receive DMA Buffer Cache Control" newline hexmask.long.byte 0x4 16.--19. 1. "RHC,Receive DMA Header Cache Control" newline hexmask.long.byte 0x4 8.--11. 1. "RPC,Receive DMA Payload Cache Control" newline hexmask.long.byte 0x4 0.--3. 1. "RDWC,Receive DMA Write Descriptor Cache Control" line.long 0x8 "ETH_DMAA4DACR,AXI4 descriptor ACE control register" hexmask.long.byte 0x8 8.--11. 1. "RDRC,Receive DMA Read Descriptor Cache control" newline bitfld.long 0x8 4.--5. "TDWD,Transmit DMA Write Descriptor Domain control" "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "TDWC,Transmit DMA Write Descriptor Cache control" group.long 0x1040++0x3 line.long 0x0 "ETH_DMALPIEI,AXI4 LPI Entry Interval register" hexmask.long.byte 0x0 0.--3. 1. "LPIEI,LPI Entry Interval" group.long 0x1050++0x3 line.long 0x0 "ETH_DMATBSCTRL0R,DMA TBS control register 0" hexmask.long.tbyte 0x0 8.--31. 1. "FTOS,Fetch time offset" newline bitfld.long 0x0 4.--6. "FGOS,Fetch GSN offset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "FTOV,Fetch time offset valid" "0: Fetch time offset invalid,1: Fetch time offset valid" group.long 0x1100++0xB line.long 0x0 "ETH_DMAC0CR,Channel 0 control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "ETH_DMAC0TXCR,Channel 0 transmit control register" bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable" "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement" "0,1" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline rbitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "ETH_DMAC0RXCR,Channel 0 receive control register" bitfld.long 0x8 31. "RPF,DMA Rx Channel x Packet Flush" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS." newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "ETH_DMAC0TXDLAR,Channel 0 T0 descriptor list address register" hexmask.long 0x0 0.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "ETH_DMAC0RXDLAR,Channel 0 Rx descriptor list address register" hexmask.long 0x0 0.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "ETH_DMAC0TXDTPR,Channel 0 T0 descriptor tail pointer register" hexmask.long 0x4 0.--31. 1. "TDT,Transmit Descriptor Tail Pointer" group.long 0x1128++0x17 line.long 0x0 "ETH_DMAC0RXDTPR,Channel 0 R0 descriptor tail pointer register" hexmask.long 0x0 0.--31. 1. "RDT,Receive Descriptor Tail Pointer" line.long 0x4 "ETH_DMAC0TXRLR,Channel 0 T0 descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "ETH_DMAC0RXRLR,Channel 0 R0 descriptor ring length register" hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size" newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "ETH_DMAC0IER,Channel 0 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0,1" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "0,1" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "ETH_DMAC0RXIWTR,Channel 0 R0 interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" line.long 0x14 "ETH_DMAC0SFCSR,Channel 0 slot function control status register" hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value" newline bitfld.long 0x14 1. "ASC,Advance Slot Check" "0,1" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison" "0,1" rgroup.long 0x1144++0x3 line.long 0x0 "ETH_DMAC0CATXDR,Channel 0 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x114C++0x3 line.long 0x0 "ETH_DMAC0CARXDR,Channel 0 current application receive descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x1154++0x3 line.long 0x0 "ETH_DMAC0CATXBR,Channel 0 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x115C++0x3 line.long 0x0 "ETH_DMAC0CARXBR,Channel 0 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x1160++0x7 line.long 0x0 "ETH_DMAC0SR,Channel 0 status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" line.long 0x4 "ETH_DMAC0MFCR,Channel 0 missed frame count register" bitfld.long 0x4 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0x1180++0xB line.long 0x0 "ETH_DMAC1CR,Channel 1 control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "ETH_DMAC1TXCR,Channel 1 transmit control register" bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable" "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement" "0,1" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline rbitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "ETH_DMAC1RXCR,Channel 1 receive control register" bitfld.long 0x8 31. "RPF,DMA Rx Channel x Packet Flush" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS." newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1194++0x3 line.long 0x0 "ETH_DMAC1TXDLAR,Channel 1 T1 descriptor list address register" hexmask.long 0x0 0.--31. 1. "TDESLA,Start of Transmit List" group.long 0x11A0++0x3 line.long 0x0 "ETH_DMAC1TXDTPR,Channel 1 T1 descriptor tail pointer register" hexmask.long 0x0 0.--31. 1. "TDT,Transmit Descriptor Tail Pointer" group.long 0x11A8++0x17 line.long 0x0 "ETH_DMAC1RXDTPR,Channel 1 R1 descriptor tail pointer register" hexmask.long 0x0 0.--31. 1. "RDT,Receive Descriptor Tail Pointer" line.long 0x4 "ETH_DMAC1TXRLR,Channel 1 T1 descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "ETH_DMAC1RXRLR,Channel 1 R1 descriptor ring length register" hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size" newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "ETH_DMAC1IER,Channel 1 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0,1" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "0,1" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "ETH_DMAC1RXIWTR,Channel 1 R1 interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" line.long 0x14 "ETH_DMAC1SFCSR,Channel 1 slot function control status register" hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value" newline bitfld.long 0x14 1. "ASC,Advance Slot Check" "0,1" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison" "0,1" rgroup.long 0x11C4++0x3 line.long 0x0 "ETH_DMAC1CATXDR,Channel 1 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x11CC++0x3 line.long 0x0 "ETH_DMAC1CARXDR,Channel 1 current application receive descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x11D4++0x3 line.long 0x0 "ETH_DMAC1CATXBR,Channel 1 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x11DC++0x3 line.long 0x0 "ETH_DMAC1CARXBR,Channel 1 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x11E0++0x7 line.long 0x0 "ETH_DMAC1SR,Channel 1 status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" line.long 0x4 "ETH_DMAC1MFCR,Channel 1 missed frame count register" bitfld.long 0x4 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "MFC,Dropped Packet Counters" tree.end tree "ETH_S" base ad:0x58036000 group.long 0x0++0x17 line.long 0x0 "ETH_MACCR,Operating mode configuration register" bitfld.long 0x0 31. "ARPEN,ARP Offload Enable" "0,1" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control" "?,?,2: the MAC inserts the content of the MAC Address 0..,3: the MAC replaces the content of the MAC Address..,?,?,6: the MAC inserts the content of the MAC Address 1..,7: the MAC replaces the content of the MAC Address.." newline bitfld.long 0x0 27. "IPC,Checksum Offload" "0,1" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap" "0: 96 bit times,1: 88 bit times,2: 80 bit times,?,?,?,?,7: 40 bit times" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable" "0,1" newline bitfld.long 0x0 22. "S2KP,IEEE 802.3as Support for 2K Packets" "0,1" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets" "0,1" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping" "0,1" newline bitfld.long 0x0 19. "WD,Watchdog Disable" "0,1" newline bitfld.long 0x0 18. "BE,Packet Burst Enable" "0,1" newline bitfld.long 0x0 17. "JD,Jabber Disable" "0,1" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable" "0,1" newline bitfld.long 0x0 15. "PS,Port Select" "0: For 1000 Mbps operations,1: For 10 or 100 Mbps operations" newline bitfld.long 0x0 14. "FES,MAC Speed" "0: 10 Mbps,1: 100 Mbps" newline bitfld.long 0x0 13. "DM,Duplex Mode" "0,1" newline bitfld.long 0x0 12. "LM,Loopback Mode" "0,1" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-duplex mode" "0,1" newline bitfld.long 0x0 10. "DO,Disable Receive Own" "0,1" newline bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission" "0,1" newline bitfld.long 0x0 8. "DR,Disable Retry" "0,1" newline bitfld.long 0x0 5.--6. "BL,Back-Off Limit" "0: k= min (n 10),1: k = min (n 8),2: k = min (n 4),3: k = min (n 1)" newline bitfld.long 0x0 4. "DC,Deferral Check" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,?" newline bitfld.long 0x0 1. "TE,Transmitter Enable" "0,1" newline bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "ETH_MACECR,Extended operating mode configuration register" bitfld.long 0x4 30. "APDIM,ARP Packet Drop if IP Address Mismatch" "0,1" newline hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap" newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable" "0,1" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect" "0,1" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable" "0,1" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets" "0,1" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit" line.long 0x8 "ETH_MACPFR,Packet filtering control register" bitfld.long 0x8 31. "RA,Receive All" "0,1" newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets" "0,1" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable" "0,1" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable" "0,1" newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter" "0,1" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable" "0,1" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering" "0,1" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets" "0: The MAC filters all control packets from..,1: The MAC forwards all control packets except..,2: The MAC forwards all control packets to the..,3: The MAC forwards the control packets that pass.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets" "0,1" newline bitfld.long 0x8 4. "PM,Pass All Multicast" "0,1" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering" "0,1" newline bitfld.long 0x8 2. "HMC,Hash Multicast" "0,1" newline bitfld.long 0x8 1. "HUC,Hash Unicast" "0,1" newline bitfld.long 0x8 0. "PR,Promiscuous Mode" "0,1" line.long 0xC "ETH_MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable" "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout" line.long 0x10 "ETH_MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits" line.long 0x14 "ETH_MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits" group.long 0x50++0xB line.long 0x0 "ETH_MACVTCR,VLAN tag Control register" bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status" "0,1" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag" "0,1" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing" "0,1" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable" "0,1" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status" "0,1" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match" "0,1" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN" "0,1" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable" "0,1" newline bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison" "0,1" newline bitfld.long 0x0 2.--3. "OFS,Offset" "0: ETH_MACVTDR holds MAC VLAN Tag Filter0 content,1: ETH_MACVTDR holds MAC VLAN Tag Filter1 content,2: ETH_MACVTDR holds MAC VLAN Tag Filter2 content,3: ETH_MACVTDR holds MAC VLAN Tag Filter3 content" newline bitfld.long 0x0 1. "CT,Command Type" "0,1" newline bitfld.long 0x0 0. "OB,Operation Busy" "0,1" line.long 0x4 "ETH_MACVTDR,VLAN tag data register" bitfld.long 0x4 25. "DMACHN,DMA Channel Number" "0,1" newline bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable" "0,1" newline bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0,1" newline bitfld.long 0x4 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0,1" newline bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Comparison" "0,1" newline bitfld.long 0x4 17. "ETV,12-bit or 16-bit VLAN comparison" "0: 16-bit VLAN,1: 12-bit VLAN" newline bitfld.long 0x4 16. "VEN,VLAN Tag Enable" "0,1" newline hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag ID" line.long 0x8 "ETH_MACVHTR,VLAN Hash table register" hexmask.long.word 0x8 0.--15. 1. "VLHT,VLAN Hash Table" group.long 0x60++0x3 line.long 0x0 "ETH_MACVIR,VLAN inclusion register" rbitfld.long 0x0 31. "BUSY,Busy" "0,1" newline bitfld.long 0x0 30. "RDWR,Read write control" "0,1" newline bitfld.long 0x0 24. "ADDR,Address" "0: VLAN tag for insertion in the Transmit packets..,1: VLAN tag for insertion in the Transmit packets.." newline bitfld.long 0x0 21. "CBTI,Channel based tag insertion" "0,1" newline bitfld.long 0x0 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0: C-LAN,1: S-LAN" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion. The MAC removes the VLAN type..,2: VLAN tag insertion. The MAC inserts VLT in bytes..,3: VLAN tag replacement. The MAC replaces VLT in.." newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x60++0x7 line.long 0x0 "ETH_MACVIR_alternate,VLAN inclusion register" bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0: C-LAN,1: S-LAN" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" line.long 0x4 "ETH_MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN" "0: C-LAN,1: S-LAN" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x70++0x3 line.long 0x0 "ETH_MACQ0TXFCR,Tx Queue 0 flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time" newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause" "0,1" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate" "0,1" group.long 0x90++0x7 line.long 0x0 "ETH_MACRXFCR,Rx flow control register" bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect" "0,1" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable" "0,1" line.long 0x4 "ETH_MACRXQCR,Rx Queue control register" bitfld.long 0x4 17. "VFFQ,VLAN Tag Filter Fail Packets Queue" "0: Queue 0,1: Queue 1" newline bitfld.long 0x4 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 9. "MFFQ,Multicast Address Filter Fail Packets Queue." "0: Queue 0,1: Queue 1" newline bitfld.long 0x4 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable." "0,1" newline bitfld.long 0x4 1. "UFFQ,Unicast Address Filter Fail Packets Queue." "0: Queue 0,1: Queue 1" newline bitfld.long 0x4 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable." "0,1" group.long 0xA0++0xB line.long 0x0 "ETH_MACRXQC0R,Rx queue control 0 register" bitfld.long 0x0 2.--3. "RXQ1EN,Receive Queue 1 Enable" "0: Not enabled,1: Queue 1 enabled for AV,2: Queue 1 enabled for Generic traffic,?" newline bitfld.long 0x0 0.--1. "RXQ0EN,Receive Queue 0 Enable" "0: Not enabled,1: Queue 0 enabled for AV,2: Queue 0 enabled for Generic traffic,?" line.long 0x4 "ETH_MACRXQC1R,Rx queue control 1 register" bitfld.long 0x4 29. "TBRQE,Type Field Based Rx Queuing Enable" "0,1" newline bitfld.long 0x4 28. "OMCBCQ,Overriding MC-BC queue priority select" "0: Received Multicast/Broadcast packet is routed to..,1: Priority of MCBCQ is reduced and the received.." newline bitfld.long 0x4 26. "FPRQ2,Frame Preemption Residue Queue" "?,1: Rx queue 1" newline bitfld.long 0x4 25. "FPRQ1,Frame Preemption Residue Queue" "?,1: Rx queue 1" newline bitfld.long 0x4 24. "FPRQ0,Frame Preemption Residue Queue" "?,1: Rx queue 1" newline bitfld.long 0x4 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control" "0: VLAN tagged PTPoE packets are routed as generic..,1: VLAN tagged PTPoE packets are routed to Rx Queue..,2: VLAN tagged PTPoE packets are routed to only AV..,?" newline bitfld.long 0x4 21. "TACPQE,Tagged AV Control Packets Queuing Enable" "0,1" newline bitfld.long 0x4 20. "MCBCQEN,Multicast and Broadcast Queue Enable" "0,1" newline bitfld.long 0x4 16.--18. "MCBCQ,Multicast and Broadcast Queue" "0: Rx queue 0,1: Rx queue 1,?,?,?,?,?,?" newline bitfld.long 0x4 12.--14. "UPQ,Untagged Packet Queue" "0: Rx queue 0,1: Rx queue 1,?,?,?,?,?,?" newline bitfld.long 0x4 4.--6. "PTPQ,PTP Packets Queue" "0: Rx queue 0,1: Rx queue 1,?,?,?,?,?,?" newline bitfld.long 0x4 2. "AVCPQ2,AV Untagged Control Packets Queue" "0: Receive Queue 0,1: Receive Queue 1" newline bitfld.long 0x4 1. "AVCPQ1,AV Untagged Control Packets Queue" "0: Receive Queue 0,1: Receive Queue 1" newline bitfld.long 0x4 0. "AVCPQ0,AV Untagged Control Packets Queue" "0: Receive Queue 0,1: Receive Queue 1" line.long 0x8 "ETH_MACRXQC2R,Rx queue control 2 register" hexmask.long.byte 0x8 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1" newline hexmask.long.byte 0x8 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0" group.long 0xB0++0xB line.long 0x0 "ETH_MACISR,Interrupt status register" rbitfld.long 0x0 20. "MFRIS,MMC FPE Receive Interrupt Status" "0,1" newline rbitfld.long 0x0 19. "MFTIS,MMC FPE Transmit Interrupt Status" "0,1" newline bitfld.long 0x0 18. "MDIOIS,MDIO Interrupt Status" "0,1" newline rbitfld.long 0x0 17. "FPEIS,Frame Preemption Interrupt Status" "0,1" newline bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt" "0,1" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt" "0,1" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status" "0,1" newline rbitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status" "0,1" newline rbitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status" "0,1" newline rbitfld.long 0x0 8. "MMCIS,MMC Interrupt Status" "0,1" newline rbitfld.long 0x0 5. "LPIIS,LPI Interrupt Status" "0,1" newline rbitfld.long 0x0 4. "PMTIS,PMT Interrupt Status" "0,1" newline rbitfld.long 0x0 3. "PHYIS,PHY Interrupt" "0,1" newline rbitfld.long 0x0 0. "RGSMIIIS,RGMII Interrupt Status" "0,1" line.long 0x4 "ETH_MACIER,Interrupt enable register" bitfld.long 0x4 18. "MDIOIE,MDIO Interrupt Enable" "0,1" newline bitfld.long 0x4 17. "FPEIE,Frame Preemption Interrupt Enable" "0,1" newline bitfld.long 0x4 14. "RXSTSIE,Receive Status Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "TXSTSIE,Transmit Status Interrupt Enable" "0,1" newline bitfld.long 0x4 12. "TSIE,Timestamp Interrupt Enable" "0,1" newline bitfld.long 0x4 5. "LPIIE,LPI Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "PMTIE,PMT Interrupt Enable" "0,1" newline bitfld.long 0x4 3. "PHYIE,PHY Interrupt Enable" "0,1" newline bitfld.long 0x4 0. "RGSMIIIE,RGMII Interrupt Enable" "0,1" line.long 0x8 "ETH_MACRXTXSR,Rx Tx status register" bitfld.long 0x8 8. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x8 5. "EXCOL,Excessive Collisions" "0,1" newline bitfld.long 0x8 4. "LCOL,Late Collision" "0,1" newline bitfld.long 0x8 3. "EXDEF,Excessive Deferral" "0,1" newline bitfld.long 0x8 2. "LCARR,Loss of Carrier" "0,1" newline bitfld.long 0x8 1. "NCARR,No Carrier" "0,1" newline bitfld.long 0x8 0. "TJT,Transmit Jabber Timeout" "0,1" group.long 0xC0++0x7 line.long 0x0 "ETH_MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,Remote wake-up Packet Filter Register Pointer Reset" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote wake-up FIFO Pointer" newline bitfld.long 0x0 10. "RWKPFE,Remote wake-up Packet Forwarding Enable" "0,1" newline bitfld.long 0x0 9. "GLBLUCAST,Global Unicast" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,Remote wake-up Packet Received" "0,1" newline bitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received" "0,1" newline bitfld.long 0x0 2. "RWKPKTEN,Remote wake-up Packet Enable" "0,1" newline bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable" "0,1" newline bitfld.long 0x0 0. "PWRDWN,Power Down" "0,1" line.long 0x4 "ETH_MACRWKPFR,Remote wake-up packet filter register" hexmask.long 0x4 0.--31. 1. "MACRWKPFR,Remote wake-up packet filter" group.long 0xD0++0xF line.long 0x0 "ETH_MACLCSR,LPI control and status register" bitfld.long 0x0 21. "LPITCSE,LPI Tx Clock Stop Enable" "0,1" newline bitfld.long 0x0 20. "LPITE,LPI Timer Enable" "0,1" newline bitfld.long 0x0 19. "LPITXA,LPI Tx Automate" "0,1" newline bitfld.long 0x0 18. "PLSEN,PHY Link Status Enable" "0,1" newline bitfld.long 0x0 17. "PLS,PHY Link Status" "0,1" newline bitfld.long 0x0 16. "LPIEN,LPI Enable" "0,1" newline rbitfld.long 0x0 9. "RLPIST,Receive LPI State" "0,1" newline rbitfld.long 0x0 8. "TLPIST,Transmit LPI State" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,Receive LPI Exit" "0,1" newline rbitfld.long 0x0 2. "RLPIEN,Receive LPI Entry" "0,1" newline rbitfld.long 0x0 1. "TLPIEX,Transmit LPI Exit" "0,1" newline rbitfld.long 0x0 0. "TLPIEN,Transmit LPI Entry" "0,1" line.long 0x4 "ETH_MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LPI LS Timer" newline hexmask.long.word 0x4 0.--15. 1. "TWT,LPI TW Timer" line.long 0x8 "ETH_MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--19. 1. "LPIET,LPI Entry Timer" line.long 0xC "ETH_MAC1USTCR,One-microsecond-tick counter register" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,1 s tick Counter" group.long 0xF8++0x3 line.long 0x0 "ETH_MACPHYCSR,PHYIF control status register" rbitfld.long 0x0 19. "LNKSTS,Link Status" "0: Link down,1: Link up" newline rbitfld.long 0x0 17.--18. "LNKSPEED,Link Speed" "0: 2.5 MHz,1: 25 MHz,2: 125 MHz,?" newline rbitfld.long 0x0 16. "LNKMOD,Link Mode" "0: Half-duplex mode,1: Full-duplex mode" newline bitfld.long 0x0 1. "LUD,Link Up or Down" "0: Link Down,1: Link Up" newline bitfld.long 0x0 0. "TC,Transmit Configuration in RGMII" "0,1" rgroup.long 0x110++0x7 line.long 0x0 "ETH_MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,ST-defined version" newline hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,IP version" line.long 0x4 "ETH_MACDR,Debug register" bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status" "0: Idle state,1: Waiting for one of the following:,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status" "0,1" newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status" "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status" "0,1" rgroup.long 0x11C++0xF line.long 0x0 "ETH_MACHWF0R,HW feature 0 register" bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,?" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable" "0,1" newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source" "?,1: Internal,2: External,3: Both" newline bitfld.long 0x0 24. "MACADR64SEL,MAC Addresses 64-127 Selected" "0,1" newline bitfld.long 0x0 23. "MACADR32SEL,MAC Addresses 32-63 Selected" "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled" "0,1" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled" "0,1" newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled" "0,1" newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled" "0,1" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled" "0,1" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Enable" "0,1" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable" "0,1" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote wake-up Packet Enable" "0,1" newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface" "0,1" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected" "0,1" newline bitfld.long 0x0 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface)" "0,1" newline bitfld.long 0x0 2. "HDSEL,Half-duplex Support" "0,1" newline bitfld.long 0x0 1. "GMIISEL,1000 Mbps Support" "0,1" newline bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support" "0,1" line.long 0x4 "ETH_MACHWF1R,HW feature 1 register" hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size" "0: No Hash table,1: 64,2: 128,3: 256" newline bitfld.long 0x4 23. "POUOST,One Step for PTP over UDP/IP Feature Enable" "0,1" newline bitfld.long 0x4 21. "RAVSEL,Rx Side Only AV Feature Enable" "0,1" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enable" "0,1" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enable" "0,1" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable" "0,1" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable" "0,1" newline bitfld.long 0x4 16. "DCBEN,DCB Feature Enable" "0,1" newline bitfld.long 0x4 14.--15. "ADDR64,Address width" "0: 32 bits,?,?,?" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable" "0,1" newline bitfld.long 0x4 12. "PTOEN,PTP Offload Enable" "0,1" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable" "0,1" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size" newline bitfld.long 0x4 5. "SPRAM,Single Port RAM Enable" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size" line.long 0x8 "ETH_MACHWF2R,HW feature 2 register" bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary inputs,3: 3 auxiliary inputs,4: 4 auxiliary inputs,?,?,?" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs" "0: No PPS output,1: 1 PPS output,2: 2 PPS outputs,3: 3 PPS outputs,4: 4 PPS outputs,?,?,?" newline bitfld.long 0x8 22.--23. "TDCSZ,Tx DMA Descriptor Cache Size in terms of 16-byte descriptors" "0: Cache not configured,1: Four 16-byte descriptors,2: Eight 16-byte descriptors,3: Sixteen 16-byte descriptors" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels" newline bitfld.long 0x8 16.--17. "RDCSZ,Rx DMA Descriptor Cache Size in terms of 16-byte descriptors" "0: Cache not configured,1: Four 16-byte descriptors,2: Eight 16-byte descriptors,3: Sixteen 16-byte descriptors" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues" line.long 0xC "ETH_MACHWF3R,HW feature 3 register" bitfld.long 0xC 28.--29. "ASP,Automotive Safety Package" "0: None,1: ECC only,2: AS_NPPE,3: AS_PPE" newline bitfld.long 0xC 27. "TBSSEL,Time-based scheduling Enable" "0,1" newline bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable" "0,1" newline bitfld.long 0xC 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List" "0: No width,1: 16,2: 20,3: 24" newline bitfld.long 0xC 17.--19. "ESTDEP,Depth of the Gate Control List" "0: No depth,1: 64,2: 128,3: 256,4: 512,5: 1024,?,?" newline bitfld.long 0xC 16. "ESTSEL,Enhancements to Scheduled Traffic Enable" "0,1" newline bitfld.long 0xC 13.--14. "FRPES,Flexible Receive Parser Table Entries size" "0: 64 entries,1: 128 entries,2: 256 entries,?" newline bitfld.long 0xC 11.--12. "FRPBS,Flexible Receive Parser Buffer size" "0: 64 bytes,1: 128 bytes,2: 256 bytes,?" newline bitfld.long 0xC 10. "FRPSEL,Flexible Receive Parser Selected" "0,1" newline bitfld.long 0xC 9. "PDUPSEL,Broadcast/Multicast Packet Duplication" "0,1" newline bitfld.long 0xC 5. "DVLAN,Double VLAN processing enable" "0,1" newline bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx enable" "0,1" newline bitfld.long 0xC 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,?,?" group.long 0x200++0x7 line.long 0x0 "ETH_MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,Preamble Suppression Enable" "0,1" newline bitfld.long 0x0 26. "BTB,Back to Back transactions" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address" newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address" newline bitfld.long 0x0 12.--14. "NTC,Number of Training Clocks" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range" newline bitfld.long 0x0 4. "SKAP,Skip Address Packet" "0,1" newline bitfld.long 0x0 2.--3. "GOC,GMII Operation Command" "?,1: Write,2: Post Read Increment Address for Clause 45 PHY,3: Read" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable" "0,1" newline bitfld.long 0x0 0. "GB,GMII Busy" "0,1" line.long 0x4 "ETH_MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,Register Address" newline hexmask.long.word 0x4 0.--15. 1. "GD,GMII Data" group.long 0x210++0x3 line.long 0x0 "ETH_MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address" group.long 0x230++0x7 line.long 0x0 "ETH_MACCSRSWCR,CSR software control register" bitfld.long 0x0 8. "SEEN,Slave Error Response Enable" "0,1" newline bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable" "0,1" line.long 0x4 "ETH_MACFPECSR,FPE control and status register" bitfld.long 0x4 19. "TRSP,Transmitted Respond Frame" "0,1" newline bitfld.long 0x4 18. "TVER,Transmitted Verify Frame" "0,1" newline bitfld.long 0x4 17. "RRSP,Received Respond Frame" "0,1" newline bitfld.long 0x4 16. "RVER,Received Verify Frame" "0,1" newline bitfld.long 0x4 2. "SRSP,Send Respond mPacket" "0,1" newline bitfld.long 0x4 1. "SVER,Send Verify mPacket" "0,1" newline bitfld.long 0x4 0. "EFPE,Enable Tx Frame Preemption" "0,1" group.long 0x240++0x7 line.long 0x0 "ETH_MACPRSTIMR,MAC presentation time register" hexmask.long 0x0 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns" line.long 0x4 "ETH_MACPRSTIMUR,MAC presentation time update register" hexmask.long 0x4 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update" group.long 0x300++0x1F line.long 0x0 "ETH_MACA0HR,MAC Address 0 high register" rbitfld.long 0x0 31. "AE,Address Enable" "0,1" newline bitfld.long 0x0 16. "DCS,DMA Channel Select" "0: DMA Rx channel 0,1: DMA Rx channel 1" newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32]" line.long 0x4 "ETH_MACA0LR,MAC Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address x [31:0]" line.long 0x8 "ETH_MACA1HR,MAC Address 1 high register" bitfld.long 0x8 31. "AE,Address Enable" "0,1" newline bitfld.long 0x8 30. "SA,Source Address" "0: DA,1: SA" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x8 16. "DCS,DMA Channel Select" "0: DMA Rx channel 0,1: DMA Rx channel 1" newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0xC "ETH_MACA1LR,MAC Address 1 low register" hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address x [31:0]" line.long 0x10 "ETH_MACA2HR,MAC Address 2 high register" bitfld.long 0x10 31. "AE,Address Enable" "0,1" newline bitfld.long 0x10 30. "SA,Source Address" "0: DA,1: SA" newline hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x10 16. "DCS,DMA Channel Select" "0: DMA Rx channel 0,1: DMA Rx channel 1" newline hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0x14 "ETH_MACA2LR,MAC Address 2 low register" hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address x [31:0]" line.long 0x18 "ETH_MACA3HR,MAC Address 3 high register" bitfld.long 0x18 31. "AE,Address Enable" "0,1" newline bitfld.long 0x18 30. "SA,Source Address" "0: DA,1: SA" newline hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control" newline bitfld.long 0x18 16. "DCS,DMA Channel Select" "0: DMA Rx channel 0,1: DMA Rx channel 1" newline hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0x1C "ETH_MACA3LR,MAC Address 3 low register" hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address x [31:0]" group.long 0x700++0x13 line.long 0x0 "ETH_MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets" "0,1" newline bitfld.long 0x0 5. "CNTPRSTLVL,Full-Half Preset" "0,1" newline bitfld.long 0x0 4. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 3. "CNTFREEZ,MMC Counter Freeze" "0,1" newline bitfld.long 0x0 2. "RSTONRD,Reset on Read" "0,1" newline bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover" "0,1" newline bitfld.long 0x0 0. "CNTRST,Counters Reset" "0,1" line.long 0x4 "ETH_MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x4 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status" "0,1" newline bitfld.long 0x4 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status" "0,1" newline bitfld.long 0x4 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status" "0,1" line.long 0x8 "ETH_MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x8 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status" "0,1" newline bitfld.long 0x8 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status" "0,1" newline bitfld.long 0x8 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x8 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x8 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status" "0,1" line.long 0xC "ETH_MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" bitfld.long 0xC 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask" "0,1" newline bitfld.long 0xC 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask" "0,1" newline bitfld.long 0xC 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0xC 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0xC 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask" "0,1" line.long 0x10 "ETH_MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" bitfld.long 0x10 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask" "0,1" newline bitfld.long 0x10 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask" "0,1" newline bitfld.long 0x10 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x10 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x10 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "ETH_TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets register" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets" line.long 0x4 "ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets register" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets" rgroup.long 0x768++0x3 line.long 0x0 "ETH_TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,Tx Packet Count Good" rgroup.long 0x794++0x7 line.long 0x0 "ETH_RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,Rx CRC Error Packets" line.long 0x4 "ETH_RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets register" hexmask.long 0x4 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets" rgroup.long 0x7C4++0x3 line.long 0x0 "ETH_RX_UNICAST_PACKETS_GOOD,Rx unicast packets good register" hexmask.long 0x0 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good" rgroup.long 0x7EC++0xF line.long 0x0 "ETH_TX_LPI_USEC_CNTR,Tx LPI microsecond timer register" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter" line.long 0x4 "ETH_TX_LPI_TRAN_CNTR,Tx LPI transition counter register" hexmask.long 0x4 0.--31. 1. "TXLPITRC,Tx LPI Transition counter" line.long 0x8 "ETH_RX_LPI_USEC_CNTR,Rx LPI microsecond counter register" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter" line.long 0xC "ETH_RX_LPI_TRAN_CNTR,Rx LPI transition counter register" hexmask.long 0xC 0.--31. 1. "RXLPITRC,Rx LPI Transition counter" group.long 0x8A0++0x7 line.long 0x0 "ETH_MMC_FPE_TX_ISR,MMC FPE Tx interrupt status register" bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status" "0,1" line.long 0x4 "ETH_MMC_FPE_TX_IMR,MMC FPE Tx interrupt mask register" bitfld.long 0x4 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask" "0,1" rgroup.long 0x8A8++0x7 line.long 0x0 "ETH_MMC_FPE_TX_FCR,MMC FPE Tx fragment counter register" hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter" line.long 0x4 "ETH_MMC_TX_HRCR,MMC Tx hold request counter register" hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter" rgroup.long 0x8C0++0x3 line.long 0x0 "ETH_MMC_FPE_RX_ISR,MMC FPE Rx interrupt status register" bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status" "0,1" newline bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status" "0,1" newline bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status" "0,1" newline bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status" "0,1" group.long 0x8C4++0x3 line.long 0x0 "ETH_MMC_FPE_RX_IMR,MMC FPE Rx interrupt mask register" bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask" "0,1" rgroup.long 0x8C8++0xF line.long 0x0 "ETH_RX_PACKET_ASM_ERR,MMC Rx packet assembly error register" hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter" line.long 0x4 "ETH_RX_PACKET_SMD_ERR,MMC Rx packet SMD error register" hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter" line.long 0x8 "ETH_RX_PACKET_ASM_OKR,MMC Rx packet assembly OK register" hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter" line.long 0xC "ETH_RX_FPE_FRAG_CR,MMC Rx FPE fragments counter register" hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter" group.long 0x900++0x7 line.long 0x0 "ETH_MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 28. "DMCHEN0,DMA Channel Select Enable" "0,1" newline bitfld.long 0x0 24. "DMCHN0,DMA Channel Number" "0: DMA channel 0,1: DMA channel 1" newline bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA higher bits match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA higher bits match" newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable" "0,1" line.long 0x4 "ETH_MACL4A0R,Layer4 Address filter 0 register" hexmask.long.word 0x4 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field" group.long 0x910++0xF line.long 0x0 "ETH_MACL3A00R,Layer3 Address 0 filter 0 register" hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field" line.long 0x4 "ETH_MACL3A10R,Layer3 Address 1 filter 0 register" hexmask.long 0x4 0.--31. 1. "L3A10,Layer 3 Address 1 Field" line.long 0x8 "ETH_MACL3A20R,Layer3 Address 2 filter 0 register" hexmask.long 0x8 0.--31. 1. "L3A20,Layer 3 Address 2 Field" line.long 0xC "ETH_MACL3A30R,Layer3 Address 3 filter 0 register" hexmask.long 0xC 0.--31. 1. "L3A30,Layer 3 Address 3 Field" group.long 0x930++0x7 line.long 0x0 "ETH_MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 28. "DMCHEN1,DMA Channel Select Enable" "0,1" newline bitfld.long 0x0 24. "DMCHN1,DMA Channel Number" "0,1" newline bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA higher bits match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match" newline bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable" "0,1" line.long 0x4 "ETH_MACL4A1R,Layer 4 address filter 1 register" hexmask.long.word 0x4 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field" group.long 0x940++0xF line.long 0x0 "ETH_MACL3A01R,Layer3 address 0 filter 1 Register" hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field" line.long 0x4 "ETH_MACL3A11R,Layer3 address 1 filter 1 register" hexmask.long 0x4 0.--31. 1. "L3A11,Layer 3 Address 1 Field" line.long 0x8 "ETH_MACL3A21R,Layer3 address 2 filter 1 Register" hexmask.long 0x8 0.--31. 1. "L3A21,Layer 3 Address 2 Field" line.long 0xC "ETH_MACL3A31R,Layer3 address 3 filter 1 register" hexmask.long 0xC 0.--31. 1. "L3A31,Layer 3 Address 3 Field" group.long 0xA70++0x7 line.long 0x0 "ETH_MAC_IACR,MAC Indirect Access Control register" hexmask.long.byte 0x0 16.--19. 1. "MSEL,Mode Select" newline hexmask.long.byte 0x0 8.--15. 1. "AOFF,Address Offset" newline bitfld.long 0x0 5. "AUTO,Auto-increment" "0: AOFF is not automatically incremented. The..,1: AOFF is incremented by 1. The software should.." newline bitfld.long 0x0 1. "COM,Command type" "0: Indicates a write operation.,1: Indicates a read operation." newline bitfld.long 0x0 0. "OB,Operation Busy." "0,1" line.long 0x4 "ETH_MAC_TMRQR,MAC type-based Rx Queue mapping register" bitfld.long 0x4 20. "PFEX,Preemption or Express Packet" "0: Express packet,1: Preemption packet" newline bitfld.long 0x4 16.--18. "TMRQ,Type Match Rx Queue Number" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 0.--15. 1. "TYP,Type field Value" group.long 0xB00++0x7 line.long 0x0 "ETH_MACTSCR,Timestamp control Register" bitfld.long 0x0 28. "AV8021ASMEN,AV 802.1AS Mode Enable" "0,1" newline bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode" "0,1" newline bitfld.long 0x0 20. "ESTI,External System Time Input" "0,1" newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering" "0,1" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master" "0,1" newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages" "0,1" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP" "0,1" newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP" "0,1" newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets" "0,1" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format" "0,1" newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control" "0,1" newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets" "0,1" newline bitfld.long 0x0 6. "PTGE,Presentation Time Generation Enable" "0,1" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register" "0,1" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp" "0,1" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp" "0,1" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update" "0,1" newline bitfld.long 0x0 0. "TSENA,Enable Timestamp" "0,1" line.long 0x4 "ETH_MACSSIR,Subsecond increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,Subsecond Increment Value" rgroup.long 0xB08++0x7 line.long 0x0 "ETH_MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second" line.long 0x4 "ETH_MACSTNR,System time nanoseconds register" hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp subseconds" group.long 0xB10++0xB line.long 0x0 "ETH_MACSTSUR,System time seconds update register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds" line.long 0x4 "ETH_MACSTNUR,System time nanoseconds update register" bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time" "0,1" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp subseconds" line.long 0x8 "ETH_MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register" group.long 0xB20++0x3 line.long 0x0 "ETH_MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots" newline bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier" newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status" "0,1" newline bitfld.long 0x0 5. "TSTRGTERR1,Timestamp Target Time Error" "0,1" newline bitfld.long 0x0 4. "TSTARGT1,Timestamp Target Time Reached" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error" "0,1" newline bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot" "0,1" newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached" "0,1" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow" "0,1" group.long 0xB30++0x3 line.long 0x0 "ETH_MACTXTSSNR,Tx timestamp status nanoseconds register" rbitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed" "0,1" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low" rgroup.long 0xB34++0x3 line.long 0x0 "ETH_MACTXTSSSR,Tx timestamp status seconds register" hexmask.long 0x0 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High" group.long 0xB40++0x3 line.long 0x0 "ETH_MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,Auxiliary Snapshot 3 Enable" "0,1" newline bitfld.long 0x0 6. "ATSEN2,Auxiliary Snapshot 2 Enable" "0,1" newline bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable" "0,1" newline bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable" "0,1" newline bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "ETH_MACATSNR,Auxiliary timestamp nanoseconds register" hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp" line.long 0x4 "ETH_MACATSSR,Auxiliary timestamp seconds register" hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp" group.long 0xB50++0xF line.long 0x0 "ETH_MACTSIACR,Timestamp Ingress asymmetric correction register" hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction" line.long 0x4 "ETH_MACTSEACR,Timestamp Egress asymmetric correction register" hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction" line.long 0x8 "ETH_MACTSICNR,Timestamp Ingress correction nanosecond register" hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction" line.long 0xC "ETH_MACTSECNR,Timestamp Egress correction nanosecond register" hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction" rgroup.long 0xB68++0x7 line.long 0x0 "ETH_MACTSILR,Timestamp Ingress Latency register" hexmask.long.word 0x0 16.--27. 1. "ITLNS,Ingress Timestamp Latency in nanoseconds" newline hexmask.long.byte 0x0 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in subnanoseconds" line.long 0x4 "ETH_MACTSELR,Timestamp Egress Latency register" hexmask.long.word 0x4 16.--27. 1. "ETLNS,Egress Timestamp Latency in nanoseconds" newline hexmask.long.byte 0x4 8.--15. 1. "ETLSNS,Egress Timestamp Latency in subnanoseconds" group.long 0xB70++0x3 line.long 0x0 "ETH_MACPPSCR,PPS control register" bitfld.long 0x0 28. "TIMESEL,Time Select" "0,1" newline bitfld.long 0x0 7. "MCGREN0,MCGR Mode Enable for PPS0 Output" "0: PPS mode,1: MCGR mode" newline bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPS Output Frequency Control" group.long 0xB70++0x3 line.long 0x0 "ETH_MACPPSCR_alternate,PPS control register" bitfld.long 0x0 28. "TIMESEL,Time Select" "0,1" newline bitfld.long 0x0 15. "MCGREN1,MCGR Mode Enable for PPS Output 1" "0: PPS mode,1: MCGR mode" newline bitfld.long 0x0 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS Output 1" "0: Target time registers are programmed only for..,1: Enabled MCGR Interrupt whose status bit is..,2: Target time registers are programmed for..,3: Target time registers are programmed only for.." newline hexmask.long.byte 0x0 8.--11. 1. "PPSCMD1,Flexible PPS Output 1 Control" newline bitfld.long 0x0 7. "MCGREN0,MCGR Mode Enable for PPS Output 0" "0: PPS mode,1: MCGR mode" newline bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output 0" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output 0 Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCMD,Flexible PPS Output 0 (eth_ptp_pps_out) Control" group.long 0xB80++0x1F line.long 0x0 "ETH_MACPPSTTS0R,PPS 0 target time seconds register" hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register" line.long 0x4 "ETH_MACPPSTTN0R,PPS 0 target time nanoseconds register" bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy" "0,1" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register" line.long 0x8 "ETH_MACPPSI0R,PPS 0 interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval" line.long 0xC "ETH_MACPPSW0R,PPS 0 width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width" line.long 0x10 "ETH_MACPPSTTS1R,PPS 1 target time seconds register" hexmask.long 0x10 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register" line.long 0x14 "ETH_MACPPSTTN1R,PPS 1 target time nanoseconds register" bitfld.long 0x14 31. "TRGTBUSY0,PPS Target Time Register Busy" "0,1" newline hexmask.long 0x14 0.--30. 1. "TTSL0,Target Time Low for PPS Register" line.long 0x18 "ETH_MACPPSI1R,PPS 1 interval register" hexmask.long 0x18 0.--31. 1. "PPSINT0,PPS Output Signal Interval" line.long 0x1C "ETH_MACPPSW1R,PPS 1 width register" hexmask.long 0x1C 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width" group.long 0xBC0++0x13 line.long 0x0 "ETH_MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,Domain Number" newline bitfld.long 0x0 7. "PDRDIS,Disable Peer Delay Response response generation" "0,1" newline bitfld.long 0x0 6. "DRRDIS,Disable PTO Delay Request/Response response generation" "0,1" newline bitfld.long 0x0 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger" "0,1" newline bitfld.long 0x0 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger" "0,1" newline bitfld.long 0x0 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable" "0,1" newline bitfld.long 0x0 1. "ASYNCEN,Automatic PTP SYNC message Enable" "0,1" newline bitfld.long 0x0 0. "PTOEN,PTP Offload Enable" "0,1" line.long 0x4 "ETH_MACSPI0R,PTP Source Port Identity 0 Register" hexmask.long 0x4 0.--31. 1. "SPI0,Source Port Identity 0" line.long 0x8 "ETH_MACSPI1R,PTP Source port identity 1 register" hexmask.long 0x8 0.--31. 1. "SPI1,Source Port Identity 1" line.long 0xC "ETH_MACSPI2R,PTP Source port identity 2 register" hexmask.long.word 0xC 0.--15. 1. "SPI2,Source Port Identity 2" line.long 0x10 "ETH_MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval" newline bitfld.long 0x10 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio" "0: DelayReq generated for every received SYNC,1: DelayReq generated every alternate reception of..,?,?,?,?,?,?" newline hexmask.long.byte 0x10 0.--7. 1. "LSI,Log Sync Interval" group.long 0xC00++0x3 line.long 0x0 "ETH_MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,Counters Reset" "0,1" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm" "0: Weighted round robin (WRR) algorithm,?,?,3: Strict priority (SP) algorithm." newline bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm" "0: Strict priority (SP). Queue 0 has the lowest..,1: Weighted Strict priority (WSP)" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "ETH_MTLISR,Interrupt status Register" bitfld.long 0x0 18. "ESTIS,EST (TAS- 802.1Qbv) Interrupt Status" "0,1" newline bitfld.long 0x0 1. "Q1IS,Queue 1 interrupt status" "0,1" newline bitfld.long 0x0 0. "Q0IS,Queue 0 interrupt status" "0,1" group.long 0xC30++0x3 line.long 0x0 "ETH_MTLRXQDMAMR,Rx Queue and DMA Channel Mapping Register" bitfld.long 0x0 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection" "0,1" newline bitfld.long 0x0 8. "Q1MDMACH,Queue 1 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1" newline bitfld.long 0x0 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection" "0,1" newline bitfld.long 0x0 0. "Q0MDMACH,Queue 0 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1" group.long 0xC40++0x3 line.long 0x0 "ETH_MTLTBSCR,TBS control register" hexmask.long.tbyte 0x0 8.--31. 1. "LEOS,Launch Expiry Offset" newline bitfld.long 0x0 4.--6. "LEGOS,Launch Expiry GSN Offset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "LEOV,Launch expiry offset valid" "0: LEOS field invalid,1: LEOS field valid" newline bitfld.long 0x0 0. "ESTM,EST offset mode" "0: EST offset mode disabled,1: EST offset mode enabled" group.long 0xC50++0xB line.long 0x0 "ETH_MTLESTCR,EST Control Register" hexmask.long.byte 0x0 24.--31. 1. "PTOV,PTP Time Offset Value" newline hexmask.long.word 0x0 12.--23. 1. "CTOV,Current Time Offset Value" newline bitfld.long 0x0 8.--10. "TILS,Time Interval Left Shift Amount" "0: No left shift needed (equal to x1ns),1: Left shift TI by 1 bit (equal to x2ns),2: Left shift TI by 2 bits (equal to x4ns),?,4: Left shift TI by 7 bits (equal to x128ns),?,?,?" newline bitfld.long 0x0 6.--7. "LCSE,Loop Count to report Scheduling Error" "0: 4 iterations,1: 8 iterations,2: 16 iterations,3: 32 iterations" newline bitfld.long 0x0 5. "DFBS,Drop Frames causing Scheduling Error" "0: Don't drop,1: Drop" newline bitfld.long 0x0 4. "DDBF,Do not Drop frames during Frame Size Error" "0: Drop,1: Don't drop" newline bitfld.long 0x0 1. "SSWL,Switch to S/W owned list" "0,1" newline bitfld.long 0x0 0. "EEST,Enable EST" "0: EST disabled,1: EST enabled" line.long 0x4 "ETH_MTLESTECR,EST Extended Control Register" hexmask.long.byte 0x4 0.--5. 1. "OVHD,Overhead Bytes Value" line.long 0x8 "ETH_MTLESTSR,EST Status Register" hexmask.long.byte 0x8 16.--19. 1. "CGSN,Current GCL slot number" newline hexmask.long.byte 0x8 8.--15. 1. "BTRL,BTR Error Loop Count" newline rbitfld.long 0x8 7. "SWOL,S/W owned list" "0: Inactive,1: Active" newline bitfld.long 0x8 4. "CGCE,Constant Gate Control Error" "0: Inactive,1: Active" newline rbitfld.long 0x8 3. "HLBS,Head-Of-Line Blocking due to Scheduling" "0: Inactive,1: Active" newline rbitfld.long 0x8 2. "HLBF,Head-Of-Line Blocking due to Frame Size" "0,1" newline bitfld.long 0x8 1. "BTRE,BTR Error" "0: Inactive,1: Active" newline bitfld.long 0x8 0. "SWLC,Switch to S/W owned list Complete" "0: Inactive,1: Active" group.long 0xC60++0x7 line.long 0x0 "ETH_MTLESTSCHER,EST Schedule Error Register" bitfld.long 0x0 0.--1. "SEQN,Schedule Error Queue Number" "0,1,2,3" line.long 0x4 "ETH_MTLESTFSER,EST Frame size Error Register" bitfld.long 0x4 0.--1. "FEQN,Frame Size Error Queue Number" "0,1,2,3" rgroup.long 0xC68++0x3 line.long 0x0 "ETH_MTLESTFSCR,EST Frame size Capture Register" bitfld.long 0x0 16. "HBFQ,Queue Number of HLBF" "0,1" newline hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF" group.long 0xC70++0x3 line.long 0x0 "ETH_MTLESTIER,EST Interrupt Enable Register" bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE" "0,1" newline bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS" "0,1" newline bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF" "0,1" newline bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error" "0,1" newline bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List" "0,1" group.long 0xC80++0x7 line.long 0x0 "ETH_MTLESTGCLCR,EST Gate Control List Register" hexmask.long.byte 0x0 8.--13. 1. "ADDR,Gate Control List Address:" newline bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select" "0: Bank 0,1: Bank 1" newline bitfld.long 0x0 4. "DBGM,Debug Mode" "0,1" newline bitfld.long 0x0 2. "GCRR,Gate Control Related Registers" "0,1" newline bitfld.long 0x0 1. "R1W0,Read 1 Write 0" "0: Write operation.,1: Read operation" newline bitfld.long 0x0 0. "SRWO,Start Read/Write Operation" "?,1: Indicates the start/progress of a Read/Write.." line.long 0x4 "ETH_MTLESTGCLDR,EST Gate Control List Data Register" hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data" group.long 0xC90++0x7 line.long 0x0 "ETH_MTLFPECSR,FPE Frame Preemption Control Status Register" bitfld.long 0x0 28. "HRS,Hold/Release Status" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was last.." newline bitfld.long 0x0 8.--9. "PEC,Preemption Classification" "0,1,2,3" newline bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size" "0,1,2,3" line.long 0x4 "ETH_MTLFPEAR,FPE Frame Preemption Advance Register" hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance" newline hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance" group.long 0xD00++0x7 line.long 0x0 "ETH_MTLTXQ0OMR,T0 queue 0 operating mode Register" hexmask.long.byte 0x0 16.--19. 1. "TQS,Transmit queue size" newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,1: Enable in AV mode,2: Enabled,?" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" line.long 0x4 "ETH_MTLTXQ0UR,T0 queue 0 underflow register" bitfld.long 0x4 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" rgroup.long 0xD08++0x3 line.long 0x0 "ETH_MTLTXQ0DR,T0 queue 0 debug register" bitfld.long 0x0 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x0 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x0 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x0 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x0 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" rgroup.long 0xD14++0x3 line.long 0x0 "ETH_MTLTXQ0ESR,T0 queue 0 ETS status Register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD18++0x3 line.long 0x0 "ETH_MTLTXQ0QWR,Tx queue 0 quantum weight register" hexmask.long.byte 0x0 0.--6. 1. "ISCQW,Weights" group.long 0xD2C++0xB line.long 0x0 "ETH_MTLQ0ICSR,Queue 0 interrupt control status Register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "ETH_MTLRXQ0OMR,R0 queue 0 operating mode register" hexmask.long.byte 0x4 20.--23. 1. "RQS,Receive Queue Size" newline bitfld.long 0x4 14.--16. "RFD,Threshold for Deactivating Flow Control (in Half-duplex and Full-duplex modes)" "0: Full minus 1 Kbyte,1: Full minus 1.5 Kbyte,?,?,?,?,?,?" newline bitfld.long 0x4 8.--10. "RFA,Threshold for Activating Flow Control (in Half-duplex and Full-duplex)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" line.long 0x8 "ETH_MTLRXQ0MPOCR,R0 queue 0 missed packet and overflow counter register" bitfld.long 0x8 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x8 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x8 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x8 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" rgroup.long 0xD38++0x3 line.long 0x0 "ETH_MTLRXQ0DR,R0 queue 0 debug register" hexmask.long.word 0x0 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x0 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx queue empty,1: Rx queue fill-level below flow-control..,2: Rx queue fill-level above flow-control activate..,3: Rx queue full" newline bitfld.long 0x0 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x0 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD3C++0xB line.long 0x0 "ETH_MTLRXQ0CR,R0 queue 0 control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" line.long 0x4 "ETH_MTLTXQ1OMR,T1 queue 1 operating mode Register" hexmask.long.byte 0x4 16.--19. 1. "TQS,Transmit queue size" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,1: Enable in AV mode,2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue" "0,1" line.long 0x8 "ETH_MTLTXQ1UR,T1 queue 1 underflow register" bitfld.long 0x8 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x8 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" rgroup.long 0xD48++0x3 line.long 0x0 "ETH_MTLTXQ1DR,T1 queue 1 debug register" bitfld.long 0x0 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x0 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x0 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x0 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x0 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" group.long 0xD50++0x3 line.long 0x0 "ETH_MTLTXQ1ECR,Tx queue 1 ETS control Register" bitfld.long 0x0 4.--6. "SLC,Slot Count" "0: 1 Slot,1: 2 Slots,2: 4 Slots,3: 8 Slots,4: 16 Slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control" "0,1" newline bitfld.long 0x0 2. "AVALG,AV Algorithm" "0,1" rgroup.long 0xD54++0x3 line.long 0x0 "ETH_MTLTXQ1ESR,T1 queue 1 ETS status Register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD58++0xF line.long 0x0 "ETH_MTLTXQ1QWR,Tx queue 1 quantum weight register" hexmask.long.word 0x0 0.--13. 1. "ISCQW,IdleSlopeCredit or Weights" line.long 0x4 "ETH_MTLTXQ1SSCR,Tx queue 1 send slope credit Register" hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value" line.long 0x8 "ETH_MTLTXQ1HCR,Tx Queue 1 hiCredit register" hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value" line.long 0xC "ETH_MTLTXQ1LCR,Tx queue 1 loCredit register" hexmask.long 0xC 0.--28. 1. "LC,loCredit Value" group.long 0xD6C++0xB line.long 0x0 "ETH_MTLQ1ICSR,Queue 1 interrupt control status Register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "ETH_MTLRXQ1OMR,R1 queue 1 operating mode register" hexmask.long.byte 0x4 20.--23. 1. "RQS,Receive Queue Size" newline bitfld.long 0x4 14.--16. "RFD,Threshold for Deactivating Flow Control (in Half-duplex and Full-duplex modes)" "0: Full minus 1 Kbyte,1: Full minus 1.5 Kbyte,?,?,?,?,?,?" newline bitfld.long 0x4 8.--10. "RFA,Threshold for Activating Flow Control (in Half-duplex and Full-duplex)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" line.long 0x8 "ETH_MTLRXQ1MPOCR,R1 queue 1 missed packet and overflow counter register" bitfld.long 0x8 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x8 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x8 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x8 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" rgroup.long 0xD78++0x3 line.long 0x0 "ETH_MTLRXQ1DR,R1 queue 1 debug register" hexmask.long.word 0x0 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x0 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx queue empty,1: Rx queue fill-level below flow-control..,2: Rx queue fill-level above flow-control activate..,3: Rx queue full" newline bitfld.long 0x0 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x0 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD7C++0x3 line.long 0x0 "ETH_MTLRXQ1CR,R1 queue 1 control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" group.long 0x1000++0x7 line.long 0x0 "ETH_DMAMR,DMA mode register" bitfld.long 0x0 16.--17. "INTM,Interrupt Mode" "0,1,2,3" newline bitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" newline bitfld.long 0x0 8. "DSPW,Descriptor Posted Write" "0: The descriptor writes are always non-posted.,1: The descriptor writes are non-posted only when.." newline rbitfld.long 0x0 2.--4. "TAA,Transmit Arbitration Algorithm" "0: Fixed priority. In fixed priority Channel 0 has..,1: Weighted Strict priority (WSP),2: Weighted Round-Robin (WRR),?,?,?,?,?" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "ETH_DMASBMR,System bus mode register" bitfld.long 0x4 31. "EN_LPI,Enable Low Power Interface (LPI)" "0,1" newline bitfld.long 0x4 30. "LPI_XIT_PKT,Unlock on Magic Packet or Remote wake-up packet" "0,1" newline bitfld.long 0x4 24.--25. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit" "0,1,2,3" newline bitfld.long 0x4 16.--17. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit" "0,1,2,3" newline bitfld.long 0x4 13. "ONEKBBE,1 Kbyte Boundary Crossing Enable for the AXI Master" "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" newline bitfld.long 0x4 10. "AALE,Automatic AXI LPI enable" "0,1" newline bitfld.long 0x4 7. "BLEN256,AXI Burst Length 256" "0,1" newline bitfld.long 0x4 6. "BLEN128,AXI Burst Length 128" "0,1" newline bitfld.long 0x4 5. "BLEN64,AXI Burst Length 64" "0,1" newline bitfld.long 0x4 4. "BLEN32,AXI Burst Length 32" "0,1" newline bitfld.long 0x4 3. "BLEN16,AXI Burst Length 16" "0,1" newline bitfld.long 0x4 2. "BLEN8,AXI Burst Length 8" "0,1" newline bitfld.long 0x4 1. "BLEN4,AXI Burst Length 4" "0,1" newline bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "ETH_DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" newline bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status" "0,1" newline bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status" "0,1" line.long 0x4 "ETH_DMADSR,Debug status register" hexmask.long.byte 0x4 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State" newline hexmask.long.byte 0x4 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State" newline hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State" newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State" newline bitfld.long 0x4 1. "AXRHSTS,AXI Master Read Channel Status" "0,1" newline bitfld.long 0x4 0. "AXWHSTS,AXI Master Write Channel" "0,1" group.long 0x1020++0xB line.long 0x0 "ETH_DMAA4TXACR,AXI4 transmit channel ACE control register" hexmask.long.byte 0x0 16.--19. 1. "THC,Transmit DMA First Packet Buffer or TSO Header Cache Control" newline hexmask.long.byte 0x0 8.--11. 1. "TEC,Transmit DMA Extended Packet Buffer or TSO Payload Cache Control" newline hexmask.long.byte 0x0 0.--3. 1. "TDRC,Transmit DMA Read Descriptor Cache Control" line.long 0x4 "ETH_DMAA4RXACR,AXI4 receive channel ACE control register" hexmask.long.byte 0x4 24.--27. 1. "RDC,Receive DMA Buffer Cache Control" newline hexmask.long.byte 0x4 16.--19. 1. "RHC,Receive DMA Header Cache Control" newline hexmask.long.byte 0x4 8.--11. 1. "RPC,Receive DMA Payload Cache Control" newline hexmask.long.byte 0x4 0.--3. 1. "RDWC,Receive DMA Write Descriptor Cache Control" line.long 0x8 "ETH_DMAA4DACR,AXI4 descriptor ACE control register" hexmask.long.byte 0x8 8.--11. 1. "RDRC,Receive DMA Read Descriptor Cache control" newline bitfld.long 0x8 4.--5. "TDWD,Transmit DMA Write Descriptor Domain control" "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "TDWC,Transmit DMA Write Descriptor Cache control" group.long 0x1040++0x3 line.long 0x0 "ETH_DMALPIEI,AXI4 LPI Entry Interval register" hexmask.long.byte 0x0 0.--3. 1. "LPIEI,LPI Entry Interval" group.long 0x1050++0x3 line.long 0x0 "ETH_DMATBSCTRL0R,DMA TBS control register 0" hexmask.long.tbyte 0x0 8.--31. 1. "FTOS,Fetch time offset" newline bitfld.long 0x0 4.--6. "FGOS,Fetch GSN offset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "FTOV,Fetch time offset valid" "0: Fetch time offset invalid,1: Fetch time offset valid" group.long 0x1100++0xB line.long 0x0 "ETH_DMAC0CR,Channel 0 control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "ETH_DMAC0TXCR,Channel 0 transmit control register" bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable" "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement" "0,1" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline rbitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "ETH_DMAC0RXCR,Channel 0 receive control register" bitfld.long 0x8 31. "RPF,DMA Rx Channel x Packet Flush" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS." newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "ETH_DMAC0TXDLAR,Channel 0 T0 descriptor list address register" hexmask.long 0x0 0.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "ETH_DMAC0RXDLAR,Channel 0 Rx descriptor list address register" hexmask.long 0x0 0.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "ETH_DMAC0TXDTPR,Channel 0 T0 descriptor tail pointer register" hexmask.long 0x4 0.--31. 1. "TDT,Transmit Descriptor Tail Pointer" group.long 0x1128++0x17 line.long 0x0 "ETH_DMAC0RXDTPR,Channel 0 R0 descriptor tail pointer register" hexmask.long 0x0 0.--31. 1. "RDT,Receive Descriptor Tail Pointer" line.long 0x4 "ETH_DMAC0TXRLR,Channel 0 T0 descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "ETH_DMAC0RXRLR,Channel 0 R0 descriptor ring length register" hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size" newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "ETH_DMAC0IER,Channel 0 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0,1" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "0,1" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "ETH_DMAC0RXIWTR,Channel 0 R0 interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" line.long 0x14 "ETH_DMAC0SFCSR,Channel 0 slot function control status register" hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value" newline bitfld.long 0x14 1. "ASC,Advance Slot Check" "0,1" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison" "0,1" rgroup.long 0x1144++0x3 line.long 0x0 "ETH_DMAC0CATXDR,Channel 0 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x114C++0x3 line.long 0x0 "ETH_DMAC0CARXDR,Channel 0 current application receive descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x1154++0x3 line.long 0x0 "ETH_DMAC0CATXBR,Channel 0 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x115C++0x3 line.long 0x0 "ETH_DMAC0CARXBR,Channel 0 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x1160++0x7 line.long 0x0 "ETH_DMAC0SR,Channel 0 status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" line.long 0x4 "ETH_DMAC0MFCR,Channel 0 missed frame count register" bitfld.long 0x4 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0x1180++0xB line.long 0x0 "ETH_DMAC1CR,Channel 1 control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "ETH_DMAC1TXCR,Channel 1 transmit control register" bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable" "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement" "0,1" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline rbitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "ETH_DMAC1RXCR,Channel 1 receive control register" bitfld.long 0x8 31. "RPF,DMA Rx Channel x Packet Flush" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS." newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1194++0x3 line.long 0x0 "ETH_DMAC1TXDLAR,Channel 1 T1 descriptor list address register" hexmask.long 0x0 0.--31. 1. "TDESLA,Start of Transmit List" group.long 0x11A0++0x3 line.long 0x0 "ETH_DMAC1TXDTPR,Channel 1 T1 descriptor tail pointer register" hexmask.long 0x0 0.--31. 1. "TDT,Transmit Descriptor Tail Pointer" group.long 0x11A8++0x17 line.long 0x0 "ETH_DMAC1RXDTPR,Channel 1 R1 descriptor tail pointer register" hexmask.long 0x0 0.--31. 1. "RDT,Receive Descriptor Tail Pointer" line.long 0x4 "ETH_DMAC1TXRLR,Channel 1 T1 descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "ETH_DMAC1RXRLR,Channel 1 R1 descriptor ring length register" hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size" newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "ETH_DMAC1IER,Channel 1 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0,1" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "0,1" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "ETH_DMAC1RXIWTR,Channel 1 R1 interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" line.long 0x14 "ETH_DMAC1SFCSR,Channel 1 slot function control status register" hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value" newline bitfld.long 0x14 1. "ASC,Advance Slot Check" "0,1" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison" "0,1" rgroup.long 0x11C4++0x3 line.long 0x0 "ETH_DMAC1CATXDR,Channel 1 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x11CC++0x3 line.long 0x0 "ETH_DMAC1CARXDR,Channel 1 current application receive descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x11D4++0x3 line.long 0x0 "ETH_DMAC1CATXBR,Channel 1 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x11DC++0x3 line.long 0x0 "ETH_DMAC1CARXBR,Channel 1 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x11E0++0x7 line.long 0x0 "ETH_DMAC1SR,Channel 1 status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" line.long 0x4 "ETH_DMAC1MFCR,Channel 1 missed frame count register" bitfld.long 0x4 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "MFC,Dropped Packet Counters" tree.end tree.end tree "EXTI (External Interrupt/Event)" base ad:0x0 tree "EXTI" base ad:0x46025000 group.long 0x0++0x1B line.long 0x0 "EXTI_RTSR1,EXTI rising trigger selection register" bitfld.long 0x0 21. "RT21,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 20. "RT20,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit of configurable event input x" "0,1" line.long 0x4 "EXTI_FTSR1,EXTI falling trigger selection register" bitfld.long 0x4 21. "FT21,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 20. "FT20,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable event input x" "0,1" line.long 0x8 "EXTI_SWIER1,EXTI software interrupt event register" bitfld.long 0x8 21. "SWI21,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 20. "SWI20,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." newline bitfld.long 0x8 15. "SWI15,Software interrupt on event x" "0,1" bitfld.long 0x8 14. "SWI14,Software interrupt on event x" "0,1" newline bitfld.long 0x8 13. "SWI13,Software interrupt on event x" "0,1" bitfld.long 0x8 12. "SWI12,Software interrupt on event x" "0,1" newline bitfld.long 0x8 11. "SWI11,Software interrupt on event x" "0,1" bitfld.long 0x8 10. "SWI10,Software interrupt on event x" "0,1" newline bitfld.long 0x8 9. "SWI9,Software interrupt on event x" "0,1" bitfld.long 0x8 8. "SWI8,Software interrupt on event x" "0,1" newline bitfld.long 0x8 7. "SWI7,Software interrupt on event x" "0,1" bitfld.long 0x8 6. "SWI6,Software interrupt on event x" "0,1" newline bitfld.long 0x8 5. "SWI5,Software interrupt on event x" "0,1" bitfld.long 0x8 4. "SWI4,Software interrupt on event x" "0,1" newline bitfld.long 0x8 3. "SWI3,Software interrupt on event x" "0,1" bitfld.long 0x8 2. "SWI2,Software interrupt on event x" "0,1" newline bitfld.long 0x8 1. "SWI1,Software interrupt on event x" "0,1" bitfld.long 0x8 0. "SWI0,Software interrupt on event x" "0,1" line.long 0xC "EXTI_RPR1,EXTI rising edge pending register" bitfld.long 0xC 21. "RPIF21,Configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 20. "RPIF20,Configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 15. "RPIF15,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 14. "RPIF14,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 13. "RPIF13,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 12. "RPIF12,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 11. "RPIF11,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 10. "RPIF10,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 9. "RPIF9,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 8. "RPIF8,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 7. "RPIF7,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 6. "RPIF6,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 5. "RPIF5,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 4. "RPIF4,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 3. "RPIF3,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 2. "RPIF2,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 1. "RPIF1,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 0. "RPIF0,Configurable event input x rising edge pending bit" "0,1" line.long 0x10 "EXTI_FPR1,EXTI falling edge pending register" bitfld.long 0x10 21. "FPIF21,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 20. "FPIF20,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 15. "FPIF15,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 14. "FPIF14,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 13. "FPIF13,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 12. "FPIF12,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 11. "FPIF11,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 10. "FPIF10,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 9. "FPIF9,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 8. "FPIF8,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 7. "FPIF7,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 6. "FPIF6,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 5. "FPIF5,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 4. "FPIF4,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 3. "FPIF3,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 2. "FPIF2,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 1. "FPIF1,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 0. "FPIF0,Configurable event input x rising edge pending bit" "0,1" line.long 0x14 "EXTI_SECCFGR1,EXTI security configuration register" bitfld.long 0x14 31. "SEC31,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 30. "SEC30,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 29. "SEC29,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 28. "SEC28,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 27. "SEC27,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 26. "SEC26,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 25. "SEC25,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 24. "SEC24,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 23. "SEC23,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 22. "SEC22,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 21. "SEC21,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 20. "SEC20,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 19. "SEC19,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 18. "SEC18,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 17. "SEC17,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 15. "SEC15,Security enable on event input x" "0,1" newline bitfld.long 0x14 14. "SEC14,Security enable on event input x" "0,1" bitfld.long 0x14 13. "SEC13,Security enable on event input x" "0,1" newline bitfld.long 0x14 12. "SEC12,Security enable on event input x" "0,1" bitfld.long 0x14 11. "SEC11,Security enable on event input x" "0,1" newline bitfld.long 0x14 10. "SEC10,Security enable on event input x" "0,1" bitfld.long 0x14 9. "SEC9,Security enable on event input x" "0,1" newline bitfld.long 0x14 8. "SEC8,Security enable on event input x" "0,1" bitfld.long 0x14 7. "SEC7,Security enable on event input x" "0,1" newline bitfld.long 0x14 6. "SEC6,Security enable on event input x" "0,1" bitfld.long 0x14 5. "SEC5,Security enable on event input x" "0,1" newline bitfld.long 0x14 4. "SEC4,Security enable on event input x" "0,1" bitfld.long 0x14 3. "SEC3,Security enable on event input x" "0,1" newline bitfld.long 0x14 2. "SEC2,Security enable on event input x" "0,1" bitfld.long 0x14 1. "SEC1,Security enable on event input x" "0,1" newline bitfld.long 0x14 0. "SEC0,Security enable on event input x" "0,1" line.long 0x18 "EXTI_PRIVCFGR1,EXTI privilege configuration register" bitfld.long 0x18 31. "PRIV31,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 30. "PRIV30,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 29. "PRIV29,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 28. "PRIV28,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 27. "PRIV27,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 26. "PRIV26,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 25. "PRIV25,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 24. "PRIV24,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 23. "PRIV23,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 22. "PRIV22,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 21. "PRIV21,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 20. "PRIV20,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 19. "PRIV19,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 18. "PRIV18,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 17. "PRIV17,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 15. "PRIV15,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 14. "PRIV14,Privilege enable on event input x" "0,1" bitfld.long 0x18 13. "PRIV13,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 12. "PRIV12,Privilege enable on event input x" "0,1" bitfld.long 0x18 11. "PRIV11,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 10. "PRIV10,Privilege enable on event input x" "0,1" bitfld.long 0x18 9. "PRIV9,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 8. "PRIV8,Privilege enable on event input x" "0,1" bitfld.long 0x18 7. "PRIV7,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 6. "PRIV6,Privilege enable on event input x" "0,1" bitfld.long 0x18 5. "PRIV5,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 4. "PRIV4,Privilege enable on event input x" "0,1" bitfld.long 0x18 3. "PRIV3,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 2. "PRIV2,Privilege enable on event input x" "0,1" bitfld.long 0x18 1. "PRIV1,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 0. "PRIV0,Privilege enable on event input x" "0,1" group.long 0x20++0x1B line.long 0x0 "EXTI_RTSR2,EXTI rising trigger selection register" bitfld.long 0x0 24. "RT56,Rising trigger event configuration bit of configurable event input 56" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and Interrupt).." bitfld.long 0x0 22. "RT54,Rising trigger event configuration bit of configurable event input 54" "0,1" newline bitfld.long 0x0 19. "RT51,Rising trigger event configuration bit of configurable event input 51" "0,1" bitfld.long 0x0 8. "RT40,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 7. "RT39,Rising trigger event configuration bit of configurable event input x" "0,1" line.long 0x4 "EXTI_FTSR2,EXTI falling trigger selection register" bitfld.long 0x4 24. "FT56,Falling trigger event configuration bit of configurable event input 56" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 22. "FT54,Falling trigger event configuration bit of configurable event input 54" "0,1" newline bitfld.long 0x4 19. "FT51,Falling trigger event configuration bit of configurable event input 51" "0,1" bitfld.long 0x4 8. "FT40,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 7. "FT39,Falling trigger event configuration bit of configurable event input x" "0,1" line.long 0x8 "EXTI_SWIER2,EXTI software interrupt event register" bitfld.long 0x8 24. "SWI56,Software interrupt on event 56" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 22. "SWI54,Software interrupt on event 54" "0,1" newline bitfld.long 0x8 19. "SWI51,Software interrupt on event 51" "0,1" bitfld.long 0x8 8. "SWI40,Software interrupt on event x" "0,1" newline bitfld.long 0x8 7. "SWI39,Software interrupt on event x" "0,1" line.long 0xC "EXTI_RPR2,EXTI rising edge pending register" bitfld.long 0xC 24. "RPIF56,Configurable event input 56 rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 22. "RPIF54,Configurable event input 54 rising edge pending bit" "0,1" newline bitfld.long 0xC 19. "RPIF51,Configurable event input 51 rising edge pending bit" "0,1" bitfld.long 0xC 8. "RPIF40,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 7. "RPIF39,Configurable event input x rising edge pending bit" "0,1" line.long 0x10 "EXTI_FPR2,EXTI falling edge pending register" bitfld.long 0x10 24. "FPIF56,Configurable event input 56 falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 22. "FPIF54,Configurable event input 54 falling edge pending bit" "0,1" newline bitfld.long 0x10 19. "FPIF51,Configurable event input 51 falling edge pending bit" "0,1" bitfld.long 0x10 8. "FPIF40,Configurable event input x falling edge pending bit" "0,1" newline bitfld.long 0x10 7. "FPIF39,Configurable event input x falling edge pending bit" "0,1" line.long 0x14 "EXTI_SECCFGR2,EXTI security enable register" bitfld.long 0x14 31. "SEC63,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 30. "SEC62,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 29. "SEC61,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 28. "SEC60,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 26. "SEC58,Security enable on event input x" "0,1" bitfld.long 0x14 25. "SEC57,Security enable on event input x" "0,1" newline bitfld.long 0x14 24. "SEC56,Security enable on event input x" "0,1" bitfld.long 0x14 23. "SEC55,Security enable on event input x" "0,1" newline bitfld.long 0x14 22. "SEC54,Security enable on event input x" "0,1" bitfld.long 0x14 21. "SEC53,Security enable on event input x" "0,1" newline bitfld.long 0x14 20. "SEC52,Security enable on event input x" "0,1" bitfld.long 0x14 19. "SEC51,Security enable on event input x" "0,1" newline bitfld.long 0x14 18. "SEC50,Security enable on event input x" "0,1" bitfld.long 0x14 17. "SEC49,Security enable on event input x" "0,1" newline bitfld.long 0x14 16. "SEC48,Security enable on event input x" "0,1" bitfld.long 0x14 15. "SEC47,Security enable on event input x" "0,1" newline bitfld.long 0x14 14. "SEC46,Security enable on event input x" "0,1" bitfld.long 0x14 13. "SEC45,Security enable on event input x" "0,1" newline bitfld.long 0x14 12. "SEC44,Security enable on event input x" "0,1" bitfld.long 0x14 11. "SEC43,Security enable on event input x" "0,1" newline bitfld.long 0x14 10. "SEC42,Security enable on event input x" "0,1" bitfld.long 0x14 9. "SEC41,Security enable on event input x" "0,1" newline bitfld.long 0x14 8. "SEC40,Security enable on event input x" "0,1" bitfld.long 0x14 7. "SEC39,Security enable on event input x" "0,1" newline bitfld.long 0x14 6. "SEC38,Security enable on event input x" "0,1" bitfld.long 0x14 5. "SEC37,Security enable on event input x" "0,1" newline bitfld.long 0x14 4. "SEC36,Security enable on event input x" "0,1" bitfld.long 0x14 3. "SEC35,Security enable on event input x" "0,1" newline bitfld.long 0x14 2. "SEC34,Security enable on event input x" "0,1" bitfld.long 0x14 1. "SEC33,Security enable on event input x" "0,1" newline bitfld.long 0x14 0. "SEC32,Security enable on event input x" "0,1" line.long 0x18 "EXTI_PRIVCFGR2,EXTI privilege enable register" bitfld.long 0x18 31. "PRIV63,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 30. "PRIV62,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 29. "PRIV61,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 28. "PRIV60,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 26. "PRIV58,Privilege enable on event input x" "0,1" bitfld.long 0x18 25. "PRIV57,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 24. "PRIV56,Privilege enable on event input x" "0,1" bitfld.long 0x18 23. "PRIV55,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 22. "PRIV54,Privilege enable on event input x" "0,1" bitfld.long 0x18 21. "PRIV53,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 20. "PRIV52,Privilege enable on event input x" "0,1" bitfld.long 0x18 19. "PRIV51,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 18. "PRIV50,Privilege enable on event input x" "0,1" bitfld.long 0x18 17. "PRIV49,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 16. "PRIV48,Privilege enable on event input x" "0,1" bitfld.long 0x18 15. "PRIV47,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 14. "PRIV46,Privilege enable on event input x" "0,1" bitfld.long 0x18 13. "PRIV45,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 12. "PRIV44,Privilege enable on event input x" "0,1" bitfld.long 0x18 11. "PRIV43,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 10. "PRIV42,Privilege enable on event input x" "0,1" bitfld.long 0x18 9. "PRIV41,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 8. "PRIV40,Privilege enable on event input x" "0,1" bitfld.long 0x18 7. "PRIV39,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 6. "PRIV38,Privilege enable on event input x" "0,1" bitfld.long 0x18 5. "PRIV37,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 4. "PRIV36,Privilege enable on event input x" "0,1" bitfld.long 0x18 3. "PRIV35,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 2. "PRIV34,Privilege enable on event input x" "0,1" bitfld.long 0x18 1. "PRIV33,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 0. "PRIV32,Privilege enable on event input x" "0,1" group.long 0x40++0x1B line.long 0x0 "EXTI_RTSR3,EXTI rising trigger selection register" bitfld.long 0x0 10. "RT74,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 9. "RT73,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 8. "RT72,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 7. "RT71,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 6. "RT70,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 5. "RT69,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 4. "RT68,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 2. "RT66,Rising trigger event configuration bit of configurable event input 66" "0,1" line.long 0x4 "EXTI_FTSR3,EXTI falling trigger selection register" bitfld.long 0x4 10. "FT74,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 9. "FT73,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 8. "FT72,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 7. "FT71,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 6. "FT70,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 5. "FT69,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 4. "FT68,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 2. "FT66,Falling trigger event configuration bit of configurable event input 66" "0,1" line.long 0x8 "EXTI_SWIER3,EXTI software interrupt event register" bitfld.long 0x8 10. "SWI74,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 9. "SWI73,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." newline bitfld.long 0x8 8. "SWI72,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 7. "SWI71,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." newline bitfld.long 0x8 6. "SWI70,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 5. "SWI69,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." newline bitfld.long 0x8 4. "SWI68,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 2. "SWI66,Software interrupt on event 66" "0,1" line.long 0xC "EXTI_RPR3,EXTI rising edge pending register" bitfld.long 0xC 10. "RPIF74,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 9. "RPIF73,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 8. "RPIF72,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 7. "RPIF71,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 6. "RPIF70,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 5. "RPIF69,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 4. "RPIF68,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 2. "RPIF66,configurable event input 66rising edge pending bit" "0,1" line.long 0x10 "EXTI_FPR3,EXTI falling edge pending register" bitfld.long 0x10 10. "FPIF74,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 9. "FPIF73,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 8. "FPIF72,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 7. "FPIF71,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 6. "FPIF70,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 5. "FPIF69,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 4. "FPIF68,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 2. "FPIF66,configurable event input 66 falling edge pending bit" "0,1" line.long 0x14 "EXTI_SECCFGR3,EXTI security enable register" bitfld.long 0x14 13. "SEC77,Security enable on event input 77" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 10. "SEC74,Security enable on event input x" "0,1" newline bitfld.long 0x14 9. "SEC73,Security enable on event input x" "0,1" bitfld.long 0x14 8. "SEC72,Security enable on event input x" "0,1" newline bitfld.long 0x14 7. "SEC71,Security enable on event input x" "0,1" bitfld.long 0x14 6. "SEC70,Security enable on event input x" "0,1" newline bitfld.long 0x14 5. "SEC69,Security enable on event input x" "0,1" bitfld.long 0x14 4. "SEC68,Security enable on event input x" "0,1" newline bitfld.long 0x14 2. "SEC66,Security enable on event input x" "0,1" bitfld.long 0x14 1. "SEC65,Security enable on event input x" "0,1" newline bitfld.long 0x14 0. "SEC64,Security enable on event input x" "0,1" line.long 0x18 "EXTI_PRIVCFGR3,EXTI privilege enable register" bitfld.long 0x18 13. "PRIV77,Privilege enable on event input 77" "0: Event privilege disabled (unprivileged,1: Event privilege enabled (privileged)" bitfld.long 0x18 10. "PRIV74,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 9. "PRIV73,Privilege enable on event input x" "0,1" bitfld.long 0x18 8. "PRIV72,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 7. "PRIV71,Privilege enable on event input x" "0,1" bitfld.long 0x18 6. "PRIV70,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 5. "PRIV69,Privilege enable on event input x" "0,1" bitfld.long 0x18 4. "PRIV68,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 2. "PRIV66,Privilege enable on event input x" "0,1" bitfld.long 0x18 1. "PRIV65,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 0. "PRIV64,Privilege enable on event input x" "0,1" group.long 0x60++0x13 line.long 0x0 "EXTI_EXTICR1,EXTI external interrupt selection register 1" hexmask.long.byte 0x0 24.--31. 1. "EXTI3,EXTI3 GPIO port selection" hexmask.long.byte 0x0 16.--23. 1. "EXTI2,EXTI2 GPIO port selection" newline hexmask.long.byte 0x0 8.--15. 1. "EXTI1,EXTI1 GPIO port selection" hexmask.long.byte 0x0 0.--7. 1. "EXTI0,EXTI0 GPIO port selection." line.long 0x4 "EXTI_EXTICR2,EXTI external interrupt selection register 2" hexmask.long.byte 0x4 24.--31. 1. "EXTI7,EXTI7 GPIO port selection." hexmask.long.byte 0x4 16.--23. 1. "EXTI6,EXTI6 GPIO port selection." newline hexmask.long.byte 0x4 8.--15. 1. "EXTI5,EXTI5 GPIO port selection." hexmask.long.byte 0x4 0.--7. 1. "EXTI4,EXTI4 GPIO port selection." line.long 0x8 "EXTI_EXTICR3,EXTI external interrupt selection register 3" hexmask.long.byte 0x8 24.--31. 1. "EXTI11,EXTI11 GPIO port selection." hexmask.long.byte 0x8 16.--23. 1. "EXTI10,EXTI10 GPIO port selection." newline hexmask.long.byte 0x8 8.--15. 1. "EXTI9,EXTI9 GPIO port selection." hexmask.long.byte 0x8 0.--7. 1. "EXTI8,EXTI8 GPIO port selection." line.long 0xC "EXTI_EXTICR4,EXTI external interrupt selection register 4" hexmask.long.byte 0xC 24.--31. 1. "EXTI15,EXTI15 GPIO port selection." hexmask.long.byte 0xC 16.--23. 1. "EXTI14,EXTI14 GPIO port selection." newline hexmask.long.byte 0xC 8.--15. 1. "EXTI13,EXTI13 GPIO port selection." hexmask.long.byte 0xC 0.--7. 1. "EXTI12,EXTI12 GPIO port selection." line.long 0x10 "EXTI_LOCKR,EXTI lock register" bitfld.long 0x10 0. "GLOCK,Global security privilege EXTI_SECCFGRx/PRIVCFGRx" "0: Security privilege open can be modified.,1: Security privilege locked can no longer be.." group.long 0x80++0x7 line.long 0x0 "EXTI_IMR1,EXTI CPU wake-up with interrupt mask register 1" bitfld.long 0x0 31. "IM31,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 30. "IM30,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 29. "IM29,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 28. "IM28,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 27. "IM27,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 26. "IM26,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 25. "IM25,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 24. "IM24,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 23. "IM23,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 22. "IM22,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 21. "IM21,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 20. "IM20,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 19. "IM19,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 18. "IM18,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 17. "IM17,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 15. "IM15,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 14. "IM14,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 13. "IM13,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 12. "IM12,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 11. "IM11,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 10. "IM10,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 9. "IM9,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 8. "IM8,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 7. "IM7,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 6. "IM6,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 5. "IM5,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 4. "IM4,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 3. "IM3,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 2. "IM2,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 1. "IM1,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 0. "IM0,CPU wake-up with interrupt mask on event input x" "0,1" line.long 0x4 "EXTI_EMR1,EXTI CPU wake-up with event mask register 1" bitfld.long 0x4 31. "EM31,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 30. "EM30,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 29. "EM29,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 28. "EM28,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 27. "EM27,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 26. "EM26,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 25. "EM25,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 24. "EM24,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 23. "EM23,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 22. "EM22,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 21. "EM21,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 20. "EM20,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 19. "EM19,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 18. "EM18,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 17. "EM17,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 15. "EM15,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 14. "EM14,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 13. "EM13,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 12. "EM12,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 11. "EM11,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 10. "EM10,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 9. "EM9,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 8. "EM8,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 7. "EM7,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 6. "EM6,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 5. "EM5,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 4. "EM4,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 3. "EM3,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 2. "EM2,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 1. "EM1,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 0. "EM0,CPU wake-up with interrupt mask on event input x" "0,1" group.long 0x90++0x7 line.long 0x0 "EXTI_IMR2,EXTI CPU wake-up with interrupt mask register 2" bitfld.long 0x0 31. "IM63,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 30. "IM62,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 29. "IM61,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 28. "IM60,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 26. "IM58,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 25. "IM57,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 24. "IM56,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 23. "IM55,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 22. "IM54,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 21. "IM53,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 20. "IM52,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 19. "IM51,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 18. "IM50,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 17. "IM49,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 16. "IM48,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 15. "IM47,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 14. "IM46,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 13. "IM45,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 12. "IM44,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 11. "IM43,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 10. "IM42,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 9. "IM41,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 8. "IM40,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 7. "IM39,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 6. "IM38,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 5. "IM37,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 4. "IM36,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 3. "IM35,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 2. "IM34,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 1. "IM33,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 0. "IM32,CPU wake-up with interrupt mask on event input x" "0,1" line.long 0x4 "EXTI_EMR2,EXTI CPU wake-up with event mask register 2" bitfld.long 0x4 31. "EM63,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 30. "EM62,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 29. "EM61,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 28. "EM60,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 26. "EM58,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 25. "EM57,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 24. "EM56,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 23. "EM55,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 22. "EM54,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 21. "EM53,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 20. "EM52,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 19. "EM51,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 18. "EM50,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 17. "EM49,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 16. "EM48,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 15. "EM47,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 14. "EM46,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 13. "EM45,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 12. "EM44,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 11. "EM43,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 10. "EM42,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 9. "EM41,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 8. "EM40,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 7. "EM39,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 6. "EM38,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 5. "EM37,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 4. "EM36,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 3. "EM35,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 2. "EM34,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 1. "EM33,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 0. "EM32,CPU wake-up with interrupt mask on event input x" "0,1" group.long 0xA0++0x7 line.long 0x0 "EXTI_IMR3,EXTI CPU wake-up with interrupt mask register 3" bitfld.long 0x0 13. "IM77,CPU wake-up with interrupt mask on event input 77" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 10. "IM74,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 9. "IM73,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 8. "IM72,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 7. "IM71,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 6. "IM70,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 5. "IM69,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 4. "IM68,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 2. "IM66,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 1. "IM65,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 0. "IM64,CPU wake-up with interrupt mask on event input x" "0,1" line.long 0x4 "EXTI_EMR3,EXTI CPU wake-up with event mask register 3" bitfld.long 0x4 13. "EM77,CPU wake-up with event on event input 77" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 10. "EM74,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 9. "EM73,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 8. "EM72,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 7. "EM71,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 6. "EM70,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 5. "EM69,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 4. "EM68,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 2. "EM66,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 1. "EM65,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 0. "EM64,CPU wake-up with interrupt mask on event input x" "0,1" tree.end tree "EXTI_S" base ad:0x56025000 group.long 0x0++0x1B line.long 0x0 "EXTI_RTSR1,EXTI rising trigger selection register" bitfld.long 0x0 21. "RT21,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 20. "RT20,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit of configurable event input x" "0,1" line.long 0x4 "EXTI_FTSR1,EXTI falling trigger selection register" bitfld.long 0x4 21. "FT21,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 20. "FT20,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable event input x" "0,1" bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable event input x" "0,1" line.long 0x8 "EXTI_SWIER1,EXTI software interrupt event register" bitfld.long 0x8 21. "SWI21,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 20. "SWI20,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." newline bitfld.long 0x8 15. "SWI15,Software interrupt on event x" "0,1" bitfld.long 0x8 14. "SWI14,Software interrupt on event x" "0,1" newline bitfld.long 0x8 13. "SWI13,Software interrupt on event x" "0,1" bitfld.long 0x8 12. "SWI12,Software interrupt on event x" "0,1" newline bitfld.long 0x8 11. "SWI11,Software interrupt on event x" "0,1" bitfld.long 0x8 10. "SWI10,Software interrupt on event x" "0,1" newline bitfld.long 0x8 9. "SWI9,Software interrupt on event x" "0,1" bitfld.long 0x8 8. "SWI8,Software interrupt on event x" "0,1" newline bitfld.long 0x8 7. "SWI7,Software interrupt on event x" "0,1" bitfld.long 0x8 6. "SWI6,Software interrupt on event x" "0,1" newline bitfld.long 0x8 5. "SWI5,Software interrupt on event x" "0,1" bitfld.long 0x8 4. "SWI4,Software interrupt on event x" "0,1" newline bitfld.long 0x8 3. "SWI3,Software interrupt on event x" "0,1" bitfld.long 0x8 2. "SWI2,Software interrupt on event x" "0,1" newline bitfld.long 0x8 1. "SWI1,Software interrupt on event x" "0,1" bitfld.long 0x8 0. "SWI0,Software interrupt on event x" "0,1" line.long 0xC "EXTI_RPR1,EXTI rising edge pending register" bitfld.long 0xC 21. "RPIF21,Configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 20. "RPIF20,Configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 15. "RPIF15,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 14. "RPIF14,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 13. "RPIF13,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 12. "RPIF12,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 11. "RPIF11,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 10. "RPIF10,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 9. "RPIF9,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 8. "RPIF8,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 7. "RPIF7,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 6. "RPIF6,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 5. "RPIF5,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 4. "RPIF4,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 3. "RPIF3,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 2. "RPIF2,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 1. "RPIF1,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0xC 0. "RPIF0,Configurable event input x rising edge pending bit" "0,1" line.long 0x10 "EXTI_FPR1,EXTI falling edge pending register" bitfld.long 0x10 21. "FPIF21,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 20. "FPIF20,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 15. "FPIF15,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 14. "FPIF14,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 13. "FPIF13,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 12. "FPIF12,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 11. "FPIF11,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 10. "FPIF10,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 9. "FPIF9,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 8. "FPIF8,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 7. "FPIF7,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 6. "FPIF6,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 5. "FPIF5,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 4. "FPIF4,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 3. "FPIF3,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 2. "FPIF2,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0x10 1. "FPIF1,Configurable event input x rising edge pending bit" "0,1" bitfld.long 0x10 0. "FPIF0,Configurable event input x rising edge pending bit" "0,1" line.long 0x14 "EXTI_SECCFGR1,EXTI security configuration register" bitfld.long 0x14 31. "SEC31,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 30. "SEC30,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 29. "SEC29,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 28. "SEC28,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 27. "SEC27,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 26. "SEC26,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 25. "SEC25,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 24. "SEC24,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 23. "SEC23,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 22. "SEC22,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 21. "SEC21,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 20. "SEC20,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 19. "SEC19,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 18. "SEC18,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 17. "SEC17,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 15. "SEC15,Security enable on event input x" "0,1" newline bitfld.long 0x14 14. "SEC14,Security enable on event input x" "0,1" bitfld.long 0x14 13. "SEC13,Security enable on event input x" "0,1" newline bitfld.long 0x14 12. "SEC12,Security enable on event input x" "0,1" bitfld.long 0x14 11. "SEC11,Security enable on event input x" "0,1" newline bitfld.long 0x14 10. "SEC10,Security enable on event input x" "0,1" bitfld.long 0x14 9. "SEC9,Security enable on event input x" "0,1" newline bitfld.long 0x14 8. "SEC8,Security enable on event input x" "0,1" bitfld.long 0x14 7. "SEC7,Security enable on event input x" "0,1" newline bitfld.long 0x14 6. "SEC6,Security enable on event input x" "0,1" bitfld.long 0x14 5. "SEC5,Security enable on event input x" "0,1" newline bitfld.long 0x14 4. "SEC4,Security enable on event input x" "0,1" bitfld.long 0x14 3. "SEC3,Security enable on event input x" "0,1" newline bitfld.long 0x14 2. "SEC2,Security enable on event input x" "0,1" bitfld.long 0x14 1. "SEC1,Security enable on event input x" "0,1" newline bitfld.long 0x14 0. "SEC0,Security enable on event input x" "0,1" line.long 0x18 "EXTI_PRIVCFGR1,EXTI privilege configuration register" bitfld.long 0x18 31. "PRIV31,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 30. "PRIV30,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 29. "PRIV29,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 28. "PRIV28,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 27. "PRIV27,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 26. "PRIV26,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 25. "PRIV25,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 24. "PRIV24,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 23. "PRIV23,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 22. "PRIV22,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 21. "PRIV21,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 20. "PRIV20,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 19. "PRIV19,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 18. "PRIV18,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 17. "PRIV17,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 15. "PRIV15,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 14. "PRIV14,Privilege enable on event input x" "0,1" bitfld.long 0x18 13. "PRIV13,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 12. "PRIV12,Privilege enable on event input x" "0,1" bitfld.long 0x18 11. "PRIV11,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 10. "PRIV10,Privilege enable on event input x" "0,1" bitfld.long 0x18 9. "PRIV9,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 8. "PRIV8,Privilege enable on event input x" "0,1" bitfld.long 0x18 7. "PRIV7,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 6. "PRIV6,Privilege enable on event input x" "0,1" bitfld.long 0x18 5. "PRIV5,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 4. "PRIV4,Privilege enable on event input x" "0,1" bitfld.long 0x18 3. "PRIV3,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 2. "PRIV2,Privilege enable on event input x" "0,1" bitfld.long 0x18 1. "PRIV1,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 0. "PRIV0,Privilege enable on event input x" "0,1" group.long 0x20++0x1B line.long 0x0 "EXTI_RTSR2,EXTI rising trigger selection register" bitfld.long 0x0 24. "RT56,Rising trigger event configuration bit of configurable event input 56" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and Interrupt).." bitfld.long 0x0 22. "RT54,Rising trigger event configuration bit of configurable event input 54" "0,1" newline bitfld.long 0x0 19. "RT51,Rising trigger event configuration bit of configurable event input 51" "0,1" bitfld.long 0x0 8. "RT40,Rising trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x0 7. "RT39,Rising trigger event configuration bit of configurable event input x" "0,1" line.long 0x4 "EXTI_FTSR2,EXTI falling trigger selection register" bitfld.long 0x4 24. "FT56,Falling trigger event configuration bit of configurable event input 56" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 22. "FT54,Falling trigger event configuration bit of configurable event input 54" "0,1" newline bitfld.long 0x4 19. "FT51,Falling trigger event configuration bit of configurable event input 51" "0,1" bitfld.long 0x4 8. "FT40,Falling trigger event configuration bit of configurable event input x" "0,1" newline bitfld.long 0x4 7. "FT39,Falling trigger event configuration bit of configurable event input x" "0,1" line.long 0x8 "EXTI_SWIER2,EXTI software interrupt event register" bitfld.long 0x8 24. "SWI56,Software interrupt on event 56" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 22. "SWI54,Software interrupt on event 54" "0,1" newline bitfld.long 0x8 19. "SWI51,Software interrupt on event 51" "0,1" bitfld.long 0x8 8. "SWI40,Software interrupt on event x" "0,1" newline bitfld.long 0x8 7. "SWI39,Software interrupt on event x" "0,1" line.long 0xC "EXTI_RPR2,EXTI rising edge pending register" bitfld.long 0xC 24. "RPIF56,Configurable event input 56 rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 22. "RPIF54,Configurable event input 54 rising edge pending bit" "0,1" newline bitfld.long 0xC 19. "RPIF51,Configurable event input 51 rising edge pending bit" "0,1" bitfld.long 0xC 8. "RPIF40,Configurable event input x rising edge pending bit" "0,1" newline bitfld.long 0xC 7. "RPIF39,Configurable event input x rising edge pending bit" "0,1" line.long 0x10 "EXTI_FPR2,EXTI falling edge pending register" bitfld.long 0x10 24. "FPIF56,Configurable event input 56 falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 22. "FPIF54,Configurable event input 54 falling edge pending bit" "0,1" newline bitfld.long 0x10 19. "FPIF51,Configurable event input 51 falling edge pending bit" "0,1" bitfld.long 0x10 8. "FPIF40,Configurable event input x falling edge pending bit" "0,1" newline bitfld.long 0x10 7. "FPIF39,Configurable event input x falling edge pending bit" "0,1" line.long 0x14 "EXTI_SECCFGR2,EXTI security enable register" bitfld.long 0x14 31. "SEC63,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 30. "SEC62,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 29. "SEC61,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 28. "SEC60,Security enable on event input x" "0: Event security disabled (non-secure),1: Event security enabled (secure)" newline bitfld.long 0x14 26. "SEC58,Security enable on event input x" "0,1" bitfld.long 0x14 25. "SEC57,Security enable on event input x" "0,1" newline bitfld.long 0x14 24. "SEC56,Security enable on event input x" "0,1" bitfld.long 0x14 23. "SEC55,Security enable on event input x" "0,1" newline bitfld.long 0x14 22. "SEC54,Security enable on event input x" "0,1" bitfld.long 0x14 21. "SEC53,Security enable on event input x" "0,1" newline bitfld.long 0x14 20. "SEC52,Security enable on event input x" "0,1" bitfld.long 0x14 19. "SEC51,Security enable on event input x" "0,1" newline bitfld.long 0x14 18. "SEC50,Security enable on event input x" "0,1" bitfld.long 0x14 17. "SEC49,Security enable on event input x" "0,1" newline bitfld.long 0x14 16. "SEC48,Security enable on event input x" "0,1" bitfld.long 0x14 15. "SEC47,Security enable on event input x" "0,1" newline bitfld.long 0x14 14. "SEC46,Security enable on event input x" "0,1" bitfld.long 0x14 13. "SEC45,Security enable on event input x" "0,1" newline bitfld.long 0x14 12. "SEC44,Security enable on event input x" "0,1" bitfld.long 0x14 11. "SEC43,Security enable on event input x" "0,1" newline bitfld.long 0x14 10. "SEC42,Security enable on event input x" "0,1" bitfld.long 0x14 9. "SEC41,Security enable on event input x" "0,1" newline bitfld.long 0x14 8. "SEC40,Security enable on event input x" "0,1" bitfld.long 0x14 7. "SEC39,Security enable on event input x" "0,1" newline bitfld.long 0x14 6. "SEC38,Security enable on event input x" "0,1" bitfld.long 0x14 5. "SEC37,Security enable on event input x" "0,1" newline bitfld.long 0x14 4. "SEC36,Security enable on event input x" "0,1" bitfld.long 0x14 3. "SEC35,Security enable on event input x" "0,1" newline bitfld.long 0x14 2. "SEC34,Security enable on event input x" "0,1" bitfld.long 0x14 1. "SEC33,Security enable on event input x" "0,1" newline bitfld.long 0x14 0. "SEC32,Security enable on event input x" "0,1" line.long 0x18 "EXTI_PRIVCFGR2,EXTI privilege enable register" bitfld.long 0x18 31. "PRIV63,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 30. "PRIV62,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 29. "PRIV61,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" bitfld.long 0x18 28. "PRIV60,Privilege enable on event input x" "0: Event privilege disabled (unprivileged),1: Event privilege enabled (privileged)" newline bitfld.long 0x18 26. "PRIV58,Privilege enable on event input x" "0,1" bitfld.long 0x18 25. "PRIV57,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 24. "PRIV56,Privilege enable on event input x" "0,1" bitfld.long 0x18 23. "PRIV55,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 22. "PRIV54,Privilege enable on event input x" "0,1" bitfld.long 0x18 21. "PRIV53,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 20. "PRIV52,Privilege enable on event input x" "0,1" bitfld.long 0x18 19. "PRIV51,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 18. "PRIV50,Privilege enable on event input x" "0,1" bitfld.long 0x18 17. "PRIV49,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 16. "PRIV48,Privilege enable on event input x" "0,1" bitfld.long 0x18 15. "PRIV47,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 14. "PRIV46,Privilege enable on event input x" "0,1" bitfld.long 0x18 13. "PRIV45,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 12. "PRIV44,Privilege enable on event input x" "0,1" bitfld.long 0x18 11. "PRIV43,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 10. "PRIV42,Privilege enable on event input x" "0,1" bitfld.long 0x18 9. "PRIV41,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 8. "PRIV40,Privilege enable on event input x" "0,1" bitfld.long 0x18 7. "PRIV39,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 6. "PRIV38,Privilege enable on event input x" "0,1" bitfld.long 0x18 5. "PRIV37,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 4. "PRIV36,Privilege enable on event input x" "0,1" bitfld.long 0x18 3. "PRIV35,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 2. "PRIV34,Privilege enable on event input x" "0,1" bitfld.long 0x18 1. "PRIV33,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 0. "PRIV32,Privilege enable on event input x" "0,1" group.long 0x40++0x1B line.long 0x0 "EXTI_RTSR3,EXTI rising trigger selection register" bitfld.long 0x0 10. "RT74,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 9. "RT73,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 8. "RT72,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 7. "RT71,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 6. "RT70,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 5. "RT69,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." newline bitfld.long 0x0 4. "RT68,Rising trigger event configuration bit of configurable event input x" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).." bitfld.long 0x0 2. "RT66,Rising trigger event configuration bit of configurable event input 66" "0,1" line.long 0x4 "EXTI_FTSR3,EXTI falling trigger selection register" bitfld.long 0x4 10. "FT74,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 9. "FT73,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 8. "FT72,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 7. "FT71,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 6. "FT70,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 5. "FT69,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." newline bitfld.long 0x4 4. "FT68,Falling trigger event configuration bit of configurable event input x" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.." bitfld.long 0x4 2. "FT66,Falling trigger event configuration bit of configurable event input 66" "0,1" line.long 0x8 "EXTI_SWIER3,EXTI software interrupt event register" bitfld.long 0x8 10. "SWI74,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 9. "SWI73,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." newline bitfld.long 0x8 8. "SWI72,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 7. "SWI71,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." newline bitfld.long 0x8 6. "SWI70,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 5. "SWI69,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." newline bitfld.long 0x8 4. "SWI68,Software interrupt on event x" "0: Writing 0 has no effect.,1: Writing 1 to this bit triggers a rising edge.." bitfld.long 0x8 2. "SWI66,Software interrupt on event 66" "0,1" line.long 0xC "EXTI_RPR3,EXTI rising edge pending register" bitfld.long 0xC 10. "RPIF74,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 9. "RPIF73,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 8. "RPIF72,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 7. "RPIF71,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 6. "RPIF70,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 5. "RPIF69,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" newline bitfld.long 0xC 4. "RPIF68,configurable event input x rising edge pending bit" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred" bitfld.long 0xC 2. "RPIF66,configurable event input 66rising edge pending bit" "0,1" line.long 0x10 "EXTI_FPR3,EXTI falling edge pending register" bitfld.long 0x10 10. "FPIF74,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 9. "FPIF73,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 8. "FPIF72,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 7. "FPIF71,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 6. "FPIF70,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 5. "FPIF69,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" newline bitfld.long 0x10 4. "FPIF68,configurable event input x falling edge pending bit" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred" bitfld.long 0x10 2. "FPIF66,configurable event input 66 falling edge pending bit" "0,1" line.long 0x14 "EXTI_SECCFGR3,EXTI security enable register" bitfld.long 0x14 13. "SEC77,Security enable on event input 77" "0: Event security disabled (non-secure),1: Event security enabled (secure)" bitfld.long 0x14 10. "SEC74,Security enable on event input x" "0,1" newline bitfld.long 0x14 9. "SEC73,Security enable on event input x" "0,1" bitfld.long 0x14 8. "SEC72,Security enable on event input x" "0,1" newline bitfld.long 0x14 7. "SEC71,Security enable on event input x" "0,1" bitfld.long 0x14 6. "SEC70,Security enable on event input x" "0,1" newline bitfld.long 0x14 5. "SEC69,Security enable on event input x" "0,1" bitfld.long 0x14 4. "SEC68,Security enable on event input x" "0,1" newline bitfld.long 0x14 2. "SEC66,Security enable on event input x" "0,1" bitfld.long 0x14 1. "SEC65,Security enable on event input x" "0,1" newline bitfld.long 0x14 0. "SEC64,Security enable on event input x" "0,1" line.long 0x18 "EXTI_PRIVCFGR3,EXTI privilege enable register" bitfld.long 0x18 13. "PRIV77,Privilege enable on event input 77" "0: Event privilege disabled (unprivileged,1: Event privilege enabled (privileged)" bitfld.long 0x18 10. "PRIV74,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 9. "PRIV73,Privilege enable on event input x" "0,1" bitfld.long 0x18 8. "PRIV72,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 7. "PRIV71,Privilege enable on event input x" "0,1" bitfld.long 0x18 6. "PRIV70,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 5. "PRIV69,Privilege enable on event input x" "0,1" bitfld.long 0x18 4. "PRIV68,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 2. "PRIV66,Privilege enable on event input x" "0,1" bitfld.long 0x18 1. "PRIV65,Privilege enable on event input x" "0,1" newline bitfld.long 0x18 0. "PRIV64,Privilege enable on event input x" "0,1" group.long 0x60++0x13 line.long 0x0 "EXTI_EXTICR1,EXTI external interrupt selection register 1" hexmask.long.byte 0x0 24.--31. 1. "EXTI3,EXTI3 GPIO port selection" hexmask.long.byte 0x0 16.--23. 1. "EXTI2,EXTI2 GPIO port selection" newline hexmask.long.byte 0x0 8.--15. 1. "EXTI1,EXTI1 GPIO port selection" hexmask.long.byte 0x0 0.--7. 1. "EXTI0,EXTI0 GPIO port selection." line.long 0x4 "EXTI_EXTICR2,EXTI external interrupt selection register 2" hexmask.long.byte 0x4 24.--31. 1. "EXTI7,EXTI7 GPIO port selection." hexmask.long.byte 0x4 16.--23. 1. "EXTI6,EXTI6 GPIO port selection." newline hexmask.long.byte 0x4 8.--15. 1. "EXTI5,EXTI5 GPIO port selection." hexmask.long.byte 0x4 0.--7. 1. "EXTI4,EXTI4 GPIO port selection." line.long 0x8 "EXTI_EXTICR3,EXTI external interrupt selection register 3" hexmask.long.byte 0x8 24.--31. 1. "EXTI11,EXTI11 GPIO port selection." hexmask.long.byte 0x8 16.--23. 1. "EXTI10,EXTI10 GPIO port selection." newline hexmask.long.byte 0x8 8.--15. 1. "EXTI9,EXTI9 GPIO port selection." hexmask.long.byte 0x8 0.--7. 1. "EXTI8,EXTI8 GPIO port selection." line.long 0xC "EXTI_EXTICR4,EXTI external interrupt selection register 4" hexmask.long.byte 0xC 24.--31. 1. "EXTI15,EXTI15 GPIO port selection." hexmask.long.byte 0xC 16.--23. 1. "EXTI14,EXTI14 GPIO port selection." newline hexmask.long.byte 0xC 8.--15. 1. "EXTI13,EXTI13 GPIO port selection." hexmask.long.byte 0xC 0.--7. 1. "EXTI12,EXTI12 GPIO port selection." line.long 0x10 "EXTI_LOCKR,EXTI lock register" bitfld.long 0x10 0. "GLOCK,Global security privilege EXTI_SECCFGRx/PRIVCFGRx" "0: Security privilege open can be modified.,1: Security privilege locked can no longer be.." group.long 0x80++0x7 line.long 0x0 "EXTI_IMR1,EXTI CPU wake-up with interrupt mask register 1" bitfld.long 0x0 31. "IM31,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 30. "IM30,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 29. "IM29,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 28. "IM28,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 27. "IM27,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 26. "IM26,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 25. "IM25,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 24. "IM24,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 23. "IM23,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 22. "IM22,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 21. "IM21,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 20. "IM20,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 19. "IM19,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 18. "IM18,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 17. "IM17,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 15. "IM15,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 14. "IM14,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 13. "IM13,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 12. "IM12,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 11. "IM11,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 10. "IM10,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 9. "IM9,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 8. "IM8,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 7. "IM7,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 6. "IM6,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 5. "IM5,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 4. "IM4,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 3. "IM3,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 2. "IM2,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 1. "IM1,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 0. "IM0,CPU wake-up with interrupt mask on event input x" "0,1" line.long 0x4 "EXTI_EMR1,EXTI CPU wake-up with event mask register 1" bitfld.long 0x4 31. "EM31,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 30. "EM30,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 29. "EM29,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 28. "EM28,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 27. "EM27,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 26. "EM26,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 25. "EM25,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 24. "EM24,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 23. "EM23,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 22. "EM22,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 21. "EM21,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 20. "EM20,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 19. "EM19,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 18. "EM18,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 17. "EM17,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 15. "EM15,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 14. "EM14,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 13. "EM13,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 12. "EM12,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 11. "EM11,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 10. "EM10,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 9. "EM9,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 8. "EM8,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 7. "EM7,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 6. "EM6,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 5. "EM5,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 4. "EM4,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 3. "EM3,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 2. "EM2,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 1. "EM1,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 0. "EM0,CPU wake-up with interrupt mask on event input x" "0,1" group.long 0x90++0x7 line.long 0x0 "EXTI_IMR2,EXTI CPU wake-up with interrupt mask register 2" bitfld.long 0x0 31. "IM63,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 30. "IM62,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 29. "IM61,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 28. "IM60,CPU wake-up with interrupt mask on event input x" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." newline bitfld.long 0x0 26. "IM58,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 25. "IM57,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 24. "IM56,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 23. "IM55,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 22. "IM54,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 21. "IM53,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 20. "IM52,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 19. "IM51,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 18. "IM50,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 17. "IM49,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 16. "IM48,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 15. "IM47,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 14. "IM46,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 13. "IM45,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 12. "IM44,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 11. "IM43,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 10. "IM42,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 9. "IM41,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 8. "IM40,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 7. "IM39,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 6. "IM38,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 5. "IM37,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 4. "IM36,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 3. "IM35,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 2. "IM34,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 1. "IM33,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 0. "IM32,CPU wake-up with interrupt mask on event input x" "0,1" line.long 0x4 "EXTI_EMR2,EXTI CPU wake-up with event mask register 2" bitfld.long 0x4 31. "EM63,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 30. "EM62,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 29. "EM61,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 28. "EM60,CPU wake-up with event on event input x" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." newline bitfld.long 0x4 26. "EM58,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 25. "EM57,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 24. "EM56,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 23. "EM55,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 22. "EM54,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 21. "EM53,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 20. "EM52,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 19. "EM51,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 18. "EM50,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 17. "EM49,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 16. "EM48,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 15. "EM47,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 14. "EM46,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 13. "EM45,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 12. "EM44,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 11. "EM43,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 10. "EM42,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 9. "EM41,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 8. "EM40,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 7. "EM39,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 6. "EM38,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 5. "EM37,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 4. "EM36,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 3. "EM35,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 2. "EM34,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 1. "EM33,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 0. "EM32,CPU wake-up with interrupt mask on event input x" "0,1" group.long 0xA0++0x7 line.long 0x0 "EXTI_IMR3,EXTI CPU wake-up with interrupt mask register 3" bitfld.long 0x0 13. "IM77,CPU wake-up with interrupt mask on event input 77" "0: Wake-up and interrupt from input event x is..,1: Wake-up and interrupt from input event x is.." bitfld.long 0x0 10. "IM74,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 9. "IM73,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 8. "IM72,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 7. "IM71,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 6. "IM70,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 5. "IM69,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 4. "IM68,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 2. "IM66,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x0 1. "IM65,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x0 0. "IM64,CPU wake-up with interrupt mask on event input x" "0,1" line.long 0x4 "EXTI_EMR3,EXTI CPU wake-up with event mask register 3" bitfld.long 0x4 13. "EM77,CPU wake-up with event on event input 77" "0: Wake-up with event request from line x is masked.,1: Wake-up with event request from line x is.." bitfld.long 0x4 10. "EM74,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 9. "EM73,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 8. "EM72,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 7. "EM71,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 6. "EM70,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 5. "EM69,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 4. "EM68,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 2. "EM66,CPU wake-up with interrupt mask on event input x" "0,1" bitfld.long 0x4 1. "EM65,CPU wake-up with interrupt mask on event input x" "0,1" newline bitfld.long 0x4 0. "EM64,CPU wake-up with interrupt mask on event input x" "0,1" tree.end tree.end tree "FDCAN (Controller Area Network with Flexible Data Rate)" base ad:0x0 tree "FDCAN1" base ad:0x4000A000 rgroup.long 0x0++0x3 line.long 0x0 "FDCAN_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 3" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 2" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year = 4" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day =18" rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CCU_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 1" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 1" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year =" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day = 18" line.long 0x4 "FDCAN_ENDN,FDCAN Endian register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test value" group.long 0x4++0x3 line.long 0x0 "FDCAN_CCU_CCFG,FDCAN Endian register" bitfld.long 0x0 31. "SWR,Software reset" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CDIV,Clock divider" newline hexmask.long.byte 0x0 8.--15. 1. "OCPM,Oscillator clock periods minimum" bitfld.long 0x0 7. "CFL,Calibration field length" "0: Calibration field length is 32 bits,1: Calibration field length is 64 bits" newline bitfld.long 0x0 6. "BCC,Bypass clock calibration" "0: Clock calibration unit generates time quanta clock,1: Clock calibration unit bypassed (default.." hexmask.long.byte 0x0 0.--4. 1. "TQBT,Time quanta per bit time" rgroup.long 0x8++0x3 line.long 0x0 "FDCAN_CCU_CSTAT,Calibration status register" bitfld.long 0x0 30.--31. "CALS,Calibration state" "0: Not_Calibrated,1: Basic_Calibrated,2: Precision_Calibrated,?" hexmask.long.word 0x0 18.--28. 1. "TQC,Time quanta counter" newline hexmask.long.tbyte 0x0 0.--17. 1. "OCPC,Oscillator clock period counter" group.long 0xC++0x3 line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register" bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bitrate prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width" group.long 0xC++0x7 line.long 0x0 "FDCAN_CCU_CWD,FDCAN data bit timing and prescaler register" hexmask.long.word 0x0 16.--31. 1. "WDV,Watchdog value" hexmask.long.word 0x0 0.--15. 1. "WDC,WDC" line.long 0x4 "FDCAN_TEST,FDCAN test register" rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)" bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX" newline bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value loop back mode is disabled,1: Loop back mode is enabled (see Test modes)" group.long 0x10++0x7 line.long 0x0 "FDCAN_CCU_IR,FDCAN test register" bitfld.long 0x0 1. "CSC,Calibration state changed" "0: Calibration state unchanged,1: Calibration state has changed" bitfld.long 0x0 0. "CWE,Calibration watchdog event" "0: No calibration watchdog event,1: Calibration watchdog event occurred" line.long 0x4 "FDCAN_RWD,FDCAN RAM watchdog register" hexmask.long.byte 0x4 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x4 0.--7. 1. "WDC,Watchdog configuration" group.long 0x14++0x1B line.long 0x0 "FDCAN_CCU_IE,FDCAN RAM watchdog register" bitfld.long 0x0 1. "CSCE,Calibration state changed enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 0. "CWEE,Calibration watchdog event enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x4 "FDCAN_CCCR,FDCAN CC control register" bitfld.long 0x4 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x4 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: Disabled,1: Enabled" newline bitfld.long 0x4 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0x4 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0x4 9. "BRSE,FDCAN bitrate switching" "0: Bitrate switching for transmissions disabled,1: Bitrate switching for transmissions enabled" bitfld.long 0x4 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0x4 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test mode write access to register TEST enabled" bitfld.long 0x4 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0x4 5. "MON,Bus monitoring mode" "0: Bus monitoring mode is disabled,1: Bus monitoring mode is enabled" bitfld.long 0x4 4. "CSR,Clock stop request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline rbitfld.long 0x4 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.." bitfld.long 0x4 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation mode active" newline bitfld.long 0x4 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0x4 0. "INIT,Initialization" "0: Normal operation,1: Initialization is started (while FDCAN_CCCR.INIT.." line.long 0x8 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register" hexmask.long.byte 0x8 25.--31. 1. "NSJW,Nominal (re)synchronization jump width" hexmask.long.word 0x8 16.--24. 1. "NBRP,Bitrate prescaler" newline hexmask.long.byte 0x8 8.--15. 1. "NTSEG1,Nominal time segment before sample point" hexmask.long.byte 0x8 0.--6. 1. "NTSEG2,Nominal time segment after sample point" line.long 0xC "FDCAN_TSCC,FDCAN timestamp counter configuration register" hexmask.long.byte 0xC 16.--19. 1. "TCP,Timestamp counter prescaler" bitfld.long 0xC 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value used..,3: Same as 00." line.long 0x10 "FDCAN_TSCV,FDCAN timestamp counter value register" hexmask.long.word 0x10 0.--15. 1. "TSC,Timestamp counter" line.long 0x14 "FDCAN_TOCC,FDCAN timeout counter configuration register" hexmask.long.word 0x14 16.--31. 1. "TOP,Timeout period" bitfld.long 0x14 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x14 0. "ETOC,Enable timeout counter" "0: Timeout counter disabled,1: Timeout counter enabled" line.long 0x18 "FDCAN_TOCV,FDCAN timeout counter value register" hexmask.long.word 0x18 0.--15. 1. "TOC,Timeout counter" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN error counter register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging" rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter" line.long 0x4 "FDCAN_PSR,FDCAN protocol status register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value" bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not ha ve its..,1: Last received FDCAN message had its ESI flag set" rbitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off,1: The FDCAN is in Bus_Off state" rbitfld.long 0x4 6. "EW,Warning status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state" rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter,2: Receiver: node is operating as receiver,3: Transmitter: node is operating as transmitter" newline rbitfld.long 0x4 0.--2. "LEC,Last error code" "0: No error: No error occurred since LEC has been..,1: Stuff error: More than 5 equal bits in a..,2: Form error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the protocol status.." line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register" hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset" hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,FDCAN interrupt register" bitfld.long 0x0 29. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.." bitfld.long 0x0 26. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow,1: Overflow of CAN error logging counter occurred" newline bitfld.long 0x0 19. "DRX,Message stored to dedicated Rx buffer" "0: No Rx buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM access failure" "0: No message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp wraparound" "0: No timestamp counter wraparound,1: Timestamp counter wraparound" newline bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached" "0: Tx event FIFO fill level below watermark,1: Tx event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High priority message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register" bitfld.long 0x4 29. "ARAE,Access to Reserved address enable" "0,1" bitfld.long 0x4 28. "PEDE,Protocol error in data phase enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol error in Arbitration phase enable" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to dedicated Rx buffer interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register" bitfld.long 0x8 29. "ARAL,Access to reserved address line" "0,1" bitfld.long 0x8 28. "PEDL,Protocol error in data phase line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase line" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog interrupt line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off status" "0,1" bitfld.long 0x8 24. "EWL,Warning status interrupt line" "0,1" newline bitfld.long 0x8 23. "EPL,Error passive interrupt line" "0,1" bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to dedicated Rx buffer interrupt line" "0,1" bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx event FIFO element Lost interrupt line" "0,1" bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line" "0,1" bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line" "0,1" bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission completed interrupt line" "0,1" bitfld.long 0x8 8. "HPML,High priority message interrupt line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line" "0,1" line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register" bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled" bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN global filter configuration register" bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard ID,1: Reject all remote frames with 11-bit standard ID" bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard ID,1: Reject all remote frames with 29-bit standard ID" line.long 0x4 "FDCAN_SIDFC,FDCAN standard ID filter configuration register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address" line.long 0x8 "FDCAN_XIDFC,FDCAN extended ID filter configuration register" hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN extended ID and mask register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "FDCAN_HPMS,FDCAN high priority message status register" bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index" newline bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index" group.long 0x98++0x1B line.long 0x0 "FDCAN_NDAT1,FDCAN new data 1 register" bitfld.long 0x0 31. "ND31,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 30. "ND30,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 28. "ND28,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 26. "ND26,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 24. "ND24,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 22. "ND22,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 20. "ND20,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 18. "ND18,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 16. "ND16,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 14. "ND14,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 12. "ND12,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 10. "ND10,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 8. "ND8,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 6. "ND6,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 4. "ND4,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 2. "ND2,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 0. "ND0,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x4 "FDCAN_NDAT2,FDCAN new data 2 register" bitfld.long 0x4 31. "ND63,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 30. "ND62,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 28. "ND60,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 26. "ND58,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 24. "ND56,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 22. "ND54,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 20. "ND52,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 18. "ND50,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 16. "ND48,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 14. "ND46,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 12. "ND44,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 10. "ND42,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 8. "ND40,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 6. "ND38,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 4. "ND36,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 2. "ND34,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 0. "ND32,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x8 "FDCAN_RXF0C,FDCAN Rx FIFO 0 configuration register" bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,FIFO 0 watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address" line.long 0xC "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register" bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0xC 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index" hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index" newline hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level" line.long 0x10 "FDCAN_RXF0A,FDCAN Rx FIFO 0 acknowledge register" hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index" line.long 0x14 "FDCAN_RXBC,FDCAN Rx buffer configuration register" hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address" line.long 0x18 "FDCAN_RXF1C,FDCAN Rx FIFO 1 configuration register" bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark" newline hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size" hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address" rgroup.long 0xB4++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register" bitfld.long 0x0 30.--31. "DMS,Debug message status" "0: Idle state wait for reception of debug messages,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level" group.long 0xB8++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index" rgroup.long 0xBC++0x3 line.long 0x0 "FDCAN_RXESC,FDCAN Rx buffer element size configuration register" bitfld.long 0x0 8.--10. "RBDS,Rx buffer data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 0 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" newline bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 1 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 30. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation." hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/queue size" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of dedicated transmit buffers" hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx buffers start address" rgroup.long 0xC4++0xB line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register" bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/queue put index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO get index." hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO free level" line.long 0x4 "FDCAN_TXESC,FDCAN Tx buffer element size configuration register" bitfld.long 0x4 0.--2. "TBDS,Tx buffer data Field size:" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" line.long 0x8 "FDCAN_TXBRP,FDCAN Tx buffer request pending register" hexmask.long 0x8 0.--31. 1. "TRP,Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register" hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register" hexmask.long 0x4 0.--31. 1. "CR,Cancellation request" rgroup.long 0xD8++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register" hexmask.long 0x0 0.--31. 1. "TO,Transmission occurred" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register" hexmask.long 0x4 0.--31. 1. "CF,Cancellation finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register" hexmask.long 0x0 0.--31. 1. "TIE,Transmission interrupt enable" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register" hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation finished interrupt enable" group.long 0xF0++0x3 line.long 0x0 "FDCAN_TXEFC,FDCAN Tx event FIFO configuration register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address" rgroup.long 0xF4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register" bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO put index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level" group.long 0xF8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT trigger memory configuration register" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger memory elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger memory start address." line.long 0x4 "FDCAN_TTRMC,FDCAN TT reference message configuration register" bitfld.long 0x4 31. "RMPS,Reference message payload select" "0: Reference message has no additional payload,1: The following elements are taken from Tx buffer 0:" bitfld.long 0x4 30. "XTD,Extended identifier" "0: 11-bit standard identifier,1: 29-bit extended identifier" newline hexmask.long 0x4 0.--28. 1. "RID,Reference identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT operation configuration register" bitfld.long 0x8 26. "EVTP,Event trigger polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x8 25. "ECC,Enable clock calibration." "0: Automatic clock calibration in FDCAN level 0 2..,1: Automatic clock calibration in FDCAN level 0 2.." newline bitfld.long 0x8 24. "EGTF,Enable global time filtering." "0: Global time filtering in FDCAN level 0 2 is..,1: Global time filtering in FDCAN level 0 2 is.." hexmask.long.byte 0x8 16.--23. 1. "AWL,Application watchdog limit." newline bitfld.long 0x8 15. "EECS,Enable external clock synchronization" "0: External clock synchronization in FDCAN level 0..,1: External clock synchronization in FDCAN level 0.." hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial reference trigger offset." newline bitfld.long 0x8 5.--7. "LDSDL,LD of synchronization deviation limit." "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time master." "0: Time master function disabled,1: Potential time master" newline bitfld.long 0x8 3. "GEN,Gap enable." "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.." bitfld.long 0x8 0.--1. "OM,Operation mode." "0: Event-driven CAN communication default,1: TTCAN level 1,2: TTCAN level 2,3: TTCAN level 0" line.long 0xC "FDCAN_TTMLM,FDCAN TT matrix limits register" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected number of Tx triggers" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx enable window" newline bitfld.long 0xC 6.--7. "CSS,Cycle start synchronization" "0: No sync pulse,1: Sync pulse at start of basic cycle,2: Sync pulse at start of matrix cycle,?" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR configuration register" bitfld.long 0x10 31. "ELT,Enable local time." "0: Local time is stopped default,1: Local time is enabled" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator configuration." newline hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator configuration low." line.long 0x14 "FDCAN_TTOCN,FDCAN TT operation control register" rbitfld.long 0x14 15. "LCKC,TT operation control register locked." "0: Write access to FDCAN_TTOCN enabled,1: Write access to FDCAN_TTOCN locked" bitfld.long 0x14 13. "ESCN,External synchronization control" "0: External synchronization disabled,1: External synchronization enabled" newline bitfld.long 0x14 12. "NIG,Next is gap." "0: No action reset by reception of any reference..,1: Transmit next reference message with Next_is_Gap.." bitfld.long 0x14 11. "TMG,Time mark gap." "0: Reset by each reference message,1: Next reference message started when register.." newline bitfld.long 0x14 10. "FGP,Finish gap." "0: No reference message requested,1: Application requested start of reference message" bitfld.long 0x14 9. "GCS,Gap control select" "0: Gap control independent from event trigger,1: Gap control by input event trigger pin" newline bitfld.long 0x14 8. "TTIE,Trigger time mark interrupt pulse enable" "0: Trigger time mark interrupt output fdcan1_tmp..,1: Trigger time mark interrupt output fdcan1_tmp.." bitfld.long 0x14 6.--7. "TMC,Register time mark compare." "0: No Register time mark interrupt generated,1: Register time mark interrupt if time mark =..,2: Register time mark interrupt if time mark =..,3: Register time mark interrupt if time mark =.." newline bitfld.long 0x14 5. "RTIE,Register time mark interrupt pulse enable." "0: Register time mark interrupt output disabled,1: Register time mark interrupt output enabled" bitfld.long 0x14 3.--4. "SWS,Stop watch source." "0: Stop watch disabled,1: Actual value of cycle time is copied to..,2: Actual value of local time is copied to..,3: Actual value of global time is copied to.." newline bitfld.long 0x14 2. "SWP,Stop watch polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x14 1. "ECS,External clock synchronization." "0,1" newline bitfld.long 0x14 0. "SGT,Set global time." "0,1" line.long 0x18 "FDCAN_TTGTP,FDCAN TT global time preset register" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle time target phase" hexmask.long.word 0x18 0.--15. 1. "TP,Time preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT time mark register" rbitfld.long 0x1C 31. "LCKM,TT time mark register locked" "0: Write access to FDCAN_TTTMK enabled,1: Write access to FDCAN_TTTMK locked" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time mark cycle code" newline hexmask.long.word 0x1C 0.--15. 1. "TM,Time mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT interrupt register" bitfld.long 0x20 18. "CER,Configuration error" "0: No error found in trigger list,1: Error found in trigger list" bitfld.long 0x20 17. "AW,Application watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time" newline bitfld.long 0x20 16. "WT,Watch trigger" "0: No missing reference message,1: Missing reference message (level 0: cycle time.." bitfld.long 0x20 15. "IWTG,Initialization watch trigger" "0,1" newline bitfld.long 0x20 14. "ELC,Error level changed" "0: No change in error level,1: Error level changed" bitfld.long 0x20 13. "SE2,Scheduling error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred" newline bitfld.long 0x20 12. "SE1,Scheduling error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred" bitfld.long 0x20 11. "TXO,Tx count overflow" "0: Number of Tx trigger as expected,1: More Tx trigger than expected in one cycle" newline bitfld.long 0x20 10. "TXU,Tx count underflow" "0: Number of Tx trigger as expected,1: Less Tx trigger than expected in one cycle" bitfld.long 0x20 9. "GTE,Global time error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit" newline bitfld.long 0x20 8. "GTD,Global time discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time" bitfld.long 0x20 7. "GTW,Global time wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred" newline bitfld.long 0x20 6. "SWE,Stop watch event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.." bitfld.long 0x20 5. "TTMI,Trigger time mark event internal" "0: Time mark not reached,1: Time mark reached (level 0: cycle time.." newline bitfld.long 0x20 4. "RTMI,Register time mark interrupt" "0: Time mark not reached,1: Time mark reached" bitfld.long 0x20 3. "SOG,Start of gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of synchronization mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.." bitfld.long 0x20 1. "SMC,Start of matrix cycle" "0: No matrix cycle started since bit has been reset,1: Matrix cycle started" newline bitfld.long 0x20 0. "SBC,Start of basic cycle" "0: No basic cycle started since bit has been reset,1: Basic cycle started" line.long 0x24 "FDCAN_TTIE,FDCAN TT interrupt enable register" bitfld.long 0x24 18. "CERE,Configuration error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 17. "AWE,Application watchdog interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 16. "WTE,Watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 15. "IWTE,Initialization watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 14. "ELCE,Change error level interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 13. "SE2E,Scheduling error 2 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 12. "SE1E,Scheduling error 1 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 11. "TXOE,Tx count overflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 10. "TXUE,Tx count underflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 9. "GTEE,Global time error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 8. "GTDE,Global time discontinuity interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 7. "GTWE,Global time wrap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 6. "SWEE,Stop watch event interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 5. "TTMIE,Trigger time mark event internal interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 4. "RTMIE,Register time mark interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 3. "SOGE,Start of gap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 2. "CSME,Change of synchronization mode interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 1. "SMCE,Start of matrix cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 0. "SBCE,Start of basic cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" line.long 0x28 "FDCAN_TTILS,FDCAN TT interrupt line select register" bitfld.long 0x28 18. "CERL,Configuration error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 17. "AWL,Application watchdog interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 16. "WTL,Watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 15. "IWTL,Initialization watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 14. "ELCL,Change error level interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 13. "SE2L,Scheduling error 2 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 12. "SE1L,Scheduling error 1 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 11. "TXOL,Tx count overflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 10. "TXUL,Tx count underflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 9. "GTEL,Global time error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 8. "GTDL,Global time discontinuity interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 7. "GTWL,Global time wrap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 6. "SWEL,Stop watch event interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 5. "TTMIL,Trigger time mark event internal interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 4. "RTMIL,Register time mark interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 3. "SOGL,Start of gap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 2. "CSML,Change of synchronization mode interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 1. "SMCL,Start of matrix cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 0. "SBCL,Start of basic cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT operation status register" bitfld.long 0x0 31. "SPL,Schedule phase lock" "0: Phase outside range,1: Phase inside range" bitfld.long 0x0 30. "WECS,Wait for external clock synchronization." "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.." newline bitfld.long 0x0 29. "AWE,Application watchdog event" "0: Application watchdog served in time,1: Failed to serve application watchdog in time" bitfld.long 0x0 28. "WFE,Wait for event" "0: No gap announced reset by a reference message..,1: Reference message with Next_is_Gap = 1 received" newline bitfld.long 0x0 27. "GSI,Gap started indicator" "0: No gap in schedule reset by each reference..,1: Gap time after basic cycle has started" bitfld.long 0x0 24.--26. "TMP,Time master priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GFI,Gap finished indicator" "0: Reset at the end of each reference message,1: Gap finished by FDCAN" bitfld.long 0x0 22. "WGTD,Wait for global time discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.." newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference trigger offset" bitfld.long 0x0 7. "QCS,Quality of clock speed" "0: Local clock speed not synchronized to time..,1: Synchronization deviation less than or equal SDL" newline bitfld.long 0x0 6. "QGTP,Quality of global time phase" "0: Global time not valid,1: Global time in phase with time master" bitfld.long 0x0 4.--5. "SYS,Synchronization state" "0: Out of Synchronization,1: Synchronizing to FDCAN communication,2: Schedule suspended by gap (In_Gap),3: Synchronized to schedule (In_Schedule)" newline bitfld.long 0x0 2.--3. "MS,Master state" "0: Master_Off no master properties relevant,1: Operating as time Slave,2: Operating as backup time master,3: Operating as current time master" bitfld.long 0x0 0.--1. "EL,Error level" "0: Severity 0 - No error,1: Severity 1 - Warning,2: Severity 2 - error,3: Severity 3 - Severe error" line.long 0x4 "FDCAN_TURNA,FDCAN TUR numerator actual register" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator actual value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT local and global time register" hexmask.long.word 0x8 16.--31. 1. "GT,Global time" hexmask.long.word 0x8 0.--15. 1. "LT,Local time" line.long 0xC "FDCAN_TTCTC,FDCAN TT cycle time and count register" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT capture time register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop watch value" hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle count value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT cycle sync mark register" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle sync mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT trigger select register" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input selection" "0: fdcan1_evt0,1: fdcan1_evt1,2: fdcan1_evt2,3: fdcan1_evt3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input selection" "0: fdcan1_swt0,1: fdcan1_swt1,2: fdcan1_swt2,3: fdcan1_swt3" tree.end tree "FDCAN1_S" base ad:0x5000A000 rgroup.long 0x0++0x3 line.long 0x0 "FDCAN_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 3" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 2" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year = 4" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day =18" rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CCU_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 1" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 1" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year =" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day = 18" line.long 0x4 "FDCAN_ENDN,FDCAN Endian register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test value" group.long 0x4++0x3 line.long 0x0 "FDCAN_CCU_CCFG,FDCAN Endian register" bitfld.long 0x0 31. "SWR,Software reset" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CDIV,Clock divider" newline hexmask.long.byte 0x0 8.--15. 1. "OCPM,Oscillator clock periods minimum" bitfld.long 0x0 7. "CFL,Calibration field length" "0: Calibration field length is 32 bits,1: Calibration field length is 64 bits" newline bitfld.long 0x0 6. "BCC,Bypass clock calibration" "0: Clock calibration unit generates time quanta clock,1: Clock calibration unit bypassed (default.." hexmask.long.byte 0x0 0.--4. 1. "TQBT,Time quanta per bit time" rgroup.long 0x8++0x3 line.long 0x0 "FDCAN_CCU_CSTAT,Calibration status register" bitfld.long 0x0 30.--31. "CALS,Calibration state" "0: Not_Calibrated,1: Basic_Calibrated,2: Precision_Calibrated,?" hexmask.long.word 0x0 18.--28. 1. "TQC,Time quanta counter" newline hexmask.long.tbyte 0x0 0.--17. 1. "OCPC,Oscillator clock period counter" group.long 0xC++0x3 line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register" bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bitrate prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width" group.long 0xC++0x7 line.long 0x0 "FDCAN_CCU_CWD,FDCAN data bit timing and prescaler register" hexmask.long.word 0x0 16.--31. 1. "WDV,Watchdog value" hexmask.long.word 0x0 0.--15. 1. "WDC,WDC" line.long 0x4 "FDCAN_TEST,FDCAN test register" rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)" bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX" newline bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value loop back mode is disabled,1: Loop back mode is enabled (see Test modes)" group.long 0x10++0x7 line.long 0x0 "FDCAN_CCU_IR,FDCAN test register" bitfld.long 0x0 1. "CSC,Calibration state changed" "0: Calibration state unchanged,1: Calibration state has changed" bitfld.long 0x0 0. "CWE,Calibration watchdog event" "0: No calibration watchdog event,1: Calibration watchdog event occurred" line.long 0x4 "FDCAN_RWD,FDCAN RAM watchdog register" hexmask.long.byte 0x4 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x4 0.--7. 1. "WDC,Watchdog configuration" group.long 0x14++0x1B line.long 0x0 "FDCAN_CCU_IE,FDCAN RAM watchdog register" bitfld.long 0x0 1. "CSCE,Calibration state changed enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 0. "CWEE,Calibration watchdog event enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x4 "FDCAN_CCCR,FDCAN CC control register" bitfld.long 0x4 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x4 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: Disabled,1: Enabled" newline bitfld.long 0x4 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0x4 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0x4 9. "BRSE,FDCAN bitrate switching" "0: Bitrate switching for transmissions disabled,1: Bitrate switching for transmissions enabled" bitfld.long 0x4 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0x4 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test mode write access to register TEST enabled" bitfld.long 0x4 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0x4 5. "MON,Bus monitoring mode" "0: Bus monitoring mode is disabled,1: Bus monitoring mode is enabled" bitfld.long 0x4 4. "CSR,Clock stop request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline rbitfld.long 0x4 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.." bitfld.long 0x4 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation mode active" newline bitfld.long 0x4 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0x4 0. "INIT,Initialization" "0: Normal operation,1: Initialization is started (while FDCAN_CCCR.INIT.." line.long 0x8 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register" hexmask.long.byte 0x8 25.--31. 1. "NSJW,Nominal (re)synchronization jump width" hexmask.long.word 0x8 16.--24. 1. "NBRP,Bitrate prescaler" newline hexmask.long.byte 0x8 8.--15. 1. "NTSEG1,Nominal time segment before sample point" hexmask.long.byte 0x8 0.--6. 1. "NTSEG2,Nominal time segment after sample point" line.long 0xC "FDCAN_TSCC,FDCAN timestamp counter configuration register" hexmask.long.byte 0xC 16.--19. 1. "TCP,Timestamp counter prescaler" bitfld.long 0xC 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value used..,3: Same as 00." line.long 0x10 "FDCAN_TSCV,FDCAN timestamp counter value register" hexmask.long.word 0x10 0.--15. 1. "TSC,Timestamp counter" line.long 0x14 "FDCAN_TOCC,FDCAN timeout counter configuration register" hexmask.long.word 0x14 16.--31. 1. "TOP,Timeout period" bitfld.long 0x14 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x14 0. "ETOC,Enable timeout counter" "0: Timeout counter disabled,1: Timeout counter enabled" line.long 0x18 "FDCAN_TOCV,FDCAN timeout counter value register" hexmask.long.word 0x18 0.--15. 1. "TOC,Timeout counter" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN error counter register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging" rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter" line.long 0x4 "FDCAN_PSR,FDCAN protocol status register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value" bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not ha ve its..,1: Last received FDCAN message had its ESI flag set" rbitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off,1: The FDCAN is in Bus_Off state" rbitfld.long 0x4 6. "EW,Warning status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state" rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter,2: Receiver: node is operating as receiver,3: Transmitter: node is operating as transmitter" newline rbitfld.long 0x4 0.--2. "LEC,Last error code" "0: No error: No error occurred since LEC has been..,1: Stuff error: More than 5 equal bits in a..,2: Form error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the protocol status.." line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register" hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset" hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,FDCAN interrupt register" bitfld.long 0x0 29. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.." bitfld.long 0x0 26. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow,1: Overflow of CAN error logging counter occurred" newline bitfld.long 0x0 19. "DRX,Message stored to dedicated Rx buffer" "0: No Rx buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM access failure" "0: No message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp wraparound" "0: No timestamp counter wraparound,1: Timestamp counter wraparound" newline bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached" "0: Tx event FIFO fill level below watermark,1: Tx event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High priority message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register" bitfld.long 0x4 29. "ARAE,Access to Reserved address enable" "0,1" bitfld.long 0x4 28. "PEDE,Protocol error in data phase enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol error in Arbitration phase enable" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to dedicated Rx buffer interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register" bitfld.long 0x8 29. "ARAL,Access to reserved address line" "0,1" bitfld.long 0x8 28. "PEDL,Protocol error in data phase line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase line" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog interrupt line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off status" "0,1" bitfld.long 0x8 24. "EWL,Warning status interrupt line" "0,1" newline bitfld.long 0x8 23. "EPL,Error passive interrupt line" "0,1" bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to dedicated Rx buffer interrupt line" "0,1" bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx event FIFO element Lost interrupt line" "0,1" bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line" "0,1" bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line" "0,1" bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission completed interrupt line" "0,1" bitfld.long 0x8 8. "HPML,High priority message interrupt line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line" "0,1" line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register" bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled" bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN global filter configuration register" bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard ID,1: Reject all remote frames with 11-bit standard ID" bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard ID,1: Reject all remote frames with 29-bit standard ID" line.long 0x4 "FDCAN_SIDFC,FDCAN standard ID filter configuration register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address" line.long 0x8 "FDCAN_XIDFC,FDCAN extended ID filter configuration register" hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN extended ID and mask register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "FDCAN_HPMS,FDCAN high priority message status register" bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index" newline bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index" group.long 0x98++0x1B line.long 0x0 "FDCAN_NDAT1,FDCAN new data 1 register" bitfld.long 0x0 31. "ND31,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 30. "ND30,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 28. "ND28,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 26. "ND26,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 24. "ND24,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 22. "ND22,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 20. "ND20,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 18. "ND18,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 16. "ND16,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 14. "ND14,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 12. "ND12,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 10. "ND10,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 8. "ND8,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 6. "ND6,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 4. "ND4,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 2. "ND2,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 0. "ND0,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x4 "FDCAN_NDAT2,FDCAN new data 2 register" bitfld.long 0x4 31. "ND63,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 30. "ND62,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 28. "ND60,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 26. "ND58,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 24. "ND56,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 22. "ND54,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 20. "ND52,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 18. "ND50,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 16. "ND48,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 14. "ND46,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 12. "ND44,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 10. "ND42,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 8. "ND40,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 6. "ND38,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 4. "ND36,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 2. "ND34,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 0. "ND32,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x8 "FDCAN_RXF0C,FDCAN Rx FIFO 0 configuration register" bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,FIFO 0 watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address" line.long 0xC "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register" bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0xC 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index" hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index" newline hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level" line.long 0x10 "FDCAN_RXF0A,FDCAN Rx FIFO 0 acknowledge register" hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index" line.long 0x14 "FDCAN_RXBC,FDCAN Rx buffer configuration register" hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address" line.long 0x18 "FDCAN_RXF1C,FDCAN Rx FIFO 1 configuration register" bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark" newline hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size" hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address" rgroup.long 0xB4++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register" bitfld.long 0x0 30.--31. "DMS,Debug message status" "0: Idle state wait for reception of debug messages,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level" group.long 0xB8++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index" rgroup.long 0xBC++0x3 line.long 0x0 "FDCAN_RXESC,FDCAN Rx buffer element size configuration register" bitfld.long 0x0 8.--10. "RBDS,Rx buffer data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 0 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" newline bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 1 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 30. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation." hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/queue size" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of dedicated transmit buffers" hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx buffers start address" rgroup.long 0xC4++0xB line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register" bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/queue put index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO get index." hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO free level" line.long 0x4 "FDCAN_TXESC,FDCAN Tx buffer element size configuration register" bitfld.long 0x4 0.--2. "TBDS,Tx buffer data Field size:" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" line.long 0x8 "FDCAN_TXBRP,FDCAN Tx buffer request pending register" hexmask.long 0x8 0.--31. 1. "TRP,Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register" hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register" hexmask.long 0x4 0.--31. 1. "CR,Cancellation request" rgroup.long 0xD8++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register" hexmask.long 0x0 0.--31. 1. "TO,Transmission occurred" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register" hexmask.long 0x4 0.--31. 1. "CF,Cancellation finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register" hexmask.long 0x0 0.--31. 1. "TIE,Transmission interrupt enable" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register" hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation finished interrupt enable" group.long 0xF0++0x3 line.long 0x0 "FDCAN_TXEFC,FDCAN Tx event FIFO configuration register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address" rgroup.long 0xF4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register" bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO put index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level" group.long 0xF8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT trigger memory configuration register" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger memory elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger memory start address." line.long 0x4 "FDCAN_TTRMC,FDCAN TT reference message configuration register" bitfld.long 0x4 31. "RMPS,Reference message payload select" "0: Reference message has no additional payload,1: The following elements are taken from Tx buffer 0:" bitfld.long 0x4 30. "XTD,Extended identifier" "0: 11-bit standard identifier,1: 29-bit extended identifier" newline hexmask.long 0x4 0.--28. 1. "RID,Reference identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT operation configuration register" bitfld.long 0x8 26. "EVTP,Event trigger polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x8 25. "ECC,Enable clock calibration." "0: Automatic clock calibration in FDCAN level 0 2..,1: Automatic clock calibration in FDCAN level 0 2.." newline bitfld.long 0x8 24. "EGTF,Enable global time filtering." "0: Global time filtering in FDCAN level 0 2 is..,1: Global time filtering in FDCAN level 0 2 is.." hexmask.long.byte 0x8 16.--23. 1. "AWL,Application watchdog limit." newline bitfld.long 0x8 15. "EECS,Enable external clock synchronization" "0: External clock synchronization in FDCAN level 0..,1: External clock synchronization in FDCAN level 0.." hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial reference trigger offset." newline bitfld.long 0x8 5.--7. "LDSDL,LD of synchronization deviation limit." "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time master." "0: Time master function disabled,1: Potential time master" newline bitfld.long 0x8 3. "GEN,Gap enable." "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.." bitfld.long 0x8 0.--1. "OM,Operation mode." "0: Event-driven CAN communication default,1: TTCAN level 1,2: TTCAN level 2,3: TTCAN level 0" line.long 0xC "FDCAN_TTMLM,FDCAN TT matrix limits register" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected number of Tx triggers" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx enable window" newline bitfld.long 0xC 6.--7. "CSS,Cycle start synchronization" "0: No sync pulse,1: Sync pulse at start of basic cycle,2: Sync pulse at start of matrix cycle,?" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR configuration register" bitfld.long 0x10 31. "ELT,Enable local time." "0: Local time is stopped default,1: Local time is enabled" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator configuration." newline hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator configuration low." line.long 0x14 "FDCAN_TTOCN,FDCAN TT operation control register" rbitfld.long 0x14 15. "LCKC,TT operation control register locked." "0: Write access to FDCAN_TTOCN enabled,1: Write access to FDCAN_TTOCN locked" bitfld.long 0x14 13. "ESCN,External synchronization control" "0: External synchronization disabled,1: External synchronization enabled" newline bitfld.long 0x14 12. "NIG,Next is gap." "0: No action reset by reception of any reference..,1: Transmit next reference message with Next_is_Gap.." bitfld.long 0x14 11. "TMG,Time mark gap." "0: Reset by each reference message,1: Next reference message started when register.." newline bitfld.long 0x14 10. "FGP,Finish gap." "0: No reference message requested,1: Application requested start of reference message" bitfld.long 0x14 9. "GCS,Gap control select" "0: Gap control independent from event trigger,1: Gap control by input event trigger pin" newline bitfld.long 0x14 8. "TTIE,Trigger time mark interrupt pulse enable" "0: Trigger time mark interrupt output fdcan1_tmp..,1: Trigger time mark interrupt output fdcan1_tmp.." bitfld.long 0x14 6.--7. "TMC,Register time mark compare." "0: No Register time mark interrupt generated,1: Register time mark interrupt if time mark =..,2: Register time mark interrupt if time mark =..,3: Register time mark interrupt if time mark =.." newline bitfld.long 0x14 5. "RTIE,Register time mark interrupt pulse enable." "0: Register time mark interrupt output disabled,1: Register time mark interrupt output enabled" bitfld.long 0x14 3.--4. "SWS,Stop watch source." "0: Stop watch disabled,1: Actual value of cycle time is copied to..,2: Actual value of local time is copied to..,3: Actual value of global time is copied to.." newline bitfld.long 0x14 2. "SWP,Stop watch polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x14 1. "ECS,External clock synchronization." "0,1" newline bitfld.long 0x14 0. "SGT,Set global time." "0,1" line.long 0x18 "FDCAN_TTGTP,FDCAN TT global time preset register" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle time target phase" hexmask.long.word 0x18 0.--15. 1. "TP,Time preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT time mark register" rbitfld.long 0x1C 31. "LCKM,TT time mark register locked" "0: Write access to FDCAN_TTTMK enabled,1: Write access to FDCAN_TTTMK locked" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time mark cycle code" newline hexmask.long.word 0x1C 0.--15. 1. "TM,Time mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT interrupt register" bitfld.long 0x20 18. "CER,Configuration error" "0: No error found in trigger list,1: Error found in trigger list" bitfld.long 0x20 17. "AW,Application watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time" newline bitfld.long 0x20 16. "WT,Watch trigger" "0: No missing reference message,1: Missing reference message (level 0: cycle time.." bitfld.long 0x20 15. "IWTG,Initialization watch trigger" "0,1" newline bitfld.long 0x20 14. "ELC,Error level changed" "0: No change in error level,1: Error level changed" bitfld.long 0x20 13. "SE2,Scheduling error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred" newline bitfld.long 0x20 12. "SE1,Scheduling error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred" bitfld.long 0x20 11. "TXO,Tx count overflow" "0: Number of Tx trigger as expected,1: More Tx trigger than expected in one cycle" newline bitfld.long 0x20 10. "TXU,Tx count underflow" "0: Number of Tx trigger as expected,1: Less Tx trigger than expected in one cycle" bitfld.long 0x20 9. "GTE,Global time error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit" newline bitfld.long 0x20 8. "GTD,Global time discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time" bitfld.long 0x20 7. "GTW,Global time wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred" newline bitfld.long 0x20 6. "SWE,Stop watch event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.." bitfld.long 0x20 5. "TTMI,Trigger time mark event internal" "0: Time mark not reached,1: Time mark reached (level 0: cycle time.." newline bitfld.long 0x20 4. "RTMI,Register time mark interrupt" "0: Time mark not reached,1: Time mark reached" bitfld.long 0x20 3. "SOG,Start of gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of synchronization mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.." bitfld.long 0x20 1. "SMC,Start of matrix cycle" "0: No matrix cycle started since bit has been reset,1: Matrix cycle started" newline bitfld.long 0x20 0. "SBC,Start of basic cycle" "0: No basic cycle started since bit has been reset,1: Basic cycle started" line.long 0x24 "FDCAN_TTIE,FDCAN TT interrupt enable register" bitfld.long 0x24 18. "CERE,Configuration error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 17. "AWE,Application watchdog interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 16. "WTE,Watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 15. "IWTE,Initialization watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 14. "ELCE,Change error level interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 13. "SE2E,Scheduling error 2 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 12. "SE1E,Scheduling error 1 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 11. "TXOE,Tx count overflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 10. "TXUE,Tx count underflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 9. "GTEE,Global time error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 8. "GTDE,Global time discontinuity interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 7. "GTWE,Global time wrap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 6. "SWEE,Stop watch event interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 5. "TTMIE,Trigger time mark event internal interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 4. "RTMIE,Register time mark interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 3. "SOGE,Start of gap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 2. "CSME,Change of synchronization mode interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 1. "SMCE,Start of matrix cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 0. "SBCE,Start of basic cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" line.long 0x28 "FDCAN_TTILS,FDCAN TT interrupt line select register" bitfld.long 0x28 18. "CERL,Configuration error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 17. "AWL,Application watchdog interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 16. "WTL,Watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 15. "IWTL,Initialization watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 14. "ELCL,Change error level interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 13. "SE2L,Scheduling error 2 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 12. "SE1L,Scheduling error 1 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 11. "TXOL,Tx count overflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 10. "TXUL,Tx count underflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 9. "GTEL,Global time error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 8. "GTDL,Global time discontinuity interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 7. "GTWL,Global time wrap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 6. "SWEL,Stop watch event interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 5. "TTMIL,Trigger time mark event internal interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 4. "RTMIL,Register time mark interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 3. "SOGL,Start of gap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 2. "CSML,Change of synchronization mode interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 1. "SMCL,Start of matrix cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 0. "SBCL,Start of basic cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT operation status register" bitfld.long 0x0 31. "SPL,Schedule phase lock" "0: Phase outside range,1: Phase inside range" bitfld.long 0x0 30. "WECS,Wait for external clock synchronization." "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.." newline bitfld.long 0x0 29. "AWE,Application watchdog event" "0: Application watchdog served in time,1: Failed to serve application watchdog in time" bitfld.long 0x0 28. "WFE,Wait for event" "0: No gap announced reset by a reference message..,1: Reference message with Next_is_Gap = 1 received" newline bitfld.long 0x0 27. "GSI,Gap started indicator" "0: No gap in schedule reset by each reference..,1: Gap time after basic cycle has started" bitfld.long 0x0 24.--26. "TMP,Time master priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GFI,Gap finished indicator" "0: Reset at the end of each reference message,1: Gap finished by FDCAN" bitfld.long 0x0 22. "WGTD,Wait for global time discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.." newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference trigger offset" bitfld.long 0x0 7. "QCS,Quality of clock speed" "0: Local clock speed not synchronized to time..,1: Synchronization deviation less than or equal SDL" newline bitfld.long 0x0 6. "QGTP,Quality of global time phase" "0: Global time not valid,1: Global time in phase with time master" bitfld.long 0x0 4.--5. "SYS,Synchronization state" "0: Out of Synchronization,1: Synchronizing to FDCAN communication,2: Schedule suspended by gap (In_Gap),3: Synchronized to schedule (In_Schedule)" newline bitfld.long 0x0 2.--3. "MS,Master state" "0: Master_Off no master properties relevant,1: Operating as time Slave,2: Operating as backup time master,3: Operating as current time master" bitfld.long 0x0 0.--1. "EL,Error level" "0: Severity 0 - No error,1: Severity 1 - Warning,2: Severity 2 - error,3: Severity 3 - Severe error" line.long 0x4 "FDCAN_TURNA,FDCAN TUR numerator actual register" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator actual value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT local and global time register" hexmask.long.word 0x8 16.--31. 1. "GT,Global time" hexmask.long.word 0x8 0.--15. 1. "LT,Local time" line.long 0xC "FDCAN_TTCTC,FDCAN TT cycle time and count register" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT capture time register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop watch value" hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle count value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT cycle sync mark register" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle sync mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT trigger select register" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input selection" "0: fdcan1_evt0,1: fdcan1_evt1,2: fdcan1_evt2,3: fdcan1_evt3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input selection" "0: fdcan1_swt0,1: fdcan1_swt1,2: fdcan1_swt2,3: fdcan1_swt3" tree.end tree "FDCAN2" base ad:0x4000A400 rgroup.long 0x0++0x3 line.long 0x0 "FDCAN_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 3" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 2" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year = 4" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day =18" rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CCU_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 1" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 1" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year =" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day = 18" line.long 0x4 "FDCAN_ENDN,FDCAN Endian register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test value" group.long 0x4++0x3 line.long 0x0 "FDCAN_CCU_CCFG,FDCAN Endian register" bitfld.long 0x0 31. "SWR,Software reset" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CDIV,Clock divider" newline hexmask.long.byte 0x0 8.--15. 1. "OCPM,Oscillator clock periods minimum" bitfld.long 0x0 7. "CFL,Calibration field length" "0: Calibration field length is 32 bits,1: Calibration field length is 64 bits" newline bitfld.long 0x0 6. "BCC,Bypass clock calibration" "0: Clock calibration unit generates time quanta clock,1: Clock calibration unit bypassed (default.." hexmask.long.byte 0x0 0.--4. 1. "TQBT,Time quanta per bit time" rgroup.long 0x8++0x3 line.long 0x0 "FDCAN_CCU_CSTAT,Calibration status register" bitfld.long 0x0 30.--31. "CALS,Calibration state" "0: Not_Calibrated,1: Basic_Calibrated,2: Precision_Calibrated,?" hexmask.long.word 0x0 18.--28. 1. "TQC,Time quanta counter" newline hexmask.long.tbyte 0x0 0.--17. 1. "OCPC,Oscillator clock period counter" group.long 0xC++0x3 line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register" bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bitrate prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width" group.long 0xC++0x7 line.long 0x0 "FDCAN_CCU_CWD,FDCAN data bit timing and prescaler register" hexmask.long.word 0x0 16.--31. 1. "WDV,Watchdog value" hexmask.long.word 0x0 0.--15. 1. "WDC,WDC" line.long 0x4 "FDCAN_TEST,FDCAN test register" rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)" bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX" newline bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value loop back mode is disabled,1: Loop back mode is enabled (see Test modes)" group.long 0x10++0x7 line.long 0x0 "FDCAN_CCU_IR,FDCAN test register" bitfld.long 0x0 1. "CSC,Calibration state changed" "0: Calibration state unchanged,1: Calibration state has changed" bitfld.long 0x0 0. "CWE,Calibration watchdog event" "0: No calibration watchdog event,1: Calibration watchdog event occurred" line.long 0x4 "FDCAN_RWD,FDCAN RAM watchdog register" hexmask.long.byte 0x4 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x4 0.--7. 1. "WDC,Watchdog configuration" group.long 0x14++0x1B line.long 0x0 "FDCAN_CCU_IE,FDCAN RAM watchdog register" bitfld.long 0x0 1. "CSCE,Calibration state changed enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 0. "CWEE,Calibration watchdog event enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x4 "FDCAN_CCCR,FDCAN CC control register" bitfld.long 0x4 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x4 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: Disabled,1: Enabled" newline bitfld.long 0x4 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0x4 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0x4 9. "BRSE,FDCAN bitrate switching" "0: Bitrate switching for transmissions disabled,1: Bitrate switching for transmissions enabled" bitfld.long 0x4 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0x4 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test mode write access to register TEST enabled" bitfld.long 0x4 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0x4 5. "MON,Bus monitoring mode" "0: Bus monitoring mode is disabled,1: Bus monitoring mode is enabled" bitfld.long 0x4 4. "CSR,Clock stop request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline rbitfld.long 0x4 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.." bitfld.long 0x4 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation mode active" newline bitfld.long 0x4 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0x4 0. "INIT,Initialization" "0: Normal operation,1: Initialization is started (while FDCAN_CCCR.INIT.." line.long 0x8 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register" hexmask.long.byte 0x8 25.--31. 1. "NSJW,Nominal (re)synchronization jump width" hexmask.long.word 0x8 16.--24. 1. "NBRP,Bitrate prescaler" newline hexmask.long.byte 0x8 8.--15. 1. "NTSEG1,Nominal time segment before sample point" hexmask.long.byte 0x8 0.--6. 1. "NTSEG2,Nominal time segment after sample point" line.long 0xC "FDCAN_TSCC,FDCAN timestamp counter configuration register" hexmask.long.byte 0xC 16.--19. 1. "TCP,Timestamp counter prescaler" bitfld.long 0xC 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value used..,3: Same as 00." line.long 0x10 "FDCAN_TSCV,FDCAN timestamp counter value register" hexmask.long.word 0x10 0.--15. 1. "TSC,Timestamp counter" line.long 0x14 "FDCAN_TOCC,FDCAN timeout counter configuration register" hexmask.long.word 0x14 16.--31. 1. "TOP,Timeout period" bitfld.long 0x14 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x14 0. "ETOC,Enable timeout counter" "0: Timeout counter disabled,1: Timeout counter enabled" line.long 0x18 "FDCAN_TOCV,FDCAN timeout counter value register" hexmask.long.word 0x18 0.--15. 1. "TOC,Timeout counter" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN error counter register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging" rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter" line.long 0x4 "FDCAN_PSR,FDCAN protocol status register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value" bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not ha ve its..,1: Last received FDCAN message had its ESI flag set" rbitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off,1: The FDCAN is in Bus_Off state" rbitfld.long 0x4 6. "EW,Warning status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state" rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter,2: Receiver: node is operating as receiver,3: Transmitter: node is operating as transmitter" newline rbitfld.long 0x4 0.--2. "LEC,Last error code" "0: No error: No error occurred since LEC has been..,1: Stuff error: More than 5 equal bits in a..,2: Form error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the protocol status.." line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register" hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset" hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,FDCAN interrupt register" bitfld.long 0x0 29. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.." bitfld.long 0x0 26. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow,1: Overflow of CAN error logging counter occurred" newline bitfld.long 0x0 19. "DRX,Message stored to dedicated Rx buffer" "0: No Rx buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM access failure" "0: No message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp wraparound" "0: No timestamp counter wraparound,1: Timestamp counter wraparound" newline bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached" "0: Tx event FIFO fill level below watermark,1: Tx event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High priority message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register" bitfld.long 0x4 29. "ARAE,Access to Reserved address enable" "0,1" bitfld.long 0x4 28. "PEDE,Protocol error in data phase enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol error in Arbitration phase enable" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to dedicated Rx buffer interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register" bitfld.long 0x8 29. "ARAL,Access to reserved address line" "0,1" bitfld.long 0x8 28. "PEDL,Protocol error in data phase line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase line" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog interrupt line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off status" "0,1" bitfld.long 0x8 24. "EWL,Warning status interrupt line" "0,1" newline bitfld.long 0x8 23. "EPL,Error passive interrupt line" "0,1" bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to dedicated Rx buffer interrupt line" "0,1" bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx event FIFO element Lost interrupt line" "0,1" bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line" "0,1" bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line" "0,1" bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission completed interrupt line" "0,1" bitfld.long 0x8 8. "HPML,High priority message interrupt line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line" "0,1" line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register" bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled" bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN global filter configuration register" bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard ID,1: Reject all remote frames with 11-bit standard ID" bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard ID,1: Reject all remote frames with 29-bit standard ID" line.long 0x4 "FDCAN_SIDFC,FDCAN standard ID filter configuration register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address" line.long 0x8 "FDCAN_XIDFC,FDCAN extended ID filter configuration register" hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN extended ID and mask register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "FDCAN_HPMS,FDCAN high priority message status register" bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index" newline bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index" group.long 0x98++0x1B line.long 0x0 "FDCAN_NDAT1,FDCAN new data 1 register" bitfld.long 0x0 31. "ND31,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 30. "ND30,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 28. "ND28,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 26. "ND26,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 24. "ND24,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 22. "ND22,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 20. "ND20,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 18. "ND18,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 16. "ND16,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 14. "ND14,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 12. "ND12,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 10. "ND10,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 8. "ND8,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 6. "ND6,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 4. "ND4,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 2. "ND2,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 0. "ND0,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x4 "FDCAN_NDAT2,FDCAN new data 2 register" bitfld.long 0x4 31. "ND63,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 30. "ND62,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 28. "ND60,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 26. "ND58,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 24. "ND56,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 22. "ND54,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 20. "ND52,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 18. "ND50,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 16. "ND48,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 14. "ND46,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 12. "ND44,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 10. "ND42,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 8. "ND40,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 6. "ND38,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 4. "ND36,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 2. "ND34,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 0. "ND32,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x8 "FDCAN_RXF0C,FDCAN Rx FIFO 0 configuration register" bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,FIFO 0 watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address" line.long 0xC "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register" bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0xC 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index" hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index" newline hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level" line.long 0x10 "FDCAN_RXF0A,FDCAN Rx FIFO 0 acknowledge register" hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index" line.long 0x14 "FDCAN_RXBC,FDCAN Rx buffer configuration register" hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address" line.long 0x18 "FDCAN_RXF1C,FDCAN Rx FIFO 1 configuration register" bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark" newline hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size" hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address" rgroup.long 0xB4++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register" bitfld.long 0x0 30.--31. "DMS,Debug message status" "0: Idle state wait for reception of debug messages,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level" group.long 0xB8++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index" rgroup.long 0xBC++0x3 line.long 0x0 "FDCAN_RXESC,FDCAN Rx buffer element size configuration register" bitfld.long 0x0 8.--10. "RBDS,Rx buffer data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 0 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" newline bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 1 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 30. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation." hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/queue size" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of dedicated transmit buffers" hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx buffers start address" rgroup.long 0xC4++0xB line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register" bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/queue put index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO get index." hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO free level" line.long 0x4 "FDCAN_TXESC,FDCAN Tx buffer element size configuration register" bitfld.long 0x4 0.--2. "TBDS,Tx buffer data Field size:" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" line.long 0x8 "FDCAN_TXBRP,FDCAN Tx buffer request pending register" hexmask.long 0x8 0.--31. 1. "TRP,Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register" hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register" hexmask.long 0x4 0.--31. 1. "CR,Cancellation request" rgroup.long 0xD8++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register" hexmask.long 0x0 0.--31. 1. "TO,Transmission occurred" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register" hexmask.long 0x4 0.--31. 1. "CF,Cancellation finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register" hexmask.long 0x0 0.--31. 1. "TIE,Transmission interrupt enable" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register" hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation finished interrupt enable" group.long 0xF0++0x3 line.long 0x0 "FDCAN_TXEFC,FDCAN Tx event FIFO configuration register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address" rgroup.long 0xF4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register" bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO put index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level" group.long 0xF8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT trigger memory configuration register" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger memory elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger memory start address." line.long 0x4 "FDCAN_TTRMC,FDCAN TT reference message configuration register" bitfld.long 0x4 31. "RMPS,Reference message payload select" "0: Reference message has no additional payload,1: The following elements are taken from Tx buffer 0:" bitfld.long 0x4 30. "XTD,Extended identifier" "0: 11-bit standard identifier,1: 29-bit extended identifier" newline hexmask.long 0x4 0.--28. 1. "RID,Reference identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT operation configuration register" bitfld.long 0x8 26. "EVTP,Event trigger polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x8 25. "ECC,Enable clock calibration." "0: Automatic clock calibration in FDCAN level 0 2..,1: Automatic clock calibration in FDCAN level 0 2.." newline bitfld.long 0x8 24. "EGTF,Enable global time filtering." "0: Global time filtering in FDCAN level 0 2 is..,1: Global time filtering in FDCAN level 0 2 is.." hexmask.long.byte 0x8 16.--23. 1. "AWL,Application watchdog limit." newline bitfld.long 0x8 15. "EECS,Enable external clock synchronization" "0: External clock synchronization in FDCAN level 0..,1: External clock synchronization in FDCAN level 0.." hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial reference trigger offset." newline bitfld.long 0x8 5.--7. "LDSDL,LD of synchronization deviation limit." "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time master." "0: Time master function disabled,1: Potential time master" newline bitfld.long 0x8 3. "GEN,Gap enable." "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.." bitfld.long 0x8 0.--1. "OM,Operation mode." "0: Event-driven CAN communication default,1: TTCAN level 1,2: TTCAN level 2,3: TTCAN level 0" line.long 0xC "FDCAN_TTMLM,FDCAN TT matrix limits register" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected number of Tx triggers" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx enable window" newline bitfld.long 0xC 6.--7. "CSS,Cycle start synchronization" "0: No sync pulse,1: Sync pulse at start of basic cycle,2: Sync pulse at start of matrix cycle,?" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR configuration register" bitfld.long 0x10 31. "ELT,Enable local time." "0: Local time is stopped default,1: Local time is enabled" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator configuration." newline hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator configuration low." line.long 0x14 "FDCAN_TTOCN,FDCAN TT operation control register" rbitfld.long 0x14 15. "LCKC,TT operation control register locked." "0: Write access to FDCAN_TTOCN enabled,1: Write access to FDCAN_TTOCN locked" bitfld.long 0x14 13. "ESCN,External synchronization control" "0: External synchronization disabled,1: External synchronization enabled" newline bitfld.long 0x14 12. "NIG,Next is gap." "0: No action reset by reception of any reference..,1: Transmit next reference message with Next_is_Gap.." bitfld.long 0x14 11. "TMG,Time mark gap." "0: Reset by each reference message,1: Next reference message started when register.." newline bitfld.long 0x14 10. "FGP,Finish gap." "0: No reference message requested,1: Application requested start of reference message" bitfld.long 0x14 9. "GCS,Gap control select" "0: Gap control independent from event trigger,1: Gap control by input event trigger pin" newline bitfld.long 0x14 8. "TTIE,Trigger time mark interrupt pulse enable" "0: Trigger time mark interrupt output fdcan1_tmp..,1: Trigger time mark interrupt output fdcan1_tmp.." bitfld.long 0x14 6.--7. "TMC,Register time mark compare." "0: No Register time mark interrupt generated,1: Register time mark interrupt if time mark =..,2: Register time mark interrupt if time mark =..,3: Register time mark interrupt if time mark =.." newline bitfld.long 0x14 5. "RTIE,Register time mark interrupt pulse enable." "0: Register time mark interrupt output disabled,1: Register time mark interrupt output enabled" bitfld.long 0x14 3.--4. "SWS,Stop watch source." "0: Stop watch disabled,1: Actual value of cycle time is copied to..,2: Actual value of local time is copied to..,3: Actual value of global time is copied to.." newline bitfld.long 0x14 2. "SWP,Stop watch polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x14 1. "ECS,External clock synchronization." "0,1" newline bitfld.long 0x14 0. "SGT,Set global time." "0,1" line.long 0x18 "FDCAN_TTGTP,FDCAN TT global time preset register" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle time target phase" hexmask.long.word 0x18 0.--15. 1. "TP,Time preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT time mark register" rbitfld.long 0x1C 31. "LCKM,TT time mark register locked" "0: Write access to FDCAN_TTTMK enabled,1: Write access to FDCAN_TTTMK locked" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time mark cycle code" newline hexmask.long.word 0x1C 0.--15. 1. "TM,Time mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT interrupt register" bitfld.long 0x20 18. "CER,Configuration error" "0: No error found in trigger list,1: Error found in trigger list" bitfld.long 0x20 17. "AW,Application watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time" newline bitfld.long 0x20 16. "WT,Watch trigger" "0: No missing reference message,1: Missing reference message (level 0: cycle time.." bitfld.long 0x20 15. "IWTG,Initialization watch trigger" "0,1" newline bitfld.long 0x20 14. "ELC,Error level changed" "0: No change in error level,1: Error level changed" bitfld.long 0x20 13. "SE2,Scheduling error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred" newline bitfld.long 0x20 12. "SE1,Scheduling error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred" bitfld.long 0x20 11. "TXO,Tx count overflow" "0: Number of Tx trigger as expected,1: More Tx trigger than expected in one cycle" newline bitfld.long 0x20 10. "TXU,Tx count underflow" "0: Number of Tx trigger as expected,1: Less Tx trigger than expected in one cycle" bitfld.long 0x20 9. "GTE,Global time error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit" newline bitfld.long 0x20 8. "GTD,Global time discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time" bitfld.long 0x20 7. "GTW,Global time wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred" newline bitfld.long 0x20 6. "SWE,Stop watch event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.." bitfld.long 0x20 5. "TTMI,Trigger time mark event internal" "0: Time mark not reached,1: Time mark reached (level 0: cycle time.." newline bitfld.long 0x20 4. "RTMI,Register time mark interrupt" "0: Time mark not reached,1: Time mark reached" bitfld.long 0x20 3. "SOG,Start of gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of synchronization mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.." bitfld.long 0x20 1. "SMC,Start of matrix cycle" "0: No matrix cycle started since bit has been reset,1: Matrix cycle started" newline bitfld.long 0x20 0. "SBC,Start of basic cycle" "0: No basic cycle started since bit has been reset,1: Basic cycle started" line.long 0x24 "FDCAN_TTIE,FDCAN TT interrupt enable register" bitfld.long 0x24 18. "CERE,Configuration error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 17. "AWE,Application watchdog interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 16. "WTE,Watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 15. "IWTE,Initialization watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 14. "ELCE,Change error level interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 13. "SE2E,Scheduling error 2 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 12. "SE1E,Scheduling error 1 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 11. "TXOE,Tx count overflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 10. "TXUE,Tx count underflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 9. "GTEE,Global time error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 8. "GTDE,Global time discontinuity interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 7. "GTWE,Global time wrap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 6. "SWEE,Stop watch event interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 5. "TTMIE,Trigger time mark event internal interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 4. "RTMIE,Register time mark interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 3. "SOGE,Start of gap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 2. "CSME,Change of synchronization mode interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 1. "SMCE,Start of matrix cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 0. "SBCE,Start of basic cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" line.long 0x28 "FDCAN_TTILS,FDCAN TT interrupt line select register" bitfld.long 0x28 18. "CERL,Configuration error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 17. "AWL,Application watchdog interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 16. "WTL,Watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 15. "IWTL,Initialization watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 14. "ELCL,Change error level interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 13. "SE2L,Scheduling error 2 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 12. "SE1L,Scheduling error 1 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 11. "TXOL,Tx count overflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 10. "TXUL,Tx count underflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 9. "GTEL,Global time error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 8. "GTDL,Global time discontinuity interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 7. "GTWL,Global time wrap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 6. "SWEL,Stop watch event interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 5. "TTMIL,Trigger time mark event internal interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 4. "RTMIL,Register time mark interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 3. "SOGL,Start of gap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 2. "CSML,Change of synchronization mode interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 1. "SMCL,Start of matrix cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 0. "SBCL,Start of basic cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT operation status register" bitfld.long 0x0 31. "SPL,Schedule phase lock" "0: Phase outside range,1: Phase inside range" bitfld.long 0x0 30. "WECS,Wait for external clock synchronization." "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.." newline bitfld.long 0x0 29. "AWE,Application watchdog event" "0: Application watchdog served in time,1: Failed to serve application watchdog in time" bitfld.long 0x0 28. "WFE,Wait for event" "0: No gap announced reset by a reference message..,1: Reference message with Next_is_Gap = 1 received" newline bitfld.long 0x0 27. "GSI,Gap started indicator" "0: No gap in schedule reset by each reference..,1: Gap time after basic cycle has started" bitfld.long 0x0 24.--26. "TMP,Time master priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GFI,Gap finished indicator" "0: Reset at the end of each reference message,1: Gap finished by FDCAN" bitfld.long 0x0 22. "WGTD,Wait for global time discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.." newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference trigger offset" bitfld.long 0x0 7. "QCS,Quality of clock speed" "0: Local clock speed not synchronized to time..,1: Synchronization deviation less than or equal SDL" newline bitfld.long 0x0 6. "QGTP,Quality of global time phase" "0: Global time not valid,1: Global time in phase with time master" bitfld.long 0x0 4.--5. "SYS,Synchronization state" "0: Out of Synchronization,1: Synchronizing to FDCAN communication,2: Schedule suspended by gap (In_Gap),3: Synchronized to schedule (In_Schedule)" newline bitfld.long 0x0 2.--3. "MS,Master state" "0: Master_Off no master properties relevant,1: Operating as time Slave,2: Operating as backup time master,3: Operating as current time master" bitfld.long 0x0 0.--1. "EL,Error level" "0: Severity 0 - No error,1: Severity 1 - Warning,2: Severity 2 - error,3: Severity 3 - Severe error" line.long 0x4 "FDCAN_TURNA,FDCAN TUR numerator actual register" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator actual value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT local and global time register" hexmask.long.word 0x8 16.--31. 1. "GT,Global time" hexmask.long.word 0x8 0.--15. 1. "LT,Local time" line.long 0xC "FDCAN_TTCTC,FDCAN TT cycle time and count register" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT capture time register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop watch value" hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle count value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT cycle sync mark register" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle sync mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT trigger select register" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input selection" "0: fdcan1_evt0,1: fdcan1_evt1,2: fdcan1_evt2,3: fdcan1_evt3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input selection" "0: fdcan1_swt0,1: fdcan1_swt1,2: fdcan1_swt2,3: fdcan1_swt3" tree.end tree "FDCAN2_S" base ad:0x5000A400 rgroup.long 0x0++0x3 line.long 0x0 "FDCAN_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 3" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 2" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year = 4" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day =18" rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CCU_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 1" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 1" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year =" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day = 18" line.long 0x4 "FDCAN_ENDN,FDCAN Endian register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test value" group.long 0x4++0x3 line.long 0x0 "FDCAN_CCU_CCFG,FDCAN Endian register" bitfld.long 0x0 31. "SWR,Software reset" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CDIV,Clock divider" newline hexmask.long.byte 0x0 8.--15. 1. "OCPM,Oscillator clock periods minimum" bitfld.long 0x0 7. "CFL,Calibration field length" "0: Calibration field length is 32 bits,1: Calibration field length is 64 bits" newline bitfld.long 0x0 6. "BCC,Bypass clock calibration" "0: Clock calibration unit generates time quanta clock,1: Clock calibration unit bypassed (default.." hexmask.long.byte 0x0 0.--4. 1. "TQBT,Time quanta per bit time" rgroup.long 0x8++0x3 line.long 0x0 "FDCAN_CCU_CSTAT,Calibration status register" bitfld.long 0x0 30.--31. "CALS,Calibration state" "0: Not_Calibrated,1: Basic_Calibrated,2: Precision_Calibrated,?" hexmask.long.word 0x0 18.--28. 1. "TQC,Time quanta counter" newline hexmask.long.tbyte 0x0 0.--17. 1. "OCPC,Oscillator clock period counter" group.long 0xC++0x3 line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register" bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bitrate prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width" group.long 0xC++0x7 line.long 0x0 "FDCAN_CCU_CWD,FDCAN data bit timing and prescaler register" hexmask.long.word 0x0 16.--31. 1. "WDV,Watchdog value" hexmask.long.word 0x0 0.--15. 1. "WDC,WDC" line.long 0x4 "FDCAN_TEST,FDCAN test register" rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)" bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX" newline bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value loop back mode is disabled,1: Loop back mode is enabled (see Test modes)" group.long 0x10++0x7 line.long 0x0 "FDCAN_CCU_IR,FDCAN test register" bitfld.long 0x0 1. "CSC,Calibration state changed" "0: Calibration state unchanged,1: Calibration state has changed" bitfld.long 0x0 0. "CWE,Calibration watchdog event" "0: No calibration watchdog event,1: Calibration watchdog event occurred" line.long 0x4 "FDCAN_RWD,FDCAN RAM watchdog register" hexmask.long.byte 0x4 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x4 0.--7. 1. "WDC,Watchdog configuration" group.long 0x14++0x1B line.long 0x0 "FDCAN_CCU_IE,FDCAN RAM watchdog register" bitfld.long 0x0 1. "CSCE,Calibration state changed enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 0. "CWEE,Calibration watchdog event enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x4 "FDCAN_CCCR,FDCAN CC control register" bitfld.long 0x4 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x4 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: Disabled,1: Enabled" newline bitfld.long 0x4 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0x4 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0x4 9. "BRSE,FDCAN bitrate switching" "0: Bitrate switching for transmissions disabled,1: Bitrate switching for transmissions enabled" bitfld.long 0x4 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0x4 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test mode write access to register TEST enabled" bitfld.long 0x4 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0x4 5. "MON,Bus monitoring mode" "0: Bus monitoring mode is disabled,1: Bus monitoring mode is enabled" bitfld.long 0x4 4. "CSR,Clock stop request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline rbitfld.long 0x4 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.." bitfld.long 0x4 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation mode active" newline bitfld.long 0x4 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0x4 0. "INIT,Initialization" "0: Normal operation,1: Initialization is started (while FDCAN_CCCR.INIT.." line.long 0x8 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register" hexmask.long.byte 0x8 25.--31. 1. "NSJW,Nominal (re)synchronization jump width" hexmask.long.word 0x8 16.--24. 1. "NBRP,Bitrate prescaler" newline hexmask.long.byte 0x8 8.--15. 1. "NTSEG1,Nominal time segment before sample point" hexmask.long.byte 0x8 0.--6. 1. "NTSEG2,Nominal time segment after sample point" line.long 0xC "FDCAN_TSCC,FDCAN timestamp counter configuration register" hexmask.long.byte 0xC 16.--19. 1. "TCP,Timestamp counter prescaler" bitfld.long 0xC 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value used..,3: Same as 00." line.long 0x10 "FDCAN_TSCV,FDCAN timestamp counter value register" hexmask.long.word 0x10 0.--15. 1. "TSC,Timestamp counter" line.long 0x14 "FDCAN_TOCC,FDCAN timeout counter configuration register" hexmask.long.word 0x14 16.--31. 1. "TOP,Timeout period" bitfld.long 0x14 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x14 0. "ETOC,Enable timeout counter" "0: Timeout counter disabled,1: Timeout counter enabled" line.long 0x18 "FDCAN_TOCV,FDCAN timeout counter value register" hexmask.long.word 0x18 0.--15. 1. "TOC,Timeout counter" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN error counter register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging" rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter" line.long 0x4 "FDCAN_PSR,FDCAN protocol status register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value" bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not ha ve its..,1: Last received FDCAN message had its ESI flag set" rbitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off,1: The FDCAN is in Bus_Off state" rbitfld.long 0x4 6. "EW,Warning status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state" rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter,2: Receiver: node is operating as receiver,3: Transmitter: node is operating as transmitter" newline rbitfld.long 0x4 0.--2. "LEC,Last error code" "0: No error: No error occurred since LEC has been..,1: Stuff error: More than 5 equal bits in a..,2: Form error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the protocol status.." line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register" hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset" hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,FDCAN interrupt register" bitfld.long 0x0 29. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.." bitfld.long 0x0 26. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow,1: Overflow of CAN error logging counter occurred" newline bitfld.long 0x0 19. "DRX,Message stored to dedicated Rx buffer" "0: No Rx buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM access failure" "0: No message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp wraparound" "0: No timestamp counter wraparound,1: Timestamp counter wraparound" newline bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached" "0: Tx event FIFO fill level below watermark,1: Tx event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High priority message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register" bitfld.long 0x4 29. "ARAE,Access to Reserved address enable" "0,1" bitfld.long 0x4 28. "PEDE,Protocol error in data phase enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol error in Arbitration phase enable" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to dedicated Rx buffer interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register" bitfld.long 0x8 29. "ARAL,Access to reserved address line" "0,1" bitfld.long 0x8 28. "PEDL,Protocol error in data phase line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase line" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog interrupt line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off status" "0,1" bitfld.long 0x8 24. "EWL,Warning status interrupt line" "0,1" newline bitfld.long 0x8 23. "EPL,Error passive interrupt line" "0,1" bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to dedicated Rx buffer interrupt line" "0,1" bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx event FIFO element Lost interrupt line" "0,1" bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line" "0,1" bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line" "0,1" bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission completed interrupt line" "0,1" bitfld.long 0x8 8. "HPML,High priority message interrupt line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line" "0,1" line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register" bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled" bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN global filter configuration register" bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard ID,1: Reject all remote frames with 11-bit standard ID" bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard ID,1: Reject all remote frames with 29-bit standard ID" line.long 0x4 "FDCAN_SIDFC,FDCAN standard ID filter configuration register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address" line.long 0x8 "FDCAN_XIDFC,FDCAN extended ID filter configuration register" hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN extended ID and mask register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "FDCAN_HPMS,FDCAN high priority message status register" bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index" newline bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index" group.long 0x98++0x1B line.long 0x0 "FDCAN_NDAT1,FDCAN new data 1 register" bitfld.long 0x0 31. "ND31,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 30. "ND30,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 28. "ND28,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 26. "ND26,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 24. "ND24,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 22. "ND22,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 20. "ND20,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 18. "ND18,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 16. "ND16,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 14. "ND14,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 12. "ND12,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 10. "ND10,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 8. "ND8,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 6. "ND6,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 4. "ND4,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 2. "ND2,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 0. "ND0,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x4 "FDCAN_NDAT2,FDCAN new data 2 register" bitfld.long 0x4 31. "ND63,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 30. "ND62,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 28. "ND60,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 26. "ND58,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 24. "ND56,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 22. "ND54,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 20. "ND52,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 18. "ND50,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 16. "ND48,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 14. "ND46,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 12. "ND44,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 10. "ND42,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 8. "ND40,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 6. "ND38,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 4. "ND36,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 2. "ND34,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 0. "ND32,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x8 "FDCAN_RXF0C,FDCAN Rx FIFO 0 configuration register" bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,FIFO 0 watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address" line.long 0xC "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register" bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0xC 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index" hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index" newline hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level" line.long 0x10 "FDCAN_RXF0A,FDCAN Rx FIFO 0 acknowledge register" hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index" line.long 0x14 "FDCAN_RXBC,FDCAN Rx buffer configuration register" hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address" line.long 0x18 "FDCAN_RXF1C,FDCAN Rx FIFO 1 configuration register" bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark" newline hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size" hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address" rgroup.long 0xB4++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register" bitfld.long 0x0 30.--31. "DMS,Debug message status" "0: Idle state wait for reception of debug messages,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level" group.long 0xB8++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index" rgroup.long 0xBC++0x3 line.long 0x0 "FDCAN_RXESC,FDCAN Rx buffer element size configuration register" bitfld.long 0x0 8.--10. "RBDS,Rx buffer data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 0 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" newline bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 1 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 30. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation." hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/queue size" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of dedicated transmit buffers" hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx buffers start address" rgroup.long 0xC4++0xB line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register" bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/queue put index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO get index." hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO free level" line.long 0x4 "FDCAN_TXESC,FDCAN Tx buffer element size configuration register" bitfld.long 0x4 0.--2. "TBDS,Tx buffer data Field size:" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" line.long 0x8 "FDCAN_TXBRP,FDCAN Tx buffer request pending register" hexmask.long 0x8 0.--31. 1. "TRP,Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register" hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register" hexmask.long 0x4 0.--31. 1. "CR,Cancellation request" rgroup.long 0xD8++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register" hexmask.long 0x0 0.--31. 1. "TO,Transmission occurred" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register" hexmask.long 0x4 0.--31. 1. "CF,Cancellation finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register" hexmask.long 0x0 0.--31. 1. "TIE,Transmission interrupt enable" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register" hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation finished interrupt enable" group.long 0xF0++0x3 line.long 0x0 "FDCAN_TXEFC,FDCAN Tx event FIFO configuration register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address" rgroup.long 0xF4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register" bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO put index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level" group.long 0xF8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT trigger memory configuration register" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger memory elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger memory start address." line.long 0x4 "FDCAN_TTRMC,FDCAN TT reference message configuration register" bitfld.long 0x4 31. "RMPS,Reference message payload select" "0: Reference message has no additional payload,1: The following elements are taken from Tx buffer 0:" bitfld.long 0x4 30. "XTD,Extended identifier" "0: 11-bit standard identifier,1: 29-bit extended identifier" newline hexmask.long 0x4 0.--28. 1. "RID,Reference identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT operation configuration register" bitfld.long 0x8 26. "EVTP,Event trigger polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x8 25. "ECC,Enable clock calibration." "0: Automatic clock calibration in FDCAN level 0 2..,1: Automatic clock calibration in FDCAN level 0 2.." newline bitfld.long 0x8 24. "EGTF,Enable global time filtering." "0: Global time filtering in FDCAN level 0 2 is..,1: Global time filtering in FDCAN level 0 2 is.." hexmask.long.byte 0x8 16.--23. 1. "AWL,Application watchdog limit." newline bitfld.long 0x8 15. "EECS,Enable external clock synchronization" "0: External clock synchronization in FDCAN level 0..,1: External clock synchronization in FDCAN level 0.." hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial reference trigger offset." newline bitfld.long 0x8 5.--7. "LDSDL,LD of synchronization deviation limit." "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time master." "0: Time master function disabled,1: Potential time master" newline bitfld.long 0x8 3. "GEN,Gap enable." "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.." bitfld.long 0x8 0.--1. "OM,Operation mode." "0: Event-driven CAN communication default,1: TTCAN level 1,2: TTCAN level 2,3: TTCAN level 0" line.long 0xC "FDCAN_TTMLM,FDCAN TT matrix limits register" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected number of Tx triggers" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx enable window" newline bitfld.long 0xC 6.--7. "CSS,Cycle start synchronization" "0: No sync pulse,1: Sync pulse at start of basic cycle,2: Sync pulse at start of matrix cycle,?" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR configuration register" bitfld.long 0x10 31. "ELT,Enable local time." "0: Local time is stopped default,1: Local time is enabled" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator configuration." newline hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator configuration low." line.long 0x14 "FDCAN_TTOCN,FDCAN TT operation control register" rbitfld.long 0x14 15. "LCKC,TT operation control register locked." "0: Write access to FDCAN_TTOCN enabled,1: Write access to FDCAN_TTOCN locked" bitfld.long 0x14 13. "ESCN,External synchronization control" "0: External synchronization disabled,1: External synchronization enabled" newline bitfld.long 0x14 12. "NIG,Next is gap." "0: No action reset by reception of any reference..,1: Transmit next reference message with Next_is_Gap.." bitfld.long 0x14 11. "TMG,Time mark gap." "0: Reset by each reference message,1: Next reference message started when register.." newline bitfld.long 0x14 10. "FGP,Finish gap." "0: No reference message requested,1: Application requested start of reference message" bitfld.long 0x14 9. "GCS,Gap control select" "0: Gap control independent from event trigger,1: Gap control by input event trigger pin" newline bitfld.long 0x14 8. "TTIE,Trigger time mark interrupt pulse enable" "0: Trigger time mark interrupt output fdcan1_tmp..,1: Trigger time mark interrupt output fdcan1_tmp.." bitfld.long 0x14 6.--7. "TMC,Register time mark compare." "0: No Register time mark interrupt generated,1: Register time mark interrupt if time mark =..,2: Register time mark interrupt if time mark =..,3: Register time mark interrupt if time mark =.." newline bitfld.long 0x14 5. "RTIE,Register time mark interrupt pulse enable." "0: Register time mark interrupt output disabled,1: Register time mark interrupt output enabled" bitfld.long 0x14 3.--4. "SWS,Stop watch source." "0: Stop watch disabled,1: Actual value of cycle time is copied to..,2: Actual value of local time is copied to..,3: Actual value of global time is copied to.." newline bitfld.long 0x14 2. "SWP,Stop watch polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x14 1. "ECS,External clock synchronization." "0,1" newline bitfld.long 0x14 0. "SGT,Set global time." "0,1" line.long 0x18 "FDCAN_TTGTP,FDCAN TT global time preset register" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle time target phase" hexmask.long.word 0x18 0.--15. 1. "TP,Time preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT time mark register" rbitfld.long 0x1C 31. "LCKM,TT time mark register locked" "0: Write access to FDCAN_TTTMK enabled,1: Write access to FDCAN_TTTMK locked" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time mark cycle code" newline hexmask.long.word 0x1C 0.--15. 1. "TM,Time mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT interrupt register" bitfld.long 0x20 18. "CER,Configuration error" "0: No error found in trigger list,1: Error found in trigger list" bitfld.long 0x20 17. "AW,Application watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time" newline bitfld.long 0x20 16. "WT,Watch trigger" "0: No missing reference message,1: Missing reference message (level 0: cycle time.." bitfld.long 0x20 15. "IWTG,Initialization watch trigger" "0,1" newline bitfld.long 0x20 14. "ELC,Error level changed" "0: No change in error level,1: Error level changed" bitfld.long 0x20 13. "SE2,Scheduling error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred" newline bitfld.long 0x20 12. "SE1,Scheduling error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred" bitfld.long 0x20 11. "TXO,Tx count overflow" "0: Number of Tx trigger as expected,1: More Tx trigger than expected in one cycle" newline bitfld.long 0x20 10. "TXU,Tx count underflow" "0: Number of Tx trigger as expected,1: Less Tx trigger than expected in one cycle" bitfld.long 0x20 9. "GTE,Global time error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit" newline bitfld.long 0x20 8. "GTD,Global time discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time" bitfld.long 0x20 7. "GTW,Global time wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred" newline bitfld.long 0x20 6. "SWE,Stop watch event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.." bitfld.long 0x20 5. "TTMI,Trigger time mark event internal" "0: Time mark not reached,1: Time mark reached (level 0: cycle time.." newline bitfld.long 0x20 4. "RTMI,Register time mark interrupt" "0: Time mark not reached,1: Time mark reached" bitfld.long 0x20 3. "SOG,Start of gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of synchronization mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.." bitfld.long 0x20 1. "SMC,Start of matrix cycle" "0: No matrix cycle started since bit has been reset,1: Matrix cycle started" newline bitfld.long 0x20 0. "SBC,Start of basic cycle" "0: No basic cycle started since bit has been reset,1: Basic cycle started" line.long 0x24 "FDCAN_TTIE,FDCAN TT interrupt enable register" bitfld.long 0x24 18. "CERE,Configuration error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 17. "AWE,Application watchdog interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 16. "WTE,Watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 15. "IWTE,Initialization watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 14. "ELCE,Change error level interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 13. "SE2E,Scheduling error 2 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 12. "SE1E,Scheduling error 1 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 11. "TXOE,Tx count overflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 10. "TXUE,Tx count underflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 9. "GTEE,Global time error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 8. "GTDE,Global time discontinuity interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 7. "GTWE,Global time wrap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 6. "SWEE,Stop watch event interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 5. "TTMIE,Trigger time mark event internal interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 4. "RTMIE,Register time mark interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 3. "SOGE,Start of gap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 2. "CSME,Change of synchronization mode interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 1. "SMCE,Start of matrix cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 0. "SBCE,Start of basic cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" line.long 0x28 "FDCAN_TTILS,FDCAN TT interrupt line select register" bitfld.long 0x28 18. "CERL,Configuration error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 17. "AWL,Application watchdog interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 16. "WTL,Watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 15. "IWTL,Initialization watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 14. "ELCL,Change error level interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 13. "SE2L,Scheduling error 2 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 12. "SE1L,Scheduling error 1 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 11. "TXOL,Tx count overflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 10. "TXUL,Tx count underflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 9. "GTEL,Global time error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 8. "GTDL,Global time discontinuity interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 7. "GTWL,Global time wrap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 6. "SWEL,Stop watch event interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 5. "TTMIL,Trigger time mark event internal interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 4. "RTMIL,Register time mark interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 3. "SOGL,Start of gap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 2. "CSML,Change of synchronization mode interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 1. "SMCL,Start of matrix cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 0. "SBCL,Start of basic cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT operation status register" bitfld.long 0x0 31. "SPL,Schedule phase lock" "0: Phase outside range,1: Phase inside range" bitfld.long 0x0 30. "WECS,Wait for external clock synchronization." "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.." newline bitfld.long 0x0 29. "AWE,Application watchdog event" "0: Application watchdog served in time,1: Failed to serve application watchdog in time" bitfld.long 0x0 28. "WFE,Wait for event" "0: No gap announced reset by a reference message..,1: Reference message with Next_is_Gap = 1 received" newline bitfld.long 0x0 27. "GSI,Gap started indicator" "0: No gap in schedule reset by each reference..,1: Gap time after basic cycle has started" bitfld.long 0x0 24.--26. "TMP,Time master priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GFI,Gap finished indicator" "0: Reset at the end of each reference message,1: Gap finished by FDCAN" bitfld.long 0x0 22. "WGTD,Wait for global time discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.." newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference trigger offset" bitfld.long 0x0 7. "QCS,Quality of clock speed" "0: Local clock speed not synchronized to time..,1: Synchronization deviation less than or equal SDL" newline bitfld.long 0x0 6. "QGTP,Quality of global time phase" "0: Global time not valid,1: Global time in phase with time master" bitfld.long 0x0 4.--5. "SYS,Synchronization state" "0: Out of Synchronization,1: Synchronizing to FDCAN communication,2: Schedule suspended by gap (In_Gap),3: Synchronized to schedule (In_Schedule)" newline bitfld.long 0x0 2.--3. "MS,Master state" "0: Master_Off no master properties relevant,1: Operating as time Slave,2: Operating as backup time master,3: Operating as current time master" bitfld.long 0x0 0.--1. "EL,Error level" "0: Severity 0 - No error,1: Severity 1 - Warning,2: Severity 2 - error,3: Severity 3 - Severe error" line.long 0x4 "FDCAN_TURNA,FDCAN TUR numerator actual register" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator actual value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT local and global time register" hexmask.long.word 0x8 16.--31. 1. "GT,Global time" hexmask.long.word 0x8 0.--15. 1. "LT,Local time" line.long 0xC "FDCAN_TTCTC,FDCAN TT cycle time and count register" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT capture time register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop watch value" hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle count value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT cycle sync mark register" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle sync mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT trigger select register" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input selection" "0: fdcan1_evt0,1: fdcan1_evt1,2: fdcan1_evt2,3: fdcan1_evt3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input selection" "0: fdcan1_swt0,1: fdcan1_swt1,2: fdcan1_swt2,3: fdcan1_swt3" tree.end tree "FDCAN3" base ad:0x4000E800 rgroup.long 0x0++0x3 line.long 0x0 "FDCAN_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 3" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 2" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year = 4" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day =18" rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CCU_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 1" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 1" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year =" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day = 18" line.long 0x4 "FDCAN_ENDN,FDCAN Endian register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test value" group.long 0x4++0x3 line.long 0x0 "FDCAN_CCU_CCFG,FDCAN Endian register" bitfld.long 0x0 31. "SWR,Software reset" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CDIV,Clock divider" newline hexmask.long.byte 0x0 8.--15. 1. "OCPM,Oscillator clock periods minimum" bitfld.long 0x0 7. "CFL,Calibration field length" "0: Calibration field length is 32 bits,1: Calibration field length is 64 bits" newline bitfld.long 0x0 6. "BCC,Bypass clock calibration" "0: Clock calibration unit generates time quanta clock,1: Clock calibration unit bypassed (default.." hexmask.long.byte 0x0 0.--4. 1. "TQBT,Time quanta per bit time" rgroup.long 0x8++0x3 line.long 0x0 "FDCAN_CCU_CSTAT,Calibration status register" bitfld.long 0x0 30.--31. "CALS,Calibration state" "0: Not_Calibrated,1: Basic_Calibrated,2: Precision_Calibrated,?" hexmask.long.word 0x0 18.--28. 1. "TQC,Time quanta counter" newline hexmask.long.tbyte 0x0 0.--17. 1. "OCPC,Oscillator clock period counter" group.long 0xC++0x3 line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register" bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bitrate prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width" group.long 0xC++0x7 line.long 0x0 "FDCAN_CCU_CWD,FDCAN data bit timing and prescaler register" hexmask.long.word 0x0 16.--31. 1. "WDV,Watchdog value" hexmask.long.word 0x0 0.--15. 1. "WDC,WDC" line.long 0x4 "FDCAN_TEST,FDCAN test register" rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)" bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX" newline bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value loop back mode is disabled,1: Loop back mode is enabled (see Test modes)" group.long 0x10++0x7 line.long 0x0 "FDCAN_CCU_IR,FDCAN test register" bitfld.long 0x0 1. "CSC,Calibration state changed" "0: Calibration state unchanged,1: Calibration state has changed" bitfld.long 0x0 0. "CWE,Calibration watchdog event" "0: No calibration watchdog event,1: Calibration watchdog event occurred" line.long 0x4 "FDCAN_RWD,FDCAN RAM watchdog register" hexmask.long.byte 0x4 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x4 0.--7. 1. "WDC,Watchdog configuration" group.long 0x14++0x1B line.long 0x0 "FDCAN_CCU_IE,FDCAN RAM watchdog register" bitfld.long 0x0 1. "CSCE,Calibration state changed enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 0. "CWEE,Calibration watchdog event enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x4 "FDCAN_CCCR,FDCAN CC control register" bitfld.long 0x4 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x4 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: Disabled,1: Enabled" newline bitfld.long 0x4 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0x4 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0x4 9. "BRSE,FDCAN bitrate switching" "0: Bitrate switching for transmissions disabled,1: Bitrate switching for transmissions enabled" bitfld.long 0x4 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0x4 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test mode write access to register TEST enabled" bitfld.long 0x4 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0x4 5. "MON,Bus monitoring mode" "0: Bus monitoring mode is disabled,1: Bus monitoring mode is enabled" bitfld.long 0x4 4. "CSR,Clock stop request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline rbitfld.long 0x4 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.." bitfld.long 0x4 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation mode active" newline bitfld.long 0x4 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0x4 0. "INIT,Initialization" "0: Normal operation,1: Initialization is started (while FDCAN_CCCR.INIT.." line.long 0x8 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register" hexmask.long.byte 0x8 25.--31. 1. "NSJW,Nominal (re)synchronization jump width" hexmask.long.word 0x8 16.--24. 1. "NBRP,Bitrate prescaler" newline hexmask.long.byte 0x8 8.--15. 1. "NTSEG1,Nominal time segment before sample point" hexmask.long.byte 0x8 0.--6. 1. "NTSEG2,Nominal time segment after sample point" line.long 0xC "FDCAN_TSCC,FDCAN timestamp counter configuration register" hexmask.long.byte 0xC 16.--19. 1. "TCP,Timestamp counter prescaler" bitfld.long 0xC 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value used..,3: Same as 00." line.long 0x10 "FDCAN_TSCV,FDCAN timestamp counter value register" hexmask.long.word 0x10 0.--15. 1. "TSC,Timestamp counter" line.long 0x14 "FDCAN_TOCC,FDCAN timeout counter configuration register" hexmask.long.word 0x14 16.--31. 1. "TOP,Timeout period" bitfld.long 0x14 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x14 0. "ETOC,Enable timeout counter" "0: Timeout counter disabled,1: Timeout counter enabled" line.long 0x18 "FDCAN_TOCV,FDCAN timeout counter value register" hexmask.long.word 0x18 0.--15. 1. "TOC,Timeout counter" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN error counter register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging" rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter" line.long 0x4 "FDCAN_PSR,FDCAN protocol status register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value" bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not ha ve its..,1: Last received FDCAN message had its ESI flag set" rbitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off,1: The FDCAN is in Bus_Off state" rbitfld.long 0x4 6. "EW,Warning status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state" rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter,2: Receiver: node is operating as receiver,3: Transmitter: node is operating as transmitter" newline rbitfld.long 0x4 0.--2. "LEC,Last error code" "0: No error: No error occurred since LEC has been..,1: Stuff error: More than 5 equal bits in a..,2: Form error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the protocol status.." line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register" hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset" hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,FDCAN interrupt register" bitfld.long 0x0 29. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.." bitfld.long 0x0 26. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow,1: Overflow of CAN error logging counter occurred" newline bitfld.long 0x0 19. "DRX,Message stored to dedicated Rx buffer" "0: No Rx buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM access failure" "0: No message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp wraparound" "0: No timestamp counter wraparound,1: Timestamp counter wraparound" newline bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached" "0: Tx event FIFO fill level below watermark,1: Tx event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High priority message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register" bitfld.long 0x4 29. "ARAE,Access to Reserved address enable" "0,1" bitfld.long 0x4 28. "PEDE,Protocol error in data phase enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol error in Arbitration phase enable" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to dedicated Rx buffer interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register" bitfld.long 0x8 29. "ARAL,Access to reserved address line" "0,1" bitfld.long 0x8 28. "PEDL,Protocol error in data phase line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase line" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog interrupt line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off status" "0,1" bitfld.long 0x8 24. "EWL,Warning status interrupt line" "0,1" newline bitfld.long 0x8 23. "EPL,Error passive interrupt line" "0,1" bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to dedicated Rx buffer interrupt line" "0,1" bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx event FIFO element Lost interrupt line" "0,1" bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line" "0,1" bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line" "0,1" bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission completed interrupt line" "0,1" bitfld.long 0x8 8. "HPML,High priority message interrupt line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line" "0,1" line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register" bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled" bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN global filter configuration register" bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard ID,1: Reject all remote frames with 11-bit standard ID" bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard ID,1: Reject all remote frames with 29-bit standard ID" line.long 0x4 "FDCAN_SIDFC,FDCAN standard ID filter configuration register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address" line.long 0x8 "FDCAN_XIDFC,FDCAN extended ID filter configuration register" hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN extended ID and mask register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "FDCAN_HPMS,FDCAN high priority message status register" bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index" newline bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index" group.long 0x98++0x1B line.long 0x0 "FDCAN_NDAT1,FDCAN new data 1 register" bitfld.long 0x0 31. "ND31,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 30. "ND30,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 28. "ND28,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 26. "ND26,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 24. "ND24,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 22. "ND22,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 20. "ND20,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 18. "ND18,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 16. "ND16,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 14. "ND14,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 12. "ND12,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 10. "ND10,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 8. "ND8,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 6. "ND6,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 4. "ND4,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 2. "ND2,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 0. "ND0,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x4 "FDCAN_NDAT2,FDCAN new data 2 register" bitfld.long 0x4 31. "ND63,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 30. "ND62,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 28. "ND60,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 26. "ND58,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 24. "ND56,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 22. "ND54,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 20. "ND52,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 18. "ND50,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 16. "ND48,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 14. "ND46,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 12. "ND44,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 10. "ND42,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 8. "ND40,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 6. "ND38,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 4. "ND36,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 2. "ND34,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 0. "ND32,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x8 "FDCAN_RXF0C,FDCAN Rx FIFO 0 configuration register" bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,FIFO 0 watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address" line.long 0xC "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register" bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0xC 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index" hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index" newline hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level" line.long 0x10 "FDCAN_RXF0A,FDCAN Rx FIFO 0 acknowledge register" hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index" line.long 0x14 "FDCAN_RXBC,FDCAN Rx buffer configuration register" hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address" line.long 0x18 "FDCAN_RXF1C,FDCAN Rx FIFO 1 configuration register" bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark" newline hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size" hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address" rgroup.long 0xB4++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register" bitfld.long 0x0 30.--31. "DMS,Debug message status" "0: Idle state wait for reception of debug messages,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level" group.long 0xB8++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index" rgroup.long 0xBC++0x3 line.long 0x0 "FDCAN_RXESC,FDCAN Rx buffer element size configuration register" bitfld.long 0x0 8.--10. "RBDS,Rx buffer data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 0 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" newline bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 1 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 30. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation." hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/queue size" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of dedicated transmit buffers" hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx buffers start address" rgroup.long 0xC4++0xB line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register" bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/queue put index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO get index." hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO free level" line.long 0x4 "FDCAN_TXESC,FDCAN Tx buffer element size configuration register" bitfld.long 0x4 0.--2. "TBDS,Tx buffer data Field size:" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" line.long 0x8 "FDCAN_TXBRP,FDCAN Tx buffer request pending register" hexmask.long 0x8 0.--31. 1. "TRP,Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register" hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register" hexmask.long 0x4 0.--31. 1. "CR,Cancellation request" rgroup.long 0xD8++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register" hexmask.long 0x0 0.--31. 1. "TO,Transmission occurred" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register" hexmask.long 0x4 0.--31. 1. "CF,Cancellation finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register" hexmask.long 0x0 0.--31. 1. "TIE,Transmission interrupt enable" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register" hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation finished interrupt enable" group.long 0xF0++0x3 line.long 0x0 "FDCAN_TXEFC,FDCAN Tx event FIFO configuration register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address" rgroup.long 0xF4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register" bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO put index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level" group.long 0xF8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT trigger memory configuration register" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger memory elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger memory start address." line.long 0x4 "FDCAN_TTRMC,FDCAN TT reference message configuration register" bitfld.long 0x4 31. "RMPS,Reference message payload select" "0: Reference message has no additional payload,1: The following elements are taken from Tx buffer 0:" bitfld.long 0x4 30. "XTD,Extended identifier" "0: 11-bit standard identifier,1: 29-bit extended identifier" newline hexmask.long 0x4 0.--28. 1. "RID,Reference identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT operation configuration register" bitfld.long 0x8 26. "EVTP,Event trigger polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x8 25. "ECC,Enable clock calibration." "0: Automatic clock calibration in FDCAN level 0 2..,1: Automatic clock calibration in FDCAN level 0 2.." newline bitfld.long 0x8 24. "EGTF,Enable global time filtering." "0: Global time filtering in FDCAN level 0 2 is..,1: Global time filtering in FDCAN level 0 2 is.." hexmask.long.byte 0x8 16.--23. 1. "AWL,Application watchdog limit." newline bitfld.long 0x8 15. "EECS,Enable external clock synchronization" "0: External clock synchronization in FDCAN level 0..,1: External clock synchronization in FDCAN level 0.." hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial reference trigger offset." newline bitfld.long 0x8 5.--7. "LDSDL,LD of synchronization deviation limit." "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time master." "0: Time master function disabled,1: Potential time master" newline bitfld.long 0x8 3. "GEN,Gap enable." "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.." bitfld.long 0x8 0.--1. "OM,Operation mode." "0: Event-driven CAN communication default,1: TTCAN level 1,2: TTCAN level 2,3: TTCAN level 0" line.long 0xC "FDCAN_TTMLM,FDCAN TT matrix limits register" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected number of Tx triggers" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx enable window" newline bitfld.long 0xC 6.--7. "CSS,Cycle start synchronization" "0: No sync pulse,1: Sync pulse at start of basic cycle,2: Sync pulse at start of matrix cycle,?" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR configuration register" bitfld.long 0x10 31. "ELT,Enable local time." "0: Local time is stopped default,1: Local time is enabled" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator configuration." newline hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator configuration low." line.long 0x14 "FDCAN_TTOCN,FDCAN TT operation control register" rbitfld.long 0x14 15. "LCKC,TT operation control register locked." "0: Write access to FDCAN_TTOCN enabled,1: Write access to FDCAN_TTOCN locked" bitfld.long 0x14 13. "ESCN,External synchronization control" "0: External synchronization disabled,1: External synchronization enabled" newline bitfld.long 0x14 12. "NIG,Next is gap." "0: No action reset by reception of any reference..,1: Transmit next reference message with Next_is_Gap.." bitfld.long 0x14 11. "TMG,Time mark gap." "0: Reset by each reference message,1: Next reference message started when register.." newline bitfld.long 0x14 10. "FGP,Finish gap." "0: No reference message requested,1: Application requested start of reference message" bitfld.long 0x14 9. "GCS,Gap control select" "0: Gap control independent from event trigger,1: Gap control by input event trigger pin" newline bitfld.long 0x14 8. "TTIE,Trigger time mark interrupt pulse enable" "0: Trigger time mark interrupt output fdcan1_tmp..,1: Trigger time mark interrupt output fdcan1_tmp.." bitfld.long 0x14 6.--7. "TMC,Register time mark compare." "0: No Register time mark interrupt generated,1: Register time mark interrupt if time mark =..,2: Register time mark interrupt if time mark =..,3: Register time mark interrupt if time mark =.." newline bitfld.long 0x14 5. "RTIE,Register time mark interrupt pulse enable." "0: Register time mark interrupt output disabled,1: Register time mark interrupt output enabled" bitfld.long 0x14 3.--4. "SWS,Stop watch source." "0: Stop watch disabled,1: Actual value of cycle time is copied to..,2: Actual value of local time is copied to..,3: Actual value of global time is copied to.." newline bitfld.long 0x14 2. "SWP,Stop watch polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x14 1. "ECS,External clock synchronization." "0,1" newline bitfld.long 0x14 0. "SGT,Set global time." "0,1" line.long 0x18 "FDCAN_TTGTP,FDCAN TT global time preset register" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle time target phase" hexmask.long.word 0x18 0.--15. 1. "TP,Time preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT time mark register" rbitfld.long 0x1C 31. "LCKM,TT time mark register locked" "0: Write access to FDCAN_TTTMK enabled,1: Write access to FDCAN_TTTMK locked" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time mark cycle code" newline hexmask.long.word 0x1C 0.--15. 1. "TM,Time mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT interrupt register" bitfld.long 0x20 18. "CER,Configuration error" "0: No error found in trigger list,1: Error found in trigger list" bitfld.long 0x20 17. "AW,Application watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time" newline bitfld.long 0x20 16. "WT,Watch trigger" "0: No missing reference message,1: Missing reference message (level 0: cycle time.." bitfld.long 0x20 15. "IWTG,Initialization watch trigger" "0,1" newline bitfld.long 0x20 14. "ELC,Error level changed" "0: No change in error level,1: Error level changed" bitfld.long 0x20 13. "SE2,Scheduling error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred" newline bitfld.long 0x20 12. "SE1,Scheduling error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred" bitfld.long 0x20 11. "TXO,Tx count overflow" "0: Number of Tx trigger as expected,1: More Tx trigger than expected in one cycle" newline bitfld.long 0x20 10. "TXU,Tx count underflow" "0: Number of Tx trigger as expected,1: Less Tx trigger than expected in one cycle" bitfld.long 0x20 9. "GTE,Global time error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit" newline bitfld.long 0x20 8. "GTD,Global time discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time" bitfld.long 0x20 7. "GTW,Global time wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred" newline bitfld.long 0x20 6. "SWE,Stop watch event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.." bitfld.long 0x20 5. "TTMI,Trigger time mark event internal" "0: Time mark not reached,1: Time mark reached (level 0: cycle time.." newline bitfld.long 0x20 4. "RTMI,Register time mark interrupt" "0: Time mark not reached,1: Time mark reached" bitfld.long 0x20 3. "SOG,Start of gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of synchronization mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.." bitfld.long 0x20 1. "SMC,Start of matrix cycle" "0: No matrix cycle started since bit has been reset,1: Matrix cycle started" newline bitfld.long 0x20 0. "SBC,Start of basic cycle" "0: No basic cycle started since bit has been reset,1: Basic cycle started" line.long 0x24 "FDCAN_TTIE,FDCAN TT interrupt enable register" bitfld.long 0x24 18. "CERE,Configuration error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 17. "AWE,Application watchdog interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 16. "WTE,Watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 15. "IWTE,Initialization watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 14. "ELCE,Change error level interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 13. "SE2E,Scheduling error 2 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 12. "SE1E,Scheduling error 1 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 11. "TXOE,Tx count overflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 10. "TXUE,Tx count underflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 9. "GTEE,Global time error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 8. "GTDE,Global time discontinuity interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 7. "GTWE,Global time wrap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 6. "SWEE,Stop watch event interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 5. "TTMIE,Trigger time mark event internal interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 4. "RTMIE,Register time mark interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 3. "SOGE,Start of gap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 2. "CSME,Change of synchronization mode interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 1. "SMCE,Start of matrix cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 0. "SBCE,Start of basic cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" line.long 0x28 "FDCAN_TTILS,FDCAN TT interrupt line select register" bitfld.long 0x28 18. "CERL,Configuration error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 17. "AWL,Application watchdog interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 16. "WTL,Watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 15. "IWTL,Initialization watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 14. "ELCL,Change error level interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 13. "SE2L,Scheduling error 2 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 12. "SE1L,Scheduling error 1 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 11. "TXOL,Tx count overflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 10. "TXUL,Tx count underflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 9. "GTEL,Global time error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 8. "GTDL,Global time discontinuity interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 7. "GTWL,Global time wrap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 6. "SWEL,Stop watch event interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 5. "TTMIL,Trigger time mark event internal interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 4. "RTMIL,Register time mark interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 3. "SOGL,Start of gap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 2. "CSML,Change of synchronization mode interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 1. "SMCL,Start of matrix cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 0. "SBCL,Start of basic cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT operation status register" bitfld.long 0x0 31. "SPL,Schedule phase lock" "0: Phase outside range,1: Phase inside range" bitfld.long 0x0 30. "WECS,Wait for external clock synchronization." "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.." newline bitfld.long 0x0 29. "AWE,Application watchdog event" "0: Application watchdog served in time,1: Failed to serve application watchdog in time" bitfld.long 0x0 28. "WFE,Wait for event" "0: No gap announced reset by a reference message..,1: Reference message with Next_is_Gap = 1 received" newline bitfld.long 0x0 27. "GSI,Gap started indicator" "0: No gap in schedule reset by each reference..,1: Gap time after basic cycle has started" bitfld.long 0x0 24.--26. "TMP,Time master priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GFI,Gap finished indicator" "0: Reset at the end of each reference message,1: Gap finished by FDCAN" bitfld.long 0x0 22. "WGTD,Wait for global time discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.." newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference trigger offset" bitfld.long 0x0 7. "QCS,Quality of clock speed" "0: Local clock speed not synchronized to time..,1: Synchronization deviation less than or equal SDL" newline bitfld.long 0x0 6. "QGTP,Quality of global time phase" "0: Global time not valid,1: Global time in phase with time master" bitfld.long 0x0 4.--5. "SYS,Synchronization state" "0: Out of Synchronization,1: Synchronizing to FDCAN communication,2: Schedule suspended by gap (In_Gap),3: Synchronized to schedule (In_Schedule)" newline bitfld.long 0x0 2.--3. "MS,Master state" "0: Master_Off no master properties relevant,1: Operating as time Slave,2: Operating as backup time master,3: Operating as current time master" bitfld.long 0x0 0.--1. "EL,Error level" "0: Severity 0 - No error,1: Severity 1 - Warning,2: Severity 2 - error,3: Severity 3 - Severe error" line.long 0x4 "FDCAN_TURNA,FDCAN TUR numerator actual register" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator actual value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT local and global time register" hexmask.long.word 0x8 16.--31. 1. "GT,Global time" hexmask.long.word 0x8 0.--15. 1. "LT,Local time" line.long 0xC "FDCAN_TTCTC,FDCAN TT cycle time and count register" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT capture time register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop watch value" hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle count value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT cycle sync mark register" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle sync mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT trigger select register" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input selection" "0: fdcan1_evt0,1: fdcan1_evt1,2: fdcan1_evt2,3: fdcan1_evt3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input selection" "0: fdcan1_swt0,1: fdcan1_swt1,2: fdcan1_swt2,3: fdcan1_swt3" tree.end tree "FDCAN3_S" base ad:0x5000E800 rgroup.long 0x0++0x3 line.long 0x0 "FDCAN_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 3" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 2" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year = 4" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day =18" rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CCU_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 1" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 1" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year =" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day = 18" line.long 0x4 "FDCAN_ENDN,FDCAN Endian register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test value" group.long 0x4++0x3 line.long 0x0 "FDCAN_CCU_CCFG,FDCAN Endian register" bitfld.long 0x0 31. "SWR,Software reset" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CDIV,Clock divider" newline hexmask.long.byte 0x0 8.--15. 1. "OCPM,Oscillator clock periods minimum" bitfld.long 0x0 7. "CFL,Calibration field length" "0: Calibration field length is 32 bits,1: Calibration field length is 64 bits" newline bitfld.long 0x0 6. "BCC,Bypass clock calibration" "0: Clock calibration unit generates time quanta clock,1: Clock calibration unit bypassed (default.." hexmask.long.byte 0x0 0.--4. 1. "TQBT,Time quanta per bit time" rgroup.long 0x8++0x3 line.long 0x0 "FDCAN_CCU_CSTAT,Calibration status register" bitfld.long 0x0 30.--31. "CALS,Calibration state" "0: Not_Calibrated,1: Basic_Calibrated,2: Precision_Calibrated,?" hexmask.long.word 0x0 18.--28. 1. "TQC,Time quanta counter" newline hexmask.long.tbyte 0x0 0.--17. 1. "OCPC,Oscillator clock period counter" group.long 0xC++0x3 line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register" bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bitrate prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width" group.long 0xC++0x7 line.long 0x0 "FDCAN_CCU_CWD,FDCAN data bit timing and prescaler register" hexmask.long.word 0x0 16.--31. 1. "WDV,Watchdog value" hexmask.long.word 0x0 0.--15. 1. "WDC,WDC" line.long 0x4 "FDCAN_TEST,FDCAN test register" rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)" bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX" newline bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value loop back mode is disabled,1: Loop back mode is enabled (see Test modes)" group.long 0x10++0x7 line.long 0x0 "FDCAN_CCU_IR,FDCAN test register" bitfld.long 0x0 1. "CSC,Calibration state changed" "0: Calibration state unchanged,1: Calibration state has changed" bitfld.long 0x0 0. "CWE,Calibration watchdog event" "0: No calibration watchdog event,1: Calibration watchdog event occurred" line.long 0x4 "FDCAN_RWD,FDCAN RAM watchdog register" hexmask.long.byte 0x4 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x4 0.--7. 1. "WDC,Watchdog configuration" group.long 0x14++0x1B line.long 0x0 "FDCAN_CCU_IE,FDCAN RAM watchdog register" bitfld.long 0x0 1. "CSCE,Calibration state changed enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 0. "CWEE,Calibration watchdog event enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x4 "FDCAN_CCCR,FDCAN CC control register" bitfld.long 0x4 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x4 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: Disabled,1: Enabled" newline bitfld.long 0x4 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." bitfld.long 0x4 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled" newline bitfld.long 0x4 9. "BRSE,FDCAN bitrate switching" "0: Bitrate switching for transmissions disabled,1: Bitrate switching for transmissions enabled" bitfld.long 0x4 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0x4 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test mode write access to register TEST enabled" bitfld.long 0x4 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0x4 5. "MON,Bus monitoring mode" "0: Bus monitoring mode is disabled,1: Bus monitoring mode is enabled" bitfld.long 0x4 4. "CSR,Clock stop request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.." newline rbitfld.long 0x4 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.." bitfld.long 0x4 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation mode active" newline bitfld.long 0x4 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.." bitfld.long 0x4 0. "INIT,Initialization" "0: Normal operation,1: Initialization is started (while FDCAN_CCCR.INIT.." line.long 0x8 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register" hexmask.long.byte 0x8 25.--31. 1. "NSJW,Nominal (re)synchronization jump width" hexmask.long.word 0x8 16.--24. 1. "NBRP,Bitrate prescaler" newline hexmask.long.byte 0x8 8.--15. 1. "NTSEG1,Nominal time segment before sample point" hexmask.long.byte 0x8 0.--6. 1. "NTSEG2,Nominal time segment after sample point" line.long 0xC "FDCAN_TSCC,FDCAN timestamp counter configuration register" hexmask.long.byte 0xC 16.--19. 1. "TCP,Timestamp counter prescaler" bitfld.long 0xC 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value used..,3: Same as 00." line.long 0x10 "FDCAN_TSCV,FDCAN timestamp counter value register" hexmask.long.word 0x10 0.--15. 1. "TSC,Timestamp counter" line.long 0x14 "FDCAN_TOCC,FDCAN timeout counter configuration register" hexmask.long.word 0x14 16.--31. 1. "TOP,Timeout period" bitfld.long 0x14 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1" newline bitfld.long 0x14 0. "ETOC,Enable timeout counter" "0: Timeout counter disabled,1: Timeout counter enabled" line.long 0x18 "FDCAN_TOCV,FDCAN timeout counter value register" hexmask.long.word 0x18 0.--15. 1. "TOC,Timeout counter" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN error counter register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging" rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter" line.long 0x4 "FDCAN_PSR,FDCAN protocol status register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value" bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.." bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not ha ve its..,1: Last received FDCAN message had its ESI flag set" rbitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off,1: The FDCAN is in Bus_Off state" rbitfld.long 0x4 6. "EW,Warning status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state" rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter,2: Receiver: node is operating as receiver,3: Transmitter: node is operating as transmitter" newline rbitfld.long 0x4 0.--2. "LEC,Last error code" "0: No error: No error occurred since LEC has been..,1: Stuff error: More than 5 equal bits in a..,2: Form error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the protocol status.." line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register" hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset" hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,FDCAN interrupt register" bitfld.long 0x0 29. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x0 28. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.." newline bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.." bitfld.long 0x0 26. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY" newline bitfld.long 0x0 25. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x0 24. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x0 23. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x0 22. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow,1: Overflow of CAN error logging counter occurred" newline bitfld.long 0x0 19. "DRX,Message stored to dedicated Rx buffer" "0: No Rx buffer updated,1: At least one received message stored into a Rx.." bitfld.long 0x0 18. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x0 17. "MRAF,Message RAM access failure" "0: No message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x0 16. "TSW,Timestamp wraparound" "0: No timestamp counter wraparound,1: Timestamp counter wraparound" newline bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost also set after write.." bitfld.long 0x0 14. "TEFF,Tx event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached" "0: Tx event FIFO fill level below watermark,1: Tx event FIFO fill level reached watermark" bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element" newline bitfld.long 0x0 11. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x0 10. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x0 9. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x0 8. "HPM,High priority message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register" bitfld.long 0x4 29. "ARAE,Access to Reserved address enable" "0,1" bitfld.long 0x4 28. "PEDE,Protocol error in data phase enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol error in Arbitration phase enable" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "DRXE,Message stored to dedicated Rx buffer interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "HPME,High priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register" bitfld.long 0x8 29. "ARAL,Access to reserved address line" "0,1" bitfld.long 0x8 28. "PEDL,Protocol error in data phase line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase line" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog interrupt line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off status" "0,1" bitfld.long 0x8 24. "EWL,Warning status interrupt line" "0,1" newline bitfld.long 0x8 23. "EPL,Error passive interrupt line" "0,1" bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to dedicated Rx buffer interrupt line" "0,1" bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx event FIFO element Lost interrupt line" "0,1" bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line" "0,1" bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line" "0,1" bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission completed interrupt line" "0,1" bitfld.long 0x8 8. "HPML,High priority message interrupt line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line" "0,1" line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register" bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled" bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN global filter configuration register" bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject" newline bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard ID,1: Reject all remote frames with 11-bit standard ID" bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard ID,1: Reject all remote frames with 29-bit standard ID" line.long 0x4 "FDCAN_SIDFC,FDCAN standard ID filter configuration register" hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address" line.long 0x8 "FDCAN_XIDFC,FDCAN extended ID filter configuration register" hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN extended ID and mask register" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "FDCAN_HPMS,FDCAN high priority message status register" bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index" newline bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index" group.long 0x98++0x1B line.long 0x0 "FDCAN_NDAT1,FDCAN new data 1 register" bitfld.long 0x0 31. "ND31,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 30. "ND30,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 29. "ND29,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 28. "ND28,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 27. "ND27,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 26. "ND26,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 25. "ND25,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 24. "ND24,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 23. "ND23,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 22. "ND22,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 21. "ND21,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 20. "ND20,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 19. "ND19,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 18. "ND18,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 17. "ND17,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 16. "ND16,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 15. "ND15,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 14. "ND14,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 13. "ND13,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 12. "ND12,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 11. "ND11,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 10. "ND10,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 9. "ND9,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 8. "ND8,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 7. "ND7,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 6. "ND6,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 5. "ND5,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 4. "ND4,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 3. "ND3,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 2. "ND2,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x0 1. "ND1,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x0 0. "ND0,New data[31:0]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x4 "FDCAN_NDAT2,FDCAN new data 2 register" bitfld.long 0x4 31. "ND63,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 30. "ND62,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 29. "ND61,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 28. "ND60,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 27. "ND59,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 26. "ND58,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 25. "ND57,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 24. "ND56,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 23. "ND55,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 22. "ND54,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 21. "ND53,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 20. "ND52,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 19. "ND51,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 18. "ND50,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 17. "ND49,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 16. "ND48,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 15. "ND47,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 14. "ND46,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 13. "ND45,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 12. "ND44,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 11. "ND43,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 10. "ND42,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 9. "ND41,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 8. "ND40,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 7. "ND39,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 6. "ND38,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 5. "ND37,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 4. "ND36,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 3. "ND35,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 2. "ND34,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" newline bitfld.long 0x4 1. "ND33,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" bitfld.long 0x4 0. "ND32,New data[63:32]" "0: Rx buffer not updated,1: Rx buffer updated from new message" line.long 0x8 "FDCAN_RXF0C,FDCAN Rx FIFO 0 configuration register" bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x8 24.--30. 1. "F0WM,FIFO 0 watermark" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address" line.long 0xC "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register" bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0xC 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index" hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index" newline hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level" line.long 0x10 "FDCAN_RXF0A,FDCAN Rx FIFO 0 acknowledge register" hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index" line.long 0x14 "FDCAN_RXBC,FDCAN Rx buffer configuration register" hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address" line.long 0x18 "FDCAN_RXF1C,FDCAN Rx FIFO 1 configuration register" bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark" newline hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size" hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address" rgroup.long 0xB4++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register" bitfld.long 0x0 30.--31. "DMS,Debug message status" "0: Idle state wait for reception of debug messages,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level" group.long 0xB8++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index" rgroup.long 0xBC++0x3 line.long 0x0 "FDCAN_RXESC,FDCAN Rx buffer element size configuration register" bitfld.long 0x0 8.--10. "RBDS,Rx buffer data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 0 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" newline bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 1 data field size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 30. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation." hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/queue size" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of dedicated transmit buffers" hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx buffers start address" rgroup.long 0xC4++0xB line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register" bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/queue put index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO get index." hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO free level" line.long 0x4 "FDCAN_TXESC,FDCAN Tx buffer element size configuration register" bitfld.long 0x4 0.--2. "TBDS,Tx buffer data Field size:" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field" line.long 0x8 "FDCAN_TXBRP,FDCAN Tx buffer request pending register" hexmask.long 0x8 0.--31. 1. "TRP,Transmission request pending" group.long 0xD0++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register" hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register" hexmask.long 0x4 0.--31. 1. "CR,Cancellation request" rgroup.long 0xD8++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register" hexmask.long 0x0 0.--31. 1. "TO,Transmission occurred" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register" hexmask.long 0x4 0.--31. 1. "CF,Cancellation finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register" hexmask.long 0x0 0.--31. 1. "TIE,Transmission interrupt enable" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register" hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation finished interrupt enable" group.long 0xF0++0x3 line.long 0x0 "FDCAN_TXEFC,FDCAN Tx event FIFO configuration register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address" rgroup.long 0xF4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register" bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO put index" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level" group.long 0xF8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT trigger memory configuration register" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger memory elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger memory start address." line.long 0x4 "FDCAN_TTRMC,FDCAN TT reference message configuration register" bitfld.long 0x4 31. "RMPS,Reference message payload select" "0: Reference message has no additional payload,1: The following elements are taken from Tx buffer 0:" bitfld.long 0x4 30. "XTD,Extended identifier" "0: 11-bit standard identifier,1: 29-bit extended identifier" newline hexmask.long 0x4 0.--28. 1. "RID,Reference identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT operation configuration register" bitfld.long 0x8 26. "EVTP,Event trigger polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x8 25. "ECC,Enable clock calibration." "0: Automatic clock calibration in FDCAN level 0 2..,1: Automatic clock calibration in FDCAN level 0 2.." newline bitfld.long 0x8 24. "EGTF,Enable global time filtering." "0: Global time filtering in FDCAN level 0 2 is..,1: Global time filtering in FDCAN level 0 2 is.." hexmask.long.byte 0x8 16.--23. 1. "AWL,Application watchdog limit." newline bitfld.long 0x8 15. "EECS,Enable external clock synchronization" "0: External clock synchronization in FDCAN level 0..,1: External clock synchronization in FDCAN level 0.." hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial reference trigger offset." newline bitfld.long 0x8 5.--7. "LDSDL,LD of synchronization deviation limit." "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time master." "0: Time master function disabled,1: Potential time master" newline bitfld.long 0x8 3. "GEN,Gap enable." "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.." bitfld.long 0x8 0.--1. "OM,Operation mode." "0: Event-driven CAN communication default,1: TTCAN level 1,2: TTCAN level 2,3: TTCAN level 0" line.long 0xC "FDCAN_TTMLM,FDCAN TT matrix limits register" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected number of Tx triggers" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx enable window" newline bitfld.long 0xC 6.--7. "CSS,Cycle start synchronization" "0: No sync pulse,1: Sync pulse at start of basic cycle,2: Sync pulse at start of matrix cycle,?" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR configuration register" bitfld.long 0x10 31. "ELT,Enable local time." "0: Local time is stopped default,1: Local time is enabled" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator configuration." newline hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator configuration low." line.long 0x14 "FDCAN_TTOCN,FDCAN TT operation control register" rbitfld.long 0x14 15. "LCKC,TT operation control register locked." "0: Write access to FDCAN_TTOCN enabled,1: Write access to FDCAN_TTOCN locked" bitfld.long 0x14 13. "ESCN,External synchronization control" "0: External synchronization disabled,1: External synchronization enabled" newline bitfld.long 0x14 12. "NIG,Next is gap." "0: No action reset by reception of any reference..,1: Transmit next reference message with Next_is_Gap.." bitfld.long 0x14 11. "TMG,Time mark gap." "0: Reset by each reference message,1: Next reference message started when register.." newline bitfld.long 0x14 10. "FGP,Finish gap." "0: No reference message requested,1: Application requested start of reference message" bitfld.long 0x14 9. "GCS,Gap control select" "0: Gap control independent from event trigger,1: Gap control by input event trigger pin" newline bitfld.long 0x14 8. "TTIE,Trigger time mark interrupt pulse enable" "0: Trigger time mark interrupt output fdcan1_tmp..,1: Trigger time mark interrupt output fdcan1_tmp.." bitfld.long 0x14 6.--7. "TMC,Register time mark compare." "0: No Register time mark interrupt generated,1: Register time mark interrupt if time mark =..,2: Register time mark interrupt if time mark =..,3: Register time mark interrupt if time mark =.." newline bitfld.long 0x14 5. "RTIE,Register time mark interrupt pulse enable." "0: Register time mark interrupt output disabled,1: Register time mark interrupt output enabled" bitfld.long 0x14 3.--4. "SWS,Stop watch source." "0: Stop watch disabled,1: Actual value of cycle time is copied to..,2: Actual value of local time is copied to..,3: Actual value of global time is copied to.." newline bitfld.long 0x14 2. "SWP,Stop watch polarity." "0: Rising edge trigger,1: Falling edge trigger" bitfld.long 0x14 1. "ECS,External clock synchronization." "0,1" newline bitfld.long 0x14 0. "SGT,Set global time." "0,1" line.long 0x18 "FDCAN_TTGTP,FDCAN TT global time preset register" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle time target phase" hexmask.long.word 0x18 0.--15. 1. "TP,Time preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT time mark register" rbitfld.long 0x1C 31. "LCKM,TT time mark register locked" "0: Write access to FDCAN_TTTMK enabled,1: Write access to FDCAN_TTTMK locked" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time mark cycle code" newline hexmask.long.word 0x1C 0.--15. 1. "TM,Time mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT interrupt register" bitfld.long 0x20 18. "CER,Configuration error" "0: No error found in trigger list,1: Error found in trigger list" bitfld.long 0x20 17. "AW,Application watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time" newline bitfld.long 0x20 16. "WT,Watch trigger" "0: No missing reference message,1: Missing reference message (level 0: cycle time.." bitfld.long 0x20 15. "IWTG,Initialization watch trigger" "0,1" newline bitfld.long 0x20 14. "ELC,Error level changed" "0: No change in error level,1: Error level changed" bitfld.long 0x20 13. "SE2,Scheduling error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred" newline bitfld.long 0x20 12. "SE1,Scheduling error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred" bitfld.long 0x20 11. "TXO,Tx count overflow" "0: Number of Tx trigger as expected,1: More Tx trigger than expected in one cycle" newline bitfld.long 0x20 10. "TXU,Tx count underflow" "0: Number of Tx trigger as expected,1: Less Tx trigger than expected in one cycle" bitfld.long 0x20 9. "GTE,Global time error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit" newline bitfld.long 0x20 8. "GTD,Global time discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time" bitfld.long 0x20 7. "GTW,Global time wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred" newline bitfld.long 0x20 6. "SWE,Stop watch event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.." bitfld.long 0x20 5. "TTMI,Trigger time mark event internal" "0: Time mark not reached,1: Time mark reached (level 0: cycle time.." newline bitfld.long 0x20 4. "RTMI,Register time mark interrupt" "0: Time mark not reached,1: Time mark reached" bitfld.long 0x20 3. "SOG,Start of gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of synchronization mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.." bitfld.long 0x20 1. "SMC,Start of matrix cycle" "0: No matrix cycle started since bit has been reset,1: Matrix cycle started" newline bitfld.long 0x20 0. "SBC,Start of basic cycle" "0: No basic cycle started since bit has been reset,1: Basic cycle started" line.long 0x24 "FDCAN_TTIE,FDCAN TT interrupt enable register" bitfld.long 0x24 18. "CERE,Configuration error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 17. "AWE,Application watchdog interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 16. "WTE,Watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 15. "IWTE,Initialization watch trigger interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 14. "ELCE,Change error level interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 13. "SE2E,Scheduling error 2 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 12. "SE1E,Scheduling error 1 interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 11. "TXOE,Tx count overflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 10. "TXUE,Tx count underflow interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 9. "GTEE,Global time error interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 8. "GTDE,Global time discontinuity interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 7. "GTWE,Global time wrap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 6. "SWEE,Stop watch event interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 5. "TTMIE,Trigger time mark event internal interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 4. "RTMIE,Register time mark interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 3. "SOGE,Start of gap interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 2. "CSME,Change of synchronization mode interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" bitfld.long 0x24 1. "SMCE,Start of matrix cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" newline bitfld.long 0x24 0. "SBCE,Start of basic cycle interrupt enable" "0: TT interrupt disabled,1: TT interrupt enabled" line.long 0x28 "FDCAN_TTILS,FDCAN TT interrupt line select register" bitfld.long 0x28 18. "CERL,Configuration error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 17. "AWL,Application watchdog interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 16. "WTL,Watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 15. "IWTL,Initialization watch trigger interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 14. "ELCL,Change error level interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 13. "SE2L,Scheduling error 2 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 12. "SE1L,Scheduling error 1 interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 11. "TXOL,Tx count overflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 10. "TXUL,Tx count underflow interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 9. "GTEL,Global time error interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 8. "GTDL,Global time discontinuity interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 7. "GTWL,Global time wrap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 6. "SWEL,Stop watch event interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 5. "TTMIL,Trigger time mark event internal interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 4. "RTMIL,Register time mark interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 3. "SOGL,Start of gap interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 2. "CSML,Change of synchronization mode interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" bitfld.long 0x28 1. "SMCL,Start of matrix cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" newline bitfld.long 0x28 0. "SBCL,Start of basic cycle interrupt line" "0: TT interrupt assigned to interrupt line 0,1: TT interrupt assigned to interrupt line 1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT operation status register" bitfld.long 0x0 31. "SPL,Schedule phase lock" "0: Phase outside range,1: Phase inside range" bitfld.long 0x0 30. "WECS,Wait for external clock synchronization." "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.." newline bitfld.long 0x0 29. "AWE,Application watchdog event" "0: Application watchdog served in time,1: Failed to serve application watchdog in time" bitfld.long 0x0 28. "WFE,Wait for event" "0: No gap announced reset by a reference message..,1: Reference message with Next_is_Gap = 1 received" newline bitfld.long 0x0 27. "GSI,Gap started indicator" "0: No gap in schedule reset by each reference..,1: Gap time after basic cycle has started" bitfld.long 0x0 24.--26. "TMP,Time master priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GFI,Gap finished indicator" "0: Reset at the end of each reference message,1: Gap finished by FDCAN" bitfld.long 0x0 22. "WGTD,Wait for global time discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.." newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference trigger offset" bitfld.long 0x0 7. "QCS,Quality of clock speed" "0: Local clock speed not synchronized to time..,1: Synchronization deviation less than or equal SDL" newline bitfld.long 0x0 6. "QGTP,Quality of global time phase" "0: Global time not valid,1: Global time in phase with time master" bitfld.long 0x0 4.--5. "SYS,Synchronization state" "0: Out of Synchronization,1: Synchronizing to FDCAN communication,2: Schedule suspended by gap (In_Gap),3: Synchronized to schedule (In_Schedule)" newline bitfld.long 0x0 2.--3. "MS,Master state" "0: Master_Off no master properties relevant,1: Operating as time Slave,2: Operating as backup time master,3: Operating as current time master" bitfld.long 0x0 0.--1. "EL,Error level" "0: Severity 0 - No error,1: Severity 1 - Warning,2: Severity 2 - error,3: Severity 3 - Severe error" line.long 0x4 "FDCAN_TURNA,FDCAN TUR numerator actual register" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator actual value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT local and global time register" hexmask.long.word 0x8 16.--31. 1. "GT,Global time" hexmask.long.word 0x8 0.--15. 1. "LT,Local time" line.long 0xC "FDCAN_TTCTC,FDCAN TT cycle time and count register" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT capture time register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop watch value" hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle count value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT cycle sync mark register" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle sync mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT trigger select register" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input selection" "0: fdcan1_evt0,1: fdcan1_evt1,2: fdcan1_evt2,3: fdcan1_evt3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input selection" "0: fdcan1_swt0,1: fdcan1_swt1,2: fdcan1_swt2,3: fdcan1_swt3" tree.end tree.end tree "FMC (Flexible Memory Controller)" base ad:0x0 sif (cpuis("STM32N645*")||cpuis("STM32N647*")||cpuis("STM32N655*")) tree "FMC1" base ad:0x48024000 group.long 0x0++0x23 line.long 0x0 "FMC_BCR1,SRAM/NOR Flash chip-select control register for memory region 1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." bitfld.long 0x0 20.--21. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle,2: NEx deasserted after 64 fmc_ker_ck clock cycles,3: NEx deasserted after 256 fmc_ker_ck clock cycles" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." bitfld.long 0x0 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." bitfld.long 0x0 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." bitfld.long 0x0 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." bitfld.long 0x0 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x4 "FMC_BTR1,SRAM/NOR Flash chip-select timing registers for memory region 1" bitfld.long 0x4 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x4 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x8 "FMC_BCR2,SRAM/NOR Flash chip-select control register for memory region 2" bitfld.long 0x8 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." sif (cpuis("STM32N655*")) bitfld.long 0x8 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x8 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) bitfld.long 0x8 20.--21. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle,2: NEx deasserted after 64 fmc_ker_ck clock cycles,3: NEx deasserted after 256 fmc_ker_ck clock cycles" newline endif bitfld.long 0x8 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." bitfld.long 0x8 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." bitfld.long 0x8 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." bitfld.long 0x8 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." bitfld.long 0x8 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" bitfld.long 0x8 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." bitfld.long 0x8 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0xC "FMC_BTR2,SRAM/NOR Flash chip-select timing registers for memory region 2" bitfld.long 0xC 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0xC 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x10 "FMC_BCR3,SRAM/NOR Flash chip-select control register for memory region 3" bitfld.long 0x10 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." sif (cpuis("STM32N655*")) bitfld.long 0x10 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x10 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) bitfld.long 0x10 20.--21. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle,2: NEx deasserted after 64 fmc_ker_ck clock cycles,3: NEx deasserted after 256 fmc_ker_ck clock cycles" newline endif bitfld.long 0x10 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." bitfld.long 0x10 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." bitfld.long 0x10 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." bitfld.long 0x10 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." bitfld.long 0x10 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" bitfld.long 0x10 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." bitfld.long 0x10 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x14 "FMC_BTR3,SRAM/NOR Flash chip-select timing registers for memory region 3" bitfld.long 0x14 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x14 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x18 "FMC_BCR4,SRAM/NOR Flash chip-select control register for memory region 4" bitfld.long 0x18 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." sif (cpuis("STM32N655*")) bitfld.long 0x18 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x18 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) bitfld.long 0x18 20.--21. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle,2: NEx deasserted after 64 fmc_ker_ck clock cycles,3: NEx deasserted after 256 fmc_ker_ck clock cycles" newline endif bitfld.long 0x18 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." bitfld.long 0x18 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." bitfld.long 0x18 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." bitfld.long 0x18 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." bitfld.long 0x18 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" bitfld.long 0x18 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." bitfld.long 0x18 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x1C "FMC_BTR4,SRAM/NOR Flash chip-select timing registers for memory region 4" bitfld.long 0x1C 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x1C 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x20 "FMC_CFGR,FMC common configuration register" bitfld.long 0x20 31. "FMCEN,FMC controller enable" "0: FMC controller disabled,1: FMC controller enabled" bitfld.long 0x20 25. "BMAP1,FMC memory region mapping" "0: Default mapping (refer to Table 132),1: Devices are remapped (refer to Table 133)" newline bitfld.long 0x20 24. "BMAP0,FMC memory region mapping" "0: Default mapping (refer to Table 132),1: Devices are remapped (refer to Table 133)" bitfld.long 0x20 20. "CCLKEN,Continuous clock enable" "0: The FMC_CLK is only generated during the..,1: The FMC_CLK is generated continuously during.." newline hexmask.long.byte 0x20 16.--19. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" group.long 0x80++0x3 line.long 0x0 "FMC_PCR,NAND Flash programmable control register" bitfld.long 0x0 25. "WEN,Write enable" "0: Read access enabled,1: Write access enabled" bitfld.long 0x0 24. "BCHECC,BCH error correction capability" "0: 4-bit BCH (4-bit error correction and 8-bit..,1: 8-bit BCH (8-bit error correction and 16-bit.." newline bitfld.long 0x0 17.--19. "ECCSS,ECC sector size (used to access spare area)" "0: 256 bytes,1: 512 bytes,2: 1024 bytes,3: 2048 bytes (default),4: 4096 bytes,?,?,?" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay." newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay." bitfld.long 0x0 8. "ECCALG,ECC algorithm" "0: Hamming code is selected (default).,1: BCH code is selected." newline bitfld.long 0x0 6. "ECCEN,ECC computation logic enable bit" "0: ECC logic is disabled and reset (default after..,1: ECC logic is enabled." bitfld.long 0x0 4.--5. "PWID,Data bus width" "0: 8 bits (default after reset).,1: 16 bits,?,?" newline bitfld.long 0x0 2. "PBKEN,NAND Flash memory region enable bit" "0: Corresponding memory region is disabled (default..,1: Corresponding memory region is enabled." bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit" "0: disabled (default),1: enabled" rgroup.long 0x84++0x3 line.long 0x0 "FMC_SR,FMC status register" bitfld.long 0x0 6. "NWRF,NAND write request flag" "0: NAND Flash write requests are pending,1: No NAND Flash write requests pending" bitfld.long 0x0 4. "PEF,Pipe Empty Flag" "0,1" newline bitfld.long 0x0 0.--1. "ISOST,FMC isolation state with respect to the AXI interface" "0: FMC is not isolated; AXI transactions are..,1: FMC has been enabled (FMCEN = 1) and waits for..,2: FMC has been disabled (FMCEN = 0) and waits for..,3: FMC is isolated from its AXI interface. All AXI.." group.long 0x88++0x7 line.long 0x0 "FMC_PMEM,FMC common memory space timing register" hexmask.long.byte 0x0 24.--31. 1. "MEMHIZ,Common memory data bus Hi-Z time" hexmask.long.byte 0x0 16.--23. 1. "MEMHOLD,Common memory hold time" newline hexmask.long.byte 0x0 8.--15. 1. "MEMWAIT,Common memory wait time" hexmask.long.byte 0x0 0.--7. 1. "MEMSET,Common memory setup time" line.long 0x4 "FMC_PATT,FMC attribute memory space timing registers" hexmask.long.byte 0x4 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0x4 16.--23. 1. "ATTHOLD,Attribute memory hold time" newline hexmask.long.byte 0x4 8.--15. 1. "ATTWAIT,Attribute memory wait time" hexmask.long.byte 0x4 0.--7. 1. "ATTSET,Attribute memory setup time" rgroup.long 0x90++0x7 line.long 0x0 "FMC_HPR,FMC Hamming parity result registers" hexmask.long 0x0 0.--31. 1. "HPR,Hamming parity result" line.long 0x4 "FMC_HECCR,FMC Hamming code ECC result register" hexmask.long 0x4 0.--31. 1. "HECC,ECC result" group.long 0x104++0x3 line.long 0x0 "FMC_BWTR1,SRAM/NOR-Flash write timing registers for memory region 1" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x10C++0x3 line.long 0x0 "FMC_BWTR2,SRAM/NOR-Flash write timing registers for memory region 2" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x114++0x3 line.long 0x0 "FMC_BWTR3,SRAM/NOR-Flash write timing registers for memory region 3" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x11C++0x3 line.long 0x0 "FMC_BWTR4,SRAM/NOR-Flash write timing registers for memory region 4" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x140++0xB line.long 0x0 "FMC_SDCR1,SDRAM control registers for SDRAM device 1" bitfld.long 0x0 17. "SDINIT,SDRAM device initialization" "0: Initialization is not complete the AXI accesses..,1: Initialization is complete and the device is.." bitfld.long 0x0 16. "SDEN,SDRAM device enable" "0: SDRAM disabled,1: SDRAM device enabled" newline bitfld.long 0x0 13.--14. "RPIPE,Read pipe" "0: No fmc_ker_ck clock cycle delay (default value),1: One fmc_ker_ck clock cycle delay,2: Two fmc_ker_ck clock cycle delay,?" bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration" "0: SDCLK clock disabled,1: SDCLK period = 1 * fmc_ker_ck period,2: SDCLK period = 2 * fmc_ker_ck periods,3: SDCLK period = 3 * fmc_ker_ck periods" newline bitfld.long 0x0 9. "WP,Write protection" "0: Write accesses allowed,1: Write accesses ignored" bitfld.long 0x0 7.--8. "CAS,CAS Latency" "?,1: 1 cycle,2: 2 cycles,3: 3 cycles" newline bitfld.long 0x0 6. "NB,Number of banks" "0: Two banks,1: Four banks" bitfld.long 0x0 4.--5. "MWID,Memory data bus width." "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x0 2.--3. "NR,Number of row address bits" "0: 11 bit,1: 12 bits,2: 13 bits,?" bitfld.long 0x0 0.--1. "NC,Number of column address bits" "0: 8 bits,1: 9 bits,2: 10 bits,3: 11 bits." line.long 0x4 "FMC_SDCR2,SDRAM control registers for SDRAM device 2" bitfld.long 0x4 17. "SDINIT,SDRAM device initialization" "0: Initialization is not complete the AXI accesses..,1: Initialization is complete and the device is.." bitfld.long 0x4 16. "SDEN,SDRAM device enable" "0: SDRAM disabled,1: SDRAM device enabled" newline bitfld.long 0x4 9. "WP,Write protection" "0: Write accesses allowed,1: Write accesses ignored" bitfld.long 0x4 7.--8. "CAS,CAS Latency" "?,1: 1 cycle,2: 2 cycles,3: 3 cycles" newline bitfld.long 0x4 6. "NB,Number of banks" "0: Two banks,1: Four banks" bitfld.long 0x4 4.--5. "MWID,Memory data bus width." "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x4 2.--3. "NR,Number of row address bits" "0: 11 bit,1: 12 bits,2: 13 bits,?" bitfld.long 0x4 0.--1. "NC,Number of column address bits" "0: 8 bits,1: 9 bits,2: 10 bits,3: 11 bits." line.long 0x8 "FMC_SDTR,SDRAM timing register" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self-refresh time" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit self-refresh delay" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load mode register to active" group.long 0x150++0x7 line.long 0x0 "FMC_SDCMR,SDRAM command mode register" hexmask.long.word 0x0 9.--22. 1. "MRD,Mode register definition" hexmask.long.byte 0x0 5.--8. 1. "NRFS,Number of Refresh commands" newline bitfld.long 0x0 4. "DS1,Command targeting SDRAM device 1" "0: Command not issued to SDRAM device 1,1: Command issued to SDRAM device 1" bitfld.long 0x0 3. "DS2,Command targeting SDRAM device 2" "0: Command not issued to SDRAM device 2,1: Command issued to SDRAM device 2" newline bitfld.long 0x0 0.--2. "MODE,Command mode" "0: Normal mode command (NRM),?,2: Precharge all banks command (PALL),3: Refresh command (REF),4: Load mode register command (LMR),5: Self-refresh command (SR),6: Power-down command (PD),?" line.long 0x4 "FMC_SDRTR,SDRAM refresh timer register" bitfld.long 0x4 14. "REIE,RES Interrupt Enable" "0: Interrupt is disabled,1: An Interrupt is generated if RE = 1" hexmask.long.word 0x4 1.--13. 1. "RFSCNT,Refresh Timer Count" newline bitfld.long 0x4 0. "CRE,Clear Refresh error flag" "0: no effect,1: Refresh Error flag is cleared" rgroup.long 0x158++0x3 line.long 0x0 "FMC_SDSR,SDRAM status register" bitfld.long 0x0 15. "CMDOK,Previous command status" "0: Command not complete,1: Command complete in the SDRAM clock domain" bitfld.long 0x0 3.--4. "MODES2,Status mode for SDRAM device 2" "0: Normal mode devices are not in Self-refresh or..,1: Self-refresh,2: Power-down,?" newline bitfld.long 0x0 1.--2. "MODES1,Status Mode for SDRAM device 1" "0: Normal mode devices are not in Self-refresh or..,1: Self-refresh,2: Power-down,?" bitfld.long 0x0 0. "RE,Refresh error flag" "0: No refresh error has been detected,1: A refresh error has been detected" group.long 0x180++0x3 line.long 0x0 "FMC_IER,FMC NAND interrupt enable register" bitfld.long 0x0 2. "IFEE,Interrupt falling edge detection enable bit" "0: Interrupt falling edge detection request disabled,1: Interrupt falling edge detection request enabled" bitfld.long 0x0 1. "IHLE,Interrupt high-level detection enable bit" "0: Interrupt high-level detection request disabled,1: Interrupt high-level detection request enabled" newline bitfld.long 0x0 0. "IREE,Interrupt rising edge detection enable bit" "0: Interrupt rising edge detection request disabled,1: Interrupt rising edge detection request enabled" rgroup.long 0x184++0x3 line.long 0x0 "FMC_ISR,FMC controller interrupt status register" bitfld.long 0x0 2. "IFEF,Interrupt falling edge flag" "0: No interrupt falling edge occurred,1: Interrupt falling edge occurred" bitfld.long 0x0 1. "IHLF,Interrupt high-level flag" "0: No Interrupt high-level occurred,1: Interrupt high-level occurred" newline bitfld.long 0x0 0. "IREF,Interrupt rising edge flag" "0: No interrupt rising edge occurred,1: Interrupt rising edge occurred" wgroup.long 0x188++0x3 line.long 0x0 "FMC_ICR,FMC NAND controller interrupt clear register" bitfld.long 0x0 2. "CIFEF,Clear Interrupt falling edge flag" "0: No effect,1: Clears the IFEF flag in the FMC_ISR register" bitfld.long 0x0 1. "CIHLF,Clear Interrupt high-level flag" "0: No effect,1: Clears the IHLF flag in the FMC_ISR register" newline bitfld.long 0x0 0. "CIREF,Clear Interrupt rising edge flag" "0: No effect,1: Clear the IREF flag in the FMC_ISR register" wgroup.long 0x200++0x3 line.long 0x0 "FMC_CSQCR,FMC NAND command sequencer control register" bitfld.long 0x0 0. "CSQSTART,Command Sequencer Enable" "0,1" group.long 0x204++0x13 line.long 0x0 "FMC_CSQCFGR1,FMC NAND command sequencer configuration register 1" bitfld.long 0x0 25. "CMD2T,Command 2 Sequencer timings" "0: CMD2 issued with the timings programmed in..,1: CMD2 issued with the timings programmed in.." bitfld.long 0x0 24. "CMD1T,Command 1 Sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." newline hexmask.long.byte 0x0 16.--23. 1. "CMD2,Command 2 sequencer" hexmask.long.byte 0x0 8.--15. 1. "CMD1,Command 1 sequencer" newline bitfld.long 0x0 4.--6. "ACYNBR,Address Cycle number" "0: No address cycle.,1: 1 address cycle,2: 2 address cycles,3: 3 address cycles,4: 4 address cycles,5: 5 address cycles,?,?" bitfld.long 0x0 2. "DMADEN,Command sequencer DMA request data enable" "0: No DMA request transfer,1: A DMA request transfer" newline bitfld.long 0x0 1. "CMD2EN,Command cycle 2 Enable" "0: Command cycle 2 not issued.,1: Command cycle 2 (programmed CMD2[7:0]) sent by.." line.long 0x4 "FMC_CSQCFGR2,FMC NAND command sequencer configuration register 2" bitfld.long 0x4 25. "RCMD2T,Command 1 sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." bitfld.long 0x4 24. "RCMD1T,Command 1 sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." newline hexmask.long.byte 0x4 16.--23. 1. "RCMD2,Random Command 2 sequencer" hexmask.long.byte 0x4 8.--15. 1. "RCMD1,Random Command 1 sequencer" newline bitfld.long 0x4 2. "DMASEN,Command sequencer DMA request decoding status enable" "0: No DMA request used for ECC status registers..,1: A DMA request used for ECC status registers.." bitfld.long 0x4 1. "RCMD2EN,Random Command 2 sequencer enable" "0: Command 2 not issued.,1: Command 2 (CMD2SQ[7:0]) issued by the command.." newline bitfld.long 0x4 0. "SQSDTEN,Sequencer spare data transfer enable" "0: ECC disabled and spare data area not accessed by..,1: ECC enabled and spare data area read or.." line.long 0x8 "FMC_CSQCFGR3,FMC NAND sequencer configuration register 3" bitfld.long 0x8 23. "RAC2T,Random Address cycle 2 sequencer timings" "0: Random ADDC2 issued with the timings programmed..,1: Random ADDC2 issued with the timings programmed.." bitfld.long 0x8 22. "RAC1T,Random Address cycle 1 sequencer timings" "0: Random ADDC1 issued with the timings programmed..,1: Random ADDC1 issued with the timings programmed.." newline bitfld.long 0x8 21. "SDT,Spare data transfer sequencer timings" "0: Spare data transfer issued with the timings..,1: Spare data transfer issued with the timings.." bitfld.long 0x8 20. "AC5T,Address cycle 5 sequencer timings" "0: ADDC5 issued with the timings programmed in..,1: ADDC5 issued with the timings programmed in.." newline bitfld.long 0x8 19. "AC4T,Address cycle 4sequencer timings" "0: ADDC4 issued with the timings programmed in..,1: ADDC4 issued with the timings programmed in.." bitfld.long 0x8 18. "AC3T,Address cycle 3 sequencer timings" "0: ADDC3 issued with the timings programmed in..,1: ADDC3 issued with the timings programmed in.." newline bitfld.long 0x8 17. "AC2T,Address cycle 2 sequencer timings" "0: ADDC2 issued with the timings programmed in..,1: ADDC2 issued with the timings programmed in.." bitfld.long 0x8 16. "AC1T,Address cycle 1 sequencer timings" "0: ADDC1 issued with the timings programmed in..,1: ADDC1 issued with the timings programmed in.." newline hexmask.long.byte 0x8 8.--13. 1. "SNBR,Number of sectors to be read/written" line.long 0xC "FMC_CSQAR1,FMC NAND command sequencer address register 1" hexmask.long.byte 0xC 24.--31. 1. "ADDC4,Address Cycle 4" hexmask.long.byte 0xC 16.--23. 1. "ADDC3,Address Cycle 3" newline hexmask.long.byte 0xC 8.--15. 1. "ADDC2,Address Cycle 2" hexmask.long.byte 0xC 0.--7. 1. "ADDC1,Address Cycle 1" line.long 0x10 "FMC_CSQAR2,FMC NAND command sequencer address register 2" hexmask.long.word 0x10 16.--31. 1. "SAO,Spare Area Address Offset" hexmask.long.byte 0x10 0.--7. 1. "ADDC5,Address Cycle 5" group.long 0x220++0x7 line.long 0x0 "FMC_CSQIER,FMC NAND command sequencer interrupt enable register" bitfld.long 0x0 4. "CMDTCIE,Command Transfer Complete interrupt enable" "0: Command Transfer Complete Interrupt disable,1: Command Transfer Complete Interrupt enable" bitfld.long 0x0 3. "SUEIE,Sector Uncorrectable Error interrupt enable" "0: Command Transfer Complete Interrupt disable,1: Command Transfer Complete Interrupt enable" newline bitfld.long 0x0 2. "SEIE,Sector Error interrupt enable" "0: Sector Error Interrupt disable,1: Sector Error Interrupt enable" bitfld.long 0x0 1. "SCIE,Sector Complete interrupt enable" "0: Sector Complete Interrupt disable,1: Sector Complete Interrupt enable" newline bitfld.long 0x0 0. "TCIE,Transfer Complete Interrupt enable" "0: Transfer Complete Interrupt disable,1: Transfer Complete Interrupt enable" line.long 0x4 "FMC_CSQISR,FMC NAND command sequencer interrupt status register" bitfld.long 0x4 4. "CMDTCF,Command Transfer Complete flag" "0,1" bitfld.long 0x4 3. "SUEF,Sector Uncorrectable Error flag" "0,1" newline bitfld.long 0x4 2. "SEF,Sector Error flag" "0,1" bitfld.long 0x4 1. "SCF,Sector Complete flag" "0,1" newline bitfld.long 0x4 0. "TCF,Transfer Complete flag" "0,1" wgroup.long 0x228++0x3 line.long 0x0 "FMC_CSQICR,FMC NAND command sequencer interrupt clear register" bitfld.long 0x0 4. "CCMDTCF,Clear Command Transfer Complete flag" "0,1" bitfld.long 0x0 3. "CSUEF,Clear Sector uncorrectable Error flag" "0,1" newline bitfld.long 0x0 2. "CSEF,Clear Sector Error flag" "0,1" bitfld.long 0x0 1. "CSCF,Clear Sector Complete flag" "0,1" newline bitfld.long 0x0 0. "CTCF,Clear Transfer Complete flag" "0,1" rgroup.long 0x230++0x3 line.long 0x0 "FMC_CSQEMSR,FMC command sequencer error mapping status register" hexmask.long.word 0x0 0.--15. 1. "SEM,Sector Error mapping" group.long 0x250++0x3 line.long 0x0 "FMC_BCHIER,FMC BCH interrupt enable register" bitfld.long 0x0 4. "EPBRIE,Decoder Parity Bits Ready Interrupt enable" "0: Decoder Parity Bits Ready Interrupt disable,1: Decoder Parity Bits Ready Interrupt enable" bitfld.long 0x0 3. "DSRIE,Decoder Syndrome Ready Interrupt enable" "0: Decoder Syndrome Ready Interrupt disable,1: Decoder Syndrome Ready Interrupt enable" newline bitfld.long 0x0 2. "DEFIE,Decoder Error Found Interrupt enable" "0: Decoder Error Found Interrupt disable,1: Decoder Error Found Interrupt enable" bitfld.long 0x0 1. "DERIE,Decoder Error Ready Interrupt enable" "0: Decoder Error Ready Interrupt disable,1: Decoder Error Ready Interrupt enable" newline bitfld.long 0x0 0. "DUEIE,Decoder Uncorrectable Errors Interrupt enable" "0: Decoder Uncorrectable Errors Interrupt disable,1: Decoder Uncorrectable Errors Interrupt enable" rgroup.long 0x254++0x3 line.long 0x0 "FMC_BCHISR,FMC BCH interrupt and status register" bitfld.long 0x0 4. "EPBRF,Encoder Parity Bits Ready flag" "0,1" bitfld.long 0x0 3. "DSRF,Decoder Syndrome Ready flag" "0,1" newline bitfld.long 0x0 2. "DEFF,Decoder Error Found flag" "0,1" bitfld.long 0x0 1. "DERF,Decoder Error Ready flag" "0,1" newline bitfld.long 0x0 0. "DUEF,Decoder Uncorrectable Errors flag" "0,1" wgroup.long 0x258++0x3 line.long 0x0 "FMC_BCHICR,FMC BCH interrupt clear register" bitfld.long 0x0 4. "CEPBRF,Clear Encoder Parity Bits Ready flag" "0,1" bitfld.long 0x0 3. "CDSRF,Clear Decoder Syndrome Ready flag" "0,1" newline bitfld.long 0x0 2. "CDEFF,Clear Decoder Error Found flag" "0,1" bitfld.long 0x0 1. "CDERF,Clear Decoder Error ready flag" "0,1" newline bitfld.long 0x0 0. "CDUEF,Clear Decoder Uncorrectable Error flag" "0,1" rgroup.long 0x260++0xF line.long 0x0 "FMC_BCHPBR1,FMC BCH parity bits register 1" hexmask.long 0x0 0.--31. 1. "BCHPB,BCH parity bits" line.long 0x4 "FMC_BCHPBR2,FMC BCH parity bits register 2" hexmask.long 0x4 0.--31. 1. "BCHPB,BCH parity bits" line.long 0x8 "FMC_BCHPBR3,FMC BCH parity bits register 3" hexmask.long 0x8 0.--31. 1. "BCHPB,BCH parity bits" line.long 0xC "FMC_BCHPBR4,FMC BCH parity bits register 4" hexmask.long.byte 0xC 0.--7. 1. "BCHPB,BCH parity bits" rgroup.long 0x27C++0x13 line.long 0x0 "FMC_BCHDSR0,FMC BCH decoder status register 0" hexmask.long.byte 0x0 4.--7. 1. "DEN,Decoder error number" bitfld.long 0x0 1. "DEF,Decoder error found" "0,1" newline bitfld.long 0x0 0. "DUE,Decoder uncorrectable error" "0,1" line.long 0x4 "FMC_BCHDSR1,FMC BCH decoder status register for memory region 1" hexmask.long.word 0x4 16.--28. 1. "EBP2,Error bit position for error number 2" hexmask.long.word 0x4 0.--12. 1. "EBP1,Error bit position for error number 1" line.long 0x8 "FMC_BCHDSR2,FMC BCH decoder status register for memory region 2" hexmask.long.word 0x8 16.--28. 1. "EBP4,Error bit position for error number 4" hexmask.long.word 0x8 0.--12. 1. "EBP3,Error bit position for error number 3" line.long 0xC "FMC_BCHDSR3,FMC BCH decoder status register for memory region 3" hexmask.long.word 0xC 16.--28. 1. "EBP6,Error bit position for error number 6" hexmask.long.word 0xC 0.--12. 1. "EBP5,Error bit position for error number 5" line.long 0x10 "FMC_BCHDSR4,FMC BCH decoder status register for memory region 4" hexmask.long.word 0x10 16.--28. 1. "EBP8,Error bit position for error number 8" hexmask.long.word 0x10 0.--12. 1. "EBP7,Error bit position for error number 7" tree.end endif sif (cpuis("STM32N657*")) tree "FMC1" base ad:0x48024000 group.long 0x0++0x23 line.long 0x0 "FMC_BCR1,SRAM/NOR Flash chip-select control register for memory region 1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." bitfld.long 0x0 20.--21. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle,2: NEx deasserted after 64 fmc_ker_ck clock cycles,3: NEx deasserted after 256 fmc_ker_ck clock cycles" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." bitfld.long 0x0 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." bitfld.long 0x0 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." bitfld.long 0x0 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." bitfld.long 0x0 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x4 "FMC_BTR1,SRAM/NOR Flash chip-select timing registers for memory region 1" bitfld.long 0x4 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x4 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x8 "FMC_BCR2,SRAM/NOR Flash chip-select control register for memory region 2" bitfld.long 0x8 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." bitfld.long 0x8 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x8 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" bitfld.long 0x8 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." newline bitfld.long 0x8 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." newline bitfld.long 0x8 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" bitfld.long 0x8 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." newline bitfld.long 0x8 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." bitfld.long 0x8 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." newline bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." bitfld.long 0x8 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." newline bitfld.long 0x8 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." bitfld.long 0x8 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" newline bitfld.long 0x8 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." newline bitfld.long 0x8 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0xC "FMC_BTR2,SRAM/NOR Flash chip-select timing registers for memory region 2" bitfld.long 0xC 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0xC 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x10 "FMC_BCR3,SRAM/NOR Flash chip-select control register for memory region 3" bitfld.long 0x10 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." bitfld.long 0x10 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x10 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" bitfld.long 0x10 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." newline bitfld.long 0x10 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." newline bitfld.long 0x10 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" bitfld.long 0x10 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." newline bitfld.long 0x10 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." bitfld.long 0x10 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." newline bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." bitfld.long 0x10 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." newline bitfld.long 0x10 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." bitfld.long 0x10 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" newline bitfld.long 0x10 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." newline bitfld.long 0x10 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x14 "FMC_BTR3,SRAM/NOR Flash chip-select timing registers for memory region 3" bitfld.long 0x14 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x14 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x18 "FMC_BCR4,SRAM/NOR Flash chip-select control register for memory region 4" bitfld.long 0x18 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." bitfld.long 0x18 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x18 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" bitfld.long 0x18 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." newline bitfld.long 0x18 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." newline bitfld.long 0x18 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" bitfld.long 0x18 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." newline bitfld.long 0x18 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." bitfld.long 0x18 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." newline bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." bitfld.long 0x18 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." newline bitfld.long 0x18 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." bitfld.long 0x18 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" newline bitfld.long 0x18 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." newline bitfld.long 0x18 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x1C "FMC_BTR4,SRAM/NOR Flash chip-select timing registers for memory region 4" bitfld.long 0x1C 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x1C 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x20 "FMC_CFGR,FMC common configuration register" bitfld.long 0x20 31. "FMCEN,FMC controller enable" "0: FMC controller disabled,1: FMC controller enabled" bitfld.long 0x20 25. "BMAP1,FMC memory region mapping" "0: Default mapping (refer to Table 132),1: Devices are remapped (refer to Table 133)" newline bitfld.long 0x20 24. "BMAP0,FMC memory region mapping" "0: Default mapping (refer to Table 132),1: Devices are remapped (refer to Table 133)" bitfld.long 0x20 20. "CCLKEN,Continuous clock enable" "0: The FMC_CLK is only generated during the..,1: The FMC_CLK is generated continuously during.." newline hexmask.long.byte 0x20 16.--19. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" group.long 0x80++0x3 line.long 0x0 "FMC_PCR,NAND Flash programmable control register" bitfld.long 0x0 25. "WEN,Write enable" "0: Read access enabled,1: Write access enabled" bitfld.long 0x0 24. "BCHECC,BCH error correction capability" "0: 4-bit BCH (4-bit error correction and 8-bit..,1: 8-bit BCH (8-bit error correction and 16-bit.." newline bitfld.long 0x0 17.--19. "ECCSS,ECC sector size (used to access spare area)" "0: 256 bytes,1: 512 bytes,2: 1024 bytes,3: 2048 bytes (default),4: 4096 bytes,?,?,?" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay." newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay." bitfld.long 0x0 8. "ECCALG,ECC algorithm" "0: Hamming code is selected (default).,1: BCH code is selected." newline bitfld.long 0x0 6. "ECCEN,ECC computation logic enable bit" "0: ECC logic is disabled and reset (default after..,1: ECC logic is enabled." bitfld.long 0x0 4.--5. "PWID,Data bus width" "0: 8 bits (default after reset).,1: 16 bits,?,?" newline bitfld.long 0x0 2. "PBKEN,NAND Flash memory region enable bit" "0: Corresponding memory region is disabled (default..,1: Corresponding memory region is enabled." bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit" "0: disabled (default),1: enabled" rgroup.long 0x84++0x3 line.long 0x0 "FMC_SR,FMC status register" bitfld.long 0x0 6. "NWRF,NAND write request flag" "0: NAND Flash write requests are pending,1: No NAND Flash write requests pending" bitfld.long 0x0 4. "PEF,Pipe Empty Flag" "0,1" newline bitfld.long 0x0 0.--1. "ISOST,FMC isolation state with respect to the AXI interface" "0: FMC is not isolated; AXI transactions are..,1: FMC has been enabled (FMCEN = 1) and waits for..,2: FMC has been disabled (FMCEN = 0) and waits for..,3: FMC is isolated from its AXI interface. All AXI.." group.long 0x88++0x7 line.long 0x0 "FMC_PMEM,FMC common memory space timing register" hexmask.long.byte 0x0 24.--31. 1. "MEMHIZ,Common memory data bus Hi-Z time" hexmask.long.byte 0x0 16.--23. 1. "MEMHOLD,Common memory hold time" newline hexmask.long.byte 0x0 8.--15. 1. "MEMWAIT,Common memory wait time" hexmask.long.byte 0x0 0.--7. 1. "MEMSET,Common memory setup time" line.long 0x4 "FMC_PATT,FMC attribute memory space timing registers" hexmask.long.byte 0x4 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0x4 16.--23. 1. "ATTHOLD,Attribute memory hold time" newline hexmask.long.byte 0x4 8.--15. 1. "ATTWAIT,Attribute memory wait time" hexmask.long.byte 0x4 0.--7. 1. "ATTSET,Attribute memory setup time" rgroup.long 0x90++0x7 line.long 0x0 "FMC_HPR,FMC Hamming parity result registers" hexmask.long 0x0 0.--31. 1. "HPR,Hamming parity result" line.long 0x4 "FMC_HECCR,FMC Hamming code ECC result register" hexmask.long 0x4 0.--31. 1. "HECC,ECC result" group.long 0x104++0x3 line.long 0x0 "FMC_BWTR1,SRAM/NOR-Flash write timing registers for memory region 1" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x10C++0x3 line.long 0x0 "FMC_BWTR2,SRAM/NOR-Flash write timing registers for memory region 2" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x114++0x3 line.long 0x0 "FMC_BWTR3,SRAM/NOR-Flash write timing registers for memory region 3" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x11C++0x3 line.long 0x0 "FMC_BWTR4,SRAM/NOR-Flash write timing registers for memory region 4" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x140++0xB line.long 0x0 "FMC_SDCR1,SDRAM control registers for SDRAM device 1" bitfld.long 0x0 17. "SDINIT,SDRAM device initialization" "0: Initialization is not complete the AXI accesses..,1: Initialization is complete and the device is.." bitfld.long 0x0 16. "SDEN,SDRAM device enable" "0: SDRAM disabled,1: SDRAM device enabled" newline bitfld.long 0x0 13.--14. "RPIPE,Read pipe" "0: No fmc_ker_ck clock cycle delay (default value),1: One fmc_ker_ck clock cycle delay,2: Two fmc_ker_ck clock cycle delay,?" bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration" "0: SDCLK clock disabled,1: SDCLK period = 1 * fmc_ker_ck period,2: SDCLK period = 2 * fmc_ker_ck periods,3: SDCLK period = 3 * fmc_ker_ck periods" newline bitfld.long 0x0 9. "WP,Write protection" "0: Write accesses allowed,1: Write accesses ignored" bitfld.long 0x0 7.--8. "CAS,CAS Latency" "?,1: 1 cycle,2: 2 cycles,3: 3 cycles" newline bitfld.long 0x0 6. "NB,Number of banks" "0: Two banks,1: Four banks" bitfld.long 0x0 4.--5. "MWID,Memory data bus width." "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x0 2.--3. "NR,Number of row address bits" "0: 11 bit,1: 12 bits,2: 13 bits,?" bitfld.long 0x0 0.--1. "NC,Number of column address bits" "0: 8 bits,1: 9 bits,2: 10 bits,3: 11 bits." line.long 0x4 "FMC_SDCR2,SDRAM control registers for SDRAM device 2" bitfld.long 0x4 17. "SDINIT,SDRAM device initialization" "0: Initialization is not complete the AXI accesses..,1: Initialization is complete and the device is.." bitfld.long 0x4 16. "SDEN,SDRAM device enable" "0: SDRAM disabled,1: SDRAM device enabled" newline bitfld.long 0x4 9. "WP,Write protection" "0: Write accesses allowed,1: Write accesses ignored" bitfld.long 0x4 7.--8. "CAS,CAS Latency" "?,1: 1 cycle,2: 2 cycles,3: 3 cycles" newline bitfld.long 0x4 6. "NB,Number of banks" "0: Two banks,1: Four banks" bitfld.long 0x4 4.--5. "MWID,Memory data bus width." "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x4 2.--3. "NR,Number of row address bits" "0: 11 bit,1: 12 bits,2: 13 bits,?" bitfld.long 0x4 0.--1. "NC,Number of column address bits" "0: 8 bits,1: 9 bits,2: 10 bits,3: 11 bits." line.long 0x8 "FMC_SDTR,SDRAM timing register" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self-refresh time" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit self-refresh delay" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load mode register to active" group.long 0x150++0x7 line.long 0x0 "FMC_SDCMR,SDRAM command mode register" hexmask.long.word 0x0 9.--22. 1. "MRD,Mode register definition" hexmask.long.byte 0x0 5.--8. 1. "NRFS,Number of Refresh commands" newline bitfld.long 0x0 4. "DS1,Command targeting SDRAM device 1" "0: Command not issued to SDRAM device 1,1: Command issued to SDRAM device 1" bitfld.long 0x0 3. "DS2,Command targeting SDRAM device 2" "0: Command not issued to SDRAM device 2,1: Command issued to SDRAM device 2" newline bitfld.long 0x0 0.--2. "MODE,Command mode" "0: Normal mode command (NRM),?,2: Precharge all banks command (PALL),3: Refresh command (REF),4: Load mode register command (LMR),5: Self-refresh command (SR),6: Power-down command (PD),?" line.long 0x4 "FMC_SDRTR,SDRAM refresh timer register" bitfld.long 0x4 14. "REIE,RES Interrupt Enable" "0: Interrupt is disabled,1: An Interrupt is generated if RE = 1" hexmask.long.word 0x4 1.--13. 1. "RFSCNT,Refresh Timer Count" newline bitfld.long 0x4 0. "CRE,Clear Refresh error flag" "0: no effect,1: Refresh Error flag is cleared" rgroup.long 0x158++0x3 line.long 0x0 "FMC_SDSR,SDRAM status register" bitfld.long 0x0 15. "CMDOK,Previous command status" "0: Command not complete,1: Command complete in the SDRAM clock domain" bitfld.long 0x0 3.--4. "MODES2,Status mode for SDRAM device 2" "0: Normal mode devices are not in Self-refresh or..,1: Self-refresh,2: Power-down,?" newline bitfld.long 0x0 1.--2. "MODES1,Status Mode for SDRAM device 1" "0: Normal mode devices are not in Self-refresh or..,1: Self-refresh,2: Power-down,?" bitfld.long 0x0 0. "RE,Refresh error flag" "0: No refresh error has been detected,1: A refresh error has been detected" group.long 0x180++0x3 line.long 0x0 "FMC_IER,FMC NAND interrupt enable register" bitfld.long 0x0 2. "IFEE,Interrupt falling edge detection enable bit" "0: Interrupt falling edge detection request disabled,1: Interrupt falling edge detection request enabled" bitfld.long 0x0 1. "IHLE,Interrupt high-level detection enable bit" "0: Interrupt high-level detection request disabled,1: Interrupt high-level detection request enabled" newline bitfld.long 0x0 0. "IREE,Interrupt rising edge detection enable bit" "0: Interrupt rising edge detection request disabled,1: Interrupt rising edge detection request enabled" rgroup.long 0x184++0x3 line.long 0x0 "FMC_ISR,FMC controller interrupt status register" bitfld.long 0x0 2. "IFEF,Interrupt falling edge flag" "0: No interrupt falling edge occurred,1: Interrupt falling edge occurred" bitfld.long 0x0 1. "IHLF,Interrupt high-level flag" "0: No Interrupt high-level occurred,1: Interrupt high-level occurred" newline bitfld.long 0x0 0. "IREF,Interrupt rising edge flag" "0: No interrupt rising edge occurred,1: Interrupt rising edge occurred" wgroup.long 0x188++0x3 line.long 0x0 "FMC_ICR,FMC NAND controller interrupt clear register" bitfld.long 0x0 2. "CIFEF,Clear Interrupt falling edge flag" "0: No effect,1: Clears the IFEF flag in the FMC_ISR register" bitfld.long 0x0 1. "CIHLF,Clear Interrupt high-level flag" "0: No effect,1: Clears the IHLF flag in the FMC_ISR register" newline bitfld.long 0x0 0. "CIREF,Clear Interrupt rising edge flag" "0: No effect,1: Clear the IREF flag in the FMC_ISR register" wgroup.long 0x200++0x3 line.long 0x0 "FMC_CSQCR,FMC NAND command sequencer control register" bitfld.long 0x0 0. "CSQSTART,Command Sequencer Enable" "0,1" group.long 0x204++0x13 line.long 0x0 "FMC_CSQCFGR1,FMC NAND command sequencer configuration register 1" bitfld.long 0x0 25. "CMD2T,Command 2 Sequencer timings" "0: CMD2 issued with the timings programmed in..,1: CMD2 issued with the timings programmed in.." bitfld.long 0x0 24. "CMD1T,Command 1 Sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." newline hexmask.long.byte 0x0 16.--23. 1. "CMD2,Command 2 sequencer" hexmask.long.byte 0x0 8.--15. 1. "CMD1,Command 1 sequencer" newline bitfld.long 0x0 4.--6. "ACYNBR,Address Cycle number" "0: No address cycle.,1: 1 address cycle,2: 2 address cycles,3: 3 address cycles,4: 4 address cycles,5: 5 address cycles,?,?" bitfld.long 0x0 2. "DMADEN,Command sequencer DMA request data enable" "0: No DMA request transfer,1: A DMA request transfer" newline bitfld.long 0x0 1. "CMD2EN,Command cycle 2 Enable" "0: Command cycle 2 not issued.,1: Command cycle 2 (programmed CMD2[7:0]) sent by.." line.long 0x4 "FMC_CSQCFGR2,FMC NAND command sequencer configuration register 2" bitfld.long 0x4 25. "RCMD2T,Command 1 sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." bitfld.long 0x4 24. "RCMD1T,Command 1 sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." newline hexmask.long.byte 0x4 16.--23. 1. "RCMD2,Random Command 2 sequencer" hexmask.long.byte 0x4 8.--15. 1. "RCMD1,Random Command 1 sequencer" newline bitfld.long 0x4 2. "DMASEN,Command sequencer DMA request decoding status enable" "0: No DMA request used for ECC status registers..,1: A DMA request used for ECC status registers.." bitfld.long 0x4 1. "RCMD2EN,Random Command 2 sequencer enable" "0: Command 2 not issued.,1: Command 2 (CMD2SQ[7:0]) issued by the command.." newline bitfld.long 0x4 0. "SQSDTEN,Sequencer spare data transfer enable" "0: ECC disabled and spare data area not accessed by..,1: ECC enabled and spare data area read or.." line.long 0x8 "FMC_CSQCFGR3,FMC NAND sequencer configuration register 3" bitfld.long 0x8 23. "RAC2T,Random Address cycle 2 sequencer timings" "0: Random ADDC2 issued with the timings programmed..,1: Random ADDC2 issued with the timings programmed.." bitfld.long 0x8 22. "RAC1T,Random Address cycle 1 sequencer timings" "0: Random ADDC1 issued with the timings programmed..,1: Random ADDC1 issued with the timings programmed.." newline bitfld.long 0x8 21. "SDT,Spare data transfer sequencer timings" "0: Spare data transfer issued with the timings..,1: Spare data transfer issued with the timings.." bitfld.long 0x8 20. "AC5T,Address cycle 5 sequencer timings" "0: ADDC5 issued with the timings programmed in..,1: ADDC5 issued with the timings programmed in.." newline bitfld.long 0x8 19. "AC4T,Address cycle 4sequencer timings" "0: ADDC4 issued with the timings programmed in..,1: ADDC4 issued with the timings programmed in.." bitfld.long 0x8 18. "AC3T,Address cycle 3 sequencer timings" "0: ADDC3 issued with the timings programmed in..,1: ADDC3 issued with the timings programmed in.." newline bitfld.long 0x8 17. "AC2T,Address cycle 2 sequencer timings" "0: ADDC2 issued with the timings programmed in..,1: ADDC2 issued with the timings programmed in.." bitfld.long 0x8 16. "AC1T,Address cycle 1 sequencer timings" "0: ADDC1 issued with the timings programmed in..,1: ADDC1 issued with the timings programmed in.." newline hexmask.long.byte 0x8 8.--13. 1. "SNBR,Number of sectors to be read/written" line.long 0xC "FMC_CSQAR1,FMC NAND command sequencer address register 1" hexmask.long.byte 0xC 24.--31. 1. "ADDC4,Address Cycle 4" hexmask.long.byte 0xC 16.--23. 1. "ADDC3,Address Cycle 3" newline hexmask.long.byte 0xC 8.--15. 1. "ADDC2,Address Cycle 2" hexmask.long.byte 0xC 0.--7. 1. "ADDC1,Address Cycle 1" line.long 0x10 "FMC_CSQAR2,FMC NAND command sequencer address register 2" hexmask.long.word 0x10 16.--31. 1. "SAO,Spare Area Address Offset" hexmask.long.byte 0x10 0.--7. 1. "ADDC5,Address Cycle 5" group.long 0x220++0x7 line.long 0x0 "FMC_CSQIER,FMC NAND command sequencer interrupt enable register" bitfld.long 0x0 4. "CMDTCIE,Command Transfer Complete interrupt enable" "0: Command Transfer Complete Interrupt disable,1: Command Transfer Complete Interrupt enable" bitfld.long 0x0 3. "SUEIE,Sector Uncorrectable Error interrupt enable" "0: Command Transfer Complete Interrupt disable,1: Command Transfer Complete Interrupt enable" newline bitfld.long 0x0 2. "SEIE,Sector Error interrupt enable" "0: Sector Error Interrupt disable,1: Sector Error Interrupt enable" bitfld.long 0x0 1. "SCIE,Sector Complete interrupt enable" "0: Sector Complete Interrupt disable,1: Sector Complete Interrupt enable" newline bitfld.long 0x0 0. "TCIE,Transfer Complete Interrupt enable" "0: Transfer Complete Interrupt disable,1: Transfer Complete Interrupt enable" line.long 0x4 "FMC_CSQISR,FMC NAND command sequencer interrupt status register" bitfld.long 0x4 4. "CMDTCF,Command Transfer Complete flag" "0,1" bitfld.long 0x4 3. "SUEF,Sector Uncorrectable Error flag" "0,1" newline bitfld.long 0x4 2. "SEF,Sector Error flag" "0,1" bitfld.long 0x4 1. "SCF,Sector Complete flag" "0,1" newline bitfld.long 0x4 0. "TCF,Transfer Complete flag" "0,1" wgroup.long 0x228++0x3 line.long 0x0 "FMC_CSQICR,FMC NAND command sequencer interrupt clear register" bitfld.long 0x0 4. "CCMDTCF,Clear Command Transfer Complete flag" "0,1" bitfld.long 0x0 3. "CSUEF,Clear Sector uncorrectable Error flag" "0,1" newline bitfld.long 0x0 2. "CSEF,Clear Sector Error flag" "0,1" bitfld.long 0x0 1. "CSCF,Clear Sector Complete flag" "0,1" newline bitfld.long 0x0 0. "CTCF,Clear Transfer Complete flag" "0,1" rgroup.long 0x230++0x3 line.long 0x0 "FMC_CSQEMSR,FMC command sequencer error mapping status register" hexmask.long.word 0x0 0.--15. 1. "SEM,Sector Error mapping" group.long 0x250++0x3 line.long 0x0 "FMC_BCHIER,FMC BCH interrupt enable register" bitfld.long 0x0 4. "EPBRIE,Decoder Parity Bits Ready Interrupt enable" "0: Decoder Parity Bits Ready Interrupt disable,1: Decoder Parity Bits Ready Interrupt enable" bitfld.long 0x0 3. "DSRIE,Decoder Syndrome Ready Interrupt enable" "0: Decoder Syndrome Ready Interrupt disable,1: Decoder Syndrome Ready Interrupt enable" newline bitfld.long 0x0 2. "DEFIE,Decoder Error Found Interrupt enable" "0: Decoder Error Found Interrupt disable,1: Decoder Error Found Interrupt enable" bitfld.long 0x0 1. "DERIE,Decoder Error Ready Interrupt enable" "0: Decoder Error Ready Interrupt disable,1: Decoder Error Ready Interrupt enable" newline bitfld.long 0x0 0. "DUEIE,Decoder Uncorrectable Errors Interrupt enable" "0: Decoder Uncorrectable Errors Interrupt disable,1: Decoder Uncorrectable Errors Interrupt enable" rgroup.long 0x254++0x3 line.long 0x0 "FMC_BCHISR,FMC BCH interrupt and status register" bitfld.long 0x0 4. "EPBRF,Encoder Parity Bits Ready flag" "0,1" bitfld.long 0x0 3. "DSRF,Decoder Syndrome Ready flag" "0,1" newline bitfld.long 0x0 2. "DEFF,Decoder Error Found flag" "0,1" bitfld.long 0x0 1. "DERF,Decoder Error Ready flag" "0,1" newline bitfld.long 0x0 0. "DUEF,Decoder Uncorrectable Errors flag" "0,1" wgroup.long 0x258++0x3 line.long 0x0 "FMC_BCHICR,FMC BCH interrupt clear register" bitfld.long 0x0 4. "CEPBRF,Clear Encoder Parity Bits Ready flag" "0,1" bitfld.long 0x0 3. "CDSRF,Clear Decoder Syndrome Ready flag" "0,1" newline bitfld.long 0x0 2. "CDEFF,Clear Decoder Error Found flag" "0,1" bitfld.long 0x0 1. "CDERF,Clear Decoder Error ready flag" "0,1" newline bitfld.long 0x0 0. "CDUEF,Clear Decoder Uncorrectable Error flag" "0,1" rgroup.long 0x260++0xF line.long 0x0 "FMC_BCHPBR1,FMC BCH parity bits register 1" hexmask.long 0x0 0.--31. 1. "BCHPB,BCH parity bits" line.long 0x4 "FMC_BCHPBR2,FMC BCH parity bits register 2" hexmask.long 0x4 0.--31. 1. "BCHPB,BCH parity bits" line.long 0x8 "FMC_BCHPBR3,FMC BCH parity bits register 3" hexmask.long 0x8 0.--31. 1. "BCHPB,BCH parity bits" line.long 0xC "FMC_BCHPBR4,FMC BCH parity bits register 4" hexmask.long.byte 0xC 0.--7. 1. "BCHPB,BCH parity bits" rgroup.long 0x27C++0x13 line.long 0x0 "FMC_BCHDSR0,FMC BCH decoder status register 0" hexmask.long.byte 0x0 4.--7. 1. "DEN,Decoder error number" bitfld.long 0x0 1. "DEF,Decoder error found" "0,1" newline bitfld.long 0x0 0. "DUE,Decoder uncorrectable error" "0,1" line.long 0x4 "FMC_BCHDSR1,FMC BCH decoder status register for memory region 1" hexmask.long.word 0x4 16.--28. 1. "EBP2,Error bit position for error number 2" hexmask.long.word 0x4 0.--12. 1. "EBP1,Error bit position for error number 1" line.long 0x8 "FMC_BCHDSR2,FMC BCH decoder status register for memory region 2" hexmask.long.word 0x8 16.--28. 1. "EBP4,Error bit position for error number 4" hexmask.long.word 0x8 0.--12. 1. "EBP3,Error bit position for error number 3" line.long 0xC "FMC_BCHDSR3,FMC BCH decoder status register for memory region 3" hexmask.long.word 0xC 16.--28. 1. "EBP6,Error bit position for error number 6" hexmask.long.word 0xC 0.--12. 1. "EBP5,Error bit position for error number 5" line.long 0x10 "FMC_BCHDSR4,FMC BCH decoder status register for memory region 4" hexmask.long.word 0x10 16.--28. 1. "EBP8,Error bit position for error number 8" hexmask.long.word 0x10 0.--12. 1. "EBP7,Error bit position for error number 7" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")||cpuis("STM32N655*")) tree "FMC1_S" base ad:0x58024000 group.long 0x0++0x23 line.long 0x0 "FMC_BCR1,SRAM/NOR Flash chip-select control register for memory region 1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." bitfld.long 0x0 20.--21. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle,2: NEx deasserted after 64 fmc_ker_ck clock cycles,3: NEx deasserted after 256 fmc_ker_ck clock cycles" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." bitfld.long 0x0 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." bitfld.long 0x0 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." bitfld.long 0x0 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." bitfld.long 0x0 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x4 "FMC_BTR1,SRAM/NOR Flash chip-select timing registers for memory region 1" bitfld.long 0x4 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x4 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x8 "FMC_BCR2,SRAM/NOR Flash chip-select control register for memory region 2" bitfld.long 0x8 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." sif (cpuis("STM32N655*")) bitfld.long 0x8 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x8 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) bitfld.long 0x8 20.--21. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle,2: NEx deasserted after 64 fmc_ker_ck clock cycles,3: NEx deasserted after 256 fmc_ker_ck clock cycles" newline endif bitfld.long 0x8 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." bitfld.long 0x8 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." bitfld.long 0x8 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." bitfld.long 0x8 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." bitfld.long 0x8 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" bitfld.long 0x8 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." bitfld.long 0x8 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0xC "FMC_BTR2,SRAM/NOR Flash chip-select timing registers for memory region 2" bitfld.long 0xC 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0xC 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x10 "FMC_BCR3,SRAM/NOR Flash chip-select control register for memory region 3" bitfld.long 0x10 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." sif (cpuis("STM32N655*")) bitfld.long 0x10 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x10 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) bitfld.long 0x10 20.--21. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle,2: NEx deasserted after 64 fmc_ker_ck clock cycles,3: NEx deasserted after 256 fmc_ker_ck clock cycles" newline endif bitfld.long 0x10 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." bitfld.long 0x10 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." bitfld.long 0x10 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." bitfld.long 0x10 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." bitfld.long 0x10 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" bitfld.long 0x10 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." bitfld.long 0x10 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x14 "FMC_BTR3,SRAM/NOR Flash chip-select timing registers for memory region 3" bitfld.long 0x14 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x14 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x18 "FMC_BCR4,SRAM/NOR Flash chip-select control register for memory region 4" bitfld.long 0x18 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." sif (cpuis("STM32N655*")) bitfld.long 0x18 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x18 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) bitfld.long 0x18 20.--21. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle,2: NEx deasserted after 64 fmc_ker_ck clock cycles,3: NEx deasserted after 256 fmc_ker_ck clock cycles" newline endif bitfld.long 0x18 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." bitfld.long 0x18 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." bitfld.long 0x18 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." bitfld.long 0x18 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." bitfld.long 0x18 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" bitfld.long 0x18 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." bitfld.long 0x18 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x1C "FMC_BTR4,SRAM/NOR Flash chip-select timing registers for memory region 4" bitfld.long 0x1C 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x1C 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x20 "FMC_CFGR,FMC common configuration register" bitfld.long 0x20 31. "FMCEN,FMC controller enable" "0: FMC controller disabled,1: FMC controller enabled" bitfld.long 0x20 25. "BMAP1,FMC memory region mapping" "0: Default mapping (refer to Table 132),1: Devices are remapped (refer to Table 133)" newline bitfld.long 0x20 24. "BMAP0,FMC memory region mapping" "0: Default mapping (refer to Table 132),1: Devices are remapped (refer to Table 133)" bitfld.long 0x20 20. "CCLKEN,Continuous clock enable" "0: The FMC_CLK is only generated during the..,1: The FMC_CLK is generated continuously during.." newline hexmask.long.byte 0x20 16.--19. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" group.long 0x80++0x3 line.long 0x0 "FMC_PCR,NAND Flash programmable control register" bitfld.long 0x0 25. "WEN,Write enable" "0: Read access enabled,1: Write access enabled" bitfld.long 0x0 24. "BCHECC,BCH error correction capability" "0: 4-bit BCH (4-bit error correction and 8-bit..,1: 8-bit BCH (8-bit error correction and 16-bit.." newline bitfld.long 0x0 17.--19. "ECCSS,ECC sector size (used to access spare area)" "0: 256 bytes,1: 512 bytes,2: 1024 bytes,3: 2048 bytes (default),4: 4096 bytes,?,?,?" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay." newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay." bitfld.long 0x0 8. "ECCALG,ECC algorithm" "0: Hamming code is selected (default).,1: BCH code is selected." newline bitfld.long 0x0 6. "ECCEN,ECC computation logic enable bit" "0: ECC logic is disabled and reset (default after..,1: ECC logic is enabled." bitfld.long 0x0 4.--5. "PWID,Data bus width" "0: 8 bits (default after reset).,1: 16 bits,?,?" newline bitfld.long 0x0 2. "PBKEN,NAND Flash memory region enable bit" "0: Corresponding memory region is disabled (default..,1: Corresponding memory region is enabled." bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit" "0: disabled (default),1: enabled" rgroup.long 0x84++0x3 line.long 0x0 "FMC_SR,FMC status register" bitfld.long 0x0 6. "NWRF,NAND write request flag" "0: NAND Flash write requests are pending,1: No NAND Flash write requests pending" bitfld.long 0x0 4. "PEF,Pipe Empty Flag" "0,1" newline bitfld.long 0x0 0.--1. "ISOST,FMC isolation state with respect to the AXI interface" "0: FMC is not isolated; AXI transactions are..,1: FMC has been enabled (FMCEN = 1) and waits for..,2: FMC has been disabled (FMCEN = 0) and waits for..,3: FMC is isolated from its AXI interface. All AXI.." group.long 0x88++0x7 line.long 0x0 "FMC_PMEM,FMC common memory space timing register" hexmask.long.byte 0x0 24.--31. 1. "MEMHIZ,Common memory data bus Hi-Z time" hexmask.long.byte 0x0 16.--23. 1. "MEMHOLD,Common memory hold time" newline hexmask.long.byte 0x0 8.--15. 1. "MEMWAIT,Common memory wait time" hexmask.long.byte 0x0 0.--7. 1. "MEMSET,Common memory setup time" line.long 0x4 "FMC_PATT,FMC attribute memory space timing registers" hexmask.long.byte 0x4 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0x4 16.--23. 1. "ATTHOLD,Attribute memory hold time" newline hexmask.long.byte 0x4 8.--15. 1. "ATTWAIT,Attribute memory wait time" hexmask.long.byte 0x4 0.--7. 1. "ATTSET,Attribute memory setup time" rgroup.long 0x90++0x7 line.long 0x0 "FMC_HPR,FMC Hamming parity result registers" hexmask.long 0x0 0.--31. 1. "HPR,Hamming parity result" line.long 0x4 "FMC_HECCR,FMC Hamming code ECC result register" hexmask.long 0x4 0.--31. 1. "HECC,ECC result" group.long 0x104++0x3 line.long 0x0 "FMC_BWTR1,SRAM/NOR-Flash write timing registers for memory region 1" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x10C++0x3 line.long 0x0 "FMC_BWTR2,SRAM/NOR-Flash write timing registers for memory region 2" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x114++0x3 line.long 0x0 "FMC_BWTR3,SRAM/NOR-Flash write timing registers for memory region 3" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x11C++0x3 line.long 0x0 "FMC_BWTR4,SRAM/NOR-Flash write timing registers for memory region 4" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x140++0xB line.long 0x0 "FMC_SDCR1,SDRAM control registers for SDRAM device 1" bitfld.long 0x0 17. "SDINIT,SDRAM device initialization" "0: Initialization is not complete the AXI accesses..,1: Initialization is complete and the device is.." bitfld.long 0x0 16. "SDEN,SDRAM device enable" "0: SDRAM disabled,1: SDRAM device enabled" newline bitfld.long 0x0 13.--14. "RPIPE,Read pipe" "0: No fmc_ker_ck clock cycle delay (default value),1: One fmc_ker_ck clock cycle delay,2: Two fmc_ker_ck clock cycle delay,?" bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration" "0: SDCLK clock disabled,1: SDCLK period = 1 * fmc_ker_ck period,2: SDCLK period = 2 * fmc_ker_ck periods,3: SDCLK period = 3 * fmc_ker_ck periods" newline bitfld.long 0x0 9. "WP,Write protection" "0: Write accesses allowed,1: Write accesses ignored" bitfld.long 0x0 7.--8. "CAS,CAS Latency" "?,1: 1 cycle,2: 2 cycles,3: 3 cycles" newline bitfld.long 0x0 6. "NB,Number of banks" "0: Two banks,1: Four banks" bitfld.long 0x0 4.--5. "MWID,Memory data bus width." "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x0 2.--3. "NR,Number of row address bits" "0: 11 bit,1: 12 bits,2: 13 bits,?" bitfld.long 0x0 0.--1. "NC,Number of column address bits" "0: 8 bits,1: 9 bits,2: 10 bits,3: 11 bits." line.long 0x4 "FMC_SDCR2,SDRAM control registers for SDRAM device 2" bitfld.long 0x4 17. "SDINIT,SDRAM device initialization" "0: Initialization is not complete the AXI accesses..,1: Initialization is complete and the device is.." bitfld.long 0x4 16. "SDEN,SDRAM device enable" "0: SDRAM disabled,1: SDRAM device enabled" newline bitfld.long 0x4 9. "WP,Write protection" "0: Write accesses allowed,1: Write accesses ignored" bitfld.long 0x4 7.--8. "CAS,CAS Latency" "?,1: 1 cycle,2: 2 cycles,3: 3 cycles" newline bitfld.long 0x4 6. "NB,Number of banks" "0: Two banks,1: Four banks" bitfld.long 0x4 4.--5. "MWID,Memory data bus width." "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x4 2.--3. "NR,Number of row address bits" "0: 11 bit,1: 12 bits,2: 13 bits,?" bitfld.long 0x4 0.--1. "NC,Number of column address bits" "0: 8 bits,1: 9 bits,2: 10 bits,3: 11 bits." line.long 0x8 "FMC_SDTR,SDRAM timing register" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self-refresh time" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit self-refresh delay" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load mode register to active" group.long 0x150++0x7 line.long 0x0 "FMC_SDCMR,SDRAM command mode register" hexmask.long.word 0x0 9.--22. 1. "MRD,Mode register definition" hexmask.long.byte 0x0 5.--8. 1. "NRFS,Number of Refresh commands" newline bitfld.long 0x0 4. "DS1,Command targeting SDRAM device 1" "0: Command not issued to SDRAM device 1,1: Command issued to SDRAM device 1" bitfld.long 0x0 3. "DS2,Command targeting SDRAM device 2" "0: Command not issued to SDRAM device 2,1: Command issued to SDRAM device 2" newline bitfld.long 0x0 0.--2. "MODE,Command mode" "0: Normal mode command (NRM),?,2: Precharge all banks command (PALL),3: Refresh command (REF),4: Load mode register command (LMR),5: Self-refresh command (SR),6: Power-down command (PD),?" line.long 0x4 "FMC_SDRTR,SDRAM refresh timer register" bitfld.long 0x4 14. "REIE,RES Interrupt Enable" "0: Interrupt is disabled,1: An Interrupt is generated if RE = 1" hexmask.long.word 0x4 1.--13. 1. "RFSCNT,Refresh Timer Count" newline bitfld.long 0x4 0. "CRE,Clear Refresh error flag" "0: no effect,1: Refresh Error flag is cleared" rgroup.long 0x158++0x3 line.long 0x0 "FMC_SDSR,SDRAM status register" bitfld.long 0x0 15. "CMDOK,Previous command status" "0: Command not complete,1: Command complete in the SDRAM clock domain" bitfld.long 0x0 3.--4. "MODES2,Status mode for SDRAM device 2" "0: Normal mode devices are not in Self-refresh or..,1: Self-refresh,2: Power-down,?" newline bitfld.long 0x0 1.--2. "MODES1,Status Mode for SDRAM device 1" "0: Normal mode devices are not in Self-refresh or..,1: Self-refresh,2: Power-down,?" bitfld.long 0x0 0. "RE,Refresh error flag" "0: No refresh error has been detected,1: A refresh error has been detected" group.long 0x180++0x3 line.long 0x0 "FMC_IER,FMC NAND interrupt enable register" bitfld.long 0x0 2. "IFEE,Interrupt falling edge detection enable bit" "0: Interrupt falling edge detection request disabled,1: Interrupt falling edge detection request enabled" bitfld.long 0x0 1. "IHLE,Interrupt high-level detection enable bit" "0: Interrupt high-level detection request disabled,1: Interrupt high-level detection request enabled" newline bitfld.long 0x0 0. "IREE,Interrupt rising edge detection enable bit" "0: Interrupt rising edge detection request disabled,1: Interrupt rising edge detection request enabled" rgroup.long 0x184++0x3 line.long 0x0 "FMC_ISR,FMC controller interrupt status register" bitfld.long 0x0 2. "IFEF,Interrupt falling edge flag" "0: No interrupt falling edge occurred,1: Interrupt falling edge occurred" bitfld.long 0x0 1. "IHLF,Interrupt high-level flag" "0: No Interrupt high-level occurred,1: Interrupt high-level occurred" newline bitfld.long 0x0 0. "IREF,Interrupt rising edge flag" "0: No interrupt rising edge occurred,1: Interrupt rising edge occurred" wgroup.long 0x188++0x3 line.long 0x0 "FMC_ICR,FMC NAND controller interrupt clear register" bitfld.long 0x0 2. "CIFEF,Clear Interrupt falling edge flag" "0: No effect,1: Clears the IFEF flag in the FMC_ISR register" bitfld.long 0x0 1. "CIHLF,Clear Interrupt high-level flag" "0: No effect,1: Clears the IHLF flag in the FMC_ISR register" newline bitfld.long 0x0 0. "CIREF,Clear Interrupt rising edge flag" "0: No effect,1: Clear the IREF flag in the FMC_ISR register" wgroup.long 0x200++0x3 line.long 0x0 "FMC_CSQCR,FMC NAND command sequencer control register" bitfld.long 0x0 0. "CSQSTART,Command Sequencer Enable" "0,1" group.long 0x204++0x13 line.long 0x0 "FMC_CSQCFGR1,FMC NAND command sequencer configuration register 1" bitfld.long 0x0 25. "CMD2T,Command 2 Sequencer timings" "0: CMD2 issued with the timings programmed in..,1: CMD2 issued with the timings programmed in.." bitfld.long 0x0 24. "CMD1T,Command 1 Sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." newline hexmask.long.byte 0x0 16.--23. 1. "CMD2,Command 2 sequencer" hexmask.long.byte 0x0 8.--15. 1. "CMD1,Command 1 sequencer" newline bitfld.long 0x0 4.--6. "ACYNBR,Address Cycle number" "0: No address cycle.,1: 1 address cycle,2: 2 address cycles,3: 3 address cycles,4: 4 address cycles,5: 5 address cycles,?,?" bitfld.long 0x0 2. "DMADEN,Command sequencer DMA request data enable" "0: No DMA request transfer,1: A DMA request transfer" newline bitfld.long 0x0 1. "CMD2EN,Command cycle 2 Enable" "0: Command cycle 2 not issued.,1: Command cycle 2 (programmed CMD2[7:0]) sent by.." line.long 0x4 "FMC_CSQCFGR2,FMC NAND command sequencer configuration register 2" bitfld.long 0x4 25. "RCMD2T,Command 1 sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." bitfld.long 0x4 24. "RCMD1T,Command 1 sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." newline hexmask.long.byte 0x4 16.--23. 1. "RCMD2,Random Command 2 sequencer" hexmask.long.byte 0x4 8.--15. 1. "RCMD1,Random Command 1 sequencer" newline bitfld.long 0x4 2. "DMASEN,Command sequencer DMA request decoding status enable" "0: No DMA request used for ECC status registers..,1: A DMA request used for ECC status registers.." bitfld.long 0x4 1. "RCMD2EN,Random Command 2 sequencer enable" "0: Command 2 not issued.,1: Command 2 (CMD2SQ[7:0]) issued by the command.." newline bitfld.long 0x4 0. "SQSDTEN,Sequencer spare data transfer enable" "0: ECC disabled and spare data area not accessed by..,1: ECC enabled and spare data area read or.." line.long 0x8 "FMC_CSQCFGR3,FMC NAND sequencer configuration register 3" bitfld.long 0x8 23. "RAC2T,Random Address cycle 2 sequencer timings" "0: Random ADDC2 issued with the timings programmed..,1: Random ADDC2 issued with the timings programmed.." bitfld.long 0x8 22. "RAC1T,Random Address cycle 1 sequencer timings" "0: Random ADDC1 issued with the timings programmed..,1: Random ADDC1 issued with the timings programmed.." newline bitfld.long 0x8 21. "SDT,Spare data transfer sequencer timings" "0: Spare data transfer issued with the timings..,1: Spare data transfer issued with the timings.." bitfld.long 0x8 20. "AC5T,Address cycle 5 sequencer timings" "0: ADDC5 issued with the timings programmed in..,1: ADDC5 issued with the timings programmed in.." newline bitfld.long 0x8 19. "AC4T,Address cycle 4sequencer timings" "0: ADDC4 issued with the timings programmed in..,1: ADDC4 issued with the timings programmed in.." bitfld.long 0x8 18. "AC3T,Address cycle 3 sequencer timings" "0: ADDC3 issued with the timings programmed in..,1: ADDC3 issued with the timings programmed in.." newline bitfld.long 0x8 17. "AC2T,Address cycle 2 sequencer timings" "0: ADDC2 issued with the timings programmed in..,1: ADDC2 issued with the timings programmed in.." bitfld.long 0x8 16. "AC1T,Address cycle 1 sequencer timings" "0: ADDC1 issued with the timings programmed in..,1: ADDC1 issued with the timings programmed in.." newline hexmask.long.byte 0x8 8.--13. 1. "SNBR,Number of sectors to be read/written" line.long 0xC "FMC_CSQAR1,FMC NAND command sequencer address register 1" hexmask.long.byte 0xC 24.--31. 1. "ADDC4,Address Cycle 4" hexmask.long.byte 0xC 16.--23. 1. "ADDC3,Address Cycle 3" newline hexmask.long.byte 0xC 8.--15. 1. "ADDC2,Address Cycle 2" hexmask.long.byte 0xC 0.--7. 1. "ADDC1,Address Cycle 1" line.long 0x10 "FMC_CSQAR2,FMC NAND command sequencer address register 2" hexmask.long.word 0x10 16.--31. 1. "SAO,Spare Area Address Offset" hexmask.long.byte 0x10 0.--7. 1. "ADDC5,Address Cycle 5" group.long 0x220++0x7 line.long 0x0 "FMC_CSQIER,FMC NAND command sequencer interrupt enable register" bitfld.long 0x0 4. "CMDTCIE,Command Transfer Complete interrupt enable" "0: Command Transfer Complete Interrupt disable,1: Command Transfer Complete Interrupt enable" bitfld.long 0x0 3. "SUEIE,Sector Uncorrectable Error interrupt enable" "0: Command Transfer Complete Interrupt disable,1: Command Transfer Complete Interrupt enable" newline bitfld.long 0x0 2. "SEIE,Sector Error interrupt enable" "0: Sector Error Interrupt disable,1: Sector Error Interrupt enable" bitfld.long 0x0 1. "SCIE,Sector Complete interrupt enable" "0: Sector Complete Interrupt disable,1: Sector Complete Interrupt enable" newline bitfld.long 0x0 0. "TCIE,Transfer Complete Interrupt enable" "0: Transfer Complete Interrupt disable,1: Transfer Complete Interrupt enable" line.long 0x4 "FMC_CSQISR,FMC NAND command sequencer interrupt status register" bitfld.long 0x4 4. "CMDTCF,Command Transfer Complete flag" "0,1" bitfld.long 0x4 3. "SUEF,Sector Uncorrectable Error flag" "0,1" newline bitfld.long 0x4 2. "SEF,Sector Error flag" "0,1" bitfld.long 0x4 1. "SCF,Sector Complete flag" "0,1" newline bitfld.long 0x4 0. "TCF,Transfer Complete flag" "0,1" wgroup.long 0x228++0x3 line.long 0x0 "FMC_CSQICR,FMC NAND command sequencer interrupt clear register" bitfld.long 0x0 4. "CCMDTCF,Clear Command Transfer Complete flag" "0,1" bitfld.long 0x0 3. "CSUEF,Clear Sector uncorrectable Error flag" "0,1" newline bitfld.long 0x0 2. "CSEF,Clear Sector Error flag" "0,1" bitfld.long 0x0 1. "CSCF,Clear Sector Complete flag" "0,1" newline bitfld.long 0x0 0. "CTCF,Clear Transfer Complete flag" "0,1" rgroup.long 0x230++0x3 line.long 0x0 "FMC_CSQEMSR,FMC command sequencer error mapping status register" hexmask.long.word 0x0 0.--15. 1. "SEM,Sector Error mapping" group.long 0x250++0x3 line.long 0x0 "FMC_BCHIER,FMC BCH interrupt enable register" bitfld.long 0x0 4. "EPBRIE,Decoder Parity Bits Ready Interrupt enable" "0: Decoder Parity Bits Ready Interrupt disable,1: Decoder Parity Bits Ready Interrupt enable" bitfld.long 0x0 3. "DSRIE,Decoder Syndrome Ready Interrupt enable" "0: Decoder Syndrome Ready Interrupt disable,1: Decoder Syndrome Ready Interrupt enable" newline bitfld.long 0x0 2. "DEFIE,Decoder Error Found Interrupt enable" "0: Decoder Error Found Interrupt disable,1: Decoder Error Found Interrupt enable" bitfld.long 0x0 1. "DERIE,Decoder Error Ready Interrupt enable" "0: Decoder Error Ready Interrupt disable,1: Decoder Error Ready Interrupt enable" newline bitfld.long 0x0 0. "DUEIE,Decoder Uncorrectable Errors Interrupt enable" "0: Decoder Uncorrectable Errors Interrupt disable,1: Decoder Uncorrectable Errors Interrupt enable" rgroup.long 0x254++0x3 line.long 0x0 "FMC_BCHISR,FMC BCH interrupt and status register" bitfld.long 0x0 4. "EPBRF,Encoder Parity Bits Ready flag" "0,1" bitfld.long 0x0 3. "DSRF,Decoder Syndrome Ready flag" "0,1" newline bitfld.long 0x0 2. "DEFF,Decoder Error Found flag" "0,1" bitfld.long 0x0 1. "DERF,Decoder Error Ready flag" "0,1" newline bitfld.long 0x0 0. "DUEF,Decoder Uncorrectable Errors flag" "0,1" wgroup.long 0x258++0x3 line.long 0x0 "FMC_BCHICR,FMC BCH interrupt clear register" bitfld.long 0x0 4. "CEPBRF,Clear Encoder Parity Bits Ready flag" "0,1" bitfld.long 0x0 3. "CDSRF,Clear Decoder Syndrome Ready flag" "0,1" newline bitfld.long 0x0 2. "CDEFF,Clear Decoder Error Found flag" "0,1" bitfld.long 0x0 1. "CDERF,Clear Decoder Error ready flag" "0,1" newline bitfld.long 0x0 0. "CDUEF,Clear Decoder Uncorrectable Error flag" "0,1" rgroup.long 0x260++0xF line.long 0x0 "FMC_BCHPBR1,FMC BCH parity bits register 1" hexmask.long 0x0 0.--31. 1. "BCHPB,BCH parity bits" line.long 0x4 "FMC_BCHPBR2,FMC BCH parity bits register 2" hexmask.long 0x4 0.--31. 1. "BCHPB,BCH parity bits" line.long 0x8 "FMC_BCHPBR3,FMC BCH parity bits register 3" hexmask.long 0x8 0.--31. 1. "BCHPB,BCH parity bits" line.long 0xC "FMC_BCHPBR4,FMC BCH parity bits register 4" hexmask.long.byte 0xC 0.--7. 1. "BCHPB,BCH parity bits" rgroup.long 0x27C++0x13 line.long 0x0 "FMC_BCHDSR0,FMC BCH decoder status register 0" hexmask.long.byte 0x0 4.--7. 1. "DEN,Decoder error number" bitfld.long 0x0 1. "DEF,Decoder error found" "0,1" newline bitfld.long 0x0 0. "DUE,Decoder uncorrectable error" "0,1" line.long 0x4 "FMC_BCHDSR1,FMC BCH decoder status register for memory region 1" hexmask.long.word 0x4 16.--28. 1. "EBP2,Error bit position for error number 2" hexmask.long.word 0x4 0.--12. 1. "EBP1,Error bit position for error number 1" line.long 0x8 "FMC_BCHDSR2,FMC BCH decoder status register for memory region 2" hexmask.long.word 0x8 16.--28. 1. "EBP4,Error bit position for error number 4" hexmask.long.word 0x8 0.--12. 1. "EBP3,Error bit position for error number 3" line.long 0xC "FMC_BCHDSR3,FMC BCH decoder status register for memory region 3" hexmask.long.word 0xC 16.--28. 1. "EBP6,Error bit position for error number 6" hexmask.long.word 0xC 0.--12. 1. "EBP5,Error bit position for error number 5" line.long 0x10 "FMC_BCHDSR4,FMC BCH decoder status register for memory region 4" hexmask.long.word 0x10 16.--28. 1. "EBP8,Error bit position for error number 8" hexmask.long.word 0x10 0.--12. 1. "EBP7,Error bit position for error number 7" tree.end endif sif (cpuis("STM32N657*")) tree "FMC1_S" base ad:0x58024000 group.long 0x0++0x23 line.long 0x0 "FMC_BCR1,SRAM/NOR Flash chip-select control register for memory region 1" bitfld.long 0x0 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." bitfld.long 0x0 20.--21. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle,2: NEx deasserted after 64 fmc_ker_ck clock cycles,3: NEx deasserted after 256 fmc_ker_ck clock cycles" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." bitfld.long 0x0 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." bitfld.long 0x0 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." bitfld.long 0x0 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." bitfld.long 0x0 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" bitfld.long 0x0 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." bitfld.long 0x0 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x4 "FMC_BTR1,SRAM/NOR Flash chip-select timing registers for memory region 1" bitfld.long 0x4 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x4 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x8 "FMC_BCR2,SRAM/NOR Flash chip-select control register for memory region 2" bitfld.long 0x8 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." bitfld.long 0x8 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x8 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" bitfld.long 0x8 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." newline bitfld.long 0x8 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." newline bitfld.long 0x8 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" bitfld.long 0x8 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." newline bitfld.long 0x8 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." bitfld.long 0x8 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." newline bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." bitfld.long 0x8 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." newline bitfld.long 0x8 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." bitfld.long 0x8 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" newline bitfld.long 0x8 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." newline bitfld.long 0x8 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0xC "FMC_BTR2,SRAM/NOR Flash chip-select timing registers for memory region 2" bitfld.long 0xC 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0xC 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x10 "FMC_BCR3,SRAM/NOR Flash chip-select control register for memory region 3" bitfld.long 0x10 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." bitfld.long 0x10 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x10 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" bitfld.long 0x10 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." newline bitfld.long 0x10 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." newline bitfld.long 0x10 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" bitfld.long 0x10 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." newline bitfld.long 0x10 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." bitfld.long 0x10 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." newline bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." bitfld.long 0x10 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." newline bitfld.long 0x10 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." bitfld.long 0x10 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" newline bitfld.long 0x10 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." newline bitfld.long 0x10 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x14 "FMC_BTR3,SRAM/NOR Flash chip-select timing registers for memory region 3" bitfld.long 0x14 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x14 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x18 "FMC_BCR4,SRAM/NOR Flash chip-select control register for memory region 4" bitfld.long 0x18 22.--23. "NBLSET,Byte lane (NBL) setup" "0: NBL setup time is 0 fmc_ker_ck clock cycle.,1: NBL setup time is 1 fmc_ker_ck clock cycle.,2: NBL setup time is 2 fmc_ker_ck clock cycles.,3: NBL setup time is 3 fmc_ker_ck clock cycles." bitfld.long 0x18 21. "CSCOUNT1,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" newline bitfld.long 0x18 20. "CSCOUNT0,Chip Select (CS) counter" "0: Counter disabled,1: NEx deasserted after fmc_ker_ck clock cycle" bitfld.long 0x18 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in synchronous.." newline bitfld.long 0x18 16.--18. "CPSIZE,CRAM page size" "0: No burst split when crossing page boundary.,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1024 bytes,?,?,?" bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal not taken in to account during..,1: NWAIT signal taken in to account during.." newline bitfld.long 0x18 14. "EXTMOD,Extended mode enable" "0: Values inside FMC_BWTR register not taken into..,1: Values inside FMC_BWTR register taken into account" bitfld.long 0x18 13. "WAITEN,Wait enable bit" "0: NWAIT signal disabled (its level not taken into..,1: NWAIT signal enabled (its level is taken into.." newline bitfld.long 0x18 12. "WREN,Write enable bit" "0: Write operations to the memory region by the FMC..,1: Write operations to the memory region by the FMC.." bitfld.long 0x18 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal active one data cycle before wait..,1: NWAIT signal active during wait state (not used.." newline bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high." bitfld.long 0x18 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.." newline bitfld.long 0x18 6. "FACCEN,Flash memory access enable" "0: Corresponding NOR Flash memory access is disabled,1: Corresponding NOR Flash memory access is enabled.." bitfld.long 0x18 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,?" newline bitfld.long 0x18 2.--3. "MTYP,Memory type" "0: SRAM/ FRAM (default after reset for memory..,1: PSRAM (CRAM)/FRAM,2: NOR Flash/OneNAND Flash (default after reset for..,?" bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.." newline bitfld.long 0x18 0. "MBKEN,Memory region enable bit" "0: Corresponding memory region is disabled,1: Corresponding memory region is enabled" line.long 0x1C "FMC_BTR4,SRAM/NOR Flash chip-select timing registers for memory region 4" bitfld.long 0x1C 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = fmc_ker_ck clock cycle..,1: DATAHLD phase duration = fmc_ker_ck clock cycle..,2: DATAHLD phase duration = fmc_ker_ck clock cycle..,3: DATAHLD phase duration = fmc_ker_ck clock cycle.." bitfld.long 0x1C 28.--29. "ACCMOD,Access mode" "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory (see note below bit descriptions)" hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" newline hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration" newline hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration" hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration" line.long 0x20 "FMC_CFGR,FMC common configuration register" bitfld.long 0x20 31. "FMCEN,FMC controller enable" "0: FMC controller disabled,1: FMC controller enabled" bitfld.long 0x20 25. "BMAP1,FMC memory region mapping" "0: Default mapping (refer to Table 132),1: Devices are remapped (refer to Table 133)" newline bitfld.long 0x20 24. "BMAP0,FMC memory region mapping" "0: Default mapping (refer to Table 132),1: Devices are remapped (refer to Table 133)" bitfld.long 0x20 20. "CCLKEN,Continuous clock enable" "0: The FMC_CLK is only generated during the..,1: The FMC_CLK is generated continuously during.." newline hexmask.long.byte 0x20 16.--19. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" group.long 0x80++0x3 line.long 0x0 "FMC_PCR,NAND Flash programmable control register" bitfld.long 0x0 25. "WEN,Write enable" "0: Read access enabled,1: Write access enabled" bitfld.long 0x0 24. "BCHECC,BCH error correction capability" "0: 4-bit BCH (4-bit error correction and 8-bit..,1: 8-bit BCH (8-bit error correction and 16-bit.." newline bitfld.long 0x0 17.--19. "ECCSS,ECC sector size (used to access spare area)" "0: 256 bytes,1: 512 bytes,2: 1024 bytes,3: 2048 bytes (default),4: 4096 bytes,?,?,?" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay." newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay." bitfld.long 0x0 8. "ECCALG,ECC algorithm" "0: Hamming code is selected (default).,1: BCH code is selected." newline bitfld.long 0x0 6. "ECCEN,ECC computation logic enable bit" "0: ECC logic is disabled and reset (default after..,1: ECC logic is enabled." bitfld.long 0x0 4.--5. "PWID,Data bus width" "0: 8 bits (default after reset).,1: 16 bits,?,?" newline bitfld.long 0x0 2. "PBKEN,NAND Flash memory region enable bit" "0: Corresponding memory region is disabled (default..,1: Corresponding memory region is enabled." bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit" "0: disabled (default),1: enabled" rgroup.long 0x84++0x3 line.long 0x0 "FMC_SR,FMC status register" bitfld.long 0x0 6. "NWRF,NAND write request flag" "0: NAND Flash write requests are pending,1: No NAND Flash write requests pending" bitfld.long 0x0 4. "PEF,Pipe Empty Flag" "0,1" newline bitfld.long 0x0 0.--1. "ISOST,FMC isolation state with respect to the AXI interface" "0: FMC is not isolated; AXI transactions are..,1: FMC has been enabled (FMCEN = 1) and waits for..,2: FMC has been disabled (FMCEN = 0) and waits for..,3: FMC is isolated from its AXI interface. All AXI.." group.long 0x88++0x7 line.long 0x0 "FMC_PMEM,FMC common memory space timing register" hexmask.long.byte 0x0 24.--31. 1. "MEMHIZ,Common memory data bus Hi-Z time" hexmask.long.byte 0x0 16.--23. 1. "MEMHOLD,Common memory hold time" newline hexmask.long.byte 0x0 8.--15. 1. "MEMWAIT,Common memory wait time" hexmask.long.byte 0x0 0.--7. 1. "MEMSET,Common memory setup time" line.long 0x4 "FMC_PATT,FMC attribute memory space timing registers" hexmask.long.byte 0x4 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0x4 16.--23. 1. "ATTHOLD,Attribute memory hold time" newline hexmask.long.byte 0x4 8.--15. 1. "ATTWAIT,Attribute memory wait time" hexmask.long.byte 0x4 0.--7. 1. "ATTSET,Attribute memory setup time" rgroup.long 0x90++0x7 line.long 0x0 "FMC_HPR,FMC Hamming parity result registers" hexmask.long 0x0 0.--31. 1. "HPR,Hamming parity result" line.long 0x4 "FMC_HECCR,FMC Hamming code ECC result register" hexmask.long 0x4 0.--31. 1. "HECC,ECC result" group.long 0x104++0x3 line.long 0x0 "FMC_BWTR1,SRAM/NOR-Flash write timing registers for memory region 1" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x10C++0x3 line.long 0x0 "FMC_BWTR2,SRAM/NOR-Flash write timing registers for memory region 2" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x114++0x3 line.long 0x0 "FMC_BWTR3,SRAM/NOR-Flash write timing registers for memory region 3" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x11C++0x3 line.long 0x0 "FMC_BWTR4,SRAM/NOR-Flash write timing registers for memory region 4" bitfld.long 0x0 30.--31. "DATAHLD,Data Hold phase duration" "0: DATAHLD phase duration = 1 * fmc_ker_ck clock..,1: DATAHLD phase duration = 2 * fmc_ker_ck clock..,2: DATAHLD phase duration = 3 * fmc_ker_ck clock..,3: DATAHLD phase duration = 4 * fmc_ker_ck clock.." bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: Access mode A,1: Access mode B,2: Access mode C,3: Access mode D" newline hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration" hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration." newline hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration." hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration." group.long 0x140++0xB line.long 0x0 "FMC_SDCR1,SDRAM control registers for SDRAM device 1" bitfld.long 0x0 17. "SDINIT,SDRAM device initialization" "0: Initialization is not complete the AXI accesses..,1: Initialization is complete and the device is.." bitfld.long 0x0 16. "SDEN,SDRAM device enable" "0: SDRAM disabled,1: SDRAM device enabled" newline bitfld.long 0x0 13.--14. "RPIPE,Read pipe" "0: No fmc_ker_ck clock cycle delay (default value),1: One fmc_ker_ck clock cycle delay,2: Two fmc_ker_ck clock cycle delay,?" bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration" "0: SDCLK clock disabled,1: SDCLK period = 1 * fmc_ker_ck period,2: SDCLK period = 2 * fmc_ker_ck periods,3: SDCLK period = 3 * fmc_ker_ck periods" newline bitfld.long 0x0 9. "WP,Write protection" "0: Write accesses allowed,1: Write accesses ignored" bitfld.long 0x0 7.--8. "CAS,CAS Latency" "?,1: 1 cycle,2: 2 cycles,3: 3 cycles" newline bitfld.long 0x0 6. "NB,Number of banks" "0: Two banks,1: Four banks" bitfld.long 0x0 4.--5. "MWID,Memory data bus width." "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x0 2.--3. "NR,Number of row address bits" "0: 11 bit,1: 12 bits,2: 13 bits,?" bitfld.long 0x0 0.--1. "NC,Number of column address bits" "0: 8 bits,1: 9 bits,2: 10 bits,3: 11 bits." line.long 0x4 "FMC_SDCR2,SDRAM control registers for SDRAM device 2" bitfld.long 0x4 17. "SDINIT,SDRAM device initialization" "0: Initialization is not complete the AXI accesses..,1: Initialization is complete and the device is.." bitfld.long 0x4 16. "SDEN,SDRAM device enable" "0: SDRAM disabled,1: SDRAM device enabled" newline bitfld.long 0x4 9. "WP,Write protection" "0: Write accesses allowed,1: Write accesses ignored" bitfld.long 0x4 7.--8. "CAS,CAS Latency" "?,1: 1 cycle,2: 2 cycles,3: 3 cycles" newline bitfld.long 0x4 6. "NB,Number of banks" "0: Two banks,1: Four banks" bitfld.long 0x4 4.--5. "MWID,Memory data bus width." "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x4 2.--3. "NR,Number of row address bits" "0: 11 bit,1: 12 bits,2: 13 bits,?" bitfld.long 0x4 0.--1. "NC,Number of column address bits" "0: 8 bits,1: 9 bits,2: 10 bits,3: 11 bits." line.long 0x8 "FMC_SDTR,SDRAM timing register" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self-refresh time" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit self-refresh delay" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load mode register to active" group.long 0x150++0x7 line.long 0x0 "FMC_SDCMR,SDRAM command mode register" hexmask.long.word 0x0 9.--22. 1. "MRD,Mode register definition" hexmask.long.byte 0x0 5.--8. 1. "NRFS,Number of Refresh commands" newline bitfld.long 0x0 4. "DS1,Command targeting SDRAM device 1" "0: Command not issued to SDRAM device 1,1: Command issued to SDRAM device 1" bitfld.long 0x0 3. "DS2,Command targeting SDRAM device 2" "0: Command not issued to SDRAM device 2,1: Command issued to SDRAM device 2" newline bitfld.long 0x0 0.--2. "MODE,Command mode" "0: Normal mode command (NRM),?,2: Precharge all banks command (PALL),3: Refresh command (REF),4: Load mode register command (LMR),5: Self-refresh command (SR),6: Power-down command (PD),?" line.long 0x4 "FMC_SDRTR,SDRAM refresh timer register" bitfld.long 0x4 14. "REIE,RES Interrupt Enable" "0: Interrupt is disabled,1: An Interrupt is generated if RE = 1" hexmask.long.word 0x4 1.--13. 1. "RFSCNT,Refresh Timer Count" newline bitfld.long 0x4 0. "CRE,Clear Refresh error flag" "0: no effect,1: Refresh Error flag is cleared" rgroup.long 0x158++0x3 line.long 0x0 "FMC_SDSR,SDRAM status register" bitfld.long 0x0 15. "CMDOK,Previous command status" "0: Command not complete,1: Command complete in the SDRAM clock domain" bitfld.long 0x0 3.--4. "MODES2,Status mode for SDRAM device 2" "0: Normal mode devices are not in Self-refresh or..,1: Self-refresh,2: Power-down,?" newline bitfld.long 0x0 1.--2. "MODES1,Status Mode for SDRAM device 1" "0: Normal mode devices are not in Self-refresh or..,1: Self-refresh,2: Power-down,?" bitfld.long 0x0 0. "RE,Refresh error flag" "0: No refresh error has been detected,1: A refresh error has been detected" group.long 0x180++0x3 line.long 0x0 "FMC_IER,FMC NAND interrupt enable register" bitfld.long 0x0 2. "IFEE,Interrupt falling edge detection enable bit" "0: Interrupt falling edge detection request disabled,1: Interrupt falling edge detection request enabled" bitfld.long 0x0 1. "IHLE,Interrupt high-level detection enable bit" "0: Interrupt high-level detection request disabled,1: Interrupt high-level detection request enabled" newline bitfld.long 0x0 0. "IREE,Interrupt rising edge detection enable bit" "0: Interrupt rising edge detection request disabled,1: Interrupt rising edge detection request enabled" rgroup.long 0x184++0x3 line.long 0x0 "FMC_ISR,FMC controller interrupt status register" bitfld.long 0x0 2. "IFEF,Interrupt falling edge flag" "0: No interrupt falling edge occurred,1: Interrupt falling edge occurred" bitfld.long 0x0 1. "IHLF,Interrupt high-level flag" "0: No Interrupt high-level occurred,1: Interrupt high-level occurred" newline bitfld.long 0x0 0. "IREF,Interrupt rising edge flag" "0: No interrupt rising edge occurred,1: Interrupt rising edge occurred" wgroup.long 0x188++0x3 line.long 0x0 "FMC_ICR,FMC NAND controller interrupt clear register" bitfld.long 0x0 2. "CIFEF,Clear Interrupt falling edge flag" "0: No effect,1: Clears the IFEF flag in the FMC_ISR register" bitfld.long 0x0 1. "CIHLF,Clear Interrupt high-level flag" "0: No effect,1: Clears the IHLF flag in the FMC_ISR register" newline bitfld.long 0x0 0. "CIREF,Clear Interrupt rising edge flag" "0: No effect,1: Clear the IREF flag in the FMC_ISR register" wgroup.long 0x200++0x3 line.long 0x0 "FMC_CSQCR,FMC NAND command sequencer control register" bitfld.long 0x0 0. "CSQSTART,Command Sequencer Enable" "0,1" group.long 0x204++0x13 line.long 0x0 "FMC_CSQCFGR1,FMC NAND command sequencer configuration register 1" bitfld.long 0x0 25. "CMD2T,Command 2 Sequencer timings" "0: CMD2 issued with the timings programmed in..,1: CMD2 issued with the timings programmed in.." bitfld.long 0x0 24. "CMD1T,Command 1 Sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." newline hexmask.long.byte 0x0 16.--23. 1. "CMD2,Command 2 sequencer" hexmask.long.byte 0x0 8.--15. 1. "CMD1,Command 1 sequencer" newline bitfld.long 0x0 4.--6. "ACYNBR,Address Cycle number" "0: No address cycle.,1: 1 address cycle,2: 2 address cycles,3: 3 address cycles,4: 4 address cycles,5: 5 address cycles,?,?" bitfld.long 0x0 2. "DMADEN,Command sequencer DMA request data enable" "0: No DMA request transfer,1: A DMA request transfer" newline bitfld.long 0x0 1. "CMD2EN,Command cycle 2 Enable" "0: Command cycle 2 not issued.,1: Command cycle 2 (programmed CMD2[7:0]) sent by.." line.long 0x4 "FMC_CSQCFGR2,FMC NAND command sequencer configuration register 2" bitfld.long 0x4 25. "RCMD2T,Command 1 sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." bitfld.long 0x4 24. "RCMD1T,Command 1 sequencer timings" "0: CMD1 issued with the timings programmed in..,1: CMD1 issued with the timings programmed in.." newline hexmask.long.byte 0x4 16.--23. 1. "RCMD2,Random Command 2 sequencer" hexmask.long.byte 0x4 8.--15. 1. "RCMD1,Random Command 1 sequencer" newline bitfld.long 0x4 2. "DMASEN,Command sequencer DMA request decoding status enable" "0: No DMA request used for ECC status registers..,1: A DMA request used for ECC status registers.." bitfld.long 0x4 1. "RCMD2EN,Random Command 2 sequencer enable" "0: Command 2 not issued.,1: Command 2 (CMD2SQ[7:0]) issued by the command.." newline bitfld.long 0x4 0. "SQSDTEN,Sequencer spare data transfer enable" "0: ECC disabled and spare data area not accessed by..,1: ECC enabled and spare data area read or.." line.long 0x8 "FMC_CSQCFGR3,FMC NAND sequencer configuration register 3" bitfld.long 0x8 23. "RAC2T,Random Address cycle 2 sequencer timings" "0: Random ADDC2 issued with the timings programmed..,1: Random ADDC2 issued with the timings programmed.." bitfld.long 0x8 22. "RAC1T,Random Address cycle 1 sequencer timings" "0: Random ADDC1 issued with the timings programmed..,1: Random ADDC1 issued with the timings programmed.." newline bitfld.long 0x8 21. "SDT,Spare data transfer sequencer timings" "0: Spare data transfer issued with the timings..,1: Spare data transfer issued with the timings.." bitfld.long 0x8 20. "AC5T,Address cycle 5 sequencer timings" "0: ADDC5 issued with the timings programmed in..,1: ADDC5 issued with the timings programmed in.." newline bitfld.long 0x8 19. "AC4T,Address cycle 4sequencer timings" "0: ADDC4 issued with the timings programmed in..,1: ADDC4 issued with the timings programmed in.." bitfld.long 0x8 18. "AC3T,Address cycle 3 sequencer timings" "0: ADDC3 issued with the timings programmed in..,1: ADDC3 issued with the timings programmed in.." newline bitfld.long 0x8 17. "AC2T,Address cycle 2 sequencer timings" "0: ADDC2 issued with the timings programmed in..,1: ADDC2 issued with the timings programmed in.." bitfld.long 0x8 16. "AC1T,Address cycle 1 sequencer timings" "0: ADDC1 issued with the timings programmed in..,1: ADDC1 issued with the timings programmed in.." newline hexmask.long.byte 0x8 8.--13. 1. "SNBR,Number of sectors to be read/written" line.long 0xC "FMC_CSQAR1,FMC NAND command sequencer address register 1" hexmask.long.byte 0xC 24.--31. 1. "ADDC4,Address Cycle 4" hexmask.long.byte 0xC 16.--23. 1. "ADDC3,Address Cycle 3" newline hexmask.long.byte 0xC 8.--15. 1. "ADDC2,Address Cycle 2" hexmask.long.byte 0xC 0.--7. 1. "ADDC1,Address Cycle 1" line.long 0x10 "FMC_CSQAR2,FMC NAND command sequencer address register 2" hexmask.long.word 0x10 16.--31. 1. "SAO,Spare Area Address Offset" hexmask.long.byte 0x10 0.--7. 1. "ADDC5,Address Cycle 5" group.long 0x220++0x7 line.long 0x0 "FMC_CSQIER,FMC NAND command sequencer interrupt enable register" bitfld.long 0x0 4. "CMDTCIE,Command Transfer Complete interrupt enable" "0: Command Transfer Complete Interrupt disable,1: Command Transfer Complete Interrupt enable" bitfld.long 0x0 3. "SUEIE,Sector Uncorrectable Error interrupt enable" "0: Command Transfer Complete Interrupt disable,1: Command Transfer Complete Interrupt enable" newline bitfld.long 0x0 2. "SEIE,Sector Error interrupt enable" "0: Sector Error Interrupt disable,1: Sector Error Interrupt enable" bitfld.long 0x0 1. "SCIE,Sector Complete interrupt enable" "0: Sector Complete Interrupt disable,1: Sector Complete Interrupt enable" newline bitfld.long 0x0 0. "TCIE,Transfer Complete Interrupt enable" "0: Transfer Complete Interrupt disable,1: Transfer Complete Interrupt enable" line.long 0x4 "FMC_CSQISR,FMC NAND command sequencer interrupt status register" bitfld.long 0x4 4. "CMDTCF,Command Transfer Complete flag" "0,1" bitfld.long 0x4 3. "SUEF,Sector Uncorrectable Error flag" "0,1" newline bitfld.long 0x4 2. "SEF,Sector Error flag" "0,1" bitfld.long 0x4 1. "SCF,Sector Complete flag" "0,1" newline bitfld.long 0x4 0. "TCF,Transfer Complete flag" "0,1" wgroup.long 0x228++0x3 line.long 0x0 "FMC_CSQICR,FMC NAND command sequencer interrupt clear register" bitfld.long 0x0 4. "CCMDTCF,Clear Command Transfer Complete flag" "0,1" bitfld.long 0x0 3. "CSUEF,Clear Sector uncorrectable Error flag" "0,1" newline bitfld.long 0x0 2. "CSEF,Clear Sector Error flag" "0,1" bitfld.long 0x0 1. "CSCF,Clear Sector Complete flag" "0,1" newline bitfld.long 0x0 0. "CTCF,Clear Transfer Complete flag" "0,1" rgroup.long 0x230++0x3 line.long 0x0 "FMC_CSQEMSR,FMC command sequencer error mapping status register" hexmask.long.word 0x0 0.--15. 1. "SEM,Sector Error mapping" group.long 0x250++0x3 line.long 0x0 "FMC_BCHIER,FMC BCH interrupt enable register" bitfld.long 0x0 4. "EPBRIE,Decoder Parity Bits Ready Interrupt enable" "0: Decoder Parity Bits Ready Interrupt disable,1: Decoder Parity Bits Ready Interrupt enable" bitfld.long 0x0 3. "DSRIE,Decoder Syndrome Ready Interrupt enable" "0: Decoder Syndrome Ready Interrupt disable,1: Decoder Syndrome Ready Interrupt enable" newline bitfld.long 0x0 2. "DEFIE,Decoder Error Found Interrupt enable" "0: Decoder Error Found Interrupt disable,1: Decoder Error Found Interrupt enable" bitfld.long 0x0 1. "DERIE,Decoder Error Ready Interrupt enable" "0: Decoder Error Ready Interrupt disable,1: Decoder Error Ready Interrupt enable" newline bitfld.long 0x0 0. "DUEIE,Decoder Uncorrectable Errors Interrupt enable" "0: Decoder Uncorrectable Errors Interrupt disable,1: Decoder Uncorrectable Errors Interrupt enable" rgroup.long 0x254++0x3 line.long 0x0 "FMC_BCHISR,FMC BCH interrupt and status register" bitfld.long 0x0 4. "EPBRF,Encoder Parity Bits Ready flag" "0,1" bitfld.long 0x0 3. "DSRF,Decoder Syndrome Ready flag" "0,1" newline bitfld.long 0x0 2. "DEFF,Decoder Error Found flag" "0,1" bitfld.long 0x0 1. "DERF,Decoder Error Ready flag" "0,1" newline bitfld.long 0x0 0. "DUEF,Decoder Uncorrectable Errors flag" "0,1" wgroup.long 0x258++0x3 line.long 0x0 "FMC_BCHICR,FMC BCH interrupt clear register" bitfld.long 0x0 4. "CEPBRF,Clear Encoder Parity Bits Ready flag" "0,1" bitfld.long 0x0 3. "CDSRF,Clear Decoder Syndrome Ready flag" "0,1" newline bitfld.long 0x0 2. "CDEFF,Clear Decoder Error Found flag" "0,1" bitfld.long 0x0 1. "CDERF,Clear Decoder Error ready flag" "0,1" newline bitfld.long 0x0 0. "CDUEF,Clear Decoder Uncorrectable Error flag" "0,1" rgroup.long 0x260++0xF line.long 0x0 "FMC_BCHPBR1,FMC BCH parity bits register 1" hexmask.long 0x0 0.--31. 1. "BCHPB,BCH parity bits" line.long 0x4 "FMC_BCHPBR2,FMC BCH parity bits register 2" hexmask.long 0x4 0.--31. 1. "BCHPB,BCH parity bits" line.long 0x8 "FMC_BCHPBR3,FMC BCH parity bits register 3" hexmask.long 0x8 0.--31. 1. "BCHPB,BCH parity bits" line.long 0xC "FMC_BCHPBR4,FMC BCH parity bits register 4" hexmask.long.byte 0xC 0.--7. 1. "BCHPB,BCH parity bits" rgroup.long 0x27C++0x13 line.long 0x0 "FMC_BCHDSR0,FMC BCH decoder status register 0" hexmask.long.byte 0x0 4.--7. 1. "DEN,Decoder error number" bitfld.long 0x0 1. "DEF,Decoder error found" "0,1" newline bitfld.long 0x0 0. "DUE,Decoder uncorrectable error" "0,1" line.long 0x4 "FMC_BCHDSR1,FMC BCH decoder status register for memory region 1" hexmask.long.word 0x4 16.--28. 1. "EBP2,Error bit position for error number 2" hexmask.long.word 0x4 0.--12. 1. "EBP1,Error bit position for error number 1" line.long 0x8 "FMC_BCHDSR2,FMC BCH decoder status register for memory region 2" hexmask.long.word 0x8 16.--28. 1. "EBP4,Error bit position for error number 4" hexmask.long.word 0x8 0.--12. 1. "EBP3,Error bit position for error number 3" line.long 0xC "FMC_BCHDSR3,FMC BCH decoder status register for memory region 3" hexmask.long.word 0xC 16.--28. 1. "EBP6,Error bit position for error number 6" hexmask.long.word 0xC 0.--12. 1. "EBP5,Error bit position for error number 5" line.long 0x10 "FMC_BCHDSR4,FMC BCH decoder status register for memory region 4" hexmask.long.word 0x10 16.--28. 1. "EBP8,Error bit position for error number 8" hexmask.long.word 0x10 0.--12. 1. "EBP7,Error bit position for error number 7" tree.end endif tree.end tree "GFXMMU (Chrom-GRC)" base ad:0x0 tree "GFXMMU" base ad:0x48030000 group.long 0x0++0x3 line.long 0x0 "GFXMMU_CR,GFXMMU configuration register" bitfld.long 0x0 31. "B3PM,Buffer 3 packing mode" "0: MSB is removed,1: LSB is removed" bitfld.long 0x0 30. "B3PE,Buffer 3 packing enable" "0: Packing is disabled,1: Packing is enable" bitfld.long 0x0 29. "B2PM,Buffer 2 packing mode" "0: MSB is removed,1: LSB is removed" newline bitfld.long 0x0 28. "B2PE,Buffer 2 packing enable" "0: Packing is disabled,1: Packing is enable" bitfld.long 0x0 27. "B1PM,Buffer 1 packing mode" "0: MSB is removed,1: LSB is removed" bitfld.long 0x0 26. "B1PE,Buffer 1 packing enable" "0: Packing is disabled,1: Packing is enable" newline bitfld.long 0x0 25. "B0PM,Buffer 0 packing mode" "0: MSB is removed,1: LSB is removed" bitfld.long 0x0 24. "B0PE,Buffer 0 packing enable" "0: Packing is disabled,1: Packing is enable" bitfld.long 0x0 15. "ATE,Address translation enable" "0: Address translation is disable,1: Address translation is enable" newline bitfld.long 0x0 6. "BS,Block size" "0: 16-byte blocks,1: 12-byte blocks" bitfld.long 0x0 4. "AMEIE,AXI master error interrupt enable" "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 3. "B3OIE,Buffer 3 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" newline bitfld.long 0x0 2. "B2OIE,Buffer 2 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 1. "B1OIE,Buffer 1 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 0. "B0OIE,Buffer 0 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" rgroup.long 0x4++0x3 line.long 0x0 "GFXMMU_SR,GFXMMU status register" bitfld.long 0x0 4. "AMEF,AXI master error flag" "0,1" bitfld.long 0x0 3. "B3OF,Buffer 3 overflow flag" "0,1" bitfld.long 0x0 2. "B2OF,Buffer 2 overflow flag" "0,1" newline bitfld.long 0x0 1. "B1OF,Buffer 1 overflow flag" "0,1" bitfld.long 0x0 0. "B0OF,Buffer 0 overflow flag" "0,1" group.long 0x8++0x3 line.long 0x0 "GFXMMU_FCR,GFXMMU flag clear register" bitfld.long 0x0 4. "CAMEF,Clear AXI master error flag" "0,1" bitfld.long 0x0 3. "CB3OF,Clear buffer 3 overflow flag" "0,1" bitfld.long 0x0 2. "CB2OF,Clear buffer 2 overflow flag" "0,1" newline bitfld.long 0x0 1. "CB1OF,Clear buffer 1 overflow flag" "0,1" bitfld.long 0x0 0. "CB0OF,Clear buffer 0 overflow flag" "0,1" group.long 0x10++0x7 line.long 0x0 "GFXMMU_DVR,GFXMMU default value register" hexmask.long 0x0 0.--31. 1. "DV,Default value" line.long 0x4 "GFXMMU_DAR,GFXMMU default alpha register" hexmask.long.byte 0x4 0.--7. 1. "DA,Default alpha" group.long 0x20++0xF line.long 0x0 "GFXMMU_B0CR,GFXMMU buffer 0 configuration register" hexmask.long.word 0x0 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x0 4.--22. 1. "PBO,Physical buffer offset" line.long 0x4 "GFXMMU_B1CR,GFXMMU buffer 1 configuration register" hexmask.long.word 0x4 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x4 4.--22. 1. "PBO,Physical buffer offset" line.long 0x8 "GFXMMU_B2CR,GFXMMU buffer 2 configuration register" hexmask.long.word 0x8 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x8 4.--22. 1. "PBO,Physical buffer offset" line.long 0xC "GFXMMU_B3CR,GFXMMU buffer 3 configuration register" hexmask.long.word 0xC 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0xC 4.--22. 1. "PBO,Physical buffer offset" group.long 0x1000++0xFFF line.long 0x0 "GFXMMU_LUT0L,GFXMMU LUT entry 0 low" hexmask.long.byte 0x0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x0 8.--15. 1. "FVB,First valid block" bitfld.long 0x0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4 "GFXMMU_LUT0H,GFXMMU LUT entry 0 high" hexmask.long.tbyte 0x4 0.--17. 1. "LO,Line offset" line.long 0x8 "GFXMMU_LUT1L,GFXMMU LUT entry 1 low" hexmask.long.byte 0x8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC "GFXMMU_LUT1H,GFXMMU LUT entry 1 high" hexmask.long.tbyte 0xC 0.--17. 1. "LO,Line offset" line.long 0x10 "GFXMMU_LUT2L,GFXMMU LUT entry 2 low" hexmask.long.byte 0x10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x10 8.--15. 1. "FVB,First valid block" bitfld.long 0x10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14 "GFXMMU_LUT2H,GFXMMU LUT entry 2 high" hexmask.long.tbyte 0x14 0.--17. 1. "LO,Line offset" line.long 0x18 "GFXMMU_LUT3L,GFXMMU LUT entry 3 low" hexmask.long.byte 0x18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x18 8.--15. 1. "FVB,First valid block" bitfld.long 0x18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C "GFXMMU_LUT3H,GFXMMU LUT entry 3 high" hexmask.long.tbyte 0x1C 0.--17. 1. "LO,Line offset" line.long 0x20 "GFXMMU_LUT4L,GFXMMU LUT entry 4 low" hexmask.long.byte 0x20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x20 8.--15. 1. "FVB,First valid block" bitfld.long 0x20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24 "GFXMMU_LUT4H,GFXMMU LUT entry 4 high" hexmask.long.tbyte 0x24 0.--17. 1. "LO,Line offset" line.long 0x28 "GFXMMU_LUT5L,GFXMMU LUT entry 5 low" hexmask.long.byte 0x28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x28 8.--15. 1. "FVB,First valid block" bitfld.long 0x28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C "GFXMMU_LUT5H,GFXMMU LUT entry 5 high" hexmask.long.tbyte 0x2C 0.--17. 1. "LO,Line offset" line.long 0x30 "GFXMMU_LUT6L,GFXMMU LUT entry 6 low" hexmask.long.byte 0x30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x30 8.--15. 1. "FVB,First valid block" bitfld.long 0x30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34 "GFXMMU_LUT6H,GFXMMU LUT entry 6 high" hexmask.long.tbyte 0x34 0.--17. 1. "LO,Line offset" line.long 0x38 "GFXMMU_LUT7L,GFXMMU LUT entry 7 low" hexmask.long.byte 0x38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x38 8.--15. 1. "FVB,First valid block" bitfld.long 0x38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C "GFXMMU_LUT7H,GFXMMU LUT entry 7 high" hexmask.long.tbyte 0x3C 0.--17. 1. "LO,Line offset" line.long 0x40 "GFXMMU_LUT8L,GFXMMU LUT entry 8 low" hexmask.long.byte 0x40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x40 8.--15. 1. "FVB,First valid block" bitfld.long 0x40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44 "GFXMMU_LUT8H,GFXMMU LUT entry 8 high" hexmask.long.tbyte 0x44 0.--17. 1. "LO,Line offset" line.long 0x48 "GFXMMU_LUT9L,GFXMMU LUT entry 9 low" hexmask.long.byte 0x48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x48 8.--15. 1. "FVB,First valid block" bitfld.long 0x48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C "GFXMMU_LUT9H,GFXMMU LUT entry 9 high" hexmask.long.tbyte 0x4C 0.--17. 1. "LO,Line offset" line.long 0x50 "GFXMMU_LUT10L,GFXMMU LUT entry 10 low" hexmask.long.byte 0x50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x50 8.--15. 1. "FVB,First valid block" bitfld.long 0x50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54 "GFXMMU_LUT10H,GFXMMU LUT entry 10 high" hexmask.long.tbyte 0x54 0.--17. 1. "LO,Line offset" line.long 0x58 "GFXMMU_LUT11L,GFXMMU LUT entry 11 low" hexmask.long.byte 0x58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x58 8.--15. 1. "FVB,First valid block" bitfld.long 0x58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C "GFXMMU_LUT11H,GFXMMU LUT entry 11 high" hexmask.long.tbyte 0x5C 0.--17. 1. "LO,Line offset" line.long 0x60 "GFXMMU_LUT12L,GFXMMU LUT entry 12 low" hexmask.long.byte 0x60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x60 8.--15. 1. "FVB,First valid block" bitfld.long 0x60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64 "GFXMMU_LUT12H,GFXMMU LUT entry 12 high" hexmask.long.tbyte 0x64 0.--17. 1. "LO,Line offset" line.long 0x68 "GFXMMU_LUT13L,GFXMMU LUT entry 13 low" hexmask.long.byte 0x68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x68 8.--15. 1. "FVB,First valid block" bitfld.long 0x68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C "GFXMMU_LUT13H,GFXMMU LUT entry 13 high" hexmask.long.tbyte 0x6C 0.--17. 1. "LO,Line offset" line.long 0x70 "GFXMMU_LUT14L,GFXMMU LUT entry 14 low" hexmask.long.byte 0x70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x70 8.--15. 1. "FVB,First valid block" bitfld.long 0x70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74 "GFXMMU_LUT14H,GFXMMU LUT entry 14 high" hexmask.long.tbyte 0x74 0.--17. 1. "LO,Line offset" line.long 0x78 "GFXMMU_LUT15L,GFXMMU LUT entry 15 low" hexmask.long.byte 0x78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x78 8.--15. 1. "FVB,First valid block" bitfld.long 0x78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C "GFXMMU_LUT15H,GFXMMU LUT entry 15 high" hexmask.long.tbyte 0x7C 0.--17. 1. "LO,Line offset" line.long 0x80 "GFXMMU_LUT16L,GFXMMU LUT entry 16 low" hexmask.long.byte 0x80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x80 8.--15. 1. "FVB,First valid block" bitfld.long 0x80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84 "GFXMMU_LUT16H,GFXMMU LUT entry 16 high" hexmask.long.tbyte 0x84 0.--17. 1. "LO,Line offset" line.long 0x88 "GFXMMU_LUT17L,GFXMMU LUT entry 17 low" hexmask.long.byte 0x88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x88 8.--15. 1. "FVB,First valid block" bitfld.long 0x88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C "GFXMMU_LUT17H,GFXMMU LUT entry 17 high" hexmask.long.tbyte 0x8C 0.--17. 1. "LO,Line offset" line.long 0x90 "GFXMMU_LUT18L,GFXMMU LUT entry 18 low" hexmask.long.byte 0x90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x90 8.--15. 1. "FVB,First valid block" bitfld.long 0x90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94 "GFXMMU_LUT18H,GFXMMU LUT entry 18 high" hexmask.long.tbyte 0x94 0.--17. 1. "LO,Line offset" line.long 0x98 "GFXMMU_LUT19L,GFXMMU LUT entry 19 low" hexmask.long.byte 0x98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x98 8.--15. 1. "FVB,First valid block" bitfld.long 0x98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C "GFXMMU_LUT19H,GFXMMU LUT entry 19 high" hexmask.long.tbyte 0x9C 0.--17. 1. "LO,Line offset" line.long 0xA0 "GFXMMU_LUT20L,GFXMMU LUT entry 20 low" hexmask.long.byte 0xA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4 "GFXMMU_LUT20H,GFXMMU LUT entry 20 high" hexmask.long.tbyte 0xA4 0.--17. 1. "LO,Line offset" line.long 0xA8 "GFXMMU_LUT21L,GFXMMU LUT entry 21 low" hexmask.long.byte 0xA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC "GFXMMU_LUT21H,GFXMMU LUT entry 21 high" hexmask.long.tbyte 0xAC 0.--17. 1. "LO,Line offset" line.long 0xB0 "GFXMMU_LUT22L,GFXMMU LUT entry 22 low" hexmask.long.byte 0xB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4 "GFXMMU_LUT22H,GFXMMU LUT entry 22 high" hexmask.long.tbyte 0xB4 0.--17. 1. "LO,Line offset" line.long 0xB8 "GFXMMU_LUT23L,GFXMMU LUT entry 23 low" hexmask.long.byte 0xB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC "GFXMMU_LUT23H,GFXMMU LUT entry 23 high" hexmask.long.tbyte 0xBC 0.--17. 1. "LO,Line offset" line.long 0xC0 "GFXMMU_LUT24L,GFXMMU LUT entry 24 low" hexmask.long.byte 0xC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4 "GFXMMU_LUT24H,GFXMMU LUT entry 24 high" hexmask.long.tbyte 0xC4 0.--17. 1. "LO,Line offset" line.long 0xC8 "GFXMMU_LUT25L,GFXMMU LUT entry 25 low" hexmask.long.byte 0xC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC "GFXMMU_LUT25H,GFXMMU LUT entry 25 high" hexmask.long.tbyte 0xCC 0.--17. 1. "LO,Line offset" line.long 0xD0 "GFXMMU_LUT26L,GFXMMU LUT entry 26 low" hexmask.long.byte 0xD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4 "GFXMMU_LUT26H,GFXMMU LUT entry 26 high" hexmask.long.tbyte 0xD4 0.--17. 1. "LO,Line offset" line.long 0xD8 "GFXMMU_LUT27L,GFXMMU LUT entry 27 low" hexmask.long.byte 0xD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC "GFXMMU_LUT27H,GFXMMU LUT entry 27 high" hexmask.long.tbyte 0xDC 0.--17. 1. "LO,Line offset" line.long 0xE0 "GFXMMU_LUT28L,GFXMMU LUT entry 28 low" hexmask.long.byte 0xE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4 "GFXMMU_LUT28H,GFXMMU LUT entry 28 high" hexmask.long.tbyte 0xE4 0.--17. 1. "LO,Line offset" line.long 0xE8 "GFXMMU_LUT29L,GFXMMU LUT entry 29 low" hexmask.long.byte 0xE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC "GFXMMU_LUT29H,GFXMMU LUT entry 29 high" hexmask.long.tbyte 0xEC 0.--17. 1. "LO,Line offset" line.long 0xF0 "GFXMMU_LUT30L,GFXMMU LUT entry 30 low" hexmask.long.byte 0xF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4 "GFXMMU_LUT30H,GFXMMU LUT entry 30 high" hexmask.long.tbyte 0xF4 0.--17. 1. "LO,Line offset" line.long 0xF8 "GFXMMU_LUT31L,GFXMMU LUT entry 31 low" hexmask.long.byte 0xF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC "GFXMMU_LUT31H,GFXMMU LUT entry 31 high" hexmask.long.tbyte 0xFC 0.--17. 1. "LO,Line offset" line.long 0x100 "GFXMMU_LUT32L,GFXMMU LUT entry 32 low" hexmask.long.byte 0x100 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x100 8.--15. 1. "FVB,First valid block" bitfld.long 0x100 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x104 "GFXMMU_LUT32H,GFXMMU LUT entry 32 high" hexmask.long.tbyte 0x104 0.--17. 1. "LO,Line offset" line.long 0x108 "GFXMMU_LUT33L,GFXMMU LUT entry 33 low" hexmask.long.byte 0x108 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x108 8.--15. 1. "FVB,First valid block" bitfld.long 0x108 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x10C "GFXMMU_LUT33H,GFXMMU LUT entry 33 high" hexmask.long.tbyte 0x10C 0.--17. 1. "LO,Line offset" line.long 0x110 "GFXMMU_LUT34L,GFXMMU LUT entry 34 low" hexmask.long.byte 0x110 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x110 8.--15. 1. "FVB,First valid block" bitfld.long 0x110 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x114 "GFXMMU_LUT34H,GFXMMU LUT entry 34 high" hexmask.long.tbyte 0x114 0.--17. 1. "LO,Line offset" line.long 0x118 "GFXMMU_LUT35L,GFXMMU LUT entry 35 low" hexmask.long.byte 0x118 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x118 8.--15. 1. "FVB,First valid block" bitfld.long 0x118 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x11C "GFXMMU_LUT35H,GFXMMU LUT entry 35 high" hexmask.long.tbyte 0x11C 0.--17. 1. "LO,Line offset" line.long 0x120 "GFXMMU_LUT36L,GFXMMU LUT entry 36 low" hexmask.long.byte 0x120 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x120 8.--15. 1. "FVB,First valid block" bitfld.long 0x120 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x124 "GFXMMU_LUT36H,GFXMMU LUT entry 36 high" hexmask.long.tbyte 0x124 0.--17. 1. "LO,Line offset" line.long 0x128 "GFXMMU_LUT37L,GFXMMU LUT entry 37 low" hexmask.long.byte 0x128 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x128 8.--15. 1. "FVB,First valid block" bitfld.long 0x128 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x12C "GFXMMU_LUT37H,GFXMMU LUT entry 37 high" hexmask.long.tbyte 0x12C 0.--17. 1. "LO,Line offset" line.long 0x130 "GFXMMU_LUT38L,GFXMMU LUT entry 38 low" hexmask.long.byte 0x130 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x130 8.--15. 1. "FVB,First valid block" bitfld.long 0x130 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x134 "GFXMMU_LUT38H,GFXMMU LUT entry 38 high" hexmask.long.tbyte 0x134 0.--17. 1. "LO,Line offset" line.long 0x138 "GFXMMU_LUT39L,GFXMMU LUT entry 39 low" hexmask.long.byte 0x138 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x138 8.--15. 1. "FVB,First valid block" bitfld.long 0x138 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x13C "GFXMMU_LUT39H,GFXMMU LUT entry 39 high" hexmask.long.tbyte 0x13C 0.--17. 1. "LO,Line offset" line.long 0x140 "GFXMMU_LUT40L,GFXMMU LUT entry 40 low" hexmask.long.byte 0x140 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x140 8.--15. 1. "FVB,First valid block" bitfld.long 0x140 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x144 "GFXMMU_LUT40H,GFXMMU LUT entry 40 high" hexmask.long.tbyte 0x144 0.--17. 1. "LO,Line offset" line.long 0x148 "GFXMMU_LUT41L,GFXMMU LUT entry 41 low" hexmask.long.byte 0x148 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x148 8.--15. 1. "FVB,First valid block" bitfld.long 0x148 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14C "GFXMMU_LUT41H,GFXMMU LUT entry 41 high" hexmask.long.tbyte 0x14C 0.--17. 1. "LO,Line offset" line.long 0x150 "GFXMMU_LUT42L,GFXMMU LUT entry 42 low" hexmask.long.byte 0x150 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x150 8.--15. 1. "FVB,First valid block" bitfld.long 0x150 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x154 "GFXMMU_LUT42H,GFXMMU LUT entry 42 high" hexmask.long.tbyte 0x154 0.--17. 1. "LO,Line offset" line.long 0x158 "GFXMMU_LUT43L,GFXMMU LUT entry 43 low" hexmask.long.byte 0x158 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x158 8.--15. 1. "FVB,First valid block" bitfld.long 0x158 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x15C "GFXMMU_LUT43H,GFXMMU LUT entry 43 high" hexmask.long.tbyte 0x15C 0.--17. 1. "LO,Line offset" line.long 0x160 "GFXMMU_LUT44L,GFXMMU LUT entry 44 low" hexmask.long.byte 0x160 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x160 8.--15. 1. "FVB,First valid block" bitfld.long 0x160 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x164 "GFXMMU_LUT44H,GFXMMU LUT entry 44 high" hexmask.long.tbyte 0x164 0.--17. 1. "LO,Line offset" line.long 0x168 "GFXMMU_LUT45L,GFXMMU LUT entry 45 low" hexmask.long.byte 0x168 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x168 8.--15. 1. "FVB,First valid block" bitfld.long 0x168 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x16C "GFXMMU_LUT45H,GFXMMU LUT entry 45 high" hexmask.long.tbyte 0x16C 0.--17. 1. "LO,Line offset" line.long 0x170 "GFXMMU_LUT46L,GFXMMU LUT entry 46 low" hexmask.long.byte 0x170 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x170 8.--15. 1. "FVB,First valid block" bitfld.long 0x170 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x174 "GFXMMU_LUT46H,GFXMMU LUT entry 46 high" hexmask.long.tbyte 0x174 0.--17. 1. "LO,Line offset" line.long 0x178 "GFXMMU_LUT47L,GFXMMU LUT entry 47 low" hexmask.long.byte 0x178 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x178 8.--15. 1. "FVB,First valid block" bitfld.long 0x178 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x17C "GFXMMU_LUT47H,GFXMMU LUT entry 47 high" hexmask.long.tbyte 0x17C 0.--17. 1. "LO,Line offset" line.long 0x180 "GFXMMU_LUT48L,GFXMMU LUT entry 48 low" hexmask.long.byte 0x180 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x180 8.--15. 1. "FVB,First valid block" bitfld.long 0x180 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x184 "GFXMMU_LUT48H,GFXMMU LUT entry 48 high" hexmask.long.tbyte 0x184 0.--17. 1. "LO,Line offset" line.long 0x188 "GFXMMU_LUT49L,GFXMMU LUT entry 49 low" hexmask.long.byte 0x188 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x188 8.--15. 1. "FVB,First valid block" bitfld.long 0x188 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x18C "GFXMMU_LUT49H,GFXMMU LUT entry 49 high" hexmask.long.tbyte 0x18C 0.--17. 1. "LO,Line offset" line.long 0x190 "GFXMMU_LUT50L,GFXMMU LUT entry 50 low" hexmask.long.byte 0x190 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x190 8.--15. 1. "FVB,First valid block" bitfld.long 0x190 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x194 "GFXMMU_LUT50H,GFXMMU LUT entry 50 high" hexmask.long.tbyte 0x194 0.--17. 1. "LO,Line offset" line.long 0x198 "GFXMMU_LUT51L,GFXMMU LUT entry 51 low" hexmask.long.byte 0x198 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x198 8.--15. 1. "FVB,First valid block" bitfld.long 0x198 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x19C "GFXMMU_LUT51H,GFXMMU LUT entry 51 high" hexmask.long.tbyte 0x19C 0.--17. 1. "LO,Line offset" line.long 0x1A0 "GFXMMU_LUT52L,GFXMMU LUT entry 52 low" hexmask.long.byte 0x1A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1A4 "GFXMMU_LUT52H,GFXMMU LUT entry 52 high" hexmask.long.tbyte 0x1A4 0.--17. 1. "LO,Line offset" line.long 0x1A8 "GFXMMU_LUT53L,GFXMMU LUT entry 53 low" hexmask.long.byte 0x1A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1AC "GFXMMU_LUT53H,GFXMMU LUT entry 53 high" hexmask.long.tbyte 0x1AC 0.--17. 1. "LO,Line offset" line.long 0x1B0 "GFXMMU_LUT54L,GFXMMU LUT entry 54 low" hexmask.long.byte 0x1B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1B4 "GFXMMU_LUT54H,GFXMMU LUT entry 54 high" hexmask.long.tbyte 0x1B4 0.--17. 1. "LO,Line offset" line.long 0x1B8 "GFXMMU_LUT55L,GFXMMU LUT entry 55 low" hexmask.long.byte 0x1B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1BC "GFXMMU_LUT55H,GFXMMU LUT entry 55 high" hexmask.long.tbyte 0x1BC 0.--17. 1. "LO,Line offset" line.long 0x1C0 "GFXMMU_LUT56L,GFXMMU LUT entry 56 low" hexmask.long.byte 0x1C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C4 "GFXMMU_LUT56H,GFXMMU LUT entry 56 high" hexmask.long.tbyte 0x1C4 0.--17. 1. "LO,Line offset" line.long 0x1C8 "GFXMMU_LUT57L,GFXMMU LUT entry 57 low" hexmask.long.byte 0x1C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1CC "GFXMMU_LUT57H,GFXMMU LUT entry 57 high" hexmask.long.tbyte 0x1CC 0.--17. 1. "LO,Line offset" line.long 0x1D0 "GFXMMU_LUT58L,GFXMMU LUT entry 58 low" hexmask.long.byte 0x1D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1D4 "GFXMMU_LUT58H,GFXMMU LUT entry 58 high" hexmask.long.tbyte 0x1D4 0.--17. 1. "LO,Line offset" line.long 0x1D8 "GFXMMU_LUT59L,GFXMMU LUT entry 59 low" hexmask.long.byte 0x1D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1DC "GFXMMU_LUT59H,GFXMMU LUT entry 59 high" hexmask.long.tbyte 0x1DC 0.--17. 1. "LO,Line offset" line.long 0x1E0 "GFXMMU_LUT60L,GFXMMU LUT entry 60 low" hexmask.long.byte 0x1E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1E4 "GFXMMU_LUT60H,GFXMMU LUT entry 60 high" hexmask.long.tbyte 0x1E4 0.--17. 1. "LO,Line offset" line.long 0x1E8 "GFXMMU_LUT61L,GFXMMU LUT entry 61 low" hexmask.long.byte 0x1E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1EC "GFXMMU_LUT61H,GFXMMU LUT entry 61 high" hexmask.long.tbyte 0x1EC 0.--17. 1. "LO,Line offset" line.long 0x1F0 "GFXMMU_LUT62L,GFXMMU LUT entry 62 low" hexmask.long.byte 0x1F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1F4 "GFXMMU_LUT62H,GFXMMU LUT entry 62 high" hexmask.long.tbyte 0x1F4 0.--17. 1. "LO,Line offset" line.long 0x1F8 "GFXMMU_LUT63L,GFXMMU LUT entry 63 low" hexmask.long.byte 0x1F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1FC "GFXMMU_LUT63H,GFXMMU LUT entry 63 high" hexmask.long.tbyte 0x1FC 0.--17. 1. "LO,Line offset" line.long 0x200 "GFXMMU_LUT64L,GFXMMU LUT entry 64 low" hexmask.long.byte 0x200 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x200 8.--15. 1. "FVB,First valid block" bitfld.long 0x200 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x204 "GFXMMU_LUT64H,GFXMMU LUT entry 64 high" hexmask.long.tbyte 0x204 0.--17. 1. "LO,Line offset" line.long 0x208 "GFXMMU_LUT65L,GFXMMU LUT entry 65 low" hexmask.long.byte 0x208 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x208 8.--15. 1. "FVB,First valid block" bitfld.long 0x208 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x20C "GFXMMU_LUT65H,GFXMMU LUT entry 65 high" hexmask.long.tbyte 0x20C 0.--17. 1. "LO,Line offset" line.long 0x210 "GFXMMU_LUT66L,GFXMMU LUT entry 66 low" hexmask.long.byte 0x210 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x210 8.--15. 1. "FVB,First valid block" bitfld.long 0x210 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x214 "GFXMMU_LUT66H,GFXMMU LUT entry 66 high" hexmask.long.tbyte 0x214 0.--17. 1. "LO,Line offset" line.long 0x218 "GFXMMU_LUT67L,GFXMMU LUT entry 67 low" hexmask.long.byte 0x218 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x218 8.--15. 1. "FVB,First valid block" bitfld.long 0x218 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x21C "GFXMMU_LUT67H,GFXMMU LUT entry 67 high" hexmask.long.tbyte 0x21C 0.--17. 1. "LO,Line offset" line.long 0x220 "GFXMMU_LUT68L,GFXMMU LUT entry 68 low" hexmask.long.byte 0x220 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x220 8.--15. 1. "FVB,First valid block" bitfld.long 0x220 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x224 "GFXMMU_LUT68H,GFXMMU LUT entry 68 high" hexmask.long.tbyte 0x224 0.--17. 1. "LO,Line offset" line.long 0x228 "GFXMMU_LUT69L,GFXMMU LUT entry 69 low" hexmask.long.byte 0x228 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x228 8.--15. 1. "FVB,First valid block" bitfld.long 0x228 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x22C "GFXMMU_LUT69H,GFXMMU LUT entry 69 high" hexmask.long.tbyte 0x22C 0.--17. 1. "LO,Line offset" line.long 0x230 "GFXMMU_LUT70L,GFXMMU LUT entry 70 low" hexmask.long.byte 0x230 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x230 8.--15. 1. "FVB,First valid block" bitfld.long 0x230 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x234 "GFXMMU_LUT70H,GFXMMU LUT entry 70 high" hexmask.long.tbyte 0x234 0.--17. 1. "LO,Line offset" line.long 0x238 "GFXMMU_LUT71L,GFXMMU LUT entry 71 low" hexmask.long.byte 0x238 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x238 8.--15. 1. "FVB,First valid block" bitfld.long 0x238 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x23C "GFXMMU_LUT71H,GFXMMU LUT entry 71 high" hexmask.long.tbyte 0x23C 0.--17. 1. "LO,Line offset" line.long 0x240 "GFXMMU_LUT72L,GFXMMU LUT entry 72 low" hexmask.long.byte 0x240 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x240 8.--15. 1. "FVB,First valid block" bitfld.long 0x240 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x244 "GFXMMU_LUT72H,GFXMMU LUT entry 72 high" hexmask.long.tbyte 0x244 0.--17. 1. "LO,Line offset" line.long 0x248 "GFXMMU_LUT73L,GFXMMU LUT entry 73 low" hexmask.long.byte 0x248 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x248 8.--15. 1. "FVB,First valid block" bitfld.long 0x248 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24C "GFXMMU_LUT73H,GFXMMU LUT entry 73 high" hexmask.long.tbyte 0x24C 0.--17. 1. "LO,Line offset" line.long 0x250 "GFXMMU_LUT74L,GFXMMU LUT entry 74 low" hexmask.long.byte 0x250 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x250 8.--15. 1. "FVB,First valid block" bitfld.long 0x250 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x254 "GFXMMU_LUT74H,GFXMMU LUT entry 74 high" hexmask.long.tbyte 0x254 0.--17. 1. "LO,Line offset" line.long 0x258 "GFXMMU_LUT75L,GFXMMU LUT entry 75 low" hexmask.long.byte 0x258 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x258 8.--15. 1. "FVB,First valid block" bitfld.long 0x258 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x25C "GFXMMU_LUT75H,GFXMMU LUT entry 75 high" hexmask.long.tbyte 0x25C 0.--17. 1. "LO,Line offset" line.long 0x260 "GFXMMU_LUT76L,GFXMMU LUT entry 76 low" hexmask.long.byte 0x260 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x260 8.--15. 1. "FVB,First valid block" bitfld.long 0x260 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x264 "GFXMMU_LUT76H,GFXMMU LUT entry 76 high" hexmask.long.tbyte 0x264 0.--17. 1. "LO,Line offset" line.long 0x268 "GFXMMU_LUT77L,GFXMMU LUT entry 77 low" hexmask.long.byte 0x268 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x268 8.--15. 1. "FVB,First valid block" bitfld.long 0x268 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x26C "GFXMMU_LUT77H,GFXMMU LUT entry 77 high" hexmask.long.tbyte 0x26C 0.--17. 1. "LO,Line offset" line.long 0x270 "GFXMMU_LUT78L,GFXMMU LUT entry 78 low" hexmask.long.byte 0x270 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x270 8.--15. 1. "FVB,First valid block" bitfld.long 0x270 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x274 "GFXMMU_LUT78H,GFXMMU LUT entry 78 high" hexmask.long.tbyte 0x274 0.--17. 1. "LO,Line offset" line.long 0x278 "GFXMMU_LUT79L,GFXMMU LUT entry 79 low" hexmask.long.byte 0x278 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x278 8.--15. 1. "FVB,First valid block" bitfld.long 0x278 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x27C "GFXMMU_LUT79H,GFXMMU LUT entry 79 high" hexmask.long.tbyte 0x27C 0.--17. 1. "LO,Line offset" line.long 0x280 "GFXMMU_LUT80L,GFXMMU LUT entry 80 low" hexmask.long.byte 0x280 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x280 8.--15. 1. "FVB,First valid block" bitfld.long 0x280 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x284 "GFXMMU_LUT80H,GFXMMU LUT entry 80 high" hexmask.long.tbyte 0x284 0.--17. 1. "LO,Line offset" line.long 0x288 "GFXMMU_LUT81L,GFXMMU LUT entry 81 low" hexmask.long.byte 0x288 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x288 8.--15. 1. "FVB,First valid block" bitfld.long 0x288 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x28C "GFXMMU_LUT81H,GFXMMU LUT entry 81 high" hexmask.long.tbyte 0x28C 0.--17. 1. "LO,Line offset" line.long 0x290 "GFXMMU_LUT82L,GFXMMU LUT entry 82 low" hexmask.long.byte 0x290 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x290 8.--15. 1. "FVB,First valid block" bitfld.long 0x290 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x294 "GFXMMU_LUT82H,GFXMMU LUT entry 82 high" hexmask.long.tbyte 0x294 0.--17. 1. "LO,Line offset" line.long 0x298 "GFXMMU_LUT83L,GFXMMU LUT entry 83 low" hexmask.long.byte 0x298 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x298 8.--15. 1. "FVB,First valid block" bitfld.long 0x298 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x29C "GFXMMU_LUT83H,GFXMMU LUT entry 83 high" hexmask.long.tbyte 0x29C 0.--17. 1. "LO,Line offset" line.long 0x2A0 "GFXMMU_LUT84L,GFXMMU LUT entry 84 low" hexmask.long.byte 0x2A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2A4 "GFXMMU_LUT84H,GFXMMU LUT entry 84 high" hexmask.long.tbyte 0x2A4 0.--17. 1. "LO,Line offset" line.long 0x2A8 "GFXMMU_LUT85L,GFXMMU LUT entry 85 low" hexmask.long.byte 0x2A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2AC "GFXMMU_LUT85H,GFXMMU LUT entry 85 high" hexmask.long.tbyte 0x2AC 0.--17. 1. "LO,Line offset" line.long 0x2B0 "GFXMMU_LUT86L,GFXMMU LUT entry 86 low" hexmask.long.byte 0x2B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2B4 "GFXMMU_LUT86H,GFXMMU LUT entry 86 high" hexmask.long.tbyte 0x2B4 0.--17. 1. "LO,Line offset" line.long 0x2B8 "GFXMMU_LUT87L,GFXMMU LUT entry 87 low" hexmask.long.byte 0x2B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2BC "GFXMMU_LUT87H,GFXMMU LUT entry 87 high" hexmask.long.tbyte 0x2BC 0.--17. 1. "LO,Line offset" line.long 0x2C0 "GFXMMU_LUT88L,GFXMMU LUT entry 88 low" hexmask.long.byte 0x2C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C4 "GFXMMU_LUT88H,GFXMMU LUT entry 88 high" hexmask.long.tbyte 0x2C4 0.--17. 1. "LO,Line offset" line.long 0x2C8 "GFXMMU_LUT89L,GFXMMU LUT entry 89 low" hexmask.long.byte 0x2C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2CC "GFXMMU_LUT89H,GFXMMU LUT entry 89 high" hexmask.long.tbyte 0x2CC 0.--17. 1. "LO,Line offset" line.long 0x2D0 "GFXMMU_LUT90L,GFXMMU LUT entry 90 low" hexmask.long.byte 0x2D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2D4 "GFXMMU_LUT90H,GFXMMU LUT entry 90 high" hexmask.long.tbyte 0x2D4 0.--17. 1. "LO,Line offset" line.long 0x2D8 "GFXMMU_LUT91L,GFXMMU LUT entry 91 low" hexmask.long.byte 0x2D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2DC "GFXMMU_LUT91H,GFXMMU LUT entry 91 high" hexmask.long.tbyte 0x2DC 0.--17. 1. "LO,Line offset" line.long 0x2E0 "GFXMMU_LUT92L,GFXMMU LUT entry 92 low" hexmask.long.byte 0x2E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2E4 "GFXMMU_LUT92H,GFXMMU LUT entry 92 high" hexmask.long.tbyte 0x2E4 0.--17. 1. "LO,Line offset" line.long 0x2E8 "GFXMMU_LUT93L,GFXMMU LUT entry 93 low" hexmask.long.byte 0x2E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2EC "GFXMMU_LUT93H,GFXMMU LUT entry 93 high" hexmask.long.tbyte 0x2EC 0.--17. 1. "LO,Line offset" line.long 0x2F0 "GFXMMU_LUT94L,GFXMMU LUT entry 94 low" hexmask.long.byte 0x2F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2F4 "GFXMMU_LUT94H,GFXMMU LUT entry 94 high" hexmask.long.tbyte 0x2F4 0.--17. 1. "LO,Line offset" line.long 0x2F8 "GFXMMU_LUT95L,GFXMMU LUT entry 95 low" hexmask.long.byte 0x2F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2FC "GFXMMU_LUT95H,GFXMMU LUT entry 95 high" hexmask.long.tbyte 0x2FC 0.--17. 1. "LO,Line offset" line.long 0x300 "GFXMMU_LUT96L,GFXMMU LUT entry 96 low" hexmask.long.byte 0x300 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x300 8.--15. 1. "FVB,First valid block" bitfld.long 0x300 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x304 "GFXMMU_LUT96H,GFXMMU LUT entry 96 high" hexmask.long.tbyte 0x304 0.--17. 1. "LO,Line offset" line.long 0x308 "GFXMMU_LUT97L,GFXMMU LUT entry 97 low" hexmask.long.byte 0x308 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x308 8.--15. 1. "FVB,First valid block" bitfld.long 0x308 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x30C "GFXMMU_LUT97H,GFXMMU LUT entry 97 high" hexmask.long.tbyte 0x30C 0.--17. 1. "LO,Line offset" line.long 0x310 "GFXMMU_LUT98L,GFXMMU LUT entry 98 low" hexmask.long.byte 0x310 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x310 8.--15. 1. "FVB,First valid block" bitfld.long 0x310 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x314 "GFXMMU_LUT98H,GFXMMU LUT entry 98 high" hexmask.long.tbyte 0x314 0.--17. 1. "LO,Line offset" line.long 0x318 "GFXMMU_LUT99L,GFXMMU LUT entry 99 low" hexmask.long.byte 0x318 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x318 8.--15. 1. "FVB,First valid block" bitfld.long 0x318 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x31C "GFXMMU_LUT99H,GFXMMU LUT entry 99 high" hexmask.long.tbyte 0x31C 0.--17. 1. "LO,Line offset" line.long 0x320 "GFXMMU_LUT100L,GFXMMU LUT entry 100 low" hexmask.long.byte 0x320 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x320 8.--15. 1. "FVB,First valid block" bitfld.long 0x320 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x324 "GFXMMU_LUT100H,GFXMMU LUT entry 100 high" hexmask.long.tbyte 0x324 0.--17. 1. "LO,Line offset" line.long 0x328 "GFXMMU_LUT101L,GFXMMU LUT entry 101 low" hexmask.long.byte 0x328 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x328 8.--15. 1. "FVB,First valid block" bitfld.long 0x328 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x32C "GFXMMU_LUT101H,GFXMMU LUT entry 101 high" hexmask.long.tbyte 0x32C 0.--17. 1. "LO,Line offset" line.long 0x330 "GFXMMU_LUT102L,GFXMMU LUT entry 102 low" hexmask.long.byte 0x330 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x330 8.--15. 1. "FVB,First valid block" bitfld.long 0x330 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x334 "GFXMMU_LUT102H,GFXMMU LUT entry 102 high" hexmask.long.tbyte 0x334 0.--17. 1. "LO,Line offset" line.long 0x338 "GFXMMU_LUT103L,GFXMMU LUT entry 103 low" hexmask.long.byte 0x338 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x338 8.--15. 1. "FVB,First valid block" bitfld.long 0x338 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x33C "GFXMMU_LUT103H,GFXMMU LUT entry 103 high" hexmask.long.tbyte 0x33C 0.--17. 1. "LO,Line offset" line.long 0x340 "GFXMMU_LUT104L,GFXMMU LUT entry 104 low" hexmask.long.byte 0x340 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x340 8.--15. 1. "FVB,First valid block" bitfld.long 0x340 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x344 "GFXMMU_LUT104H,GFXMMU LUT entry 104 high" hexmask.long.tbyte 0x344 0.--17. 1. "LO,Line offset" line.long 0x348 "GFXMMU_LUT105L,GFXMMU LUT entry 105 low" hexmask.long.byte 0x348 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x348 8.--15. 1. "FVB,First valid block" bitfld.long 0x348 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34C "GFXMMU_LUT105H,GFXMMU LUT entry 105 high" hexmask.long.tbyte 0x34C 0.--17. 1. "LO,Line offset" line.long 0x350 "GFXMMU_LUT106L,GFXMMU LUT entry 106 low" hexmask.long.byte 0x350 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x350 8.--15. 1. "FVB,First valid block" bitfld.long 0x350 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x354 "GFXMMU_LUT106H,GFXMMU LUT entry 106 high" hexmask.long.tbyte 0x354 0.--17. 1. "LO,Line offset" line.long 0x358 "GFXMMU_LUT107L,GFXMMU LUT entry 107 low" hexmask.long.byte 0x358 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x358 8.--15. 1. "FVB,First valid block" bitfld.long 0x358 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x35C "GFXMMU_LUT107H,GFXMMU LUT entry 107 high" hexmask.long.tbyte 0x35C 0.--17. 1. "LO,Line offset" line.long 0x360 "GFXMMU_LUT108L,GFXMMU LUT entry 108 low" hexmask.long.byte 0x360 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x360 8.--15. 1. "FVB,First valid block" bitfld.long 0x360 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x364 "GFXMMU_LUT108H,GFXMMU LUT entry 108 high" hexmask.long.tbyte 0x364 0.--17. 1. "LO,Line offset" line.long 0x368 "GFXMMU_LUT109L,GFXMMU LUT entry 109 low" hexmask.long.byte 0x368 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x368 8.--15. 1. "FVB,First valid block" bitfld.long 0x368 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x36C "GFXMMU_LUT109H,GFXMMU LUT entry 109 high" hexmask.long.tbyte 0x36C 0.--17. 1. "LO,Line offset" line.long 0x370 "GFXMMU_LUT110L,GFXMMU LUT entry 110 low" hexmask.long.byte 0x370 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x370 8.--15. 1. "FVB,First valid block" bitfld.long 0x370 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x374 "GFXMMU_LUT110H,GFXMMU LUT entry 110 high" hexmask.long.tbyte 0x374 0.--17. 1. "LO,Line offset" line.long 0x378 "GFXMMU_LUT111L,GFXMMU LUT entry 111 low" hexmask.long.byte 0x378 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x378 8.--15. 1. "FVB,First valid block" bitfld.long 0x378 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x37C "GFXMMU_LUT111H,GFXMMU LUT entry 111 high" hexmask.long.tbyte 0x37C 0.--17. 1. "LO,Line offset" line.long 0x380 "GFXMMU_LUT112L,GFXMMU LUT entry 112 low" hexmask.long.byte 0x380 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x380 8.--15. 1. "FVB,First valid block" bitfld.long 0x380 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x384 "GFXMMU_LUT112H,GFXMMU LUT entry 112 high" hexmask.long.tbyte 0x384 0.--17. 1. "LO,Line offset" line.long 0x388 "GFXMMU_LUT113L,GFXMMU LUT entry 113 low" hexmask.long.byte 0x388 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x388 8.--15. 1. "FVB,First valid block" bitfld.long 0x388 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x38C "GFXMMU_LUT113H,GFXMMU LUT entry 113 high" hexmask.long.tbyte 0x38C 0.--17. 1. "LO,Line offset" line.long 0x390 "GFXMMU_LUT114L,GFXMMU LUT entry 114 low" hexmask.long.byte 0x390 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x390 8.--15. 1. "FVB,First valid block" bitfld.long 0x390 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x394 "GFXMMU_LUT114H,GFXMMU LUT entry 114 high" hexmask.long.tbyte 0x394 0.--17. 1. "LO,Line offset" line.long 0x398 "GFXMMU_LUT115L,GFXMMU LUT entry 115 low" hexmask.long.byte 0x398 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x398 8.--15. 1. "FVB,First valid block" bitfld.long 0x398 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x39C "GFXMMU_LUT115H,GFXMMU LUT entry 115 high" hexmask.long.tbyte 0x39C 0.--17. 1. "LO,Line offset" line.long 0x3A0 "GFXMMU_LUT116L,GFXMMU LUT entry 116 low" hexmask.long.byte 0x3A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3A4 "GFXMMU_LUT116H,GFXMMU LUT entry 116 high" hexmask.long.tbyte 0x3A4 0.--17. 1. "LO,Line offset" line.long 0x3A8 "GFXMMU_LUT117L,GFXMMU LUT entry 117 low" hexmask.long.byte 0x3A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3AC "GFXMMU_LUT117H,GFXMMU LUT entry 117 high" hexmask.long.tbyte 0x3AC 0.--17. 1. "LO,Line offset" line.long 0x3B0 "GFXMMU_LUT118L,GFXMMU LUT entry 118 low" hexmask.long.byte 0x3B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3B4 "GFXMMU_LUT118H,GFXMMU LUT entry 118 high" hexmask.long.tbyte 0x3B4 0.--17. 1. "LO,Line offset" line.long 0x3B8 "GFXMMU_LUT119L,GFXMMU LUT entry 119 low" hexmask.long.byte 0x3B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3BC "GFXMMU_LUT119H,GFXMMU LUT entry 119 high" hexmask.long.tbyte 0x3BC 0.--17. 1. "LO,Line offset" line.long 0x3C0 "GFXMMU_LUT120L,GFXMMU LUT entry 120 low" hexmask.long.byte 0x3C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C4 "GFXMMU_LUT120H,GFXMMU LUT entry 120 high" hexmask.long.tbyte 0x3C4 0.--17. 1. "LO,Line offset" line.long 0x3C8 "GFXMMU_LUT121L,GFXMMU LUT entry 121 low" hexmask.long.byte 0x3C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3CC "GFXMMU_LUT121H,GFXMMU LUT entry 121 high" hexmask.long.tbyte 0x3CC 0.--17. 1. "LO,Line offset" line.long 0x3D0 "GFXMMU_LUT122L,GFXMMU LUT entry 122 low" hexmask.long.byte 0x3D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3D4 "GFXMMU_LUT122H,GFXMMU LUT entry 122 high" hexmask.long.tbyte 0x3D4 0.--17. 1. "LO,Line offset" line.long 0x3D8 "GFXMMU_LUT123L,GFXMMU LUT entry 123 low" hexmask.long.byte 0x3D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3DC "GFXMMU_LUT123H,GFXMMU LUT entry 123 high" hexmask.long.tbyte 0x3DC 0.--17. 1. "LO,Line offset" line.long 0x3E0 "GFXMMU_LUT124L,GFXMMU LUT entry 124 low" hexmask.long.byte 0x3E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3E4 "GFXMMU_LUT124H,GFXMMU LUT entry 124 high" hexmask.long.tbyte 0x3E4 0.--17. 1. "LO,Line offset" line.long 0x3E8 "GFXMMU_LUT125L,GFXMMU LUT entry 125 low" hexmask.long.byte 0x3E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3EC "GFXMMU_LUT125H,GFXMMU LUT entry 125 high" hexmask.long.tbyte 0x3EC 0.--17. 1. "LO,Line offset" line.long 0x3F0 "GFXMMU_LUT126L,GFXMMU LUT entry 126 low" hexmask.long.byte 0x3F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3F4 "GFXMMU_LUT126H,GFXMMU LUT entry 126 high" hexmask.long.tbyte 0x3F4 0.--17. 1. "LO,Line offset" line.long 0x3F8 "GFXMMU_LUT127L,GFXMMU LUT entry 127 low" hexmask.long.byte 0x3F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3FC "GFXMMU_LUT127H,GFXMMU LUT entry 127 high" hexmask.long.tbyte 0x3FC 0.--17. 1. "LO,Line offset" line.long 0x400 "GFXMMU_LUT128L,GFXMMU LUT entry 128 low" hexmask.long.byte 0x400 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x400 8.--15. 1. "FVB,First valid block" bitfld.long 0x400 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x404 "GFXMMU_LUT128H,GFXMMU LUT entry 128 high" hexmask.long.tbyte 0x404 0.--17. 1. "LO,Line offset" line.long 0x408 "GFXMMU_LUT129L,GFXMMU LUT entry 129 low" hexmask.long.byte 0x408 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x408 8.--15. 1. "FVB,First valid block" bitfld.long 0x408 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x40C "GFXMMU_LUT129H,GFXMMU LUT entry 129 high" hexmask.long.tbyte 0x40C 0.--17. 1. "LO,Line offset" line.long 0x410 "GFXMMU_LUT130L,GFXMMU LUT entry 130 low" hexmask.long.byte 0x410 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x410 8.--15. 1. "FVB,First valid block" bitfld.long 0x410 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x414 "GFXMMU_LUT130H,GFXMMU LUT entry 130 high" hexmask.long.tbyte 0x414 0.--17. 1. "LO,Line offset" line.long 0x418 "GFXMMU_LUT131L,GFXMMU LUT entry 131 low" hexmask.long.byte 0x418 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x418 8.--15. 1. "FVB,First valid block" bitfld.long 0x418 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x41C "GFXMMU_LUT131H,GFXMMU LUT entry 131 high" hexmask.long.tbyte 0x41C 0.--17. 1. "LO,Line offset" line.long 0x420 "GFXMMU_LUT132L,GFXMMU LUT entry 132 low" hexmask.long.byte 0x420 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x420 8.--15. 1. "FVB,First valid block" bitfld.long 0x420 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x424 "GFXMMU_LUT132H,GFXMMU LUT entry 132 high" hexmask.long.tbyte 0x424 0.--17. 1. "LO,Line offset" line.long 0x428 "GFXMMU_LUT133L,GFXMMU LUT entry 133 low" hexmask.long.byte 0x428 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x428 8.--15. 1. "FVB,First valid block" bitfld.long 0x428 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x42C "GFXMMU_LUT133H,GFXMMU LUT entry 133 high" hexmask.long.tbyte 0x42C 0.--17. 1. "LO,Line offset" line.long 0x430 "GFXMMU_LUT134L,GFXMMU LUT entry 134 low" hexmask.long.byte 0x430 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x430 8.--15. 1. "FVB,First valid block" bitfld.long 0x430 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x434 "GFXMMU_LUT134H,GFXMMU LUT entry 134 high" hexmask.long.tbyte 0x434 0.--17. 1. "LO,Line offset" line.long 0x438 "GFXMMU_LUT135L,GFXMMU LUT entry 135 low" hexmask.long.byte 0x438 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x438 8.--15. 1. "FVB,First valid block" bitfld.long 0x438 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x43C "GFXMMU_LUT135H,GFXMMU LUT entry 135 high" hexmask.long.tbyte 0x43C 0.--17. 1. "LO,Line offset" line.long 0x440 "GFXMMU_LUT136L,GFXMMU LUT entry 136 low" hexmask.long.byte 0x440 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x440 8.--15. 1. "FVB,First valid block" bitfld.long 0x440 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x444 "GFXMMU_LUT136H,GFXMMU LUT entry 136 high" hexmask.long.tbyte 0x444 0.--17. 1. "LO,Line offset" line.long 0x448 "GFXMMU_LUT137L,GFXMMU LUT entry 137 low" hexmask.long.byte 0x448 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x448 8.--15. 1. "FVB,First valid block" bitfld.long 0x448 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44C "GFXMMU_LUT137H,GFXMMU LUT entry 137 high" hexmask.long.tbyte 0x44C 0.--17. 1. "LO,Line offset" line.long 0x450 "GFXMMU_LUT138L,GFXMMU LUT entry 138 low" hexmask.long.byte 0x450 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x450 8.--15. 1. "FVB,First valid block" bitfld.long 0x450 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x454 "GFXMMU_LUT138H,GFXMMU LUT entry 138 high" hexmask.long.tbyte 0x454 0.--17. 1. "LO,Line offset" line.long 0x458 "GFXMMU_LUT139L,GFXMMU LUT entry 139 low" hexmask.long.byte 0x458 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x458 8.--15. 1. "FVB,First valid block" bitfld.long 0x458 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x45C "GFXMMU_LUT139H,GFXMMU LUT entry 139 high" hexmask.long.tbyte 0x45C 0.--17. 1. "LO,Line offset" line.long 0x460 "GFXMMU_LUT140L,GFXMMU LUT entry 140 low" hexmask.long.byte 0x460 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x460 8.--15. 1. "FVB,First valid block" bitfld.long 0x460 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x464 "GFXMMU_LUT140H,GFXMMU LUT entry 140 high" hexmask.long.tbyte 0x464 0.--17. 1. "LO,Line offset" line.long 0x468 "GFXMMU_LUT141L,GFXMMU LUT entry 141 low" hexmask.long.byte 0x468 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x468 8.--15. 1. "FVB,First valid block" bitfld.long 0x468 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x46C "GFXMMU_LUT141H,GFXMMU LUT entry 141 high" hexmask.long.tbyte 0x46C 0.--17. 1. "LO,Line offset" line.long 0x470 "GFXMMU_LUT142L,GFXMMU LUT entry 142 low" hexmask.long.byte 0x470 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x470 8.--15. 1. "FVB,First valid block" bitfld.long 0x470 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x474 "GFXMMU_LUT142H,GFXMMU LUT entry 142 high" hexmask.long.tbyte 0x474 0.--17. 1. "LO,Line offset" line.long 0x478 "GFXMMU_LUT143L,GFXMMU LUT entry 143 low" hexmask.long.byte 0x478 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x478 8.--15. 1. "FVB,First valid block" bitfld.long 0x478 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x47C "GFXMMU_LUT143H,GFXMMU LUT entry 143 high" hexmask.long.tbyte 0x47C 0.--17. 1. "LO,Line offset" line.long 0x480 "GFXMMU_LUT144L,GFXMMU LUT entry 144 low" hexmask.long.byte 0x480 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x480 8.--15. 1. "FVB,First valid block" bitfld.long 0x480 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x484 "GFXMMU_LUT144H,GFXMMU LUT entry 144 high" hexmask.long.tbyte 0x484 0.--17. 1. "LO,Line offset" line.long 0x488 "GFXMMU_LUT145L,GFXMMU LUT entry 145 low" hexmask.long.byte 0x488 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x488 8.--15. 1. "FVB,First valid block" bitfld.long 0x488 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x48C "GFXMMU_LUT145H,GFXMMU LUT entry 145 high" hexmask.long.tbyte 0x48C 0.--17. 1. "LO,Line offset" line.long 0x490 "GFXMMU_LUT146L,GFXMMU LUT entry 146 low" hexmask.long.byte 0x490 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x490 8.--15. 1. "FVB,First valid block" bitfld.long 0x490 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x494 "GFXMMU_LUT146H,GFXMMU LUT entry 146 high" hexmask.long.tbyte 0x494 0.--17. 1. "LO,Line offset" line.long 0x498 "GFXMMU_LUT147L,GFXMMU LUT entry 147 low" hexmask.long.byte 0x498 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x498 8.--15. 1. "FVB,First valid block" bitfld.long 0x498 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x49C "GFXMMU_LUT147H,GFXMMU LUT entry 147 high" hexmask.long.tbyte 0x49C 0.--17. 1. "LO,Line offset" line.long 0x4A0 "GFXMMU_LUT148L,GFXMMU LUT entry 148 low" hexmask.long.byte 0x4A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4A4 "GFXMMU_LUT148H,GFXMMU LUT entry 148 high" hexmask.long.tbyte 0x4A4 0.--17. 1. "LO,Line offset" line.long 0x4A8 "GFXMMU_LUT149L,GFXMMU LUT entry 149 low" hexmask.long.byte 0x4A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4AC "GFXMMU_LUT149H,GFXMMU LUT entry 149 high" hexmask.long.tbyte 0x4AC 0.--17. 1. "LO,Line offset" line.long 0x4B0 "GFXMMU_LUT150L,GFXMMU LUT entry 150 low" hexmask.long.byte 0x4B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4B4 "GFXMMU_LUT150H,GFXMMU LUT entry 150 high" hexmask.long.tbyte 0x4B4 0.--17. 1. "LO,Line offset" line.long 0x4B8 "GFXMMU_LUT151L,GFXMMU LUT entry 151 low" hexmask.long.byte 0x4B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4BC "GFXMMU_LUT151H,GFXMMU LUT entry 151 high" hexmask.long.tbyte 0x4BC 0.--17. 1. "LO,Line offset" line.long 0x4C0 "GFXMMU_LUT152L,GFXMMU LUT entry 152 low" hexmask.long.byte 0x4C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C4 "GFXMMU_LUT152H,GFXMMU LUT entry 152 high" hexmask.long.tbyte 0x4C4 0.--17. 1. "LO,Line offset" line.long 0x4C8 "GFXMMU_LUT153L,GFXMMU LUT entry 153 low" hexmask.long.byte 0x4C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4CC "GFXMMU_LUT153H,GFXMMU LUT entry 153 high" hexmask.long.tbyte 0x4CC 0.--17. 1. "LO,Line offset" line.long 0x4D0 "GFXMMU_LUT154L,GFXMMU LUT entry 154 low" hexmask.long.byte 0x4D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4D4 "GFXMMU_LUT154H,GFXMMU LUT entry 154 high" hexmask.long.tbyte 0x4D4 0.--17. 1. "LO,Line offset" line.long 0x4D8 "GFXMMU_LUT155L,GFXMMU LUT entry 155 low" hexmask.long.byte 0x4D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4DC "GFXMMU_LUT155H,GFXMMU LUT entry 155 high" hexmask.long.tbyte 0x4DC 0.--17. 1. "LO,Line offset" line.long 0x4E0 "GFXMMU_LUT156L,GFXMMU LUT entry 156 low" hexmask.long.byte 0x4E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4E4 "GFXMMU_LUT156H,GFXMMU LUT entry 156 high" hexmask.long.tbyte 0x4E4 0.--17. 1. "LO,Line offset" line.long 0x4E8 "GFXMMU_LUT157L,GFXMMU LUT entry 157 low" hexmask.long.byte 0x4E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4EC "GFXMMU_LUT157H,GFXMMU LUT entry 157 high" hexmask.long.tbyte 0x4EC 0.--17. 1. "LO,Line offset" line.long 0x4F0 "GFXMMU_LUT158L,GFXMMU LUT entry 158 low" hexmask.long.byte 0x4F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4F4 "GFXMMU_LUT158H,GFXMMU LUT entry 158 high" hexmask.long.tbyte 0x4F4 0.--17. 1. "LO,Line offset" line.long 0x4F8 "GFXMMU_LUT159L,GFXMMU LUT entry 159 low" hexmask.long.byte 0x4F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4FC "GFXMMU_LUT159H,GFXMMU LUT entry 159 high" hexmask.long.tbyte 0x4FC 0.--17. 1. "LO,Line offset" line.long 0x500 "GFXMMU_LUT160L,GFXMMU LUT entry 160 low" hexmask.long.byte 0x500 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x500 8.--15. 1. "FVB,First valid block" bitfld.long 0x500 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x504 "GFXMMU_LUT160H,GFXMMU LUT entry 160 high" hexmask.long.tbyte 0x504 0.--17. 1. "LO,Line offset" line.long 0x508 "GFXMMU_LUT161L,GFXMMU LUT entry 161 low" hexmask.long.byte 0x508 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x508 8.--15. 1. "FVB,First valid block" bitfld.long 0x508 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x50C "GFXMMU_LUT161H,GFXMMU LUT entry 161 high" hexmask.long.tbyte 0x50C 0.--17. 1. "LO,Line offset" line.long 0x510 "GFXMMU_LUT162L,GFXMMU LUT entry 162 low" hexmask.long.byte 0x510 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x510 8.--15. 1. "FVB,First valid block" bitfld.long 0x510 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x514 "GFXMMU_LUT162H,GFXMMU LUT entry 162 high" hexmask.long.tbyte 0x514 0.--17. 1. "LO,Line offset" line.long 0x518 "GFXMMU_LUT163L,GFXMMU LUT entry 163 low" hexmask.long.byte 0x518 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x518 8.--15. 1. "FVB,First valid block" bitfld.long 0x518 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x51C "GFXMMU_LUT163H,GFXMMU LUT entry 163 high" hexmask.long.tbyte 0x51C 0.--17. 1. "LO,Line offset" line.long 0x520 "GFXMMU_LUT164L,GFXMMU LUT entry 164 low" hexmask.long.byte 0x520 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x520 8.--15. 1. "FVB,First valid block" bitfld.long 0x520 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x524 "GFXMMU_LUT164H,GFXMMU LUT entry 164 high" hexmask.long.tbyte 0x524 0.--17. 1. "LO,Line offset" line.long 0x528 "GFXMMU_LUT165L,GFXMMU LUT entry 165 low" hexmask.long.byte 0x528 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x528 8.--15. 1. "FVB,First valid block" bitfld.long 0x528 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x52C "GFXMMU_LUT165H,GFXMMU LUT entry 165 high" hexmask.long.tbyte 0x52C 0.--17. 1. "LO,Line offset" line.long 0x530 "GFXMMU_LUT166L,GFXMMU LUT entry 166 low" hexmask.long.byte 0x530 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x530 8.--15. 1. "FVB,First valid block" bitfld.long 0x530 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x534 "GFXMMU_LUT166H,GFXMMU LUT entry 166 high" hexmask.long.tbyte 0x534 0.--17. 1. "LO,Line offset" line.long 0x538 "GFXMMU_LUT167L,GFXMMU LUT entry 167 low" hexmask.long.byte 0x538 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x538 8.--15. 1. "FVB,First valid block" bitfld.long 0x538 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x53C "GFXMMU_LUT167H,GFXMMU LUT entry 167 high" hexmask.long.tbyte 0x53C 0.--17. 1. "LO,Line offset" line.long 0x540 "GFXMMU_LUT168L,GFXMMU LUT entry 168 low" hexmask.long.byte 0x540 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x540 8.--15. 1. "FVB,First valid block" bitfld.long 0x540 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x544 "GFXMMU_LUT168H,GFXMMU LUT entry 168 high" hexmask.long.tbyte 0x544 0.--17. 1. "LO,Line offset" line.long 0x548 "GFXMMU_LUT169L,GFXMMU LUT entry 169 low" hexmask.long.byte 0x548 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x548 8.--15. 1. "FVB,First valid block" bitfld.long 0x548 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54C "GFXMMU_LUT169H,GFXMMU LUT entry 169 high" hexmask.long.tbyte 0x54C 0.--17. 1. "LO,Line offset" line.long 0x550 "GFXMMU_LUT170L,GFXMMU LUT entry 170 low" hexmask.long.byte 0x550 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x550 8.--15. 1. "FVB,First valid block" bitfld.long 0x550 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x554 "GFXMMU_LUT170H,GFXMMU LUT entry 170 high" hexmask.long.tbyte 0x554 0.--17. 1. "LO,Line offset" line.long 0x558 "GFXMMU_LUT171L,GFXMMU LUT entry 171 low" hexmask.long.byte 0x558 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x558 8.--15. 1. "FVB,First valid block" bitfld.long 0x558 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x55C "GFXMMU_LUT171H,GFXMMU LUT entry 171 high" hexmask.long.tbyte 0x55C 0.--17. 1. "LO,Line offset" line.long 0x560 "GFXMMU_LUT172L,GFXMMU LUT entry 172 low" hexmask.long.byte 0x560 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x560 8.--15. 1. "FVB,First valid block" bitfld.long 0x560 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x564 "GFXMMU_LUT172H,GFXMMU LUT entry 172 high" hexmask.long.tbyte 0x564 0.--17. 1. "LO,Line offset" line.long 0x568 "GFXMMU_LUT173L,GFXMMU LUT entry 173 low" hexmask.long.byte 0x568 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x568 8.--15. 1. "FVB,First valid block" bitfld.long 0x568 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x56C "GFXMMU_LUT173H,GFXMMU LUT entry 173 high" hexmask.long.tbyte 0x56C 0.--17. 1. "LO,Line offset" line.long 0x570 "GFXMMU_LUT174L,GFXMMU LUT entry 174 low" hexmask.long.byte 0x570 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x570 8.--15. 1. "FVB,First valid block" bitfld.long 0x570 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x574 "GFXMMU_LUT174H,GFXMMU LUT entry 174 high" hexmask.long.tbyte 0x574 0.--17. 1. "LO,Line offset" line.long 0x578 "GFXMMU_LUT175L,GFXMMU LUT entry 175 low" hexmask.long.byte 0x578 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x578 8.--15. 1. "FVB,First valid block" bitfld.long 0x578 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x57C "GFXMMU_LUT175H,GFXMMU LUT entry 175 high" hexmask.long.tbyte 0x57C 0.--17. 1. "LO,Line offset" line.long 0x580 "GFXMMU_LUT176L,GFXMMU LUT entry 176 low" hexmask.long.byte 0x580 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x580 8.--15. 1. "FVB,First valid block" bitfld.long 0x580 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x584 "GFXMMU_LUT176H,GFXMMU LUT entry 176 high" hexmask.long.tbyte 0x584 0.--17. 1. "LO,Line offset" line.long 0x588 "GFXMMU_LUT177L,GFXMMU LUT entry 177 low" hexmask.long.byte 0x588 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x588 8.--15. 1. "FVB,First valid block" bitfld.long 0x588 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x58C "GFXMMU_LUT177H,GFXMMU LUT entry 177 high" hexmask.long.tbyte 0x58C 0.--17. 1. "LO,Line offset" line.long 0x590 "GFXMMU_LUT178L,GFXMMU LUT entry 178 low" hexmask.long.byte 0x590 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x590 8.--15. 1. "FVB,First valid block" bitfld.long 0x590 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x594 "GFXMMU_LUT178H,GFXMMU LUT entry 178 high" hexmask.long.tbyte 0x594 0.--17. 1. "LO,Line offset" line.long 0x598 "GFXMMU_LUT179L,GFXMMU LUT entry 179 low" hexmask.long.byte 0x598 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x598 8.--15. 1. "FVB,First valid block" bitfld.long 0x598 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x59C "GFXMMU_LUT179H,GFXMMU LUT entry 179 high" hexmask.long.tbyte 0x59C 0.--17. 1. "LO,Line offset" line.long 0x5A0 "GFXMMU_LUT180L,GFXMMU LUT entry 180 low" hexmask.long.byte 0x5A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5A4 "GFXMMU_LUT180H,GFXMMU LUT entry 180 high" hexmask.long.tbyte 0x5A4 0.--17. 1. "LO,Line offset" line.long 0x5A8 "GFXMMU_LUT181L,GFXMMU LUT entry 181 low" hexmask.long.byte 0x5A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5AC "GFXMMU_LUT181H,GFXMMU LUT entry 181 high" hexmask.long.tbyte 0x5AC 0.--17. 1. "LO,Line offset" line.long 0x5B0 "GFXMMU_LUT182L,GFXMMU LUT entry 182 low" hexmask.long.byte 0x5B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5B4 "GFXMMU_LUT182H,GFXMMU LUT entry 182 high" hexmask.long.tbyte 0x5B4 0.--17. 1. "LO,Line offset" line.long 0x5B8 "GFXMMU_LUT183L,GFXMMU LUT entry 183 low" hexmask.long.byte 0x5B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5BC "GFXMMU_LUT183H,GFXMMU LUT entry 183 high" hexmask.long.tbyte 0x5BC 0.--17. 1. "LO,Line offset" line.long 0x5C0 "GFXMMU_LUT184L,GFXMMU LUT entry 184 low" hexmask.long.byte 0x5C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C4 "GFXMMU_LUT184H,GFXMMU LUT entry 184 high" hexmask.long.tbyte 0x5C4 0.--17. 1. "LO,Line offset" line.long 0x5C8 "GFXMMU_LUT185L,GFXMMU LUT entry 185 low" hexmask.long.byte 0x5C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5CC "GFXMMU_LUT185H,GFXMMU LUT entry 185 high" hexmask.long.tbyte 0x5CC 0.--17. 1. "LO,Line offset" line.long 0x5D0 "GFXMMU_LUT186L,GFXMMU LUT entry 186 low" hexmask.long.byte 0x5D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5D4 "GFXMMU_LUT186H,GFXMMU LUT entry 186 high" hexmask.long.tbyte 0x5D4 0.--17. 1. "LO,Line offset" line.long 0x5D8 "GFXMMU_LUT187L,GFXMMU LUT entry 187 low" hexmask.long.byte 0x5D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5DC "GFXMMU_LUT187H,GFXMMU LUT entry 187 high" hexmask.long.tbyte 0x5DC 0.--17. 1. "LO,Line offset" line.long 0x5E0 "GFXMMU_LUT188L,GFXMMU LUT entry 188 low" hexmask.long.byte 0x5E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5E4 "GFXMMU_LUT188H,GFXMMU LUT entry 188 high" hexmask.long.tbyte 0x5E4 0.--17. 1. "LO,Line offset" line.long 0x5E8 "GFXMMU_LUT189L,GFXMMU LUT entry 189 low" hexmask.long.byte 0x5E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5EC "GFXMMU_LUT189H,GFXMMU LUT entry 189 high" hexmask.long.tbyte 0x5EC 0.--17. 1. "LO,Line offset" line.long 0x5F0 "GFXMMU_LUT190L,GFXMMU LUT entry 190 low" hexmask.long.byte 0x5F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5F4 "GFXMMU_LUT190H,GFXMMU LUT entry 190 high" hexmask.long.tbyte 0x5F4 0.--17. 1. "LO,Line offset" line.long 0x5F8 "GFXMMU_LUT191L,GFXMMU LUT entry 191 low" hexmask.long.byte 0x5F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5FC "GFXMMU_LUT191H,GFXMMU LUT entry 191 high" hexmask.long.tbyte 0x5FC 0.--17. 1. "LO,Line offset" line.long 0x600 "GFXMMU_LUT192L,GFXMMU LUT entry 192 low" hexmask.long.byte 0x600 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x600 8.--15. 1. "FVB,First valid block" bitfld.long 0x600 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x604 "GFXMMU_LUT192H,GFXMMU LUT entry 192 high" hexmask.long.tbyte 0x604 0.--17. 1. "LO,Line offset" line.long 0x608 "GFXMMU_LUT193L,GFXMMU LUT entry 193 low" hexmask.long.byte 0x608 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x608 8.--15. 1. "FVB,First valid block" bitfld.long 0x608 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x60C "GFXMMU_LUT193H,GFXMMU LUT entry 193 high" hexmask.long.tbyte 0x60C 0.--17. 1. "LO,Line offset" line.long 0x610 "GFXMMU_LUT194L,GFXMMU LUT entry 194 low" hexmask.long.byte 0x610 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x610 8.--15. 1. "FVB,First valid block" bitfld.long 0x610 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x614 "GFXMMU_LUT194H,GFXMMU LUT entry 194 high" hexmask.long.tbyte 0x614 0.--17. 1. "LO,Line offset" line.long 0x618 "GFXMMU_LUT195L,GFXMMU LUT entry 195 low" hexmask.long.byte 0x618 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x618 8.--15. 1. "FVB,First valid block" bitfld.long 0x618 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x61C "GFXMMU_LUT195H,GFXMMU LUT entry 195 high" hexmask.long.tbyte 0x61C 0.--17. 1. "LO,Line offset" line.long 0x620 "GFXMMU_LUT196L,GFXMMU LUT entry 196 low" hexmask.long.byte 0x620 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x620 8.--15. 1. "FVB,First valid block" bitfld.long 0x620 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x624 "GFXMMU_LUT196H,GFXMMU LUT entry 196 high" hexmask.long.tbyte 0x624 0.--17. 1. "LO,Line offset" line.long 0x628 "GFXMMU_LUT197L,GFXMMU LUT entry 197 low" hexmask.long.byte 0x628 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x628 8.--15. 1. "FVB,First valid block" bitfld.long 0x628 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x62C "GFXMMU_LUT197H,GFXMMU LUT entry 197 high" hexmask.long.tbyte 0x62C 0.--17. 1. "LO,Line offset" line.long 0x630 "GFXMMU_LUT198L,GFXMMU LUT entry 198 low" hexmask.long.byte 0x630 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x630 8.--15. 1. "FVB,First valid block" bitfld.long 0x630 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x634 "GFXMMU_LUT198H,GFXMMU LUT entry 198 high" hexmask.long.tbyte 0x634 0.--17. 1. "LO,Line offset" line.long 0x638 "GFXMMU_LUT199L,GFXMMU LUT entry 199 low" hexmask.long.byte 0x638 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x638 8.--15. 1. "FVB,First valid block" bitfld.long 0x638 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x63C "GFXMMU_LUT199H,GFXMMU LUT entry 199 high" hexmask.long.tbyte 0x63C 0.--17. 1. "LO,Line offset" line.long 0x640 "GFXMMU_LUT200L,GFXMMU LUT entry 200 low" hexmask.long.byte 0x640 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x640 8.--15. 1. "FVB,First valid block" bitfld.long 0x640 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x644 "GFXMMU_LUT200H,GFXMMU LUT entry 200 high" hexmask.long.tbyte 0x644 0.--17. 1. "LO,Line offset" line.long 0x648 "GFXMMU_LUT201L,GFXMMU LUT entry 201 low" hexmask.long.byte 0x648 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x648 8.--15. 1. "FVB,First valid block" bitfld.long 0x648 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64C "GFXMMU_LUT201H,GFXMMU LUT entry 201 high" hexmask.long.tbyte 0x64C 0.--17. 1. "LO,Line offset" line.long 0x650 "GFXMMU_LUT202L,GFXMMU LUT entry 202 low" hexmask.long.byte 0x650 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x650 8.--15. 1. "FVB,First valid block" bitfld.long 0x650 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x654 "GFXMMU_LUT202H,GFXMMU LUT entry 202 high" hexmask.long.tbyte 0x654 0.--17. 1. "LO,Line offset" line.long 0x658 "GFXMMU_LUT203L,GFXMMU LUT entry 203 low" hexmask.long.byte 0x658 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x658 8.--15. 1. "FVB,First valid block" bitfld.long 0x658 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x65C "GFXMMU_LUT203H,GFXMMU LUT entry 203 high" hexmask.long.tbyte 0x65C 0.--17. 1. "LO,Line offset" line.long 0x660 "GFXMMU_LUT204L,GFXMMU LUT entry 204 low" hexmask.long.byte 0x660 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x660 8.--15. 1. "FVB,First valid block" bitfld.long 0x660 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x664 "GFXMMU_LUT204H,GFXMMU LUT entry 204 high" hexmask.long.tbyte 0x664 0.--17. 1. "LO,Line offset" line.long 0x668 "GFXMMU_LUT205L,GFXMMU LUT entry 205 low" hexmask.long.byte 0x668 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x668 8.--15. 1. "FVB,First valid block" bitfld.long 0x668 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x66C "GFXMMU_LUT205H,GFXMMU LUT entry 205 high" hexmask.long.tbyte 0x66C 0.--17. 1. "LO,Line offset" line.long 0x670 "GFXMMU_LUT206L,GFXMMU LUT entry 206 low" hexmask.long.byte 0x670 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x670 8.--15. 1. "FVB,First valid block" bitfld.long 0x670 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x674 "GFXMMU_LUT206H,GFXMMU LUT entry 206 high" hexmask.long.tbyte 0x674 0.--17. 1. "LO,Line offset" line.long 0x678 "GFXMMU_LUT207L,GFXMMU LUT entry 207 low" hexmask.long.byte 0x678 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x678 8.--15. 1. "FVB,First valid block" bitfld.long 0x678 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x67C "GFXMMU_LUT207H,GFXMMU LUT entry 207 high" hexmask.long.tbyte 0x67C 0.--17. 1. "LO,Line offset" line.long 0x680 "GFXMMU_LUT208L,GFXMMU LUT entry 208 low" hexmask.long.byte 0x680 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x680 8.--15. 1. "FVB,First valid block" bitfld.long 0x680 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x684 "GFXMMU_LUT208H,GFXMMU LUT entry 208 high" hexmask.long.tbyte 0x684 0.--17. 1. "LO,Line offset" line.long 0x688 "GFXMMU_LUT209L,GFXMMU LUT entry 209 low" hexmask.long.byte 0x688 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x688 8.--15. 1. "FVB,First valid block" bitfld.long 0x688 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x68C "GFXMMU_LUT209H,GFXMMU LUT entry 209 high" hexmask.long.tbyte 0x68C 0.--17. 1. "LO,Line offset" line.long 0x690 "GFXMMU_LUT210L,GFXMMU LUT entry 210 low" hexmask.long.byte 0x690 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x690 8.--15. 1. "FVB,First valid block" bitfld.long 0x690 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x694 "GFXMMU_LUT210H,GFXMMU LUT entry 210 high" hexmask.long.tbyte 0x694 0.--17. 1. "LO,Line offset" line.long 0x698 "GFXMMU_LUT211L,GFXMMU LUT entry 211 low" hexmask.long.byte 0x698 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x698 8.--15. 1. "FVB,First valid block" bitfld.long 0x698 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x69C "GFXMMU_LUT211H,GFXMMU LUT entry 211 high" hexmask.long.tbyte 0x69C 0.--17. 1. "LO,Line offset" line.long 0x6A0 "GFXMMU_LUT212L,GFXMMU LUT entry 212 low" hexmask.long.byte 0x6A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6A4 "GFXMMU_LUT212H,GFXMMU LUT entry 212 high" hexmask.long.tbyte 0x6A4 0.--17. 1. "LO,Line offset" line.long 0x6A8 "GFXMMU_LUT213L,GFXMMU LUT entry 213 low" hexmask.long.byte 0x6A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6AC "GFXMMU_LUT213H,GFXMMU LUT entry 213 high" hexmask.long.tbyte 0x6AC 0.--17. 1. "LO,Line offset" line.long 0x6B0 "GFXMMU_LUT214L,GFXMMU LUT entry 214 low" hexmask.long.byte 0x6B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6B4 "GFXMMU_LUT214H,GFXMMU LUT entry 214 high" hexmask.long.tbyte 0x6B4 0.--17. 1. "LO,Line offset" line.long 0x6B8 "GFXMMU_LUT215L,GFXMMU LUT entry 215 low" hexmask.long.byte 0x6B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6BC "GFXMMU_LUT215H,GFXMMU LUT entry 215 high" hexmask.long.tbyte 0x6BC 0.--17. 1. "LO,Line offset" line.long 0x6C0 "GFXMMU_LUT216L,GFXMMU LUT entry 216 low" hexmask.long.byte 0x6C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C4 "GFXMMU_LUT216H,GFXMMU LUT entry 216 high" hexmask.long.tbyte 0x6C4 0.--17. 1. "LO,Line offset" line.long 0x6C8 "GFXMMU_LUT217L,GFXMMU LUT entry 217 low" hexmask.long.byte 0x6C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6CC "GFXMMU_LUT217H,GFXMMU LUT entry 217 high" hexmask.long.tbyte 0x6CC 0.--17. 1. "LO,Line offset" line.long 0x6D0 "GFXMMU_LUT218L,GFXMMU LUT entry 218 low" hexmask.long.byte 0x6D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6D4 "GFXMMU_LUT218H,GFXMMU LUT entry 218 high" hexmask.long.tbyte 0x6D4 0.--17. 1. "LO,Line offset" line.long 0x6D8 "GFXMMU_LUT219L,GFXMMU LUT entry 219 low" hexmask.long.byte 0x6D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6DC "GFXMMU_LUT219H,GFXMMU LUT entry 219 high" hexmask.long.tbyte 0x6DC 0.--17. 1. "LO,Line offset" line.long 0x6E0 "GFXMMU_LUT220L,GFXMMU LUT entry 220 low" hexmask.long.byte 0x6E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6E4 "GFXMMU_LUT220H,GFXMMU LUT entry 220 high" hexmask.long.tbyte 0x6E4 0.--17. 1. "LO,Line offset" line.long 0x6E8 "GFXMMU_LUT221L,GFXMMU LUT entry 221 low" hexmask.long.byte 0x6E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6EC "GFXMMU_LUT221H,GFXMMU LUT entry 221 high" hexmask.long.tbyte 0x6EC 0.--17. 1. "LO,Line offset" line.long 0x6F0 "GFXMMU_LUT222L,GFXMMU LUT entry 222 low" hexmask.long.byte 0x6F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6F4 "GFXMMU_LUT222H,GFXMMU LUT entry 222 high" hexmask.long.tbyte 0x6F4 0.--17. 1. "LO,Line offset" line.long 0x6F8 "GFXMMU_LUT223L,GFXMMU LUT entry 223 low" hexmask.long.byte 0x6F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6FC "GFXMMU_LUT223H,GFXMMU LUT entry 223 high" hexmask.long.tbyte 0x6FC 0.--17. 1. "LO,Line offset" line.long 0x700 "GFXMMU_LUT224L,GFXMMU LUT entry 224 low" hexmask.long.byte 0x700 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x700 8.--15. 1. "FVB,First valid block" bitfld.long 0x700 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x704 "GFXMMU_LUT224H,GFXMMU LUT entry 224 high" hexmask.long.tbyte 0x704 0.--17. 1. "LO,Line offset" line.long 0x708 "GFXMMU_LUT225L,GFXMMU LUT entry 225 low" hexmask.long.byte 0x708 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x708 8.--15. 1. "FVB,First valid block" bitfld.long 0x708 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x70C "GFXMMU_LUT225H,GFXMMU LUT entry 225 high" hexmask.long.tbyte 0x70C 0.--17. 1. "LO,Line offset" line.long 0x710 "GFXMMU_LUT226L,GFXMMU LUT entry 226 low" hexmask.long.byte 0x710 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x710 8.--15. 1. "FVB,First valid block" bitfld.long 0x710 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x714 "GFXMMU_LUT226H,GFXMMU LUT entry 226 high" hexmask.long.tbyte 0x714 0.--17. 1. "LO,Line offset" line.long 0x718 "GFXMMU_LUT227L,GFXMMU LUT entry 227 low" hexmask.long.byte 0x718 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x718 8.--15. 1. "FVB,First valid block" bitfld.long 0x718 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x71C "GFXMMU_LUT227H,GFXMMU LUT entry 227 high" hexmask.long.tbyte 0x71C 0.--17. 1. "LO,Line offset" line.long 0x720 "GFXMMU_LUT228L,GFXMMU LUT entry 228 low" hexmask.long.byte 0x720 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x720 8.--15. 1. "FVB,First valid block" bitfld.long 0x720 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x724 "GFXMMU_LUT228H,GFXMMU LUT entry 228 high" hexmask.long.tbyte 0x724 0.--17. 1. "LO,Line offset" line.long 0x728 "GFXMMU_LUT229L,GFXMMU LUT entry 229 low" hexmask.long.byte 0x728 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x728 8.--15. 1. "FVB,First valid block" bitfld.long 0x728 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x72C "GFXMMU_LUT229H,GFXMMU LUT entry 229 high" hexmask.long.tbyte 0x72C 0.--17. 1. "LO,Line offset" line.long 0x730 "GFXMMU_LUT230L,GFXMMU LUT entry 230 low" hexmask.long.byte 0x730 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x730 8.--15. 1. "FVB,First valid block" bitfld.long 0x730 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x734 "GFXMMU_LUT230H,GFXMMU LUT entry 230 high" hexmask.long.tbyte 0x734 0.--17. 1. "LO,Line offset" line.long 0x738 "GFXMMU_LUT231L,GFXMMU LUT entry 231 low" hexmask.long.byte 0x738 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x738 8.--15. 1. "FVB,First valid block" bitfld.long 0x738 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x73C "GFXMMU_LUT231H,GFXMMU LUT entry 231 high" hexmask.long.tbyte 0x73C 0.--17. 1. "LO,Line offset" line.long 0x740 "GFXMMU_LUT232L,GFXMMU LUT entry 232 low" hexmask.long.byte 0x740 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x740 8.--15. 1. "FVB,First valid block" bitfld.long 0x740 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x744 "GFXMMU_LUT232H,GFXMMU LUT entry 232 high" hexmask.long.tbyte 0x744 0.--17. 1. "LO,Line offset" line.long 0x748 "GFXMMU_LUT233L,GFXMMU LUT entry 233 low" hexmask.long.byte 0x748 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x748 8.--15. 1. "FVB,First valid block" bitfld.long 0x748 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74C "GFXMMU_LUT233H,GFXMMU LUT entry 233 high" hexmask.long.tbyte 0x74C 0.--17. 1. "LO,Line offset" line.long 0x750 "GFXMMU_LUT234L,GFXMMU LUT entry 234 low" hexmask.long.byte 0x750 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x750 8.--15. 1. "FVB,First valid block" bitfld.long 0x750 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x754 "GFXMMU_LUT234H,GFXMMU LUT entry 234 high" hexmask.long.tbyte 0x754 0.--17. 1. "LO,Line offset" line.long 0x758 "GFXMMU_LUT235L,GFXMMU LUT entry 235 low" hexmask.long.byte 0x758 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x758 8.--15. 1. "FVB,First valid block" bitfld.long 0x758 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x75C "GFXMMU_LUT235H,GFXMMU LUT entry 235 high" hexmask.long.tbyte 0x75C 0.--17. 1. "LO,Line offset" line.long 0x760 "GFXMMU_LUT236L,GFXMMU LUT entry 236 low" hexmask.long.byte 0x760 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x760 8.--15. 1. "FVB,First valid block" bitfld.long 0x760 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x764 "GFXMMU_LUT236H,GFXMMU LUT entry 236 high" hexmask.long.tbyte 0x764 0.--17. 1. "LO,Line offset" line.long 0x768 "GFXMMU_LUT237L,GFXMMU LUT entry 237 low" hexmask.long.byte 0x768 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x768 8.--15. 1. "FVB,First valid block" bitfld.long 0x768 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x76C "GFXMMU_LUT237H,GFXMMU LUT entry 237 high" hexmask.long.tbyte 0x76C 0.--17. 1. "LO,Line offset" line.long 0x770 "GFXMMU_LUT238L,GFXMMU LUT entry 238 low" hexmask.long.byte 0x770 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x770 8.--15. 1. "FVB,First valid block" bitfld.long 0x770 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x774 "GFXMMU_LUT238H,GFXMMU LUT entry 238 high" hexmask.long.tbyte 0x774 0.--17. 1. "LO,Line offset" line.long 0x778 "GFXMMU_LUT239L,GFXMMU LUT entry 239 low" hexmask.long.byte 0x778 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x778 8.--15. 1. "FVB,First valid block" bitfld.long 0x778 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x77C "GFXMMU_LUT239H,GFXMMU LUT entry 239 high" hexmask.long.tbyte 0x77C 0.--17. 1. "LO,Line offset" line.long 0x780 "GFXMMU_LUT240L,GFXMMU LUT entry 240 low" hexmask.long.byte 0x780 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x780 8.--15. 1. "FVB,First valid block" bitfld.long 0x780 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x784 "GFXMMU_LUT240H,GFXMMU LUT entry 240 high" hexmask.long.tbyte 0x784 0.--17. 1. "LO,Line offset" line.long 0x788 "GFXMMU_LUT241L,GFXMMU LUT entry 241 low" hexmask.long.byte 0x788 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x788 8.--15. 1. "FVB,First valid block" bitfld.long 0x788 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x78C "GFXMMU_LUT241H,GFXMMU LUT entry 241 high" hexmask.long.tbyte 0x78C 0.--17. 1. "LO,Line offset" line.long 0x790 "GFXMMU_LUT242L,GFXMMU LUT entry 242 low" hexmask.long.byte 0x790 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x790 8.--15. 1. "FVB,First valid block" bitfld.long 0x790 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x794 "GFXMMU_LUT242H,GFXMMU LUT entry 242 high" hexmask.long.tbyte 0x794 0.--17. 1. "LO,Line offset" line.long 0x798 "GFXMMU_LUT243L,GFXMMU LUT entry 243 low" hexmask.long.byte 0x798 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x798 8.--15. 1. "FVB,First valid block" bitfld.long 0x798 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x79C "GFXMMU_LUT243H,GFXMMU LUT entry 243 high" hexmask.long.tbyte 0x79C 0.--17. 1. "LO,Line offset" line.long 0x7A0 "GFXMMU_LUT244L,GFXMMU LUT entry 244 low" hexmask.long.byte 0x7A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7A4 "GFXMMU_LUT244H,GFXMMU LUT entry 244 high" hexmask.long.tbyte 0x7A4 0.--17. 1. "LO,Line offset" line.long 0x7A8 "GFXMMU_LUT245L,GFXMMU LUT entry 245 low" hexmask.long.byte 0x7A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7AC "GFXMMU_LUT245H,GFXMMU LUT entry 245 high" hexmask.long.tbyte 0x7AC 0.--17. 1. "LO,Line offset" line.long 0x7B0 "GFXMMU_LUT246L,GFXMMU LUT entry 246 low" hexmask.long.byte 0x7B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7B4 "GFXMMU_LUT246H,GFXMMU LUT entry 246 high" hexmask.long.tbyte 0x7B4 0.--17. 1. "LO,Line offset" line.long 0x7B8 "GFXMMU_LUT247L,GFXMMU LUT entry 247 low" hexmask.long.byte 0x7B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7BC "GFXMMU_LUT247H,GFXMMU LUT entry 247 high" hexmask.long.tbyte 0x7BC 0.--17. 1. "LO,Line offset" line.long 0x7C0 "GFXMMU_LUT248L,GFXMMU LUT entry 248 low" hexmask.long.byte 0x7C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C4 "GFXMMU_LUT248H,GFXMMU LUT entry 248 high" hexmask.long.tbyte 0x7C4 0.--17. 1. "LO,Line offset" line.long 0x7C8 "GFXMMU_LUT249L,GFXMMU LUT entry 249 low" hexmask.long.byte 0x7C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7CC "GFXMMU_LUT249H,GFXMMU LUT entry 249 high" hexmask.long.tbyte 0x7CC 0.--17. 1. "LO,Line offset" line.long 0x7D0 "GFXMMU_LUT250L,GFXMMU LUT entry 250 low" hexmask.long.byte 0x7D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7D4 "GFXMMU_LUT250H,GFXMMU LUT entry 250 high" hexmask.long.tbyte 0x7D4 0.--17. 1. "LO,Line offset" line.long 0x7D8 "GFXMMU_LUT251L,GFXMMU LUT entry 251 low" hexmask.long.byte 0x7D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7DC "GFXMMU_LUT251H,GFXMMU LUT entry 251 high" hexmask.long.tbyte 0x7DC 0.--17. 1. "LO,Line offset" line.long 0x7E0 "GFXMMU_LUT252L,GFXMMU LUT entry 252 low" hexmask.long.byte 0x7E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7E4 "GFXMMU_LUT252H,GFXMMU LUT entry 252 high" hexmask.long.tbyte 0x7E4 0.--17. 1. "LO,Line offset" line.long 0x7E8 "GFXMMU_LUT253L,GFXMMU LUT entry 253 low" hexmask.long.byte 0x7E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7EC "GFXMMU_LUT253H,GFXMMU LUT entry 253 high" hexmask.long.tbyte 0x7EC 0.--17. 1. "LO,Line offset" line.long 0x7F0 "GFXMMU_LUT254L,GFXMMU LUT entry 254 low" hexmask.long.byte 0x7F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7F4 "GFXMMU_LUT254H,GFXMMU LUT entry 254 high" hexmask.long.tbyte 0x7F4 0.--17. 1. "LO,Line offset" line.long 0x7F8 "GFXMMU_LUT255L,GFXMMU LUT entry 255 low" hexmask.long.byte 0x7F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7FC "GFXMMU_LUT255H,GFXMMU LUT entry 255 high" hexmask.long.tbyte 0x7FC 0.--17. 1. "LO,Line offset" line.long 0x800 "GFXMMU_LUT256L,GFXMMU LUT entry 256 low" hexmask.long.byte 0x800 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x800 8.--15. 1. "FVB,First valid block" bitfld.long 0x800 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x804 "GFXMMU_LUT256H,GFXMMU LUT entry 256 high" hexmask.long.tbyte 0x804 0.--17. 1. "LO,Line offset" line.long 0x808 "GFXMMU_LUT257L,GFXMMU LUT entry 257 low" hexmask.long.byte 0x808 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x808 8.--15. 1. "FVB,First valid block" bitfld.long 0x808 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x80C "GFXMMU_LUT257H,GFXMMU LUT entry 257 high" hexmask.long.tbyte 0x80C 0.--17. 1. "LO,Line offset" line.long 0x810 "GFXMMU_LUT258L,GFXMMU LUT entry 258 low" hexmask.long.byte 0x810 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x810 8.--15. 1. "FVB,First valid block" bitfld.long 0x810 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x814 "GFXMMU_LUT258H,GFXMMU LUT entry 258 high" hexmask.long.tbyte 0x814 0.--17. 1. "LO,Line offset" line.long 0x818 "GFXMMU_LUT259L,GFXMMU LUT entry 259 low" hexmask.long.byte 0x818 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x818 8.--15. 1. "FVB,First valid block" bitfld.long 0x818 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x81C "GFXMMU_LUT259H,GFXMMU LUT entry 259 high" hexmask.long.tbyte 0x81C 0.--17. 1. "LO,Line offset" line.long 0x820 "GFXMMU_LUT260L,GFXMMU LUT entry 260 low" hexmask.long.byte 0x820 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x820 8.--15. 1. "FVB,First valid block" bitfld.long 0x820 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x824 "GFXMMU_LUT260H,GFXMMU LUT entry 260 high" hexmask.long.tbyte 0x824 0.--17. 1. "LO,Line offset" line.long 0x828 "GFXMMU_LUT261L,GFXMMU LUT entry 261 low" hexmask.long.byte 0x828 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x828 8.--15. 1. "FVB,First valid block" bitfld.long 0x828 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x82C "GFXMMU_LUT261H,GFXMMU LUT entry 261 high" hexmask.long.tbyte 0x82C 0.--17. 1. "LO,Line offset" line.long 0x830 "GFXMMU_LUT262L,GFXMMU LUT entry 262 low" hexmask.long.byte 0x830 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x830 8.--15. 1. "FVB,First valid block" bitfld.long 0x830 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x834 "GFXMMU_LUT262H,GFXMMU LUT entry 262 high" hexmask.long.tbyte 0x834 0.--17. 1. "LO,Line offset" line.long 0x838 "GFXMMU_LUT263L,GFXMMU LUT entry 263 low" hexmask.long.byte 0x838 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x838 8.--15. 1. "FVB,First valid block" bitfld.long 0x838 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x83C "GFXMMU_LUT263H,GFXMMU LUT entry 263 high" hexmask.long.tbyte 0x83C 0.--17. 1. "LO,Line offset" line.long 0x840 "GFXMMU_LUT264L,GFXMMU LUT entry 264 low" hexmask.long.byte 0x840 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x840 8.--15. 1. "FVB,First valid block" bitfld.long 0x840 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x844 "GFXMMU_LUT264H,GFXMMU LUT entry 264 high" hexmask.long.tbyte 0x844 0.--17. 1. "LO,Line offset" line.long 0x848 "GFXMMU_LUT265L,GFXMMU LUT entry 265 low" hexmask.long.byte 0x848 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x848 8.--15. 1. "FVB,First valid block" bitfld.long 0x848 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84C "GFXMMU_LUT265H,GFXMMU LUT entry 265 high" hexmask.long.tbyte 0x84C 0.--17. 1. "LO,Line offset" line.long 0x850 "GFXMMU_LUT266L,GFXMMU LUT entry 266 low" hexmask.long.byte 0x850 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x850 8.--15. 1. "FVB,First valid block" bitfld.long 0x850 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x854 "GFXMMU_LUT266H,GFXMMU LUT entry 266 high" hexmask.long.tbyte 0x854 0.--17. 1. "LO,Line offset" line.long 0x858 "GFXMMU_LUT267L,GFXMMU LUT entry 267 low" hexmask.long.byte 0x858 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x858 8.--15. 1. "FVB,First valid block" bitfld.long 0x858 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x85C "GFXMMU_LUT267H,GFXMMU LUT entry 267 high" hexmask.long.tbyte 0x85C 0.--17. 1. "LO,Line offset" line.long 0x860 "GFXMMU_LUT268L,GFXMMU LUT entry 268 low" hexmask.long.byte 0x860 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x860 8.--15. 1. "FVB,First valid block" bitfld.long 0x860 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x864 "GFXMMU_LUT268H,GFXMMU LUT entry 268 high" hexmask.long.tbyte 0x864 0.--17. 1. "LO,Line offset" line.long 0x868 "GFXMMU_LUT269L,GFXMMU LUT entry 269 low" hexmask.long.byte 0x868 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x868 8.--15. 1. "FVB,First valid block" bitfld.long 0x868 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x86C "GFXMMU_LUT269H,GFXMMU LUT entry 269 high" hexmask.long.tbyte 0x86C 0.--17. 1. "LO,Line offset" line.long 0x870 "GFXMMU_LUT270L,GFXMMU LUT entry 270 low" hexmask.long.byte 0x870 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x870 8.--15. 1. "FVB,First valid block" bitfld.long 0x870 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x874 "GFXMMU_LUT270H,GFXMMU LUT entry 270 high" hexmask.long.tbyte 0x874 0.--17. 1. "LO,Line offset" line.long 0x878 "GFXMMU_LUT271L,GFXMMU LUT entry 271 low" hexmask.long.byte 0x878 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x878 8.--15. 1. "FVB,First valid block" bitfld.long 0x878 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x87C "GFXMMU_LUT271H,GFXMMU LUT entry 271 high" hexmask.long.tbyte 0x87C 0.--17. 1. "LO,Line offset" line.long 0x880 "GFXMMU_LUT272L,GFXMMU LUT entry 272 low" hexmask.long.byte 0x880 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x880 8.--15. 1. "FVB,First valid block" bitfld.long 0x880 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x884 "GFXMMU_LUT272H,GFXMMU LUT entry 272 high" hexmask.long.tbyte 0x884 0.--17. 1. "LO,Line offset" line.long 0x888 "GFXMMU_LUT273L,GFXMMU LUT entry 273 low" hexmask.long.byte 0x888 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x888 8.--15. 1. "FVB,First valid block" bitfld.long 0x888 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x88C "GFXMMU_LUT273H,GFXMMU LUT entry 273 high" hexmask.long.tbyte 0x88C 0.--17. 1. "LO,Line offset" line.long 0x890 "GFXMMU_LUT274L,GFXMMU LUT entry 274 low" hexmask.long.byte 0x890 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x890 8.--15. 1. "FVB,First valid block" bitfld.long 0x890 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x894 "GFXMMU_LUT274H,GFXMMU LUT entry 274 high" hexmask.long.tbyte 0x894 0.--17. 1. "LO,Line offset" line.long 0x898 "GFXMMU_LUT275L,GFXMMU LUT entry 275 low" hexmask.long.byte 0x898 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x898 8.--15. 1. "FVB,First valid block" bitfld.long 0x898 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x89C "GFXMMU_LUT275H,GFXMMU LUT entry 275 high" hexmask.long.tbyte 0x89C 0.--17. 1. "LO,Line offset" line.long 0x8A0 "GFXMMU_LUT276L,GFXMMU LUT entry 276 low" hexmask.long.byte 0x8A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8A4 "GFXMMU_LUT276H,GFXMMU LUT entry 276 high" hexmask.long.tbyte 0x8A4 0.--17. 1. "LO,Line offset" line.long 0x8A8 "GFXMMU_LUT277L,GFXMMU LUT entry 277 low" hexmask.long.byte 0x8A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8AC "GFXMMU_LUT277H,GFXMMU LUT entry 277 high" hexmask.long.tbyte 0x8AC 0.--17. 1. "LO,Line offset" line.long 0x8B0 "GFXMMU_LUT278L,GFXMMU LUT entry 278 low" hexmask.long.byte 0x8B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8B4 "GFXMMU_LUT278H,GFXMMU LUT entry 278 high" hexmask.long.tbyte 0x8B4 0.--17. 1. "LO,Line offset" line.long 0x8B8 "GFXMMU_LUT279L,GFXMMU LUT entry 279 low" hexmask.long.byte 0x8B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8BC "GFXMMU_LUT279H,GFXMMU LUT entry 279 high" hexmask.long.tbyte 0x8BC 0.--17. 1. "LO,Line offset" line.long 0x8C0 "GFXMMU_LUT280L,GFXMMU LUT entry 280 low" hexmask.long.byte 0x8C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C4 "GFXMMU_LUT280H,GFXMMU LUT entry 280 high" hexmask.long.tbyte 0x8C4 0.--17. 1. "LO,Line offset" line.long 0x8C8 "GFXMMU_LUT281L,GFXMMU LUT entry 281 low" hexmask.long.byte 0x8C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8CC "GFXMMU_LUT281H,GFXMMU LUT entry 281 high" hexmask.long.tbyte 0x8CC 0.--17. 1. "LO,Line offset" line.long 0x8D0 "GFXMMU_LUT282L,GFXMMU LUT entry 282 low" hexmask.long.byte 0x8D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8D4 "GFXMMU_LUT282H,GFXMMU LUT entry 282 high" hexmask.long.tbyte 0x8D4 0.--17. 1. "LO,Line offset" line.long 0x8D8 "GFXMMU_LUT283L,GFXMMU LUT entry 283 low" hexmask.long.byte 0x8D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8DC "GFXMMU_LUT283H,GFXMMU LUT entry 283 high" hexmask.long.tbyte 0x8DC 0.--17. 1. "LO,Line offset" line.long 0x8E0 "GFXMMU_LUT284L,GFXMMU LUT entry 284 low" hexmask.long.byte 0x8E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8E4 "GFXMMU_LUT284H,GFXMMU LUT entry 284 high" hexmask.long.tbyte 0x8E4 0.--17. 1. "LO,Line offset" line.long 0x8E8 "GFXMMU_LUT285L,GFXMMU LUT entry 285 low" hexmask.long.byte 0x8E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8EC "GFXMMU_LUT285H,GFXMMU LUT entry 285 high" hexmask.long.tbyte 0x8EC 0.--17. 1. "LO,Line offset" line.long 0x8F0 "GFXMMU_LUT286L,GFXMMU LUT entry 286 low" hexmask.long.byte 0x8F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8F4 "GFXMMU_LUT286H,GFXMMU LUT entry 286 high" hexmask.long.tbyte 0x8F4 0.--17. 1. "LO,Line offset" line.long 0x8F8 "GFXMMU_LUT287L,GFXMMU LUT entry 287 low" hexmask.long.byte 0x8F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8FC "GFXMMU_LUT287H,GFXMMU LUT entry 287 high" hexmask.long.tbyte 0x8FC 0.--17. 1. "LO,Line offset" line.long 0x900 "GFXMMU_LUT288L,GFXMMU LUT entry 288 low" hexmask.long.byte 0x900 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x900 8.--15. 1. "FVB,First valid block" bitfld.long 0x900 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x904 "GFXMMU_LUT288H,GFXMMU LUT entry 288 high" hexmask.long.tbyte 0x904 0.--17. 1. "LO,Line offset" line.long 0x908 "GFXMMU_LUT289L,GFXMMU LUT entry 289 low" hexmask.long.byte 0x908 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x908 8.--15. 1. "FVB,First valid block" bitfld.long 0x908 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x90C "GFXMMU_LUT289H,GFXMMU LUT entry 289 high" hexmask.long.tbyte 0x90C 0.--17. 1. "LO,Line offset" line.long 0x910 "GFXMMU_LUT290L,GFXMMU LUT entry 290 low" hexmask.long.byte 0x910 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x910 8.--15. 1. "FVB,First valid block" bitfld.long 0x910 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x914 "GFXMMU_LUT290H,GFXMMU LUT entry 290 high" hexmask.long.tbyte 0x914 0.--17. 1. "LO,Line offset" line.long 0x918 "GFXMMU_LUT291L,GFXMMU LUT entry 291 low" hexmask.long.byte 0x918 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x918 8.--15. 1. "FVB,First valid block" bitfld.long 0x918 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x91C "GFXMMU_LUT291H,GFXMMU LUT entry 291 high" hexmask.long.tbyte 0x91C 0.--17. 1. "LO,Line offset" line.long 0x920 "GFXMMU_LUT292L,GFXMMU LUT entry 292 low" hexmask.long.byte 0x920 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x920 8.--15. 1. "FVB,First valid block" bitfld.long 0x920 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x924 "GFXMMU_LUT292H,GFXMMU LUT entry 292 high" hexmask.long.tbyte 0x924 0.--17. 1. "LO,Line offset" line.long 0x928 "GFXMMU_LUT293L,GFXMMU LUT entry 293 low" hexmask.long.byte 0x928 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x928 8.--15. 1. "FVB,First valid block" bitfld.long 0x928 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x92C "GFXMMU_LUT293H,GFXMMU LUT entry 293 high" hexmask.long.tbyte 0x92C 0.--17. 1. "LO,Line offset" line.long 0x930 "GFXMMU_LUT294L,GFXMMU LUT entry 294 low" hexmask.long.byte 0x930 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x930 8.--15. 1. "FVB,First valid block" bitfld.long 0x930 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x934 "GFXMMU_LUT294H,GFXMMU LUT entry 294 high" hexmask.long.tbyte 0x934 0.--17. 1. "LO,Line offset" line.long 0x938 "GFXMMU_LUT295L,GFXMMU LUT entry 295 low" hexmask.long.byte 0x938 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x938 8.--15. 1. "FVB,First valid block" bitfld.long 0x938 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x93C "GFXMMU_LUT295H,GFXMMU LUT entry 295 high" hexmask.long.tbyte 0x93C 0.--17. 1. "LO,Line offset" line.long 0x940 "GFXMMU_LUT296L,GFXMMU LUT entry 296 low" hexmask.long.byte 0x940 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x940 8.--15. 1. "FVB,First valid block" bitfld.long 0x940 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x944 "GFXMMU_LUT296H,GFXMMU LUT entry 296 high" hexmask.long.tbyte 0x944 0.--17. 1. "LO,Line offset" line.long 0x948 "GFXMMU_LUT297L,GFXMMU LUT entry 297 low" hexmask.long.byte 0x948 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x948 8.--15. 1. "FVB,First valid block" bitfld.long 0x948 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94C "GFXMMU_LUT297H,GFXMMU LUT entry 297 high" hexmask.long.tbyte 0x94C 0.--17. 1. "LO,Line offset" line.long 0x950 "GFXMMU_LUT298L,GFXMMU LUT entry 298 low" hexmask.long.byte 0x950 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x950 8.--15. 1. "FVB,First valid block" bitfld.long 0x950 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x954 "GFXMMU_LUT298H,GFXMMU LUT entry 298 high" hexmask.long.tbyte 0x954 0.--17. 1. "LO,Line offset" line.long 0x958 "GFXMMU_LUT299L,GFXMMU LUT entry 299 low" hexmask.long.byte 0x958 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x958 8.--15. 1. "FVB,First valid block" bitfld.long 0x958 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x95C "GFXMMU_LUT299H,GFXMMU LUT entry 299 high" hexmask.long.tbyte 0x95C 0.--17. 1. "LO,Line offset" line.long 0x960 "GFXMMU_LUT300L,GFXMMU LUT entry 300 low" hexmask.long.byte 0x960 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x960 8.--15. 1. "FVB,First valid block" bitfld.long 0x960 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x964 "GFXMMU_LUT300H,GFXMMU LUT entry 300 high" hexmask.long.tbyte 0x964 0.--17. 1. "LO,Line offset" line.long 0x968 "GFXMMU_LUT301L,GFXMMU LUT entry 301 low" hexmask.long.byte 0x968 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x968 8.--15. 1. "FVB,First valid block" bitfld.long 0x968 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x96C "GFXMMU_LUT301H,GFXMMU LUT entry 301 high" hexmask.long.tbyte 0x96C 0.--17. 1. "LO,Line offset" line.long 0x970 "GFXMMU_LUT302L,GFXMMU LUT entry 302 low" hexmask.long.byte 0x970 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x970 8.--15. 1. "FVB,First valid block" bitfld.long 0x970 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x974 "GFXMMU_LUT302H,GFXMMU LUT entry 302 high" hexmask.long.tbyte 0x974 0.--17. 1. "LO,Line offset" line.long 0x978 "GFXMMU_LUT303L,GFXMMU LUT entry 303 low" hexmask.long.byte 0x978 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x978 8.--15. 1. "FVB,First valid block" bitfld.long 0x978 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x97C "GFXMMU_LUT303H,GFXMMU LUT entry 303 high" hexmask.long.tbyte 0x97C 0.--17. 1. "LO,Line offset" line.long 0x980 "GFXMMU_LUT304L,GFXMMU LUT entry 304 low" hexmask.long.byte 0x980 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x980 8.--15. 1. "FVB,First valid block" bitfld.long 0x980 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x984 "GFXMMU_LUT304H,GFXMMU LUT entry 304 high" hexmask.long.tbyte 0x984 0.--17. 1. "LO,Line offset" line.long 0x988 "GFXMMU_LUT305L,GFXMMU LUT entry 305 low" hexmask.long.byte 0x988 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x988 8.--15. 1. "FVB,First valid block" bitfld.long 0x988 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x98C "GFXMMU_LUT305H,GFXMMU LUT entry 305 high" hexmask.long.tbyte 0x98C 0.--17. 1. "LO,Line offset" line.long 0x990 "GFXMMU_LUT306L,GFXMMU LUT entry 306 low" hexmask.long.byte 0x990 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x990 8.--15. 1. "FVB,First valid block" bitfld.long 0x990 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x994 "GFXMMU_LUT306H,GFXMMU LUT entry 306 high" hexmask.long.tbyte 0x994 0.--17. 1. "LO,Line offset" line.long 0x998 "GFXMMU_LUT307L,GFXMMU LUT entry 307 low" hexmask.long.byte 0x998 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x998 8.--15. 1. "FVB,First valid block" bitfld.long 0x998 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x99C "GFXMMU_LUT307H,GFXMMU LUT entry 307 high" hexmask.long.tbyte 0x99C 0.--17. 1. "LO,Line offset" line.long 0x9A0 "GFXMMU_LUT308L,GFXMMU LUT entry 308 low" hexmask.long.byte 0x9A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9A4 "GFXMMU_LUT308H,GFXMMU LUT entry 308 high" hexmask.long.tbyte 0x9A4 0.--17. 1. "LO,Line offset" line.long 0x9A8 "GFXMMU_LUT309L,GFXMMU LUT entry 309 low" hexmask.long.byte 0x9A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9AC "GFXMMU_LUT309H,GFXMMU LUT entry 309 high" hexmask.long.tbyte 0x9AC 0.--17. 1. "LO,Line offset" line.long 0x9B0 "GFXMMU_LUT310L,GFXMMU LUT entry 310 low" hexmask.long.byte 0x9B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9B4 "GFXMMU_LUT310H,GFXMMU LUT entry 310 high" hexmask.long.tbyte 0x9B4 0.--17. 1. "LO,Line offset" line.long 0x9B8 "GFXMMU_LUT311L,GFXMMU LUT entry 311 low" hexmask.long.byte 0x9B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9BC "GFXMMU_LUT311H,GFXMMU LUT entry 311 high" hexmask.long.tbyte 0x9BC 0.--17. 1. "LO,Line offset" line.long 0x9C0 "GFXMMU_LUT312L,GFXMMU LUT entry 312 low" hexmask.long.byte 0x9C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C4 "GFXMMU_LUT312H,GFXMMU LUT entry 312 high" hexmask.long.tbyte 0x9C4 0.--17. 1. "LO,Line offset" line.long 0x9C8 "GFXMMU_LUT313L,GFXMMU LUT entry 313 low" hexmask.long.byte 0x9C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9CC "GFXMMU_LUT313H,GFXMMU LUT entry 313 high" hexmask.long.tbyte 0x9CC 0.--17. 1. "LO,Line offset" line.long 0x9D0 "GFXMMU_LUT314L,GFXMMU LUT entry 314 low" hexmask.long.byte 0x9D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9D4 "GFXMMU_LUT314H,GFXMMU LUT entry 314 high" hexmask.long.tbyte 0x9D4 0.--17. 1. "LO,Line offset" line.long 0x9D8 "GFXMMU_LUT315L,GFXMMU LUT entry 315 low" hexmask.long.byte 0x9D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9DC "GFXMMU_LUT315H,GFXMMU LUT entry 315 high" hexmask.long.tbyte 0x9DC 0.--17. 1. "LO,Line offset" line.long 0x9E0 "GFXMMU_LUT316L,GFXMMU LUT entry 316 low" hexmask.long.byte 0x9E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9E4 "GFXMMU_LUT316H,GFXMMU LUT entry 316 high" hexmask.long.tbyte 0x9E4 0.--17. 1. "LO,Line offset" line.long 0x9E8 "GFXMMU_LUT317L,GFXMMU LUT entry 317 low" hexmask.long.byte 0x9E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9EC "GFXMMU_LUT317H,GFXMMU LUT entry 317 high" hexmask.long.tbyte 0x9EC 0.--17. 1. "LO,Line offset" line.long 0x9F0 "GFXMMU_LUT318L,GFXMMU LUT entry 318 low" hexmask.long.byte 0x9F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9F4 "GFXMMU_LUT318H,GFXMMU LUT entry 318 high" hexmask.long.tbyte 0x9F4 0.--17. 1. "LO,Line offset" line.long 0x9F8 "GFXMMU_LUT319L,GFXMMU LUT entry 319 low" hexmask.long.byte 0x9F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9FC "GFXMMU_LUT319H,GFXMMU LUT entry 319 high" hexmask.long.tbyte 0x9FC 0.--17. 1. "LO,Line offset" line.long 0xA00 "GFXMMU_LUT320L,GFXMMU LUT entry 320 low" hexmask.long.byte 0xA00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA00 8.--15. 1. "FVB,First valid block" bitfld.long 0xA00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA04 "GFXMMU_LUT320H,GFXMMU LUT entry 320 high" hexmask.long.tbyte 0xA04 0.--17. 1. "LO,Line offset" line.long 0xA08 "GFXMMU_LUT321L,GFXMMU LUT entry 321 low" hexmask.long.byte 0xA08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA08 8.--15. 1. "FVB,First valid block" bitfld.long 0xA08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA0C "GFXMMU_LUT321H,GFXMMU LUT entry 321 high" hexmask.long.tbyte 0xA0C 0.--17. 1. "LO,Line offset" line.long 0xA10 "GFXMMU_LUT322L,GFXMMU LUT entry 322 low" hexmask.long.byte 0xA10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA10 8.--15. 1. "FVB,First valid block" bitfld.long 0xA10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA14 "GFXMMU_LUT322H,GFXMMU LUT entry 322 high" hexmask.long.tbyte 0xA14 0.--17. 1. "LO,Line offset" line.long 0xA18 "GFXMMU_LUT323L,GFXMMU LUT entry 323 low" hexmask.long.byte 0xA18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA18 8.--15. 1. "FVB,First valid block" bitfld.long 0xA18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA1C "GFXMMU_LUT323H,GFXMMU LUT entry 323 high" hexmask.long.tbyte 0xA1C 0.--17. 1. "LO,Line offset" line.long 0xA20 "GFXMMU_LUT324L,GFXMMU LUT entry 324 low" hexmask.long.byte 0xA20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA20 8.--15. 1. "FVB,First valid block" bitfld.long 0xA20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA24 "GFXMMU_LUT324H,GFXMMU LUT entry 324 high" hexmask.long.tbyte 0xA24 0.--17. 1. "LO,Line offset" line.long 0xA28 "GFXMMU_LUT325L,GFXMMU LUT entry 325 low" hexmask.long.byte 0xA28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA28 8.--15. 1. "FVB,First valid block" bitfld.long 0xA28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA2C "GFXMMU_LUT325H,GFXMMU LUT entry 325 high" hexmask.long.tbyte 0xA2C 0.--17. 1. "LO,Line offset" line.long 0xA30 "GFXMMU_LUT326L,GFXMMU LUT entry 326 low" hexmask.long.byte 0xA30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA30 8.--15. 1. "FVB,First valid block" bitfld.long 0xA30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA34 "GFXMMU_LUT326H,GFXMMU LUT entry 326 high" hexmask.long.tbyte 0xA34 0.--17. 1. "LO,Line offset" line.long 0xA38 "GFXMMU_LUT327L,GFXMMU LUT entry 327 low" hexmask.long.byte 0xA38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA38 8.--15. 1. "FVB,First valid block" bitfld.long 0xA38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA3C "GFXMMU_LUT327H,GFXMMU LUT entry 327 high" hexmask.long.tbyte 0xA3C 0.--17. 1. "LO,Line offset" line.long 0xA40 "GFXMMU_LUT328L,GFXMMU LUT entry 328 low" hexmask.long.byte 0xA40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA40 8.--15. 1. "FVB,First valid block" bitfld.long 0xA40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA44 "GFXMMU_LUT328H,GFXMMU LUT entry 328 high" hexmask.long.tbyte 0xA44 0.--17. 1. "LO,Line offset" line.long 0xA48 "GFXMMU_LUT329L,GFXMMU LUT entry 329 low" hexmask.long.byte 0xA48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA48 8.--15. 1. "FVB,First valid block" bitfld.long 0xA48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4C "GFXMMU_LUT329H,GFXMMU LUT entry 329 high" hexmask.long.tbyte 0xA4C 0.--17. 1. "LO,Line offset" line.long 0xA50 "GFXMMU_LUT330L,GFXMMU LUT entry 330 low" hexmask.long.byte 0xA50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA50 8.--15. 1. "FVB,First valid block" bitfld.long 0xA50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA54 "GFXMMU_LUT330H,GFXMMU LUT entry 330 high" hexmask.long.tbyte 0xA54 0.--17. 1. "LO,Line offset" line.long 0xA58 "GFXMMU_LUT331L,GFXMMU LUT entry 331 low" hexmask.long.byte 0xA58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA58 8.--15. 1. "FVB,First valid block" bitfld.long 0xA58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA5C "GFXMMU_LUT331H,GFXMMU LUT entry 331 high" hexmask.long.tbyte 0xA5C 0.--17. 1. "LO,Line offset" line.long 0xA60 "GFXMMU_LUT332L,GFXMMU LUT entry 332 low" hexmask.long.byte 0xA60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA60 8.--15. 1. "FVB,First valid block" bitfld.long 0xA60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA64 "GFXMMU_LUT332H,GFXMMU LUT entry 332 high" hexmask.long.tbyte 0xA64 0.--17. 1. "LO,Line offset" line.long 0xA68 "GFXMMU_LUT333L,GFXMMU LUT entry 333 low" hexmask.long.byte 0xA68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA68 8.--15. 1. "FVB,First valid block" bitfld.long 0xA68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA6C "GFXMMU_LUT333H,GFXMMU LUT entry 333 high" hexmask.long.tbyte 0xA6C 0.--17. 1. "LO,Line offset" line.long 0xA70 "GFXMMU_LUT334L,GFXMMU LUT entry 334 low" hexmask.long.byte 0xA70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA70 8.--15. 1. "FVB,First valid block" bitfld.long 0xA70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA74 "GFXMMU_LUT334H,GFXMMU LUT entry 334 high" hexmask.long.tbyte 0xA74 0.--17. 1. "LO,Line offset" line.long 0xA78 "GFXMMU_LUT335L,GFXMMU LUT entry 335 low" hexmask.long.byte 0xA78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA78 8.--15. 1. "FVB,First valid block" bitfld.long 0xA78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA7C "GFXMMU_LUT335H,GFXMMU LUT entry 335 high" hexmask.long.tbyte 0xA7C 0.--17. 1. "LO,Line offset" line.long 0xA80 "GFXMMU_LUT336L,GFXMMU LUT entry 336 low" hexmask.long.byte 0xA80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA80 8.--15. 1. "FVB,First valid block" bitfld.long 0xA80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA84 "GFXMMU_LUT336H,GFXMMU LUT entry 336 high" hexmask.long.tbyte 0xA84 0.--17. 1. "LO,Line offset" line.long 0xA88 "GFXMMU_LUT337L,GFXMMU LUT entry 337 low" hexmask.long.byte 0xA88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA88 8.--15. 1. "FVB,First valid block" bitfld.long 0xA88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA8C "GFXMMU_LUT337H,GFXMMU LUT entry 337 high" hexmask.long.tbyte 0xA8C 0.--17. 1. "LO,Line offset" line.long 0xA90 "GFXMMU_LUT338L,GFXMMU LUT entry 338 low" hexmask.long.byte 0xA90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA90 8.--15. 1. "FVB,First valid block" bitfld.long 0xA90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA94 "GFXMMU_LUT338H,GFXMMU LUT entry 338 high" hexmask.long.tbyte 0xA94 0.--17. 1. "LO,Line offset" line.long 0xA98 "GFXMMU_LUT339L,GFXMMU LUT entry 339 low" hexmask.long.byte 0xA98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA98 8.--15. 1. "FVB,First valid block" bitfld.long 0xA98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA9C "GFXMMU_LUT339H,GFXMMU LUT entry 339 high" hexmask.long.tbyte 0xA9C 0.--17. 1. "LO,Line offset" line.long 0xAA0 "GFXMMU_LUT340L,GFXMMU LUT entry 340 low" hexmask.long.byte 0xAA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAA4 "GFXMMU_LUT340H,GFXMMU LUT entry 340 high" hexmask.long.tbyte 0xAA4 0.--17. 1. "LO,Line offset" line.long 0xAA8 "GFXMMU_LUT341L,GFXMMU LUT entry 341 low" hexmask.long.byte 0xAA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAAC "GFXMMU_LUT341H,GFXMMU LUT entry 341 high" hexmask.long.tbyte 0xAAC 0.--17. 1. "LO,Line offset" line.long 0xAB0 "GFXMMU_LUT342L,GFXMMU LUT entry 342 low" hexmask.long.byte 0xAB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAB4 "GFXMMU_LUT342H,GFXMMU LUT entry 342 high" hexmask.long.tbyte 0xAB4 0.--17. 1. "LO,Line offset" line.long 0xAB8 "GFXMMU_LUT343L,GFXMMU LUT entry 343 low" hexmask.long.byte 0xAB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xABC "GFXMMU_LUT343H,GFXMMU LUT entry 343 high" hexmask.long.tbyte 0xABC 0.--17. 1. "LO,Line offset" line.long 0xAC0 "GFXMMU_LUT344L,GFXMMU LUT entry 344 low" hexmask.long.byte 0xAC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC4 "GFXMMU_LUT344H,GFXMMU LUT entry 344 high" hexmask.long.tbyte 0xAC4 0.--17. 1. "LO,Line offset" line.long 0xAC8 "GFXMMU_LUT345L,GFXMMU LUT entry 345 low" hexmask.long.byte 0xAC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xACC "GFXMMU_LUT345H,GFXMMU LUT entry 345 high" hexmask.long.tbyte 0xACC 0.--17. 1. "LO,Line offset" line.long 0xAD0 "GFXMMU_LUT346L,GFXMMU LUT entry 346 low" hexmask.long.byte 0xAD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAD4 "GFXMMU_LUT346H,GFXMMU LUT entry 346 high" hexmask.long.tbyte 0xAD4 0.--17. 1. "LO,Line offset" line.long 0xAD8 "GFXMMU_LUT347L,GFXMMU LUT entry 347 low" hexmask.long.byte 0xAD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xADC "GFXMMU_LUT347H,GFXMMU LUT entry 347 high" hexmask.long.tbyte 0xADC 0.--17. 1. "LO,Line offset" line.long 0xAE0 "GFXMMU_LUT348L,GFXMMU LUT entry 348 low" hexmask.long.byte 0xAE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAE4 "GFXMMU_LUT348H,GFXMMU LUT entry 348 high" hexmask.long.tbyte 0xAE4 0.--17. 1. "LO,Line offset" line.long 0xAE8 "GFXMMU_LUT349L,GFXMMU LUT entry 349 low" hexmask.long.byte 0xAE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAEC "GFXMMU_LUT349H,GFXMMU LUT entry 349 high" hexmask.long.tbyte 0xAEC 0.--17. 1. "LO,Line offset" line.long 0xAF0 "GFXMMU_LUT350L,GFXMMU LUT entry 350 low" hexmask.long.byte 0xAF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAF4 "GFXMMU_LUT350H,GFXMMU LUT entry 350 high" hexmask.long.tbyte 0xAF4 0.--17. 1. "LO,Line offset" line.long 0xAF8 "GFXMMU_LUT351L,GFXMMU LUT entry 351 low" hexmask.long.byte 0xAF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAFC "GFXMMU_LUT351H,GFXMMU LUT entry 351 high" hexmask.long.tbyte 0xAFC 0.--17. 1. "LO,Line offset" line.long 0xB00 "GFXMMU_LUT352L,GFXMMU LUT entry 352 low" hexmask.long.byte 0xB00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB00 8.--15. 1. "FVB,First valid block" bitfld.long 0xB00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB04 "GFXMMU_LUT352H,GFXMMU LUT entry 352 high" hexmask.long.tbyte 0xB04 0.--17. 1. "LO,Line offset" line.long 0xB08 "GFXMMU_LUT353L,GFXMMU LUT entry 353 low" hexmask.long.byte 0xB08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB08 8.--15. 1. "FVB,First valid block" bitfld.long 0xB08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB0C "GFXMMU_LUT353H,GFXMMU LUT entry 353 high" hexmask.long.tbyte 0xB0C 0.--17. 1. "LO,Line offset" line.long 0xB10 "GFXMMU_LUT354L,GFXMMU LUT entry 354 low" hexmask.long.byte 0xB10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB10 8.--15. 1. "FVB,First valid block" bitfld.long 0xB10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB14 "GFXMMU_LUT354H,GFXMMU LUT entry 354 high" hexmask.long.tbyte 0xB14 0.--17. 1. "LO,Line offset" line.long 0xB18 "GFXMMU_LUT355L,GFXMMU LUT entry 355 low" hexmask.long.byte 0xB18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB18 8.--15. 1. "FVB,First valid block" bitfld.long 0xB18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB1C "GFXMMU_LUT355H,GFXMMU LUT entry 355 high" hexmask.long.tbyte 0xB1C 0.--17. 1. "LO,Line offset" line.long 0xB20 "GFXMMU_LUT356L,GFXMMU LUT entry 356 low" hexmask.long.byte 0xB20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB20 8.--15. 1. "FVB,First valid block" bitfld.long 0xB20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB24 "GFXMMU_LUT356H,GFXMMU LUT entry 356 high" hexmask.long.tbyte 0xB24 0.--17. 1. "LO,Line offset" line.long 0xB28 "GFXMMU_LUT357L,GFXMMU LUT entry 357 low" hexmask.long.byte 0xB28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB28 8.--15. 1. "FVB,First valid block" bitfld.long 0xB28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB2C "GFXMMU_LUT357H,GFXMMU LUT entry 357 high" hexmask.long.tbyte 0xB2C 0.--17. 1. "LO,Line offset" line.long 0xB30 "GFXMMU_LUT358L,GFXMMU LUT entry 358 low" hexmask.long.byte 0xB30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB30 8.--15. 1. "FVB,First valid block" bitfld.long 0xB30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB34 "GFXMMU_LUT358H,GFXMMU LUT entry 358 high" hexmask.long.tbyte 0xB34 0.--17. 1. "LO,Line offset" line.long 0xB38 "GFXMMU_LUT359L,GFXMMU LUT entry 359 low" hexmask.long.byte 0xB38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB38 8.--15. 1. "FVB,First valid block" bitfld.long 0xB38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB3C "GFXMMU_LUT359H,GFXMMU LUT entry 359 high" hexmask.long.tbyte 0xB3C 0.--17. 1. "LO,Line offset" line.long 0xB40 "GFXMMU_LUT360L,GFXMMU LUT entry 360 low" hexmask.long.byte 0xB40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB40 8.--15. 1. "FVB,First valid block" bitfld.long 0xB40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB44 "GFXMMU_LUT360H,GFXMMU LUT entry 360 high" hexmask.long.tbyte 0xB44 0.--17. 1. "LO,Line offset" line.long 0xB48 "GFXMMU_LUT361L,GFXMMU LUT entry 361 low" hexmask.long.byte 0xB48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB48 8.--15. 1. "FVB,First valid block" bitfld.long 0xB48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4C "GFXMMU_LUT361H,GFXMMU LUT entry 361 high" hexmask.long.tbyte 0xB4C 0.--17. 1. "LO,Line offset" line.long 0xB50 "GFXMMU_LUT362L,GFXMMU LUT entry 362 low" hexmask.long.byte 0xB50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB50 8.--15. 1. "FVB,First valid block" bitfld.long 0xB50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB54 "GFXMMU_LUT362H,GFXMMU LUT entry 362 high" hexmask.long.tbyte 0xB54 0.--17. 1. "LO,Line offset" line.long 0xB58 "GFXMMU_LUT363L,GFXMMU LUT entry 363 low" hexmask.long.byte 0xB58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB58 8.--15. 1. "FVB,First valid block" bitfld.long 0xB58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB5C "GFXMMU_LUT363H,GFXMMU LUT entry 363 high" hexmask.long.tbyte 0xB5C 0.--17. 1. "LO,Line offset" line.long 0xB60 "GFXMMU_LUT364L,GFXMMU LUT entry 364 low" hexmask.long.byte 0xB60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB60 8.--15. 1. "FVB,First valid block" bitfld.long 0xB60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB64 "GFXMMU_LUT364H,GFXMMU LUT entry 364 high" hexmask.long.tbyte 0xB64 0.--17. 1. "LO,Line offset" line.long 0xB68 "GFXMMU_LUT365L,GFXMMU LUT entry 365 low" hexmask.long.byte 0xB68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB68 8.--15. 1. "FVB,First valid block" bitfld.long 0xB68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB6C "GFXMMU_LUT365H,GFXMMU LUT entry 365 high" hexmask.long.tbyte 0xB6C 0.--17. 1. "LO,Line offset" line.long 0xB70 "GFXMMU_LUT366L,GFXMMU LUT entry 366 low" hexmask.long.byte 0xB70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB70 8.--15. 1. "FVB,First valid block" bitfld.long 0xB70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB74 "GFXMMU_LUT366H,GFXMMU LUT entry 366 high" hexmask.long.tbyte 0xB74 0.--17. 1. "LO,Line offset" line.long 0xB78 "GFXMMU_LUT367L,GFXMMU LUT entry 367 low" hexmask.long.byte 0xB78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB78 8.--15. 1. "FVB,First valid block" bitfld.long 0xB78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB7C "GFXMMU_LUT367H,GFXMMU LUT entry 367 high" hexmask.long.tbyte 0xB7C 0.--17. 1. "LO,Line offset" line.long 0xB80 "GFXMMU_LUT368L,GFXMMU LUT entry 368 low" hexmask.long.byte 0xB80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB80 8.--15. 1. "FVB,First valid block" bitfld.long 0xB80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB84 "GFXMMU_LUT368H,GFXMMU LUT entry 368 high" hexmask.long.tbyte 0xB84 0.--17. 1. "LO,Line offset" line.long 0xB88 "GFXMMU_LUT369L,GFXMMU LUT entry 369 low" hexmask.long.byte 0xB88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB88 8.--15. 1. "FVB,First valid block" bitfld.long 0xB88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB8C "GFXMMU_LUT369H,GFXMMU LUT entry 369 high" hexmask.long.tbyte 0xB8C 0.--17. 1. "LO,Line offset" line.long 0xB90 "GFXMMU_LUT370L,GFXMMU LUT entry 370 low" hexmask.long.byte 0xB90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB90 8.--15. 1. "FVB,First valid block" bitfld.long 0xB90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB94 "GFXMMU_LUT370H,GFXMMU LUT entry 370 high" hexmask.long.tbyte 0xB94 0.--17. 1. "LO,Line offset" line.long 0xB98 "GFXMMU_LUT371L,GFXMMU LUT entry 371 low" hexmask.long.byte 0xB98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB98 8.--15. 1. "FVB,First valid block" bitfld.long 0xB98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB9C "GFXMMU_LUT371H,GFXMMU LUT entry 371 high" hexmask.long.tbyte 0xB9C 0.--17. 1. "LO,Line offset" line.long 0xBA0 "GFXMMU_LUT372L,GFXMMU LUT entry 372 low" hexmask.long.byte 0xBA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBA4 "GFXMMU_LUT372H,GFXMMU LUT entry 372 high" hexmask.long.tbyte 0xBA4 0.--17. 1. "LO,Line offset" line.long 0xBA8 "GFXMMU_LUT373L,GFXMMU LUT entry 373 low" hexmask.long.byte 0xBA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBAC "GFXMMU_LUT373H,GFXMMU LUT entry 373 high" hexmask.long.tbyte 0xBAC 0.--17. 1. "LO,Line offset" line.long 0xBB0 "GFXMMU_LUT374L,GFXMMU LUT entry 374 low" hexmask.long.byte 0xBB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBB4 "GFXMMU_LUT374H,GFXMMU LUT entry 374 high" hexmask.long.tbyte 0xBB4 0.--17. 1. "LO,Line offset" line.long 0xBB8 "GFXMMU_LUT375L,GFXMMU LUT entry 375 low" hexmask.long.byte 0xBB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBBC "GFXMMU_LUT375H,GFXMMU LUT entry 375 high" hexmask.long.tbyte 0xBBC 0.--17. 1. "LO,Line offset" line.long 0xBC0 "GFXMMU_LUT376L,GFXMMU LUT entry 376 low" hexmask.long.byte 0xBC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC4 "GFXMMU_LUT376H,GFXMMU LUT entry 376 high" hexmask.long.tbyte 0xBC4 0.--17. 1. "LO,Line offset" line.long 0xBC8 "GFXMMU_LUT377L,GFXMMU LUT entry 377 low" hexmask.long.byte 0xBC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBCC "GFXMMU_LUT377H,GFXMMU LUT entry 377 high" hexmask.long.tbyte 0xBCC 0.--17. 1. "LO,Line offset" line.long 0xBD0 "GFXMMU_LUT378L,GFXMMU LUT entry 378 low" hexmask.long.byte 0xBD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBD4 "GFXMMU_LUT378H,GFXMMU LUT entry 378 high" hexmask.long.tbyte 0xBD4 0.--17. 1. "LO,Line offset" line.long 0xBD8 "GFXMMU_LUT379L,GFXMMU LUT entry 379 low" hexmask.long.byte 0xBD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBDC "GFXMMU_LUT379H,GFXMMU LUT entry 379 high" hexmask.long.tbyte 0xBDC 0.--17. 1. "LO,Line offset" line.long 0xBE0 "GFXMMU_LUT380L,GFXMMU LUT entry 380 low" hexmask.long.byte 0xBE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBE4 "GFXMMU_LUT380H,GFXMMU LUT entry 380 high" hexmask.long.tbyte 0xBE4 0.--17. 1. "LO,Line offset" line.long 0xBE8 "GFXMMU_LUT381L,GFXMMU LUT entry 381 low" hexmask.long.byte 0xBE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBEC "GFXMMU_LUT381H,GFXMMU LUT entry 381 high" hexmask.long.tbyte 0xBEC 0.--17. 1. "LO,Line offset" line.long 0xBF0 "GFXMMU_LUT382L,GFXMMU LUT entry 382 low" hexmask.long.byte 0xBF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBF4 "GFXMMU_LUT382H,GFXMMU LUT entry 382 high" hexmask.long.tbyte 0xBF4 0.--17. 1. "LO,Line offset" line.long 0xBF8 "GFXMMU_LUT383L,GFXMMU LUT entry 383 low" hexmask.long.byte 0xBF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBFC "GFXMMU_LUT383H,GFXMMU LUT entry 383 high" hexmask.long.tbyte 0xBFC 0.--17. 1. "LO,Line offset" line.long 0xC00 "GFXMMU_LUT384L,GFXMMU LUT entry 384 low" hexmask.long.byte 0xC00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC00 8.--15. 1. "FVB,First valid block" bitfld.long 0xC00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC04 "GFXMMU_LUT384H,GFXMMU LUT entry 384 high" hexmask.long.tbyte 0xC04 0.--17. 1. "LO,Line offset" line.long 0xC08 "GFXMMU_LUT385L,GFXMMU LUT entry 385 low" hexmask.long.byte 0xC08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC08 8.--15. 1. "FVB,First valid block" bitfld.long 0xC08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC0C "GFXMMU_LUT385H,GFXMMU LUT entry 385 high" hexmask.long.tbyte 0xC0C 0.--17. 1. "LO,Line offset" line.long 0xC10 "GFXMMU_LUT386L,GFXMMU LUT entry 386 low" hexmask.long.byte 0xC10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC10 8.--15. 1. "FVB,First valid block" bitfld.long 0xC10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC14 "GFXMMU_LUT386H,GFXMMU LUT entry 386 high" hexmask.long.tbyte 0xC14 0.--17. 1. "LO,Line offset" line.long 0xC18 "GFXMMU_LUT387L,GFXMMU LUT entry 387 low" hexmask.long.byte 0xC18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC18 8.--15. 1. "FVB,First valid block" bitfld.long 0xC18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC1C "GFXMMU_LUT387H,GFXMMU LUT entry 387 high" hexmask.long.tbyte 0xC1C 0.--17. 1. "LO,Line offset" line.long 0xC20 "GFXMMU_LUT388L,GFXMMU LUT entry 388 low" hexmask.long.byte 0xC20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC20 8.--15. 1. "FVB,First valid block" bitfld.long 0xC20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC24 "GFXMMU_LUT388H,GFXMMU LUT entry 388 high" hexmask.long.tbyte 0xC24 0.--17. 1. "LO,Line offset" line.long 0xC28 "GFXMMU_LUT389L,GFXMMU LUT entry 389 low" hexmask.long.byte 0xC28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC28 8.--15. 1. "FVB,First valid block" bitfld.long 0xC28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC2C "GFXMMU_LUT389H,GFXMMU LUT entry 389 high" hexmask.long.tbyte 0xC2C 0.--17. 1. "LO,Line offset" line.long 0xC30 "GFXMMU_LUT390L,GFXMMU LUT entry 390 low" hexmask.long.byte 0xC30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC30 8.--15. 1. "FVB,First valid block" bitfld.long 0xC30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC34 "GFXMMU_LUT390H,GFXMMU LUT entry 390 high" hexmask.long.tbyte 0xC34 0.--17. 1. "LO,Line offset" line.long 0xC38 "GFXMMU_LUT391L,GFXMMU LUT entry 391 low" hexmask.long.byte 0xC38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC38 8.--15. 1. "FVB,First valid block" bitfld.long 0xC38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC3C "GFXMMU_LUT391H,GFXMMU LUT entry 391 high" hexmask.long.tbyte 0xC3C 0.--17. 1. "LO,Line offset" line.long 0xC40 "GFXMMU_LUT392L,GFXMMU LUT entry 392 low" hexmask.long.byte 0xC40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC40 8.--15. 1. "FVB,First valid block" bitfld.long 0xC40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC44 "GFXMMU_LUT392H,GFXMMU LUT entry 392 high" hexmask.long.tbyte 0xC44 0.--17. 1. "LO,Line offset" line.long 0xC48 "GFXMMU_LUT393L,GFXMMU LUT entry 393 low" hexmask.long.byte 0xC48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC48 8.--15. 1. "FVB,First valid block" bitfld.long 0xC48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4C "GFXMMU_LUT393H,GFXMMU LUT entry 393 high" hexmask.long.tbyte 0xC4C 0.--17. 1. "LO,Line offset" line.long 0xC50 "GFXMMU_LUT394L,GFXMMU LUT entry 394 low" hexmask.long.byte 0xC50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC50 8.--15. 1. "FVB,First valid block" bitfld.long 0xC50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC54 "GFXMMU_LUT394H,GFXMMU LUT entry 394 high" hexmask.long.tbyte 0xC54 0.--17. 1. "LO,Line offset" line.long 0xC58 "GFXMMU_LUT395L,GFXMMU LUT entry 395 low" hexmask.long.byte 0xC58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC58 8.--15. 1. "FVB,First valid block" bitfld.long 0xC58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC5C "GFXMMU_LUT395H,GFXMMU LUT entry 395 high" hexmask.long.tbyte 0xC5C 0.--17. 1. "LO,Line offset" line.long 0xC60 "GFXMMU_LUT396L,GFXMMU LUT entry 396 low" hexmask.long.byte 0xC60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC60 8.--15. 1. "FVB,First valid block" bitfld.long 0xC60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC64 "GFXMMU_LUT396H,GFXMMU LUT entry 396 high" hexmask.long.tbyte 0xC64 0.--17. 1. "LO,Line offset" line.long 0xC68 "GFXMMU_LUT397L,GFXMMU LUT entry 397 low" hexmask.long.byte 0xC68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC68 8.--15. 1. "FVB,First valid block" bitfld.long 0xC68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC6C "GFXMMU_LUT397H,GFXMMU LUT entry 397 high" hexmask.long.tbyte 0xC6C 0.--17. 1. "LO,Line offset" line.long 0xC70 "GFXMMU_LUT398L,GFXMMU LUT entry 398 low" hexmask.long.byte 0xC70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC70 8.--15. 1. "FVB,First valid block" bitfld.long 0xC70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC74 "GFXMMU_LUT398H,GFXMMU LUT entry 398 high" hexmask.long.tbyte 0xC74 0.--17. 1. "LO,Line offset" line.long 0xC78 "GFXMMU_LUT399L,GFXMMU LUT entry 399 low" hexmask.long.byte 0xC78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC78 8.--15. 1. "FVB,First valid block" bitfld.long 0xC78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC7C "GFXMMU_LUT399H,GFXMMU LUT entry 399 high" hexmask.long.tbyte 0xC7C 0.--17. 1. "LO,Line offset" line.long 0xC80 "GFXMMU_LUT400L,GFXMMU LUT entry 400 low" hexmask.long.byte 0xC80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC80 8.--15. 1. "FVB,First valid block" bitfld.long 0xC80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC84 "GFXMMU_LUT400H,GFXMMU LUT entry 400 high" hexmask.long.tbyte 0xC84 0.--17. 1. "LO,Line offset" line.long 0xC88 "GFXMMU_LUT401L,GFXMMU LUT entry 401 low" hexmask.long.byte 0xC88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC88 8.--15. 1. "FVB,First valid block" bitfld.long 0xC88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC8C "GFXMMU_LUT401H,GFXMMU LUT entry 401 high" hexmask.long.tbyte 0xC8C 0.--17. 1. "LO,Line offset" line.long 0xC90 "GFXMMU_LUT402L,GFXMMU LUT entry 402 low" hexmask.long.byte 0xC90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC90 8.--15. 1. "FVB,First valid block" bitfld.long 0xC90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC94 "GFXMMU_LUT402H,GFXMMU LUT entry 402 high" hexmask.long.tbyte 0xC94 0.--17. 1. "LO,Line offset" line.long 0xC98 "GFXMMU_LUT403L,GFXMMU LUT entry 403 low" hexmask.long.byte 0xC98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC98 8.--15. 1. "FVB,First valid block" bitfld.long 0xC98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC9C "GFXMMU_LUT403H,GFXMMU LUT entry 403 high" hexmask.long.tbyte 0xC9C 0.--17. 1. "LO,Line offset" line.long 0xCA0 "GFXMMU_LUT404L,GFXMMU LUT entry 404 low" hexmask.long.byte 0xCA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCA4 "GFXMMU_LUT404H,GFXMMU LUT entry 404 high" hexmask.long.tbyte 0xCA4 0.--17. 1. "LO,Line offset" line.long 0xCA8 "GFXMMU_LUT405L,GFXMMU LUT entry 405 low" hexmask.long.byte 0xCA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCAC "GFXMMU_LUT405H,GFXMMU LUT entry 405 high" hexmask.long.tbyte 0xCAC 0.--17. 1. "LO,Line offset" line.long 0xCB0 "GFXMMU_LUT406L,GFXMMU LUT entry 406 low" hexmask.long.byte 0xCB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCB4 "GFXMMU_LUT406H,GFXMMU LUT entry 406 high" hexmask.long.tbyte 0xCB4 0.--17. 1. "LO,Line offset" line.long 0xCB8 "GFXMMU_LUT407L,GFXMMU LUT entry 407 low" hexmask.long.byte 0xCB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCBC "GFXMMU_LUT407H,GFXMMU LUT entry 407 high" hexmask.long.tbyte 0xCBC 0.--17. 1. "LO,Line offset" line.long 0xCC0 "GFXMMU_LUT408L,GFXMMU LUT entry 408 low" hexmask.long.byte 0xCC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC4 "GFXMMU_LUT408H,GFXMMU LUT entry 408 high" hexmask.long.tbyte 0xCC4 0.--17. 1. "LO,Line offset" line.long 0xCC8 "GFXMMU_LUT409L,GFXMMU LUT entry 409 low" hexmask.long.byte 0xCC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCCC "GFXMMU_LUT409H,GFXMMU LUT entry 409 high" hexmask.long.tbyte 0xCCC 0.--17. 1. "LO,Line offset" line.long 0xCD0 "GFXMMU_LUT410L,GFXMMU LUT entry 410 low" hexmask.long.byte 0xCD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCD4 "GFXMMU_LUT410H,GFXMMU LUT entry 410 high" hexmask.long.tbyte 0xCD4 0.--17. 1. "LO,Line offset" line.long 0xCD8 "GFXMMU_LUT411L,GFXMMU LUT entry 411 low" hexmask.long.byte 0xCD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCDC "GFXMMU_LUT411H,GFXMMU LUT entry 411 high" hexmask.long.tbyte 0xCDC 0.--17. 1. "LO,Line offset" line.long 0xCE0 "GFXMMU_LUT412L,GFXMMU LUT entry 412 low" hexmask.long.byte 0xCE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCE4 "GFXMMU_LUT412H,GFXMMU LUT entry 412 high" hexmask.long.tbyte 0xCE4 0.--17. 1. "LO,Line offset" line.long 0xCE8 "GFXMMU_LUT413L,GFXMMU LUT entry 413 low" hexmask.long.byte 0xCE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCEC "GFXMMU_LUT413H,GFXMMU LUT entry 413 high" hexmask.long.tbyte 0xCEC 0.--17. 1. "LO,Line offset" line.long 0xCF0 "GFXMMU_LUT414L,GFXMMU LUT entry 414 low" hexmask.long.byte 0xCF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCF4 "GFXMMU_LUT414H,GFXMMU LUT entry 414 high" hexmask.long.tbyte 0xCF4 0.--17. 1. "LO,Line offset" line.long 0xCF8 "GFXMMU_LUT415L,GFXMMU LUT entry 415 low" hexmask.long.byte 0xCF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCFC "GFXMMU_LUT415H,GFXMMU LUT entry 415 high" hexmask.long.tbyte 0xCFC 0.--17. 1. "LO,Line offset" line.long 0xD00 "GFXMMU_LUT416L,GFXMMU LUT entry 416 low" hexmask.long.byte 0xD00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD00 8.--15. 1. "FVB,First valid block" bitfld.long 0xD00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD04 "GFXMMU_LUT416H,GFXMMU LUT entry 416 high" hexmask.long.tbyte 0xD04 0.--17. 1. "LO,Line offset" line.long 0xD08 "GFXMMU_LUT417L,GFXMMU LUT entry 417 low" hexmask.long.byte 0xD08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD08 8.--15. 1. "FVB,First valid block" bitfld.long 0xD08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD0C "GFXMMU_LUT417H,GFXMMU LUT entry 417 high" hexmask.long.tbyte 0xD0C 0.--17. 1. "LO,Line offset" line.long 0xD10 "GFXMMU_LUT418L,GFXMMU LUT entry 418 low" hexmask.long.byte 0xD10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD10 8.--15. 1. "FVB,First valid block" bitfld.long 0xD10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD14 "GFXMMU_LUT418H,GFXMMU LUT entry 418 high" hexmask.long.tbyte 0xD14 0.--17. 1. "LO,Line offset" line.long 0xD18 "GFXMMU_LUT419L,GFXMMU LUT entry 419 low" hexmask.long.byte 0xD18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD18 8.--15. 1. "FVB,First valid block" bitfld.long 0xD18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD1C "GFXMMU_LUT419H,GFXMMU LUT entry 419 high" hexmask.long.tbyte 0xD1C 0.--17. 1. "LO,Line offset" line.long 0xD20 "GFXMMU_LUT420L,GFXMMU LUT entry 420 low" hexmask.long.byte 0xD20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD20 8.--15. 1. "FVB,First valid block" bitfld.long 0xD20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD24 "GFXMMU_LUT420H,GFXMMU LUT entry 420 high" hexmask.long.tbyte 0xD24 0.--17. 1. "LO,Line offset" line.long 0xD28 "GFXMMU_LUT421L,GFXMMU LUT entry 421 low" hexmask.long.byte 0xD28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD28 8.--15. 1. "FVB,First valid block" bitfld.long 0xD28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD2C "GFXMMU_LUT421H,GFXMMU LUT entry 421 high" hexmask.long.tbyte 0xD2C 0.--17. 1. "LO,Line offset" line.long 0xD30 "GFXMMU_LUT422L,GFXMMU LUT entry 422 low" hexmask.long.byte 0xD30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD30 8.--15. 1. "FVB,First valid block" bitfld.long 0xD30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD34 "GFXMMU_LUT422H,GFXMMU LUT entry 422 high" hexmask.long.tbyte 0xD34 0.--17. 1. "LO,Line offset" line.long 0xD38 "GFXMMU_LUT423L,GFXMMU LUT entry 423 low" hexmask.long.byte 0xD38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD38 8.--15. 1. "FVB,First valid block" bitfld.long 0xD38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD3C "GFXMMU_LUT423H,GFXMMU LUT entry 423 high" hexmask.long.tbyte 0xD3C 0.--17. 1. "LO,Line offset" line.long 0xD40 "GFXMMU_LUT424L,GFXMMU LUT entry 424 low" hexmask.long.byte 0xD40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD40 8.--15. 1. "FVB,First valid block" bitfld.long 0xD40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD44 "GFXMMU_LUT424H,GFXMMU LUT entry 424 high" hexmask.long.tbyte 0xD44 0.--17. 1. "LO,Line offset" line.long 0xD48 "GFXMMU_LUT425L,GFXMMU LUT entry 425 low" hexmask.long.byte 0xD48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD48 8.--15. 1. "FVB,First valid block" bitfld.long 0xD48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4C "GFXMMU_LUT425H,GFXMMU LUT entry 425 high" hexmask.long.tbyte 0xD4C 0.--17. 1. "LO,Line offset" line.long 0xD50 "GFXMMU_LUT426L,GFXMMU LUT entry 426 low" hexmask.long.byte 0xD50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD50 8.--15. 1. "FVB,First valid block" bitfld.long 0xD50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD54 "GFXMMU_LUT426H,GFXMMU LUT entry 426 high" hexmask.long.tbyte 0xD54 0.--17. 1. "LO,Line offset" line.long 0xD58 "GFXMMU_LUT427L,GFXMMU LUT entry 427 low" hexmask.long.byte 0xD58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD58 8.--15. 1. "FVB,First valid block" bitfld.long 0xD58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD5C "GFXMMU_LUT427H,GFXMMU LUT entry 427 high" hexmask.long.tbyte 0xD5C 0.--17. 1. "LO,Line offset" line.long 0xD60 "GFXMMU_LUT428L,GFXMMU LUT entry 428 low" hexmask.long.byte 0xD60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD60 8.--15. 1. "FVB,First valid block" bitfld.long 0xD60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD64 "GFXMMU_LUT428H,GFXMMU LUT entry 428 high" hexmask.long.tbyte 0xD64 0.--17. 1. "LO,Line offset" line.long 0xD68 "GFXMMU_LUT429L,GFXMMU LUT entry 429 low" hexmask.long.byte 0xD68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD68 8.--15. 1. "FVB,First valid block" bitfld.long 0xD68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD6C "GFXMMU_LUT429H,GFXMMU LUT entry 429 high" hexmask.long.tbyte 0xD6C 0.--17. 1. "LO,Line offset" line.long 0xD70 "GFXMMU_LUT430L,GFXMMU LUT entry 430 low" hexmask.long.byte 0xD70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD70 8.--15. 1. "FVB,First valid block" bitfld.long 0xD70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD74 "GFXMMU_LUT430H,GFXMMU LUT entry 430 high" hexmask.long.tbyte 0xD74 0.--17. 1. "LO,Line offset" line.long 0xD78 "GFXMMU_LUT431L,GFXMMU LUT entry 431 low" hexmask.long.byte 0xD78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD78 8.--15. 1. "FVB,First valid block" bitfld.long 0xD78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD7C "GFXMMU_LUT431H,GFXMMU LUT entry 431 high" hexmask.long.tbyte 0xD7C 0.--17. 1. "LO,Line offset" line.long 0xD80 "GFXMMU_LUT432L,GFXMMU LUT entry 432 low" hexmask.long.byte 0xD80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD80 8.--15. 1. "FVB,First valid block" bitfld.long 0xD80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD84 "GFXMMU_LUT432H,GFXMMU LUT entry 432 high" hexmask.long.tbyte 0xD84 0.--17. 1. "LO,Line offset" line.long 0xD88 "GFXMMU_LUT433L,GFXMMU LUT entry 433 low" hexmask.long.byte 0xD88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD88 8.--15. 1. "FVB,First valid block" bitfld.long 0xD88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD8C "GFXMMU_LUT433H,GFXMMU LUT entry 433 high" hexmask.long.tbyte 0xD8C 0.--17. 1. "LO,Line offset" line.long 0xD90 "GFXMMU_LUT434L,GFXMMU LUT entry 434 low" hexmask.long.byte 0xD90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD90 8.--15. 1. "FVB,First valid block" bitfld.long 0xD90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD94 "GFXMMU_LUT434H,GFXMMU LUT entry 434 high" hexmask.long.tbyte 0xD94 0.--17. 1. "LO,Line offset" line.long 0xD98 "GFXMMU_LUT435L,GFXMMU LUT entry 435 low" hexmask.long.byte 0xD98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD98 8.--15. 1. "FVB,First valid block" bitfld.long 0xD98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD9C "GFXMMU_LUT435H,GFXMMU LUT entry 435 high" hexmask.long.tbyte 0xD9C 0.--17. 1. "LO,Line offset" line.long 0xDA0 "GFXMMU_LUT436L,GFXMMU LUT entry 436 low" hexmask.long.byte 0xDA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDA4 "GFXMMU_LUT436H,GFXMMU LUT entry 436 high" hexmask.long.tbyte 0xDA4 0.--17. 1. "LO,Line offset" line.long 0xDA8 "GFXMMU_LUT437L,GFXMMU LUT entry 437 low" hexmask.long.byte 0xDA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDAC "GFXMMU_LUT437H,GFXMMU LUT entry 437 high" hexmask.long.tbyte 0xDAC 0.--17. 1. "LO,Line offset" line.long 0xDB0 "GFXMMU_LUT438L,GFXMMU LUT entry 438 low" hexmask.long.byte 0xDB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDB4 "GFXMMU_LUT438H,GFXMMU LUT entry 438 high" hexmask.long.tbyte 0xDB4 0.--17. 1. "LO,Line offset" line.long 0xDB8 "GFXMMU_LUT439L,GFXMMU LUT entry 439 low" hexmask.long.byte 0xDB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDBC "GFXMMU_LUT439H,GFXMMU LUT entry 439 high" hexmask.long.tbyte 0xDBC 0.--17. 1. "LO,Line offset" line.long 0xDC0 "GFXMMU_LUT440L,GFXMMU LUT entry 440 low" hexmask.long.byte 0xDC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC4 "GFXMMU_LUT440H,GFXMMU LUT entry 440 high" hexmask.long.tbyte 0xDC4 0.--17. 1. "LO,Line offset" line.long 0xDC8 "GFXMMU_LUT441L,GFXMMU LUT entry 441 low" hexmask.long.byte 0xDC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDCC "GFXMMU_LUT441H,GFXMMU LUT entry 441 high" hexmask.long.tbyte 0xDCC 0.--17. 1. "LO,Line offset" line.long 0xDD0 "GFXMMU_LUT442L,GFXMMU LUT entry 442 low" hexmask.long.byte 0xDD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDD4 "GFXMMU_LUT442H,GFXMMU LUT entry 442 high" hexmask.long.tbyte 0xDD4 0.--17. 1. "LO,Line offset" line.long 0xDD8 "GFXMMU_LUT443L,GFXMMU LUT entry 443 low" hexmask.long.byte 0xDD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDDC "GFXMMU_LUT443H,GFXMMU LUT entry 443 high" hexmask.long.tbyte 0xDDC 0.--17. 1. "LO,Line offset" line.long 0xDE0 "GFXMMU_LUT444L,GFXMMU LUT entry 444 low" hexmask.long.byte 0xDE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDE4 "GFXMMU_LUT444H,GFXMMU LUT entry 444 high" hexmask.long.tbyte 0xDE4 0.--17. 1. "LO,Line offset" line.long 0xDE8 "GFXMMU_LUT445L,GFXMMU LUT entry 445 low" hexmask.long.byte 0xDE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDEC "GFXMMU_LUT445H,GFXMMU LUT entry 445 high" hexmask.long.tbyte 0xDEC 0.--17. 1. "LO,Line offset" line.long 0xDF0 "GFXMMU_LUT446L,GFXMMU LUT entry 446 low" hexmask.long.byte 0xDF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDF4 "GFXMMU_LUT446H,GFXMMU LUT entry 446 high" hexmask.long.tbyte 0xDF4 0.--17. 1. "LO,Line offset" line.long 0xDF8 "GFXMMU_LUT447L,GFXMMU LUT entry 447 low" hexmask.long.byte 0xDF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDFC "GFXMMU_LUT447H,GFXMMU LUT entry 447 high" hexmask.long.tbyte 0xDFC 0.--17. 1. "LO,Line offset" line.long 0xE00 "GFXMMU_LUT448L,GFXMMU LUT entry 448 low" hexmask.long.byte 0xE00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE00 8.--15. 1. "FVB,First valid block" bitfld.long 0xE00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE04 "GFXMMU_LUT448H,GFXMMU LUT entry 448 high" hexmask.long.tbyte 0xE04 0.--17. 1. "LO,Line offset" line.long 0xE08 "GFXMMU_LUT449L,GFXMMU LUT entry 449 low" hexmask.long.byte 0xE08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE08 8.--15. 1. "FVB,First valid block" bitfld.long 0xE08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE0C "GFXMMU_LUT449H,GFXMMU LUT entry 449 high" hexmask.long.tbyte 0xE0C 0.--17. 1. "LO,Line offset" line.long 0xE10 "GFXMMU_LUT450L,GFXMMU LUT entry 450 low" hexmask.long.byte 0xE10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE10 8.--15. 1. "FVB,First valid block" bitfld.long 0xE10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE14 "GFXMMU_LUT450H,GFXMMU LUT entry 450 high" hexmask.long.tbyte 0xE14 0.--17. 1. "LO,Line offset" line.long 0xE18 "GFXMMU_LUT451L,GFXMMU LUT entry 451 low" hexmask.long.byte 0xE18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE18 8.--15. 1. "FVB,First valid block" bitfld.long 0xE18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE1C "GFXMMU_LUT451H,GFXMMU LUT entry 451 high" hexmask.long.tbyte 0xE1C 0.--17. 1. "LO,Line offset" line.long 0xE20 "GFXMMU_LUT452L,GFXMMU LUT entry 452 low" hexmask.long.byte 0xE20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE20 8.--15. 1. "FVB,First valid block" bitfld.long 0xE20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE24 "GFXMMU_LUT452H,GFXMMU LUT entry 452 high" hexmask.long.tbyte 0xE24 0.--17. 1. "LO,Line offset" line.long 0xE28 "GFXMMU_LUT453L,GFXMMU LUT entry 453 low" hexmask.long.byte 0xE28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE28 8.--15. 1. "FVB,First valid block" bitfld.long 0xE28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE2C "GFXMMU_LUT453H,GFXMMU LUT entry 453 high" hexmask.long.tbyte 0xE2C 0.--17. 1. "LO,Line offset" line.long 0xE30 "GFXMMU_LUT454L,GFXMMU LUT entry 454 low" hexmask.long.byte 0xE30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE30 8.--15. 1. "FVB,First valid block" bitfld.long 0xE30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE34 "GFXMMU_LUT454H,GFXMMU LUT entry 454 high" hexmask.long.tbyte 0xE34 0.--17. 1. "LO,Line offset" line.long 0xE38 "GFXMMU_LUT455L,GFXMMU LUT entry 455 low" hexmask.long.byte 0xE38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE38 8.--15. 1. "FVB,First valid block" bitfld.long 0xE38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE3C "GFXMMU_LUT455H,GFXMMU LUT entry 455 high" hexmask.long.tbyte 0xE3C 0.--17. 1. "LO,Line offset" line.long 0xE40 "GFXMMU_LUT456L,GFXMMU LUT entry 456 low" hexmask.long.byte 0xE40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE40 8.--15. 1. "FVB,First valid block" bitfld.long 0xE40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE44 "GFXMMU_LUT456H,GFXMMU LUT entry 456 high" hexmask.long.tbyte 0xE44 0.--17. 1. "LO,Line offset" line.long 0xE48 "GFXMMU_LUT457L,GFXMMU LUT entry 457 low" hexmask.long.byte 0xE48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE48 8.--15. 1. "FVB,First valid block" bitfld.long 0xE48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4C "GFXMMU_LUT457H,GFXMMU LUT entry 457 high" hexmask.long.tbyte 0xE4C 0.--17. 1. "LO,Line offset" line.long 0xE50 "GFXMMU_LUT458L,GFXMMU LUT entry 458 low" hexmask.long.byte 0xE50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE50 8.--15. 1. "FVB,First valid block" bitfld.long 0xE50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE54 "GFXMMU_LUT458H,GFXMMU LUT entry 458 high" hexmask.long.tbyte 0xE54 0.--17. 1. "LO,Line offset" line.long 0xE58 "GFXMMU_LUT459L,GFXMMU LUT entry 459 low" hexmask.long.byte 0xE58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE58 8.--15. 1. "FVB,First valid block" bitfld.long 0xE58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE5C "GFXMMU_LUT459H,GFXMMU LUT entry 459 high" hexmask.long.tbyte 0xE5C 0.--17. 1. "LO,Line offset" line.long 0xE60 "GFXMMU_LUT460L,GFXMMU LUT entry 460 low" hexmask.long.byte 0xE60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE60 8.--15. 1. "FVB,First valid block" bitfld.long 0xE60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE64 "GFXMMU_LUT460H,GFXMMU LUT entry 460 high" hexmask.long.tbyte 0xE64 0.--17. 1. "LO,Line offset" line.long 0xE68 "GFXMMU_LUT461L,GFXMMU LUT entry 461 low" hexmask.long.byte 0xE68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE68 8.--15. 1. "FVB,First valid block" bitfld.long 0xE68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE6C "GFXMMU_LUT461H,GFXMMU LUT entry 461 high" hexmask.long.tbyte 0xE6C 0.--17. 1. "LO,Line offset" line.long 0xE70 "GFXMMU_LUT462L,GFXMMU LUT entry 462 low" hexmask.long.byte 0xE70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE70 8.--15. 1. "FVB,First valid block" bitfld.long 0xE70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE74 "GFXMMU_LUT462H,GFXMMU LUT entry 462 high" hexmask.long.tbyte 0xE74 0.--17. 1. "LO,Line offset" line.long 0xE78 "GFXMMU_LUT463L,GFXMMU LUT entry 463 low" hexmask.long.byte 0xE78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE78 8.--15. 1. "FVB,First valid block" bitfld.long 0xE78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE7C "GFXMMU_LUT463H,GFXMMU LUT entry 463 high" hexmask.long.tbyte 0xE7C 0.--17. 1. "LO,Line offset" line.long 0xE80 "GFXMMU_LUT464L,GFXMMU LUT entry 464 low" hexmask.long.byte 0xE80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE80 8.--15. 1. "FVB,First valid block" bitfld.long 0xE80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE84 "GFXMMU_LUT464H,GFXMMU LUT entry 464 high" hexmask.long.tbyte 0xE84 0.--17. 1. "LO,Line offset" line.long 0xE88 "GFXMMU_LUT465L,GFXMMU LUT entry 465 low" hexmask.long.byte 0xE88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE88 8.--15. 1. "FVB,First valid block" bitfld.long 0xE88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE8C "GFXMMU_LUT465H,GFXMMU LUT entry 465 high" hexmask.long.tbyte 0xE8C 0.--17. 1. "LO,Line offset" line.long 0xE90 "GFXMMU_LUT466L,GFXMMU LUT entry 466 low" hexmask.long.byte 0xE90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE90 8.--15. 1. "FVB,First valid block" bitfld.long 0xE90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE94 "GFXMMU_LUT466H,GFXMMU LUT entry 466 high" hexmask.long.tbyte 0xE94 0.--17. 1. "LO,Line offset" line.long 0xE98 "GFXMMU_LUT467L,GFXMMU LUT entry 467 low" hexmask.long.byte 0xE98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE98 8.--15. 1. "FVB,First valid block" bitfld.long 0xE98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE9C "GFXMMU_LUT467H,GFXMMU LUT entry 467 high" hexmask.long.tbyte 0xE9C 0.--17. 1. "LO,Line offset" line.long 0xEA0 "GFXMMU_LUT468L,GFXMMU LUT entry 468 low" hexmask.long.byte 0xEA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEA4 "GFXMMU_LUT468H,GFXMMU LUT entry 468 high" hexmask.long.tbyte 0xEA4 0.--17. 1. "LO,Line offset" line.long 0xEA8 "GFXMMU_LUT469L,GFXMMU LUT entry 469 low" hexmask.long.byte 0xEA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEAC "GFXMMU_LUT469H,GFXMMU LUT entry 469 high" hexmask.long.tbyte 0xEAC 0.--17. 1. "LO,Line offset" line.long 0xEB0 "GFXMMU_LUT470L,GFXMMU LUT entry 470 low" hexmask.long.byte 0xEB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEB4 "GFXMMU_LUT470H,GFXMMU LUT entry 470 high" hexmask.long.tbyte 0xEB4 0.--17. 1. "LO,Line offset" line.long 0xEB8 "GFXMMU_LUT471L,GFXMMU LUT entry 471 low" hexmask.long.byte 0xEB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEBC "GFXMMU_LUT471H,GFXMMU LUT entry 471 high" hexmask.long.tbyte 0xEBC 0.--17. 1. "LO,Line offset" line.long 0xEC0 "GFXMMU_LUT472L,GFXMMU LUT entry 472 low" hexmask.long.byte 0xEC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC4 "GFXMMU_LUT472H,GFXMMU LUT entry 472 high" hexmask.long.tbyte 0xEC4 0.--17. 1. "LO,Line offset" line.long 0xEC8 "GFXMMU_LUT473L,GFXMMU LUT entry 473 low" hexmask.long.byte 0xEC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xECC "GFXMMU_LUT473H,GFXMMU LUT entry 473 high" hexmask.long.tbyte 0xECC 0.--17. 1. "LO,Line offset" line.long 0xED0 "GFXMMU_LUT474L,GFXMMU LUT entry 474 low" hexmask.long.byte 0xED0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xED0 8.--15. 1. "FVB,First valid block" bitfld.long 0xED0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xED4 "GFXMMU_LUT474H,GFXMMU LUT entry 474 high" hexmask.long.tbyte 0xED4 0.--17. 1. "LO,Line offset" line.long 0xED8 "GFXMMU_LUT475L,GFXMMU LUT entry 475 low" hexmask.long.byte 0xED8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xED8 8.--15. 1. "FVB,First valid block" bitfld.long 0xED8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEDC "GFXMMU_LUT475H,GFXMMU LUT entry 475 high" hexmask.long.tbyte 0xEDC 0.--17. 1. "LO,Line offset" line.long 0xEE0 "GFXMMU_LUT476L,GFXMMU LUT entry 476 low" hexmask.long.byte 0xEE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEE4 "GFXMMU_LUT476H,GFXMMU LUT entry 476 high" hexmask.long.tbyte 0xEE4 0.--17. 1. "LO,Line offset" line.long 0xEE8 "GFXMMU_LUT477L,GFXMMU LUT entry 477 low" hexmask.long.byte 0xEE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEEC "GFXMMU_LUT477H,GFXMMU LUT entry 477 high" hexmask.long.tbyte 0xEEC 0.--17. 1. "LO,Line offset" line.long 0xEF0 "GFXMMU_LUT478L,GFXMMU LUT entry 478 low" hexmask.long.byte 0xEF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEF4 "GFXMMU_LUT478H,GFXMMU LUT entry 478 high" hexmask.long.tbyte 0xEF4 0.--17. 1. "LO,Line offset" line.long 0xEF8 "GFXMMU_LUT479L,GFXMMU LUT entry 479 low" hexmask.long.byte 0xEF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEFC "GFXMMU_LUT479H,GFXMMU LUT entry 479 high" hexmask.long.tbyte 0xEFC 0.--17. 1. "LO,Line offset" line.long 0xF00 "GFXMMU_LUT480L,GFXMMU LUT entry 480 low" hexmask.long.byte 0xF00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF00 8.--15. 1. "FVB,First valid block" bitfld.long 0xF00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF04 "GFXMMU_LUT480H,GFXMMU LUT entry 480 high" hexmask.long.tbyte 0xF04 0.--17. 1. "LO,Line offset" line.long 0xF08 "GFXMMU_LUT481L,GFXMMU LUT entry 481 low" hexmask.long.byte 0xF08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF08 8.--15. 1. "FVB,First valid block" bitfld.long 0xF08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF0C "GFXMMU_LUT481H,GFXMMU LUT entry 481 high" hexmask.long.tbyte 0xF0C 0.--17. 1. "LO,Line offset" line.long 0xF10 "GFXMMU_LUT482L,GFXMMU LUT entry 482 low" hexmask.long.byte 0xF10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF10 8.--15. 1. "FVB,First valid block" bitfld.long 0xF10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF14 "GFXMMU_LUT482H,GFXMMU LUT entry 482 high" hexmask.long.tbyte 0xF14 0.--17. 1. "LO,Line offset" line.long 0xF18 "GFXMMU_LUT483L,GFXMMU LUT entry 483 low" hexmask.long.byte 0xF18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF18 8.--15. 1. "FVB,First valid block" bitfld.long 0xF18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF1C "GFXMMU_LUT483H,GFXMMU LUT entry 483 high" hexmask.long.tbyte 0xF1C 0.--17. 1. "LO,Line offset" line.long 0xF20 "GFXMMU_LUT484L,GFXMMU LUT entry 484 low" hexmask.long.byte 0xF20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF20 8.--15. 1. "FVB,First valid block" bitfld.long 0xF20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF24 "GFXMMU_LUT484H,GFXMMU LUT entry 484 high" hexmask.long.tbyte 0xF24 0.--17. 1. "LO,Line offset" line.long 0xF28 "GFXMMU_LUT485L,GFXMMU LUT entry 485 low" hexmask.long.byte 0xF28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF28 8.--15. 1. "FVB,First valid block" bitfld.long 0xF28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF2C "GFXMMU_LUT485H,GFXMMU LUT entry 485 high" hexmask.long.tbyte 0xF2C 0.--17. 1. "LO,Line offset" line.long 0xF30 "GFXMMU_LUT486L,GFXMMU LUT entry 486 low" hexmask.long.byte 0xF30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF30 8.--15. 1. "FVB,First valid block" bitfld.long 0xF30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF34 "GFXMMU_LUT486H,GFXMMU LUT entry 486 high" hexmask.long.tbyte 0xF34 0.--17. 1. "LO,Line offset" line.long 0xF38 "GFXMMU_LUT487L,GFXMMU LUT entry 487 low" hexmask.long.byte 0xF38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF38 8.--15. 1. "FVB,First valid block" bitfld.long 0xF38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF3C "GFXMMU_LUT487H,GFXMMU LUT entry 487 high" hexmask.long.tbyte 0xF3C 0.--17. 1. "LO,Line offset" line.long 0xF40 "GFXMMU_LUT488L,GFXMMU LUT entry 488 low" hexmask.long.byte 0xF40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF40 8.--15. 1. "FVB,First valid block" bitfld.long 0xF40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF44 "GFXMMU_LUT488H,GFXMMU LUT entry 488 high" hexmask.long.tbyte 0xF44 0.--17. 1. "LO,Line offset" line.long 0xF48 "GFXMMU_LUT489L,GFXMMU LUT entry 489 low" hexmask.long.byte 0xF48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF48 8.--15. 1. "FVB,First valid block" bitfld.long 0xF48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4C "GFXMMU_LUT489H,GFXMMU LUT entry 489 high" hexmask.long.tbyte 0xF4C 0.--17. 1. "LO,Line offset" line.long 0xF50 "GFXMMU_LUT490L,GFXMMU LUT entry 490 low" hexmask.long.byte 0xF50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF50 8.--15. 1. "FVB,First valid block" bitfld.long 0xF50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF54 "GFXMMU_LUT490H,GFXMMU LUT entry 490 high" hexmask.long.tbyte 0xF54 0.--17. 1. "LO,Line offset" line.long 0xF58 "GFXMMU_LUT491L,GFXMMU LUT entry 491 low" hexmask.long.byte 0xF58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF58 8.--15. 1. "FVB,First valid block" bitfld.long 0xF58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF5C "GFXMMU_LUT491H,GFXMMU LUT entry 491 high" hexmask.long.tbyte 0xF5C 0.--17. 1. "LO,Line offset" line.long 0xF60 "GFXMMU_LUT492L,GFXMMU LUT entry 492 low" hexmask.long.byte 0xF60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF60 8.--15. 1. "FVB,First valid block" bitfld.long 0xF60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF64 "GFXMMU_LUT492H,GFXMMU LUT entry 492 high" hexmask.long.tbyte 0xF64 0.--17. 1. "LO,Line offset" line.long 0xF68 "GFXMMU_LUT493L,GFXMMU LUT entry 493 low" hexmask.long.byte 0xF68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF68 8.--15. 1. "FVB,First valid block" bitfld.long 0xF68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF6C "GFXMMU_LUT493H,GFXMMU LUT entry 493 high" hexmask.long.tbyte 0xF6C 0.--17. 1. "LO,Line offset" line.long 0xF70 "GFXMMU_LUT494L,GFXMMU LUT entry 494 low" hexmask.long.byte 0xF70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF70 8.--15. 1. "FVB,First valid block" bitfld.long 0xF70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF74 "GFXMMU_LUT494H,GFXMMU LUT entry 494 high" hexmask.long.tbyte 0xF74 0.--17. 1. "LO,Line offset" line.long 0xF78 "GFXMMU_LUT495L,GFXMMU LUT entry 495 low" hexmask.long.byte 0xF78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF78 8.--15. 1. "FVB,First valid block" bitfld.long 0xF78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF7C "GFXMMU_LUT495H,GFXMMU LUT entry 495 high" hexmask.long.tbyte 0xF7C 0.--17. 1. "LO,Line offset" line.long 0xF80 "GFXMMU_LUT496L,GFXMMU LUT entry 496 low" hexmask.long.byte 0xF80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF80 8.--15. 1. "FVB,First valid block" bitfld.long 0xF80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF84 "GFXMMU_LUT496H,GFXMMU LUT entry 496 high" hexmask.long.tbyte 0xF84 0.--17. 1. "LO,Line offset" line.long 0xF88 "GFXMMU_LUT497L,GFXMMU LUT entry 497 low" hexmask.long.byte 0xF88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF88 8.--15. 1. "FVB,First valid block" bitfld.long 0xF88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF8C "GFXMMU_LUT497H,GFXMMU LUT entry 497 high" hexmask.long.tbyte 0xF8C 0.--17. 1. "LO,Line offset" line.long 0xF90 "GFXMMU_LUT498L,GFXMMU LUT entry 498 low" hexmask.long.byte 0xF90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF90 8.--15. 1. "FVB,First valid block" bitfld.long 0xF90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF94 "GFXMMU_LUT498H,GFXMMU LUT entry 498 high" hexmask.long.tbyte 0xF94 0.--17. 1. "LO,Line offset" line.long 0xF98 "GFXMMU_LUT499L,GFXMMU LUT entry 499 low" hexmask.long.byte 0xF98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF98 8.--15. 1. "FVB,First valid block" bitfld.long 0xF98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF9C "GFXMMU_LUT499H,GFXMMU LUT entry 499 high" hexmask.long.tbyte 0xF9C 0.--17. 1. "LO,Line offset" line.long 0xFA0 "GFXMMU_LUT500L,GFXMMU LUT entry 500 low" hexmask.long.byte 0xFA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFA4 "GFXMMU_LUT500H,GFXMMU LUT entry 500 high" hexmask.long.tbyte 0xFA4 0.--17. 1. "LO,Line offset" line.long 0xFA8 "GFXMMU_LUT501L,GFXMMU LUT entry 501 low" hexmask.long.byte 0xFA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFAC "GFXMMU_LUT501H,GFXMMU LUT entry 501 high" hexmask.long.tbyte 0xFAC 0.--17. 1. "LO,Line offset" line.long 0xFB0 "GFXMMU_LUT502L,GFXMMU LUT entry 502 low" hexmask.long.byte 0xFB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFB4 "GFXMMU_LUT502H,GFXMMU LUT entry 502 high" hexmask.long.tbyte 0xFB4 0.--17. 1. "LO,Line offset" line.long 0xFB8 "GFXMMU_LUT503L,GFXMMU LUT entry 503 low" hexmask.long.byte 0xFB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFBC "GFXMMU_LUT503H,GFXMMU LUT entry 503 high" hexmask.long.tbyte 0xFBC 0.--17. 1. "LO,Line offset" line.long 0xFC0 "GFXMMU_LUT504L,GFXMMU LUT entry 504 low" hexmask.long.byte 0xFC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC4 "GFXMMU_LUT504H,GFXMMU LUT entry 504 high" hexmask.long.tbyte 0xFC4 0.--17. 1. "LO,Line offset" line.long 0xFC8 "GFXMMU_LUT505L,GFXMMU LUT entry 505 low" hexmask.long.byte 0xFC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFCC "GFXMMU_LUT505H,GFXMMU LUT entry 505 high" hexmask.long.tbyte 0xFCC 0.--17. 1. "LO,Line offset" line.long 0xFD0 "GFXMMU_LUT506L,GFXMMU LUT entry 506 low" hexmask.long.byte 0xFD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFD4 "GFXMMU_LUT506H,GFXMMU LUT entry 506 high" hexmask.long.tbyte 0xFD4 0.--17. 1. "LO,Line offset" line.long 0xFD8 "GFXMMU_LUT507L,GFXMMU LUT entry 507 low" hexmask.long.byte 0xFD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFDC "GFXMMU_LUT507H,GFXMMU LUT entry 507 high" hexmask.long.tbyte 0xFDC 0.--17. 1. "LO,Line offset" line.long 0xFE0 "GFXMMU_LUT508L,GFXMMU LUT entry 508 low" hexmask.long.byte 0xFE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFE4 "GFXMMU_LUT508H,GFXMMU LUT entry 508 high" hexmask.long.tbyte 0xFE4 0.--17. 1. "LO,Line offset" line.long 0xFE8 "GFXMMU_LUT509L,GFXMMU LUT entry 509 low" hexmask.long.byte 0xFE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFEC "GFXMMU_LUT509H,GFXMMU LUT entry 509 high" hexmask.long.tbyte 0xFEC 0.--17. 1. "LO,Line offset" line.long 0xFF0 "GFXMMU_LUT510L,GFXMMU LUT entry 510 low" hexmask.long.byte 0xFF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFF4 "GFXMMU_LUT510H,GFXMMU LUT entry 510 high" hexmask.long.tbyte 0xFF4 0.--17. 1. "LO,Line offset" line.long 0xFF8 "GFXMMU_LUT511L,GFXMMU LUT entry 511 low" hexmask.long.byte 0xFF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFFC "GFXMMU_LUT511H,GFXMMU LUT entry 511 high" hexmask.long.tbyte 0xFFC 0.--17. 1. "LO,Line offset" group.long 0x2000++0xFFF line.long 0x0 "GFXMMU_LUT512L,GFXMMU LUT entry 512 low" hexmask.long.byte 0x0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x0 8.--15. 1. "FVB,First valid block" bitfld.long 0x0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4 "GFXMMU_LUT512H,GFXMMU LUT entry 512 high" hexmask.long.tbyte 0x4 0.--17. 1. "LO,Line offset" line.long 0x8 "GFXMMU_LUT513L,GFXMMU LUT entry 513 low" hexmask.long.byte 0x8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC "GFXMMU_LUT513H,GFXMMU LUT entry 513 high" hexmask.long.tbyte 0xC 0.--17. 1. "LO,Line offset" line.long 0x10 "GFXMMU_LUT514L,GFXMMU LUT entry 514 low" hexmask.long.byte 0x10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x10 8.--15. 1. "FVB,First valid block" bitfld.long 0x10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14 "GFXMMU_LUT514H,GFXMMU LUT entry 514 high" hexmask.long.tbyte 0x14 0.--17. 1. "LO,Line offset" line.long 0x18 "GFXMMU_LUT515L,GFXMMU LUT entry 515 low" hexmask.long.byte 0x18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x18 8.--15. 1. "FVB,First valid block" bitfld.long 0x18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C "GFXMMU_LUT515H,GFXMMU LUT entry 515 high" hexmask.long.tbyte 0x1C 0.--17. 1. "LO,Line offset" line.long 0x20 "GFXMMU_LUT516L,GFXMMU LUT entry 516 low" hexmask.long.byte 0x20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x20 8.--15. 1. "FVB,First valid block" bitfld.long 0x20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24 "GFXMMU_LUT516H,GFXMMU LUT entry 516 high" hexmask.long.tbyte 0x24 0.--17. 1. "LO,Line offset" line.long 0x28 "GFXMMU_LUT517L,GFXMMU LUT entry 517 low" hexmask.long.byte 0x28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x28 8.--15. 1. "FVB,First valid block" bitfld.long 0x28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C "GFXMMU_LUT517H,GFXMMU LUT entry 517 high" hexmask.long.tbyte 0x2C 0.--17. 1. "LO,Line offset" line.long 0x30 "GFXMMU_LUT518L,GFXMMU LUT entry 518 low" hexmask.long.byte 0x30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x30 8.--15. 1. "FVB,First valid block" bitfld.long 0x30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34 "GFXMMU_LUT518H,GFXMMU LUT entry 518 high" hexmask.long.tbyte 0x34 0.--17. 1. "LO,Line offset" line.long 0x38 "GFXMMU_LUT519L,GFXMMU LUT entry 519 low" hexmask.long.byte 0x38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x38 8.--15. 1. "FVB,First valid block" bitfld.long 0x38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C "GFXMMU_LUT519H,GFXMMU LUT entry 519 high" hexmask.long.tbyte 0x3C 0.--17. 1. "LO,Line offset" line.long 0x40 "GFXMMU_LUT520L,GFXMMU LUT entry 520 low" hexmask.long.byte 0x40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x40 8.--15. 1. "FVB,First valid block" bitfld.long 0x40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44 "GFXMMU_LUT520H,GFXMMU LUT entry 520 high" hexmask.long.tbyte 0x44 0.--17. 1. "LO,Line offset" line.long 0x48 "GFXMMU_LUT521L,GFXMMU LUT entry 521 low" hexmask.long.byte 0x48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x48 8.--15. 1. "FVB,First valid block" bitfld.long 0x48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C "GFXMMU_LUT521H,GFXMMU LUT entry 521 high" hexmask.long.tbyte 0x4C 0.--17. 1. "LO,Line offset" line.long 0x50 "GFXMMU_LUT522L,GFXMMU LUT entry 522 low" hexmask.long.byte 0x50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x50 8.--15. 1. "FVB,First valid block" bitfld.long 0x50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54 "GFXMMU_LUT522H,GFXMMU LUT entry 522 high" hexmask.long.tbyte 0x54 0.--17. 1. "LO,Line offset" line.long 0x58 "GFXMMU_LUT523L,GFXMMU LUT entry 523 low" hexmask.long.byte 0x58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x58 8.--15. 1. "FVB,First valid block" bitfld.long 0x58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C "GFXMMU_LUT523H,GFXMMU LUT entry 523 high" hexmask.long.tbyte 0x5C 0.--17. 1. "LO,Line offset" line.long 0x60 "GFXMMU_LUT524L,GFXMMU LUT entry 524 low" hexmask.long.byte 0x60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x60 8.--15. 1. "FVB,First valid block" bitfld.long 0x60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64 "GFXMMU_LUT524H,GFXMMU LUT entry 524 high" hexmask.long.tbyte 0x64 0.--17. 1. "LO,Line offset" line.long 0x68 "GFXMMU_LUT525L,GFXMMU LUT entry 525 low" hexmask.long.byte 0x68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x68 8.--15. 1. "FVB,First valid block" bitfld.long 0x68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C "GFXMMU_LUT525H,GFXMMU LUT entry 525 high" hexmask.long.tbyte 0x6C 0.--17. 1. "LO,Line offset" line.long 0x70 "GFXMMU_LUT526L,GFXMMU LUT entry 526 low" hexmask.long.byte 0x70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x70 8.--15. 1. "FVB,First valid block" bitfld.long 0x70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74 "GFXMMU_LUT526H,GFXMMU LUT entry 526 high" hexmask.long.tbyte 0x74 0.--17. 1. "LO,Line offset" line.long 0x78 "GFXMMU_LUT527L,GFXMMU LUT entry 527 low" hexmask.long.byte 0x78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x78 8.--15. 1. "FVB,First valid block" bitfld.long 0x78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C "GFXMMU_LUT527H,GFXMMU LUT entry 527 high" hexmask.long.tbyte 0x7C 0.--17. 1. "LO,Line offset" line.long 0x80 "GFXMMU_LUT528L,GFXMMU LUT entry 528 low" hexmask.long.byte 0x80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x80 8.--15. 1. "FVB,First valid block" bitfld.long 0x80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84 "GFXMMU_LUT528H,GFXMMU LUT entry 528 high" hexmask.long.tbyte 0x84 0.--17. 1. "LO,Line offset" line.long 0x88 "GFXMMU_LUT529L,GFXMMU LUT entry 529 low" hexmask.long.byte 0x88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x88 8.--15. 1. "FVB,First valid block" bitfld.long 0x88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C "GFXMMU_LUT529H,GFXMMU LUT entry 529 high" hexmask.long.tbyte 0x8C 0.--17. 1. "LO,Line offset" line.long 0x90 "GFXMMU_LUT530L,GFXMMU LUT entry 530 low" hexmask.long.byte 0x90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x90 8.--15. 1. "FVB,First valid block" bitfld.long 0x90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94 "GFXMMU_LUT530H,GFXMMU LUT entry 530 high" hexmask.long.tbyte 0x94 0.--17. 1. "LO,Line offset" line.long 0x98 "GFXMMU_LUT531L,GFXMMU LUT entry 531 low" hexmask.long.byte 0x98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x98 8.--15. 1. "FVB,First valid block" bitfld.long 0x98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C "GFXMMU_LUT531H,GFXMMU LUT entry 531 high" hexmask.long.tbyte 0x9C 0.--17. 1. "LO,Line offset" line.long 0xA0 "GFXMMU_LUT532L,GFXMMU LUT entry 532 low" hexmask.long.byte 0xA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4 "GFXMMU_LUT532H,GFXMMU LUT entry 532 high" hexmask.long.tbyte 0xA4 0.--17. 1. "LO,Line offset" line.long 0xA8 "GFXMMU_LUT533L,GFXMMU LUT entry 533 low" hexmask.long.byte 0xA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC "GFXMMU_LUT533H,GFXMMU LUT entry 533 high" hexmask.long.tbyte 0xAC 0.--17. 1. "LO,Line offset" line.long 0xB0 "GFXMMU_LUT534L,GFXMMU LUT entry 534 low" hexmask.long.byte 0xB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4 "GFXMMU_LUT534H,GFXMMU LUT entry 534 high" hexmask.long.tbyte 0xB4 0.--17. 1. "LO,Line offset" line.long 0xB8 "GFXMMU_LUT535L,GFXMMU LUT entry 535 low" hexmask.long.byte 0xB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC "GFXMMU_LUT535H,GFXMMU LUT entry 535 high" hexmask.long.tbyte 0xBC 0.--17. 1. "LO,Line offset" line.long 0xC0 "GFXMMU_LUT536L,GFXMMU LUT entry 536 low" hexmask.long.byte 0xC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4 "GFXMMU_LUT536H,GFXMMU LUT entry 536 high" hexmask.long.tbyte 0xC4 0.--17. 1. "LO,Line offset" line.long 0xC8 "GFXMMU_LUT537L,GFXMMU LUT entry 537 low" hexmask.long.byte 0xC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC "GFXMMU_LUT537H,GFXMMU LUT entry 537 high" hexmask.long.tbyte 0xCC 0.--17. 1. "LO,Line offset" line.long 0xD0 "GFXMMU_LUT538L,GFXMMU LUT entry 538 low" hexmask.long.byte 0xD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4 "GFXMMU_LUT538H,GFXMMU LUT entry 538 high" hexmask.long.tbyte 0xD4 0.--17. 1. "LO,Line offset" line.long 0xD8 "GFXMMU_LUT539L,GFXMMU LUT entry 539 low" hexmask.long.byte 0xD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC "GFXMMU_LUT539H,GFXMMU LUT entry 539 high" hexmask.long.tbyte 0xDC 0.--17. 1. "LO,Line offset" line.long 0xE0 "GFXMMU_LUT540L,GFXMMU LUT entry 540 low" hexmask.long.byte 0xE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4 "GFXMMU_LUT540H,GFXMMU LUT entry 540 high" hexmask.long.tbyte 0xE4 0.--17. 1. "LO,Line offset" line.long 0xE8 "GFXMMU_LUT541L,GFXMMU LUT entry 541 low" hexmask.long.byte 0xE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC "GFXMMU_LUT541H,GFXMMU LUT entry 541 high" hexmask.long.tbyte 0xEC 0.--17. 1. "LO,Line offset" line.long 0xF0 "GFXMMU_LUT542L,GFXMMU LUT entry 542 low" hexmask.long.byte 0xF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4 "GFXMMU_LUT542H,GFXMMU LUT entry 542 high" hexmask.long.tbyte 0xF4 0.--17. 1. "LO,Line offset" line.long 0xF8 "GFXMMU_LUT543L,GFXMMU LUT entry 543 low" hexmask.long.byte 0xF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC "GFXMMU_LUT543H,GFXMMU LUT entry 543 high" hexmask.long.tbyte 0xFC 0.--17. 1. "LO,Line offset" line.long 0x100 "GFXMMU_LUT544L,GFXMMU LUT entry 544 low" hexmask.long.byte 0x100 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x100 8.--15. 1. "FVB,First valid block" bitfld.long 0x100 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x104 "GFXMMU_LUT544H,GFXMMU LUT entry 544 high" hexmask.long.tbyte 0x104 0.--17. 1. "LO,Line offset" line.long 0x108 "GFXMMU_LUT545L,GFXMMU LUT entry 545 low" hexmask.long.byte 0x108 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x108 8.--15. 1. "FVB,First valid block" bitfld.long 0x108 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x10C "GFXMMU_LUT545H,GFXMMU LUT entry 545 high" hexmask.long.tbyte 0x10C 0.--17. 1. "LO,Line offset" line.long 0x110 "GFXMMU_LUT546L,GFXMMU LUT entry 546 low" hexmask.long.byte 0x110 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x110 8.--15. 1. "FVB,First valid block" bitfld.long 0x110 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x114 "GFXMMU_LUT546H,GFXMMU LUT entry 546 high" hexmask.long.tbyte 0x114 0.--17. 1. "LO,Line offset" line.long 0x118 "GFXMMU_LUT547L,GFXMMU LUT entry 547 low" hexmask.long.byte 0x118 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x118 8.--15. 1. "FVB,First valid block" bitfld.long 0x118 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x11C "GFXMMU_LUT547H,GFXMMU LUT entry 547 high" hexmask.long.tbyte 0x11C 0.--17. 1. "LO,Line offset" line.long 0x120 "GFXMMU_LUT548L,GFXMMU LUT entry 548 low" hexmask.long.byte 0x120 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x120 8.--15. 1. "FVB,First valid block" bitfld.long 0x120 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x124 "GFXMMU_LUT548H,GFXMMU LUT entry 548 high" hexmask.long.tbyte 0x124 0.--17. 1. "LO,Line offset" line.long 0x128 "GFXMMU_LUT549L,GFXMMU LUT entry 549 low" hexmask.long.byte 0x128 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x128 8.--15. 1. "FVB,First valid block" bitfld.long 0x128 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x12C "GFXMMU_LUT549H,GFXMMU LUT entry 549 high" hexmask.long.tbyte 0x12C 0.--17. 1. "LO,Line offset" line.long 0x130 "GFXMMU_LUT550L,GFXMMU LUT entry 550 low" hexmask.long.byte 0x130 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x130 8.--15. 1. "FVB,First valid block" bitfld.long 0x130 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x134 "GFXMMU_LUT550H,GFXMMU LUT entry 550 high" hexmask.long.tbyte 0x134 0.--17. 1. "LO,Line offset" line.long 0x138 "GFXMMU_LUT551L,GFXMMU LUT entry 551 low" hexmask.long.byte 0x138 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x138 8.--15. 1. "FVB,First valid block" bitfld.long 0x138 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x13C "GFXMMU_LUT551H,GFXMMU LUT entry 551 high" hexmask.long.tbyte 0x13C 0.--17. 1. "LO,Line offset" line.long 0x140 "GFXMMU_LUT552L,GFXMMU LUT entry 552 low" hexmask.long.byte 0x140 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x140 8.--15. 1. "FVB,First valid block" bitfld.long 0x140 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x144 "GFXMMU_LUT552H,GFXMMU LUT entry 552 high" hexmask.long.tbyte 0x144 0.--17. 1. "LO,Line offset" line.long 0x148 "GFXMMU_LUT553L,GFXMMU LUT entry 553 low" hexmask.long.byte 0x148 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x148 8.--15. 1. "FVB,First valid block" bitfld.long 0x148 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14C "GFXMMU_LUT553H,GFXMMU LUT entry 553 high" hexmask.long.tbyte 0x14C 0.--17. 1. "LO,Line offset" line.long 0x150 "GFXMMU_LUT554L,GFXMMU LUT entry 554 low" hexmask.long.byte 0x150 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x150 8.--15. 1. "FVB,First valid block" bitfld.long 0x150 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x154 "GFXMMU_LUT554H,GFXMMU LUT entry 554 high" hexmask.long.tbyte 0x154 0.--17. 1. "LO,Line offset" line.long 0x158 "GFXMMU_LUT555L,GFXMMU LUT entry 555 low" hexmask.long.byte 0x158 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x158 8.--15. 1. "FVB,First valid block" bitfld.long 0x158 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x15C "GFXMMU_LUT555H,GFXMMU LUT entry 555 high" hexmask.long.tbyte 0x15C 0.--17. 1. "LO,Line offset" line.long 0x160 "GFXMMU_LUT556L,GFXMMU LUT entry 556 low" hexmask.long.byte 0x160 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x160 8.--15. 1. "FVB,First valid block" bitfld.long 0x160 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x164 "GFXMMU_LUT556H,GFXMMU LUT entry 556 high" hexmask.long.tbyte 0x164 0.--17. 1. "LO,Line offset" line.long 0x168 "GFXMMU_LUT557L,GFXMMU LUT entry 557 low" hexmask.long.byte 0x168 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x168 8.--15. 1. "FVB,First valid block" bitfld.long 0x168 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x16C "GFXMMU_LUT557H,GFXMMU LUT entry 557 high" hexmask.long.tbyte 0x16C 0.--17. 1. "LO,Line offset" line.long 0x170 "GFXMMU_LUT558L,GFXMMU LUT entry 558 low" hexmask.long.byte 0x170 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x170 8.--15. 1. "FVB,First valid block" bitfld.long 0x170 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x174 "GFXMMU_LUT558H,GFXMMU LUT entry 558 high" hexmask.long.tbyte 0x174 0.--17. 1. "LO,Line offset" line.long 0x178 "GFXMMU_LUT559L,GFXMMU LUT entry 559 low" hexmask.long.byte 0x178 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x178 8.--15. 1. "FVB,First valid block" bitfld.long 0x178 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x17C "GFXMMU_LUT559H,GFXMMU LUT entry 559 high" hexmask.long.tbyte 0x17C 0.--17. 1. "LO,Line offset" line.long 0x180 "GFXMMU_LUT560L,GFXMMU LUT entry 560 low" hexmask.long.byte 0x180 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x180 8.--15. 1. "FVB,First valid block" bitfld.long 0x180 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x184 "GFXMMU_LUT560H,GFXMMU LUT entry 560 high" hexmask.long.tbyte 0x184 0.--17. 1. "LO,Line offset" line.long 0x188 "GFXMMU_LUT561L,GFXMMU LUT entry 561 low" hexmask.long.byte 0x188 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x188 8.--15. 1. "FVB,First valid block" bitfld.long 0x188 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x18C "GFXMMU_LUT561H,GFXMMU LUT entry 561 high" hexmask.long.tbyte 0x18C 0.--17. 1. "LO,Line offset" line.long 0x190 "GFXMMU_LUT562L,GFXMMU LUT entry 562 low" hexmask.long.byte 0x190 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x190 8.--15. 1. "FVB,First valid block" bitfld.long 0x190 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x194 "GFXMMU_LUT562H,GFXMMU LUT entry 562 high" hexmask.long.tbyte 0x194 0.--17. 1. "LO,Line offset" line.long 0x198 "GFXMMU_LUT563L,GFXMMU LUT entry 563 low" hexmask.long.byte 0x198 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x198 8.--15. 1. "FVB,First valid block" bitfld.long 0x198 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x19C "GFXMMU_LUT563H,GFXMMU LUT entry 563 high" hexmask.long.tbyte 0x19C 0.--17. 1. "LO,Line offset" line.long 0x1A0 "GFXMMU_LUT564L,GFXMMU LUT entry 564 low" hexmask.long.byte 0x1A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1A4 "GFXMMU_LUT564H,GFXMMU LUT entry 564 high" hexmask.long.tbyte 0x1A4 0.--17. 1. "LO,Line offset" line.long 0x1A8 "GFXMMU_LUT565L,GFXMMU LUT entry 565 low" hexmask.long.byte 0x1A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1AC "GFXMMU_LUT565H,GFXMMU LUT entry 565 high" hexmask.long.tbyte 0x1AC 0.--17. 1. "LO,Line offset" line.long 0x1B0 "GFXMMU_LUT566L,GFXMMU LUT entry 566 low" hexmask.long.byte 0x1B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1B4 "GFXMMU_LUT566H,GFXMMU LUT entry 566 high" hexmask.long.tbyte 0x1B4 0.--17. 1. "LO,Line offset" line.long 0x1B8 "GFXMMU_LUT567L,GFXMMU LUT entry 567 low" hexmask.long.byte 0x1B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1BC "GFXMMU_LUT567H,GFXMMU LUT entry 567 high" hexmask.long.tbyte 0x1BC 0.--17. 1. "LO,Line offset" line.long 0x1C0 "GFXMMU_LUT568L,GFXMMU LUT entry 568 low" hexmask.long.byte 0x1C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C4 "GFXMMU_LUT568H,GFXMMU LUT entry 568 high" hexmask.long.tbyte 0x1C4 0.--17. 1. "LO,Line offset" line.long 0x1C8 "GFXMMU_LUT569L,GFXMMU LUT entry 569 low" hexmask.long.byte 0x1C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1CC "GFXMMU_LUT569H,GFXMMU LUT entry 569 high" hexmask.long.tbyte 0x1CC 0.--17. 1. "LO,Line offset" line.long 0x1D0 "GFXMMU_LUT570L,GFXMMU LUT entry 570 low" hexmask.long.byte 0x1D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1D4 "GFXMMU_LUT570H,GFXMMU LUT entry 570 high" hexmask.long.tbyte 0x1D4 0.--17. 1. "LO,Line offset" line.long 0x1D8 "GFXMMU_LUT571L,GFXMMU LUT entry 571 low" hexmask.long.byte 0x1D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1DC "GFXMMU_LUT571H,GFXMMU LUT entry 571 high" hexmask.long.tbyte 0x1DC 0.--17. 1. "LO,Line offset" line.long 0x1E0 "GFXMMU_LUT572L,GFXMMU LUT entry 572 low" hexmask.long.byte 0x1E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1E4 "GFXMMU_LUT572H,GFXMMU LUT entry 572 high" hexmask.long.tbyte 0x1E4 0.--17. 1. "LO,Line offset" line.long 0x1E8 "GFXMMU_LUT573L,GFXMMU LUT entry 573 low" hexmask.long.byte 0x1E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1EC "GFXMMU_LUT573H,GFXMMU LUT entry 573 high" hexmask.long.tbyte 0x1EC 0.--17. 1. "LO,Line offset" line.long 0x1F0 "GFXMMU_LUT574L,GFXMMU LUT entry 574 low" hexmask.long.byte 0x1F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1F4 "GFXMMU_LUT574H,GFXMMU LUT entry 574 high" hexmask.long.tbyte 0x1F4 0.--17. 1. "LO,Line offset" line.long 0x1F8 "GFXMMU_LUT575L,GFXMMU LUT entry 575 low" hexmask.long.byte 0x1F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1FC "GFXMMU_LUT575H,GFXMMU LUT entry 575 high" hexmask.long.tbyte 0x1FC 0.--17. 1. "LO,Line offset" line.long 0x200 "GFXMMU_LUT576L,GFXMMU LUT entry 576 low" hexmask.long.byte 0x200 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x200 8.--15. 1. "FVB,First valid block" bitfld.long 0x200 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x204 "GFXMMU_LUT576H,GFXMMU LUT entry 576 high" hexmask.long.tbyte 0x204 0.--17. 1. "LO,Line offset" line.long 0x208 "GFXMMU_LUT577L,GFXMMU LUT entry 577 low" hexmask.long.byte 0x208 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x208 8.--15. 1. "FVB,First valid block" bitfld.long 0x208 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x20C "GFXMMU_LUT577H,GFXMMU LUT entry 577 high" hexmask.long.tbyte 0x20C 0.--17. 1. "LO,Line offset" line.long 0x210 "GFXMMU_LUT578L,GFXMMU LUT entry 578 low" hexmask.long.byte 0x210 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x210 8.--15. 1. "FVB,First valid block" bitfld.long 0x210 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x214 "GFXMMU_LUT578H,GFXMMU LUT entry 578 high" hexmask.long.tbyte 0x214 0.--17. 1. "LO,Line offset" line.long 0x218 "GFXMMU_LUT579L,GFXMMU LUT entry 579 low" hexmask.long.byte 0x218 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x218 8.--15. 1. "FVB,First valid block" bitfld.long 0x218 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x21C "GFXMMU_LUT579H,GFXMMU LUT entry 579 high" hexmask.long.tbyte 0x21C 0.--17. 1. "LO,Line offset" line.long 0x220 "GFXMMU_LUT580L,GFXMMU LUT entry 580 low" hexmask.long.byte 0x220 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x220 8.--15. 1. "FVB,First valid block" bitfld.long 0x220 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x224 "GFXMMU_LUT580H,GFXMMU LUT entry 580 high" hexmask.long.tbyte 0x224 0.--17. 1. "LO,Line offset" line.long 0x228 "GFXMMU_LUT581L,GFXMMU LUT entry 581 low" hexmask.long.byte 0x228 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x228 8.--15. 1. "FVB,First valid block" bitfld.long 0x228 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x22C "GFXMMU_LUT581H,GFXMMU LUT entry 581 high" hexmask.long.tbyte 0x22C 0.--17. 1. "LO,Line offset" line.long 0x230 "GFXMMU_LUT582L,GFXMMU LUT entry 582 low" hexmask.long.byte 0x230 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x230 8.--15. 1. "FVB,First valid block" bitfld.long 0x230 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x234 "GFXMMU_LUT582H,GFXMMU LUT entry 582 high" hexmask.long.tbyte 0x234 0.--17. 1. "LO,Line offset" line.long 0x238 "GFXMMU_LUT583L,GFXMMU LUT entry 583 low" hexmask.long.byte 0x238 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x238 8.--15. 1. "FVB,First valid block" bitfld.long 0x238 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x23C "GFXMMU_LUT583H,GFXMMU LUT entry 583 high" hexmask.long.tbyte 0x23C 0.--17. 1. "LO,Line offset" line.long 0x240 "GFXMMU_LUT584L,GFXMMU LUT entry 584 low" hexmask.long.byte 0x240 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x240 8.--15. 1. "FVB,First valid block" bitfld.long 0x240 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x244 "GFXMMU_LUT584H,GFXMMU LUT entry 584 high" hexmask.long.tbyte 0x244 0.--17. 1. "LO,Line offset" line.long 0x248 "GFXMMU_LUT585L,GFXMMU LUT entry 585 low" hexmask.long.byte 0x248 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x248 8.--15. 1. "FVB,First valid block" bitfld.long 0x248 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24C "GFXMMU_LUT585H,GFXMMU LUT entry 585 high" hexmask.long.tbyte 0x24C 0.--17. 1. "LO,Line offset" line.long 0x250 "GFXMMU_LUT586L,GFXMMU LUT entry 586 low" hexmask.long.byte 0x250 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x250 8.--15. 1. "FVB,First valid block" bitfld.long 0x250 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x254 "GFXMMU_LUT586H,GFXMMU LUT entry 586 high" hexmask.long.tbyte 0x254 0.--17. 1. "LO,Line offset" line.long 0x258 "GFXMMU_LUT587L,GFXMMU LUT entry 587 low" hexmask.long.byte 0x258 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x258 8.--15. 1. "FVB,First valid block" bitfld.long 0x258 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x25C "GFXMMU_LUT587H,GFXMMU LUT entry 587 high" hexmask.long.tbyte 0x25C 0.--17. 1. "LO,Line offset" line.long 0x260 "GFXMMU_LUT588L,GFXMMU LUT entry 588 low" hexmask.long.byte 0x260 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x260 8.--15. 1. "FVB,First valid block" bitfld.long 0x260 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x264 "GFXMMU_LUT588H,GFXMMU LUT entry 588 high" hexmask.long.tbyte 0x264 0.--17. 1. "LO,Line offset" line.long 0x268 "GFXMMU_LUT589L,GFXMMU LUT entry 589 low" hexmask.long.byte 0x268 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x268 8.--15. 1. "FVB,First valid block" bitfld.long 0x268 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x26C "GFXMMU_LUT589H,GFXMMU LUT entry 589 high" hexmask.long.tbyte 0x26C 0.--17. 1. "LO,Line offset" line.long 0x270 "GFXMMU_LUT590L,GFXMMU LUT entry 590 low" hexmask.long.byte 0x270 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x270 8.--15. 1. "FVB,First valid block" bitfld.long 0x270 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x274 "GFXMMU_LUT590H,GFXMMU LUT entry 590 high" hexmask.long.tbyte 0x274 0.--17. 1. "LO,Line offset" line.long 0x278 "GFXMMU_LUT591L,GFXMMU LUT entry 591 low" hexmask.long.byte 0x278 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x278 8.--15. 1. "FVB,First valid block" bitfld.long 0x278 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x27C "GFXMMU_LUT591H,GFXMMU LUT entry 591 high" hexmask.long.tbyte 0x27C 0.--17. 1. "LO,Line offset" line.long 0x280 "GFXMMU_LUT592L,GFXMMU LUT entry 592 low" hexmask.long.byte 0x280 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x280 8.--15. 1. "FVB,First valid block" bitfld.long 0x280 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x284 "GFXMMU_LUT592H,GFXMMU LUT entry 592 high" hexmask.long.tbyte 0x284 0.--17. 1. "LO,Line offset" line.long 0x288 "GFXMMU_LUT593L,GFXMMU LUT entry 593 low" hexmask.long.byte 0x288 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x288 8.--15. 1. "FVB,First valid block" bitfld.long 0x288 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x28C "GFXMMU_LUT593H,GFXMMU LUT entry 593 high" hexmask.long.tbyte 0x28C 0.--17. 1. "LO,Line offset" line.long 0x290 "GFXMMU_LUT594L,GFXMMU LUT entry 594 low" hexmask.long.byte 0x290 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x290 8.--15. 1. "FVB,First valid block" bitfld.long 0x290 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x294 "GFXMMU_LUT594H,GFXMMU LUT entry 594 high" hexmask.long.tbyte 0x294 0.--17. 1. "LO,Line offset" line.long 0x298 "GFXMMU_LUT595L,GFXMMU LUT entry 595 low" hexmask.long.byte 0x298 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x298 8.--15. 1. "FVB,First valid block" bitfld.long 0x298 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x29C "GFXMMU_LUT595H,GFXMMU LUT entry 595 high" hexmask.long.tbyte 0x29C 0.--17. 1. "LO,Line offset" line.long 0x2A0 "GFXMMU_LUT596L,GFXMMU LUT entry 596 low" hexmask.long.byte 0x2A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2A4 "GFXMMU_LUT596H,GFXMMU LUT entry 596 high" hexmask.long.tbyte 0x2A4 0.--17. 1. "LO,Line offset" line.long 0x2A8 "GFXMMU_LUT597L,GFXMMU LUT entry 597 low" hexmask.long.byte 0x2A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2AC "GFXMMU_LUT597H,GFXMMU LUT entry 597 high" hexmask.long.tbyte 0x2AC 0.--17. 1. "LO,Line offset" line.long 0x2B0 "GFXMMU_LUT598L,GFXMMU LUT entry 598 low" hexmask.long.byte 0x2B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2B4 "GFXMMU_LUT598H,GFXMMU LUT entry 598 high" hexmask.long.tbyte 0x2B4 0.--17. 1. "LO,Line offset" line.long 0x2B8 "GFXMMU_LUT599L,GFXMMU LUT entry 599 low" hexmask.long.byte 0x2B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2BC "GFXMMU_LUT599H,GFXMMU LUT entry 599 high" hexmask.long.tbyte 0x2BC 0.--17. 1. "LO,Line offset" line.long 0x2C0 "GFXMMU_LUT600L,GFXMMU LUT entry 600 low" hexmask.long.byte 0x2C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C4 "GFXMMU_LUT600H,GFXMMU LUT entry 600 high" hexmask.long.tbyte 0x2C4 0.--17. 1. "LO,Line offset" line.long 0x2C8 "GFXMMU_LUT601L,GFXMMU LUT entry 601 low" hexmask.long.byte 0x2C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2CC "GFXMMU_LUT601H,GFXMMU LUT entry 601 high" hexmask.long.tbyte 0x2CC 0.--17. 1. "LO,Line offset" line.long 0x2D0 "GFXMMU_LUT602L,GFXMMU LUT entry 602 low" hexmask.long.byte 0x2D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2D4 "GFXMMU_LUT602H,GFXMMU LUT entry 602 high" hexmask.long.tbyte 0x2D4 0.--17. 1. "LO,Line offset" line.long 0x2D8 "GFXMMU_LUT603L,GFXMMU LUT entry 603 low" hexmask.long.byte 0x2D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2DC "GFXMMU_LUT603H,GFXMMU LUT entry 603 high" hexmask.long.tbyte 0x2DC 0.--17. 1. "LO,Line offset" line.long 0x2E0 "GFXMMU_LUT604L,GFXMMU LUT entry 604 low" hexmask.long.byte 0x2E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2E4 "GFXMMU_LUT604H,GFXMMU LUT entry 604 high" hexmask.long.tbyte 0x2E4 0.--17. 1. "LO,Line offset" line.long 0x2E8 "GFXMMU_LUT605L,GFXMMU LUT entry 605 low" hexmask.long.byte 0x2E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2EC "GFXMMU_LUT605H,GFXMMU LUT entry 605 high" hexmask.long.tbyte 0x2EC 0.--17. 1. "LO,Line offset" line.long 0x2F0 "GFXMMU_LUT606L,GFXMMU LUT entry 606 low" hexmask.long.byte 0x2F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2F4 "GFXMMU_LUT606H,GFXMMU LUT entry 606 high" hexmask.long.tbyte 0x2F4 0.--17. 1. "LO,Line offset" line.long 0x2F8 "GFXMMU_LUT607L,GFXMMU LUT entry 607 low" hexmask.long.byte 0x2F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2FC "GFXMMU_LUT607H,GFXMMU LUT entry 607 high" hexmask.long.tbyte 0x2FC 0.--17. 1. "LO,Line offset" line.long 0x300 "GFXMMU_LUT608L,GFXMMU LUT entry 608 low" hexmask.long.byte 0x300 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x300 8.--15. 1. "FVB,First valid block" bitfld.long 0x300 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x304 "GFXMMU_LUT608H,GFXMMU LUT entry 608 high" hexmask.long.tbyte 0x304 0.--17. 1. "LO,Line offset" line.long 0x308 "GFXMMU_LUT609L,GFXMMU LUT entry 609 low" hexmask.long.byte 0x308 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x308 8.--15. 1. "FVB,First valid block" bitfld.long 0x308 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x30C "GFXMMU_LUT609H,GFXMMU LUT entry 609 high" hexmask.long.tbyte 0x30C 0.--17. 1. "LO,Line offset" line.long 0x310 "GFXMMU_LUT610L,GFXMMU LUT entry 610 low" hexmask.long.byte 0x310 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x310 8.--15. 1. "FVB,First valid block" bitfld.long 0x310 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x314 "GFXMMU_LUT610H,GFXMMU LUT entry 610 high" hexmask.long.tbyte 0x314 0.--17. 1. "LO,Line offset" line.long 0x318 "GFXMMU_LUT611L,GFXMMU LUT entry 611 low" hexmask.long.byte 0x318 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x318 8.--15. 1. "FVB,First valid block" bitfld.long 0x318 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x31C "GFXMMU_LUT611H,GFXMMU LUT entry 611 high" hexmask.long.tbyte 0x31C 0.--17. 1. "LO,Line offset" line.long 0x320 "GFXMMU_LUT612L,GFXMMU LUT entry 612 low" hexmask.long.byte 0x320 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x320 8.--15. 1. "FVB,First valid block" bitfld.long 0x320 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x324 "GFXMMU_LUT612H,GFXMMU LUT entry 612 high" hexmask.long.tbyte 0x324 0.--17. 1. "LO,Line offset" line.long 0x328 "GFXMMU_LUT613L,GFXMMU LUT entry 613 low" hexmask.long.byte 0x328 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x328 8.--15. 1. "FVB,First valid block" bitfld.long 0x328 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x32C "GFXMMU_LUT613H,GFXMMU LUT entry 613 high" hexmask.long.tbyte 0x32C 0.--17. 1. "LO,Line offset" line.long 0x330 "GFXMMU_LUT614L,GFXMMU LUT entry 614 low" hexmask.long.byte 0x330 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x330 8.--15. 1. "FVB,First valid block" bitfld.long 0x330 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x334 "GFXMMU_LUT614H,GFXMMU LUT entry 614 high" hexmask.long.tbyte 0x334 0.--17. 1. "LO,Line offset" line.long 0x338 "GFXMMU_LUT615L,GFXMMU LUT entry 615 low" hexmask.long.byte 0x338 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x338 8.--15. 1. "FVB,First valid block" bitfld.long 0x338 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x33C "GFXMMU_LUT615H,GFXMMU LUT entry 615 high" hexmask.long.tbyte 0x33C 0.--17. 1. "LO,Line offset" line.long 0x340 "GFXMMU_LUT616L,GFXMMU LUT entry 616 low" hexmask.long.byte 0x340 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x340 8.--15. 1. "FVB,First valid block" bitfld.long 0x340 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x344 "GFXMMU_LUT616H,GFXMMU LUT entry 616 high" hexmask.long.tbyte 0x344 0.--17. 1. "LO,Line offset" line.long 0x348 "GFXMMU_LUT617L,GFXMMU LUT entry 617 low" hexmask.long.byte 0x348 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x348 8.--15. 1. "FVB,First valid block" bitfld.long 0x348 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34C "GFXMMU_LUT617H,GFXMMU LUT entry 617 high" hexmask.long.tbyte 0x34C 0.--17. 1. "LO,Line offset" line.long 0x350 "GFXMMU_LUT618L,GFXMMU LUT entry 618 low" hexmask.long.byte 0x350 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x350 8.--15. 1. "FVB,First valid block" bitfld.long 0x350 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x354 "GFXMMU_LUT618H,GFXMMU LUT entry 618 high" hexmask.long.tbyte 0x354 0.--17. 1. "LO,Line offset" line.long 0x358 "GFXMMU_LUT619L,GFXMMU LUT entry 619 low" hexmask.long.byte 0x358 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x358 8.--15. 1. "FVB,First valid block" bitfld.long 0x358 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x35C "GFXMMU_LUT619H,GFXMMU LUT entry 619 high" hexmask.long.tbyte 0x35C 0.--17. 1. "LO,Line offset" line.long 0x360 "GFXMMU_LUT620L,GFXMMU LUT entry 620 low" hexmask.long.byte 0x360 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x360 8.--15. 1. "FVB,First valid block" bitfld.long 0x360 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x364 "GFXMMU_LUT620H,GFXMMU LUT entry 620 high" hexmask.long.tbyte 0x364 0.--17. 1. "LO,Line offset" line.long 0x368 "GFXMMU_LUT621L,GFXMMU LUT entry 621 low" hexmask.long.byte 0x368 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x368 8.--15. 1. "FVB,First valid block" bitfld.long 0x368 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x36C "GFXMMU_LUT621H,GFXMMU LUT entry 621 high" hexmask.long.tbyte 0x36C 0.--17. 1. "LO,Line offset" line.long 0x370 "GFXMMU_LUT622L,GFXMMU LUT entry 622 low" hexmask.long.byte 0x370 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x370 8.--15. 1. "FVB,First valid block" bitfld.long 0x370 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x374 "GFXMMU_LUT622H,GFXMMU LUT entry 622 high" hexmask.long.tbyte 0x374 0.--17. 1. "LO,Line offset" line.long 0x378 "GFXMMU_LUT623L,GFXMMU LUT entry 623 low" hexmask.long.byte 0x378 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x378 8.--15. 1. "FVB,First valid block" bitfld.long 0x378 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x37C "GFXMMU_LUT623H,GFXMMU LUT entry 623 high" hexmask.long.tbyte 0x37C 0.--17. 1. "LO,Line offset" line.long 0x380 "GFXMMU_LUT624L,GFXMMU LUT entry 624 low" hexmask.long.byte 0x380 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x380 8.--15. 1. "FVB,First valid block" bitfld.long 0x380 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x384 "GFXMMU_LUT624H,GFXMMU LUT entry 624 high" hexmask.long.tbyte 0x384 0.--17. 1. "LO,Line offset" line.long 0x388 "GFXMMU_LUT625L,GFXMMU LUT entry 625 low" hexmask.long.byte 0x388 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x388 8.--15. 1. "FVB,First valid block" bitfld.long 0x388 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x38C "GFXMMU_LUT625H,GFXMMU LUT entry 625 high" hexmask.long.tbyte 0x38C 0.--17. 1. "LO,Line offset" line.long 0x390 "GFXMMU_LUT626L,GFXMMU LUT entry 626 low" hexmask.long.byte 0x390 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x390 8.--15. 1. "FVB,First valid block" bitfld.long 0x390 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x394 "GFXMMU_LUT626H,GFXMMU LUT entry 626 high" hexmask.long.tbyte 0x394 0.--17. 1. "LO,Line offset" line.long 0x398 "GFXMMU_LUT627L,GFXMMU LUT entry 627 low" hexmask.long.byte 0x398 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x398 8.--15. 1. "FVB,First valid block" bitfld.long 0x398 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x39C "GFXMMU_LUT627H,GFXMMU LUT entry 627 high" hexmask.long.tbyte 0x39C 0.--17. 1. "LO,Line offset" line.long 0x3A0 "GFXMMU_LUT628L,GFXMMU LUT entry 628 low" hexmask.long.byte 0x3A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3A4 "GFXMMU_LUT628H,GFXMMU LUT entry 628 high" hexmask.long.tbyte 0x3A4 0.--17. 1. "LO,Line offset" line.long 0x3A8 "GFXMMU_LUT629L,GFXMMU LUT entry 629 low" hexmask.long.byte 0x3A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3AC "GFXMMU_LUT629H,GFXMMU LUT entry 629 high" hexmask.long.tbyte 0x3AC 0.--17. 1. "LO,Line offset" line.long 0x3B0 "GFXMMU_LUT630L,GFXMMU LUT entry 630 low" hexmask.long.byte 0x3B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3B4 "GFXMMU_LUT630H,GFXMMU LUT entry 630 high" hexmask.long.tbyte 0x3B4 0.--17. 1. "LO,Line offset" line.long 0x3B8 "GFXMMU_LUT631L,GFXMMU LUT entry 631 low" hexmask.long.byte 0x3B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3BC "GFXMMU_LUT631H,GFXMMU LUT entry 631 high" hexmask.long.tbyte 0x3BC 0.--17. 1. "LO,Line offset" line.long 0x3C0 "GFXMMU_LUT632L,GFXMMU LUT entry 632 low" hexmask.long.byte 0x3C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C4 "GFXMMU_LUT632H,GFXMMU LUT entry 632 high" hexmask.long.tbyte 0x3C4 0.--17. 1. "LO,Line offset" line.long 0x3C8 "GFXMMU_LUT633L,GFXMMU LUT entry 633 low" hexmask.long.byte 0x3C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3CC "GFXMMU_LUT633H,GFXMMU LUT entry 633 high" hexmask.long.tbyte 0x3CC 0.--17. 1. "LO,Line offset" line.long 0x3D0 "GFXMMU_LUT634L,GFXMMU LUT entry 634 low" hexmask.long.byte 0x3D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3D4 "GFXMMU_LUT634H,GFXMMU LUT entry 634 high" hexmask.long.tbyte 0x3D4 0.--17. 1. "LO,Line offset" line.long 0x3D8 "GFXMMU_LUT635L,GFXMMU LUT entry 635 low" hexmask.long.byte 0x3D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3DC "GFXMMU_LUT635H,GFXMMU LUT entry 635 high" hexmask.long.tbyte 0x3DC 0.--17. 1. "LO,Line offset" line.long 0x3E0 "GFXMMU_LUT636L,GFXMMU LUT entry 636 low" hexmask.long.byte 0x3E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3E4 "GFXMMU_LUT636H,GFXMMU LUT entry 636 high" hexmask.long.tbyte 0x3E4 0.--17. 1. "LO,Line offset" line.long 0x3E8 "GFXMMU_LUT637L,GFXMMU LUT entry 637 low" hexmask.long.byte 0x3E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3EC "GFXMMU_LUT637H,GFXMMU LUT entry 637 high" hexmask.long.tbyte 0x3EC 0.--17. 1. "LO,Line offset" line.long 0x3F0 "GFXMMU_LUT638L,GFXMMU LUT entry 638 low" hexmask.long.byte 0x3F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3F4 "GFXMMU_LUT638H,GFXMMU LUT entry 638 high" hexmask.long.tbyte 0x3F4 0.--17. 1. "LO,Line offset" line.long 0x3F8 "GFXMMU_LUT639L,GFXMMU LUT entry 639 low" hexmask.long.byte 0x3F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3FC "GFXMMU_LUT639H,GFXMMU LUT entry 639 high" hexmask.long.tbyte 0x3FC 0.--17. 1. "LO,Line offset" line.long 0x400 "GFXMMU_LUT640L,GFXMMU LUT entry 640 low" hexmask.long.byte 0x400 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x400 8.--15. 1. "FVB,First valid block" bitfld.long 0x400 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x404 "GFXMMU_LUT640H,GFXMMU LUT entry 640 high" hexmask.long.tbyte 0x404 0.--17. 1. "LO,Line offset" line.long 0x408 "GFXMMU_LUT641L,GFXMMU LUT entry 641 low" hexmask.long.byte 0x408 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x408 8.--15. 1. "FVB,First valid block" bitfld.long 0x408 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x40C "GFXMMU_LUT641H,GFXMMU LUT entry 641 high" hexmask.long.tbyte 0x40C 0.--17. 1. "LO,Line offset" line.long 0x410 "GFXMMU_LUT642L,GFXMMU LUT entry 642 low" hexmask.long.byte 0x410 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x410 8.--15. 1. "FVB,First valid block" bitfld.long 0x410 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x414 "GFXMMU_LUT642H,GFXMMU LUT entry 642 high" hexmask.long.tbyte 0x414 0.--17. 1. "LO,Line offset" line.long 0x418 "GFXMMU_LUT643L,GFXMMU LUT entry 643 low" hexmask.long.byte 0x418 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x418 8.--15. 1. "FVB,First valid block" bitfld.long 0x418 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x41C "GFXMMU_LUT643H,GFXMMU LUT entry 643 high" hexmask.long.tbyte 0x41C 0.--17. 1. "LO,Line offset" line.long 0x420 "GFXMMU_LUT644L,GFXMMU LUT entry 644 low" hexmask.long.byte 0x420 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x420 8.--15. 1. "FVB,First valid block" bitfld.long 0x420 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x424 "GFXMMU_LUT644H,GFXMMU LUT entry 644 high" hexmask.long.tbyte 0x424 0.--17. 1. "LO,Line offset" line.long 0x428 "GFXMMU_LUT645L,GFXMMU LUT entry 645 low" hexmask.long.byte 0x428 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x428 8.--15. 1. "FVB,First valid block" bitfld.long 0x428 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x42C "GFXMMU_LUT645H,GFXMMU LUT entry 645 high" hexmask.long.tbyte 0x42C 0.--17. 1. "LO,Line offset" line.long 0x430 "GFXMMU_LUT646L,GFXMMU LUT entry 646 low" hexmask.long.byte 0x430 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x430 8.--15. 1. "FVB,First valid block" bitfld.long 0x430 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x434 "GFXMMU_LUT646H,GFXMMU LUT entry 646 high" hexmask.long.tbyte 0x434 0.--17. 1. "LO,Line offset" line.long 0x438 "GFXMMU_LUT647L,GFXMMU LUT entry 647 low" hexmask.long.byte 0x438 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x438 8.--15. 1. "FVB,First valid block" bitfld.long 0x438 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x43C "GFXMMU_LUT647H,GFXMMU LUT entry 647 high" hexmask.long.tbyte 0x43C 0.--17. 1. "LO,Line offset" line.long 0x440 "GFXMMU_LUT648L,GFXMMU LUT entry 648 low" hexmask.long.byte 0x440 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x440 8.--15. 1. "FVB,First valid block" bitfld.long 0x440 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x444 "GFXMMU_LUT648H,GFXMMU LUT entry 648 high" hexmask.long.tbyte 0x444 0.--17. 1. "LO,Line offset" line.long 0x448 "GFXMMU_LUT649L,GFXMMU LUT entry 649 low" hexmask.long.byte 0x448 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x448 8.--15. 1. "FVB,First valid block" bitfld.long 0x448 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44C "GFXMMU_LUT649H,GFXMMU LUT entry 649 high" hexmask.long.tbyte 0x44C 0.--17. 1. "LO,Line offset" line.long 0x450 "GFXMMU_LUT650L,GFXMMU LUT entry 650 low" hexmask.long.byte 0x450 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x450 8.--15. 1. "FVB,First valid block" bitfld.long 0x450 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x454 "GFXMMU_LUT650H,GFXMMU LUT entry 650 high" hexmask.long.tbyte 0x454 0.--17. 1. "LO,Line offset" line.long 0x458 "GFXMMU_LUT651L,GFXMMU LUT entry 651 low" hexmask.long.byte 0x458 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x458 8.--15. 1. "FVB,First valid block" bitfld.long 0x458 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x45C "GFXMMU_LUT651H,GFXMMU LUT entry 651 high" hexmask.long.tbyte 0x45C 0.--17. 1. "LO,Line offset" line.long 0x460 "GFXMMU_LUT652L,GFXMMU LUT entry 652 low" hexmask.long.byte 0x460 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x460 8.--15. 1. "FVB,First valid block" bitfld.long 0x460 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x464 "GFXMMU_LUT652H,GFXMMU LUT entry 652 high" hexmask.long.tbyte 0x464 0.--17. 1. "LO,Line offset" line.long 0x468 "GFXMMU_LUT653L,GFXMMU LUT entry 653 low" hexmask.long.byte 0x468 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x468 8.--15. 1. "FVB,First valid block" bitfld.long 0x468 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x46C "GFXMMU_LUT653H,GFXMMU LUT entry 653 high" hexmask.long.tbyte 0x46C 0.--17. 1. "LO,Line offset" line.long 0x470 "GFXMMU_LUT654L,GFXMMU LUT entry 654 low" hexmask.long.byte 0x470 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x470 8.--15. 1. "FVB,First valid block" bitfld.long 0x470 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x474 "GFXMMU_LUT654H,GFXMMU LUT entry 654 high" hexmask.long.tbyte 0x474 0.--17. 1. "LO,Line offset" line.long 0x478 "GFXMMU_LUT655L,GFXMMU LUT entry 655 low" hexmask.long.byte 0x478 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x478 8.--15. 1. "FVB,First valid block" bitfld.long 0x478 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x47C "GFXMMU_LUT655H,GFXMMU LUT entry 655 high" hexmask.long.tbyte 0x47C 0.--17. 1. "LO,Line offset" line.long 0x480 "GFXMMU_LUT656L,GFXMMU LUT entry 656 low" hexmask.long.byte 0x480 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x480 8.--15. 1. "FVB,First valid block" bitfld.long 0x480 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x484 "GFXMMU_LUT656H,GFXMMU LUT entry 656 high" hexmask.long.tbyte 0x484 0.--17. 1. "LO,Line offset" line.long 0x488 "GFXMMU_LUT657L,GFXMMU LUT entry 657 low" hexmask.long.byte 0x488 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x488 8.--15. 1. "FVB,First valid block" bitfld.long 0x488 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x48C "GFXMMU_LUT657H,GFXMMU LUT entry 657 high" hexmask.long.tbyte 0x48C 0.--17. 1. "LO,Line offset" line.long 0x490 "GFXMMU_LUT658L,GFXMMU LUT entry 658 low" hexmask.long.byte 0x490 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x490 8.--15. 1. "FVB,First valid block" bitfld.long 0x490 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x494 "GFXMMU_LUT658H,GFXMMU LUT entry 658 high" hexmask.long.tbyte 0x494 0.--17. 1. "LO,Line offset" line.long 0x498 "GFXMMU_LUT659L,GFXMMU LUT entry 659 low" hexmask.long.byte 0x498 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x498 8.--15. 1. "FVB,First valid block" bitfld.long 0x498 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x49C "GFXMMU_LUT659H,GFXMMU LUT entry 659 high" hexmask.long.tbyte 0x49C 0.--17. 1. "LO,Line offset" line.long 0x4A0 "GFXMMU_LUT660L,GFXMMU LUT entry 660 low" hexmask.long.byte 0x4A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4A4 "GFXMMU_LUT660H,GFXMMU LUT entry 660 high" hexmask.long.tbyte 0x4A4 0.--17. 1. "LO,Line offset" line.long 0x4A8 "GFXMMU_LUT661L,GFXMMU LUT entry 661 low" hexmask.long.byte 0x4A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4AC "GFXMMU_LUT661H,GFXMMU LUT entry 661 high" hexmask.long.tbyte 0x4AC 0.--17. 1. "LO,Line offset" line.long 0x4B0 "GFXMMU_LUT662L,GFXMMU LUT entry 662 low" hexmask.long.byte 0x4B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4B4 "GFXMMU_LUT662H,GFXMMU LUT entry 662 high" hexmask.long.tbyte 0x4B4 0.--17. 1. "LO,Line offset" line.long 0x4B8 "GFXMMU_LUT663L,GFXMMU LUT entry 663 low" hexmask.long.byte 0x4B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4BC "GFXMMU_LUT663H,GFXMMU LUT entry 663 high" hexmask.long.tbyte 0x4BC 0.--17. 1. "LO,Line offset" line.long 0x4C0 "GFXMMU_LUT664L,GFXMMU LUT entry 664 low" hexmask.long.byte 0x4C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C4 "GFXMMU_LUT664H,GFXMMU LUT entry 664 high" hexmask.long.tbyte 0x4C4 0.--17. 1. "LO,Line offset" line.long 0x4C8 "GFXMMU_LUT665L,GFXMMU LUT entry 665 low" hexmask.long.byte 0x4C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4CC "GFXMMU_LUT665H,GFXMMU LUT entry 665 high" hexmask.long.tbyte 0x4CC 0.--17. 1. "LO,Line offset" line.long 0x4D0 "GFXMMU_LUT666L,GFXMMU LUT entry 666 low" hexmask.long.byte 0x4D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4D4 "GFXMMU_LUT666H,GFXMMU LUT entry 666 high" hexmask.long.tbyte 0x4D4 0.--17. 1. "LO,Line offset" line.long 0x4D8 "GFXMMU_LUT667L,GFXMMU LUT entry 667 low" hexmask.long.byte 0x4D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4DC "GFXMMU_LUT667H,GFXMMU LUT entry 667 high" hexmask.long.tbyte 0x4DC 0.--17. 1. "LO,Line offset" line.long 0x4E0 "GFXMMU_LUT668L,GFXMMU LUT entry 668 low" hexmask.long.byte 0x4E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4E4 "GFXMMU_LUT668H,GFXMMU LUT entry 668 high" hexmask.long.tbyte 0x4E4 0.--17. 1. "LO,Line offset" line.long 0x4E8 "GFXMMU_LUT669L,GFXMMU LUT entry 669 low" hexmask.long.byte 0x4E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4EC "GFXMMU_LUT669H,GFXMMU LUT entry 669 high" hexmask.long.tbyte 0x4EC 0.--17. 1. "LO,Line offset" line.long 0x4F0 "GFXMMU_LUT670L,GFXMMU LUT entry 670 low" hexmask.long.byte 0x4F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4F4 "GFXMMU_LUT670H,GFXMMU LUT entry 670 high" hexmask.long.tbyte 0x4F4 0.--17. 1. "LO,Line offset" line.long 0x4F8 "GFXMMU_LUT671L,GFXMMU LUT entry 671 low" hexmask.long.byte 0x4F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4FC "GFXMMU_LUT671H,GFXMMU LUT entry 671 high" hexmask.long.tbyte 0x4FC 0.--17. 1. "LO,Line offset" line.long 0x500 "GFXMMU_LUT672L,GFXMMU LUT entry 672 low" hexmask.long.byte 0x500 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x500 8.--15. 1. "FVB,First valid block" bitfld.long 0x500 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x504 "GFXMMU_LUT672H,GFXMMU LUT entry 672 high" hexmask.long.tbyte 0x504 0.--17. 1. "LO,Line offset" line.long 0x508 "GFXMMU_LUT673L,GFXMMU LUT entry 673 low" hexmask.long.byte 0x508 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x508 8.--15. 1. "FVB,First valid block" bitfld.long 0x508 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x50C "GFXMMU_LUT673H,GFXMMU LUT entry 673 high" hexmask.long.tbyte 0x50C 0.--17. 1. "LO,Line offset" line.long 0x510 "GFXMMU_LUT674L,GFXMMU LUT entry 674 low" hexmask.long.byte 0x510 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x510 8.--15. 1. "FVB,First valid block" bitfld.long 0x510 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x514 "GFXMMU_LUT674H,GFXMMU LUT entry 674 high" hexmask.long.tbyte 0x514 0.--17. 1. "LO,Line offset" line.long 0x518 "GFXMMU_LUT675L,GFXMMU LUT entry 675 low" hexmask.long.byte 0x518 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x518 8.--15. 1. "FVB,First valid block" bitfld.long 0x518 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x51C "GFXMMU_LUT675H,GFXMMU LUT entry 675 high" hexmask.long.tbyte 0x51C 0.--17. 1. "LO,Line offset" line.long 0x520 "GFXMMU_LUT676L,GFXMMU LUT entry 676 low" hexmask.long.byte 0x520 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x520 8.--15. 1. "FVB,First valid block" bitfld.long 0x520 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x524 "GFXMMU_LUT676H,GFXMMU LUT entry 676 high" hexmask.long.tbyte 0x524 0.--17. 1. "LO,Line offset" line.long 0x528 "GFXMMU_LUT677L,GFXMMU LUT entry 677 low" hexmask.long.byte 0x528 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x528 8.--15. 1. "FVB,First valid block" bitfld.long 0x528 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x52C "GFXMMU_LUT677H,GFXMMU LUT entry 677 high" hexmask.long.tbyte 0x52C 0.--17. 1. "LO,Line offset" line.long 0x530 "GFXMMU_LUT678L,GFXMMU LUT entry 678 low" hexmask.long.byte 0x530 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x530 8.--15. 1. "FVB,First valid block" bitfld.long 0x530 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x534 "GFXMMU_LUT678H,GFXMMU LUT entry 678 high" hexmask.long.tbyte 0x534 0.--17. 1. "LO,Line offset" line.long 0x538 "GFXMMU_LUT679L,GFXMMU LUT entry 679 low" hexmask.long.byte 0x538 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x538 8.--15. 1. "FVB,First valid block" bitfld.long 0x538 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x53C "GFXMMU_LUT679H,GFXMMU LUT entry 679 high" hexmask.long.tbyte 0x53C 0.--17. 1. "LO,Line offset" line.long 0x540 "GFXMMU_LUT680L,GFXMMU LUT entry 680 low" hexmask.long.byte 0x540 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x540 8.--15. 1. "FVB,First valid block" bitfld.long 0x540 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x544 "GFXMMU_LUT680H,GFXMMU LUT entry 680 high" hexmask.long.tbyte 0x544 0.--17. 1. "LO,Line offset" line.long 0x548 "GFXMMU_LUT681L,GFXMMU LUT entry 681 low" hexmask.long.byte 0x548 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x548 8.--15. 1. "FVB,First valid block" bitfld.long 0x548 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54C "GFXMMU_LUT681H,GFXMMU LUT entry 681 high" hexmask.long.tbyte 0x54C 0.--17. 1. "LO,Line offset" line.long 0x550 "GFXMMU_LUT682L,GFXMMU LUT entry 682 low" hexmask.long.byte 0x550 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x550 8.--15. 1. "FVB,First valid block" bitfld.long 0x550 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x554 "GFXMMU_LUT682H,GFXMMU LUT entry 682 high" hexmask.long.tbyte 0x554 0.--17. 1. "LO,Line offset" line.long 0x558 "GFXMMU_LUT683L,GFXMMU LUT entry 683 low" hexmask.long.byte 0x558 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x558 8.--15. 1. "FVB,First valid block" bitfld.long 0x558 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x55C "GFXMMU_LUT683H,GFXMMU LUT entry 683 high" hexmask.long.tbyte 0x55C 0.--17. 1. "LO,Line offset" line.long 0x560 "GFXMMU_LUT684L,GFXMMU LUT entry 684 low" hexmask.long.byte 0x560 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x560 8.--15. 1. "FVB,First valid block" bitfld.long 0x560 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x564 "GFXMMU_LUT684H,GFXMMU LUT entry 684 high" hexmask.long.tbyte 0x564 0.--17. 1. "LO,Line offset" line.long 0x568 "GFXMMU_LUT685L,GFXMMU LUT entry 685 low" hexmask.long.byte 0x568 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x568 8.--15. 1. "FVB,First valid block" bitfld.long 0x568 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x56C "GFXMMU_LUT685H,GFXMMU LUT entry 685 high" hexmask.long.tbyte 0x56C 0.--17. 1. "LO,Line offset" line.long 0x570 "GFXMMU_LUT686L,GFXMMU LUT entry 686 low" hexmask.long.byte 0x570 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x570 8.--15. 1. "FVB,First valid block" bitfld.long 0x570 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x574 "GFXMMU_LUT686H,GFXMMU LUT entry 686 high" hexmask.long.tbyte 0x574 0.--17. 1. "LO,Line offset" line.long 0x578 "GFXMMU_LUT687L,GFXMMU LUT entry 687 low" hexmask.long.byte 0x578 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x578 8.--15. 1. "FVB,First valid block" bitfld.long 0x578 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x57C "GFXMMU_LUT687H,GFXMMU LUT entry 687 high" hexmask.long.tbyte 0x57C 0.--17. 1. "LO,Line offset" line.long 0x580 "GFXMMU_LUT688L,GFXMMU LUT entry 688 low" hexmask.long.byte 0x580 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x580 8.--15. 1. "FVB,First valid block" bitfld.long 0x580 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x584 "GFXMMU_LUT688H,GFXMMU LUT entry 688 high" hexmask.long.tbyte 0x584 0.--17. 1. "LO,Line offset" line.long 0x588 "GFXMMU_LUT689L,GFXMMU LUT entry 689 low" hexmask.long.byte 0x588 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x588 8.--15. 1. "FVB,First valid block" bitfld.long 0x588 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x58C "GFXMMU_LUT689H,GFXMMU LUT entry 689 high" hexmask.long.tbyte 0x58C 0.--17. 1. "LO,Line offset" line.long 0x590 "GFXMMU_LUT690L,GFXMMU LUT entry 690 low" hexmask.long.byte 0x590 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x590 8.--15. 1. "FVB,First valid block" bitfld.long 0x590 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x594 "GFXMMU_LUT690H,GFXMMU LUT entry 690 high" hexmask.long.tbyte 0x594 0.--17. 1. "LO,Line offset" line.long 0x598 "GFXMMU_LUT691L,GFXMMU LUT entry 691 low" hexmask.long.byte 0x598 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x598 8.--15. 1. "FVB,First valid block" bitfld.long 0x598 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x59C "GFXMMU_LUT691H,GFXMMU LUT entry 691 high" hexmask.long.tbyte 0x59C 0.--17. 1. "LO,Line offset" line.long 0x5A0 "GFXMMU_LUT692L,GFXMMU LUT entry 692 low" hexmask.long.byte 0x5A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5A4 "GFXMMU_LUT692H,GFXMMU LUT entry 692 high" hexmask.long.tbyte 0x5A4 0.--17. 1. "LO,Line offset" line.long 0x5A8 "GFXMMU_LUT693L,GFXMMU LUT entry 693 low" hexmask.long.byte 0x5A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5AC "GFXMMU_LUT693H,GFXMMU LUT entry 693 high" hexmask.long.tbyte 0x5AC 0.--17. 1. "LO,Line offset" line.long 0x5B0 "GFXMMU_LUT694L,GFXMMU LUT entry 694 low" hexmask.long.byte 0x5B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5B4 "GFXMMU_LUT694H,GFXMMU LUT entry 694 high" hexmask.long.tbyte 0x5B4 0.--17. 1. "LO,Line offset" line.long 0x5B8 "GFXMMU_LUT695L,GFXMMU LUT entry 695 low" hexmask.long.byte 0x5B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5BC "GFXMMU_LUT695H,GFXMMU LUT entry 695 high" hexmask.long.tbyte 0x5BC 0.--17. 1. "LO,Line offset" line.long 0x5C0 "GFXMMU_LUT696L,GFXMMU LUT entry 696 low" hexmask.long.byte 0x5C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C4 "GFXMMU_LUT696H,GFXMMU LUT entry 696 high" hexmask.long.tbyte 0x5C4 0.--17. 1. "LO,Line offset" line.long 0x5C8 "GFXMMU_LUT697L,GFXMMU LUT entry 697 low" hexmask.long.byte 0x5C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5CC "GFXMMU_LUT697H,GFXMMU LUT entry 697 high" hexmask.long.tbyte 0x5CC 0.--17. 1. "LO,Line offset" line.long 0x5D0 "GFXMMU_LUT698L,GFXMMU LUT entry 698 low" hexmask.long.byte 0x5D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5D4 "GFXMMU_LUT698H,GFXMMU LUT entry 698 high" hexmask.long.tbyte 0x5D4 0.--17. 1. "LO,Line offset" line.long 0x5D8 "GFXMMU_LUT699L,GFXMMU LUT entry 699 low" hexmask.long.byte 0x5D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5DC "GFXMMU_LUT699H,GFXMMU LUT entry 699 high" hexmask.long.tbyte 0x5DC 0.--17. 1. "LO,Line offset" line.long 0x5E0 "GFXMMU_LUT700L,GFXMMU LUT entry 700 low" hexmask.long.byte 0x5E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5E4 "GFXMMU_LUT700H,GFXMMU LUT entry 700 high" hexmask.long.tbyte 0x5E4 0.--17. 1. "LO,Line offset" line.long 0x5E8 "GFXMMU_LUT701L,GFXMMU LUT entry 701 low" hexmask.long.byte 0x5E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5EC "GFXMMU_LUT701H,GFXMMU LUT entry 701 high" hexmask.long.tbyte 0x5EC 0.--17. 1. "LO,Line offset" line.long 0x5F0 "GFXMMU_LUT702L,GFXMMU LUT entry 702 low" hexmask.long.byte 0x5F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5F4 "GFXMMU_LUT702H,GFXMMU LUT entry 702 high" hexmask.long.tbyte 0x5F4 0.--17. 1. "LO,Line offset" line.long 0x5F8 "GFXMMU_LUT703L,GFXMMU LUT entry 703 low" hexmask.long.byte 0x5F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5FC "GFXMMU_LUT703H,GFXMMU LUT entry 703 high" hexmask.long.tbyte 0x5FC 0.--17. 1. "LO,Line offset" line.long 0x600 "GFXMMU_LUT704L,GFXMMU LUT entry 704 low" hexmask.long.byte 0x600 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x600 8.--15. 1. "FVB,First valid block" bitfld.long 0x600 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x604 "GFXMMU_LUT704H,GFXMMU LUT entry 704 high" hexmask.long.tbyte 0x604 0.--17. 1. "LO,Line offset" line.long 0x608 "GFXMMU_LUT705L,GFXMMU LUT entry 705 low" hexmask.long.byte 0x608 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x608 8.--15. 1. "FVB,First valid block" bitfld.long 0x608 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x60C "GFXMMU_LUT705H,GFXMMU LUT entry 705 high" hexmask.long.tbyte 0x60C 0.--17. 1. "LO,Line offset" line.long 0x610 "GFXMMU_LUT706L,GFXMMU LUT entry 706 low" hexmask.long.byte 0x610 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x610 8.--15. 1. "FVB,First valid block" bitfld.long 0x610 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x614 "GFXMMU_LUT706H,GFXMMU LUT entry 706 high" hexmask.long.tbyte 0x614 0.--17. 1. "LO,Line offset" line.long 0x618 "GFXMMU_LUT707L,GFXMMU LUT entry 707 low" hexmask.long.byte 0x618 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x618 8.--15. 1. "FVB,First valid block" bitfld.long 0x618 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x61C "GFXMMU_LUT707H,GFXMMU LUT entry 707 high" hexmask.long.tbyte 0x61C 0.--17. 1. "LO,Line offset" line.long 0x620 "GFXMMU_LUT708L,GFXMMU LUT entry 708 low" hexmask.long.byte 0x620 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x620 8.--15. 1. "FVB,First valid block" bitfld.long 0x620 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x624 "GFXMMU_LUT708H,GFXMMU LUT entry 708 high" hexmask.long.tbyte 0x624 0.--17. 1. "LO,Line offset" line.long 0x628 "GFXMMU_LUT709L,GFXMMU LUT entry 709 low" hexmask.long.byte 0x628 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x628 8.--15. 1. "FVB,First valid block" bitfld.long 0x628 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x62C "GFXMMU_LUT709H,GFXMMU LUT entry 709 high" hexmask.long.tbyte 0x62C 0.--17. 1. "LO,Line offset" line.long 0x630 "GFXMMU_LUT710L,GFXMMU LUT entry 710 low" hexmask.long.byte 0x630 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x630 8.--15. 1. "FVB,First valid block" bitfld.long 0x630 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x634 "GFXMMU_LUT710H,GFXMMU LUT entry 710 high" hexmask.long.tbyte 0x634 0.--17. 1. "LO,Line offset" line.long 0x638 "GFXMMU_LUT711L,GFXMMU LUT entry 711 low" hexmask.long.byte 0x638 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x638 8.--15. 1. "FVB,First valid block" bitfld.long 0x638 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x63C "GFXMMU_LUT711H,GFXMMU LUT entry 711 high" hexmask.long.tbyte 0x63C 0.--17. 1. "LO,Line offset" line.long 0x640 "GFXMMU_LUT712L,GFXMMU LUT entry 712 low" hexmask.long.byte 0x640 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x640 8.--15. 1. "FVB,First valid block" bitfld.long 0x640 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x644 "GFXMMU_LUT712H,GFXMMU LUT entry 712 high" hexmask.long.tbyte 0x644 0.--17. 1. "LO,Line offset" line.long 0x648 "GFXMMU_LUT713L,GFXMMU LUT entry 713 low" hexmask.long.byte 0x648 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x648 8.--15. 1. "FVB,First valid block" bitfld.long 0x648 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64C "GFXMMU_LUT713H,GFXMMU LUT entry 713 high" hexmask.long.tbyte 0x64C 0.--17. 1. "LO,Line offset" line.long 0x650 "GFXMMU_LUT714L,GFXMMU LUT entry 714 low" hexmask.long.byte 0x650 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x650 8.--15. 1. "FVB,First valid block" bitfld.long 0x650 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x654 "GFXMMU_LUT714H,GFXMMU LUT entry 714 high" hexmask.long.tbyte 0x654 0.--17. 1. "LO,Line offset" line.long 0x658 "GFXMMU_LUT715L,GFXMMU LUT entry 715 low" hexmask.long.byte 0x658 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x658 8.--15. 1. "FVB,First valid block" bitfld.long 0x658 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x65C "GFXMMU_LUT715H,GFXMMU LUT entry 715 high" hexmask.long.tbyte 0x65C 0.--17. 1. "LO,Line offset" line.long 0x660 "GFXMMU_LUT716L,GFXMMU LUT entry 716 low" hexmask.long.byte 0x660 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x660 8.--15. 1. "FVB,First valid block" bitfld.long 0x660 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x664 "GFXMMU_LUT716H,GFXMMU LUT entry 716 high" hexmask.long.tbyte 0x664 0.--17. 1. "LO,Line offset" line.long 0x668 "GFXMMU_LUT717L,GFXMMU LUT entry 717 low" hexmask.long.byte 0x668 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x668 8.--15. 1. "FVB,First valid block" bitfld.long 0x668 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x66C "GFXMMU_LUT717H,GFXMMU LUT entry 717 high" hexmask.long.tbyte 0x66C 0.--17. 1. "LO,Line offset" line.long 0x670 "GFXMMU_LUT718L,GFXMMU LUT entry 718 low" hexmask.long.byte 0x670 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x670 8.--15. 1. "FVB,First valid block" bitfld.long 0x670 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x674 "GFXMMU_LUT718H,GFXMMU LUT entry 718 high" hexmask.long.tbyte 0x674 0.--17. 1. "LO,Line offset" line.long 0x678 "GFXMMU_LUT719L,GFXMMU LUT entry 719 low" hexmask.long.byte 0x678 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x678 8.--15. 1. "FVB,First valid block" bitfld.long 0x678 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x67C "GFXMMU_LUT719H,GFXMMU LUT entry 719 high" hexmask.long.tbyte 0x67C 0.--17. 1. "LO,Line offset" line.long 0x680 "GFXMMU_LUT720L,GFXMMU LUT entry 720 low" hexmask.long.byte 0x680 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x680 8.--15. 1. "FVB,First valid block" bitfld.long 0x680 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x684 "GFXMMU_LUT720H,GFXMMU LUT entry 720 high" hexmask.long.tbyte 0x684 0.--17. 1. "LO,Line offset" line.long 0x688 "GFXMMU_LUT721L,GFXMMU LUT entry 721 low" hexmask.long.byte 0x688 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x688 8.--15. 1. "FVB,First valid block" bitfld.long 0x688 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x68C "GFXMMU_LUT721H,GFXMMU LUT entry 721 high" hexmask.long.tbyte 0x68C 0.--17. 1. "LO,Line offset" line.long 0x690 "GFXMMU_LUT722L,GFXMMU LUT entry 722 low" hexmask.long.byte 0x690 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x690 8.--15. 1. "FVB,First valid block" bitfld.long 0x690 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x694 "GFXMMU_LUT722H,GFXMMU LUT entry 722 high" hexmask.long.tbyte 0x694 0.--17. 1. "LO,Line offset" line.long 0x698 "GFXMMU_LUT723L,GFXMMU LUT entry 723 low" hexmask.long.byte 0x698 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x698 8.--15. 1. "FVB,First valid block" bitfld.long 0x698 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x69C "GFXMMU_LUT723H,GFXMMU LUT entry 723 high" hexmask.long.tbyte 0x69C 0.--17. 1. "LO,Line offset" line.long 0x6A0 "GFXMMU_LUT724L,GFXMMU LUT entry 724 low" hexmask.long.byte 0x6A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6A4 "GFXMMU_LUT724H,GFXMMU LUT entry 724 high" hexmask.long.tbyte 0x6A4 0.--17. 1. "LO,Line offset" line.long 0x6A8 "GFXMMU_LUT725L,GFXMMU LUT entry 725 low" hexmask.long.byte 0x6A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6AC "GFXMMU_LUT725H,GFXMMU LUT entry 725 high" hexmask.long.tbyte 0x6AC 0.--17. 1. "LO,Line offset" line.long 0x6B0 "GFXMMU_LUT726L,GFXMMU LUT entry 726 low" hexmask.long.byte 0x6B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6B4 "GFXMMU_LUT726H,GFXMMU LUT entry 726 high" hexmask.long.tbyte 0x6B4 0.--17. 1. "LO,Line offset" line.long 0x6B8 "GFXMMU_LUT727L,GFXMMU LUT entry 727 low" hexmask.long.byte 0x6B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6BC "GFXMMU_LUT727H,GFXMMU LUT entry 727 high" hexmask.long.tbyte 0x6BC 0.--17. 1. "LO,Line offset" line.long 0x6C0 "GFXMMU_LUT728L,GFXMMU LUT entry 728 low" hexmask.long.byte 0x6C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C4 "GFXMMU_LUT728H,GFXMMU LUT entry 728 high" hexmask.long.tbyte 0x6C4 0.--17. 1. "LO,Line offset" line.long 0x6C8 "GFXMMU_LUT729L,GFXMMU LUT entry 729 low" hexmask.long.byte 0x6C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6CC "GFXMMU_LUT729H,GFXMMU LUT entry 729 high" hexmask.long.tbyte 0x6CC 0.--17. 1. "LO,Line offset" line.long 0x6D0 "GFXMMU_LUT730L,GFXMMU LUT entry 730 low" hexmask.long.byte 0x6D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6D4 "GFXMMU_LUT730H,GFXMMU LUT entry 730 high" hexmask.long.tbyte 0x6D4 0.--17. 1. "LO,Line offset" line.long 0x6D8 "GFXMMU_LUT731L,GFXMMU LUT entry 731 low" hexmask.long.byte 0x6D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6DC "GFXMMU_LUT731H,GFXMMU LUT entry 731 high" hexmask.long.tbyte 0x6DC 0.--17. 1. "LO,Line offset" line.long 0x6E0 "GFXMMU_LUT732L,GFXMMU LUT entry 732 low" hexmask.long.byte 0x6E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6E4 "GFXMMU_LUT732H,GFXMMU LUT entry 732 high" hexmask.long.tbyte 0x6E4 0.--17. 1. "LO,Line offset" line.long 0x6E8 "GFXMMU_LUT733L,GFXMMU LUT entry 733 low" hexmask.long.byte 0x6E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6EC "GFXMMU_LUT733H,GFXMMU LUT entry 733 high" hexmask.long.tbyte 0x6EC 0.--17. 1. "LO,Line offset" line.long 0x6F0 "GFXMMU_LUT734L,GFXMMU LUT entry 734 low" hexmask.long.byte 0x6F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6F4 "GFXMMU_LUT734H,GFXMMU LUT entry 734 high" hexmask.long.tbyte 0x6F4 0.--17. 1. "LO,Line offset" line.long 0x6F8 "GFXMMU_LUT735L,GFXMMU LUT entry 735 low" hexmask.long.byte 0x6F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6FC "GFXMMU_LUT735H,GFXMMU LUT entry 735 high" hexmask.long.tbyte 0x6FC 0.--17. 1. "LO,Line offset" line.long 0x700 "GFXMMU_LUT736L,GFXMMU LUT entry 736 low" hexmask.long.byte 0x700 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x700 8.--15. 1. "FVB,First valid block" bitfld.long 0x700 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x704 "GFXMMU_LUT736H,GFXMMU LUT entry 736 high" hexmask.long.tbyte 0x704 0.--17. 1. "LO,Line offset" line.long 0x708 "GFXMMU_LUT737L,GFXMMU LUT entry 737 low" hexmask.long.byte 0x708 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x708 8.--15. 1. "FVB,First valid block" bitfld.long 0x708 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x70C "GFXMMU_LUT737H,GFXMMU LUT entry 737 high" hexmask.long.tbyte 0x70C 0.--17. 1. "LO,Line offset" line.long 0x710 "GFXMMU_LUT738L,GFXMMU LUT entry 738 low" hexmask.long.byte 0x710 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x710 8.--15. 1. "FVB,First valid block" bitfld.long 0x710 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x714 "GFXMMU_LUT738H,GFXMMU LUT entry 738 high" hexmask.long.tbyte 0x714 0.--17. 1. "LO,Line offset" line.long 0x718 "GFXMMU_LUT739L,GFXMMU LUT entry 739 low" hexmask.long.byte 0x718 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x718 8.--15. 1. "FVB,First valid block" bitfld.long 0x718 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x71C "GFXMMU_LUT739H,GFXMMU LUT entry 739 high" hexmask.long.tbyte 0x71C 0.--17. 1. "LO,Line offset" line.long 0x720 "GFXMMU_LUT740L,GFXMMU LUT entry 740 low" hexmask.long.byte 0x720 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x720 8.--15. 1. "FVB,First valid block" bitfld.long 0x720 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x724 "GFXMMU_LUT740H,GFXMMU LUT entry 740 high" hexmask.long.tbyte 0x724 0.--17. 1. "LO,Line offset" line.long 0x728 "GFXMMU_LUT741L,GFXMMU LUT entry 741 low" hexmask.long.byte 0x728 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x728 8.--15. 1. "FVB,First valid block" bitfld.long 0x728 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x72C "GFXMMU_LUT741H,GFXMMU LUT entry 741 high" hexmask.long.tbyte 0x72C 0.--17. 1. "LO,Line offset" line.long 0x730 "GFXMMU_LUT742L,GFXMMU LUT entry 742 low" hexmask.long.byte 0x730 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x730 8.--15. 1. "FVB,First valid block" bitfld.long 0x730 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x734 "GFXMMU_LUT742H,GFXMMU LUT entry 742 high" hexmask.long.tbyte 0x734 0.--17. 1. "LO,Line offset" line.long 0x738 "GFXMMU_LUT743L,GFXMMU LUT entry 743 low" hexmask.long.byte 0x738 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x738 8.--15. 1. "FVB,First valid block" bitfld.long 0x738 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x73C "GFXMMU_LUT743H,GFXMMU LUT entry 743 high" hexmask.long.tbyte 0x73C 0.--17. 1. "LO,Line offset" line.long 0x740 "GFXMMU_LUT744L,GFXMMU LUT entry 744 low" hexmask.long.byte 0x740 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x740 8.--15. 1. "FVB,First valid block" bitfld.long 0x740 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x744 "GFXMMU_LUT744H,GFXMMU LUT entry 744 high" hexmask.long.tbyte 0x744 0.--17. 1. "LO,Line offset" line.long 0x748 "GFXMMU_LUT745L,GFXMMU LUT entry 745 low" hexmask.long.byte 0x748 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x748 8.--15. 1. "FVB,First valid block" bitfld.long 0x748 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74C "GFXMMU_LUT745H,GFXMMU LUT entry 745 high" hexmask.long.tbyte 0x74C 0.--17. 1. "LO,Line offset" line.long 0x750 "GFXMMU_LUT746L,GFXMMU LUT entry 746 low" hexmask.long.byte 0x750 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x750 8.--15. 1. "FVB,First valid block" bitfld.long 0x750 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x754 "GFXMMU_LUT746H,GFXMMU LUT entry 746 high" hexmask.long.tbyte 0x754 0.--17. 1. "LO,Line offset" line.long 0x758 "GFXMMU_LUT747L,GFXMMU LUT entry 747 low" hexmask.long.byte 0x758 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x758 8.--15. 1. "FVB,First valid block" bitfld.long 0x758 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x75C "GFXMMU_LUT747H,GFXMMU LUT entry 747 high" hexmask.long.tbyte 0x75C 0.--17. 1. "LO,Line offset" line.long 0x760 "GFXMMU_LUT748L,GFXMMU LUT entry 748 low" hexmask.long.byte 0x760 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x760 8.--15. 1. "FVB,First valid block" bitfld.long 0x760 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x764 "GFXMMU_LUT748H,GFXMMU LUT entry 748 high" hexmask.long.tbyte 0x764 0.--17. 1. "LO,Line offset" line.long 0x768 "GFXMMU_LUT749L,GFXMMU LUT entry 749 low" hexmask.long.byte 0x768 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x768 8.--15. 1. "FVB,First valid block" bitfld.long 0x768 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x76C "GFXMMU_LUT749H,GFXMMU LUT entry 749 high" hexmask.long.tbyte 0x76C 0.--17. 1. "LO,Line offset" line.long 0x770 "GFXMMU_LUT750L,GFXMMU LUT entry 750 low" hexmask.long.byte 0x770 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x770 8.--15. 1. "FVB,First valid block" bitfld.long 0x770 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x774 "GFXMMU_LUT750H,GFXMMU LUT entry 750 high" hexmask.long.tbyte 0x774 0.--17. 1. "LO,Line offset" line.long 0x778 "GFXMMU_LUT751L,GFXMMU LUT entry 751 low" hexmask.long.byte 0x778 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x778 8.--15. 1. "FVB,First valid block" bitfld.long 0x778 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x77C "GFXMMU_LUT751H,GFXMMU LUT entry 751 high" hexmask.long.tbyte 0x77C 0.--17. 1. "LO,Line offset" line.long 0x780 "GFXMMU_LUT752L,GFXMMU LUT entry 752 low" hexmask.long.byte 0x780 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x780 8.--15. 1. "FVB,First valid block" bitfld.long 0x780 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x784 "GFXMMU_LUT752H,GFXMMU LUT entry 752 high" hexmask.long.tbyte 0x784 0.--17. 1. "LO,Line offset" line.long 0x788 "GFXMMU_LUT753L,GFXMMU LUT entry 753 low" hexmask.long.byte 0x788 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x788 8.--15. 1. "FVB,First valid block" bitfld.long 0x788 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x78C "GFXMMU_LUT753H,GFXMMU LUT entry 753 high" hexmask.long.tbyte 0x78C 0.--17. 1. "LO,Line offset" line.long 0x790 "GFXMMU_LUT754L,GFXMMU LUT entry 754 low" hexmask.long.byte 0x790 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x790 8.--15. 1. "FVB,First valid block" bitfld.long 0x790 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x794 "GFXMMU_LUT754H,GFXMMU LUT entry 754 high" hexmask.long.tbyte 0x794 0.--17. 1. "LO,Line offset" line.long 0x798 "GFXMMU_LUT755L,GFXMMU LUT entry 755 low" hexmask.long.byte 0x798 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x798 8.--15. 1. "FVB,First valid block" bitfld.long 0x798 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x79C "GFXMMU_LUT755H,GFXMMU LUT entry 755 high" hexmask.long.tbyte 0x79C 0.--17. 1. "LO,Line offset" line.long 0x7A0 "GFXMMU_LUT756L,GFXMMU LUT entry 756 low" hexmask.long.byte 0x7A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7A4 "GFXMMU_LUT756H,GFXMMU LUT entry 756 high" hexmask.long.tbyte 0x7A4 0.--17. 1. "LO,Line offset" line.long 0x7A8 "GFXMMU_LUT757L,GFXMMU LUT entry 757 low" hexmask.long.byte 0x7A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7AC "GFXMMU_LUT757H,GFXMMU LUT entry 757 high" hexmask.long.tbyte 0x7AC 0.--17. 1. "LO,Line offset" line.long 0x7B0 "GFXMMU_LUT758L,GFXMMU LUT entry 758 low" hexmask.long.byte 0x7B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7B4 "GFXMMU_LUT758H,GFXMMU LUT entry 758 high" hexmask.long.tbyte 0x7B4 0.--17. 1. "LO,Line offset" line.long 0x7B8 "GFXMMU_LUT759L,GFXMMU LUT entry 759 low" hexmask.long.byte 0x7B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7BC "GFXMMU_LUT759H,GFXMMU LUT entry 759 high" hexmask.long.tbyte 0x7BC 0.--17. 1. "LO,Line offset" line.long 0x7C0 "GFXMMU_LUT760L,GFXMMU LUT entry 760 low" hexmask.long.byte 0x7C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C4 "GFXMMU_LUT760H,GFXMMU LUT entry 760 high" hexmask.long.tbyte 0x7C4 0.--17. 1. "LO,Line offset" line.long 0x7C8 "GFXMMU_LUT761L,GFXMMU LUT entry 761 low" hexmask.long.byte 0x7C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7CC "GFXMMU_LUT761H,GFXMMU LUT entry 761 high" hexmask.long.tbyte 0x7CC 0.--17. 1. "LO,Line offset" line.long 0x7D0 "GFXMMU_LUT762L,GFXMMU LUT entry 762 low" hexmask.long.byte 0x7D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7D4 "GFXMMU_LUT762H,GFXMMU LUT entry 762 high" hexmask.long.tbyte 0x7D4 0.--17. 1. "LO,Line offset" line.long 0x7D8 "GFXMMU_LUT763L,GFXMMU LUT entry 763 low" hexmask.long.byte 0x7D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7DC "GFXMMU_LUT763H,GFXMMU LUT entry 763 high" hexmask.long.tbyte 0x7DC 0.--17. 1. "LO,Line offset" line.long 0x7E0 "GFXMMU_LUT764L,GFXMMU LUT entry 764 low" hexmask.long.byte 0x7E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7E4 "GFXMMU_LUT764H,GFXMMU LUT entry 764 high" hexmask.long.tbyte 0x7E4 0.--17. 1. "LO,Line offset" line.long 0x7E8 "GFXMMU_LUT765L,GFXMMU LUT entry 765 low" hexmask.long.byte 0x7E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7EC "GFXMMU_LUT765H,GFXMMU LUT entry 765 high" hexmask.long.tbyte 0x7EC 0.--17. 1. "LO,Line offset" line.long 0x7F0 "GFXMMU_LUT766L,GFXMMU LUT entry 766 low" hexmask.long.byte 0x7F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7F4 "GFXMMU_LUT766H,GFXMMU LUT entry 766 high" hexmask.long.tbyte 0x7F4 0.--17. 1. "LO,Line offset" line.long 0x7F8 "GFXMMU_LUT767L,GFXMMU LUT entry 767 low" hexmask.long.byte 0x7F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7FC "GFXMMU_LUT767H,GFXMMU LUT entry 767 high" hexmask.long.tbyte 0x7FC 0.--17. 1. "LO,Line offset" line.long 0x800 "GFXMMU_LUT768L,GFXMMU LUT entry 768 low" hexmask.long.byte 0x800 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x800 8.--15. 1. "FVB,First valid block" bitfld.long 0x800 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x804 "GFXMMU_LUT768H,GFXMMU LUT entry 768 high" hexmask.long.tbyte 0x804 0.--17. 1. "LO,Line offset" line.long 0x808 "GFXMMU_LUT769L,GFXMMU LUT entry 769 low" hexmask.long.byte 0x808 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x808 8.--15. 1. "FVB,First valid block" bitfld.long 0x808 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x80C "GFXMMU_LUT769H,GFXMMU LUT entry 769 high" hexmask.long.tbyte 0x80C 0.--17. 1. "LO,Line offset" line.long 0x810 "GFXMMU_LUT770L,GFXMMU LUT entry 770 low" hexmask.long.byte 0x810 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x810 8.--15. 1. "FVB,First valid block" bitfld.long 0x810 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x814 "GFXMMU_LUT770H,GFXMMU LUT entry 770 high" hexmask.long.tbyte 0x814 0.--17. 1. "LO,Line offset" line.long 0x818 "GFXMMU_LUT771L,GFXMMU LUT entry 771 low" hexmask.long.byte 0x818 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x818 8.--15. 1. "FVB,First valid block" bitfld.long 0x818 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x81C "GFXMMU_LUT771H,GFXMMU LUT entry 771 high" hexmask.long.tbyte 0x81C 0.--17. 1. "LO,Line offset" line.long 0x820 "GFXMMU_LUT772L,GFXMMU LUT entry 772 low" hexmask.long.byte 0x820 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x820 8.--15. 1. "FVB,First valid block" bitfld.long 0x820 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x824 "GFXMMU_LUT772H,GFXMMU LUT entry 772 high" hexmask.long.tbyte 0x824 0.--17. 1. "LO,Line offset" line.long 0x828 "GFXMMU_LUT773L,GFXMMU LUT entry 773 low" hexmask.long.byte 0x828 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x828 8.--15. 1. "FVB,First valid block" bitfld.long 0x828 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x82C "GFXMMU_LUT773H,GFXMMU LUT entry 773 high" hexmask.long.tbyte 0x82C 0.--17. 1. "LO,Line offset" line.long 0x830 "GFXMMU_LUT774L,GFXMMU LUT entry 774 low" hexmask.long.byte 0x830 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x830 8.--15. 1. "FVB,First valid block" bitfld.long 0x830 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x834 "GFXMMU_LUT774H,GFXMMU LUT entry 774 high" hexmask.long.tbyte 0x834 0.--17. 1. "LO,Line offset" line.long 0x838 "GFXMMU_LUT775L,GFXMMU LUT entry 775 low" hexmask.long.byte 0x838 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x838 8.--15. 1. "FVB,First valid block" bitfld.long 0x838 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x83C "GFXMMU_LUT775H,GFXMMU LUT entry 775 high" hexmask.long.tbyte 0x83C 0.--17. 1. "LO,Line offset" line.long 0x840 "GFXMMU_LUT776L,GFXMMU LUT entry 776 low" hexmask.long.byte 0x840 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x840 8.--15. 1. "FVB,First valid block" bitfld.long 0x840 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x844 "GFXMMU_LUT776H,GFXMMU LUT entry 776 high" hexmask.long.tbyte 0x844 0.--17. 1. "LO,Line offset" line.long 0x848 "GFXMMU_LUT777L,GFXMMU LUT entry 777 low" hexmask.long.byte 0x848 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x848 8.--15. 1. "FVB,First valid block" bitfld.long 0x848 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84C "GFXMMU_LUT777H,GFXMMU LUT entry 777 high" hexmask.long.tbyte 0x84C 0.--17. 1. "LO,Line offset" line.long 0x850 "GFXMMU_LUT778L,GFXMMU LUT entry 778 low" hexmask.long.byte 0x850 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x850 8.--15. 1. "FVB,First valid block" bitfld.long 0x850 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x854 "GFXMMU_LUT778H,GFXMMU LUT entry 778 high" hexmask.long.tbyte 0x854 0.--17. 1. "LO,Line offset" line.long 0x858 "GFXMMU_LUT779L,GFXMMU LUT entry 779 low" hexmask.long.byte 0x858 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x858 8.--15. 1. "FVB,First valid block" bitfld.long 0x858 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x85C "GFXMMU_LUT779H,GFXMMU LUT entry 779 high" hexmask.long.tbyte 0x85C 0.--17. 1. "LO,Line offset" line.long 0x860 "GFXMMU_LUT780L,GFXMMU LUT entry 780 low" hexmask.long.byte 0x860 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x860 8.--15. 1. "FVB,First valid block" bitfld.long 0x860 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x864 "GFXMMU_LUT780H,GFXMMU LUT entry 780 high" hexmask.long.tbyte 0x864 0.--17. 1. "LO,Line offset" line.long 0x868 "GFXMMU_LUT781L,GFXMMU LUT entry 781 low" hexmask.long.byte 0x868 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x868 8.--15. 1. "FVB,First valid block" bitfld.long 0x868 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x86C "GFXMMU_LUT781H,GFXMMU LUT entry 781 high" hexmask.long.tbyte 0x86C 0.--17. 1. "LO,Line offset" line.long 0x870 "GFXMMU_LUT782L,GFXMMU LUT entry 782 low" hexmask.long.byte 0x870 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x870 8.--15. 1. "FVB,First valid block" bitfld.long 0x870 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x874 "GFXMMU_LUT782H,GFXMMU LUT entry 782 high" hexmask.long.tbyte 0x874 0.--17. 1. "LO,Line offset" line.long 0x878 "GFXMMU_LUT783L,GFXMMU LUT entry 783 low" hexmask.long.byte 0x878 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x878 8.--15. 1. "FVB,First valid block" bitfld.long 0x878 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x87C "GFXMMU_LUT783H,GFXMMU LUT entry 783 high" hexmask.long.tbyte 0x87C 0.--17. 1. "LO,Line offset" line.long 0x880 "GFXMMU_LUT784L,GFXMMU LUT entry 784 low" hexmask.long.byte 0x880 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x880 8.--15. 1. "FVB,First valid block" bitfld.long 0x880 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x884 "GFXMMU_LUT784H,GFXMMU LUT entry 784 high" hexmask.long.tbyte 0x884 0.--17. 1. "LO,Line offset" line.long 0x888 "GFXMMU_LUT785L,GFXMMU LUT entry 785 low" hexmask.long.byte 0x888 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x888 8.--15. 1. "FVB,First valid block" bitfld.long 0x888 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x88C "GFXMMU_LUT785H,GFXMMU LUT entry 785 high" hexmask.long.tbyte 0x88C 0.--17. 1. "LO,Line offset" line.long 0x890 "GFXMMU_LUT786L,GFXMMU LUT entry 786 low" hexmask.long.byte 0x890 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x890 8.--15. 1. "FVB,First valid block" bitfld.long 0x890 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x894 "GFXMMU_LUT786H,GFXMMU LUT entry 786 high" hexmask.long.tbyte 0x894 0.--17. 1. "LO,Line offset" line.long 0x898 "GFXMMU_LUT787L,GFXMMU LUT entry 787 low" hexmask.long.byte 0x898 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x898 8.--15. 1. "FVB,First valid block" bitfld.long 0x898 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x89C "GFXMMU_LUT787H,GFXMMU LUT entry 787 high" hexmask.long.tbyte 0x89C 0.--17. 1. "LO,Line offset" line.long 0x8A0 "GFXMMU_LUT788L,GFXMMU LUT entry 788 low" hexmask.long.byte 0x8A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8A4 "GFXMMU_LUT788H,GFXMMU LUT entry 788 high" hexmask.long.tbyte 0x8A4 0.--17. 1. "LO,Line offset" line.long 0x8A8 "GFXMMU_LUT789L,GFXMMU LUT entry 789 low" hexmask.long.byte 0x8A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8AC "GFXMMU_LUT789H,GFXMMU LUT entry 789 high" hexmask.long.tbyte 0x8AC 0.--17. 1. "LO,Line offset" line.long 0x8B0 "GFXMMU_LUT790L,GFXMMU LUT entry 790 low" hexmask.long.byte 0x8B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8B4 "GFXMMU_LUT790H,GFXMMU LUT entry 790 high" hexmask.long.tbyte 0x8B4 0.--17. 1. "LO,Line offset" line.long 0x8B8 "GFXMMU_LUT791L,GFXMMU LUT entry 791 low" hexmask.long.byte 0x8B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8BC "GFXMMU_LUT791H,GFXMMU LUT entry 791 high" hexmask.long.tbyte 0x8BC 0.--17. 1. "LO,Line offset" line.long 0x8C0 "GFXMMU_LUT792L,GFXMMU LUT entry 792 low" hexmask.long.byte 0x8C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C4 "GFXMMU_LUT792H,GFXMMU LUT entry 792 high" hexmask.long.tbyte 0x8C4 0.--17. 1. "LO,Line offset" line.long 0x8C8 "GFXMMU_LUT793L,GFXMMU LUT entry 793 low" hexmask.long.byte 0x8C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8CC "GFXMMU_LUT793H,GFXMMU LUT entry 793 high" hexmask.long.tbyte 0x8CC 0.--17. 1. "LO,Line offset" line.long 0x8D0 "GFXMMU_LUT794L,GFXMMU LUT entry 794 low" hexmask.long.byte 0x8D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8D4 "GFXMMU_LUT794H,GFXMMU LUT entry 794 high" hexmask.long.tbyte 0x8D4 0.--17. 1. "LO,Line offset" line.long 0x8D8 "GFXMMU_LUT795L,GFXMMU LUT entry 795 low" hexmask.long.byte 0x8D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8DC "GFXMMU_LUT795H,GFXMMU LUT entry 795 high" hexmask.long.tbyte 0x8DC 0.--17. 1. "LO,Line offset" line.long 0x8E0 "GFXMMU_LUT796L,GFXMMU LUT entry 796 low" hexmask.long.byte 0x8E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8E4 "GFXMMU_LUT796H,GFXMMU LUT entry 796 high" hexmask.long.tbyte 0x8E4 0.--17. 1. "LO,Line offset" line.long 0x8E8 "GFXMMU_LUT797L,GFXMMU LUT entry 797 low" hexmask.long.byte 0x8E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8EC "GFXMMU_LUT797H,GFXMMU LUT entry 797 high" hexmask.long.tbyte 0x8EC 0.--17. 1. "LO,Line offset" line.long 0x8F0 "GFXMMU_LUT798L,GFXMMU LUT entry 798 low" hexmask.long.byte 0x8F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8F4 "GFXMMU_LUT798H,GFXMMU LUT entry 798 high" hexmask.long.tbyte 0x8F4 0.--17. 1. "LO,Line offset" line.long 0x8F8 "GFXMMU_LUT799L,GFXMMU LUT entry 799 low" hexmask.long.byte 0x8F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8FC "GFXMMU_LUT799H,GFXMMU LUT entry 799 high" hexmask.long.tbyte 0x8FC 0.--17. 1. "LO,Line offset" line.long 0x900 "GFXMMU_LUT800L,GFXMMU LUT entry 800 low" hexmask.long.byte 0x900 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x900 8.--15. 1. "FVB,First valid block" bitfld.long 0x900 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x904 "GFXMMU_LUT800H,GFXMMU LUT entry 800 high" hexmask.long.tbyte 0x904 0.--17. 1. "LO,Line offset" line.long 0x908 "GFXMMU_LUT801L,GFXMMU LUT entry 801 low" hexmask.long.byte 0x908 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x908 8.--15. 1. "FVB,First valid block" bitfld.long 0x908 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x90C "GFXMMU_LUT801H,GFXMMU LUT entry 801 high" hexmask.long.tbyte 0x90C 0.--17. 1. "LO,Line offset" line.long 0x910 "GFXMMU_LUT802L,GFXMMU LUT entry 802 low" hexmask.long.byte 0x910 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x910 8.--15. 1. "FVB,First valid block" bitfld.long 0x910 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x914 "GFXMMU_LUT802H,GFXMMU LUT entry 802 high" hexmask.long.tbyte 0x914 0.--17. 1. "LO,Line offset" line.long 0x918 "GFXMMU_LUT803L,GFXMMU LUT entry 803 low" hexmask.long.byte 0x918 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x918 8.--15. 1. "FVB,First valid block" bitfld.long 0x918 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x91C "GFXMMU_LUT803H,GFXMMU LUT entry 803 high" hexmask.long.tbyte 0x91C 0.--17. 1. "LO,Line offset" line.long 0x920 "GFXMMU_LUT804L,GFXMMU LUT entry 804 low" hexmask.long.byte 0x920 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x920 8.--15. 1. "FVB,First valid block" bitfld.long 0x920 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x924 "GFXMMU_LUT804H,GFXMMU LUT entry 804 high" hexmask.long.tbyte 0x924 0.--17. 1. "LO,Line offset" line.long 0x928 "GFXMMU_LUT805L,GFXMMU LUT entry 805 low" hexmask.long.byte 0x928 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x928 8.--15. 1. "FVB,First valid block" bitfld.long 0x928 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x92C "GFXMMU_LUT805H,GFXMMU LUT entry 805 high" hexmask.long.tbyte 0x92C 0.--17. 1. "LO,Line offset" line.long 0x930 "GFXMMU_LUT806L,GFXMMU LUT entry 806 low" hexmask.long.byte 0x930 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x930 8.--15. 1. "FVB,First valid block" bitfld.long 0x930 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x934 "GFXMMU_LUT806H,GFXMMU LUT entry 806 high" hexmask.long.tbyte 0x934 0.--17. 1. "LO,Line offset" line.long 0x938 "GFXMMU_LUT807L,GFXMMU LUT entry 807 low" hexmask.long.byte 0x938 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x938 8.--15. 1. "FVB,First valid block" bitfld.long 0x938 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x93C "GFXMMU_LUT807H,GFXMMU LUT entry 807 high" hexmask.long.tbyte 0x93C 0.--17. 1. "LO,Line offset" line.long 0x940 "GFXMMU_LUT808L,GFXMMU LUT entry 808 low" hexmask.long.byte 0x940 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x940 8.--15. 1. "FVB,First valid block" bitfld.long 0x940 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x944 "GFXMMU_LUT808H,GFXMMU LUT entry 808 high" hexmask.long.tbyte 0x944 0.--17. 1. "LO,Line offset" line.long 0x948 "GFXMMU_LUT809L,GFXMMU LUT entry 809 low" hexmask.long.byte 0x948 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x948 8.--15. 1. "FVB,First valid block" bitfld.long 0x948 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94C "GFXMMU_LUT809H,GFXMMU LUT entry 809 high" hexmask.long.tbyte 0x94C 0.--17. 1. "LO,Line offset" line.long 0x950 "GFXMMU_LUT810L,GFXMMU LUT entry 810 low" hexmask.long.byte 0x950 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x950 8.--15. 1. "FVB,First valid block" bitfld.long 0x950 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x954 "GFXMMU_LUT810H,GFXMMU LUT entry 810 high" hexmask.long.tbyte 0x954 0.--17. 1. "LO,Line offset" line.long 0x958 "GFXMMU_LUT811L,GFXMMU LUT entry 811 low" hexmask.long.byte 0x958 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x958 8.--15. 1. "FVB,First valid block" bitfld.long 0x958 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x95C "GFXMMU_LUT811H,GFXMMU LUT entry 811 high" hexmask.long.tbyte 0x95C 0.--17. 1. "LO,Line offset" line.long 0x960 "GFXMMU_LUT812L,GFXMMU LUT entry 812 low" hexmask.long.byte 0x960 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x960 8.--15. 1. "FVB,First valid block" bitfld.long 0x960 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x964 "GFXMMU_LUT812H,GFXMMU LUT entry 812 high" hexmask.long.tbyte 0x964 0.--17. 1. "LO,Line offset" line.long 0x968 "GFXMMU_LUT813L,GFXMMU LUT entry 813 low" hexmask.long.byte 0x968 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x968 8.--15. 1. "FVB,First valid block" bitfld.long 0x968 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x96C "GFXMMU_LUT813H,GFXMMU LUT entry 813 high" hexmask.long.tbyte 0x96C 0.--17. 1. "LO,Line offset" line.long 0x970 "GFXMMU_LUT814L,GFXMMU LUT entry 814 low" hexmask.long.byte 0x970 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x970 8.--15. 1. "FVB,First valid block" bitfld.long 0x970 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x974 "GFXMMU_LUT814H,GFXMMU LUT entry 814 high" hexmask.long.tbyte 0x974 0.--17. 1. "LO,Line offset" line.long 0x978 "GFXMMU_LUT815L,GFXMMU LUT entry 815 low" hexmask.long.byte 0x978 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x978 8.--15. 1. "FVB,First valid block" bitfld.long 0x978 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x97C "GFXMMU_LUT815H,GFXMMU LUT entry 815 high" hexmask.long.tbyte 0x97C 0.--17. 1. "LO,Line offset" line.long 0x980 "GFXMMU_LUT816L,GFXMMU LUT entry 816 low" hexmask.long.byte 0x980 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x980 8.--15. 1. "FVB,First valid block" bitfld.long 0x980 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x984 "GFXMMU_LUT816H,GFXMMU LUT entry 816 high" hexmask.long.tbyte 0x984 0.--17. 1. "LO,Line offset" line.long 0x988 "GFXMMU_LUT817L,GFXMMU LUT entry 817 low" hexmask.long.byte 0x988 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x988 8.--15. 1. "FVB,First valid block" bitfld.long 0x988 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x98C "GFXMMU_LUT817H,GFXMMU LUT entry 817 high" hexmask.long.tbyte 0x98C 0.--17. 1. "LO,Line offset" line.long 0x990 "GFXMMU_LUT818L,GFXMMU LUT entry 818 low" hexmask.long.byte 0x990 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x990 8.--15. 1. "FVB,First valid block" bitfld.long 0x990 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x994 "GFXMMU_LUT818H,GFXMMU LUT entry 818 high" hexmask.long.tbyte 0x994 0.--17. 1. "LO,Line offset" line.long 0x998 "GFXMMU_LUT819L,GFXMMU LUT entry 819 low" hexmask.long.byte 0x998 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x998 8.--15. 1. "FVB,First valid block" bitfld.long 0x998 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x99C "GFXMMU_LUT819H,GFXMMU LUT entry 819 high" hexmask.long.tbyte 0x99C 0.--17. 1. "LO,Line offset" line.long 0x9A0 "GFXMMU_LUT820L,GFXMMU LUT entry 820 low" hexmask.long.byte 0x9A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9A4 "GFXMMU_LUT820H,GFXMMU LUT entry 820 high" hexmask.long.tbyte 0x9A4 0.--17. 1. "LO,Line offset" line.long 0x9A8 "GFXMMU_LUT821L,GFXMMU LUT entry 821 low" hexmask.long.byte 0x9A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9AC "GFXMMU_LUT821H,GFXMMU LUT entry 821 high" hexmask.long.tbyte 0x9AC 0.--17. 1. "LO,Line offset" line.long 0x9B0 "GFXMMU_LUT822L,GFXMMU LUT entry 822 low" hexmask.long.byte 0x9B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9B4 "GFXMMU_LUT822H,GFXMMU LUT entry 822 high" hexmask.long.tbyte 0x9B4 0.--17. 1. "LO,Line offset" line.long 0x9B8 "GFXMMU_LUT823L,GFXMMU LUT entry 823 low" hexmask.long.byte 0x9B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9BC "GFXMMU_LUT823H,GFXMMU LUT entry 823 high" hexmask.long.tbyte 0x9BC 0.--17. 1. "LO,Line offset" line.long 0x9C0 "GFXMMU_LUT824L,GFXMMU LUT entry 824 low" hexmask.long.byte 0x9C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C4 "GFXMMU_LUT824H,GFXMMU LUT entry 824 high" hexmask.long.tbyte 0x9C4 0.--17. 1. "LO,Line offset" line.long 0x9C8 "GFXMMU_LUT825L,GFXMMU LUT entry 825 low" hexmask.long.byte 0x9C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9CC "GFXMMU_LUT825H,GFXMMU LUT entry 825 high" hexmask.long.tbyte 0x9CC 0.--17. 1. "LO,Line offset" line.long 0x9D0 "GFXMMU_LUT826L,GFXMMU LUT entry 826 low" hexmask.long.byte 0x9D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9D4 "GFXMMU_LUT826H,GFXMMU LUT entry 826 high" hexmask.long.tbyte 0x9D4 0.--17. 1. "LO,Line offset" line.long 0x9D8 "GFXMMU_LUT827L,GFXMMU LUT entry 827 low" hexmask.long.byte 0x9D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9DC "GFXMMU_LUT827H,GFXMMU LUT entry 827 high" hexmask.long.tbyte 0x9DC 0.--17. 1. "LO,Line offset" line.long 0x9E0 "GFXMMU_LUT828L,GFXMMU LUT entry 828 low" hexmask.long.byte 0x9E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9E4 "GFXMMU_LUT828H,GFXMMU LUT entry 828 high" hexmask.long.tbyte 0x9E4 0.--17. 1. "LO,Line offset" line.long 0x9E8 "GFXMMU_LUT829L,GFXMMU LUT entry 829 low" hexmask.long.byte 0x9E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9EC "GFXMMU_LUT829H,GFXMMU LUT entry 829 high" hexmask.long.tbyte 0x9EC 0.--17. 1. "LO,Line offset" line.long 0x9F0 "GFXMMU_LUT830L,GFXMMU LUT entry 830 low" hexmask.long.byte 0x9F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9F4 "GFXMMU_LUT830H,GFXMMU LUT entry 830 high" hexmask.long.tbyte 0x9F4 0.--17. 1. "LO,Line offset" line.long 0x9F8 "GFXMMU_LUT831L,GFXMMU LUT entry 831 low" hexmask.long.byte 0x9F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9FC "GFXMMU_LUT831H,GFXMMU LUT entry 831 high" hexmask.long.tbyte 0x9FC 0.--17. 1. "LO,Line offset" line.long 0xA00 "GFXMMU_LUT832L,GFXMMU LUT entry 832 low" hexmask.long.byte 0xA00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA00 8.--15. 1. "FVB,First valid block" bitfld.long 0xA00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA04 "GFXMMU_LUT832H,GFXMMU LUT entry 832 high" hexmask.long.tbyte 0xA04 0.--17. 1. "LO,Line offset" line.long 0xA08 "GFXMMU_LUT833L,GFXMMU LUT entry 833 low" hexmask.long.byte 0xA08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA08 8.--15. 1. "FVB,First valid block" bitfld.long 0xA08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA0C "GFXMMU_LUT833H,GFXMMU LUT entry 833 high" hexmask.long.tbyte 0xA0C 0.--17. 1. "LO,Line offset" line.long 0xA10 "GFXMMU_LUT834L,GFXMMU LUT entry 834 low" hexmask.long.byte 0xA10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA10 8.--15. 1. "FVB,First valid block" bitfld.long 0xA10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA14 "GFXMMU_LUT834H,GFXMMU LUT entry 834 high" hexmask.long.tbyte 0xA14 0.--17. 1. "LO,Line offset" line.long 0xA18 "GFXMMU_LUT835L,GFXMMU LUT entry 835 low" hexmask.long.byte 0xA18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA18 8.--15. 1. "FVB,First valid block" bitfld.long 0xA18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA1C "GFXMMU_LUT835H,GFXMMU LUT entry 835 high" hexmask.long.tbyte 0xA1C 0.--17. 1. "LO,Line offset" line.long 0xA20 "GFXMMU_LUT836L,GFXMMU LUT entry 836 low" hexmask.long.byte 0xA20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA20 8.--15. 1. "FVB,First valid block" bitfld.long 0xA20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA24 "GFXMMU_LUT836H,GFXMMU LUT entry 836 high" hexmask.long.tbyte 0xA24 0.--17. 1. "LO,Line offset" line.long 0xA28 "GFXMMU_LUT837L,GFXMMU LUT entry 837 low" hexmask.long.byte 0xA28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA28 8.--15. 1. "FVB,First valid block" bitfld.long 0xA28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA2C "GFXMMU_LUT837H,GFXMMU LUT entry 837 high" hexmask.long.tbyte 0xA2C 0.--17. 1. "LO,Line offset" line.long 0xA30 "GFXMMU_LUT838L,GFXMMU LUT entry 838 low" hexmask.long.byte 0xA30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA30 8.--15. 1. "FVB,First valid block" bitfld.long 0xA30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA34 "GFXMMU_LUT838H,GFXMMU LUT entry 838 high" hexmask.long.tbyte 0xA34 0.--17. 1. "LO,Line offset" line.long 0xA38 "GFXMMU_LUT839L,GFXMMU LUT entry 839 low" hexmask.long.byte 0xA38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA38 8.--15. 1. "FVB,First valid block" bitfld.long 0xA38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA3C "GFXMMU_LUT839H,GFXMMU LUT entry 839 high" hexmask.long.tbyte 0xA3C 0.--17. 1. "LO,Line offset" line.long 0xA40 "GFXMMU_LUT840L,GFXMMU LUT entry 840 low" hexmask.long.byte 0xA40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA40 8.--15. 1. "FVB,First valid block" bitfld.long 0xA40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA44 "GFXMMU_LUT840H,GFXMMU LUT entry 840 high" hexmask.long.tbyte 0xA44 0.--17. 1. "LO,Line offset" line.long 0xA48 "GFXMMU_LUT841L,GFXMMU LUT entry 841 low" hexmask.long.byte 0xA48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA48 8.--15. 1. "FVB,First valid block" bitfld.long 0xA48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4C "GFXMMU_LUT841H,GFXMMU LUT entry 841 high" hexmask.long.tbyte 0xA4C 0.--17. 1. "LO,Line offset" line.long 0xA50 "GFXMMU_LUT842L,GFXMMU LUT entry 842 low" hexmask.long.byte 0xA50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA50 8.--15. 1. "FVB,First valid block" bitfld.long 0xA50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA54 "GFXMMU_LUT842H,GFXMMU LUT entry 842 high" hexmask.long.tbyte 0xA54 0.--17. 1. "LO,Line offset" line.long 0xA58 "GFXMMU_LUT843L,GFXMMU LUT entry 843 low" hexmask.long.byte 0xA58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA58 8.--15. 1. "FVB,First valid block" bitfld.long 0xA58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA5C "GFXMMU_LUT843H,GFXMMU LUT entry 843 high" hexmask.long.tbyte 0xA5C 0.--17. 1. "LO,Line offset" line.long 0xA60 "GFXMMU_LUT844L,GFXMMU LUT entry 844 low" hexmask.long.byte 0xA60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA60 8.--15. 1. "FVB,First valid block" bitfld.long 0xA60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA64 "GFXMMU_LUT844H,GFXMMU LUT entry 844 high" hexmask.long.tbyte 0xA64 0.--17. 1. "LO,Line offset" line.long 0xA68 "GFXMMU_LUT845L,GFXMMU LUT entry 845 low" hexmask.long.byte 0xA68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA68 8.--15. 1. "FVB,First valid block" bitfld.long 0xA68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA6C "GFXMMU_LUT845H,GFXMMU LUT entry 845 high" hexmask.long.tbyte 0xA6C 0.--17. 1. "LO,Line offset" line.long 0xA70 "GFXMMU_LUT846L,GFXMMU LUT entry 846 low" hexmask.long.byte 0xA70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA70 8.--15. 1. "FVB,First valid block" bitfld.long 0xA70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA74 "GFXMMU_LUT846H,GFXMMU LUT entry 846 high" hexmask.long.tbyte 0xA74 0.--17. 1. "LO,Line offset" line.long 0xA78 "GFXMMU_LUT847L,GFXMMU LUT entry 847 low" hexmask.long.byte 0xA78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA78 8.--15. 1. "FVB,First valid block" bitfld.long 0xA78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA7C "GFXMMU_LUT847H,GFXMMU LUT entry 847 high" hexmask.long.tbyte 0xA7C 0.--17. 1. "LO,Line offset" line.long 0xA80 "GFXMMU_LUT848L,GFXMMU LUT entry 848 low" hexmask.long.byte 0xA80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA80 8.--15. 1. "FVB,First valid block" bitfld.long 0xA80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA84 "GFXMMU_LUT848H,GFXMMU LUT entry 848 high" hexmask.long.tbyte 0xA84 0.--17. 1. "LO,Line offset" line.long 0xA88 "GFXMMU_LUT849L,GFXMMU LUT entry 849 low" hexmask.long.byte 0xA88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA88 8.--15. 1. "FVB,First valid block" bitfld.long 0xA88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA8C "GFXMMU_LUT849H,GFXMMU LUT entry 849 high" hexmask.long.tbyte 0xA8C 0.--17. 1. "LO,Line offset" line.long 0xA90 "GFXMMU_LUT850L,GFXMMU LUT entry 850 low" hexmask.long.byte 0xA90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA90 8.--15. 1. "FVB,First valid block" bitfld.long 0xA90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA94 "GFXMMU_LUT850H,GFXMMU LUT entry 850 high" hexmask.long.tbyte 0xA94 0.--17. 1. "LO,Line offset" line.long 0xA98 "GFXMMU_LUT851L,GFXMMU LUT entry 851 low" hexmask.long.byte 0xA98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA98 8.--15. 1. "FVB,First valid block" bitfld.long 0xA98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA9C "GFXMMU_LUT851H,GFXMMU LUT entry 851 high" hexmask.long.tbyte 0xA9C 0.--17. 1. "LO,Line offset" line.long 0xAA0 "GFXMMU_LUT852L,GFXMMU LUT entry 852 low" hexmask.long.byte 0xAA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAA4 "GFXMMU_LUT852H,GFXMMU LUT entry 852 high" hexmask.long.tbyte 0xAA4 0.--17. 1. "LO,Line offset" line.long 0xAA8 "GFXMMU_LUT853L,GFXMMU LUT entry 853 low" hexmask.long.byte 0xAA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAAC "GFXMMU_LUT853H,GFXMMU LUT entry 853 high" hexmask.long.tbyte 0xAAC 0.--17. 1. "LO,Line offset" line.long 0xAB0 "GFXMMU_LUT854L,GFXMMU LUT entry 854 low" hexmask.long.byte 0xAB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAB4 "GFXMMU_LUT854H,GFXMMU LUT entry 854 high" hexmask.long.tbyte 0xAB4 0.--17. 1. "LO,Line offset" line.long 0xAB8 "GFXMMU_LUT855L,GFXMMU LUT entry 855 low" hexmask.long.byte 0xAB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xABC "GFXMMU_LUT855H,GFXMMU LUT entry 855 high" hexmask.long.tbyte 0xABC 0.--17. 1. "LO,Line offset" line.long 0xAC0 "GFXMMU_LUT856L,GFXMMU LUT entry 856 low" hexmask.long.byte 0xAC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC4 "GFXMMU_LUT856H,GFXMMU LUT entry 856 high" hexmask.long.tbyte 0xAC4 0.--17. 1. "LO,Line offset" line.long 0xAC8 "GFXMMU_LUT857L,GFXMMU LUT entry 857 low" hexmask.long.byte 0xAC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xACC "GFXMMU_LUT857H,GFXMMU LUT entry 857 high" hexmask.long.tbyte 0xACC 0.--17. 1. "LO,Line offset" line.long 0xAD0 "GFXMMU_LUT858L,GFXMMU LUT entry 858 low" hexmask.long.byte 0xAD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAD4 "GFXMMU_LUT858H,GFXMMU LUT entry 858 high" hexmask.long.tbyte 0xAD4 0.--17. 1. "LO,Line offset" line.long 0xAD8 "GFXMMU_LUT859L,GFXMMU LUT entry 859 low" hexmask.long.byte 0xAD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xADC "GFXMMU_LUT859H,GFXMMU LUT entry 859 high" hexmask.long.tbyte 0xADC 0.--17. 1. "LO,Line offset" line.long 0xAE0 "GFXMMU_LUT860L,GFXMMU LUT entry 860 low" hexmask.long.byte 0xAE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAE4 "GFXMMU_LUT860H,GFXMMU LUT entry 860 high" hexmask.long.tbyte 0xAE4 0.--17. 1. "LO,Line offset" line.long 0xAE8 "GFXMMU_LUT861L,GFXMMU LUT entry 861 low" hexmask.long.byte 0xAE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAEC "GFXMMU_LUT861H,GFXMMU LUT entry 861 high" hexmask.long.tbyte 0xAEC 0.--17. 1. "LO,Line offset" line.long 0xAF0 "GFXMMU_LUT862L,GFXMMU LUT entry 862 low" hexmask.long.byte 0xAF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAF4 "GFXMMU_LUT862H,GFXMMU LUT entry 862 high" hexmask.long.tbyte 0xAF4 0.--17. 1. "LO,Line offset" line.long 0xAF8 "GFXMMU_LUT863L,GFXMMU LUT entry 863 low" hexmask.long.byte 0xAF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAFC "GFXMMU_LUT863H,GFXMMU LUT entry 863 high" hexmask.long.tbyte 0xAFC 0.--17. 1. "LO,Line offset" line.long 0xB00 "GFXMMU_LUT864L,GFXMMU LUT entry 864 low" hexmask.long.byte 0xB00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB00 8.--15. 1. "FVB,First valid block" bitfld.long 0xB00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB04 "GFXMMU_LUT864H,GFXMMU LUT entry 864 high" hexmask.long.tbyte 0xB04 0.--17. 1. "LO,Line offset" line.long 0xB08 "GFXMMU_LUT865L,GFXMMU LUT entry 865 low" hexmask.long.byte 0xB08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB08 8.--15. 1. "FVB,First valid block" bitfld.long 0xB08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB0C "GFXMMU_LUT865H,GFXMMU LUT entry 865 high" hexmask.long.tbyte 0xB0C 0.--17. 1. "LO,Line offset" line.long 0xB10 "GFXMMU_LUT866L,GFXMMU LUT entry 866 low" hexmask.long.byte 0xB10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB10 8.--15. 1. "FVB,First valid block" bitfld.long 0xB10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB14 "GFXMMU_LUT866H,GFXMMU LUT entry 866 high" hexmask.long.tbyte 0xB14 0.--17. 1. "LO,Line offset" line.long 0xB18 "GFXMMU_LUT867L,GFXMMU LUT entry 867 low" hexmask.long.byte 0xB18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB18 8.--15. 1. "FVB,First valid block" bitfld.long 0xB18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB1C "GFXMMU_LUT867H,GFXMMU LUT entry 867 high" hexmask.long.tbyte 0xB1C 0.--17. 1. "LO,Line offset" line.long 0xB20 "GFXMMU_LUT868L,GFXMMU LUT entry 868 low" hexmask.long.byte 0xB20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB20 8.--15. 1. "FVB,First valid block" bitfld.long 0xB20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB24 "GFXMMU_LUT868H,GFXMMU LUT entry 868 high" hexmask.long.tbyte 0xB24 0.--17. 1. "LO,Line offset" line.long 0xB28 "GFXMMU_LUT869L,GFXMMU LUT entry 869 low" hexmask.long.byte 0xB28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB28 8.--15. 1. "FVB,First valid block" bitfld.long 0xB28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB2C "GFXMMU_LUT869H,GFXMMU LUT entry 869 high" hexmask.long.tbyte 0xB2C 0.--17. 1. "LO,Line offset" line.long 0xB30 "GFXMMU_LUT870L,GFXMMU LUT entry 870 low" hexmask.long.byte 0xB30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB30 8.--15. 1. "FVB,First valid block" bitfld.long 0xB30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB34 "GFXMMU_LUT870H,GFXMMU LUT entry 870 high" hexmask.long.tbyte 0xB34 0.--17. 1. "LO,Line offset" line.long 0xB38 "GFXMMU_LUT871L,GFXMMU LUT entry 871 low" hexmask.long.byte 0xB38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB38 8.--15. 1. "FVB,First valid block" bitfld.long 0xB38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB3C "GFXMMU_LUT871H,GFXMMU LUT entry 871 high" hexmask.long.tbyte 0xB3C 0.--17. 1. "LO,Line offset" line.long 0xB40 "GFXMMU_LUT872L,GFXMMU LUT entry 872 low" hexmask.long.byte 0xB40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB40 8.--15. 1. "FVB,First valid block" bitfld.long 0xB40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB44 "GFXMMU_LUT872H,GFXMMU LUT entry 872 high" hexmask.long.tbyte 0xB44 0.--17. 1. "LO,Line offset" line.long 0xB48 "GFXMMU_LUT873L,GFXMMU LUT entry 873 low" hexmask.long.byte 0xB48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB48 8.--15. 1. "FVB,First valid block" bitfld.long 0xB48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4C "GFXMMU_LUT873H,GFXMMU LUT entry 873 high" hexmask.long.tbyte 0xB4C 0.--17. 1. "LO,Line offset" line.long 0xB50 "GFXMMU_LUT874L,GFXMMU LUT entry 874 low" hexmask.long.byte 0xB50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB50 8.--15. 1. "FVB,First valid block" bitfld.long 0xB50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB54 "GFXMMU_LUT874H,GFXMMU LUT entry 874 high" hexmask.long.tbyte 0xB54 0.--17. 1. "LO,Line offset" line.long 0xB58 "GFXMMU_LUT875L,GFXMMU LUT entry 875 low" hexmask.long.byte 0xB58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB58 8.--15. 1. "FVB,First valid block" bitfld.long 0xB58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB5C "GFXMMU_LUT875H,GFXMMU LUT entry 875 high" hexmask.long.tbyte 0xB5C 0.--17. 1. "LO,Line offset" line.long 0xB60 "GFXMMU_LUT876L,GFXMMU LUT entry 876 low" hexmask.long.byte 0xB60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB60 8.--15. 1. "FVB,First valid block" bitfld.long 0xB60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB64 "GFXMMU_LUT876H,GFXMMU LUT entry 876 high" hexmask.long.tbyte 0xB64 0.--17. 1. "LO,Line offset" line.long 0xB68 "GFXMMU_LUT877L,GFXMMU LUT entry 877 low" hexmask.long.byte 0xB68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB68 8.--15. 1. "FVB,First valid block" bitfld.long 0xB68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB6C "GFXMMU_LUT877H,GFXMMU LUT entry 877 high" hexmask.long.tbyte 0xB6C 0.--17. 1. "LO,Line offset" line.long 0xB70 "GFXMMU_LUT878L,GFXMMU LUT entry 878 low" hexmask.long.byte 0xB70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB70 8.--15. 1. "FVB,First valid block" bitfld.long 0xB70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB74 "GFXMMU_LUT878H,GFXMMU LUT entry 878 high" hexmask.long.tbyte 0xB74 0.--17. 1. "LO,Line offset" line.long 0xB78 "GFXMMU_LUT879L,GFXMMU LUT entry 879 low" hexmask.long.byte 0xB78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB78 8.--15. 1. "FVB,First valid block" bitfld.long 0xB78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB7C "GFXMMU_LUT879H,GFXMMU LUT entry 879 high" hexmask.long.tbyte 0xB7C 0.--17. 1. "LO,Line offset" line.long 0xB80 "GFXMMU_LUT880L,GFXMMU LUT entry 880 low" hexmask.long.byte 0xB80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB80 8.--15. 1. "FVB,First valid block" bitfld.long 0xB80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB84 "GFXMMU_LUT880H,GFXMMU LUT entry 880 high" hexmask.long.tbyte 0xB84 0.--17. 1. "LO,Line offset" line.long 0xB88 "GFXMMU_LUT881L,GFXMMU LUT entry 881 low" hexmask.long.byte 0xB88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB88 8.--15. 1. "FVB,First valid block" bitfld.long 0xB88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB8C "GFXMMU_LUT881H,GFXMMU LUT entry 881 high" hexmask.long.tbyte 0xB8C 0.--17. 1. "LO,Line offset" line.long 0xB90 "GFXMMU_LUT882L,GFXMMU LUT entry 882 low" hexmask.long.byte 0xB90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB90 8.--15. 1. "FVB,First valid block" bitfld.long 0xB90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB94 "GFXMMU_LUT882H,GFXMMU LUT entry 882 high" hexmask.long.tbyte 0xB94 0.--17. 1. "LO,Line offset" line.long 0xB98 "GFXMMU_LUT883L,GFXMMU LUT entry 883 low" hexmask.long.byte 0xB98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB98 8.--15. 1. "FVB,First valid block" bitfld.long 0xB98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB9C "GFXMMU_LUT883H,GFXMMU LUT entry 883 high" hexmask.long.tbyte 0xB9C 0.--17. 1. "LO,Line offset" line.long 0xBA0 "GFXMMU_LUT884L,GFXMMU LUT entry 884 low" hexmask.long.byte 0xBA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBA4 "GFXMMU_LUT884H,GFXMMU LUT entry 884 high" hexmask.long.tbyte 0xBA4 0.--17. 1. "LO,Line offset" line.long 0xBA8 "GFXMMU_LUT885L,GFXMMU LUT entry 885 low" hexmask.long.byte 0xBA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBAC "GFXMMU_LUT885H,GFXMMU LUT entry 885 high" hexmask.long.tbyte 0xBAC 0.--17. 1. "LO,Line offset" line.long 0xBB0 "GFXMMU_LUT886L,GFXMMU LUT entry 886 low" hexmask.long.byte 0xBB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBB4 "GFXMMU_LUT886H,GFXMMU LUT entry 886 high" hexmask.long.tbyte 0xBB4 0.--17. 1. "LO,Line offset" line.long 0xBB8 "GFXMMU_LUT887L,GFXMMU LUT entry 887 low" hexmask.long.byte 0xBB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBBC "GFXMMU_LUT887H,GFXMMU LUT entry 887 high" hexmask.long.tbyte 0xBBC 0.--17. 1. "LO,Line offset" line.long 0xBC0 "GFXMMU_LUT888L,GFXMMU LUT entry 888 low" hexmask.long.byte 0xBC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC4 "GFXMMU_LUT888H,GFXMMU LUT entry 888 high" hexmask.long.tbyte 0xBC4 0.--17. 1. "LO,Line offset" line.long 0xBC8 "GFXMMU_LUT889L,GFXMMU LUT entry 889 low" hexmask.long.byte 0xBC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBCC "GFXMMU_LUT889H,GFXMMU LUT entry 889 high" hexmask.long.tbyte 0xBCC 0.--17. 1. "LO,Line offset" line.long 0xBD0 "GFXMMU_LUT890L,GFXMMU LUT entry 890 low" hexmask.long.byte 0xBD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBD4 "GFXMMU_LUT890H,GFXMMU LUT entry 890 high" hexmask.long.tbyte 0xBD4 0.--17. 1. "LO,Line offset" line.long 0xBD8 "GFXMMU_LUT891L,GFXMMU LUT entry 891 low" hexmask.long.byte 0xBD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBDC "GFXMMU_LUT891H,GFXMMU LUT entry 891 high" hexmask.long.tbyte 0xBDC 0.--17. 1. "LO,Line offset" line.long 0xBE0 "GFXMMU_LUT892L,GFXMMU LUT entry 892 low" hexmask.long.byte 0xBE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBE4 "GFXMMU_LUT892H,GFXMMU LUT entry 892 high" hexmask.long.tbyte 0xBE4 0.--17. 1. "LO,Line offset" line.long 0xBE8 "GFXMMU_LUT893L,GFXMMU LUT entry 893 low" hexmask.long.byte 0xBE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBEC "GFXMMU_LUT893H,GFXMMU LUT entry 893 high" hexmask.long.tbyte 0xBEC 0.--17. 1. "LO,Line offset" line.long 0xBF0 "GFXMMU_LUT894L,GFXMMU LUT entry 894 low" hexmask.long.byte 0xBF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBF4 "GFXMMU_LUT894H,GFXMMU LUT entry 894 high" hexmask.long.tbyte 0xBF4 0.--17. 1. "LO,Line offset" line.long 0xBF8 "GFXMMU_LUT895L,GFXMMU LUT entry 895 low" hexmask.long.byte 0xBF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBFC "GFXMMU_LUT895H,GFXMMU LUT entry 895 high" hexmask.long.tbyte 0xBFC 0.--17. 1. "LO,Line offset" line.long 0xC00 "GFXMMU_LUT896L,GFXMMU LUT entry 896 low" hexmask.long.byte 0xC00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC00 8.--15. 1. "FVB,First valid block" bitfld.long 0xC00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC04 "GFXMMU_LUT896H,GFXMMU LUT entry 896 high" hexmask.long.tbyte 0xC04 0.--17. 1. "LO,Line offset" line.long 0xC08 "GFXMMU_LUT897L,GFXMMU LUT entry 897 low" hexmask.long.byte 0xC08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC08 8.--15. 1. "FVB,First valid block" bitfld.long 0xC08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC0C "GFXMMU_LUT897H,GFXMMU LUT entry 897 high" hexmask.long.tbyte 0xC0C 0.--17. 1. "LO,Line offset" line.long 0xC10 "GFXMMU_LUT898L,GFXMMU LUT entry 898 low" hexmask.long.byte 0xC10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC10 8.--15. 1. "FVB,First valid block" bitfld.long 0xC10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC14 "GFXMMU_LUT898H,GFXMMU LUT entry 898 high" hexmask.long.tbyte 0xC14 0.--17. 1. "LO,Line offset" line.long 0xC18 "GFXMMU_LUT899L,GFXMMU LUT entry 899 low" hexmask.long.byte 0xC18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC18 8.--15. 1. "FVB,First valid block" bitfld.long 0xC18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC1C "GFXMMU_LUT899H,GFXMMU LUT entry 899 high" hexmask.long.tbyte 0xC1C 0.--17. 1. "LO,Line offset" line.long 0xC20 "GFXMMU_LUT900L,GFXMMU LUT entry 900 low" hexmask.long.byte 0xC20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC20 8.--15. 1. "FVB,First valid block" bitfld.long 0xC20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC24 "GFXMMU_LUT900H,GFXMMU LUT entry 900 high" hexmask.long.tbyte 0xC24 0.--17. 1. "LO,Line offset" line.long 0xC28 "GFXMMU_LUT901L,GFXMMU LUT entry 901 low" hexmask.long.byte 0xC28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC28 8.--15. 1. "FVB,First valid block" bitfld.long 0xC28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC2C "GFXMMU_LUT901H,GFXMMU LUT entry 901 high" hexmask.long.tbyte 0xC2C 0.--17. 1. "LO,Line offset" line.long 0xC30 "GFXMMU_LUT902L,GFXMMU LUT entry 902 low" hexmask.long.byte 0xC30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC30 8.--15. 1. "FVB,First valid block" bitfld.long 0xC30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC34 "GFXMMU_LUT902H,GFXMMU LUT entry 902 high" hexmask.long.tbyte 0xC34 0.--17. 1. "LO,Line offset" line.long 0xC38 "GFXMMU_LUT903L,GFXMMU LUT entry 903 low" hexmask.long.byte 0xC38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC38 8.--15. 1. "FVB,First valid block" bitfld.long 0xC38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC3C "GFXMMU_LUT903H,GFXMMU LUT entry 903 high" hexmask.long.tbyte 0xC3C 0.--17. 1. "LO,Line offset" line.long 0xC40 "GFXMMU_LUT904L,GFXMMU LUT entry 904 low" hexmask.long.byte 0xC40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC40 8.--15. 1. "FVB,First valid block" bitfld.long 0xC40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC44 "GFXMMU_LUT904H,GFXMMU LUT entry 904 high" hexmask.long.tbyte 0xC44 0.--17. 1. "LO,Line offset" line.long 0xC48 "GFXMMU_LUT905L,GFXMMU LUT entry 905 low" hexmask.long.byte 0xC48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC48 8.--15. 1. "FVB,First valid block" bitfld.long 0xC48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4C "GFXMMU_LUT905H,GFXMMU LUT entry 905 high" hexmask.long.tbyte 0xC4C 0.--17. 1. "LO,Line offset" line.long 0xC50 "GFXMMU_LUT906L,GFXMMU LUT entry 906 low" hexmask.long.byte 0xC50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC50 8.--15. 1. "FVB,First valid block" bitfld.long 0xC50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC54 "GFXMMU_LUT906H,GFXMMU LUT entry 906 high" hexmask.long.tbyte 0xC54 0.--17. 1. "LO,Line offset" line.long 0xC58 "GFXMMU_LUT907L,GFXMMU LUT entry 907 low" hexmask.long.byte 0xC58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC58 8.--15. 1. "FVB,First valid block" bitfld.long 0xC58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC5C "GFXMMU_LUT907H,GFXMMU LUT entry 907 high" hexmask.long.tbyte 0xC5C 0.--17. 1. "LO,Line offset" line.long 0xC60 "GFXMMU_LUT908L,GFXMMU LUT entry 908 low" hexmask.long.byte 0xC60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC60 8.--15. 1. "FVB,First valid block" bitfld.long 0xC60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC64 "GFXMMU_LUT908H,GFXMMU LUT entry 908 high" hexmask.long.tbyte 0xC64 0.--17. 1. "LO,Line offset" line.long 0xC68 "GFXMMU_LUT909L,GFXMMU LUT entry 909 low" hexmask.long.byte 0xC68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC68 8.--15. 1. "FVB,First valid block" bitfld.long 0xC68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC6C "GFXMMU_LUT909H,GFXMMU LUT entry 909 high" hexmask.long.tbyte 0xC6C 0.--17. 1. "LO,Line offset" line.long 0xC70 "GFXMMU_LUT910L,GFXMMU LUT entry 910 low" hexmask.long.byte 0xC70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC70 8.--15. 1. "FVB,First valid block" bitfld.long 0xC70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC74 "GFXMMU_LUT910H,GFXMMU LUT entry 910 high" hexmask.long.tbyte 0xC74 0.--17. 1. "LO,Line offset" line.long 0xC78 "GFXMMU_LUT911L,GFXMMU LUT entry 911 low" hexmask.long.byte 0xC78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC78 8.--15. 1. "FVB,First valid block" bitfld.long 0xC78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC7C "GFXMMU_LUT911H,GFXMMU LUT entry 911 high" hexmask.long.tbyte 0xC7C 0.--17. 1. "LO,Line offset" line.long 0xC80 "GFXMMU_LUT912L,GFXMMU LUT entry 912 low" hexmask.long.byte 0xC80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC80 8.--15. 1. "FVB,First valid block" bitfld.long 0xC80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC84 "GFXMMU_LUT912H,GFXMMU LUT entry 912 high" hexmask.long.tbyte 0xC84 0.--17. 1. "LO,Line offset" line.long 0xC88 "GFXMMU_LUT913L,GFXMMU LUT entry 913 low" hexmask.long.byte 0xC88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC88 8.--15. 1. "FVB,First valid block" bitfld.long 0xC88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC8C "GFXMMU_LUT913H,GFXMMU LUT entry 913 high" hexmask.long.tbyte 0xC8C 0.--17. 1. "LO,Line offset" line.long 0xC90 "GFXMMU_LUT914L,GFXMMU LUT entry 914 low" hexmask.long.byte 0xC90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC90 8.--15. 1. "FVB,First valid block" bitfld.long 0xC90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC94 "GFXMMU_LUT914H,GFXMMU LUT entry 914 high" hexmask.long.tbyte 0xC94 0.--17. 1. "LO,Line offset" line.long 0xC98 "GFXMMU_LUT915L,GFXMMU LUT entry 915 low" hexmask.long.byte 0xC98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC98 8.--15. 1. "FVB,First valid block" bitfld.long 0xC98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC9C "GFXMMU_LUT915H,GFXMMU LUT entry 915 high" hexmask.long.tbyte 0xC9C 0.--17. 1. "LO,Line offset" line.long 0xCA0 "GFXMMU_LUT916L,GFXMMU LUT entry 916 low" hexmask.long.byte 0xCA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCA4 "GFXMMU_LUT916H,GFXMMU LUT entry 916 high" hexmask.long.tbyte 0xCA4 0.--17. 1. "LO,Line offset" line.long 0xCA8 "GFXMMU_LUT917L,GFXMMU LUT entry 917 low" hexmask.long.byte 0xCA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCAC "GFXMMU_LUT917H,GFXMMU LUT entry 917 high" hexmask.long.tbyte 0xCAC 0.--17. 1. "LO,Line offset" line.long 0xCB0 "GFXMMU_LUT918L,GFXMMU LUT entry 918 low" hexmask.long.byte 0xCB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCB4 "GFXMMU_LUT918H,GFXMMU LUT entry 918 high" hexmask.long.tbyte 0xCB4 0.--17. 1. "LO,Line offset" line.long 0xCB8 "GFXMMU_LUT919L,GFXMMU LUT entry 919 low" hexmask.long.byte 0xCB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCBC "GFXMMU_LUT919H,GFXMMU LUT entry 919 high" hexmask.long.tbyte 0xCBC 0.--17. 1. "LO,Line offset" line.long 0xCC0 "GFXMMU_LUT920L,GFXMMU LUT entry 920 low" hexmask.long.byte 0xCC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC4 "GFXMMU_LUT920H,GFXMMU LUT entry 920 high" hexmask.long.tbyte 0xCC4 0.--17. 1. "LO,Line offset" line.long 0xCC8 "GFXMMU_LUT921L,GFXMMU LUT entry 921 low" hexmask.long.byte 0xCC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCCC "GFXMMU_LUT921H,GFXMMU LUT entry 921 high" hexmask.long.tbyte 0xCCC 0.--17. 1. "LO,Line offset" line.long 0xCD0 "GFXMMU_LUT922L,GFXMMU LUT entry 922 low" hexmask.long.byte 0xCD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCD4 "GFXMMU_LUT922H,GFXMMU LUT entry 922 high" hexmask.long.tbyte 0xCD4 0.--17. 1. "LO,Line offset" line.long 0xCD8 "GFXMMU_LUT923L,GFXMMU LUT entry 923 low" hexmask.long.byte 0xCD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCDC "GFXMMU_LUT923H,GFXMMU LUT entry 923 high" hexmask.long.tbyte 0xCDC 0.--17. 1. "LO,Line offset" line.long 0xCE0 "GFXMMU_LUT924L,GFXMMU LUT entry 924 low" hexmask.long.byte 0xCE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCE4 "GFXMMU_LUT924H,GFXMMU LUT entry 924 high" hexmask.long.tbyte 0xCE4 0.--17. 1. "LO,Line offset" line.long 0xCE8 "GFXMMU_LUT925L,GFXMMU LUT entry 925 low" hexmask.long.byte 0xCE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCEC "GFXMMU_LUT925H,GFXMMU LUT entry 925 high" hexmask.long.tbyte 0xCEC 0.--17. 1. "LO,Line offset" line.long 0xCF0 "GFXMMU_LUT926L,GFXMMU LUT entry 926 low" hexmask.long.byte 0xCF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCF4 "GFXMMU_LUT926H,GFXMMU LUT entry 926 high" hexmask.long.tbyte 0xCF4 0.--17. 1. "LO,Line offset" line.long 0xCF8 "GFXMMU_LUT927L,GFXMMU LUT entry 927 low" hexmask.long.byte 0xCF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCFC "GFXMMU_LUT927H,GFXMMU LUT entry 927 high" hexmask.long.tbyte 0xCFC 0.--17. 1. "LO,Line offset" line.long 0xD00 "GFXMMU_LUT928L,GFXMMU LUT entry 928 low" hexmask.long.byte 0xD00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD00 8.--15. 1. "FVB,First valid block" bitfld.long 0xD00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD04 "GFXMMU_LUT928H,GFXMMU LUT entry 928 high" hexmask.long.tbyte 0xD04 0.--17. 1. "LO,Line offset" line.long 0xD08 "GFXMMU_LUT929L,GFXMMU LUT entry 929 low" hexmask.long.byte 0xD08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD08 8.--15. 1. "FVB,First valid block" bitfld.long 0xD08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD0C "GFXMMU_LUT929H,GFXMMU LUT entry 929 high" hexmask.long.tbyte 0xD0C 0.--17. 1. "LO,Line offset" line.long 0xD10 "GFXMMU_LUT930L,GFXMMU LUT entry 930 low" hexmask.long.byte 0xD10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD10 8.--15. 1. "FVB,First valid block" bitfld.long 0xD10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD14 "GFXMMU_LUT930H,GFXMMU LUT entry 930 high" hexmask.long.tbyte 0xD14 0.--17. 1. "LO,Line offset" line.long 0xD18 "GFXMMU_LUT931L,GFXMMU LUT entry 931 low" hexmask.long.byte 0xD18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD18 8.--15. 1. "FVB,First valid block" bitfld.long 0xD18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD1C "GFXMMU_LUT931H,GFXMMU LUT entry 931 high" hexmask.long.tbyte 0xD1C 0.--17. 1. "LO,Line offset" line.long 0xD20 "GFXMMU_LUT932L,GFXMMU LUT entry 932 low" hexmask.long.byte 0xD20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD20 8.--15. 1. "FVB,First valid block" bitfld.long 0xD20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD24 "GFXMMU_LUT932H,GFXMMU LUT entry 932 high" hexmask.long.tbyte 0xD24 0.--17. 1. "LO,Line offset" line.long 0xD28 "GFXMMU_LUT933L,GFXMMU LUT entry 933 low" hexmask.long.byte 0xD28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD28 8.--15. 1. "FVB,First valid block" bitfld.long 0xD28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD2C "GFXMMU_LUT933H,GFXMMU LUT entry 933 high" hexmask.long.tbyte 0xD2C 0.--17. 1. "LO,Line offset" line.long 0xD30 "GFXMMU_LUT934L,GFXMMU LUT entry 934 low" hexmask.long.byte 0xD30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD30 8.--15. 1. "FVB,First valid block" bitfld.long 0xD30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD34 "GFXMMU_LUT934H,GFXMMU LUT entry 934 high" hexmask.long.tbyte 0xD34 0.--17. 1. "LO,Line offset" line.long 0xD38 "GFXMMU_LUT935L,GFXMMU LUT entry 935 low" hexmask.long.byte 0xD38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD38 8.--15. 1. "FVB,First valid block" bitfld.long 0xD38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD3C "GFXMMU_LUT935H,GFXMMU LUT entry 935 high" hexmask.long.tbyte 0xD3C 0.--17. 1. "LO,Line offset" line.long 0xD40 "GFXMMU_LUT936L,GFXMMU LUT entry 936 low" hexmask.long.byte 0xD40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD40 8.--15. 1. "FVB,First valid block" bitfld.long 0xD40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD44 "GFXMMU_LUT936H,GFXMMU LUT entry 936 high" hexmask.long.tbyte 0xD44 0.--17. 1. "LO,Line offset" line.long 0xD48 "GFXMMU_LUT937L,GFXMMU LUT entry 937 low" hexmask.long.byte 0xD48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD48 8.--15. 1. "FVB,First valid block" bitfld.long 0xD48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4C "GFXMMU_LUT937H,GFXMMU LUT entry 937 high" hexmask.long.tbyte 0xD4C 0.--17. 1. "LO,Line offset" line.long 0xD50 "GFXMMU_LUT938L,GFXMMU LUT entry 938 low" hexmask.long.byte 0xD50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD50 8.--15. 1. "FVB,First valid block" bitfld.long 0xD50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD54 "GFXMMU_LUT938H,GFXMMU LUT entry 938 high" hexmask.long.tbyte 0xD54 0.--17. 1. "LO,Line offset" line.long 0xD58 "GFXMMU_LUT939L,GFXMMU LUT entry 939 low" hexmask.long.byte 0xD58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD58 8.--15. 1. "FVB,First valid block" bitfld.long 0xD58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD5C "GFXMMU_LUT939H,GFXMMU LUT entry 939 high" hexmask.long.tbyte 0xD5C 0.--17. 1. "LO,Line offset" line.long 0xD60 "GFXMMU_LUT940L,GFXMMU LUT entry 940 low" hexmask.long.byte 0xD60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD60 8.--15. 1. "FVB,First valid block" bitfld.long 0xD60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD64 "GFXMMU_LUT940H,GFXMMU LUT entry 940 high" hexmask.long.tbyte 0xD64 0.--17. 1. "LO,Line offset" line.long 0xD68 "GFXMMU_LUT941L,GFXMMU LUT entry 941 low" hexmask.long.byte 0xD68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD68 8.--15. 1. "FVB,First valid block" bitfld.long 0xD68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD6C "GFXMMU_LUT941H,GFXMMU LUT entry 941 high" hexmask.long.tbyte 0xD6C 0.--17. 1. "LO,Line offset" line.long 0xD70 "GFXMMU_LUT942L,GFXMMU LUT entry 942 low" hexmask.long.byte 0xD70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD70 8.--15. 1. "FVB,First valid block" bitfld.long 0xD70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD74 "GFXMMU_LUT942H,GFXMMU LUT entry 942 high" hexmask.long.tbyte 0xD74 0.--17. 1. "LO,Line offset" line.long 0xD78 "GFXMMU_LUT943L,GFXMMU LUT entry 943 low" hexmask.long.byte 0xD78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD78 8.--15. 1. "FVB,First valid block" bitfld.long 0xD78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD7C "GFXMMU_LUT943H,GFXMMU LUT entry 943 high" hexmask.long.tbyte 0xD7C 0.--17. 1. "LO,Line offset" line.long 0xD80 "GFXMMU_LUT944L,GFXMMU LUT entry 944 low" hexmask.long.byte 0xD80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD80 8.--15. 1. "FVB,First valid block" bitfld.long 0xD80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD84 "GFXMMU_LUT944H,GFXMMU LUT entry 944 high" hexmask.long.tbyte 0xD84 0.--17. 1. "LO,Line offset" line.long 0xD88 "GFXMMU_LUT945L,GFXMMU LUT entry 945 low" hexmask.long.byte 0xD88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD88 8.--15. 1. "FVB,First valid block" bitfld.long 0xD88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD8C "GFXMMU_LUT945H,GFXMMU LUT entry 945 high" hexmask.long.tbyte 0xD8C 0.--17. 1. "LO,Line offset" line.long 0xD90 "GFXMMU_LUT946L,GFXMMU LUT entry 946 low" hexmask.long.byte 0xD90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD90 8.--15. 1. "FVB,First valid block" bitfld.long 0xD90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD94 "GFXMMU_LUT946H,GFXMMU LUT entry 946 high" hexmask.long.tbyte 0xD94 0.--17. 1. "LO,Line offset" line.long 0xD98 "GFXMMU_LUT947L,GFXMMU LUT entry 947 low" hexmask.long.byte 0xD98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD98 8.--15. 1. "FVB,First valid block" bitfld.long 0xD98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD9C "GFXMMU_LUT947H,GFXMMU LUT entry 947 high" hexmask.long.tbyte 0xD9C 0.--17. 1. "LO,Line offset" line.long 0xDA0 "GFXMMU_LUT948L,GFXMMU LUT entry 948 low" hexmask.long.byte 0xDA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDA4 "GFXMMU_LUT948H,GFXMMU LUT entry 948 high" hexmask.long.tbyte 0xDA4 0.--17. 1. "LO,Line offset" line.long 0xDA8 "GFXMMU_LUT949L,GFXMMU LUT entry 949 low" hexmask.long.byte 0xDA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDAC "GFXMMU_LUT949H,GFXMMU LUT entry 949 high" hexmask.long.tbyte 0xDAC 0.--17. 1. "LO,Line offset" line.long 0xDB0 "GFXMMU_LUT950L,GFXMMU LUT entry 950 low" hexmask.long.byte 0xDB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDB4 "GFXMMU_LUT950H,GFXMMU LUT entry 950 high" hexmask.long.tbyte 0xDB4 0.--17. 1. "LO,Line offset" line.long 0xDB8 "GFXMMU_LUT951L,GFXMMU LUT entry 951 low" hexmask.long.byte 0xDB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDBC "GFXMMU_LUT951H,GFXMMU LUT entry 951 high" hexmask.long.tbyte 0xDBC 0.--17. 1. "LO,Line offset" line.long 0xDC0 "GFXMMU_LUT952L,GFXMMU LUT entry 952 low" hexmask.long.byte 0xDC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC4 "GFXMMU_LUT952H,GFXMMU LUT entry 952 high" hexmask.long.tbyte 0xDC4 0.--17. 1. "LO,Line offset" line.long 0xDC8 "GFXMMU_LUT953L,GFXMMU LUT entry 953 low" hexmask.long.byte 0xDC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDCC "GFXMMU_LUT953H,GFXMMU LUT entry 953 high" hexmask.long.tbyte 0xDCC 0.--17. 1. "LO,Line offset" line.long 0xDD0 "GFXMMU_LUT954L,GFXMMU LUT entry 954 low" hexmask.long.byte 0xDD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDD4 "GFXMMU_LUT954H,GFXMMU LUT entry 954 high" hexmask.long.tbyte 0xDD4 0.--17. 1. "LO,Line offset" line.long 0xDD8 "GFXMMU_LUT955L,GFXMMU LUT entry 955 low" hexmask.long.byte 0xDD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDDC "GFXMMU_LUT955H,GFXMMU LUT entry 955 high" hexmask.long.tbyte 0xDDC 0.--17. 1. "LO,Line offset" line.long 0xDE0 "GFXMMU_LUT956L,GFXMMU LUT entry 956 low" hexmask.long.byte 0xDE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDE4 "GFXMMU_LUT956H,GFXMMU LUT entry 956 high" hexmask.long.tbyte 0xDE4 0.--17. 1. "LO,Line offset" line.long 0xDE8 "GFXMMU_LUT957L,GFXMMU LUT entry 957 low" hexmask.long.byte 0xDE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDEC "GFXMMU_LUT957H,GFXMMU LUT entry 957 high" hexmask.long.tbyte 0xDEC 0.--17. 1. "LO,Line offset" line.long 0xDF0 "GFXMMU_LUT958L,GFXMMU LUT entry 958 low" hexmask.long.byte 0xDF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDF4 "GFXMMU_LUT958H,GFXMMU LUT entry 958 high" hexmask.long.tbyte 0xDF4 0.--17. 1. "LO,Line offset" line.long 0xDF8 "GFXMMU_LUT959L,GFXMMU LUT entry 959 low" hexmask.long.byte 0xDF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDFC "GFXMMU_LUT959H,GFXMMU LUT entry 959 high" hexmask.long.tbyte 0xDFC 0.--17. 1. "LO,Line offset" line.long 0xE00 "GFXMMU_LUT960L,GFXMMU LUT entry 960 low" hexmask.long.byte 0xE00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE00 8.--15. 1. "FVB,First valid block" bitfld.long 0xE00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE04 "GFXMMU_LUT960H,GFXMMU LUT entry 960 high" hexmask.long.tbyte 0xE04 0.--17. 1. "LO,Line offset" line.long 0xE08 "GFXMMU_LUT961L,GFXMMU LUT entry 961 low" hexmask.long.byte 0xE08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE08 8.--15. 1. "FVB,First valid block" bitfld.long 0xE08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE0C "GFXMMU_LUT961H,GFXMMU LUT entry 961 high" hexmask.long.tbyte 0xE0C 0.--17. 1. "LO,Line offset" line.long 0xE10 "GFXMMU_LUT962L,GFXMMU LUT entry 962 low" hexmask.long.byte 0xE10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE10 8.--15. 1. "FVB,First valid block" bitfld.long 0xE10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE14 "GFXMMU_LUT962H,GFXMMU LUT entry 962 high" hexmask.long.tbyte 0xE14 0.--17. 1. "LO,Line offset" line.long 0xE18 "GFXMMU_LUT963L,GFXMMU LUT entry 963 low" hexmask.long.byte 0xE18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE18 8.--15. 1. "FVB,First valid block" bitfld.long 0xE18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE1C "GFXMMU_LUT963H,GFXMMU LUT entry 963 high" hexmask.long.tbyte 0xE1C 0.--17. 1. "LO,Line offset" line.long 0xE20 "GFXMMU_LUT964L,GFXMMU LUT entry 964 low" hexmask.long.byte 0xE20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE20 8.--15. 1. "FVB,First valid block" bitfld.long 0xE20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE24 "GFXMMU_LUT964H,GFXMMU LUT entry 964 high" hexmask.long.tbyte 0xE24 0.--17. 1. "LO,Line offset" line.long 0xE28 "GFXMMU_LUT965L,GFXMMU LUT entry 965 low" hexmask.long.byte 0xE28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE28 8.--15. 1. "FVB,First valid block" bitfld.long 0xE28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE2C "GFXMMU_LUT965H,GFXMMU LUT entry 965 high" hexmask.long.tbyte 0xE2C 0.--17. 1. "LO,Line offset" line.long 0xE30 "GFXMMU_LUT966L,GFXMMU LUT entry 966 low" hexmask.long.byte 0xE30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE30 8.--15. 1. "FVB,First valid block" bitfld.long 0xE30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE34 "GFXMMU_LUT966H,GFXMMU LUT entry 966 high" hexmask.long.tbyte 0xE34 0.--17. 1. "LO,Line offset" line.long 0xE38 "GFXMMU_LUT967L,GFXMMU LUT entry 967 low" hexmask.long.byte 0xE38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE38 8.--15. 1. "FVB,First valid block" bitfld.long 0xE38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE3C "GFXMMU_LUT967H,GFXMMU LUT entry 967 high" hexmask.long.tbyte 0xE3C 0.--17. 1. "LO,Line offset" line.long 0xE40 "GFXMMU_LUT968L,GFXMMU LUT entry 968 low" hexmask.long.byte 0xE40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE40 8.--15. 1. "FVB,First valid block" bitfld.long 0xE40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE44 "GFXMMU_LUT968H,GFXMMU LUT entry 968 high" hexmask.long.tbyte 0xE44 0.--17. 1. "LO,Line offset" line.long 0xE48 "GFXMMU_LUT969L,GFXMMU LUT entry 969 low" hexmask.long.byte 0xE48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE48 8.--15. 1. "FVB,First valid block" bitfld.long 0xE48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4C "GFXMMU_LUT969H,GFXMMU LUT entry 969 high" hexmask.long.tbyte 0xE4C 0.--17. 1. "LO,Line offset" line.long 0xE50 "GFXMMU_LUT970L,GFXMMU LUT entry 970 low" hexmask.long.byte 0xE50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE50 8.--15. 1. "FVB,First valid block" bitfld.long 0xE50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE54 "GFXMMU_LUT970H,GFXMMU LUT entry 970 high" hexmask.long.tbyte 0xE54 0.--17. 1. "LO,Line offset" line.long 0xE58 "GFXMMU_LUT971L,GFXMMU LUT entry 971 low" hexmask.long.byte 0xE58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE58 8.--15. 1. "FVB,First valid block" bitfld.long 0xE58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE5C "GFXMMU_LUT971H,GFXMMU LUT entry 971 high" hexmask.long.tbyte 0xE5C 0.--17. 1. "LO,Line offset" line.long 0xE60 "GFXMMU_LUT972L,GFXMMU LUT entry 972 low" hexmask.long.byte 0xE60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE60 8.--15. 1. "FVB,First valid block" bitfld.long 0xE60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE64 "GFXMMU_LUT972H,GFXMMU LUT entry 972 high" hexmask.long.tbyte 0xE64 0.--17. 1. "LO,Line offset" line.long 0xE68 "GFXMMU_LUT973L,GFXMMU LUT entry 973 low" hexmask.long.byte 0xE68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE68 8.--15. 1. "FVB,First valid block" bitfld.long 0xE68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE6C "GFXMMU_LUT973H,GFXMMU LUT entry 973 high" hexmask.long.tbyte 0xE6C 0.--17. 1. "LO,Line offset" line.long 0xE70 "GFXMMU_LUT974L,GFXMMU LUT entry 974 low" hexmask.long.byte 0xE70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE70 8.--15. 1. "FVB,First valid block" bitfld.long 0xE70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE74 "GFXMMU_LUT974H,GFXMMU LUT entry 974 high" hexmask.long.tbyte 0xE74 0.--17. 1. "LO,Line offset" line.long 0xE78 "GFXMMU_LUT975L,GFXMMU LUT entry 975 low" hexmask.long.byte 0xE78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE78 8.--15. 1. "FVB,First valid block" bitfld.long 0xE78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE7C "GFXMMU_LUT975H,GFXMMU LUT entry 975 high" hexmask.long.tbyte 0xE7C 0.--17. 1. "LO,Line offset" line.long 0xE80 "GFXMMU_LUT976L,GFXMMU LUT entry 976 low" hexmask.long.byte 0xE80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE80 8.--15. 1. "FVB,First valid block" bitfld.long 0xE80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE84 "GFXMMU_LUT976H,GFXMMU LUT entry 976 high" hexmask.long.tbyte 0xE84 0.--17. 1. "LO,Line offset" line.long 0xE88 "GFXMMU_LUT977L,GFXMMU LUT entry 977 low" hexmask.long.byte 0xE88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE88 8.--15. 1. "FVB,First valid block" bitfld.long 0xE88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE8C "GFXMMU_LUT977H,GFXMMU LUT entry 977 high" hexmask.long.tbyte 0xE8C 0.--17. 1. "LO,Line offset" line.long 0xE90 "GFXMMU_LUT978L,GFXMMU LUT entry 978 low" hexmask.long.byte 0xE90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE90 8.--15. 1. "FVB,First valid block" bitfld.long 0xE90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE94 "GFXMMU_LUT978H,GFXMMU LUT entry 978 high" hexmask.long.tbyte 0xE94 0.--17. 1. "LO,Line offset" line.long 0xE98 "GFXMMU_LUT979L,GFXMMU LUT entry 979 low" hexmask.long.byte 0xE98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE98 8.--15. 1. "FVB,First valid block" bitfld.long 0xE98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE9C "GFXMMU_LUT979H,GFXMMU LUT entry 979 high" hexmask.long.tbyte 0xE9C 0.--17. 1. "LO,Line offset" line.long 0xEA0 "GFXMMU_LUT980L,GFXMMU LUT entry 980 low" hexmask.long.byte 0xEA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEA4 "GFXMMU_LUT980H,GFXMMU LUT entry 980 high" hexmask.long.tbyte 0xEA4 0.--17. 1. "LO,Line offset" line.long 0xEA8 "GFXMMU_LUT981L,GFXMMU LUT entry 981 low" hexmask.long.byte 0xEA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEAC "GFXMMU_LUT981H,GFXMMU LUT entry 981 high" hexmask.long.tbyte 0xEAC 0.--17. 1. "LO,Line offset" line.long 0xEB0 "GFXMMU_LUT982L,GFXMMU LUT entry 982 low" hexmask.long.byte 0xEB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEB4 "GFXMMU_LUT982H,GFXMMU LUT entry 982 high" hexmask.long.tbyte 0xEB4 0.--17. 1. "LO,Line offset" line.long 0xEB8 "GFXMMU_LUT983L,GFXMMU LUT entry 983 low" hexmask.long.byte 0xEB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEBC "GFXMMU_LUT983H,GFXMMU LUT entry 983 high" hexmask.long.tbyte 0xEBC 0.--17. 1. "LO,Line offset" line.long 0xEC0 "GFXMMU_LUT984L,GFXMMU LUT entry 984 low" hexmask.long.byte 0xEC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC4 "GFXMMU_LUT984H,GFXMMU LUT entry 984 high" hexmask.long.tbyte 0xEC4 0.--17. 1. "LO,Line offset" line.long 0xEC8 "GFXMMU_LUT985L,GFXMMU LUT entry 985 low" hexmask.long.byte 0xEC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xECC "GFXMMU_LUT985H,GFXMMU LUT entry 985 high" hexmask.long.tbyte 0xECC 0.--17. 1. "LO,Line offset" line.long 0xED0 "GFXMMU_LUT986L,GFXMMU LUT entry 986 low" hexmask.long.byte 0xED0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xED0 8.--15. 1. "FVB,First valid block" bitfld.long 0xED0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xED4 "GFXMMU_LUT986H,GFXMMU LUT entry 986 high" hexmask.long.tbyte 0xED4 0.--17. 1. "LO,Line offset" line.long 0xED8 "GFXMMU_LUT987L,GFXMMU LUT entry 987 low" hexmask.long.byte 0xED8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xED8 8.--15. 1. "FVB,First valid block" bitfld.long 0xED8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEDC "GFXMMU_LUT987H,GFXMMU LUT entry 987 high" hexmask.long.tbyte 0xEDC 0.--17. 1. "LO,Line offset" line.long 0xEE0 "GFXMMU_LUT988L,GFXMMU LUT entry 988 low" hexmask.long.byte 0xEE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEE4 "GFXMMU_LUT988H,GFXMMU LUT entry 988 high" hexmask.long.tbyte 0xEE4 0.--17. 1. "LO,Line offset" line.long 0xEE8 "GFXMMU_LUT989L,GFXMMU LUT entry 989 low" hexmask.long.byte 0xEE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEEC "GFXMMU_LUT989H,GFXMMU LUT entry 989 high" hexmask.long.tbyte 0xEEC 0.--17. 1. "LO,Line offset" line.long 0xEF0 "GFXMMU_LUT990L,GFXMMU LUT entry 990 low" hexmask.long.byte 0xEF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEF4 "GFXMMU_LUT990H,GFXMMU LUT entry 990 high" hexmask.long.tbyte 0xEF4 0.--17. 1. "LO,Line offset" line.long 0xEF8 "GFXMMU_LUT991L,GFXMMU LUT entry 991 low" hexmask.long.byte 0xEF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEFC "GFXMMU_LUT991H,GFXMMU LUT entry 991 high" hexmask.long.tbyte 0xEFC 0.--17. 1. "LO,Line offset" line.long 0xF00 "GFXMMU_LUT992L,GFXMMU LUT entry 992 low" hexmask.long.byte 0xF00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF00 8.--15. 1. "FVB,First valid block" bitfld.long 0xF00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF04 "GFXMMU_LUT992H,GFXMMU LUT entry 992 high" hexmask.long.tbyte 0xF04 0.--17. 1. "LO,Line offset" line.long 0xF08 "GFXMMU_LUT993L,GFXMMU LUT entry 993 low" hexmask.long.byte 0xF08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF08 8.--15. 1. "FVB,First valid block" bitfld.long 0xF08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF0C "GFXMMU_LUT993H,GFXMMU LUT entry 993 high" hexmask.long.tbyte 0xF0C 0.--17. 1. "LO,Line offset" line.long 0xF10 "GFXMMU_LUT994L,GFXMMU LUT entry 994 low" hexmask.long.byte 0xF10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF10 8.--15. 1. "FVB,First valid block" bitfld.long 0xF10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF14 "GFXMMU_LUT994H,GFXMMU LUT entry 994 high" hexmask.long.tbyte 0xF14 0.--17. 1. "LO,Line offset" line.long 0xF18 "GFXMMU_LUT995L,GFXMMU LUT entry 995 low" hexmask.long.byte 0xF18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF18 8.--15. 1. "FVB,First valid block" bitfld.long 0xF18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF1C "GFXMMU_LUT995H,GFXMMU LUT entry 995 high" hexmask.long.tbyte 0xF1C 0.--17. 1. "LO,Line offset" line.long 0xF20 "GFXMMU_LUT996L,GFXMMU LUT entry 996 low" hexmask.long.byte 0xF20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF20 8.--15. 1. "FVB,First valid block" bitfld.long 0xF20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF24 "GFXMMU_LUT996H,GFXMMU LUT entry 996 high" hexmask.long.tbyte 0xF24 0.--17. 1. "LO,Line offset" line.long 0xF28 "GFXMMU_LUT997L,GFXMMU LUT entry 997 low" hexmask.long.byte 0xF28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF28 8.--15. 1. "FVB,First valid block" bitfld.long 0xF28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF2C "GFXMMU_LUT997H,GFXMMU LUT entry 997 high" hexmask.long.tbyte 0xF2C 0.--17. 1. "LO,Line offset" line.long 0xF30 "GFXMMU_LUT998L,GFXMMU LUT entry 998 low" hexmask.long.byte 0xF30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF30 8.--15. 1. "FVB,First valid block" bitfld.long 0xF30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF34 "GFXMMU_LUT998H,GFXMMU LUT entry 998 high" hexmask.long.tbyte 0xF34 0.--17. 1. "LO,Line offset" line.long 0xF38 "GFXMMU_LUT999L,GFXMMU LUT entry 999 low" hexmask.long.byte 0xF38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF38 8.--15. 1. "FVB,First valid block" bitfld.long 0xF38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF3C "GFXMMU_LUT999H,GFXMMU LUT entry 999 high" hexmask.long.tbyte 0xF3C 0.--17. 1. "LO,Line offset" line.long 0xF40 "GFXMMU_LUT1000L,GFXMMU LUT entry 1000 low" hexmask.long.byte 0xF40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF40 8.--15. 1. "FVB,First valid block" bitfld.long 0xF40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF44 "GFXMMU_LUT1000H,GFXMMU LUT entry 1000 high" hexmask.long.tbyte 0xF44 0.--17. 1. "LO,Line offset" line.long 0xF48 "GFXMMU_LUT1001L,GFXMMU LUT entry 1001 low" hexmask.long.byte 0xF48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF48 8.--15. 1. "FVB,First valid block" bitfld.long 0xF48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4C "GFXMMU_LUT1001H,GFXMMU LUT entry 1001 high" hexmask.long.tbyte 0xF4C 0.--17. 1. "LO,Line offset" line.long 0xF50 "GFXMMU_LUT1002L,GFXMMU LUT entry 1002 low" hexmask.long.byte 0xF50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF50 8.--15. 1. "FVB,First valid block" bitfld.long 0xF50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF54 "GFXMMU_LUT1002H,GFXMMU LUT entry 1002 high" hexmask.long.tbyte 0xF54 0.--17. 1. "LO,Line offset" line.long 0xF58 "GFXMMU_LUT1003L,GFXMMU LUT entry 1003 low" hexmask.long.byte 0xF58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF58 8.--15. 1. "FVB,First valid block" bitfld.long 0xF58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF5C "GFXMMU_LUT1003H,GFXMMU LUT entry 1003 high" hexmask.long.tbyte 0xF5C 0.--17. 1. "LO,Line offset" line.long 0xF60 "GFXMMU_LUT1004L,GFXMMU LUT entry 1004 low" hexmask.long.byte 0xF60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF60 8.--15. 1. "FVB,First valid block" bitfld.long 0xF60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF64 "GFXMMU_LUT1004H,GFXMMU LUT entry 1004 high" hexmask.long.tbyte 0xF64 0.--17. 1. "LO,Line offset" line.long 0xF68 "GFXMMU_LUT1005L,GFXMMU LUT entry 1005 low" hexmask.long.byte 0xF68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF68 8.--15. 1. "FVB,First valid block" bitfld.long 0xF68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF6C "GFXMMU_LUT1005H,GFXMMU LUT entry 1005 high" hexmask.long.tbyte 0xF6C 0.--17. 1. "LO,Line offset" line.long 0xF70 "GFXMMU_LUT1006L,GFXMMU LUT entry 1006 low" hexmask.long.byte 0xF70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF70 8.--15. 1. "FVB,First valid block" bitfld.long 0xF70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF74 "GFXMMU_LUT1006H,GFXMMU LUT entry 1006 high" hexmask.long.tbyte 0xF74 0.--17. 1. "LO,Line offset" line.long 0xF78 "GFXMMU_LUT1007L,GFXMMU LUT entry 1007 low" hexmask.long.byte 0xF78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF78 8.--15. 1. "FVB,First valid block" bitfld.long 0xF78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF7C "GFXMMU_LUT1007H,GFXMMU LUT entry 1007 high" hexmask.long.tbyte 0xF7C 0.--17. 1. "LO,Line offset" line.long 0xF80 "GFXMMU_LUT1008L,GFXMMU LUT entry 1008 low" hexmask.long.byte 0xF80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF80 8.--15. 1. "FVB,First valid block" bitfld.long 0xF80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF84 "GFXMMU_LUT1008H,GFXMMU LUT entry 1008 high" hexmask.long.tbyte 0xF84 0.--17. 1. "LO,Line offset" line.long 0xF88 "GFXMMU_LUT1009L,GFXMMU LUT entry 1009 low" hexmask.long.byte 0xF88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF88 8.--15. 1. "FVB,First valid block" bitfld.long 0xF88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF8C "GFXMMU_LUT1009H,GFXMMU LUT entry 1009 high" hexmask.long.tbyte 0xF8C 0.--17. 1. "LO,Line offset" line.long 0xF90 "GFXMMU_LUT1010L,GFXMMU LUT entry 1010 low" hexmask.long.byte 0xF90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF90 8.--15. 1. "FVB,First valid block" bitfld.long 0xF90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF94 "GFXMMU_LUT1010H,GFXMMU LUT entry 1010 high" hexmask.long.tbyte 0xF94 0.--17. 1. "LO,Line offset" line.long 0xF98 "GFXMMU_LUT1011L,GFXMMU LUT entry 1011 low" hexmask.long.byte 0xF98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF98 8.--15. 1. "FVB,First valid block" bitfld.long 0xF98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF9C "GFXMMU_LUT1011H,GFXMMU LUT entry 1011 high" hexmask.long.tbyte 0xF9C 0.--17. 1. "LO,Line offset" line.long 0xFA0 "GFXMMU_LUT1012L,GFXMMU LUT entry 1012 low" hexmask.long.byte 0xFA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFA4 "GFXMMU_LUT1012H,GFXMMU LUT entry 1012 high" hexmask.long.tbyte 0xFA4 0.--17. 1. "LO,Line offset" line.long 0xFA8 "GFXMMU_LUT1013L,GFXMMU LUT entry 1013 low" hexmask.long.byte 0xFA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFAC "GFXMMU_LUT1013H,GFXMMU LUT entry 1013 high" hexmask.long.tbyte 0xFAC 0.--17. 1. "LO,Line offset" line.long 0xFB0 "GFXMMU_LUT1014L,GFXMMU LUT entry 1014 low" hexmask.long.byte 0xFB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFB4 "GFXMMU_LUT1014H,GFXMMU LUT entry 1014 high" hexmask.long.tbyte 0xFB4 0.--17. 1. "LO,Line offset" line.long 0xFB8 "GFXMMU_LUT1015L,GFXMMU LUT entry 1015 low" hexmask.long.byte 0xFB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFBC "GFXMMU_LUT1015H,GFXMMU LUT entry 1015 high" hexmask.long.tbyte 0xFBC 0.--17. 1. "LO,Line offset" line.long 0xFC0 "GFXMMU_LUT1016L,GFXMMU LUT entry 1016 low" hexmask.long.byte 0xFC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC4 "GFXMMU_LUT1016H,GFXMMU LUT entry 1016 high" hexmask.long.tbyte 0xFC4 0.--17. 1. "LO,Line offset" line.long 0xFC8 "GFXMMU_LUT1017L,GFXMMU LUT entry 1017 low" hexmask.long.byte 0xFC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFCC "GFXMMU_LUT1017H,GFXMMU LUT entry 1017 high" hexmask.long.tbyte 0xFCC 0.--17. 1. "LO,Line offset" line.long 0xFD0 "GFXMMU_LUT1018L,GFXMMU LUT entry 1018 low" hexmask.long.byte 0xFD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFD4 "GFXMMU_LUT1018H,GFXMMU LUT entry 1018 high" hexmask.long.tbyte 0xFD4 0.--17. 1. "LO,Line offset" line.long 0xFD8 "GFXMMU_LUT1019L,GFXMMU LUT entry 1019 low" hexmask.long.byte 0xFD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFDC "GFXMMU_LUT1019H,GFXMMU LUT entry 1019 high" hexmask.long.tbyte 0xFDC 0.--17. 1. "LO,Line offset" line.long 0xFE0 "GFXMMU_LUT1020L,GFXMMU LUT entry 1020 low" hexmask.long.byte 0xFE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFE4 "GFXMMU_LUT1020H,GFXMMU LUT entry 1020 high" hexmask.long.tbyte 0xFE4 0.--17. 1. "LO,Line offset" line.long 0xFE8 "GFXMMU_LUT1021L,GFXMMU LUT entry 1021 low" hexmask.long.byte 0xFE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFEC "GFXMMU_LUT1021H,GFXMMU LUT entry 1021 high" hexmask.long.tbyte 0xFEC 0.--17. 1. "LO,Line offset" line.long 0xFF0 "GFXMMU_LUT1022L,GFXMMU LUT entry 1022 low" hexmask.long.byte 0xFF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFF4 "GFXMMU_LUT1022H,GFXMMU LUT entry 1022 high" hexmask.long.tbyte 0xFF4 0.--17. 1. "LO,Line offset" line.long 0xFF8 "GFXMMU_LUT1023L,GFXMMU LUT entry 1023 low" hexmask.long.byte 0xFF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFFC "GFXMMU_LUT1023H,GFXMMU LUT entry 1023 high" hexmask.long.tbyte 0xFFC 0.--17. 1. "LO,Line offset" tree.end tree "GFXMMU_S" base ad:0x58030000 group.long 0x0++0x3 line.long 0x0 "GFXMMU_CR,GFXMMU configuration register" bitfld.long 0x0 31. "B3PM,Buffer 3 packing mode" "0: MSB is removed,1: LSB is removed" bitfld.long 0x0 30. "B3PE,Buffer 3 packing enable" "0: Packing is disabled,1: Packing is enable" bitfld.long 0x0 29. "B2PM,Buffer 2 packing mode" "0: MSB is removed,1: LSB is removed" newline bitfld.long 0x0 28. "B2PE,Buffer 2 packing enable" "0: Packing is disabled,1: Packing is enable" bitfld.long 0x0 27. "B1PM,Buffer 1 packing mode" "0: MSB is removed,1: LSB is removed" bitfld.long 0x0 26. "B1PE,Buffer 1 packing enable" "0: Packing is disabled,1: Packing is enable" newline bitfld.long 0x0 25. "B0PM,Buffer 0 packing mode" "0: MSB is removed,1: LSB is removed" bitfld.long 0x0 24. "B0PE,Buffer 0 packing enable" "0: Packing is disabled,1: Packing is enable" bitfld.long 0x0 15. "ATE,Address translation enable" "0: Address translation is disable,1: Address translation is enable" newline bitfld.long 0x0 6. "BS,Block size" "0: 16-byte blocks,1: 12-byte blocks" bitfld.long 0x0 4. "AMEIE,AXI master error interrupt enable" "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 3. "B3OIE,Buffer 3 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" newline bitfld.long 0x0 2. "B2OIE,Buffer 2 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 1. "B1OIE,Buffer 1 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" bitfld.long 0x0 0. "B0OIE,Buffer 0 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled" rgroup.long 0x4++0x3 line.long 0x0 "GFXMMU_SR,GFXMMU status register" bitfld.long 0x0 4. "AMEF,AXI master error flag" "0,1" bitfld.long 0x0 3. "B3OF,Buffer 3 overflow flag" "0,1" bitfld.long 0x0 2. "B2OF,Buffer 2 overflow flag" "0,1" newline bitfld.long 0x0 1. "B1OF,Buffer 1 overflow flag" "0,1" bitfld.long 0x0 0. "B0OF,Buffer 0 overflow flag" "0,1" group.long 0x8++0x3 line.long 0x0 "GFXMMU_FCR,GFXMMU flag clear register" bitfld.long 0x0 4. "CAMEF,Clear AXI master error flag" "0,1" bitfld.long 0x0 3. "CB3OF,Clear buffer 3 overflow flag" "0,1" bitfld.long 0x0 2. "CB2OF,Clear buffer 2 overflow flag" "0,1" newline bitfld.long 0x0 1. "CB1OF,Clear buffer 1 overflow flag" "0,1" bitfld.long 0x0 0. "CB0OF,Clear buffer 0 overflow flag" "0,1" group.long 0x10++0x7 line.long 0x0 "GFXMMU_DVR,GFXMMU default value register" hexmask.long 0x0 0.--31. 1. "DV,Default value" line.long 0x4 "GFXMMU_DAR,GFXMMU default alpha register" hexmask.long.byte 0x4 0.--7. 1. "DA,Default alpha" group.long 0x20++0xF line.long 0x0 "GFXMMU_B0CR,GFXMMU buffer 0 configuration register" hexmask.long.word 0x0 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x0 4.--22. 1. "PBO,Physical buffer offset" line.long 0x4 "GFXMMU_B1CR,GFXMMU buffer 1 configuration register" hexmask.long.word 0x4 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x4 4.--22. 1. "PBO,Physical buffer offset" line.long 0x8 "GFXMMU_B2CR,GFXMMU buffer 2 configuration register" hexmask.long.word 0x8 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0x8 4.--22. 1. "PBO,Physical buffer offset" line.long 0xC "GFXMMU_B3CR,GFXMMU buffer 3 configuration register" hexmask.long.word 0xC 23.--31. 1. "PBBA,Physical buffer base address" hexmask.long.tbyte 0xC 4.--22. 1. "PBO,Physical buffer offset" group.long 0x1000++0xFFF line.long 0x0 "GFXMMU_LUT0L,GFXMMU LUT entry 0 low" hexmask.long.byte 0x0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x0 8.--15. 1. "FVB,First valid block" bitfld.long 0x0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4 "GFXMMU_LUT0H,GFXMMU LUT entry 0 high" hexmask.long.tbyte 0x4 0.--17. 1. "LO,Line offset" line.long 0x8 "GFXMMU_LUT1L,GFXMMU LUT entry 1 low" hexmask.long.byte 0x8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC "GFXMMU_LUT1H,GFXMMU LUT entry 1 high" hexmask.long.tbyte 0xC 0.--17. 1. "LO,Line offset" line.long 0x10 "GFXMMU_LUT2L,GFXMMU LUT entry 2 low" hexmask.long.byte 0x10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x10 8.--15. 1. "FVB,First valid block" bitfld.long 0x10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14 "GFXMMU_LUT2H,GFXMMU LUT entry 2 high" hexmask.long.tbyte 0x14 0.--17. 1. "LO,Line offset" line.long 0x18 "GFXMMU_LUT3L,GFXMMU LUT entry 3 low" hexmask.long.byte 0x18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x18 8.--15. 1. "FVB,First valid block" bitfld.long 0x18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C "GFXMMU_LUT3H,GFXMMU LUT entry 3 high" hexmask.long.tbyte 0x1C 0.--17. 1. "LO,Line offset" line.long 0x20 "GFXMMU_LUT4L,GFXMMU LUT entry 4 low" hexmask.long.byte 0x20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x20 8.--15. 1. "FVB,First valid block" bitfld.long 0x20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24 "GFXMMU_LUT4H,GFXMMU LUT entry 4 high" hexmask.long.tbyte 0x24 0.--17. 1. "LO,Line offset" line.long 0x28 "GFXMMU_LUT5L,GFXMMU LUT entry 5 low" hexmask.long.byte 0x28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x28 8.--15. 1. "FVB,First valid block" bitfld.long 0x28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C "GFXMMU_LUT5H,GFXMMU LUT entry 5 high" hexmask.long.tbyte 0x2C 0.--17. 1. "LO,Line offset" line.long 0x30 "GFXMMU_LUT6L,GFXMMU LUT entry 6 low" hexmask.long.byte 0x30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x30 8.--15. 1. "FVB,First valid block" bitfld.long 0x30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34 "GFXMMU_LUT6H,GFXMMU LUT entry 6 high" hexmask.long.tbyte 0x34 0.--17. 1. "LO,Line offset" line.long 0x38 "GFXMMU_LUT7L,GFXMMU LUT entry 7 low" hexmask.long.byte 0x38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x38 8.--15. 1. "FVB,First valid block" bitfld.long 0x38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C "GFXMMU_LUT7H,GFXMMU LUT entry 7 high" hexmask.long.tbyte 0x3C 0.--17. 1. "LO,Line offset" line.long 0x40 "GFXMMU_LUT8L,GFXMMU LUT entry 8 low" hexmask.long.byte 0x40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x40 8.--15. 1. "FVB,First valid block" bitfld.long 0x40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44 "GFXMMU_LUT8H,GFXMMU LUT entry 8 high" hexmask.long.tbyte 0x44 0.--17. 1. "LO,Line offset" line.long 0x48 "GFXMMU_LUT9L,GFXMMU LUT entry 9 low" hexmask.long.byte 0x48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x48 8.--15. 1. "FVB,First valid block" bitfld.long 0x48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C "GFXMMU_LUT9H,GFXMMU LUT entry 9 high" hexmask.long.tbyte 0x4C 0.--17. 1. "LO,Line offset" line.long 0x50 "GFXMMU_LUT10L,GFXMMU LUT entry 10 low" hexmask.long.byte 0x50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x50 8.--15. 1. "FVB,First valid block" bitfld.long 0x50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54 "GFXMMU_LUT10H,GFXMMU LUT entry 10 high" hexmask.long.tbyte 0x54 0.--17. 1. "LO,Line offset" line.long 0x58 "GFXMMU_LUT11L,GFXMMU LUT entry 11 low" hexmask.long.byte 0x58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x58 8.--15. 1. "FVB,First valid block" bitfld.long 0x58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C "GFXMMU_LUT11H,GFXMMU LUT entry 11 high" hexmask.long.tbyte 0x5C 0.--17. 1. "LO,Line offset" line.long 0x60 "GFXMMU_LUT12L,GFXMMU LUT entry 12 low" hexmask.long.byte 0x60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x60 8.--15. 1. "FVB,First valid block" bitfld.long 0x60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64 "GFXMMU_LUT12H,GFXMMU LUT entry 12 high" hexmask.long.tbyte 0x64 0.--17. 1. "LO,Line offset" line.long 0x68 "GFXMMU_LUT13L,GFXMMU LUT entry 13 low" hexmask.long.byte 0x68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x68 8.--15. 1. "FVB,First valid block" bitfld.long 0x68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C "GFXMMU_LUT13H,GFXMMU LUT entry 13 high" hexmask.long.tbyte 0x6C 0.--17. 1. "LO,Line offset" line.long 0x70 "GFXMMU_LUT14L,GFXMMU LUT entry 14 low" hexmask.long.byte 0x70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x70 8.--15. 1. "FVB,First valid block" bitfld.long 0x70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74 "GFXMMU_LUT14H,GFXMMU LUT entry 14 high" hexmask.long.tbyte 0x74 0.--17. 1. "LO,Line offset" line.long 0x78 "GFXMMU_LUT15L,GFXMMU LUT entry 15 low" hexmask.long.byte 0x78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x78 8.--15. 1. "FVB,First valid block" bitfld.long 0x78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C "GFXMMU_LUT15H,GFXMMU LUT entry 15 high" hexmask.long.tbyte 0x7C 0.--17. 1. "LO,Line offset" line.long 0x80 "GFXMMU_LUT16L,GFXMMU LUT entry 16 low" hexmask.long.byte 0x80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x80 8.--15. 1. "FVB,First valid block" bitfld.long 0x80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84 "GFXMMU_LUT16H,GFXMMU LUT entry 16 high" hexmask.long.tbyte 0x84 0.--17. 1. "LO,Line offset" line.long 0x88 "GFXMMU_LUT17L,GFXMMU LUT entry 17 low" hexmask.long.byte 0x88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x88 8.--15. 1. "FVB,First valid block" bitfld.long 0x88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C "GFXMMU_LUT17H,GFXMMU LUT entry 17 high" hexmask.long.tbyte 0x8C 0.--17. 1. "LO,Line offset" line.long 0x90 "GFXMMU_LUT18L,GFXMMU LUT entry 18 low" hexmask.long.byte 0x90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x90 8.--15. 1. "FVB,First valid block" bitfld.long 0x90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94 "GFXMMU_LUT18H,GFXMMU LUT entry 18 high" hexmask.long.tbyte 0x94 0.--17. 1. "LO,Line offset" line.long 0x98 "GFXMMU_LUT19L,GFXMMU LUT entry 19 low" hexmask.long.byte 0x98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x98 8.--15. 1. "FVB,First valid block" bitfld.long 0x98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C "GFXMMU_LUT19H,GFXMMU LUT entry 19 high" hexmask.long.tbyte 0x9C 0.--17. 1. "LO,Line offset" line.long 0xA0 "GFXMMU_LUT20L,GFXMMU LUT entry 20 low" hexmask.long.byte 0xA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4 "GFXMMU_LUT20H,GFXMMU LUT entry 20 high" hexmask.long.tbyte 0xA4 0.--17. 1. "LO,Line offset" line.long 0xA8 "GFXMMU_LUT21L,GFXMMU LUT entry 21 low" hexmask.long.byte 0xA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC "GFXMMU_LUT21H,GFXMMU LUT entry 21 high" hexmask.long.tbyte 0xAC 0.--17. 1. "LO,Line offset" line.long 0xB0 "GFXMMU_LUT22L,GFXMMU LUT entry 22 low" hexmask.long.byte 0xB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4 "GFXMMU_LUT22H,GFXMMU LUT entry 22 high" hexmask.long.tbyte 0xB4 0.--17. 1. "LO,Line offset" line.long 0xB8 "GFXMMU_LUT23L,GFXMMU LUT entry 23 low" hexmask.long.byte 0xB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC "GFXMMU_LUT23H,GFXMMU LUT entry 23 high" hexmask.long.tbyte 0xBC 0.--17. 1. "LO,Line offset" line.long 0xC0 "GFXMMU_LUT24L,GFXMMU LUT entry 24 low" hexmask.long.byte 0xC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4 "GFXMMU_LUT24H,GFXMMU LUT entry 24 high" hexmask.long.tbyte 0xC4 0.--17. 1. "LO,Line offset" line.long 0xC8 "GFXMMU_LUT25L,GFXMMU LUT entry 25 low" hexmask.long.byte 0xC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC "GFXMMU_LUT25H,GFXMMU LUT entry 25 high" hexmask.long.tbyte 0xCC 0.--17. 1. "LO,Line offset" line.long 0xD0 "GFXMMU_LUT26L,GFXMMU LUT entry 26 low" hexmask.long.byte 0xD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4 "GFXMMU_LUT26H,GFXMMU LUT entry 26 high" hexmask.long.tbyte 0xD4 0.--17. 1. "LO,Line offset" line.long 0xD8 "GFXMMU_LUT27L,GFXMMU LUT entry 27 low" hexmask.long.byte 0xD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC "GFXMMU_LUT27H,GFXMMU LUT entry 27 high" hexmask.long.tbyte 0xDC 0.--17. 1. "LO,Line offset" line.long 0xE0 "GFXMMU_LUT28L,GFXMMU LUT entry 28 low" hexmask.long.byte 0xE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4 "GFXMMU_LUT28H,GFXMMU LUT entry 28 high" hexmask.long.tbyte 0xE4 0.--17. 1. "LO,Line offset" line.long 0xE8 "GFXMMU_LUT29L,GFXMMU LUT entry 29 low" hexmask.long.byte 0xE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC "GFXMMU_LUT29H,GFXMMU LUT entry 29 high" hexmask.long.tbyte 0xEC 0.--17. 1. "LO,Line offset" line.long 0xF0 "GFXMMU_LUT30L,GFXMMU LUT entry 30 low" hexmask.long.byte 0xF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4 "GFXMMU_LUT30H,GFXMMU LUT entry 30 high" hexmask.long.tbyte 0xF4 0.--17. 1. "LO,Line offset" line.long 0xF8 "GFXMMU_LUT31L,GFXMMU LUT entry 31 low" hexmask.long.byte 0xF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC "GFXMMU_LUT31H,GFXMMU LUT entry 31 high" hexmask.long.tbyte 0xFC 0.--17. 1. "LO,Line offset" line.long 0x100 "GFXMMU_LUT32L,GFXMMU LUT entry 32 low" hexmask.long.byte 0x100 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x100 8.--15. 1. "FVB,First valid block" bitfld.long 0x100 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x104 "GFXMMU_LUT32H,GFXMMU LUT entry 32 high" hexmask.long.tbyte 0x104 0.--17. 1. "LO,Line offset" line.long 0x108 "GFXMMU_LUT33L,GFXMMU LUT entry 33 low" hexmask.long.byte 0x108 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x108 8.--15. 1. "FVB,First valid block" bitfld.long 0x108 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x10C "GFXMMU_LUT33H,GFXMMU LUT entry 33 high" hexmask.long.tbyte 0x10C 0.--17. 1. "LO,Line offset" line.long 0x110 "GFXMMU_LUT34L,GFXMMU LUT entry 34 low" hexmask.long.byte 0x110 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x110 8.--15. 1. "FVB,First valid block" bitfld.long 0x110 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x114 "GFXMMU_LUT34H,GFXMMU LUT entry 34 high" hexmask.long.tbyte 0x114 0.--17. 1. "LO,Line offset" line.long 0x118 "GFXMMU_LUT35L,GFXMMU LUT entry 35 low" hexmask.long.byte 0x118 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x118 8.--15. 1. "FVB,First valid block" bitfld.long 0x118 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x11C "GFXMMU_LUT35H,GFXMMU LUT entry 35 high" hexmask.long.tbyte 0x11C 0.--17. 1. "LO,Line offset" line.long 0x120 "GFXMMU_LUT36L,GFXMMU LUT entry 36 low" hexmask.long.byte 0x120 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x120 8.--15. 1. "FVB,First valid block" bitfld.long 0x120 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x124 "GFXMMU_LUT36H,GFXMMU LUT entry 36 high" hexmask.long.tbyte 0x124 0.--17. 1. "LO,Line offset" line.long 0x128 "GFXMMU_LUT37L,GFXMMU LUT entry 37 low" hexmask.long.byte 0x128 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x128 8.--15. 1. "FVB,First valid block" bitfld.long 0x128 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x12C "GFXMMU_LUT37H,GFXMMU LUT entry 37 high" hexmask.long.tbyte 0x12C 0.--17. 1. "LO,Line offset" line.long 0x130 "GFXMMU_LUT38L,GFXMMU LUT entry 38 low" hexmask.long.byte 0x130 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x130 8.--15. 1. "FVB,First valid block" bitfld.long 0x130 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x134 "GFXMMU_LUT38H,GFXMMU LUT entry 38 high" hexmask.long.tbyte 0x134 0.--17. 1. "LO,Line offset" line.long 0x138 "GFXMMU_LUT39L,GFXMMU LUT entry 39 low" hexmask.long.byte 0x138 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x138 8.--15. 1. "FVB,First valid block" bitfld.long 0x138 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x13C "GFXMMU_LUT39H,GFXMMU LUT entry 39 high" hexmask.long.tbyte 0x13C 0.--17. 1. "LO,Line offset" line.long 0x140 "GFXMMU_LUT40L,GFXMMU LUT entry 40 low" hexmask.long.byte 0x140 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x140 8.--15. 1. "FVB,First valid block" bitfld.long 0x140 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x144 "GFXMMU_LUT40H,GFXMMU LUT entry 40 high" hexmask.long.tbyte 0x144 0.--17. 1. "LO,Line offset" line.long 0x148 "GFXMMU_LUT41L,GFXMMU LUT entry 41 low" hexmask.long.byte 0x148 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x148 8.--15. 1. "FVB,First valid block" bitfld.long 0x148 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14C "GFXMMU_LUT41H,GFXMMU LUT entry 41 high" hexmask.long.tbyte 0x14C 0.--17. 1. "LO,Line offset" line.long 0x150 "GFXMMU_LUT42L,GFXMMU LUT entry 42 low" hexmask.long.byte 0x150 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x150 8.--15. 1. "FVB,First valid block" bitfld.long 0x150 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x154 "GFXMMU_LUT42H,GFXMMU LUT entry 42 high" hexmask.long.tbyte 0x154 0.--17. 1. "LO,Line offset" line.long 0x158 "GFXMMU_LUT43L,GFXMMU LUT entry 43 low" hexmask.long.byte 0x158 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x158 8.--15. 1. "FVB,First valid block" bitfld.long 0x158 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x15C "GFXMMU_LUT43H,GFXMMU LUT entry 43 high" hexmask.long.tbyte 0x15C 0.--17. 1. "LO,Line offset" line.long 0x160 "GFXMMU_LUT44L,GFXMMU LUT entry 44 low" hexmask.long.byte 0x160 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x160 8.--15. 1. "FVB,First valid block" bitfld.long 0x160 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x164 "GFXMMU_LUT44H,GFXMMU LUT entry 44 high" hexmask.long.tbyte 0x164 0.--17. 1. "LO,Line offset" line.long 0x168 "GFXMMU_LUT45L,GFXMMU LUT entry 45 low" hexmask.long.byte 0x168 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x168 8.--15. 1. "FVB,First valid block" bitfld.long 0x168 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x16C "GFXMMU_LUT45H,GFXMMU LUT entry 45 high" hexmask.long.tbyte 0x16C 0.--17. 1. "LO,Line offset" line.long 0x170 "GFXMMU_LUT46L,GFXMMU LUT entry 46 low" hexmask.long.byte 0x170 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x170 8.--15. 1. "FVB,First valid block" bitfld.long 0x170 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x174 "GFXMMU_LUT46H,GFXMMU LUT entry 46 high" hexmask.long.tbyte 0x174 0.--17. 1. "LO,Line offset" line.long 0x178 "GFXMMU_LUT47L,GFXMMU LUT entry 47 low" hexmask.long.byte 0x178 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x178 8.--15. 1. "FVB,First valid block" bitfld.long 0x178 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x17C "GFXMMU_LUT47H,GFXMMU LUT entry 47 high" hexmask.long.tbyte 0x17C 0.--17. 1. "LO,Line offset" line.long 0x180 "GFXMMU_LUT48L,GFXMMU LUT entry 48 low" hexmask.long.byte 0x180 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x180 8.--15. 1. "FVB,First valid block" bitfld.long 0x180 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x184 "GFXMMU_LUT48H,GFXMMU LUT entry 48 high" hexmask.long.tbyte 0x184 0.--17. 1. "LO,Line offset" line.long 0x188 "GFXMMU_LUT49L,GFXMMU LUT entry 49 low" hexmask.long.byte 0x188 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x188 8.--15. 1. "FVB,First valid block" bitfld.long 0x188 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x18C "GFXMMU_LUT49H,GFXMMU LUT entry 49 high" hexmask.long.tbyte 0x18C 0.--17. 1. "LO,Line offset" line.long 0x190 "GFXMMU_LUT50L,GFXMMU LUT entry 50 low" hexmask.long.byte 0x190 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x190 8.--15. 1. "FVB,First valid block" bitfld.long 0x190 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x194 "GFXMMU_LUT50H,GFXMMU LUT entry 50 high" hexmask.long.tbyte 0x194 0.--17. 1. "LO,Line offset" line.long 0x198 "GFXMMU_LUT51L,GFXMMU LUT entry 51 low" hexmask.long.byte 0x198 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x198 8.--15. 1. "FVB,First valid block" bitfld.long 0x198 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x19C "GFXMMU_LUT51H,GFXMMU LUT entry 51 high" hexmask.long.tbyte 0x19C 0.--17. 1. "LO,Line offset" line.long 0x1A0 "GFXMMU_LUT52L,GFXMMU LUT entry 52 low" hexmask.long.byte 0x1A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1A4 "GFXMMU_LUT52H,GFXMMU LUT entry 52 high" hexmask.long.tbyte 0x1A4 0.--17. 1. "LO,Line offset" line.long 0x1A8 "GFXMMU_LUT53L,GFXMMU LUT entry 53 low" hexmask.long.byte 0x1A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1AC "GFXMMU_LUT53H,GFXMMU LUT entry 53 high" hexmask.long.tbyte 0x1AC 0.--17. 1. "LO,Line offset" line.long 0x1B0 "GFXMMU_LUT54L,GFXMMU LUT entry 54 low" hexmask.long.byte 0x1B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1B4 "GFXMMU_LUT54H,GFXMMU LUT entry 54 high" hexmask.long.tbyte 0x1B4 0.--17. 1. "LO,Line offset" line.long 0x1B8 "GFXMMU_LUT55L,GFXMMU LUT entry 55 low" hexmask.long.byte 0x1B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1BC "GFXMMU_LUT55H,GFXMMU LUT entry 55 high" hexmask.long.tbyte 0x1BC 0.--17. 1. "LO,Line offset" line.long 0x1C0 "GFXMMU_LUT56L,GFXMMU LUT entry 56 low" hexmask.long.byte 0x1C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C4 "GFXMMU_LUT56H,GFXMMU LUT entry 56 high" hexmask.long.tbyte 0x1C4 0.--17. 1. "LO,Line offset" line.long 0x1C8 "GFXMMU_LUT57L,GFXMMU LUT entry 57 low" hexmask.long.byte 0x1C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1CC "GFXMMU_LUT57H,GFXMMU LUT entry 57 high" hexmask.long.tbyte 0x1CC 0.--17. 1. "LO,Line offset" line.long 0x1D0 "GFXMMU_LUT58L,GFXMMU LUT entry 58 low" hexmask.long.byte 0x1D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1D4 "GFXMMU_LUT58H,GFXMMU LUT entry 58 high" hexmask.long.tbyte 0x1D4 0.--17. 1. "LO,Line offset" line.long 0x1D8 "GFXMMU_LUT59L,GFXMMU LUT entry 59 low" hexmask.long.byte 0x1D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1DC "GFXMMU_LUT59H,GFXMMU LUT entry 59 high" hexmask.long.tbyte 0x1DC 0.--17. 1. "LO,Line offset" line.long 0x1E0 "GFXMMU_LUT60L,GFXMMU LUT entry 60 low" hexmask.long.byte 0x1E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1E4 "GFXMMU_LUT60H,GFXMMU LUT entry 60 high" hexmask.long.tbyte 0x1E4 0.--17. 1. "LO,Line offset" line.long 0x1E8 "GFXMMU_LUT61L,GFXMMU LUT entry 61 low" hexmask.long.byte 0x1E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1EC "GFXMMU_LUT61H,GFXMMU LUT entry 61 high" hexmask.long.tbyte 0x1EC 0.--17. 1. "LO,Line offset" line.long 0x1F0 "GFXMMU_LUT62L,GFXMMU LUT entry 62 low" hexmask.long.byte 0x1F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1F4 "GFXMMU_LUT62H,GFXMMU LUT entry 62 high" hexmask.long.tbyte 0x1F4 0.--17. 1. "LO,Line offset" line.long 0x1F8 "GFXMMU_LUT63L,GFXMMU LUT entry 63 low" hexmask.long.byte 0x1F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1FC "GFXMMU_LUT63H,GFXMMU LUT entry 63 high" hexmask.long.tbyte 0x1FC 0.--17. 1. "LO,Line offset" line.long 0x200 "GFXMMU_LUT64L,GFXMMU LUT entry 64 low" hexmask.long.byte 0x200 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x200 8.--15. 1. "FVB,First valid block" bitfld.long 0x200 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x204 "GFXMMU_LUT64H,GFXMMU LUT entry 64 high" hexmask.long.tbyte 0x204 0.--17. 1. "LO,Line offset" line.long 0x208 "GFXMMU_LUT65L,GFXMMU LUT entry 65 low" hexmask.long.byte 0x208 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x208 8.--15. 1. "FVB,First valid block" bitfld.long 0x208 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x20C "GFXMMU_LUT65H,GFXMMU LUT entry 65 high" hexmask.long.tbyte 0x20C 0.--17. 1. "LO,Line offset" line.long 0x210 "GFXMMU_LUT66L,GFXMMU LUT entry 66 low" hexmask.long.byte 0x210 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x210 8.--15. 1. "FVB,First valid block" bitfld.long 0x210 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x214 "GFXMMU_LUT66H,GFXMMU LUT entry 66 high" hexmask.long.tbyte 0x214 0.--17. 1. "LO,Line offset" line.long 0x218 "GFXMMU_LUT67L,GFXMMU LUT entry 67 low" hexmask.long.byte 0x218 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x218 8.--15. 1. "FVB,First valid block" bitfld.long 0x218 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x21C "GFXMMU_LUT67H,GFXMMU LUT entry 67 high" hexmask.long.tbyte 0x21C 0.--17. 1. "LO,Line offset" line.long 0x220 "GFXMMU_LUT68L,GFXMMU LUT entry 68 low" hexmask.long.byte 0x220 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x220 8.--15. 1. "FVB,First valid block" bitfld.long 0x220 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x224 "GFXMMU_LUT68H,GFXMMU LUT entry 68 high" hexmask.long.tbyte 0x224 0.--17. 1. "LO,Line offset" line.long 0x228 "GFXMMU_LUT69L,GFXMMU LUT entry 69 low" hexmask.long.byte 0x228 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x228 8.--15. 1. "FVB,First valid block" bitfld.long 0x228 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x22C "GFXMMU_LUT69H,GFXMMU LUT entry 69 high" hexmask.long.tbyte 0x22C 0.--17. 1. "LO,Line offset" line.long 0x230 "GFXMMU_LUT70L,GFXMMU LUT entry 70 low" hexmask.long.byte 0x230 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x230 8.--15. 1. "FVB,First valid block" bitfld.long 0x230 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x234 "GFXMMU_LUT70H,GFXMMU LUT entry 70 high" hexmask.long.tbyte 0x234 0.--17. 1. "LO,Line offset" line.long 0x238 "GFXMMU_LUT71L,GFXMMU LUT entry 71 low" hexmask.long.byte 0x238 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x238 8.--15. 1. "FVB,First valid block" bitfld.long 0x238 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x23C "GFXMMU_LUT71H,GFXMMU LUT entry 71 high" hexmask.long.tbyte 0x23C 0.--17. 1. "LO,Line offset" line.long 0x240 "GFXMMU_LUT72L,GFXMMU LUT entry 72 low" hexmask.long.byte 0x240 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x240 8.--15. 1. "FVB,First valid block" bitfld.long 0x240 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x244 "GFXMMU_LUT72H,GFXMMU LUT entry 72 high" hexmask.long.tbyte 0x244 0.--17. 1. "LO,Line offset" line.long 0x248 "GFXMMU_LUT73L,GFXMMU LUT entry 73 low" hexmask.long.byte 0x248 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x248 8.--15. 1. "FVB,First valid block" bitfld.long 0x248 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24C "GFXMMU_LUT73H,GFXMMU LUT entry 73 high" hexmask.long.tbyte 0x24C 0.--17. 1. "LO,Line offset" line.long 0x250 "GFXMMU_LUT74L,GFXMMU LUT entry 74 low" hexmask.long.byte 0x250 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x250 8.--15. 1. "FVB,First valid block" bitfld.long 0x250 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x254 "GFXMMU_LUT74H,GFXMMU LUT entry 74 high" hexmask.long.tbyte 0x254 0.--17. 1. "LO,Line offset" line.long 0x258 "GFXMMU_LUT75L,GFXMMU LUT entry 75 low" hexmask.long.byte 0x258 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x258 8.--15. 1. "FVB,First valid block" bitfld.long 0x258 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x25C "GFXMMU_LUT75H,GFXMMU LUT entry 75 high" hexmask.long.tbyte 0x25C 0.--17. 1. "LO,Line offset" line.long 0x260 "GFXMMU_LUT76L,GFXMMU LUT entry 76 low" hexmask.long.byte 0x260 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x260 8.--15. 1. "FVB,First valid block" bitfld.long 0x260 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x264 "GFXMMU_LUT76H,GFXMMU LUT entry 76 high" hexmask.long.tbyte 0x264 0.--17. 1. "LO,Line offset" line.long 0x268 "GFXMMU_LUT77L,GFXMMU LUT entry 77 low" hexmask.long.byte 0x268 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x268 8.--15. 1. "FVB,First valid block" bitfld.long 0x268 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x26C "GFXMMU_LUT77H,GFXMMU LUT entry 77 high" hexmask.long.tbyte 0x26C 0.--17. 1. "LO,Line offset" line.long 0x270 "GFXMMU_LUT78L,GFXMMU LUT entry 78 low" hexmask.long.byte 0x270 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x270 8.--15. 1. "FVB,First valid block" bitfld.long 0x270 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x274 "GFXMMU_LUT78H,GFXMMU LUT entry 78 high" hexmask.long.tbyte 0x274 0.--17. 1. "LO,Line offset" line.long 0x278 "GFXMMU_LUT79L,GFXMMU LUT entry 79 low" hexmask.long.byte 0x278 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x278 8.--15. 1. "FVB,First valid block" bitfld.long 0x278 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x27C "GFXMMU_LUT79H,GFXMMU LUT entry 79 high" hexmask.long.tbyte 0x27C 0.--17. 1. "LO,Line offset" line.long 0x280 "GFXMMU_LUT80L,GFXMMU LUT entry 80 low" hexmask.long.byte 0x280 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x280 8.--15. 1. "FVB,First valid block" bitfld.long 0x280 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x284 "GFXMMU_LUT80H,GFXMMU LUT entry 80 high" hexmask.long.tbyte 0x284 0.--17. 1. "LO,Line offset" line.long 0x288 "GFXMMU_LUT81L,GFXMMU LUT entry 81 low" hexmask.long.byte 0x288 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x288 8.--15. 1. "FVB,First valid block" bitfld.long 0x288 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x28C "GFXMMU_LUT81H,GFXMMU LUT entry 81 high" hexmask.long.tbyte 0x28C 0.--17. 1. "LO,Line offset" line.long 0x290 "GFXMMU_LUT82L,GFXMMU LUT entry 82 low" hexmask.long.byte 0x290 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x290 8.--15. 1. "FVB,First valid block" bitfld.long 0x290 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x294 "GFXMMU_LUT82H,GFXMMU LUT entry 82 high" hexmask.long.tbyte 0x294 0.--17. 1. "LO,Line offset" line.long 0x298 "GFXMMU_LUT83L,GFXMMU LUT entry 83 low" hexmask.long.byte 0x298 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x298 8.--15. 1. "FVB,First valid block" bitfld.long 0x298 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x29C "GFXMMU_LUT83H,GFXMMU LUT entry 83 high" hexmask.long.tbyte 0x29C 0.--17. 1. "LO,Line offset" line.long 0x2A0 "GFXMMU_LUT84L,GFXMMU LUT entry 84 low" hexmask.long.byte 0x2A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2A4 "GFXMMU_LUT84H,GFXMMU LUT entry 84 high" hexmask.long.tbyte 0x2A4 0.--17. 1. "LO,Line offset" line.long 0x2A8 "GFXMMU_LUT85L,GFXMMU LUT entry 85 low" hexmask.long.byte 0x2A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2AC "GFXMMU_LUT85H,GFXMMU LUT entry 85 high" hexmask.long.tbyte 0x2AC 0.--17. 1. "LO,Line offset" line.long 0x2B0 "GFXMMU_LUT86L,GFXMMU LUT entry 86 low" hexmask.long.byte 0x2B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2B4 "GFXMMU_LUT86H,GFXMMU LUT entry 86 high" hexmask.long.tbyte 0x2B4 0.--17. 1. "LO,Line offset" line.long 0x2B8 "GFXMMU_LUT87L,GFXMMU LUT entry 87 low" hexmask.long.byte 0x2B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2BC "GFXMMU_LUT87H,GFXMMU LUT entry 87 high" hexmask.long.tbyte 0x2BC 0.--17. 1. "LO,Line offset" line.long 0x2C0 "GFXMMU_LUT88L,GFXMMU LUT entry 88 low" hexmask.long.byte 0x2C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C4 "GFXMMU_LUT88H,GFXMMU LUT entry 88 high" hexmask.long.tbyte 0x2C4 0.--17. 1. "LO,Line offset" line.long 0x2C8 "GFXMMU_LUT89L,GFXMMU LUT entry 89 low" hexmask.long.byte 0x2C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2CC "GFXMMU_LUT89H,GFXMMU LUT entry 89 high" hexmask.long.tbyte 0x2CC 0.--17. 1. "LO,Line offset" line.long 0x2D0 "GFXMMU_LUT90L,GFXMMU LUT entry 90 low" hexmask.long.byte 0x2D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2D4 "GFXMMU_LUT90H,GFXMMU LUT entry 90 high" hexmask.long.tbyte 0x2D4 0.--17. 1. "LO,Line offset" line.long 0x2D8 "GFXMMU_LUT91L,GFXMMU LUT entry 91 low" hexmask.long.byte 0x2D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2DC "GFXMMU_LUT91H,GFXMMU LUT entry 91 high" hexmask.long.tbyte 0x2DC 0.--17. 1. "LO,Line offset" line.long 0x2E0 "GFXMMU_LUT92L,GFXMMU LUT entry 92 low" hexmask.long.byte 0x2E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2E4 "GFXMMU_LUT92H,GFXMMU LUT entry 92 high" hexmask.long.tbyte 0x2E4 0.--17. 1. "LO,Line offset" line.long 0x2E8 "GFXMMU_LUT93L,GFXMMU LUT entry 93 low" hexmask.long.byte 0x2E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2EC "GFXMMU_LUT93H,GFXMMU LUT entry 93 high" hexmask.long.tbyte 0x2EC 0.--17. 1. "LO,Line offset" line.long 0x2F0 "GFXMMU_LUT94L,GFXMMU LUT entry 94 low" hexmask.long.byte 0x2F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2F4 "GFXMMU_LUT94H,GFXMMU LUT entry 94 high" hexmask.long.tbyte 0x2F4 0.--17. 1. "LO,Line offset" line.long 0x2F8 "GFXMMU_LUT95L,GFXMMU LUT entry 95 low" hexmask.long.byte 0x2F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2FC "GFXMMU_LUT95H,GFXMMU LUT entry 95 high" hexmask.long.tbyte 0x2FC 0.--17. 1. "LO,Line offset" line.long 0x300 "GFXMMU_LUT96L,GFXMMU LUT entry 96 low" hexmask.long.byte 0x300 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x300 8.--15. 1. "FVB,First valid block" bitfld.long 0x300 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x304 "GFXMMU_LUT96H,GFXMMU LUT entry 96 high" hexmask.long.tbyte 0x304 0.--17. 1. "LO,Line offset" line.long 0x308 "GFXMMU_LUT97L,GFXMMU LUT entry 97 low" hexmask.long.byte 0x308 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x308 8.--15. 1. "FVB,First valid block" bitfld.long 0x308 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x30C "GFXMMU_LUT97H,GFXMMU LUT entry 97 high" hexmask.long.tbyte 0x30C 0.--17. 1. "LO,Line offset" line.long 0x310 "GFXMMU_LUT98L,GFXMMU LUT entry 98 low" hexmask.long.byte 0x310 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x310 8.--15. 1. "FVB,First valid block" bitfld.long 0x310 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x314 "GFXMMU_LUT98H,GFXMMU LUT entry 98 high" hexmask.long.tbyte 0x314 0.--17. 1. "LO,Line offset" line.long 0x318 "GFXMMU_LUT99L,GFXMMU LUT entry 99 low" hexmask.long.byte 0x318 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x318 8.--15. 1. "FVB,First valid block" bitfld.long 0x318 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x31C "GFXMMU_LUT99H,GFXMMU LUT entry 99 high" hexmask.long.tbyte 0x31C 0.--17. 1. "LO,Line offset" line.long 0x320 "GFXMMU_LUT100L,GFXMMU LUT entry 100 low" hexmask.long.byte 0x320 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x320 8.--15. 1. "FVB,First valid block" bitfld.long 0x320 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x324 "GFXMMU_LUT100H,GFXMMU LUT entry 100 high" hexmask.long.tbyte 0x324 0.--17. 1. "LO,Line offset" line.long 0x328 "GFXMMU_LUT101L,GFXMMU LUT entry 101 low" hexmask.long.byte 0x328 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x328 8.--15. 1. "FVB,First valid block" bitfld.long 0x328 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x32C "GFXMMU_LUT101H,GFXMMU LUT entry 101 high" hexmask.long.tbyte 0x32C 0.--17. 1. "LO,Line offset" line.long 0x330 "GFXMMU_LUT102L,GFXMMU LUT entry 102 low" hexmask.long.byte 0x330 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x330 8.--15. 1. "FVB,First valid block" bitfld.long 0x330 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x334 "GFXMMU_LUT102H,GFXMMU LUT entry 102 high" hexmask.long.tbyte 0x334 0.--17. 1. "LO,Line offset" line.long 0x338 "GFXMMU_LUT103L,GFXMMU LUT entry 103 low" hexmask.long.byte 0x338 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x338 8.--15. 1. "FVB,First valid block" bitfld.long 0x338 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x33C "GFXMMU_LUT103H,GFXMMU LUT entry 103 high" hexmask.long.tbyte 0x33C 0.--17. 1. "LO,Line offset" line.long 0x340 "GFXMMU_LUT104L,GFXMMU LUT entry 104 low" hexmask.long.byte 0x340 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x340 8.--15. 1. "FVB,First valid block" bitfld.long 0x340 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x344 "GFXMMU_LUT104H,GFXMMU LUT entry 104 high" hexmask.long.tbyte 0x344 0.--17. 1. "LO,Line offset" line.long 0x348 "GFXMMU_LUT105L,GFXMMU LUT entry 105 low" hexmask.long.byte 0x348 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x348 8.--15. 1. "FVB,First valid block" bitfld.long 0x348 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34C "GFXMMU_LUT105H,GFXMMU LUT entry 105 high" hexmask.long.tbyte 0x34C 0.--17. 1. "LO,Line offset" line.long 0x350 "GFXMMU_LUT106L,GFXMMU LUT entry 106 low" hexmask.long.byte 0x350 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x350 8.--15. 1. "FVB,First valid block" bitfld.long 0x350 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x354 "GFXMMU_LUT106H,GFXMMU LUT entry 106 high" hexmask.long.tbyte 0x354 0.--17. 1. "LO,Line offset" line.long 0x358 "GFXMMU_LUT107L,GFXMMU LUT entry 107 low" hexmask.long.byte 0x358 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x358 8.--15. 1. "FVB,First valid block" bitfld.long 0x358 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x35C "GFXMMU_LUT107H,GFXMMU LUT entry 107 high" hexmask.long.tbyte 0x35C 0.--17. 1. "LO,Line offset" line.long 0x360 "GFXMMU_LUT108L,GFXMMU LUT entry 108 low" hexmask.long.byte 0x360 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x360 8.--15. 1. "FVB,First valid block" bitfld.long 0x360 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x364 "GFXMMU_LUT108H,GFXMMU LUT entry 108 high" hexmask.long.tbyte 0x364 0.--17. 1. "LO,Line offset" line.long 0x368 "GFXMMU_LUT109L,GFXMMU LUT entry 109 low" hexmask.long.byte 0x368 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x368 8.--15. 1. "FVB,First valid block" bitfld.long 0x368 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x36C "GFXMMU_LUT109H,GFXMMU LUT entry 109 high" hexmask.long.tbyte 0x36C 0.--17. 1. "LO,Line offset" line.long 0x370 "GFXMMU_LUT110L,GFXMMU LUT entry 110 low" hexmask.long.byte 0x370 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x370 8.--15. 1. "FVB,First valid block" bitfld.long 0x370 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x374 "GFXMMU_LUT110H,GFXMMU LUT entry 110 high" hexmask.long.tbyte 0x374 0.--17. 1. "LO,Line offset" line.long 0x378 "GFXMMU_LUT111L,GFXMMU LUT entry 111 low" hexmask.long.byte 0x378 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x378 8.--15. 1. "FVB,First valid block" bitfld.long 0x378 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x37C "GFXMMU_LUT111H,GFXMMU LUT entry 111 high" hexmask.long.tbyte 0x37C 0.--17. 1. "LO,Line offset" line.long 0x380 "GFXMMU_LUT112L,GFXMMU LUT entry 112 low" hexmask.long.byte 0x380 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x380 8.--15. 1. "FVB,First valid block" bitfld.long 0x380 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x384 "GFXMMU_LUT112H,GFXMMU LUT entry 112 high" hexmask.long.tbyte 0x384 0.--17. 1. "LO,Line offset" line.long 0x388 "GFXMMU_LUT113L,GFXMMU LUT entry 113 low" hexmask.long.byte 0x388 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x388 8.--15. 1. "FVB,First valid block" bitfld.long 0x388 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x38C "GFXMMU_LUT113H,GFXMMU LUT entry 113 high" hexmask.long.tbyte 0x38C 0.--17. 1. "LO,Line offset" line.long 0x390 "GFXMMU_LUT114L,GFXMMU LUT entry 114 low" hexmask.long.byte 0x390 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x390 8.--15. 1. "FVB,First valid block" bitfld.long 0x390 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x394 "GFXMMU_LUT114H,GFXMMU LUT entry 114 high" hexmask.long.tbyte 0x394 0.--17. 1. "LO,Line offset" line.long 0x398 "GFXMMU_LUT115L,GFXMMU LUT entry 115 low" hexmask.long.byte 0x398 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x398 8.--15. 1. "FVB,First valid block" bitfld.long 0x398 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x39C "GFXMMU_LUT115H,GFXMMU LUT entry 115 high" hexmask.long.tbyte 0x39C 0.--17. 1. "LO,Line offset" line.long 0x3A0 "GFXMMU_LUT116L,GFXMMU LUT entry 116 low" hexmask.long.byte 0x3A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3A4 "GFXMMU_LUT116H,GFXMMU LUT entry 116 high" hexmask.long.tbyte 0x3A4 0.--17. 1. "LO,Line offset" line.long 0x3A8 "GFXMMU_LUT117L,GFXMMU LUT entry 117 low" hexmask.long.byte 0x3A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3AC "GFXMMU_LUT117H,GFXMMU LUT entry 117 high" hexmask.long.tbyte 0x3AC 0.--17. 1. "LO,Line offset" line.long 0x3B0 "GFXMMU_LUT118L,GFXMMU LUT entry 118 low" hexmask.long.byte 0x3B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3B4 "GFXMMU_LUT118H,GFXMMU LUT entry 118 high" hexmask.long.tbyte 0x3B4 0.--17. 1. "LO,Line offset" line.long 0x3B8 "GFXMMU_LUT119L,GFXMMU LUT entry 119 low" hexmask.long.byte 0x3B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3BC "GFXMMU_LUT119H,GFXMMU LUT entry 119 high" hexmask.long.tbyte 0x3BC 0.--17. 1. "LO,Line offset" line.long 0x3C0 "GFXMMU_LUT120L,GFXMMU LUT entry 120 low" hexmask.long.byte 0x3C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C4 "GFXMMU_LUT120H,GFXMMU LUT entry 120 high" hexmask.long.tbyte 0x3C4 0.--17. 1. "LO,Line offset" line.long 0x3C8 "GFXMMU_LUT121L,GFXMMU LUT entry 121 low" hexmask.long.byte 0x3C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3CC "GFXMMU_LUT121H,GFXMMU LUT entry 121 high" hexmask.long.tbyte 0x3CC 0.--17. 1. "LO,Line offset" line.long 0x3D0 "GFXMMU_LUT122L,GFXMMU LUT entry 122 low" hexmask.long.byte 0x3D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3D4 "GFXMMU_LUT122H,GFXMMU LUT entry 122 high" hexmask.long.tbyte 0x3D4 0.--17. 1. "LO,Line offset" line.long 0x3D8 "GFXMMU_LUT123L,GFXMMU LUT entry 123 low" hexmask.long.byte 0x3D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3DC "GFXMMU_LUT123H,GFXMMU LUT entry 123 high" hexmask.long.tbyte 0x3DC 0.--17. 1. "LO,Line offset" line.long 0x3E0 "GFXMMU_LUT124L,GFXMMU LUT entry 124 low" hexmask.long.byte 0x3E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3E4 "GFXMMU_LUT124H,GFXMMU LUT entry 124 high" hexmask.long.tbyte 0x3E4 0.--17. 1. "LO,Line offset" line.long 0x3E8 "GFXMMU_LUT125L,GFXMMU LUT entry 125 low" hexmask.long.byte 0x3E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3EC "GFXMMU_LUT125H,GFXMMU LUT entry 125 high" hexmask.long.tbyte 0x3EC 0.--17. 1. "LO,Line offset" line.long 0x3F0 "GFXMMU_LUT126L,GFXMMU LUT entry 126 low" hexmask.long.byte 0x3F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3F4 "GFXMMU_LUT126H,GFXMMU LUT entry 126 high" hexmask.long.tbyte 0x3F4 0.--17. 1. "LO,Line offset" line.long 0x3F8 "GFXMMU_LUT127L,GFXMMU LUT entry 127 low" hexmask.long.byte 0x3F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3FC "GFXMMU_LUT127H,GFXMMU LUT entry 127 high" hexmask.long.tbyte 0x3FC 0.--17. 1. "LO,Line offset" line.long 0x400 "GFXMMU_LUT128L,GFXMMU LUT entry 128 low" hexmask.long.byte 0x400 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x400 8.--15. 1. "FVB,First valid block" bitfld.long 0x400 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x404 "GFXMMU_LUT128H,GFXMMU LUT entry 128 high" hexmask.long.tbyte 0x404 0.--17. 1. "LO,Line offset" line.long 0x408 "GFXMMU_LUT129L,GFXMMU LUT entry 129 low" hexmask.long.byte 0x408 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x408 8.--15. 1. "FVB,First valid block" bitfld.long 0x408 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x40C "GFXMMU_LUT129H,GFXMMU LUT entry 129 high" hexmask.long.tbyte 0x40C 0.--17. 1. "LO,Line offset" line.long 0x410 "GFXMMU_LUT130L,GFXMMU LUT entry 130 low" hexmask.long.byte 0x410 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x410 8.--15. 1. "FVB,First valid block" bitfld.long 0x410 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x414 "GFXMMU_LUT130H,GFXMMU LUT entry 130 high" hexmask.long.tbyte 0x414 0.--17. 1. "LO,Line offset" line.long 0x418 "GFXMMU_LUT131L,GFXMMU LUT entry 131 low" hexmask.long.byte 0x418 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x418 8.--15. 1. "FVB,First valid block" bitfld.long 0x418 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x41C "GFXMMU_LUT131H,GFXMMU LUT entry 131 high" hexmask.long.tbyte 0x41C 0.--17. 1. "LO,Line offset" line.long 0x420 "GFXMMU_LUT132L,GFXMMU LUT entry 132 low" hexmask.long.byte 0x420 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x420 8.--15. 1. "FVB,First valid block" bitfld.long 0x420 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x424 "GFXMMU_LUT132H,GFXMMU LUT entry 132 high" hexmask.long.tbyte 0x424 0.--17. 1. "LO,Line offset" line.long 0x428 "GFXMMU_LUT133L,GFXMMU LUT entry 133 low" hexmask.long.byte 0x428 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x428 8.--15. 1. "FVB,First valid block" bitfld.long 0x428 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x42C "GFXMMU_LUT133H,GFXMMU LUT entry 133 high" hexmask.long.tbyte 0x42C 0.--17. 1. "LO,Line offset" line.long 0x430 "GFXMMU_LUT134L,GFXMMU LUT entry 134 low" hexmask.long.byte 0x430 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x430 8.--15. 1. "FVB,First valid block" bitfld.long 0x430 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x434 "GFXMMU_LUT134H,GFXMMU LUT entry 134 high" hexmask.long.tbyte 0x434 0.--17. 1. "LO,Line offset" line.long 0x438 "GFXMMU_LUT135L,GFXMMU LUT entry 135 low" hexmask.long.byte 0x438 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x438 8.--15. 1. "FVB,First valid block" bitfld.long 0x438 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x43C "GFXMMU_LUT135H,GFXMMU LUT entry 135 high" hexmask.long.tbyte 0x43C 0.--17. 1. "LO,Line offset" line.long 0x440 "GFXMMU_LUT136L,GFXMMU LUT entry 136 low" hexmask.long.byte 0x440 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x440 8.--15. 1. "FVB,First valid block" bitfld.long 0x440 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x444 "GFXMMU_LUT136H,GFXMMU LUT entry 136 high" hexmask.long.tbyte 0x444 0.--17. 1. "LO,Line offset" line.long 0x448 "GFXMMU_LUT137L,GFXMMU LUT entry 137 low" hexmask.long.byte 0x448 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x448 8.--15. 1. "FVB,First valid block" bitfld.long 0x448 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44C "GFXMMU_LUT137H,GFXMMU LUT entry 137 high" hexmask.long.tbyte 0x44C 0.--17. 1. "LO,Line offset" line.long 0x450 "GFXMMU_LUT138L,GFXMMU LUT entry 138 low" hexmask.long.byte 0x450 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x450 8.--15. 1. "FVB,First valid block" bitfld.long 0x450 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x454 "GFXMMU_LUT138H,GFXMMU LUT entry 138 high" hexmask.long.tbyte 0x454 0.--17. 1. "LO,Line offset" line.long 0x458 "GFXMMU_LUT139L,GFXMMU LUT entry 139 low" hexmask.long.byte 0x458 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x458 8.--15. 1. "FVB,First valid block" bitfld.long 0x458 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x45C "GFXMMU_LUT139H,GFXMMU LUT entry 139 high" hexmask.long.tbyte 0x45C 0.--17. 1. "LO,Line offset" line.long 0x460 "GFXMMU_LUT140L,GFXMMU LUT entry 140 low" hexmask.long.byte 0x460 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x460 8.--15. 1. "FVB,First valid block" bitfld.long 0x460 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x464 "GFXMMU_LUT140H,GFXMMU LUT entry 140 high" hexmask.long.tbyte 0x464 0.--17. 1. "LO,Line offset" line.long 0x468 "GFXMMU_LUT141L,GFXMMU LUT entry 141 low" hexmask.long.byte 0x468 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x468 8.--15. 1. "FVB,First valid block" bitfld.long 0x468 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x46C "GFXMMU_LUT141H,GFXMMU LUT entry 141 high" hexmask.long.tbyte 0x46C 0.--17. 1. "LO,Line offset" line.long 0x470 "GFXMMU_LUT142L,GFXMMU LUT entry 142 low" hexmask.long.byte 0x470 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x470 8.--15. 1. "FVB,First valid block" bitfld.long 0x470 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x474 "GFXMMU_LUT142H,GFXMMU LUT entry 142 high" hexmask.long.tbyte 0x474 0.--17. 1. "LO,Line offset" line.long 0x478 "GFXMMU_LUT143L,GFXMMU LUT entry 143 low" hexmask.long.byte 0x478 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x478 8.--15. 1. "FVB,First valid block" bitfld.long 0x478 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x47C "GFXMMU_LUT143H,GFXMMU LUT entry 143 high" hexmask.long.tbyte 0x47C 0.--17. 1. "LO,Line offset" line.long 0x480 "GFXMMU_LUT144L,GFXMMU LUT entry 144 low" hexmask.long.byte 0x480 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x480 8.--15. 1. "FVB,First valid block" bitfld.long 0x480 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x484 "GFXMMU_LUT144H,GFXMMU LUT entry 144 high" hexmask.long.tbyte 0x484 0.--17. 1. "LO,Line offset" line.long 0x488 "GFXMMU_LUT145L,GFXMMU LUT entry 145 low" hexmask.long.byte 0x488 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x488 8.--15. 1. "FVB,First valid block" bitfld.long 0x488 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x48C "GFXMMU_LUT145H,GFXMMU LUT entry 145 high" hexmask.long.tbyte 0x48C 0.--17. 1. "LO,Line offset" line.long 0x490 "GFXMMU_LUT146L,GFXMMU LUT entry 146 low" hexmask.long.byte 0x490 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x490 8.--15. 1. "FVB,First valid block" bitfld.long 0x490 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x494 "GFXMMU_LUT146H,GFXMMU LUT entry 146 high" hexmask.long.tbyte 0x494 0.--17. 1. "LO,Line offset" line.long 0x498 "GFXMMU_LUT147L,GFXMMU LUT entry 147 low" hexmask.long.byte 0x498 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x498 8.--15. 1. "FVB,First valid block" bitfld.long 0x498 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x49C "GFXMMU_LUT147H,GFXMMU LUT entry 147 high" hexmask.long.tbyte 0x49C 0.--17. 1. "LO,Line offset" line.long 0x4A0 "GFXMMU_LUT148L,GFXMMU LUT entry 148 low" hexmask.long.byte 0x4A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4A4 "GFXMMU_LUT148H,GFXMMU LUT entry 148 high" hexmask.long.tbyte 0x4A4 0.--17. 1. "LO,Line offset" line.long 0x4A8 "GFXMMU_LUT149L,GFXMMU LUT entry 149 low" hexmask.long.byte 0x4A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4AC "GFXMMU_LUT149H,GFXMMU LUT entry 149 high" hexmask.long.tbyte 0x4AC 0.--17. 1. "LO,Line offset" line.long 0x4B0 "GFXMMU_LUT150L,GFXMMU LUT entry 150 low" hexmask.long.byte 0x4B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4B4 "GFXMMU_LUT150H,GFXMMU LUT entry 150 high" hexmask.long.tbyte 0x4B4 0.--17. 1. "LO,Line offset" line.long 0x4B8 "GFXMMU_LUT151L,GFXMMU LUT entry 151 low" hexmask.long.byte 0x4B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4BC "GFXMMU_LUT151H,GFXMMU LUT entry 151 high" hexmask.long.tbyte 0x4BC 0.--17. 1. "LO,Line offset" line.long 0x4C0 "GFXMMU_LUT152L,GFXMMU LUT entry 152 low" hexmask.long.byte 0x4C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C4 "GFXMMU_LUT152H,GFXMMU LUT entry 152 high" hexmask.long.tbyte 0x4C4 0.--17. 1. "LO,Line offset" line.long 0x4C8 "GFXMMU_LUT153L,GFXMMU LUT entry 153 low" hexmask.long.byte 0x4C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4CC "GFXMMU_LUT153H,GFXMMU LUT entry 153 high" hexmask.long.tbyte 0x4CC 0.--17. 1. "LO,Line offset" line.long 0x4D0 "GFXMMU_LUT154L,GFXMMU LUT entry 154 low" hexmask.long.byte 0x4D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4D4 "GFXMMU_LUT154H,GFXMMU LUT entry 154 high" hexmask.long.tbyte 0x4D4 0.--17. 1. "LO,Line offset" line.long 0x4D8 "GFXMMU_LUT155L,GFXMMU LUT entry 155 low" hexmask.long.byte 0x4D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4DC "GFXMMU_LUT155H,GFXMMU LUT entry 155 high" hexmask.long.tbyte 0x4DC 0.--17. 1. "LO,Line offset" line.long 0x4E0 "GFXMMU_LUT156L,GFXMMU LUT entry 156 low" hexmask.long.byte 0x4E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4E4 "GFXMMU_LUT156H,GFXMMU LUT entry 156 high" hexmask.long.tbyte 0x4E4 0.--17. 1. "LO,Line offset" line.long 0x4E8 "GFXMMU_LUT157L,GFXMMU LUT entry 157 low" hexmask.long.byte 0x4E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4EC "GFXMMU_LUT157H,GFXMMU LUT entry 157 high" hexmask.long.tbyte 0x4EC 0.--17. 1. "LO,Line offset" line.long 0x4F0 "GFXMMU_LUT158L,GFXMMU LUT entry 158 low" hexmask.long.byte 0x4F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4F4 "GFXMMU_LUT158H,GFXMMU LUT entry 158 high" hexmask.long.tbyte 0x4F4 0.--17. 1. "LO,Line offset" line.long 0x4F8 "GFXMMU_LUT159L,GFXMMU LUT entry 159 low" hexmask.long.byte 0x4F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4FC "GFXMMU_LUT159H,GFXMMU LUT entry 159 high" hexmask.long.tbyte 0x4FC 0.--17. 1. "LO,Line offset" line.long 0x500 "GFXMMU_LUT160L,GFXMMU LUT entry 160 low" hexmask.long.byte 0x500 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x500 8.--15. 1. "FVB,First valid block" bitfld.long 0x500 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x504 "GFXMMU_LUT160H,GFXMMU LUT entry 160 high" hexmask.long.tbyte 0x504 0.--17. 1. "LO,Line offset" line.long 0x508 "GFXMMU_LUT161L,GFXMMU LUT entry 161 low" hexmask.long.byte 0x508 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x508 8.--15. 1. "FVB,First valid block" bitfld.long 0x508 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x50C "GFXMMU_LUT161H,GFXMMU LUT entry 161 high" hexmask.long.tbyte 0x50C 0.--17. 1. "LO,Line offset" line.long 0x510 "GFXMMU_LUT162L,GFXMMU LUT entry 162 low" hexmask.long.byte 0x510 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x510 8.--15. 1. "FVB,First valid block" bitfld.long 0x510 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x514 "GFXMMU_LUT162H,GFXMMU LUT entry 162 high" hexmask.long.tbyte 0x514 0.--17. 1. "LO,Line offset" line.long 0x518 "GFXMMU_LUT163L,GFXMMU LUT entry 163 low" hexmask.long.byte 0x518 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x518 8.--15. 1. "FVB,First valid block" bitfld.long 0x518 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x51C "GFXMMU_LUT163H,GFXMMU LUT entry 163 high" hexmask.long.tbyte 0x51C 0.--17. 1. "LO,Line offset" line.long 0x520 "GFXMMU_LUT164L,GFXMMU LUT entry 164 low" hexmask.long.byte 0x520 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x520 8.--15. 1. "FVB,First valid block" bitfld.long 0x520 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x524 "GFXMMU_LUT164H,GFXMMU LUT entry 164 high" hexmask.long.tbyte 0x524 0.--17. 1. "LO,Line offset" line.long 0x528 "GFXMMU_LUT165L,GFXMMU LUT entry 165 low" hexmask.long.byte 0x528 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x528 8.--15. 1. "FVB,First valid block" bitfld.long 0x528 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x52C "GFXMMU_LUT165H,GFXMMU LUT entry 165 high" hexmask.long.tbyte 0x52C 0.--17. 1. "LO,Line offset" line.long 0x530 "GFXMMU_LUT166L,GFXMMU LUT entry 166 low" hexmask.long.byte 0x530 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x530 8.--15. 1. "FVB,First valid block" bitfld.long 0x530 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x534 "GFXMMU_LUT166H,GFXMMU LUT entry 166 high" hexmask.long.tbyte 0x534 0.--17. 1. "LO,Line offset" line.long 0x538 "GFXMMU_LUT167L,GFXMMU LUT entry 167 low" hexmask.long.byte 0x538 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x538 8.--15. 1. "FVB,First valid block" bitfld.long 0x538 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x53C "GFXMMU_LUT167H,GFXMMU LUT entry 167 high" hexmask.long.tbyte 0x53C 0.--17. 1. "LO,Line offset" line.long 0x540 "GFXMMU_LUT168L,GFXMMU LUT entry 168 low" hexmask.long.byte 0x540 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x540 8.--15. 1. "FVB,First valid block" bitfld.long 0x540 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x544 "GFXMMU_LUT168H,GFXMMU LUT entry 168 high" hexmask.long.tbyte 0x544 0.--17. 1. "LO,Line offset" line.long 0x548 "GFXMMU_LUT169L,GFXMMU LUT entry 169 low" hexmask.long.byte 0x548 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x548 8.--15. 1. "FVB,First valid block" bitfld.long 0x548 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54C "GFXMMU_LUT169H,GFXMMU LUT entry 169 high" hexmask.long.tbyte 0x54C 0.--17. 1. "LO,Line offset" line.long 0x550 "GFXMMU_LUT170L,GFXMMU LUT entry 170 low" hexmask.long.byte 0x550 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x550 8.--15. 1. "FVB,First valid block" bitfld.long 0x550 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x554 "GFXMMU_LUT170H,GFXMMU LUT entry 170 high" hexmask.long.tbyte 0x554 0.--17. 1. "LO,Line offset" line.long 0x558 "GFXMMU_LUT171L,GFXMMU LUT entry 171 low" hexmask.long.byte 0x558 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x558 8.--15. 1. "FVB,First valid block" bitfld.long 0x558 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x55C "GFXMMU_LUT171H,GFXMMU LUT entry 171 high" hexmask.long.tbyte 0x55C 0.--17. 1. "LO,Line offset" line.long 0x560 "GFXMMU_LUT172L,GFXMMU LUT entry 172 low" hexmask.long.byte 0x560 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x560 8.--15. 1. "FVB,First valid block" bitfld.long 0x560 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x564 "GFXMMU_LUT172H,GFXMMU LUT entry 172 high" hexmask.long.tbyte 0x564 0.--17. 1. "LO,Line offset" line.long 0x568 "GFXMMU_LUT173L,GFXMMU LUT entry 173 low" hexmask.long.byte 0x568 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x568 8.--15. 1. "FVB,First valid block" bitfld.long 0x568 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x56C "GFXMMU_LUT173H,GFXMMU LUT entry 173 high" hexmask.long.tbyte 0x56C 0.--17. 1. "LO,Line offset" line.long 0x570 "GFXMMU_LUT174L,GFXMMU LUT entry 174 low" hexmask.long.byte 0x570 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x570 8.--15. 1. "FVB,First valid block" bitfld.long 0x570 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x574 "GFXMMU_LUT174H,GFXMMU LUT entry 174 high" hexmask.long.tbyte 0x574 0.--17. 1. "LO,Line offset" line.long 0x578 "GFXMMU_LUT175L,GFXMMU LUT entry 175 low" hexmask.long.byte 0x578 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x578 8.--15. 1. "FVB,First valid block" bitfld.long 0x578 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x57C "GFXMMU_LUT175H,GFXMMU LUT entry 175 high" hexmask.long.tbyte 0x57C 0.--17. 1. "LO,Line offset" line.long 0x580 "GFXMMU_LUT176L,GFXMMU LUT entry 176 low" hexmask.long.byte 0x580 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x580 8.--15. 1. "FVB,First valid block" bitfld.long 0x580 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x584 "GFXMMU_LUT176H,GFXMMU LUT entry 176 high" hexmask.long.tbyte 0x584 0.--17. 1. "LO,Line offset" line.long 0x588 "GFXMMU_LUT177L,GFXMMU LUT entry 177 low" hexmask.long.byte 0x588 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x588 8.--15. 1. "FVB,First valid block" bitfld.long 0x588 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x58C "GFXMMU_LUT177H,GFXMMU LUT entry 177 high" hexmask.long.tbyte 0x58C 0.--17. 1. "LO,Line offset" line.long 0x590 "GFXMMU_LUT178L,GFXMMU LUT entry 178 low" hexmask.long.byte 0x590 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x590 8.--15. 1. "FVB,First valid block" bitfld.long 0x590 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x594 "GFXMMU_LUT178H,GFXMMU LUT entry 178 high" hexmask.long.tbyte 0x594 0.--17. 1. "LO,Line offset" line.long 0x598 "GFXMMU_LUT179L,GFXMMU LUT entry 179 low" hexmask.long.byte 0x598 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x598 8.--15. 1. "FVB,First valid block" bitfld.long 0x598 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x59C "GFXMMU_LUT179H,GFXMMU LUT entry 179 high" hexmask.long.tbyte 0x59C 0.--17. 1. "LO,Line offset" line.long 0x5A0 "GFXMMU_LUT180L,GFXMMU LUT entry 180 low" hexmask.long.byte 0x5A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5A4 "GFXMMU_LUT180H,GFXMMU LUT entry 180 high" hexmask.long.tbyte 0x5A4 0.--17. 1. "LO,Line offset" line.long 0x5A8 "GFXMMU_LUT181L,GFXMMU LUT entry 181 low" hexmask.long.byte 0x5A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5AC "GFXMMU_LUT181H,GFXMMU LUT entry 181 high" hexmask.long.tbyte 0x5AC 0.--17. 1. "LO,Line offset" line.long 0x5B0 "GFXMMU_LUT182L,GFXMMU LUT entry 182 low" hexmask.long.byte 0x5B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5B4 "GFXMMU_LUT182H,GFXMMU LUT entry 182 high" hexmask.long.tbyte 0x5B4 0.--17. 1. "LO,Line offset" line.long 0x5B8 "GFXMMU_LUT183L,GFXMMU LUT entry 183 low" hexmask.long.byte 0x5B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5BC "GFXMMU_LUT183H,GFXMMU LUT entry 183 high" hexmask.long.tbyte 0x5BC 0.--17. 1. "LO,Line offset" line.long 0x5C0 "GFXMMU_LUT184L,GFXMMU LUT entry 184 low" hexmask.long.byte 0x5C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C4 "GFXMMU_LUT184H,GFXMMU LUT entry 184 high" hexmask.long.tbyte 0x5C4 0.--17. 1. "LO,Line offset" line.long 0x5C8 "GFXMMU_LUT185L,GFXMMU LUT entry 185 low" hexmask.long.byte 0x5C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5CC "GFXMMU_LUT185H,GFXMMU LUT entry 185 high" hexmask.long.tbyte 0x5CC 0.--17. 1. "LO,Line offset" line.long 0x5D0 "GFXMMU_LUT186L,GFXMMU LUT entry 186 low" hexmask.long.byte 0x5D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5D4 "GFXMMU_LUT186H,GFXMMU LUT entry 186 high" hexmask.long.tbyte 0x5D4 0.--17. 1. "LO,Line offset" line.long 0x5D8 "GFXMMU_LUT187L,GFXMMU LUT entry 187 low" hexmask.long.byte 0x5D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5DC "GFXMMU_LUT187H,GFXMMU LUT entry 187 high" hexmask.long.tbyte 0x5DC 0.--17. 1. "LO,Line offset" line.long 0x5E0 "GFXMMU_LUT188L,GFXMMU LUT entry 188 low" hexmask.long.byte 0x5E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5E4 "GFXMMU_LUT188H,GFXMMU LUT entry 188 high" hexmask.long.tbyte 0x5E4 0.--17. 1. "LO,Line offset" line.long 0x5E8 "GFXMMU_LUT189L,GFXMMU LUT entry 189 low" hexmask.long.byte 0x5E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5EC "GFXMMU_LUT189H,GFXMMU LUT entry 189 high" hexmask.long.tbyte 0x5EC 0.--17. 1. "LO,Line offset" line.long 0x5F0 "GFXMMU_LUT190L,GFXMMU LUT entry 190 low" hexmask.long.byte 0x5F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5F4 "GFXMMU_LUT190H,GFXMMU LUT entry 190 high" hexmask.long.tbyte 0x5F4 0.--17. 1. "LO,Line offset" line.long 0x5F8 "GFXMMU_LUT191L,GFXMMU LUT entry 191 low" hexmask.long.byte 0x5F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5FC "GFXMMU_LUT191H,GFXMMU LUT entry 191 high" hexmask.long.tbyte 0x5FC 0.--17. 1. "LO,Line offset" line.long 0x600 "GFXMMU_LUT192L,GFXMMU LUT entry 192 low" hexmask.long.byte 0x600 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x600 8.--15. 1. "FVB,First valid block" bitfld.long 0x600 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x604 "GFXMMU_LUT192H,GFXMMU LUT entry 192 high" hexmask.long.tbyte 0x604 0.--17. 1. "LO,Line offset" line.long 0x608 "GFXMMU_LUT193L,GFXMMU LUT entry 193 low" hexmask.long.byte 0x608 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x608 8.--15. 1. "FVB,First valid block" bitfld.long 0x608 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x60C "GFXMMU_LUT193H,GFXMMU LUT entry 193 high" hexmask.long.tbyte 0x60C 0.--17. 1. "LO,Line offset" line.long 0x610 "GFXMMU_LUT194L,GFXMMU LUT entry 194 low" hexmask.long.byte 0x610 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x610 8.--15. 1. "FVB,First valid block" bitfld.long 0x610 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x614 "GFXMMU_LUT194H,GFXMMU LUT entry 194 high" hexmask.long.tbyte 0x614 0.--17. 1. "LO,Line offset" line.long 0x618 "GFXMMU_LUT195L,GFXMMU LUT entry 195 low" hexmask.long.byte 0x618 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x618 8.--15. 1. "FVB,First valid block" bitfld.long 0x618 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x61C "GFXMMU_LUT195H,GFXMMU LUT entry 195 high" hexmask.long.tbyte 0x61C 0.--17. 1. "LO,Line offset" line.long 0x620 "GFXMMU_LUT196L,GFXMMU LUT entry 196 low" hexmask.long.byte 0x620 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x620 8.--15. 1. "FVB,First valid block" bitfld.long 0x620 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x624 "GFXMMU_LUT196H,GFXMMU LUT entry 196 high" hexmask.long.tbyte 0x624 0.--17. 1. "LO,Line offset" line.long 0x628 "GFXMMU_LUT197L,GFXMMU LUT entry 197 low" hexmask.long.byte 0x628 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x628 8.--15. 1. "FVB,First valid block" bitfld.long 0x628 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x62C "GFXMMU_LUT197H,GFXMMU LUT entry 197 high" hexmask.long.tbyte 0x62C 0.--17. 1. "LO,Line offset" line.long 0x630 "GFXMMU_LUT198L,GFXMMU LUT entry 198 low" hexmask.long.byte 0x630 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x630 8.--15. 1. "FVB,First valid block" bitfld.long 0x630 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x634 "GFXMMU_LUT198H,GFXMMU LUT entry 198 high" hexmask.long.tbyte 0x634 0.--17. 1. "LO,Line offset" line.long 0x638 "GFXMMU_LUT199L,GFXMMU LUT entry 199 low" hexmask.long.byte 0x638 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x638 8.--15. 1. "FVB,First valid block" bitfld.long 0x638 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x63C "GFXMMU_LUT199H,GFXMMU LUT entry 199 high" hexmask.long.tbyte 0x63C 0.--17. 1. "LO,Line offset" line.long 0x640 "GFXMMU_LUT200L,GFXMMU LUT entry 200 low" hexmask.long.byte 0x640 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x640 8.--15. 1. "FVB,First valid block" bitfld.long 0x640 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x644 "GFXMMU_LUT200H,GFXMMU LUT entry 200 high" hexmask.long.tbyte 0x644 0.--17. 1. "LO,Line offset" line.long 0x648 "GFXMMU_LUT201L,GFXMMU LUT entry 201 low" hexmask.long.byte 0x648 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x648 8.--15. 1. "FVB,First valid block" bitfld.long 0x648 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64C "GFXMMU_LUT201H,GFXMMU LUT entry 201 high" hexmask.long.tbyte 0x64C 0.--17. 1. "LO,Line offset" line.long 0x650 "GFXMMU_LUT202L,GFXMMU LUT entry 202 low" hexmask.long.byte 0x650 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x650 8.--15. 1. "FVB,First valid block" bitfld.long 0x650 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x654 "GFXMMU_LUT202H,GFXMMU LUT entry 202 high" hexmask.long.tbyte 0x654 0.--17. 1. "LO,Line offset" line.long 0x658 "GFXMMU_LUT203L,GFXMMU LUT entry 203 low" hexmask.long.byte 0x658 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x658 8.--15. 1. "FVB,First valid block" bitfld.long 0x658 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x65C "GFXMMU_LUT203H,GFXMMU LUT entry 203 high" hexmask.long.tbyte 0x65C 0.--17. 1. "LO,Line offset" line.long 0x660 "GFXMMU_LUT204L,GFXMMU LUT entry 204 low" hexmask.long.byte 0x660 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x660 8.--15. 1. "FVB,First valid block" bitfld.long 0x660 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x664 "GFXMMU_LUT204H,GFXMMU LUT entry 204 high" hexmask.long.tbyte 0x664 0.--17. 1. "LO,Line offset" line.long 0x668 "GFXMMU_LUT205L,GFXMMU LUT entry 205 low" hexmask.long.byte 0x668 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x668 8.--15. 1. "FVB,First valid block" bitfld.long 0x668 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x66C "GFXMMU_LUT205H,GFXMMU LUT entry 205 high" hexmask.long.tbyte 0x66C 0.--17. 1. "LO,Line offset" line.long 0x670 "GFXMMU_LUT206L,GFXMMU LUT entry 206 low" hexmask.long.byte 0x670 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x670 8.--15. 1. "FVB,First valid block" bitfld.long 0x670 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x674 "GFXMMU_LUT206H,GFXMMU LUT entry 206 high" hexmask.long.tbyte 0x674 0.--17. 1. "LO,Line offset" line.long 0x678 "GFXMMU_LUT207L,GFXMMU LUT entry 207 low" hexmask.long.byte 0x678 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x678 8.--15. 1. "FVB,First valid block" bitfld.long 0x678 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x67C "GFXMMU_LUT207H,GFXMMU LUT entry 207 high" hexmask.long.tbyte 0x67C 0.--17. 1. "LO,Line offset" line.long 0x680 "GFXMMU_LUT208L,GFXMMU LUT entry 208 low" hexmask.long.byte 0x680 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x680 8.--15. 1. "FVB,First valid block" bitfld.long 0x680 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x684 "GFXMMU_LUT208H,GFXMMU LUT entry 208 high" hexmask.long.tbyte 0x684 0.--17. 1. "LO,Line offset" line.long 0x688 "GFXMMU_LUT209L,GFXMMU LUT entry 209 low" hexmask.long.byte 0x688 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x688 8.--15. 1. "FVB,First valid block" bitfld.long 0x688 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x68C "GFXMMU_LUT209H,GFXMMU LUT entry 209 high" hexmask.long.tbyte 0x68C 0.--17. 1. "LO,Line offset" line.long 0x690 "GFXMMU_LUT210L,GFXMMU LUT entry 210 low" hexmask.long.byte 0x690 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x690 8.--15. 1. "FVB,First valid block" bitfld.long 0x690 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x694 "GFXMMU_LUT210H,GFXMMU LUT entry 210 high" hexmask.long.tbyte 0x694 0.--17. 1. "LO,Line offset" line.long 0x698 "GFXMMU_LUT211L,GFXMMU LUT entry 211 low" hexmask.long.byte 0x698 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x698 8.--15. 1. "FVB,First valid block" bitfld.long 0x698 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x69C "GFXMMU_LUT211H,GFXMMU LUT entry 211 high" hexmask.long.tbyte 0x69C 0.--17. 1. "LO,Line offset" line.long 0x6A0 "GFXMMU_LUT212L,GFXMMU LUT entry 212 low" hexmask.long.byte 0x6A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6A4 "GFXMMU_LUT212H,GFXMMU LUT entry 212 high" hexmask.long.tbyte 0x6A4 0.--17. 1. "LO,Line offset" line.long 0x6A8 "GFXMMU_LUT213L,GFXMMU LUT entry 213 low" hexmask.long.byte 0x6A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6AC "GFXMMU_LUT213H,GFXMMU LUT entry 213 high" hexmask.long.tbyte 0x6AC 0.--17. 1. "LO,Line offset" line.long 0x6B0 "GFXMMU_LUT214L,GFXMMU LUT entry 214 low" hexmask.long.byte 0x6B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6B4 "GFXMMU_LUT214H,GFXMMU LUT entry 214 high" hexmask.long.tbyte 0x6B4 0.--17. 1. "LO,Line offset" line.long 0x6B8 "GFXMMU_LUT215L,GFXMMU LUT entry 215 low" hexmask.long.byte 0x6B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6BC "GFXMMU_LUT215H,GFXMMU LUT entry 215 high" hexmask.long.tbyte 0x6BC 0.--17. 1. "LO,Line offset" line.long 0x6C0 "GFXMMU_LUT216L,GFXMMU LUT entry 216 low" hexmask.long.byte 0x6C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C4 "GFXMMU_LUT216H,GFXMMU LUT entry 216 high" hexmask.long.tbyte 0x6C4 0.--17. 1. "LO,Line offset" line.long 0x6C8 "GFXMMU_LUT217L,GFXMMU LUT entry 217 low" hexmask.long.byte 0x6C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6CC "GFXMMU_LUT217H,GFXMMU LUT entry 217 high" hexmask.long.tbyte 0x6CC 0.--17. 1. "LO,Line offset" line.long 0x6D0 "GFXMMU_LUT218L,GFXMMU LUT entry 218 low" hexmask.long.byte 0x6D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6D4 "GFXMMU_LUT218H,GFXMMU LUT entry 218 high" hexmask.long.tbyte 0x6D4 0.--17. 1. "LO,Line offset" line.long 0x6D8 "GFXMMU_LUT219L,GFXMMU LUT entry 219 low" hexmask.long.byte 0x6D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6DC "GFXMMU_LUT219H,GFXMMU LUT entry 219 high" hexmask.long.tbyte 0x6DC 0.--17. 1. "LO,Line offset" line.long 0x6E0 "GFXMMU_LUT220L,GFXMMU LUT entry 220 low" hexmask.long.byte 0x6E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6E4 "GFXMMU_LUT220H,GFXMMU LUT entry 220 high" hexmask.long.tbyte 0x6E4 0.--17. 1. "LO,Line offset" line.long 0x6E8 "GFXMMU_LUT221L,GFXMMU LUT entry 221 low" hexmask.long.byte 0x6E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6EC "GFXMMU_LUT221H,GFXMMU LUT entry 221 high" hexmask.long.tbyte 0x6EC 0.--17. 1. "LO,Line offset" line.long 0x6F0 "GFXMMU_LUT222L,GFXMMU LUT entry 222 low" hexmask.long.byte 0x6F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6F4 "GFXMMU_LUT222H,GFXMMU LUT entry 222 high" hexmask.long.tbyte 0x6F4 0.--17. 1. "LO,Line offset" line.long 0x6F8 "GFXMMU_LUT223L,GFXMMU LUT entry 223 low" hexmask.long.byte 0x6F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6FC "GFXMMU_LUT223H,GFXMMU LUT entry 223 high" hexmask.long.tbyte 0x6FC 0.--17. 1. "LO,Line offset" line.long 0x700 "GFXMMU_LUT224L,GFXMMU LUT entry 224 low" hexmask.long.byte 0x700 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x700 8.--15. 1. "FVB,First valid block" bitfld.long 0x700 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x704 "GFXMMU_LUT224H,GFXMMU LUT entry 224 high" hexmask.long.tbyte 0x704 0.--17. 1. "LO,Line offset" line.long 0x708 "GFXMMU_LUT225L,GFXMMU LUT entry 225 low" hexmask.long.byte 0x708 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x708 8.--15. 1. "FVB,First valid block" bitfld.long 0x708 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x70C "GFXMMU_LUT225H,GFXMMU LUT entry 225 high" hexmask.long.tbyte 0x70C 0.--17. 1. "LO,Line offset" line.long 0x710 "GFXMMU_LUT226L,GFXMMU LUT entry 226 low" hexmask.long.byte 0x710 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x710 8.--15. 1. "FVB,First valid block" bitfld.long 0x710 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x714 "GFXMMU_LUT226H,GFXMMU LUT entry 226 high" hexmask.long.tbyte 0x714 0.--17. 1. "LO,Line offset" line.long 0x718 "GFXMMU_LUT227L,GFXMMU LUT entry 227 low" hexmask.long.byte 0x718 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x718 8.--15. 1. "FVB,First valid block" bitfld.long 0x718 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x71C "GFXMMU_LUT227H,GFXMMU LUT entry 227 high" hexmask.long.tbyte 0x71C 0.--17. 1. "LO,Line offset" line.long 0x720 "GFXMMU_LUT228L,GFXMMU LUT entry 228 low" hexmask.long.byte 0x720 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x720 8.--15. 1. "FVB,First valid block" bitfld.long 0x720 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x724 "GFXMMU_LUT228H,GFXMMU LUT entry 228 high" hexmask.long.tbyte 0x724 0.--17. 1. "LO,Line offset" line.long 0x728 "GFXMMU_LUT229L,GFXMMU LUT entry 229 low" hexmask.long.byte 0x728 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x728 8.--15. 1. "FVB,First valid block" bitfld.long 0x728 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x72C "GFXMMU_LUT229H,GFXMMU LUT entry 229 high" hexmask.long.tbyte 0x72C 0.--17. 1. "LO,Line offset" line.long 0x730 "GFXMMU_LUT230L,GFXMMU LUT entry 230 low" hexmask.long.byte 0x730 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x730 8.--15. 1. "FVB,First valid block" bitfld.long 0x730 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x734 "GFXMMU_LUT230H,GFXMMU LUT entry 230 high" hexmask.long.tbyte 0x734 0.--17. 1. "LO,Line offset" line.long 0x738 "GFXMMU_LUT231L,GFXMMU LUT entry 231 low" hexmask.long.byte 0x738 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x738 8.--15. 1. "FVB,First valid block" bitfld.long 0x738 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x73C "GFXMMU_LUT231H,GFXMMU LUT entry 231 high" hexmask.long.tbyte 0x73C 0.--17. 1. "LO,Line offset" line.long 0x740 "GFXMMU_LUT232L,GFXMMU LUT entry 232 low" hexmask.long.byte 0x740 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x740 8.--15. 1. "FVB,First valid block" bitfld.long 0x740 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x744 "GFXMMU_LUT232H,GFXMMU LUT entry 232 high" hexmask.long.tbyte 0x744 0.--17. 1. "LO,Line offset" line.long 0x748 "GFXMMU_LUT233L,GFXMMU LUT entry 233 low" hexmask.long.byte 0x748 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x748 8.--15. 1. "FVB,First valid block" bitfld.long 0x748 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74C "GFXMMU_LUT233H,GFXMMU LUT entry 233 high" hexmask.long.tbyte 0x74C 0.--17. 1. "LO,Line offset" line.long 0x750 "GFXMMU_LUT234L,GFXMMU LUT entry 234 low" hexmask.long.byte 0x750 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x750 8.--15. 1. "FVB,First valid block" bitfld.long 0x750 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x754 "GFXMMU_LUT234H,GFXMMU LUT entry 234 high" hexmask.long.tbyte 0x754 0.--17. 1. "LO,Line offset" line.long 0x758 "GFXMMU_LUT235L,GFXMMU LUT entry 235 low" hexmask.long.byte 0x758 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x758 8.--15. 1. "FVB,First valid block" bitfld.long 0x758 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x75C "GFXMMU_LUT235H,GFXMMU LUT entry 235 high" hexmask.long.tbyte 0x75C 0.--17. 1. "LO,Line offset" line.long 0x760 "GFXMMU_LUT236L,GFXMMU LUT entry 236 low" hexmask.long.byte 0x760 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x760 8.--15. 1. "FVB,First valid block" bitfld.long 0x760 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x764 "GFXMMU_LUT236H,GFXMMU LUT entry 236 high" hexmask.long.tbyte 0x764 0.--17. 1. "LO,Line offset" line.long 0x768 "GFXMMU_LUT237L,GFXMMU LUT entry 237 low" hexmask.long.byte 0x768 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x768 8.--15. 1. "FVB,First valid block" bitfld.long 0x768 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x76C "GFXMMU_LUT237H,GFXMMU LUT entry 237 high" hexmask.long.tbyte 0x76C 0.--17. 1. "LO,Line offset" line.long 0x770 "GFXMMU_LUT238L,GFXMMU LUT entry 238 low" hexmask.long.byte 0x770 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x770 8.--15. 1. "FVB,First valid block" bitfld.long 0x770 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x774 "GFXMMU_LUT238H,GFXMMU LUT entry 238 high" hexmask.long.tbyte 0x774 0.--17. 1. "LO,Line offset" line.long 0x778 "GFXMMU_LUT239L,GFXMMU LUT entry 239 low" hexmask.long.byte 0x778 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x778 8.--15. 1. "FVB,First valid block" bitfld.long 0x778 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x77C "GFXMMU_LUT239H,GFXMMU LUT entry 239 high" hexmask.long.tbyte 0x77C 0.--17. 1. "LO,Line offset" line.long 0x780 "GFXMMU_LUT240L,GFXMMU LUT entry 240 low" hexmask.long.byte 0x780 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x780 8.--15. 1. "FVB,First valid block" bitfld.long 0x780 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x784 "GFXMMU_LUT240H,GFXMMU LUT entry 240 high" hexmask.long.tbyte 0x784 0.--17. 1. "LO,Line offset" line.long 0x788 "GFXMMU_LUT241L,GFXMMU LUT entry 241 low" hexmask.long.byte 0x788 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x788 8.--15. 1. "FVB,First valid block" bitfld.long 0x788 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x78C "GFXMMU_LUT241H,GFXMMU LUT entry 241 high" hexmask.long.tbyte 0x78C 0.--17. 1. "LO,Line offset" line.long 0x790 "GFXMMU_LUT242L,GFXMMU LUT entry 242 low" hexmask.long.byte 0x790 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x790 8.--15. 1. "FVB,First valid block" bitfld.long 0x790 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x794 "GFXMMU_LUT242H,GFXMMU LUT entry 242 high" hexmask.long.tbyte 0x794 0.--17. 1. "LO,Line offset" line.long 0x798 "GFXMMU_LUT243L,GFXMMU LUT entry 243 low" hexmask.long.byte 0x798 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x798 8.--15. 1. "FVB,First valid block" bitfld.long 0x798 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x79C "GFXMMU_LUT243H,GFXMMU LUT entry 243 high" hexmask.long.tbyte 0x79C 0.--17. 1. "LO,Line offset" line.long 0x7A0 "GFXMMU_LUT244L,GFXMMU LUT entry 244 low" hexmask.long.byte 0x7A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7A4 "GFXMMU_LUT244H,GFXMMU LUT entry 244 high" hexmask.long.tbyte 0x7A4 0.--17. 1. "LO,Line offset" line.long 0x7A8 "GFXMMU_LUT245L,GFXMMU LUT entry 245 low" hexmask.long.byte 0x7A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7AC "GFXMMU_LUT245H,GFXMMU LUT entry 245 high" hexmask.long.tbyte 0x7AC 0.--17. 1. "LO,Line offset" line.long 0x7B0 "GFXMMU_LUT246L,GFXMMU LUT entry 246 low" hexmask.long.byte 0x7B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7B4 "GFXMMU_LUT246H,GFXMMU LUT entry 246 high" hexmask.long.tbyte 0x7B4 0.--17. 1. "LO,Line offset" line.long 0x7B8 "GFXMMU_LUT247L,GFXMMU LUT entry 247 low" hexmask.long.byte 0x7B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7BC "GFXMMU_LUT247H,GFXMMU LUT entry 247 high" hexmask.long.tbyte 0x7BC 0.--17. 1. "LO,Line offset" line.long 0x7C0 "GFXMMU_LUT248L,GFXMMU LUT entry 248 low" hexmask.long.byte 0x7C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C4 "GFXMMU_LUT248H,GFXMMU LUT entry 248 high" hexmask.long.tbyte 0x7C4 0.--17. 1. "LO,Line offset" line.long 0x7C8 "GFXMMU_LUT249L,GFXMMU LUT entry 249 low" hexmask.long.byte 0x7C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7CC "GFXMMU_LUT249H,GFXMMU LUT entry 249 high" hexmask.long.tbyte 0x7CC 0.--17. 1. "LO,Line offset" line.long 0x7D0 "GFXMMU_LUT250L,GFXMMU LUT entry 250 low" hexmask.long.byte 0x7D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7D4 "GFXMMU_LUT250H,GFXMMU LUT entry 250 high" hexmask.long.tbyte 0x7D4 0.--17. 1. "LO,Line offset" line.long 0x7D8 "GFXMMU_LUT251L,GFXMMU LUT entry 251 low" hexmask.long.byte 0x7D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7DC "GFXMMU_LUT251H,GFXMMU LUT entry 251 high" hexmask.long.tbyte 0x7DC 0.--17. 1. "LO,Line offset" line.long 0x7E0 "GFXMMU_LUT252L,GFXMMU LUT entry 252 low" hexmask.long.byte 0x7E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7E4 "GFXMMU_LUT252H,GFXMMU LUT entry 252 high" hexmask.long.tbyte 0x7E4 0.--17. 1. "LO,Line offset" line.long 0x7E8 "GFXMMU_LUT253L,GFXMMU LUT entry 253 low" hexmask.long.byte 0x7E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7EC "GFXMMU_LUT253H,GFXMMU LUT entry 253 high" hexmask.long.tbyte 0x7EC 0.--17. 1. "LO,Line offset" line.long 0x7F0 "GFXMMU_LUT254L,GFXMMU LUT entry 254 low" hexmask.long.byte 0x7F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7F4 "GFXMMU_LUT254H,GFXMMU LUT entry 254 high" hexmask.long.tbyte 0x7F4 0.--17. 1. "LO,Line offset" line.long 0x7F8 "GFXMMU_LUT255L,GFXMMU LUT entry 255 low" hexmask.long.byte 0x7F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7FC "GFXMMU_LUT255H,GFXMMU LUT entry 255 high" hexmask.long.tbyte 0x7FC 0.--17. 1. "LO,Line offset" line.long 0x800 "GFXMMU_LUT256L,GFXMMU LUT entry 256 low" hexmask.long.byte 0x800 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x800 8.--15. 1. "FVB,First valid block" bitfld.long 0x800 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x804 "GFXMMU_LUT256H,GFXMMU LUT entry 256 high" hexmask.long.tbyte 0x804 0.--17. 1. "LO,Line offset" line.long 0x808 "GFXMMU_LUT257L,GFXMMU LUT entry 257 low" hexmask.long.byte 0x808 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x808 8.--15. 1. "FVB,First valid block" bitfld.long 0x808 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x80C "GFXMMU_LUT257H,GFXMMU LUT entry 257 high" hexmask.long.tbyte 0x80C 0.--17. 1. "LO,Line offset" line.long 0x810 "GFXMMU_LUT258L,GFXMMU LUT entry 258 low" hexmask.long.byte 0x810 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x810 8.--15. 1. "FVB,First valid block" bitfld.long 0x810 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x814 "GFXMMU_LUT258H,GFXMMU LUT entry 258 high" hexmask.long.tbyte 0x814 0.--17. 1. "LO,Line offset" line.long 0x818 "GFXMMU_LUT259L,GFXMMU LUT entry 259 low" hexmask.long.byte 0x818 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x818 8.--15. 1. "FVB,First valid block" bitfld.long 0x818 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x81C "GFXMMU_LUT259H,GFXMMU LUT entry 259 high" hexmask.long.tbyte 0x81C 0.--17. 1. "LO,Line offset" line.long 0x820 "GFXMMU_LUT260L,GFXMMU LUT entry 260 low" hexmask.long.byte 0x820 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x820 8.--15. 1. "FVB,First valid block" bitfld.long 0x820 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x824 "GFXMMU_LUT260H,GFXMMU LUT entry 260 high" hexmask.long.tbyte 0x824 0.--17. 1. "LO,Line offset" line.long 0x828 "GFXMMU_LUT261L,GFXMMU LUT entry 261 low" hexmask.long.byte 0x828 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x828 8.--15. 1. "FVB,First valid block" bitfld.long 0x828 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x82C "GFXMMU_LUT261H,GFXMMU LUT entry 261 high" hexmask.long.tbyte 0x82C 0.--17. 1. "LO,Line offset" line.long 0x830 "GFXMMU_LUT262L,GFXMMU LUT entry 262 low" hexmask.long.byte 0x830 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x830 8.--15. 1. "FVB,First valid block" bitfld.long 0x830 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x834 "GFXMMU_LUT262H,GFXMMU LUT entry 262 high" hexmask.long.tbyte 0x834 0.--17. 1. "LO,Line offset" line.long 0x838 "GFXMMU_LUT263L,GFXMMU LUT entry 263 low" hexmask.long.byte 0x838 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x838 8.--15. 1. "FVB,First valid block" bitfld.long 0x838 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x83C "GFXMMU_LUT263H,GFXMMU LUT entry 263 high" hexmask.long.tbyte 0x83C 0.--17. 1. "LO,Line offset" line.long 0x840 "GFXMMU_LUT264L,GFXMMU LUT entry 264 low" hexmask.long.byte 0x840 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x840 8.--15. 1. "FVB,First valid block" bitfld.long 0x840 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x844 "GFXMMU_LUT264H,GFXMMU LUT entry 264 high" hexmask.long.tbyte 0x844 0.--17. 1. "LO,Line offset" line.long 0x848 "GFXMMU_LUT265L,GFXMMU LUT entry 265 low" hexmask.long.byte 0x848 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x848 8.--15. 1. "FVB,First valid block" bitfld.long 0x848 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84C "GFXMMU_LUT265H,GFXMMU LUT entry 265 high" hexmask.long.tbyte 0x84C 0.--17. 1. "LO,Line offset" line.long 0x850 "GFXMMU_LUT266L,GFXMMU LUT entry 266 low" hexmask.long.byte 0x850 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x850 8.--15. 1. "FVB,First valid block" bitfld.long 0x850 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x854 "GFXMMU_LUT266H,GFXMMU LUT entry 266 high" hexmask.long.tbyte 0x854 0.--17. 1. "LO,Line offset" line.long 0x858 "GFXMMU_LUT267L,GFXMMU LUT entry 267 low" hexmask.long.byte 0x858 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x858 8.--15. 1. "FVB,First valid block" bitfld.long 0x858 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x85C "GFXMMU_LUT267H,GFXMMU LUT entry 267 high" hexmask.long.tbyte 0x85C 0.--17. 1. "LO,Line offset" line.long 0x860 "GFXMMU_LUT268L,GFXMMU LUT entry 268 low" hexmask.long.byte 0x860 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x860 8.--15. 1. "FVB,First valid block" bitfld.long 0x860 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x864 "GFXMMU_LUT268H,GFXMMU LUT entry 268 high" hexmask.long.tbyte 0x864 0.--17. 1. "LO,Line offset" line.long 0x868 "GFXMMU_LUT269L,GFXMMU LUT entry 269 low" hexmask.long.byte 0x868 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x868 8.--15. 1. "FVB,First valid block" bitfld.long 0x868 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x86C "GFXMMU_LUT269H,GFXMMU LUT entry 269 high" hexmask.long.tbyte 0x86C 0.--17. 1. "LO,Line offset" line.long 0x870 "GFXMMU_LUT270L,GFXMMU LUT entry 270 low" hexmask.long.byte 0x870 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x870 8.--15. 1. "FVB,First valid block" bitfld.long 0x870 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x874 "GFXMMU_LUT270H,GFXMMU LUT entry 270 high" hexmask.long.tbyte 0x874 0.--17. 1. "LO,Line offset" line.long 0x878 "GFXMMU_LUT271L,GFXMMU LUT entry 271 low" hexmask.long.byte 0x878 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x878 8.--15. 1. "FVB,First valid block" bitfld.long 0x878 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x87C "GFXMMU_LUT271H,GFXMMU LUT entry 271 high" hexmask.long.tbyte 0x87C 0.--17. 1. "LO,Line offset" line.long 0x880 "GFXMMU_LUT272L,GFXMMU LUT entry 272 low" hexmask.long.byte 0x880 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x880 8.--15. 1. "FVB,First valid block" bitfld.long 0x880 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x884 "GFXMMU_LUT272H,GFXMMU LUT entry 272 high" hexmask.long.tbyte 0x884 0.--17. 1. "LO,Line offset" line.long 0x888 "GFXMMU_LUT273L,GFXMMU LUT entry 273 low" hexmask.long.byte 0x888 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x888 8.--15. 1. "FVB,First valid block" bitfld.long 0x888 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x88C "GFXMMU_LUT273H,GFXMMU LUT entry 273 high" hexmask.long.tbyte 0x88C 0.--17. 1. "LO,Line offset" line.long 0x890 "GFXMMU_LUT274L,GFXMMU LUT entry 274 low" hexmask.long.byte 0x890 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x890 8.--15. 1. "FVB,First valid block" bitfld.long 0x890 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x894 "GFXMMU_LUT274H,GFXMMU LUT entry 274 high" hexmask.long.tbyte 0x894 0.--17. 1. "LO,Line offset" line.long 0x898 "GFXMMU_LUT275L,GFXMMU LUT entry 275 low" hexmask.long.byte 0x898 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x898 8.--15. 1. "FVB,First valid block" bitfld.long 0x898 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x89C "GFXMMU_LUT275H,GFXMMU LUT entry 275 high" hexmask.long.tbyte 0x89C 0.--17. 1. "LO,Line offset" line.long 0x8A0 "GFXMMU_LUT276L,GFXMMU LUT entry 276 low" hexmask.long.byte 0x8A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8A4 "GFXMMU_LUT276H,GFXMMU LUT entry 276 high" hexmask.long.tbyte 0x8A4 0.--17. 1. "LO,Line offset" line.long 0x8A8 "GFXMMU_LUT277L,GFXMMU LUT entry 277 low" hexmask.long.byte 0x8A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8AC "GFXMMU_LUT277H,GFXMMU LUT entry 277 high" hexmask.long.tbyte 0x8AC 0.--17. 1. "LO,Line offset" line.long 0x8B0 "GFXMMU_LUT278L,GFXMMU LUT entry 278 low" hexmask.long.byte 0x8B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8B4 "GFXMMU_LUT278H,GFXMMU LUT entry 278 high" hexmask.long.tbyte 0x8B4 0.--17. 1. "LO,Line offset" line.long 0x8B8 "GFXMMU_LUT279L,GFXMMU LUT entry 279 low" hexmask.long.byte 0x8B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8BC "GFXMMU_LUT279H,GFXMMU LUT entry 279 high" hexmask.long.tbyte 0x8BC 0.--17. 1. "LO,Line offset" line.long 0x8C0 "GFXMMU_LUT280L,GFXMMU LUT entry 280 low" hexmask.long.byte 0x8C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C4 "GFXMMU_LUT280H,GFXMMU LUT entry 280 high" hexmask.long.tbyte 0x8C4 0.--17. 1. "LO,Line offset" line.long 0x8C8 "GFXMMU_LUT281L,GFXMMU LUT entry 281 low" hexmask.long.byte 0x8C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8CC "GFXMMU_LUT281H,GFXMMU LUT entry 281 high" hexmask.long.tbyte 0x8CC 0.--17. 1. "LO,Line offset" line.long 0x8D0 "GFXMMU_LUT282L,GFXMMU LUT entry 282 low" hexmask.long.byte 0x8D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8D4 "GFXMMU_LUT282H,GFXMMU LUT entry 282 high" hexmask.long.tbyte 0x8D4 0.--17. 1. "LO,Line offset" line.long 0x8D8 "GFXMMU_LUT283L,GFXMMU LUT entry 283 low" hexmask.long.byte 0x8D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8DC "GFXMMU_LUT283H,GFXMMU LUT entry 283 high" hexmask.long.tbyte 0x8DC 0.--17. 1. "LO,Line offset" line.long 0x8E0 "GFXMMU_LUT284L,GFXMMU LUT entry 284 low" hexmask.long.byte 0x8E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8E4 "GFXMMU_LUT284H,GFXMMU LUT entry 284 high" hexmask.long.tbyte 0x8E4 0.--17. 1. "LO,Line offset" line.long 0x8E8 "GFXMMU_LUT285L,GFXMMU LUT entry 285 low" hexmask.long.byte 0x8E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8EC "GFXMMU_LUT285H,GFXMMU LUT entry 285 high" hexmask.long.tbyte 0x8EC 0.--17. 1. "LO,Line offset" line.long 0x8F0 "GFXMMU_LUT286L,GFXMMU LUT entry 286 low" hexmask.long.byte 0x8F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8F4 "GFXMMU_LUT286H,GFXMMU LUT entry 286 high" hexmask.long.tbyte 0x8F4 0.--17. 1. "LO,Line offset" line.long 0x8F8 "GFXMMU_LUT287L,GFXMMU LUT entry 287 low" hexmask.long.byte 0x8F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8FC "GFXMMU_LUT287H,GFXMMU LUT entry 287 high" hexmask.long.tbyte 0x8FC 0.--17. 1. "LO,Line offset" line.long 0x900 "GFXMMU_LUT288L,GFXMMU LUT entry 288 low" hexmask.long.byte 0x900 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x900 8.--15. 1. "FVB,First valid block" bitfld.long 0x900 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x904 "GFXMMU_LUT288H,GFXMMU LUT entry 288 high" hexmask.long.tbyte 0x904 0.--17. 1. "LO,Line offset" line.long 0x908 "GFXMMU_LUT289L,GFXMMU LUT entry 289 low" hexmask.long.byte 0x908 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x908 8.--15. 1. "FVB,First valid block" bitfld.long 0x908 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x90C "GFXMMU_LUT289H,GFXMMU LUT entry 289 high" hexmask.long.tbyte 0x90C 0.--17. 1. "LO,Line offset" line.long 0x910 "GFXMMU_LUT290L,GFXMMU LUT entry 290 low" hexmask.long.byte 0x910 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x910 8.--15. 1. "FVB,First valid block" bitfld.long 0x910 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x914 "GFXMMU_LUT290H,GFXMMU LUT entry 290 high" hexmask.long.tbyte 0x914 0.--17. 1. "LO,Line offset" line.long 0x918 "GFXMMU_LUT291L,GFXMMU LUT entry 291 low" hexmask.long.byte 0x918 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x918 8.--15. 1. "FVB,First valid block" bitfld.long 0x918 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x91C "GFXMMU_LUT291H,GFXMMU LUT entry 291 high" hexmask.long.tbyte 0x91C 0.--17. 1. "LO,Line offset" line.long 0x920 "GFXMMU_LUT292L,GFXMMU LUT entry 292 low" hexmask.long.byte 0x920 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x920 8.--15. 1. "FVB,First valid block" bitfld.long 0x920 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x924 "GFXMMU_LUT292H,GFXMMU LUT entry 292 high" hexmask.long.tbyte 0x924 0.--17. 1. "LO,Line offset" line.long 0x928 "GFXMMU_LUT293L,GFXMMU LUT entry 293 low" hexmask.long.byte 0x928 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x928 8.--15. 1. "FVB,First valid block" bitfld.long 0x928 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x92C "GFXMMU_LUT293H,GFXMMU LUT entry 293 high" hexmask.long.tbyte 0x92C 0.--17. 1. "LO,Line offset" line.long 0x930 "GFXMMU_LUT294L,GFXMMU LUT entry 294 low" hexmask.long.byte 0x930 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x930 8.--15. 1. "FVB,First valid block" bitfld.long 0x930 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x934 "GFXMMU_LUT294H,GFXMMU LUT entry 294 high" hexmask.long.tbyte 0x934 0.--17. 1. "LO,Line offset" line.long 0x938 "GFXMMU_LUT295L,GFXMMU LUT entry 295 low" hexmask.long.byte 0x938 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x938 8.--15. 1. "FVB,First valid block" bitfld.long 0x938 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x93C "GFXMMU_LUT295H,GFXMMU LUT entry 295 high" hexmask.long.tbyte 0x93C 0.--17. 1. "LO,Line offset" line.long 0x940 "GFXMMU_LUT296L,GFXMMU LUT entry 296 low" hexmask.long.byte 0x940 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x940 8.--15. 1. "FVB,First valid block" bitfld.long 0x940 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x944 "GFXMMU_LUT296H,GFXMMU LUT entry 296 high" hexmask.long.tbyte 0x944 0.--17. 1. "LO,Line offset" line.long 0x948 "GFXMMU_LUT297L,GFXMMU LUT entry 297 low" hexmask.long.byte 0x948 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x948 8.--15. 1. "FVB,First valid block" bitfld.long 0x948 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94C "GFXMMU_LUT297H,GFXMMU LUT entry 297 high" hexmask.long.tbyte 0x94C 0.--17. 1. "LO,Line offset" line.long 0x950 "GFXMMU_LUT298L,GFXMMU LUT entry 298 low" hexmask.long.byte 0x950 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x950 8.--15. 1. "FVB,First valid block" bitfld.long 0x950 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x954 "GFXMMU_LUT298H,GFXMMU LUT entry 298 high" hexmask.long.tbyte 0x954 0.--17. 1. "LO,Line offset" line.long 0x958 "GFXMMU_LUT299L,GFXMMU LUT entry 299 low" hexmask.long.byte 0x958 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x958 8.--15. 1. "FVB,First valid block" bitfld.long 0x958 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x95C "GFXMMU_LUT299H,GFXMMU LUT entry 299 high" hexmask.long.tbyte 0x95C 0.--17. 1. "LO,Line offset" line.long 0x960 "GFXMMU_LUT300L,GFXMMU LUT entry 300 low" hexmask.long.byte 0x960 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x960 8.--15. 1. "FVB,First valid block" bitfld.long 0x960 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x964 "GFXMMU_LUT300H,GFXMMU LUT entry 300 high" hexmask.long.tbyte 0x964 0.--17. 1. "LO,Line offset" line.long 0x968 "GFXMMU_LUT301L,GFXMMU LUT entry 301 low" hexmask.long.byte 0x968 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x968 8.--15. 1. "FVB,First valid block" bitfld.long 0x968 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x96C "GFXMMU_LUT301H,GFXMMU LUT entry 301 high" hexmask.long.tbyte 0x96C 0.--17. 1. "LO,Line offset" line.long 0x970 "GFXMMU_LUT302L,GFXMMU LUT entry 302 low" hexmask.long.byte 0x970 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x970 8.--15. 1. "FVB,First valid block" bitfld.long 0x970 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x974 "GFXMMU_LUT302H,GFXMMU LUT entry 302 high" hexmask.long.tbyte 0x974 0.--17. 1. "LO,Line offset" line.long 0x978 "GFXMMU_LUT303L,GFXMMU LUT entry 303 low" hexmask.long.byte 0x978 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x978 8.--15. 1. "FVB,First valid block" bitfld.long 0x978 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x97C "GFXMMU_LUT303H,GFXMMU LUT entry 303 high" hexmask.long.tbyte 0x97C 0.--17. 1. "LO,Line offset" line.long 0x980 "GFXMMU_LUT304L,GFXMMU LUT entry 304 low" hexmask.long.byte 0x980 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x980 8.--15. 1. "FVB,First valid block" bitfld.long 0x980 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x984 "GFXMMU_LUT304H,GFXMMU LUT entry 304 high" hexmask.long.tbyte 0x984 0.--17. 1. "LO,Line offset" line.long 0x988 "GFXMMU_LUT305L,GFXMMU LUT entry 305 low" hexmask.long.byte 0x988 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x988 8.--15. 1. "FVB,First valid block" bitfld.long 0x988 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x98C "GFXMMU_LUT305H,GFXMMU LUT entry 305 high" hexmask.long.tbyte 0x98C 0.--17. 1. "LO,Line offset" line.long 0x990 "GFXMMU_LUT306L,GFXMMU LUT entry 306 low" hexmask.long.byte 0x990 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x990 8.--15. 1. "FVB,First valid block" bitfld.long 0x990 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x994 "GFXMMU_LUT306H,GFXMMU LUT entry 306 high" hexmask.long.tbyte 0x994 0.--17. 1. "LO,Line offset" line.long 0x998 "GFXMMU_LUT307L,GFXMMU LUT entry 307 low" hexmask.long.byte 0x998 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x998 8.--15. 1. "FVB,First valid block" bitfld.long 0x998 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x99C "GFXMMU_LUT307H,GFXMMU LUT entry 307 high" hexmask.long.tbyte 0x99C 0.--17. 1. "LO,Line offset" line.long 0x9A0 "GFXMMU_LUT308L,GFXMMU LUT entry 308 low" hexmask.long.byte 0x9A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9A4 "GFXMMU_LUT308H,GFXMMU LUT entry 308 high" hexmask.long.tbyte 0x9A4 0.--17. 1. "LO,Line offset" line.long 0x9A8 "GFXMMU_LUT309L,GFXMMU LUT entry 309 low" hexmask.long.byte 0x9A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9AC "GFXMMU_LUT309H,GFXMMU LUT entry 309 high" hexmask.long.tbyte 0x9AC 0.--17. 1. "LO,Line offset" line.long 0x9B0 "GFXMMU_LUT310L,GFXMMU LUT entry 310 low" hexmask.long.byte 0x9B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9B4 "GFXMMU_LUT310H,GFXMMU LUT entry 310 high" hexmask.long.tbyte 0x9B4 0.--17. 1. "LO,Line offset" line.long 0x9B8 "GFXMMU_LUT311L,GFXMMU LUT entry 311 low" hexmask.long.byte 0x9B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9BC "GFXMMU_LUT311H,GFXMMU LUT entry 311 high" hexmask.long.tbyte 0x9BC 0.--17. 1. "LO,Line offset" line.long 0x9C0 "GFXMMU_LUT312L,GFXMMU LUT entry 312 low" hexmask.long.byte 0x9C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C4 "GFXMMU_LUT312H,GFXMMU LUT entry 312 high" hexmask.long.tbyte 0x9C4 0.--17. 1. "LO,Line offset" line.long 0x9C8 "GFXMMU_LUT313L,GFXMMU LUT entry 313 low" hexmask.long.byte 0x9C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9CC "GFXMMU_LUT313H,GFXMMU LUT entry 313 high" hexmask.long.tbyte 0x9CC 0.--17. 1. "LO,Line offset" line.long 0x9D0 "GFXMMU_LUT314L,GFXMMU LUT entry 314 low" hexmask.long.byte 0x9D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9D4 "GFXMMU_LUT314H,GFXMMU LUT entry 314 high" hexmask.long.tbyte 0x9D4 0.--17. 1. "LO,Line offset" line.long 0x9D8 "GFXMMU_LUT315L,GFXMMU LUT entry 315 low" hexmask.long.byte 0x9D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9DC "GFXMMU_LUT315H,GFXMMU LUT entry 315 high" hexmask.long.tbyte 0x9DC 0.--17. 1. "LO,Line offset" line.long 0x9E0 "GFXMMU_LUT316L,GFXMMU LUT entry 316 low" hexmask.long.byte 0x9E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9E4 "GFXMMU_LUT316H,GFXMMU LUT entry 316 high" hexmask.long.tbyte 0x9E4 0.--17. 1. "LO,Line offset" line.long 0x9E8 "GFXMMU_LUT317L,GFXMMU LUT entry 317 low" hexmask.long.byte 0x9E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9EC "GFXMMU_LUT317H,GFXMMU LUT entry 317 high" hexmask.long.tbyte 0x9EC 0.--17. 1. "LO,Line offset" line.long 0x9F0 "GFXMMU_LUT318L,GFXMMU LUT entry 318 low" hexmask.long.byte 0x9F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9F4 "GFXMMU_LUT318H,GFXMMU LUT entry 318 high" hexmask.long.tbyte 0x9F4 0.--17. 1. "LO,Line offset" line.long 0x9F8 "GFXMMU_LUT319L,GFXMMU LUT entry 319 low" hexmask.long.byte 0x9F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9FC "GFXMMU_LUT319H,GFXMMU LUT entry 319 high" hexmask.long.tbyte 0x9FC 0.--17. 1. "LO,Line offset" line.long 0xA00 "GFXMMU_LUT320L,GFXMMU LUT entry 320 low" hexmask.long.byte 0xA00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA00 8.--15. 1. "FVB,First valid block" bitfld.long 0xA00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA04 "GFXMMU_LUT320H,GFXMMU LUT entry 320 high" hexmask.long.tbyte 0xA04 0.--17. 1. "LO,Line offset" line.long 0xA08 "GFXMMU_LUT321L,GFXMMU LUT entry 321 low" hexmask.long.byte 0xA08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA08 8.--15. 1. "FVB,First valid block" bitfld.long 0xA08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA0C "GFXMMU_LUT321H,GFXMMU LUT entry 321 high" hexmask.long.tbyte 0xA0C 0.--17. 1. "LO,Line offset" line.long 0xA10 "GFXMMU_LUT322L,GFXMMU LUT entry 322 low" hexmask.long.byte 0xA10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA10 8.--15. 1. "FVB,First valid block" bitfld.long 0xA10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA14 "GFXMMU_LUT322H,GFXMMU LUT entry 322 high" hexmask.long.tbyte 0xA14 0.--17. 1. "LO,Line offset" line.long 0xA18 "GFXMMU_LUT323L,GFXMMU LUT entry 323 low" hexmask.long.byte 0xA18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA18 8.--15. 1. "FVB,First valid block" bitfld.long 0xA18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA1C "GFXMMU_LUT323H,GFXMMU LUT entry 323 high" hexmask.long.tbyte 0xA1C 0.--17. 1. "LO,Line offset" line.long 0xA20 "GFXMMU_LUT324L,GFXMMU LUT entry 324 low" hexmask.long.byte 0xA20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA20 8.--15. 1. "FVB,First valid block" bitfld.long 0xA20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA24 "GFXMMU_LUT324H,GFXMMU LUT entry 324 high" hexmask.long.tbyte 0xA24 0.--17. 1. "LO,Line offset" line.long 0xA28 "GFXMMU_LUT325L,GFXMMU LUT entry 325 low" hexmask.long.byte 0xA28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA28 8.--15. 1. "FVB,First valid block" bitfld.long 0xA28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA2C "GFXMMU_LUT325H,GFXMMU LUT entry 325 high" hexmask.long.tbyte 0xA2C 0.--17. 1. "LO,Line offset" line.long 0xA30 "GFXMMU_LUT326L,GFXMMU LUT entry 326 low" hexmask.long.byte 0xA30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA30 8.--15. 1. "FVB,First valid block" bitfld.long 0xA30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA34 "GFXMMU_LUT326H,GFXMMU LUT entry 326 high" hexmask.long.tbyte 0xA34 0.--17. 1. "LO,Line offset" line.long 0xA38 "GFXMMU_LUT327L,GFXMMU LUT entry 327 low" hexmask.long.byte 0xA38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA38 8.--15. 1. "FVB,First valid block" bitfld.long 0xA38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA3C "GFXMMU_LUT327H,GFXMMU LUT entry 327 high" hexmask.long.tbyte 0xA3C 0.--17. 1. "LO,Line offset" line.long 0xA40 "GFXMMU_LUT328L,GFXMMU LUT entry 328 low" hexmask.long.byte 0xA40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA40 8.--15. 1. "FVB,First valid block" bitfld.long 0xA40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA44 "GFXMMU_LUT328H,GFXMMU LUT entry 328 high" hexmask.long.tbyte 0xA44 0.--17. 1. "LO,Line offset" line.long 0xA48 "GFXMMU_LUT329L,GFXMMU LUT entry 329 low" hexmask.long.byte 0xA48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA48 8.--15. 1. "FVB,First valid block" bitfld.long 0xA48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4C "GFXMMU_LUT329H,GFXMMU LUT entry 329 high" hexmask.long.tbyte 0xA4C 0.--17. 1. "LO,Line offset" line.long 0xA50 "GFXMMU_LUT330L,GFXMMU LUT entry 330 low" hexmask.long.byte 0xA50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA50 8.--15. 1. "FVB,First valid block" bitfld.long 0xA50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA54 "GFXMMU_LUT330H,GFXMMU LUT entry 330 high" hexmask.long.tbyte 0xA54 0.--17. 1. "LO,Line offset" line.long 0xA58 "GFXMMU_LUT331L,GFXMMU LUT entry 331 low" hexmask.long.byte 0xA58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA58 8.--15. 1. "FVB,First valid block" bitfld.long 0xA58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA5C "GFXMMU_LUT331H,GFXMMU LUT entry 331 high" hexmask.long.tbyte 0xA5C 0.--17. 1. "LO,Line offset" line.long 0xA60 "GFXMMU_LUT332L,GFXMMU LUT entry 332 low" hexmask.long.byte 0xA60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA60 8.--15. 1. "FVB,First valid block" bitfld.long 0xA60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA64 "GFXMMU_LUT332H,GFXMMU LUT entry 332 high" hexmask.long.tbyte 0xA64 0.--17. 1. "LO,Line offset" line.long 0xA68 "GFXMMU_LUT333L,GFXMMU LUT entry 333 low" hexmask.long.byte 0xA68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA68 8.--15. 1. "FVB,First valid block" bitfld.long 0xA68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA6C "GFXMMU_LUT333H,GFXMMU LUT entry 333 high" hexmask.long.tbyte 0xA6C 0.--17. 1. "LO,Line offset" line.long 0xA70 "GFXMMU_LUT334L,GFXMMU LUT entry 334 low" hexmask.long.byte 0xA70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA70 8.--15. 1. "FVB,First valid block" bitfld.long 0xA70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA74 "GFXMMU_LUT334H,GFXMMU LUT entry 334 high" hexmask.long.tbyte 0xA74 0.--17. 1. "LO,Line offset" line.long 0xA78 "GFXMMU_LUT335L,GFXMMU LUT entry 335 low" hexmask.long.byte 0xA78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA78 8.--15. 1. "FVB,First valid block" bitfld.long 0xA78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA7C "GFXMMU_LUT335H,GFXMMU LUT entry 335 high" hexmask.long.tbyte 0xA7C 0.--17. 1. "LO,Line offset" line.long 0xA80 "GFXMMU_LUT336L,GFXMMU LUT entry 336 low" hexmask.long.byte 0xA80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA80 8.--15. 1. "FVB,First valid block" bitfld.long 0xA80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA84 "GFXMMU_LUT336H,GFXMMU LUT entry 336 high" hexmask.long.tbyte 0xA84 0.--17. 1. "LO,Line offset" line.long 0xA88 "GFXMMU_LUT337L,GFXMMU LUT entry 337 low" hexmask.long.byte 0xA88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA88 8.--15. 1. "FVB,First valid block" bitfld.long 0xA88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA8C "GFXMMU_LUT337H,GFXMMU LUT entry 337 high" hexmask.long.tbyte 0xA8C 0.--17. 1. "LO,Line offset" line.long 0xA90 "GFXMMU_LUT338L,GFXMMU LUT entry 338 low" hexmask.long.byte 0xA90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA90 8.--15. 1. "FVB,First valid block" bitfld.long 0xA90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA94 "GFXMMU_LUT338H,GFXMMU LUT entry 338 high" hexmask.long.tbyte 0xA94 0.--17. 1. "LO,Line offset" line.long 0xA98 "GFXMMU_LUT339L,GFXMMU LUT entry 339 low" hexmask.long.byte 0xA98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA98 8.--15. 1. "FVB,First valid block" bitfld.long 0xA98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA9C "GFXMMU_LUT339H,GFXMMU LUT entry 339 high" hexmask.long.tbyte 0xA9C 0.--17. 1. "LO,Line offset" line.long 0xAA0 "GFXMMU_LUT340L,GFXMMU LUT entry 340 low" hexmask.long.byte 0xAA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAA4 "GFXMMU_LUT340H,GFXMMU LUT entry 340 high" hexmask.long.tbyte 0xAA4 0.--17. 1. "LO,Line offset" line.long 0xAA8 "GFXMMU_LUT341L,GFXMMU LUT entry 341 low" hexmask.long.byte 0xAA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAAC "GFXMMU_LUT341H,GFXMMU LUT entry 341 high" hexmask.long.tbyte 0xAAC 0.--17. 1. "LO,Line offset" line.long 0xAB0 "GFXMMU_LUT342L,GFXMMU LUT entry 342 low" hexmask.long.byte 0xAB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAB4 "GFXMMU_LUT342H,GFXMMU LUT entry 342 high" hexmask.long.tbyte 0xAB4 0.--17. 1. "LO,Line offset" line.long 0xAB8 "GFXMMU_LUT343L,GFXMMU LUT entry 343 low" hexmask.long.byte 0xAB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xABC "GFXMMU_LUT343H,GFXMMU LUT entry 343 high" hexmask.long.tbyte 0xABC 0.--17. 1. "LO,Line offset" line.long 0xAC0 "GFXMMU_LUT344L,GFXMMU LUT entry 344 low" hexmask.long.byte 0xAC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC4 "GFXMMU_LUT344H,GFXMMU LUT entry 344 high" hexmask.long.tbyte 0xAC4 0.--17. 1. "LO,Line offset" line.long 0xAC8 "GFXMMU_LUT345L,GFXMMU LUT entry 345 low" hexmask.long.byte 0xAC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xACC "GFXMMU_LUT345H,GFXMMU LUT entry 345 high" hexmask.long.tbyte 0xACC 0.--17. 1. "LO,Line offset" line.long 0xAD0 "GFXMMU_LUT346L,GFXMMU LUT entry 346 low" hexmask.long.byte 0xAD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAD4 "GFXMMU_LUT346H,GFXMMU LUT entry 346 high" hexmask.long.tbyte 0xAD4 0.--17. 1. "LO,Line offset" line.long 0xAD8 "GFXMMU_LUT347L,GFXMMU LUT entry 347 low" hexmask.long.byte 0xAD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xADC "GFXMMU_LUT347H,GFXMMU LUT entry 347 high" hexmask.long.tbyte 0xADC 0.--17. 1. "LO,Line offset" line.long 0xAE0 "GFXMMU_LUT348L,GFXMMU LUT entry 348 low" hexmask.long.byte 0xAE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAE4 "GFXMMU_LUT348H,GFXMMU LUT entry 348 high" hexmask.long.tbyte 0xAE4 0.--17. 1. "LO,Line offset" line.long 0xAE8 "GFXMMU_LUT349L,GFXMMU LUT entry 349 low" hexmask.long.byte 0xAE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAEC "GFXMMU_LUT349H,GFXMMU LUT entry 349 high" hexmask.long.tbyte 0xAEC 0.--17. 1. "LO,Line offset" line.long 0xAF0 "GFXMMU_LUT350L,GFXMMU LUT entry 350 low" hexmask.long.byte 0xAF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAF4 "GFXMMU_LUT350H,GFXMMU LUT entry 350 high" hexmask.long.tbyte 0xAF4 0.--17. 1. "LO,Line offset" line.long 0xAF8 "GFXMMU_LUT351L,GFXMMU LUT entry 351 low" hexmask.long.byte 0xAF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAFC "GFXMMU_LUT351H,GFXMMU LUT entry 351 high" hexmask.long.tbyte 0xAFC 0.--17. 1. "LO,Line offset" line.long 0xB00 "GFXMMU_LUT352L,GFXMMU LUT entry 352 low" hexmask.long.byte 0xB00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB00 8.--15. 1. "FVB,First valid block" bitfld.long 0xB00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB04 "GFXMMU_LUT352H,GFXMMU LUT entry 352 high" hexmask.long.tbyte 0xB04 0.--17. 1. "LO,Line offset" line.long 0xB08 "GFXMMU_LUT353L,GFXMMU LUT entry 353 low" hexmask.long.byte 0xB08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB08 8.--15. 1. "FVB,First valid block" bitfld.long 0xB08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB0C "GFXMMU_LUT353H,GFXMMU LUT entry 353 high" hexmask.long.tbyte 0xB0C 0.--17. 1. "LO,Line offset" line.long 0xB10 "GFXMMU_LUT354L,GFXMMU LUT entry 354 low" hexmask.long.byte 0xB10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB10 8.--15. 1. "FVB,First valid block" bitfld.long 0xB10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB14 "GFXMMU_LUT354H,GFXMMU LUT entry 354 high" hexmask.long.tbyte 0xB14 0.--17. 1. "LO,Line offset" line.long 0xB18 "GFXMMU_LUT355L,GFXMMU LUT entry 355 low" hexmask.long.byte 0xB18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB18 8.--15. 1. "FVB,First valid block" bitfld.long 0xB18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB1C "GFXMMU_LUT355H,GFXMMU LUT entry 355 high" hexmask.long.tbyte 0xB1C 0.--17. 1. "LO,Line offset" line.long 0xB20 "GFXMMU_LUT356L,GFXMMU LUT entry 356 low" hexmask.long.byte 0xB20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB20 8.--15. 1. "FVB,First valid block" bitfld.long 0xB20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB24 "GFXMMU_LUT356H,GFXMMU LUT entry 356 high" hexmask.long.tbyte 0xB24 0.--17. 1. "LO,Line offset" line.long 0xB28 "GFXMMU_LUT357L,GFXMMU LUT entry 357 low" hexmask.long.byte 0xB28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB28 8.--15. 1. "FVB,First valid block" bitfld.long 0xB28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB2C "GFXMMU_LUT357H,GFXMMU LUT entry 357 high" hexmask.long.tbyte 0xB2C 0.--17. 1. "LO,Line offset" line.long 0xB30 "GFXMMU_LUT358L,GFXMMU LUT entry 358 low" hexmask.long.byte 0xB30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB30 8.--15. 1. "FVB,First valid block" bitfld.long 0xB30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB34 "GFXMMU_LUT358H,GFXMMU LUT entry 358 high" hexmask.long.tbyte 0xB34 0.--17. 1. "LO,Line offset" line.long 0xB38 "GFXMMU_LUT359L,GFXMMU LUT entry 359 low" hexmask.long.byte 0xB38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB38 8.--15. 1. "FVB,First valid block" bitfld.long 0xB38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB3C "GFXMMU_LUT359H,GFXMMU LUT entry 359 high" hexmask.long.tbyte 0xB3C 0.--17. 1. "LO,Line offset" line.long 0xB40 "GFXMMU_LUT360L,GFXMMU LUT entry 360 low" hexmask.long.byte 0xB40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB40 8.--15. 1. "FVB,First valid block" bitfld.long 0xB40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB44 "GFXMMU_LUT360H,GFXMMU LUT entry 360 high" hexmask.long.tbyte 0xB44 0.--17. 1. "LO,Line offset" line.long 0xB48 "GFXMMU_LUT361L,GFXMMU LUT entry 361 low" hexmask.long.byte 0xB48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB48 8.--15. 1. "FVB,First valid block" bitfld.long 0xB48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4C "GFXMMU_LUT361H,GFXMMU LUT entry 361 high" hexmask.long.tbyte 0xB4C 0.--17. 1. "LO,Line offset" line.long 0xB50 "GFXMMU_LUT362L,GFXMMU LUT entry 362 low" hexmask.long.byte 0xB50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB50 8.--15. 1. "FVB,First valid block" bitfld.long 0xB50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB54 "GFXMMU_LUT362H,GFXMMU LUT entry 362 high" hexmask.long.tbyte 0xB54 0.--17. 1. "LO,Line offset" line.long 0xB58 "GFXMMU_LUT363L,GFXMMU LUT entry 363 low" hexmask.long.byte 0xB58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB58 8.--15. 1. "FVB,First valid block" bitfld.long 0xB58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB5C "GFXMMU_LUT363H,GFXMMU LUT entry 363 high" hexmask.long.tbyte 0xB5C 0.--17. 1. "LO,Line offset" line.long 0xB60 "GFXMMU_LUT364L,GFXMMU LUT entry 364 low" hexmask.long.byte 0xB60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB60 8.--15. 1. "FVB,First valid block" bitfld.long 0xB60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB64 "GFXMMU_LUT364H,GFXMMU LUT entry 364 high" hexmask.long.tbyte 0xB64 0.--17. 1. "LO,Line offset" line.long 0xB68 "GFXMMU_LUT365L,GFXMMU LUT entry 365 low" hexmask.long.byte 0xB68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB68 8.--15. 1. "FVB,First valid block" bitfld.long 0xB68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB6C "GFXMMU_LUT365H,GFXMMU LUT entry 365 high" hexmask.long.tbyte 0xB6C 0.--17. 1. "LO,Line offset" line.long 0xB70 "GFXMMU_LUT366L,GFXMMU LUT entry 366 low" hexmask.long.byte 0xB70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB70 8.--15. 1. "FVB,First valid block" bitfld.long 0xB70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB74 "GFXMMU_LUT366H,GFXMMU LUT entry 366 high" hexmask.long.tbyte 0xB74 0.--17. 1. "LO,Line offset" line.long 0xB78 "GFXMMU_LUT367L,GFXMMU LUT entry 367 low" hexmask.long.byte 0xB78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB78 8.--15. 1. "FVB,First valid block" bitfld.long 0xB78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB7C "GFXMMU_LUT367H,GFXMMU LUT entry 367 high" hexmask.long.tbyte 0xB7C 0.--17. 1. "LO,Line offset" line.long 0xB80 "GFXMMU_LUT368L,GFXMMU LUT entry 368 low" hexmask.long.byte 0xB80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB80 8.--15. 1. "FVB,First valid block" bitfld.long 0xB80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB84 "GFXMMU_LUT368H,GFXMMU LUT entry 368 high" hexmask.long.tbyte 0xB84 0.--17. 1. "LO,Line offset" line.long 0xB88 "GFXMMU_LUT369L,GFXMMU LUT entry 369 low" hexmask.long.byte 0xB88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB88 8.--15. 1. "FVB,First valid block" bitfld.long 0xB88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB8C "GFXMMU_LUT369H,GFXMMU LUT entry 369 high" hexmask.long.tbyte 0xB8C 0.--17. 1. "LO,Line offset" line.long 0xB90 "GFXMMU_LUT370L,GFXMMU LUT entry 370 low" hexmask.long.byte 0xB90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB90 8.--15. 1. "FVB,First valid block" bitfld.long 0xB90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB94 "GFXMMU_LUT370H,GFXMMU LUT entry 370 high" hexmask.long.tbyte 0xB94 0.--17. 1. "LO,Line offset" line.long 0xB98 "GFXMMU_LUT371L,GFXMMU LUT entry 371 low" hexmask.long.byte 0xB98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB98 8.--15. 1. "FVB,First valid block" bitfld.long 0xB98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB9C "GFXMMU_LUT371H,GFXMMU LUT entry 371 high" hexmask.long.tbyte 0xB9C 0.--17. 1. "LO,Line offset" line.long 0xBA0 "GFXMMU_LUT372L,GFXMMU LUT entry 372 low" hexmask.long.byte 0xBA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBA4 "GFXMMU_LUT372H,GFXMMU LUT entry 372 high" hexmask.long.tbyte 0xBA4 0.--17. 1. "LO,Line offset" line.long 0xBA8 "GFXMMU_LUT373L,GFXMMU LUT entry 373 low" hexmask.long.byte 0xBA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBAC "GFXMMU_LUT373H,GFXMMU LUT entry 373 high" hexmask.long.tbyte 0xBAC 0.--17. 1. "LO,Line offset" line.long 0xBB0 "GFXMMU_LUT374L,GFXMMU LUT entry 374 low" hexmask.long.byte 0xBB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBB4 "GFXMMU_LUT374H,GFXMMU LUT entry 374 high" hexmask.long.tbyte 0xBB4 0.--17. 1. "LO,Line offset" line.long 0xBB8 "GFXMMU_LUT375L,GFXMMU LUT entry 375 low" hexmask.long.byte 0xBB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBBC "GFXMMU_LUT375H,GFXMMU LUT entry 375 high" hexmask.long.tbyte 0xBBC 0.--17. 1. "LO,Line offset" line.long 0xBC0 "GFXMMU_LUT376L,GFXMMU LUT entry 376 low" hexmask.long.byte 0xBC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC4 "GFXMMU_LUT376H,GFXMMU LUT entry 376 high" hexmask.long.tbyte 0xBC4 0.--17. 1. "LO,Line offset" line.long 0xBC8 "GFXMMU_LUT377L,GFXMMU LUT entry 377 low" hexmask.long.byte 0xBC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBCC "GFXMMU_LUT377H,GFXMMU LUT entry 377 high" hexmask.long.tbyte 0xBCC 0.--17. 1. "LO,Line offset" line.long 0xBD0 "GFXMMU_LUT378L,GFXMMU LUT entry 378 low" hexmask.long.byte 0xBD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBD4 "GFXMMU_LUT378H,GFXMMU LUT entry 378 high" hexmask.long.tbyte 0xBD4 0.--17. 1. "LO,Line offset" line.long 0xBD8 "GFXMMU_LUT379L,GFXMMU LUT entry 379 low" hexmask.long.byte 0xBD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBDC "GFXMMU_LUT379H,GFXMMU LUT entry 379 high" hexmask.long.tbyte 0xBDC 0.--17. 1. "LO,Line offset" line.long 0xBE0 "GFXMMU_LUT380L,GFXMMU LUT entry 380 low" hexmask.long.byte 0xBE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBE4 "GFXMMU_LUT380H,GFXMMU LUT entry 380 high" hexmask.long.tbyte 0xBE4 0.--17. 1. "LO,Line offset" line.long 0xBE8 "GFXMMU_LUT381L,GFXMMU LUT entry 381 low" hexmask.long.byte 0xBE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBEC "GFXMMU_LUT381H,GFXMMU LUT entry 381 high" hexmask.long.tbyte 0xBEC 0.--17. 1. "LO,Line offset" line.long 0xBF0 "GFXMMU_LUT382L,GFXMMU LUT entry 382 low" hexmask.long.byte 0xBF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBF4 "GFXMMU_LUT382H,GFXMMU LUT entry 382 high" hexmask.long.tbyte 0xBF4 0.--17. 1. "LO,Line offset" line.long 0xBF8 "GFXMMU_LUT383L,GFXMMU LUT entry 383 low" hexmask.long.byte 0xBF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBFC "GFXMMU_LUT383H,GFXMMU LUT entry 383 high" hexmask.long.tbyte 0xBFC 0.--17. 1. "LO,Line offset" line.long 0xC00 "GFXMMU_LUT384L,GFXMMU LUT entry 384 low" hexmask.long.byte 0xC00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC00 8.--15. 1. "FVB,First valid block" bitfld.long 0xC00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC04 "GFXMMU_LUT384H,GFXMMU LUT entry 384 high" hexmask.long.tbyte 0xC04 0.--17. 1. "LO,Line offset" line.long 0xC08 "GFXMMU_LUT385L,GFXMMU LUT entry 385 low" hexmask.long.byte 0xC08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC08 8.--15. 1. "FVB,First valid block" bitfld.long 0xC08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC0C "GFXMMU_LUT385H,GFXMMU LUT entry 385 high" hexmask.long.tbyte 0xC0C 0.--17. 1. "LO,Line offset" line.long 0xC10 "GFXMMU_LUT386L,GFXMMU LUT entry 386 low" hexmask.long.byte 0xC10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC10 8.--15. 1. "FVB,First valid block" bitfld.long 0xC10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC14 "GFXMMU_LUT386H,GFXMMU LUT entry 386 high" hexmask.long.tbyte 0xC14 0.--17. 1. "LO,Line offset" line.long 0xC18 "GFXMMU_LUT387L,GFXMMU LUT entry 387 low" hexmask.long.byte 0xC18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC18 8.--15. 1. "FVB,First valid block" bitfld.long 0xC18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC1C "GFXMMU_LUT387H,GFXMMU LUT entry 387 high" hexmask.long.tbyte 0xC1C 0.--17. 1. "LO,Line offset" line.long 0xC20 "GFXMMU_LUT388L,GFXMMU LUT entry 388 low" hexmask.long.byte 0xC20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC20 8.--15. 1. "FVB,First valid block" bitfld.long 0xC20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC24 "GFXMMU_LUT388H,GFXMMU LUT entry 388 high" hexmask.long.tbyte 0xC24 0.--17. 1. "LO,Line offset" line.long 0xC28 "GFXMMU_LUT389L,GFXMMU LUT entry 389 low" hexmask.long.byte 0xC28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC28 8.--15. 1. "FVB,First valid block" bitfld.long 0xC28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC2C "GFXMMU_LUT389H,GFXMMU LUT entry 389 high" hexmask.long.tbyte 0xC2C 0.--17. 1. "LO,Line offset" line.long 0xC30 "GFXMMU_LUT390L,GFXMMU LUT entry 390 low" hexmask.long.byte 0xC30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC30 8.--15. 1. "FVB,First valid block" bitfld.long 0xC30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC34 "GFXMMU_LUT390H,GFXMMU LUT entry 390 high" hexmask.long.tbyte 0xC34 0.--17. 1. "LO,Line offset" line.long 0xC38 "GFXMMU_LUT391L,GFXMMU LUT entry 391 low" hexmask.long.byte 0xC38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC38 8.--15. 1. "FVB,First valid block" bitfld.long 0xC38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC3C "GFXMMU_LUT391H,GFXMMU LUT entry 391 high" hexmask.long.tbyte 0xC3C 0.--17. 1. "LO,Line offset" line.long 0xC40 "GFXMMU_LUT392L,GFXMMU LUT entry 392 low" hexmask.long.byte 0xC40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC40 8.--15. 1. "FVB,First valid block" bitfld.long 0xC40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC44 "GFXMMU_LUT392H,GFXMMU LUT entry 392 high" hexmask.long.tbyte 0xC44 0.--17. 1. "LO,Line offset" line.long 0xC48 "GFXMMU_LUT393L,GFXMMU LUT entry 393 low" hexmask.long.byte 0xC48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC48 8.--15. 1. "FVB,First valid block" bitfld.long 0xC48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4C "GFXMMU_LUT393H,GFXMMU LUT entry 393 high" hexmask.long.tbyte 0xC4C 0.--17. 1. "LO,Line offset" line.long 0xC50 "GFXMMU_LUT394L,GFXMMU LUT entry 394 low" hexmask.long.byte 0xC50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC50 8.--15. 1. "FVB,First valid block" bitfld.long 0xC50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC54 "GFXMMU_LUT394H,GFXMMU LUT entry 394 high" hexmask.long.tbyte 0xC54 0.--17. 1. "LO,Line offset" line.long 0xC58 "GFXMMU_LUT395L,GFXMMU LUT entry 395 low" hexmask.long.byte 0xC58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC58 8.--15. 1. "FVB,First valid block" bitfld.long 0xC58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC5C "GFXMMU_LUT395H,GFXMMU LUT entry 395 high" hexmask.long.tbyte 0xC5C 0.--17. 1. "LO,Line offset" line.long 0xC60 "GFXMMU_LUT396L,GFXMMU LUT entry 396 low" hexmask.long.byte 0xC60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC60 8.--15. 1. "FVB,First valid block" bitfld.long 0xC60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC64 "GFXMMU_LUT396H,GFXMMU LUT entry 396 high" hexmask.long.tbyte 0xC64 0.--17. 1. "LO,Line offset" line.long 0xC68 "GFXMMU_LUT397L,GFXMMU LUT entry 397 low" hexmask.long.byte 0xC68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC68 8.--15. 1. "FVB,First valid block" bitfld.long 0xC68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC6C "GFXMMU_LUT397H,GFXMMU LUT entry 397 high" hexmask.long.tbyte 0xC6C 0.--17. 1. "LO,Line offset" line.long 0xC70 "GFXMMU_LUT398L,GFXMMU LUT entry 398 low" hexmask.long.byte 0xC70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC70 8.--15. 1. "FVB,First valid block" bitfld.long 0xC70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC74 "GFXMMU_LUT398H,GFXMMU LUT entry 398 high" hexmask.long.tbyte 0xC74 0.--17. 1. "LO,Line offset" line.long 0xC78 "GFXMMU_LUT399L,GFXMMU LUT entry 399 low" hexmask.long.byte 0xC78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC78 8.--15. 1. "FVB,First valid block" bitfld.long 0xC78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC7C "GFXMMU_LUT399H,GFXMMU LUT entry 399 high" hexmask.long.tbyte 0xC7C 0.--17. 1. "LO,Line offset" line.long 0xC80 "GFXMMU_LUT400L,GFXMMU LUT entry 400 low" hexmask.long.byte 0xC80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC80 8.--15. 1. "FVB,First valid block" bitfld.long 0xC80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC84 "GFXMMU_LUT400H,GFXMMU LUT entry 400 high" hexmask.long.tbyte 0xC84 0.--17. 1. "LO,Line offset" line.long 0xC88 "GFXMMU_LUT401L,GFXMMU LUT entry 401 low" hexmask.long.byte 0xC88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC88 8.--15. 1. "FVB,First valid block" bitfld.long 0xC88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC8C "GFXMMU_LUT401H,GFXMMU LUT entry 401 high" hexmask.long.tbyte 0xC8C 0.--17. 1. "LO,Line offset" line.long 0xC90 "GFXMMU_LUT402L,GFXMMU LUT entry 402 low" hexmask.long.byte 0xC90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC90 8.--15. 1. "FVB,First valid block" bitfld.long 0xC90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC94 "GFXMMU_LUT402H,GFXMMU LUT entry 402 high" hexmask.long.tbyte 0xC94 0.--17. 1. "LO,Line offset" line.long 0xC98 "GFXMMU_LUT403L,GFXMMU LUT entry 403 low" hexmask.long.byte 0xC98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC98 8.--15. 1. "FVB,First valid block" bitfld.long 0xC98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC9C "GFXMMU_LUT403H,GFXMMU LUT entry 403 high" hexmask.long.tbyte 0xC9C 0.--17. 1. "LO,Line offset" line.long 0xCA0 "GFXMMU_LUT404L,GFXMMU LUT entry 404 low" hexmask.long.byte 0xCA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCA4 "GFXMMU_LUT404H,GFXMMU LUT entry 404 high" hexmask.long.tbyte 0xCA4 0.--17. 1. "LO,Line offset" line.long 0xCA8 "GFXMMU_LUT405L,GFXMMU LUT entry 405 low" hexmask.long.byte 0xCA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCAC "GFXMMU_LUT405H,GFXMMU LUT entry 405 high" hexmask.long.tbyte 0xCAC 0.--17. 1. "LO,Line offset" line.long 0xCB0 "GFXMMU_LUT406L,GFXMMU LUT entry 406 low" hexmask.long.byte 0xCB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCB4 "GFXMMU_LUT406H,GFXMMU LUT entry 406 high" hexmask.long.tbyte 0xCB4 0.--17. 1. "LO,Line offset" line.long 0xCB8 "GFXMMU_LUT407L,GFXMMU LUT entry 407 low" hexmask.long.byte 0xCB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCBC "GFXMMU_LUT407H,GFXMMU LUT entry 407 high" hexmask.long.tbyte 0xCBC 0.--17. 1. "LO,Line offset" line.long 0xCC0 "GFXMMU_LUT408L,GFXMMU LUT entry 408 low" hexmask.long.byte 0xCC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC4 "GFXMMU_LUT408H,GFXMMU LUT entry 408 high" hexmask.long.tbyte 0xCC4 0.--17. 1. "LO,Line offset" line.long 0xCC8 "GFXMMU_LUT409L,GFXMMU LUT entry 409 low" hexmask.long.byte 0xCC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCCC "GFXMMU_LUT409H,GFXMMU LUT entry 409 high" hexmask.long.tbyte 0xCCC 0.--17. 1. "LO,Line offset" line.long 0xCD0 "GFXMMU_LUT410L,GFXMMU LUT entry 410 low" hexmask.long.byte 0xCD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCD4 "GFXMMU_LUT410H,GFXMMU LUT entry 410 high" hexmask.long.tbyte 0xCD4 0.--17. 1. "LO,Line offset" line.long 0xCD8 "GFXMMU_LUT411L,GFXMMU LUT entry 411 low" hexmask.long.byte 0xCD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCDC "GFXMMU_LUT411H,GFXMMU LUT entry 411 high" hexmask.long.tbyte 0xCDC 0.--17. 1. "LO,Line offset" line.long 0xCE0 "GFXMMU_LUT412L,GFXMMU LUT entry 412 low" hexmask.long.byte 0xCE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCE4 "GFXMMU_LUT412H,GFXMMU LUT entry 412 high" hexmask.long.tbyte 0xCE4 0.--17. 1. "LO,Line offset" line.long 0xCE8 "GFXMMU_LUT413L,GFXMMU LUT entry 413 low" hexmask.long.byte 0xCE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCEC "GFXMMU_LUT413H,GFXMMU LUT entry 413 high" hexmask.long.tbyte 0xCEC 0.--17. 1. "LO,Line offset" line.long 0xCF0 "GFXMMU_LUT414L,GFXMMU LUT entry 414 low" hexmask.long.byte 0xCF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCF4 "GFXMMU_LUT414H,GFXMMU LUT entry 414 high" hexmask.long.tbyte 0xCF4 0.--17. 1. "LO,Line offset" line.long 0xCF8 "GFXMMU_LUT415L,GFXMMU LUT entry 415 low" hexmask.long.byte 0xCF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCFC "GFXMMU_LUT415H,GFXMMU LUT entry 415 high" hexmask.long.tbyte 0xCFC 0.--17. 1. "LO,Line offset" line.long 0xD00 "GFXMMU_LUT416L,GFXMMU LUT entry 416 low" hexmask.long.byte 0xD00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD00 8.--15. 1. "FVB,First valid block" bitfld.long 0xD00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD04 "GFXMMU_LUT416H,GFXMMU LUT entry 416 high" hexmask.long.tbyte 0xD04 0.--17. 1. "LO,Line offset" line.long 0xD08 "GFXMMU_LUT417L,GFXMMU LUT entry 417 low" hexmask.long.byte 0xD08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD08 8.--15. 1. "FVB,First valid block" bitfld.long 0xD08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD0C "GFXMMU_LUT417H,GFXMMU LUT entry 417 high" hexmask.long.tbyte 0xD0C 0.--17. 1. "LO,Line offset" line.long 0xD10 "GFXMMU_LUT418L,GFXMMU LUT entry 418 low" hexmask.long.byte 0xD10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD10 8.--15. 1. "FVB,First valid block" bitfld.long 0xD10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD14 "GFXMMU_LUT418H,GFXMMU LUT entry 418 high" hexmask.long.tbyte 0xD14 0.--17. 1. "LO,Line offset" line.long 0xD18 "GFXMMU_LUT419L,GFXMMU LUT entry 419 low" hexmask.long.byte 0xD18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD18 8.--15. 1. "FVB,First valid block" bitfld.long 0xD18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD1C "GFXMMU_LUT419H,GFXMMU LUT entry 419 high" hexmask.long.tbyte 0xD1C 0.--17. 1. "LO,Line offset" line.long 0xD20 "GFXMMU_LUT420L,GFXMMU LUT entry 420 low" hexmask.long.byte 0xD20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD20 8.--15. 1. "FVB,First valid block" bitfld.long 0xD20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD24 "GFXMMU_LUT420H,GFXMMU LUT entry 420 high" hexmask.long.tbyte 0xD24 0.--17. 1. "LO,Line offset" line.long 0xD28 "GFXMMU_LUT421L,GFXMMU LUT entry 421 low" hexmask.long.byte 0xD28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD28 8.--15. 1. "FVB,First valid block" bitfld.long 0xD28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD2C "GFXMMU_LUT421H,GFXMMU LUT entry 421 high" hexmask.long.tbyte 0xD2C 0.--17. 1. "LO,Line offset" line.long 0xD30 "GFXMMU_LUT422L,GFXMMU LUT entry 422 low" hexmask.long.byte 0xD30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD30 8.--15. 1. "FVB,First valid block" bitfld.long 0xD30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD34 "GFXMMU_LUT422H,GFXMMU LUT entry 422 high" hexmask.long.tbyte 0xD34 0.--17. 1. "LO,Line offset" line.long 0xD38 "GFXMMU_LUT423L,GFXMMU LUT entry 423 low" hexmask.long.byte 0xD38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD38 8.--15. 1. "FVB,First valid block" bitfld.long 0xD38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD3C "GFXMMU_LUT423H,GFXMMU LUT entry 423 high" hexmask.long.tbyte 0xD3C 0.--17. 1. "LO,Line offset" line.long 0xD40 "GFXMMU_LUT424L,GFXMMU LUT entry 424 low" hexmask.long.byte 0xD40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD40 8.--15. 1. "FVB,First valid block" bitfld.long 0xD40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD44 "GFXMMU_LUT424H,GFXMMU LUT entry 424 high" hexmask.long.tbyte 0xD44 0.--17. 1. "LO,Line offset" line.long 0xD48 "GFXMMU_LUT425L,GFXMMU LUT entry 425 low" hexmask.long.byte 0xD48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD48 8.--15. 1. "FVB,First valid block" bitfld.long 0xD48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4C "GFXMMU_LUT425H,GFXMMU LUT entry 425 high" hexmask.long.tbyte 0xD4C 0.--17. 1. "LO,Line offset" line.long 0xD50 "GFXMMU_LUT426L,GFXMMU LUT entry 426 low" hexmask.long.byte 0xD50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD50 8.--15. 1. "FVB,First valid block" bitfld.long 0xD50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD54 "GFXMMU_LUT426H,GFXMMU LUT entry 426 high" hexmask.long.tbyte 0xD54 0.--17. 1. "LO,Line offset" line.long 0xD58 "GFXMMU_LUT427L,GFXMMU LUT entry 427 low" hexmask.long.byte 0xD58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD58 8.--15. 1. "FVB,First valid block" bitfld.long 0xD58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD5C "GFXMMU_LUT427H,GFXMMU LUT entry 427 high" hexmask.long.tbyte 0xD5C 0.--17. 1. "LO,Line offset" line.long 0xD60 "GFXMMU_LUT428L,GFXMMU LUT entry 428 low" hexmask.long.byte 0xD60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD60 8.--15. 1. "FVB,First valid block" bitfld.long 0xD60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD64 "GFXMMU_LUT428H,GFXMMU LUT entry 428 high" hexmask.long.tbyte 0xD64 0.--17. 1. "LO,Line offset" line.long 0xD68 "GFXMMU_LUT429L,GFXMMU LUT entry 429 low" hexmask.long.byte 0xD68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD68 8.--15. 1. "FVB,First valid block" bitfld.long 0xD68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD6C "GFXMMU_LUT429H,GFXMMU LUT entry 429 high" hexmask.long.tbyte 0xD6C 0.--17. 1. "LO,Line offset" line.long 0xD70 "GFXMMU_LUT430L,GFXMMU LUT entry 430 low" hexmask.long.byte 0xD70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD70 8.--15. 1. "FVB,First valid block" bitfld.long 0xD70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD74 "GFXMMU_LUT430H,GFXMMU LUT entry 430 high" hexmask.long.tbyte 0xD74 0.--17. 1. "LO,Line offset" line.long 0xD78 "GFXMMU_LUT431L,GFXMMU LUT entry 431 low" hexmask.long.byte 0xD78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD78 8.--15. 1. "FVB,First valid block" bitfld.long 0xD78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD7C "GFXMMU_LUT431H,GFXMMU LUT entry 431 high" hexmask.long.tbyte 0xD7C 0.--17. 1. "LO,Line offset" line.long 0xD80 "GFXMMU_LUT432L,GFXMMU LUT entry 432 low" hexmask.long.byte 0xD80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD80 8.--15. 1. "FVB,First valid block" bitfld.long 0xD80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD84 "GFXMMU_LUT432H,GFXMMU LUT entry 432 high" hexmask.long.tbyte 0xD84 0.--17. 1. "LO,Line offset" line.long 0xD88 "GFXMMU_LUT433L,GFXMMU LUT entry 433 low" hexmask.long.byte 0xD88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD88 8.--15. 1. "FVB,First valid block" bitfld.long 0xD88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD8C "GFXMMU_LUT433H,GFXMMU LUT entry 433 high" hexmask.long.tbyte 0xD8C 0.--17. 1. "LO,Line offset" line.long 0xD90 "GFXMMU_LUT434L,GFXMMU LUT entry 434 low" hexmask.long.byte 0xD90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD90 8.--15. 1. "FVB,First valid block" bitfld.long 0xD90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD94 "GFXMMU_LUT434H,GFXMMU LUT entry 434 high" hexmask.long.tbyte 0xD94 0.--17. 1. "LO,Line offset" line.long 0xD98 "GFXMMU_LUT435L,GFXMMU LUT entry 435 low" hexmask.long.byte 0xD98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD98 8.--15. 1. "FVB,First valid block" bitfld.long 0xD98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD9C "GFXMMU_LUT435H,GFXMMU LUT entry 435 high" hexmask.long.tbyte 0xD9C 0.--17. 1. "LO,Line offset" line.long 0xDA0 "GFXMMU_LUT436L,GFXMMU LUT entry 436 low" hexmask.long.byte 0xDA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDA4 "GFXMMU_LUT436H,GFXMMU LUT entry 436 high" hexmask.long.tbyte 0xDA4 0.--17. 1. "LO,Line offset" line.long 0xDA8 "GFXMMU_LUT437L,GFXMMU LUT entry 437 low" hexmask.long.byte 0xDA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDAC "GFXMMU_LUT437H,GFXMMU LUT entry 437 high" hexmask.long.tbyte 0xDAC 0.--17. 1. "LO,Line offset" line.long 0xDB0 "GFXMMU_LUT438L,GFXMMU LUT entry 438 low" hexmask.long.byte 0xDB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDB4 "GFXMMU_LUT438H,GFXMMU LUT entry 438 high" hexmask.long.tbyte 0xDB4 0.--17. 1. "LO,Line offset" line.long 0xDB8 "GFXMMU_LUT439L,GFXMMU LUT entry 439 low" hexmask.long.byte 0xDB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDBC "GFXMMU_LUT439H,GFXMMU LUT entry 439 high" hexmask.long.tbyte 0xDBC 0.--17. 1. "LO,Line offset" line.long 0xDC0 "GFXMMU_LUT440L,GFXMMU LUT entry 440 low" hexmask.long.byte 0xDC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC4 "GFXMMU_LUT440H,GFXMMU LUT entry 440 high" hexmask.long.tbyte 0xDC4 0.--17. 1. "LO,Line offset" line.long 0xDC8 "GFXMMU_LUT441L,GFXMMU LUT entry 441 low" hexmask.long.byte 0xDC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDCC "GFXMMU_LUT441H,GFXMMU LUT entry 441 high" hexmask.long.tbyte 0xDCC 0.--17. 1. "LO,Line offset" line.long 0xDD0 "GFXMMU_LUT442L,GFXMMU LUT entry 442 low" hexmask.long.byte 0xDD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDD4 "GFXMMU_LUT442H,GFXMMU LUT entry 442 high" hexmask.long.tbyte 0xDD4 0.--17. 1. "LO,Line offset" line.long 0xDD8 "GFXMMU_LUT443L,GFXMMU LUT entry 443 low" hexmask.long.byte 0xDD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDDC "GFXMMU_LUT443H,GFXMMU LUT entry 443 high" hexmask.long.tbyte 0xDDC 0.--17. 1. "LO,Line offset" line.long 0xDE0 "GFXMMU_LUT444L,GFXMMU LUT entry 444 low" hexmask.long.byte 0xDE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDE4 "GFXMMU_LUT444H,GFXMMU LUT entry 444 high" hexmask.long.tbyte 0xDE4 0.--17. 1. "LO,Line offset" line.long 0xDE8 "GFXMMU_LUT445L,GFXMMU LUT entry 445 low" hexmask.long.byte 0xDE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDEC "GFXMMU_LUT445H,GFXMMU LUT entry 445 high" hexmask.long.tbyte 0xDEC 0.--17. 1. "LO,Line offset" line.long 0xDF0 "GFXMMU_LUT446L,GFXMMU LUT entry 446 low" hexmask.long.byte 0xDF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDF4 "GFXMMU_LUT446H,GFXMMU LUT entry 446 high" hexmask.long.tbyte 0xDF4 0.--17. 1. "LO,Line offset" line.long 0xDF8 "GFXMMU_LUT447L,GFXMMU LUT entry 447 low" hexmask.long.byte 0xDF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDFC "GFXMMU_LUT447H,GFXMMU LUT entry 447 high" hexmask.long.tbyte 0xDFC 0.--17. 1. "LO,Line offset" line.long 0xE00 "GFXMMU_LUT448L,GFXMMU LUT entry 448 low" hexmask.long.byte 0xE00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE00 8.--15. 1. "FVB,First valid block" bitfld.long 0xE00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE04 "GFXMMU_LUT448H,GFXMMU LUT entry 448 high" hexmask.long.tbyte 0xE04 0.--17. 1. "LO,Line offset" line.long 0xE08 "GFXMMU_LUT449L,GFXMMU LUT entry 449 low" hexmask.long.byte 0xE08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE08 8.--15. 1. "FVB,First valid block" bitfld.long 0xE08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE0C "GFXMMU_LUT449H,GFXMMU LUT entry 449 high" hexmask.long.tbyte 0xE0C 0.--17. 1. "LO,Line offset" line.long 0xE10 "GFXMMU_LUT450L,GFXMMU LUT entry 450 low" hexmask.long.byte 0xE10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE10 8.--15. 1. "FVB,First valid block" bitfld.long 0xE10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE14 "GFXMMU_LUT450H,GFXMMU LUT entry 450 high" hexmask.long.tbyte 0xE14 0.--17. 1. "LO,Line offset" line.long 0xE18 "GFXMMU_LUT451L,GFXMMU LUT entry 451 low" hexmask.long.byte 0xE18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE18 8.--15. 1. "FVB,First valid block" bitfld.long 0xE18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE1C "GFXMMU_LUT451H,GFXMMU LUT entry 451 high" hexmask.long.tbyte 0xE1C 0.--17. 1. "LO,Line offset" line.long 0xE20 "GFXMMU_LUT452L,GFXMMU LUT entry 452 low" hexmask.long.byte 0xE20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE20 8.--15. 1. "FVB,First valid block" bitfld.long 0xE20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE24 "GFXMMU_LUT452H,GFXMMU LUT entry 452 high" hexmask.long.tbyte 0xE24 0.--17. 1. "LO,Line offset" line.long 0xE28 "GFXMMU_LUT453L,GFXMMU LUT entry 453 low" hexmask.long.byte 0xE28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE28 8.--15. 1. "FVB,First valid block" bitfld.long 0xE28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE2C "GFXMMU_LUT453H,GFXMMU LUT entry 453 high" hexmask.long.tbyte 0xE2C 0.--17. 1. "LO,Line offset" line.long 0xE30 "GFXMMU_LUT454L,GFXMMU LUT entry 454 low" hexmask.long.byte 0xE30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE30 8.--15. 1. "FVB,First valid block" bitfld.long 0xE30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE34 "GFXMMU_LUT454H,GFXMMU LUT entry 454 high" hexmask.long.tbyte 0xE34 0.--17. 1. "LO,Line offset" line.long 0xE38 "GFXMMU_LUT455L,GFXMMU LUT entry 455 low" hexmask.long.byte 0xE38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE38 8.--15. 1. "FVB,First valid block" bitfld.long 0xE38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE3C "GFXMMU_LUT455H,GFXMMU LUT entry 455 high" hexmask.long.tbyte 0xE3C 0.--17. 1. "LO,Line offset" line.long 0xE40 "GFXMMU_LUT456L,GFXMMU LUT entry 456 low" hexmask.long.byte 0xE40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE40 8.--15. 1. "FVB,First valid block" bitfld.long 0xE40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE44 "GFXMMU_LUT456H,GFXMMU LUT entry 456 high" hexmask.long.tbyte 0xE44 0.--17. 1. "LO,Line offset" line.long 0xE48 "GFXMMU_LUT457L,GFXMMU LUT entry 457 low" hexmask.long.byte 0xE48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE48 8.--15. 1. "FVB,First valid block" bitfld.long 0xE48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4C "GFXMMU_LUT457H,GFXMMU LUT entry 457 high" hexmask.long.tbyte 0xE4C 0.--17. 1. "LO,Line offset" line.long 0xE50 "GFXMMU_LUT458L,GFXMMU LUT entry 458 low" hexmask.long.byte 0xE50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE50 8.--15. 1. "FVB,First valid block" bitfld.long 0xE50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE54 "GFXMMU_LUT458H,GFXMMU LUT entry 458 high" hexmask.long.tbyte 0xE54 0.--17. 1. "LO,Line offset" line.long 0xE58 "GFXMMU_LUT459L,GFXMMU LUT entry 459 low" hexmask.long.byte 0xE58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE58 8.--15. 1. "FVB,First valid block" bitfld.long 0xE58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE5C "GFXMMU_LUT459H,GFXMMU LUT entry 459 high" hexmask.long.tbyte 0xE5C 0.--17. 1. "LO,Line offset" line.long 0xE60 "GFXMMU_LUT460L,GFXMMU LUT entry 460 low" hexmask.long.byte 0xE60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE60 8.--15. 1. "FVB,First valid block" bitfld.long 0xE60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE64 "GFXMMU_LUT460H,GFXMMU LUT entry 460 high" hexmask.long.tbyte 0xE64 0.--17. 1. "LO,Line offset" line.long 0xE68 "GFXMMU_LUT461L,GFXMMU LUT entry 461 low" hexmask.long.byte 0xE68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE68 8.--15. 1. "FVB,First valid block" bitfld.long 0xE68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE6C "GFXMMU_LUT461H,GFXMMU LUT entry 461 high" hexmask.long.tbyte 0xE6C 0.--17. 1. "LO,Line offset" line.long 0xE70 "GFXMMU_LUT462L,GFXMMU LUT entry 462 low" hexmask.long.byte 0xE70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE70 8.--15. 1. "FVB,First valid block" bitfld.long 0xE70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE74 "GFXMMU_LUT462H,GFXMMU LUT entry 462 high" hexmask.long.tbyte 0xE74 0.--17. 1. "LO,Line offset" line.long 0xE78 "GFXMMU_LUT463L,GFXMMU LUT entry 463 low" hexmask.long.byte 0xE78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE78 8.--15. 1. "FVB,First valid block" bitfld.long 0xE78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE7C "GFXMMU_LUT463H,GFXMMU LUT entry 463 high" hexmask.long.tbyte 0xE7C 0.--17. 1. "LO,Line offset" line.long 0xE80 "GFXMMU_LUT464L,GFXMMU LUT entry 464 low" hexmask.long.byte 0xE80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE80 8.--15. 1. "FVB,First valid block" bitfld.long 0xE80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE84 "GFXMMU_LUT464H,GFXMMU LUT entry 464 high" hexmask.long.tbyte 0xE84 0.--17. 1. "LO,Line offset" line.long 0xE88 "GFXMMU_LUT465L,GFXMMU LUT entry 465 low" hexmask.long.byte 0xE88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE88 8.--15. 1. "FVB,First valid block" bitfld.long 0xE88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE8C "GFXMMU_LUT465H,GFXMMU LUT entry 465 high" hexmask.long.tbyte 0xE8C 0.--17. 1. "LO,Line offset" line.long 0xE90 "GFXMMU_LUT466L,GFXMMU LUT entry 466 low" hexmask.long.byte 0xE90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE90 8.--15. 1. "FVB,First valid block" bitfld.long 0xE90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE94 "GFXMMU_LUT466H,GFXMMU LUT entry 466 high" hexmask.long.tbyte 0xE94 0.--17. 1. "LO,Line offset" line.long 0xE98 "GFXMMU_LUT467L,GFXMMU LUT entry 467 low" hexmask.long.byte 0xE98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE98 8.--15. 1. "FVB,First valid block" bitfld.long 0xE98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE9C "GFXMMU_LUT467H,GFXMMU LUT entry 467 high" hexmask.long.tbyte 0xE9C 0.--17. 1. "LO,Line offset" line.long 0xEA0 "GFXMMU_LUT468L,GFXMMU LUT entry 468 low" hexmask.long.byte 0xEA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEA4 "GFXMMU_LUT468H,GFXMMU LUT entry 468 high" hexmask.long.tbyte 0xEA4 0.--17. 1. "LO,Line offset" line.long 0xEA8 "GFXMMU_LUT469L,GFXMMU LUT entry 469 low" hexmask.long.byte 0xEA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEAC "GFXMMU_LUT469H,GFXMMU LUT entry 469 high" hexmask.long.tbyte 0xEAC 0.--17. 1. "LO,Line offset" line.long 0xEB0 "GFXMMU_LUT470L,GFXMMU LUT entry 470 low" hexmask.long.byte 0xEB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEB4 "GFXMMU_LUT470H,GFXMMU LUT entry 470 high" hexmask.long.tbyte 0xEB4 0.--17. 1. "LO,Line offset" line.long 0xEB8 "GFXMMU_LUT471L,GFXMMU LUT entry 471 low" hexmask.long.byte 0xEB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEBC "GFXMMU_LUT471H,GFXMMU LUT entry 471 high" hexmask.long.tbyte 0xEBC 0.--17. 1. "LO,Line offset" line.long 0xEC0 "GFXMMU_LUT472L,GFXMMU LUT entry 472 low" hexmask.long.byte 0xEC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC4 "GFXMMU_LUT472H,GFXMMU LUT entry 472 high" hexmask.long.tbyte 0xEC4 0.--17. 1. "LO,Line offset" line.long 0xEC8 "GFXMMU_LUT473L,GFXMMU LUT entry 473 low" hexmask.long.byte 0xEC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xECC "GFXMMU_LUT473H,GFXMMU LUT entry 473 high" hexmask.long.tbyte 0xECC 0.--17. 1. "LO,Line offset" line.long 0xED0 "GFXMMU_LUT474L,GFXMMU LUT entry 474 low" hexmask.long.byte 0xED0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xED0 8.--15. 1. "FVB,First valid block" bitfld.long 0xED0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xED4 "GFXMMU_LUT474H,GFXMMU LUT entry 474 high" hexmask.long.tbyte 0xED4 0.--17. 1. "LO,Line offset" line.long 0xED8 "GFXMMU_LUT475L,GFXMMU LUT entry 475 low" hexmask.long.byte 0xED8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xED8 8.--15. 1. "FVB,First valid block" bitfld.long 0xED8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEDC "GFXMMU_LUT475H,GFXMMU LUT entry 475 high" hexmask.long.tbyte 0xEDC 0.--17. 1. "LO,Line offset" line.long 0xEE0 "GFXMMU_LUT476L,GFXMMU LUT entry 476 low" hexmask.long.byte 0xEE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEE4 "GFXMMU_LUT476H,GFXMMU LUT entry 476 high" hexmask.long.tbyte 0xEE4 0.--17. 1. "LO,Line offset" line.long 0xEE8 "GFXMMU_LUT477L,GFXMMU LUT entry 477 low" hexmask.long.byte 0xEE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEEC "GFXMMU_LUT477H,GFXMMU LUT entry 477 high" hexmask.long.tbyte 0xEEC 0.--17. 1. "LO,Line offset" line.long 0xEF0 "GFXMMU_LUT478L,GFXMMU LUT entry 478 low" hexmask.long.byte 0xEF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEF4 "GFXMMU_LUT478H,GFXMMU LUT entry 478 high" hexmask.long.tbyte 0xEF4 0.--17. 1. "LO,Line offset" line.long 0xEF8 "GFXMMU_LUT479L,GFXMMU LUT entry 479 low" hexmask.long.byte 0xEF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEFC "GFXMMU_LUT479H,GFXMMU LUT entry 479 high" hexmask.long.tbyte 0xEFC 0.--17. 1. "LO,Line offset" line.long 0xF00 "GFXMMU_LUT480L,GFXMMU LUT entry 480 low" hexmask.long.byte 0xF00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF00 8.--15. 1. "FVB,First valid block" bitfld.long 0xF00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF04 "GFXMMU_LUT480H,GFXMMU LUT entry 480 high" hexmask.long.tbyte 0xF04 0.--17. 1. "LO,Line offset" line.long 0xF08 "GFXMMU_LUT481L,GFXMMU LUT entry 481 low" hexmask.long.byte 0xF08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF08 8.--15. 1. "FVB,First valid block" bitfld.long 0xF08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF0C "GFXMMU_LUT481H,GFXMMU LUT entry 481 high" hexmask.long.tbyte 0xF0C 0.--17. 1. "LO,Line offset" line.long 0xF10 "GFXMMU_LUT482L,GFXMMU LUT entry 482 low" hexmask.long.byte 0xF10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF10 8.--15. 1. "FVB,First valid block" bitfld.long 0xF10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF14 "GFXMMU_LUT482H,GFXMMU LUT entry 482 high" hexmask.long.tbyte 0xF14 0.--17. 1. "LO,Line offset" line.long 0xF18 "GFXMMU_LUT483L,GFXMMU LUT entry 483 low" hexmask.long.byte 0xF18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF18 8.--15. 1. "FVB,First valid block" bitfld.long 0xF18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF1C "GFXMMU_LUT483H,GFXMMU LUT entry 483 high" hexmask.long.tbyte 0xF1C 0.--17. 1. "LO,Line offset" line.long 0xF20 "GFXMMU_LUT484L,GFXMMU LUT entry 484 low" hexmask.long.byte 0xF20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF20 8.--15. 1. "FVB,First valid block" bitfld.long 0xF20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF24 "GFXMMU_LUT484H,GFXMMU LUT entry 484 high" hexmask.long.tbyte 0xF24 0.--17. 1. "LO,Line offset" line.long 0xF28 "GFXMMU_LUT485L,GFXMMU LUT entry 485 low" hexmask.long.byte 0xF28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF28 8.--15. 1. "FVB,First valid block" bitfld.long 0xF28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF2C "GFXMMU_LUT485H,GFXMMU LUT entry 485 high" hexmask.long.tbyte 0xF2C 0.--17. 1. "LO,Line offset" line.long 0xF30 "GFXMMU_LUT486L,GFXMMU LUT entry 486 low" hexmask.long.byte 0xF30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF30 8.--15. 1. "FVB,First valid block" bitfld.long 0xF30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF34 "GFXMMU_LUT486H,GFXMMU LUT entry 486 high" hexmask.long.tbyte 0xF34 0.--17. 1. "LO,Line offset" line.long 0xF38 "GFXMMU_LUT487L,GFXMMU LUT entry 487 low" hexmask.long.byte 0xF38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF38 8.--15. 1. "FVB,First valid block" bitfld.long 0xF38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF3C "GFXMMU_LUT487H,GFXMMU LUT entry 487 high" hexmask.long.tbyte 0xF3C 0.--17. 1. "LO,Line offset" line.long 0xF40 "GFXMMU_LUT488L,GFXMMU LUT entry 488 low" hexmask.long.byte 0xF40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF40 8.--15. 1. "FVB,First valid block" bitfld.long 0xF40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF44 "GFXMMU_LUT488H,GFXMMU LUT entry 488 high" hexmask.long.tbyte 0xF44 0.--17. 1. "LO,Line offset" line.long 0xF48 "GFXMMU_LUT489L,GFXMMU LUT entry 489 low" hexmask.long.byte 0xF48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF48 8.--15. 1. "FVB,First valid block" bitfld.long 0xF48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4C "GFXMMU_LUT489H,GFXMMU LUT entry 489 high" hexmask.long.tbyte 0xF4C 0.--17. 1. "LO,Line offset" line.long 0xF50 "GFXMMU_LUT490L,GFXMMU LUT entry 490 low" hexmask.long.byte 0xF50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF50 8.--15. 1. "FVB,First valid block" bitfld.long 0xF50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF54 "GFXMMU_LUT490H,GFXMMU LUT entry 490 high" hexmask.long.tbyte 0xF54 0.--17. 1. "LO,Line offset" line.long 0xF58 "GFXMMU_LUT491L,GFXMMU LUT entry 491 low" hexmask.long.byte 0xF58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF58 8.--15. 1. "FVB,First valid block" bitfld.long 0xF58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF5C "GFXMMU_LUT491H,GFXMMU LUT entry 491 high" hexmask.long.tbyte 0xF5C 0.--17. 1. "LO,Line offset" line.long 0xF60 "GFXMMU_LUT492L,GFXMMU LUT entry 492 low" hexmask.long.byte 0xF60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF60 8.--15. 1. "FVB,First valid block" bitfld.long 0xF60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF64 "GFXMMU_LUT492H,GFXMMU LUT entry 492 high" hexmask.long.tbyte 0xF64 0.--17. 1. "LO,Line offset" line.long 0xF68 "GFXMMU_LUT493L,GFXMMU LUT entry 493 low" hexmask.long.byte 0xF68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF68 8.--15. 1. "FVB,First valid block" bitfld.long 0xF68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF6C "GFXMMU_LUT493H,GFXMMU LUT entry 493 high" hexmask.long.tbyte 0xF6C 0.--17. 1. "LO,Line offset" line.long 0xF70 "GFXMMU_LUT494L,GFXMMU LUT entry 494 low" hexmask.long.byte 0xF70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF70 8.--15. 1. "FVB,First valid block" bitfld.long 0xF70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF74 "GFXMMU_LUT494H,GFXMMU LUT entry 494 high" hexmask.long.tbyte 0xF74 0.--17. 1. "LO,Line offset" line.long 0xF78 "GFXMMU_LUT495L,GFXMMU LUT entry 495 low" hexmask.long.byte 0xF78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF78 8.--15. 1. "FVB,First valid block" bitfld.long 0xF78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF7C "GFXMMU_LUT495H,GFXMMU LUT entry 495 high" hexmask.long.tbyte 0xF7C 0.--17. 1. "LO,Line offset" line.long 0xF80 "GFXMMU_LUT496L,GFXMMU LUT entry 496 low" hexmask.long.byte 0xF80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF80 8.--15. 1. "FVB,First valid block" bitfld.long 0xF80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF84 "GFXMMU_LUT496H,GFXMMU LUT entry 496 high" hexmask.long.tbyte 0xF84 0.--17. 1. "LO,Line offset" line.long 0xF88 "GFXMMU_LUT497L,GFXMMU LUT entry 497 low" hexmask.long.byte 0xF88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF88 8.--15. 1. "FVB,First valid block" bitfld.long 0xF88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF8C "GFXMMU_LUT497H,GFXMMU LUT entry 497 high" hexmask.long.tbyte 0xF8C 0.--17. 1. "LO,Line offset" line.long 0xF90 "GFXMMU_LUT498L,GFXMMU LUT entry 498 low" hexmask.long.byte 0xF90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF90 8.--15. 1. "FVB,First valid block" bitfld.long 0xF90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF94 "GFXMMU_LUT498H,GFXMMU LUT entry 498 high" hexmask.long.tbyte 0xF94 0.--17. 1. "LO,Line offset" line.long 0xF98 "GFXMMU_LUT499L,GFXMMU LUT entry 499 low" hexmask.long.byte 0xF98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF98 8.--15. 1. "FVB,First valid block" bitfld.long 0xF98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF9C "GFXMMU_LUT499H,GFXMMU LUT entry 499 high" hexmask.long.tbyte 0xF9C 0.--17. 1. "LO,Line offset" line.long 0xFA0 "GFXMMU_LUT500L,GFXMMU LUT entry 500 low" hexmask.long.byte 0xFA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFA4 "GFXMMU_LUT500H,GFXMMU LUT entry 500 high" hexmask.long.tbyte 0xFA4 0.--17. 1. "LO,Line offset" line.long 0xFA8 "GFXMMU_LUT501L,GFXMMU LUT entry 501 low" hexmask.long.byte 0xFA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFAC "GFXMMU_LUT501H,GFXMMU LUT entry 501 high" hexmask.long.tbyte 0xFAC 0.--17. 1. "LO,Line offset" line.long 0xFB0 "GFXMMU_LUT502L,GFXMMU LUT entry 502 low" hexmask.long.byte 0xFB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFB4 "GFXMMU_LUT502H,GFXMMU LUT entry 502 high" hexmask.long.tbyte 0xFB4 0.--17. 1. "LO,Line offset" line.long 0xFB8 "GFXMMU_LUT503L,GFXMMU LUT entry 503 low" hexmask.long.byte 0xFB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFBC "GFXMMU_LUT503H,GFXMMU LUT entry 503 high" hexmask.long.tbyte 0xFBC 0.--17. 1. "LO,Line offset" line.long 0xFC0 "GFXMMU_LUT504L,GFXMMU LUT entry 504 low" hexmask.long.byte 0xFC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC4 "GFXMMU_LUT504H,GFXMMU LUT entry 504 high" hexmask.long.tbyte 0xFC4 0.--17. 1. "LO,Line offset" line.long 0xFC8 "GFXMMU_LUT505L,GFXMMU LUT entry 505 low" hexmask.long.byte 0xFC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFCC "GFXMMU_LUT505H,GFXMMU LUT entry 505 high" hexmask.long.tbyte 0xFCC 0.--17. 1. "LO,Line offset" line.long 0xFD0 "GFXMMU_LUT506L,GFXMMU LUT entry 506 low" hexmask.long.byte 0xFD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFD4 "GFXMMU_LUT506H,GFXMMU LUT entry 506 high" hexmask.long.tbyte 0xFD4 0.--17. 1. "LO,Line offset" line.long 0xFD8 "GFXMMU_LUT507L,GFXMMU LUT entry 507 low" hexmask.long.byte 0xFD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFDC "GFXMMU_LUT507H,GFXMMU LUT entry 507 high" hexmask.long.tbyte 0xFDC 0.--17. 1. "LO,Line offset" line.long 0xFE0 "GFXMMU_LUT508L,GFXMMU LUT entry 508 low" hexmask.long.byte 0xFE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFE4 "GFXMMU_LUT508H,GFXMMU LUT entry 508 high" hexmask.long.tbyte 0xFE4 0.--17. 1. "LO,Line offset" line.long 0xFE8 "GFXMMU_LUT509L,GFXMMU LUT entry 509 low" hexmask.long.byte 0xFE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFEC "GFXMMU_LUT509H,GFXMMU LUT entry 509 high" hexmask.long.tbyte 0xFEC 0.--17. 1. "LO,Line offset" line.long 0xFF0 "GFXMMU_LUT510L,GFXMMU LUT entry 510 low" hexmask.long.byte 0xFF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFF4 "GFXMMU_LUT510H,GFXMMU LUT entry 510 high" hexmask.long.tbyte 0xFF4 0.--17. 1. "LO,Line offset" line.long 0xFF8 "GFXMMU_LUT511L,GFXMMU LUT entry 511 low" hexmask.long.byte 0xFF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFFC "GFXMMU_LUT511H,GFXMMU LUT entry 511 high" hexmask.long.tbyte 0xFFC 0.--17. 1. "LO,Line offset" group.long 0x2000++0xFFF line.long 0x0 "GFXMMU_LUT512L,GFXMMU LUT entry 512 low" hexmask.long.byte 0x0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x0 8.--15. 1. "FVB,First valid block" bitfld.long 0x0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4 "GFXMMU_LUT512H,GFXMMU LUT entry 512 high" hexmask.long.tbyte 0x4 0.--17. 1. "LO,Line offset" line.long 0x8 "GFXMMU_LUT513L,GFXMMU LUT entry 513 low" hexmask.long.byte 0x8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC "GFXMMU_LUT513H,GFXMMU LUT entry 513 high" hexmask.long.tbyte 0xC 0.--17. 1. "LO,Line offset" line.long 0x10 "GFXMMU_LUT514L,GFXMMU LUT entry 514 low" hexmask.long.byte 0x10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x10 8.--15. 1. "FVB,First valid block" bitfld.long 0x10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14 "GFXMMU_LUT514H,GFXMMU LUT entry 514 high" hexmask.long.tbyte 0x14 0.--17. 1. "LO,Line offset" line.long 0x18 "GFXMMU_LUT515L,GFXMMU LUT entry 515 low" hexmask.long.byte 0x18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x18 8.--15. 1. "FVB,First valid block" bitfld.long 0x18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C "GFXMMU_LUT515H,GFXMMU LUT entry 515 high" hexmask.long.tbyte 0x1C 0.--17. 1. "LO,Line offset" line.long 0x20 "GFXMMU_LUT516L,GFXMMU LUT entry 516 low" hexmask.long.byte 0x20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x20 8.--15. 1. "FVB,First valid block" bitfld.long 0x20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24 "GFXMMU_LUT516H,GFXMMU LUT entry 516 high" hexmask.long.tbyte 0x24 0.--17. 1. "LO,Line offset" line.long 0x28 "GFXMMU_LUT517L,GFXMMU LUT entry 517 low" hexmask.long.byte 0x28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x28 8.--15. 1. "FVB,First valid block" bitfld.long 0x28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C "GFXMMU_LUT517H,GFXMMU LUT entry 517 high" hexmask.long.tbyte 0x2C 0.--17. 1. "LO,Line offset" line.long 0x30 "GFXMMU_LUT518L,GFXMMU LUT entry 518 low" hexmask.long.byte 0x30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x30 8.--15. 1. "FVB,First valid block" bitfld.long 0x30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34 "GFXMMU_LUT518H,GFXMMU LUT entry 518 high" hexmask.long.tbyte 0x34 0.--17. 1. "LO,Line offset" line.long 0x38 "GFXMMU_LUT519L,GFXMMU LUT entry 519 low" hexmask.long.byte 0x38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x38 8.--15. 1. "FVB,First valid block" bitfld.long 0x38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C "GFXMMU_LUT519H,GFXMMU LUT entry 519 high" hexmask.long.tbyte 0x3C 0.--17. 1. "LO,Line offset" line.long 0x40 "GFXMMU_LUT520L,GFXMMU LUT entry 520 low" hexmask.long.byte 0x40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x40 8.--15. 1. "FVB,First valid block" bitfld.long 0x40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44 "GFXMMU_LUT520H,GFXMMU LUT entry 520 high" hexmask.long.tbyte 0x44 0.--17. 1. "LO,Line offset" line.long 0x48 "GFXMMU_LUT521L,GFXMMU LUT entry 521 low" hexmask.long.byte 0x48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x48 8.--15. 1. "FVB,First valid block" bitfld.long 0x48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C "GFXMMU_LUT521H,GFXMMU LUT entry 521 high" hexmask.long.tbyte 0x4C 0.--17. 1. "LO,Line offset" line.long 0x50 "GFXMMU_LUT522L,GFXMMU LUT entry 522 low" hexmask.long.byte 0x50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x50 8.--15. 1. "FVB,First valid block" bitfld.long 0x50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54 "GFXMMU_LUT522H,GFXMMU LUT entry 522 high" hexmask.long.tbyte 0x54 0.--17. 1. "LO,Line offset" line.long 0x58 "GFXMMU_LUT523L,GFXMMU LUT entry 523 low" hexmask.long.byte 0x58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x58 8.--15. 1. "FVB,First valid block" bitfld.long 0x58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C "GFXMMU_LUT523H,GFXMMU LUT entry 523 high" hexmask.long.tbyte 0x5C 0.--17. 1. "LO,Line offset" line.long 0x60 "GFXMMU_LUT524L,GFXMMU LUT entry 524 low" hexmask.long.byte 0x60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x60 8.--15. 1. "FVB,First valid block" bitfld.long 0x60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64 "GFXMMU_LUT524H,GFXMMU LUT entry 524 high" hexmask.long.tbyte 0x64 0.--17. 1. "LO,Line offset" line.long 0x68 "GFXMMU_LUT525L,GFXMMU LUT entry 525 low" hexmask.long.byte 0x68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x68 8.--15. 1. "FVB,First valid block" bitfld.long 0x68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C "GFXMMU_LUT525H,GFXMMU LUT entry 525 high" hexmask.long.tbyte 0x6C 0.--17. 1. "LO,Line offset" line.long 0x70 "GFXMMU_LUT526L,GFXMMU LUT entry 526 low" hexmask.long.byte 0x70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x70 8.--15. 1. "FVB,First valid block" bitfld.long 0x70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74 "GFXMMU_LUT526H,GFXMMU LUT entry 526 high" hexmask.long.tbyte 0x74 0.--17. 1. "LO,Line offset" line.long 0x78 "GFXMMU_LUT527L,GFXMMU LUT entry 527 low" hexmask.long.byte 0x78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x78 8.--15. 1. "FVB,First valid block" bitfld.long 0x78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C "GFXMMU_LUT527H,GFXMMU LUT entry 527 high" hexmask.long.tbyte 0x7C 0.--17. 1. "LO,Line offset" line.long 0x80 "GFXMMU_LUT528L,GFXMMU LUT entry 528 low" hexmask.long.byte 0x80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x80 8.--15. 1. "FVB,First valid block" bitfld.long 0x80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84 "GFXMMU_LUT528H,GFXMMU LUT entry 528 high" hexmask.long.tbyte 0x84 0.--17. 1. "LO,Line offset" line.long 0x88 "GFXMMU_LUT529L,GFXMMU LUT entry 529 low" hexmask.long.byte 0x88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x88 8.--15. 1. "FVB,First valid block" bitfld.long 0x88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C "GFXMMU_LUT529H,GFXMMU LUT entry 529 high" hexmask.long.tbyte 0x8C 0.--17. 1. "LO,Line offset" line.long 0x90 "GFXMMU_LUT530L,GFXMMU LUT entry 530 low" hexmask.long.byte 0x90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x90 8.--15. 1. "FVB,First valid block" bitfld.long 0x90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94 "GFXMMU_LUT530H,GFXMMU LUT entry 530 high" hexmask.long.tbyte 0x94 0.--17. 1. "LO,Line offset" line.long 0x98 "GFXMMU_LUT531L,GFXMMU LUT entry 531 low" hexmask.long.byte 0x98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x98 8.--15. 1. "FVB,First valid block" bitfld.long 0x98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C "GFXMMU_LUT531H,GFXMMU LUT entry 531 high" hexmask.long.tbyte 0x9C 0.--17. 1. "LO,Line offset" line.long 0xA0 "GFXMMU_LUT532L,GFXMMU LUT entry 532 low" hexmask.long.byte 0xA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4 "GFXMMU_LUT532H,GFXMMU LUT entry 532 high" hexmask.long.tbyte 0xA4 0.--17. 1. "LO,Line offset" line.long 0xA8 "GFXMMU_LUT533L,GFXMMU LUT entry 533 low" hexmask.long.byte 0xA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC "GFXMMU_LUT533H,GFXMMU LUT entry 533 high" hexmask.long.tbyte 0xAC 0.--17. 1. "LO,Line offset" line.long 0xB0 "GFXMMU_LUT534L,GFXMMU LUT entry 534 low" hexmask.long.byte 0xB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4 "GFXMMU_LUT534H,GFXMMU LUT entry 534 high" hexmask.long.tbyte 0xB4 0.--17. 1. "LO,Line offset" line.long 0xB8 "GFXMMU_LUT535L,GFXMMU LUT entry 535 low" hexmask.long.byte 0xB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC "GFXMMU_LUT535H,GFXMMU LUT entry 535 high" hexmask.long.tbyte 0xBC 0.--17. 1. "LO,Line offset" line.long 0xC0 "GFXMMU_LUT536L,GFXMMU LUT entry 536 low" hexmask.long.byte 0xC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4 "GFXMMU_LUT536H,GFXMMU LUT entry 536 high" hexmask.long.tbyte 0xC4 0.--17. 1. "LO,Line offset" line.long 0xC8 "GFXMMU_LUT537L,GFXMMU LUT entry 537 low" hexmask.long.byte 0xC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC "GFXMMU_LUT537H,GFXMMU LUT entry 537 high" hexmask.long.tbyte 0xCC 0.--17. 1. "LO,Line offset" line.long 0xD0 "GFXMMU_LUT538L,GFXMMU LUT entry 538 low" hexmask.long.byte 0xD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4 "GFXMMU_LUT538H,GFXMMU LUT entry 538 high" hexmask.long.tbyte 0xD4 0.--17. 1. "LO,Line offset" line.long 0xD8 "GFXMMU_LUT539L,GFXMMU LUT entry 539 low" hexmask.long.byte 0xD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC "GFXMMU_LUT539H,GFXMMU LUT entry 539 high" hexmask.long.tbyte 0xDC 0.--17. 1. "LO,Line offset" line.long 0xE0 "GFXMMU_LUT540L,GFXMMU LUT entry 540 low" hexmask.long.byte 0xE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4 "GFXMMU_LUT540H,GFXMMU LUT entry 540 high" hexmask.long.tbyte 0xE4 0.--17. 1. "LO,Line offset" line.long 0xE8 "GFXMMU_LUT541L,GFXMMU LUT entry 541 low" hexmask.long.byte 0xE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC "GFXMMU_LUT541H,GFXMMU LUT entry 541 high" hexmask.long.tbyte 0xEC 0.--17. 1. "LO,Line offset" line.long 0xF0 "GFXMMU_LUT542L,GFXMMU LUT entry 542 low" hexmask.long.byte 0xF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4 "GFXMMU_LUT542H,GFXMMU LUT entry 542 high" hexmask.long.tbyte 0xF4 0.--17. 1. "LO,Line offset" line.long 0xF8 "GFXMMU_LUT543L,GFXMMU LUT entry 543 low" hexmask.long.byte 0xF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC "GFXMMU_LUT543H,GFXMMU LUT entry 543 high" hexmask.long.tbyte 0xFC 0.--17. 1. "LO,Line offset" line.long 0x100 "GFXMMU_LUT544L,GFXMMU LUT entry 544 low" hexmask.long.byte 0x100 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x100 8.--15. 1. "FVB,First valid block" bitfld.long 0x100 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x104 "GFXMMU_LUT544H,GFXMMU LUT entry 544 high" hexmask.long.tbyte 0x104 0.--17. 1. "LO,Line offset" line.long 0x108 "GFXMMU_LUT545L,GFXMMU LUT entry 545 low" hexmask.long.byte 0x108 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x108 8.--15. 1. "FVB,First valid block" bitfld.long 0x108 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x10C "GFXMMU_LUT545H,GFXMMU LUT entry 545 high" hexmask.long.tbyte 0x10C 0.--17. 1. "LO,Line offset" line.long 0x110 "GFXMMU_LUT546L,GFXMMU LUT entry 546 low" hexmask.long.byte 0x110 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x110 8.--15. 1. "FVB,First valid block" bitfld.long 0x110 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x114 "GFXMMU_LUT546H,GFXMMU LUT entry 546 high" hexmask.long.tbyte 0x114 0.--17. 1. "LO,Line offset" line.long 0x118 "GFXMMU_LUT547L,GFXMMU LUT entry 547 low" hexmask.long.byte 0x118 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x118 8.--15. 1. "FVB,First valid block" bitfld.long 0x118 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x11C "GFXMMU_LUT547H,GFXMMU LUT entry 547 high" hexmask.long.tbyte 0x11C 0.--17. 1. "LO,Line offset" line.long 0x120 "GFXMMU_LUT548L,GFXMMU LUT entry 548 low" hexmask.long.byte 0x120 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x120 8.--15. 1. "FVB,First valid block" bitfld.long 0x120 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x124 "GFXMMU_LUT548H,GFXMMU LUT entry 548 high" hexmask.long.tbyte 0x124 0.--17. 1. "LO,Line offset" line.long 0x128 "GFXMMU_LUT549L,GFXMMU LUT entry 549 low" hexmask.long.byte 0x128 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x128 8.--15. 1. "FVB,First valid block" bitfld.long 0x128 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x12C "GFXMMU_LUT549H,GFXMMU LUT entry 549 high" hexmask.long.tbyte 0x12C 0.--17. 1. "LO,Line offset" line.long 0x130 "GFXMMU_LUT550L,GFXMMU LUT entry 550 low" hexmask.long.byte 0x130 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x130 8.--15. 1. "FVB,First valid block" bitfld.long 0x130 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x134 "GFXMMU_LUT550H,GFXMMU LUT entry 550 high" hexmask.long.tbyte 0x134 0.--17. 1. "LO,Line offset" line.long 0x138 "GFXMMU_LUT551L,GFXMMU LUT entry 551 low" hexmask.long.byte 0x138 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x138 8.--15. 1. "FVB,First valid block" bitfld.long 0x138 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x13C "GFXMMU_LUT551H,GFXMMU LUT entry 551 high" hexmask.long.tbyte 0x13C 0.--17. 1. "LO,Line offset" line.long 0x140 "GFXMMU_LUT552L,GFXMMU LUT entry 552 low" hexmask.long.byte 0x140 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x140 8.--15. 1. "FVB,First valid block" bitfld.long 0x140 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x144 "GFXMMU_LUT552H,GFXMMU LUT entry 552 high" hexmask.long.tbyte 0x144 0.--17. 1. "LO,Line offset" line.long 0x148 "GFXMMU_LUT553L,GFXMMU LUT entry 553 low" hexmask.long.byte 0x148 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x148 8.--15. 1. "FVB,First valid block" bitfld.long 0x148 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x14C "GFXMMU_LUT553H,GFXMMU LUT entry 553 high" hexmask.long.tbyte 0x14C 0.--17. 1. "LO,Line offset" line.long 0x150 "GFXMMU_LUT554L,GFXMMU LUT entry 554 low" hexmask.long.byte 0x150 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x150 8.--15. 1. "FVB,First valid block" bitfld.long 0x150 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x154 "GFXMMU_LUT554H,GFXMMU LUT entry 554 high" hexmask.long.tbyte 0x154 0.--17. 1. "LO,Line offset" line.long 0x158 "GFXMMU_LUT555L,GFXMMU LUT entry 555 low" hexmask.long.byte 0x158 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x158 8.--15. 1. "FVB,First valid block" bitfld.long 0x158 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x15C "GFXMMU_LUT555H,GFXMMU LUT entry 555 high" hexmask.long.tbyte 0x15C 0.--17. 1. "LO,Line offset" line.long 0x160 "GFXMMU_LUT556L,GFXMMU LUT entry 556 low" hexmask.long.byte 0x160 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x160 8.--15. 1. "FVB,First valid block" bitfld.long 0x160 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x164 "GFXMMU_LUT556H,GFXMMU LUT entry 556 high" hexmask.long.tbyte 0x164 0.--17. 1. "LO,Line offset" line.long 0x168 "GFXMMU_LUT557L,GFXMMU LUT entry 557 low" hexmask.long.byte 0x168 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x168 8.--15. 1. "FVB,First valid block" bitfld.long 0x168 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x16C "GFXMMU_LUT557H,GFXMMU LUT entry 557 high" hexmask.long.tbyte 0x16C 0.--17. 1. "LO,Line offset" line.long 0x170 "GFXMMU_LUT558L,GFXMMU LUT entry 558 low" hexmask.long.byte 0x170 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x170 8.--15. 1. "FVB,First valid block" bitfld.long 0x170 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x174 "GFXMMU_LUT558H,GFXMMU LUT entry 558 high" hexmask.long.tbyte 0x174 0.--17. 1. "LO,Line offset" line.long 0x178 "GFXMMU_LUT559L,GFXMMU LUT entry 559 low" hexmask.long.byte 0x178 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x178 8.--15. 1. "FVB,First valid block" bitfld.long 0x178 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x17C "GFXMMU_LUT559H,GFXMMU LUT entry 559 high" hexmask.long.tbyte 0x17C 0.--17. 1. "LO,Line offset" line.long 0x180 "GFXMMU_LUT560L,GFXMMU LUT entry 560 low" hexmask.long.byte 0x180 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x180 8.--15. 1. "FVB,First valid block" bitfld.long 0x180 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x184 "GFXMMU_LUT560H,GFXMMU LUT entry 560 high" hexmask.long.tbyte 0x184 0.--17. 1. "LO,Line offset" line.long 0x188 "GFXMMU_LUT561L,GFXMMU LUT entry 561 low" hexmask.long.byte 0x188 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x188 8.--15. 1. "FVB,First valid block" bitfld.long 0x188 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x18C "GFXMMU_LUT561H,GFXMMU LUT entry 561 high" hexmask.long.tbyte 0x18C 0.--17. 1. "LO,Line offset" line.long 0x190 "GFXMMU_LUT562L,GFXMMU LUT entry 562 low" hexmask.long.byte 0x190 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x190 8.--15. 1. "FVB,First valid block" bitfld.long 0x190 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x194 "GFXMMU_LUT562H,GFXMMU LUT entry 562 high" hexmask.long.tbyte 0x194 0.--17. 1. "LO,Line offset" line.long 0x198 "GFXMMU_LUT563L,GFXMMU LUT entry 563 low" hexmask.long.byte 0x198 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x198 8.--15. 1. "FVB,First valid block" bitfld.long 0x198 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x19C "GFXMMU_LUT563H,GFXMMU LUT entry 563 high" hexmask.long.tbyte 0x19C 0.--17. 1. "LO,Line offset" line.long 0x1A0 "GFXMMU_LUT564L,GFXMMU LUT entry 564 low" hexmask.long.byte 0x1A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1A4 "GFXMMU_LUT564H,GFXMMU LUT entry 564 high" hexmask.long.tbyte 0x1A4 0.--17. 1. "LO,Line offset" line.long 0x1A8 "GFXMMU_LUT565L,GFXMMU LUT entry 565 low" hexmask.long.byte 0x1A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1AC "GFXMMU_LUT565H,GFXMMU LUT entry 565 high" hexmask.long.tbyte 0x1AC 0.--17. 1. "LO,Line offset" line.long 0x1B0 "GFXMMU_LUT566L,GFXMMU LUT entry 566 low" hexmask.long.byte 0x1B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1B4 "GFXMMU_LUT566H,GFXMMU LUT entry 566 high" hexmask.long.tbyte 0x1B4 0.--17. 1. "LO,Line offset" line.long 0x1B8 "GFXMMU_LUT567L,GFXMMU LUT entry 567 low" hexmask.long.byte 0x1B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1BC "GFXMMU_LUT567H,GFXMMU LUT entry 567 high" hexmask.long.tbyte 0x1BC 0.--17. 1. "LO,Line offset" line.long 0x1C0 "GFXMMU_LUT568L,GFXMMU LUT entry 568 low" hexmask.long.byte 0x1C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1C4 "GFXMMU_LUT568H,GFXMMU LUT entry 568 high" hexmask.long.tbyte 0x1C4 0.--17. 1. "LO,Line offset" line.long 0x1C8 "GFXMMU_LUT569L,GFXMMU LUT entry 569 low" hexmask.long.byte 0x1C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1CC "GFXMMU_LUT569H,GFXMMU LUT entry 569 high" hexmask.long.tbyte 0x1CC 0.--17. 1. "LO,Line offset" line.long 0x1D0 "GFXMMU_LUT570L,GFXMMU LUT entry 570 low" hexmask.long.byte 0x1D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1D4 "GFXMMU_LUT570H,GFXMMU LUT entry 570 high" hexmask.long.tbyte 0x1D4 0.--17. 1. "LO,Line offset" line.long 0x1D8 "GFXMMU_LUT571L,GFXMMU LUT entry 571 low" hexmask.long.byte 0x1D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1DC "GFXMMU_LUT571H,GFXMMU LUT entry 571 high" hexmask.long.tbyte 0x1DC 0.--17. 1. "LO,Line offset" line.long 0x1E0 "GFXMMU_LUT572L,GFXMMU LUT entry 572 low" hexmask.long.byte 0x1E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1E4 "GFXMMU_LUT572H,GFXMMU LUT entry 572 high" hexmask.long.tbyte 0x1E4 0.--17. 1. "LO,Line offset" line.long 0x1E8 "GFXMMU_LUT573L,GFXMMU LUT entry 573 low" hexmask.long.byte 0x1E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1EC "GFXMMU_LUT573H,GFXMMU LUT entry 573 high" hexmask.long.tbyte 0x1EC 0.--17. 1. "LO,Line offset" line.long 0x1F0 "GFXMMU_LUT574L,GFXMMU LUT entry 574 low" hexmask.long.byte 0x1F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x1F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1F4 "GFXMMU_LUT574H,GFXMMU LUT entry 574 high" hexmask.long.tbyte 0x1F4 0.--17. 1. "LO,Line offset" line.long 0x1F8 "GFXMMU_LUT575L,GFXMMU LUT entry 575 low" hexmask.long.byte 0x1F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x1F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x1F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x1FC "GFXMMU_LUT575H,GFXMMU LUT entry 575 high" hexmask.long.tbyte 0x1FC 0.--17. 1. "LO,Line offset" line.long 0x200 "GFXMMU_LUT576L,GFXMMU LUT entry 576 low" hexmask.long.byte 0x200 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x200 8.--15. 1. "FVB,First valid block" bitfld.long 0x200 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x204 "GFXMMU_LUT576H,GFXMMU LUT entry 576 high" hexmask.long.tbyte 0x204 0.--17. 1. "LO,Line offset" line.long 0x208 "GFXMMU_LUT577L,GFXMMU LUT entry 577 low" hexmask.long.byte 0x208 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x208 8.--15. 1. "FVB,First valid block" bitfld.long 0x208 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x20C "GFXMMU_LUT577H,GFXMMU LUT entry 577 high" hexmask.long.tbyte 0x20C 0.--17. 1. "LO,Line offset" line.long 0x210 "GFXMMU_LUT578L,GFXMMU LUT entry 578 low" hexmask.long.byte 0x210 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x210 8.--15. 1. "FVB,First valid block" bitfld.long 0x210 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x214 "GFXMMU_LUT578H,GFXMMU LUT entry 578 high" hexmask.long.tbyte 0x214 0.--17. 1. "LO,Line offset" line.long 0x218 "GFXMMU_LUT579L,GFXMMU LUT entry 579 low" hexmask.long.byte 0x218 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x218 8.--15. 1. "FVB,First valid block" bitfld.long 0x218 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x21C "GFXMMU_LUT579H,GFXMMU LUT entry 579 high" hexmask.long.tbyte 0x21C 0.--17. 1. "LO,Line offset" line.long 0x220 "GFXMMU_LUT580L,GFXMMU LUT entry 580 low" hexmask.long.byte 0x220 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x220 8.--15. 1. "FVB,First valid block" bitfld.long 0x220 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x224 "GFXMMU_LUT580H,GFXMMU LUT entry 580 high" hexmask.long.tbyte 0x224 0.--17. 1. "LO,Line offset" line.long 0x228 "GFXMMU_LUT581L,GFXMMU LUT entry 581 low" hexmask.long.byte 0x228 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x228 8.--15. 1. "FVB,First valid block" bitfld.long 0x228 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x22C "GFXMMU_LUT581H,GFXMMU LUT entry 581 high" hexmask.long.tbyte 0x22C 0.--17. 1. "LO,Line offset" line.long 0x230 "GFXMMU_LUT582L,GFXMMU LUT entry 582 low" hexmask.long.byte 0x230 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x230 8.--15. 1. "FVB,First valid block" bitfld.long 0x230 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x234 "GFXMMU_LUT582H,GFXMMU LUT entry 582 high" hexmask.long.tbyte 0x234 0.--17. 1. "LO,Line offset" line.long 0x238 "GFXMMU_LUT583L,GFXMMU LUT entry 583 low" hexmask.long.byte 0x238 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x238 8.--15. 1. "FVB,First valid block" bitfld.long 0x238 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x23C "GFXMMU_LUT583H,GFXMMU LUT entry 583 high" hexmask.long.tbyte 0x23C 0.--17. 1. "LO,Line offset" line.long 0x240 "GFXMMU_LUT584L,GFXMMU LUT entry 584 low" hexmask.long.byte 0x240 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x240 8.--15. 1. "FVB,First valid block" bitfld.long 0x240 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x244 "GFXMMU_LUT584H,GFXMMU LUT entry 584 high" hexmask.long.tbyte 0x244 0.--17. 1. "LO,Line offset" line.long 0x248 "GFXMMU_LUT585L,GFXMMU LUT entry 585 low" hexmask.long.byte 0x248 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x248 8.--15. 1. "FVB,First valid block" bitfld.long 0x248 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x24C "GFXMMU_LUT585H,GFXMMU LUT entry 585 high" hexmask.long.tbyte 0x24C 0.--17. 1. "LO,Line offset" line.long 0x250 "GFXMMU_LUT586L,GFXMMU LUT entry 586 low" hexmask.long.byte 0x250 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x250 8.--15. 1. "FVB,First valid block" bitfld.long 0x250 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x254 "GFXMMU_LUT586H,GFXMMU LUT entry 586 high" hexmask.long.tbyte 0x254 0.--17. 1. "LO,Line offset" line.long 0x258 "GFXMMU_LUT587L,GFXMMU LUT entry 587 low" hexmask.long.byte 0x258 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x258 8.--15. 1. "FVB,First valid block" bitfld.long 0x258 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x25C "GFXMMU_LUT587H,GFXMMU LUT entry 587 high" hexmask.long.tbyte 0x25C 0.--17. 1. "LO,Line offset" line.long 0x260 "GFXMMU_LUT588L,GFXMMU LUT entry 588 low" hexmask.long.byte 0x260 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x260 8.--15. 1. "FVB,First valid block" bitfld.long 0x260 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x264 "GFXMMU_LUT588H,GFXMMU LUT entry 588 high" hexmask.long.tbyte 0x264 0.--17. 1. "LO,Line offset" line.long 0x268 "GFXMMU_LUT589L,GFXMMU LUT entry 589 low" hexmask.long.byte 0x268 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x268 8.--15. 1. "FVB,First valid block" bitfld.long 0x268 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x26C "GFXMMU_LUT589H,GFXMMU LUT entry 589 high" hexmask.long.tbyte 0x26C 0.--17. 1. "LO,Line offset" line.long 0x270 "GFXMMU_LUT590L,GFXMMU LUT entry 590 low" hexmask.long.byte 0x270 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x270 8.--15. 1. "FVB,First valid block" bitfld.long 0x270 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x274 "GFXMMU_LUT590H,GFXMMU LUT entry 590 high" hexmask.long.tbyte 0x274 0.--17. 1. "LO,Line offset" line.long 0x278 "GFXMMU_LUT591L,GFXMMU LUT entry 591 low" hexmask.long.byte 0x278 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x278 8.--15. 1. "FVB,First valid block" bitfld.long 0x278 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x27C "GFXMMU_LUT591H,GFXMMU LUT entry 591 high" hexmask.long.tbyte 0x27C 0.--17. 1. "LO,Line offset" line.long 0x280 "GFXMMU_LUT592L,GFXMMU LUT entry 592 low" hexmask.long.byte 0x280 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x280 8.--15. 1. "FVB,First valid block" bitfld.long 0x280 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x284 "GFXMMU_LUT592H,GFXMMU LUT entry 592 high" hexmask.long.tbyte 0x284 0.--17. 1. "LO,Line offset" line.long 0x288 "GFXMMU_LUT593L,GFXMMU LUT entry 593 low" hexmask.long.byte 0x288 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x288 8.--15. 1. "FVB,First valid block" bitfld.long 0x288 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x28C "GFXMMU_LUT593H,GFXMMU LUT entry 593 high" hexmask.long.tbyte 0x28C 0.--17. 1. "LO,Line offset" line.long 0x290 "GFXMMU_LUT594L,GFXMMU LUT entry 594 low" hexmask.long.byte 0x290 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x290 8.--15. 1. "FVB,First valid block" bitfld.long 0x290 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x294 "GFXMMU_LUT594H,GFXMMU LUT entry 594 high" hexmask.long.tbyte 0x294 0.--17. 1. "LO,Line offset" line.long 0x298 "GFXMMU_LUT595L,GFXMMU LUT entry 595 low" hexmask.long.byte 0x298 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x298 8.--15. 1. "FVB,First valid block" bitfld.long 0x298 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x29C "GFXMMU_LUT595H,GFXMMU LUT entry 595 high" hexmask.long.tbyte 0x29C 0.--17. 1. "LO,Line offset" line.long 0x2A0 "GFXMMU_LUT596L,GFXMMU LUT entry 596 low" hexmask.long.byte 0x2A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2A4 "GFXMMU_LUT596H,GFXMMU LUT entry 596 high" hexmask.long.tbyte 0x2A4 0.--17. 1. "LO,Line offset" line.long 0x2A8 "GFXMMU_LUT597L,GFXMMU LUT entry 597 low" hexmask.long.byte 0x2A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2AC "GFXMMU_LUT597H,GFXMMU LUT entry 597 high" hexmask.long.tbyte 0x2AC 0.--17. 1. "LO,Line offset" line.long 0x2B0 "GFXMMU_LUT598L,GFXMMU LUT entry 598 low" hexmask.long.byte 0x2B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2B4 "GFXMMU_LUT598H,GFXMMU LUT entry 598 high" hexmask.long.tbyte 0x2B4 0.--17. 1. "LO,Line offset" line.long 0x2B8 "GFXMMU_LUT599L,GFXMMU LUT entry 599 low" hexmask.long.byte 0x2B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2BC "GFXMMU_LUT599H,GFXMMU LUT entry 599 high" hexmask.long.tbyte 0x2BC 0.--17. 1. "LO,Line offset" line.long 0x2C0 "GFXMMU_LUT600L,GFXMMU LUT entry 600 low" hexmask.long.byte 0x2C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2C4 "GFXMMU_LUT600H,GFXMMU LUT entry 600 high" hexmask.long.tbyte 0x2C4 0.--17. 1. "LO,Line offset" line.long 0x2C8 "GFXMMU_LUT601L,GFXMMU LUT entry 601 low" hexmask.long.byte 0x2C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2CC "GFXMMU_LUT601H,GFXMMU LUT entry 601 high" hexmask.long.tbyte 0x2CC 0.--17. 1. "LO,Line offset" line.long 0x2D0 "GFXMMU_LUT602L,GFXMMU LUT entry 602 low" hexmask.long.byte 0x2D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2D4 "GFXMMU_LUT602H,GFXMMU LUT entry 602 high" hexmask.long.tbyte 0x2D4 0.--17. 1. "LO,Line offset" line.long 0x2D8 "GFXMMU_LUT603L,GFXMMU LUT entry 603 low" hexmask.long.byte 0x2D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2DC "GFXMMU_LUT603H,GFXMMU LUT entry 603 high" hexmask.long.tbyte 0x2DC 0.--17. 1. "LO,Line offset" line.long 0x2E0 "GFXMMU_LUT604L,GFXMMU LUT entry 604 low" hexmask.long.byte 0x2E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2E4 "GFXMMU_LUT604H,GFXMMU LUT entry 604 high" hexmask.long.tbyte 0x2E4 0.--17. 1. "LO,Line offset" line.long 0x2E8 "GFXMMU_LUT605L,GFXMMU LUT entry 605 low" hexmask.long.byte 0x2E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2EC "GFXMMU_LUT605H,GFXMMU LUT entry 605 high" hexmask.long.tbyte 0x2EC 0.--17. 1. "LO,Line offset" line.long 0x2F0 "GFXMMU_LUT606L,GFXMMU LUT entry 606 low" hexmask.long.byte 0x2F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x2F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2F4 "GFXMMU_LUT606H,GFXMMU LUT entry 606 high" hexmask.long.tbyte 0x2F4 0.--17. 1. "LO,Line offset" line.long 0x2F8 "GFXMMU_LUT607L,GFXMMU LUT entry 607 low" hexmask.long.byte 0x2F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x2F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x2F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x2FC "GFXMMU_LUT607H,GFXMMU LUT entry 607 high" hexmask.long.tbyte 0x2FC 0.--17. 1. "LO,Line offset" line.long 0x300 "GFXMMU_LUT608L,GFXMMU LUT entry 608 low" hexmask.long.byte 0x300 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x300 8.--15. 1. "FVB,First valid block" bitfld.long 0x300 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x304 "GFXMMU_LUT608H,GFXMMU LUT entry 608 high" hexmask.long.tbyte 0x304 0.--17. 1. "LO,Line offset" line.long 0x308 "GFXMMU_LUT609L,GFXMMU LUT entry 609 low" hexmask.long.byte 0x308 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x308 8.--15. 1. "FVB,First valid block" bitfld.long 0x308 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x30C "GFXMMU_LUT609H,GFXMMU LUT entry 609 high" hexmask.long.tbyte 0x30C 0.--17. 1. "LO,Line offset" line.long 0x310 "GFXMMU_LUT610L,GFXMMU LUT entry 610 low" hexmask.long.byte 0x310 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x310 8.--15. 1. "FVB,First valid block" bitfld.long 0x310 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x314 "GFXMMU_LUT610H,GFXMMU LUT entry 610 high" hexmask.long.tbyte 0x314 0.--17. 1. "LO,Line offset" line.long 0x318 "GFXMMU_LUT611L,GFXMMU LUT entry 611 low" hexmask.long.byte 0x318 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x318 8.--15. 1. "FVB,First valid block" bitfld.long 0x318 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x31C "GFXMMU_LUT611H,GFXMMU LUT entry 611 high" hexmask.long.tbyte 0x31C 0.--17. 1. "LO,Line offset" line.long 0x320 "GFXMMU_LUT612L,GFXMMU LUT entry 612 low" hexmask.long.byte 0x320 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x320 8.--15. 1. "FVB,First valid block" bitfld.long 0x320 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x324 "GFXMMU_LUT612H,GFXMMU LUT entry 612 high" hexmask.long.tbyte 0x324 0.--17. 1. "LO,Line offset" line.long 0x328 "GFXMMU_LUT613L,GFXMMU LUT entry 613 low" hexmask.long.byte 0x328 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x328 8.--15. 1. "FVB,First valid block" bitfld.long 0x328 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x32C "GFXMMU_LUT613H,GFXMMU LUT entry 613 high" hexmask.long.tbyte 0x32C 0.--17. 1. "LO,Line offset" line.long 0x330 "GFXMMU_LUT614L,GFXMMU LUT entry 614 low" hexmask.long.byte 0x330 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x330 8.--15. 1. "FVB,First valid block" bitfld.long 0x330 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x334 "GFXMMU_LUT614H,GFXMMU LUT entry 614 high" hexmask.long.tbyte 0x334 0.--17. 1. "LO,Line offset" line.long 0x338 "GFXMMU_LUT615L,GFXMMU LUT entry 615 low" hexmask.long.byte 0x338 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x338 8.--15. 1. "FVB,First valid block" bitfld.long 0x338 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x33C "GFXMMU_LUT615H,GFXMMU LUT entry 615 high" hexmask.long.tbyte 0x33C 0.--17. 1. "LO,Line offset" line.long 0x340 "GFXMMU_LUT616L,GFXMMU LUT entry 616 low" hexmask.long.byte 0x340 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x340 8.--15. 1. "FVB,First valid block" bitfld.long 0x340 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x344 "GFXMMU_LUT616H,GFXMMU LUT entry 616 high" hexmask.long.tbyte 0x344 0.--17. 1. "LO,Line offset" line.long 0x348 "GFXMMU_LUT617L,GFXMMU LUT entry 617 low" hexmask.long.byte 0x348 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x348 8.--15. 1. "FVB,First valid block" bitfld.long 0x348 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x34C "GFXMMU_LUT617H,GFXMMU LUT entry 617 high" hexmask.long.tbyte 0x34C 0.--17. 1. "LO,Line offset" line.long 0x350 "GFXMMU_LUT618L,GFXMMU LUT entry 618 low" hexmask.long.byte 0x350 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x350 8.--15. 1. "FVB,First valid block" bitfld.long 0x350 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x354 "GFXMMU_LUT618H,GFXMMU LUT entry 618 high" hexmask.long.tbyte 0x354 0.--17. 1. "LO,Line offset" line.long 0x358 "GFXMMU_LUT619L,GFXMMU LUT entry 619 low" hexmask.long.byte 0x358 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x358 8.--15. 1. "FVB,First valid block" bitfld.long 0x358 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x35C "GFXMMU_LUT619H,GFXMMU LUT entry 619 high" hexmask.long.tbyte 0x35C 0.--17. 1. "LO,Line offset" line.long 0x360 "GFXMMU_LUT620L,GFXMMU LUT entry 620 low" hexmask.long.byte 0x360 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x360 8.--15. 1. "FVB,First valid block" bitfld.long 0x360 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x364 "GFXMMU_LUT620H,GFXMMU LUT entry 620 high" hexmask.long.tbyte 0x364 0.--17. 1. "LO,Line offset" line.long 0x368 "GFXMMU_LUT621L,GFXMMU LUT entry 621 low" hexmask.long.byte 0x368 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x368 8.--15. 1. "FVB,First valid block" bitfld.long 0x368 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x36C "GFXMMU_LUT621H,GFXMMU LUT entry 621 high" hexmask.long.tbyte 0x36C 0.--17. 1. "LO,Line offset" line.long 0x370 "GFXMMU_LUT622L,GFXMMU LUT entry 622 low" hexmask.long.byte 0x370 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x370 8.--15. 1. "FVB,First valid block" bitfld.long 0x370 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x374 "GFXMMU_LUT622H,GFXMMU LUT entry 622 high" hexmask.long.tbyte 0x374 0.--17. 1. "LO,Line offset" line.long 0x378 "GFXMMU_LUT623L,GFXMMU LUT entry 623 low" hexmask.long.byte 0x378 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x378 8.--15. 1. "FVB,First valid block" bitfld.long 0x378 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x37C "GFXMMU_LUT623H,GFXMMU LUT entry 623 high" hexmask.long.tbyte 0x37C 0.--17. 1. "LO,Line offset" line.long 0x380 "GFXMMU_LUT624L,GFXMMU LUT entry 624 low" hexmask.long.byte 0x380 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x380 8.--15. 1. "FVB,First valid block" bitfld.long 0x380 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x384 "GFXMMU_LUT624H,GFXMMU LUT entry 624 high" hexmask.long.tbyte 0x384 0.--17. 1. "LO,Line offset" line.long 0x388 "GFXMMU_LUT625L,GFXMMU LUT entry 625 low" hexmask.long.byte 0x388 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x388 8.--15. 1. "FVB,First valid block" bitfld.long 0x388 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x38C "GFXMMU_LUT625H,GFXMMU LUT entry 625 high" hexmask.long.tbyte 0x38C 0.--17. 1. "LO,Line offset" line.long 0x390 "GFXMMU_LUT626L,GFXMMU LUT entry 626 low" hexmask.long.byte 0x390 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x390 8.--15. 1. "FVB,First valid block" bitfld.long 0x390 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x394 "GFXMMU_LUT626H,GFXMMU LUT entry 626 high" hexmask.long.tbyte 0x394 0.--17. 1. "LO,Line offset" line.long 0x398 "GFXMMU_LUT627L,GFXMMU LUT entry 627 low" hexmask.long.byte 0x398 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x398 8.--15. 1. "FVB,First valid block" bitfld.long 0x398 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x39C "GFXMMU_LUT627H,GFXMMU LUT entry 627 high" hexmask.long.tbyte 0x39C 0.--17. 1. "LO,Line offset" line.long 0x3A0 "GFXMMU_LUT628L,GFXMMU LUT entry 628 low" hexmask.long.byte 0x3A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3A4 "GFXMMU_LUT628H,GFXMMU LUT entry 628 high" hexmask.long.tbyte 0x3A4 0.--17. 1. "LO,Line offset" line.long 0x3A8 "GFXMMU_LUT629L,GFXMMU LUT entry 629 low" hexmask.long.byte 0x3A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3AC "GFXMMU_LUT629H,GFXMMU LUT entry 629 high" hexmask.long.tbyte 0x3AC 0.--17. 1. "LO,Line offset" line.long 0x3B0 "GFXMMU_LUT630L,GFXMMU LUT entry 630 low" hexmask.long.byte 0x3B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3B4 "GFXMMU_LUT630H,GFXMMU LUT entry 630 high" hexmask.long.tbyte 0x3B4 0.--17. 1. "LO,Line offset" line.long 0x3B8 "GFXMMU_LUT631L,GFXMMU LUT entry 631 low" hexmask.long.byte 0x3B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3BC "GFXMMU_LUT631H,GFXMMU LUT entry 631 high" hexmask.long.tbyte 0x3BC 0.--17. 1. "LO,Line offset" line.long 0x3C0 "GFXMMU_LUT632L,GFXMMU LUT entry 632 low" hexmask.long.byte 0x3C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3C4 "GFXMMU_LUT632H,GFXMMU LUT entry 632 high" hexmask.long.tbyte 0x3C4 0.--17. 1. "LO,Line offset" line.long 0x3C8 "GFXMMU_LUT633L,GFXMMU LUT entry 633 low" hexmask.long.byte 0x3C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3CC "GFXMMU_LUT633H,GFXMMU LUT entry 633 high" hexmask.long.tbyte 0x3CC 0.--17. 1. "LO,Line offset" line.long 0x3D0 "GFXMMU_LUT634L,GFXMMU LUT entry 634 low" hexmask.long.byte 0x3D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3D4 "GFXMMU_LUT634H,GFXMMU LUT entry 634 high" hexmask.long.tbyte 0x3D4 0.--17. 1. "LO,Line offset" line.long 0x3D8 "GFXMMU_LUT635L,GFXMMU LUT entry 635 low" hexmask.long.byte 0x3D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3DC "GFXMMU_LUT635H,GFXMMU LUT entry 635 high" hexmask.long.tbyte 0x3DC 0.--17. 1. "LO,Line offset" line.long 0x3E0 "GFXMMU_LUT636L,GFXMMU LUT entry 636 low" hexmask.long.byte 0x3E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3E4 "GFXMMU_LUT636H,GFXMMU LUT entry 636 high" hexmask.long.tbyte 0x3E4 0.--17. 1. "LO,Line offset" line.long 0x3E8 "GFXMMU_LUT637L,GFXMMU LUT entry 637 low" hexmask.long.byte 0x3E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3EC "GFXMMU_LUT637H,GFXMMU LUT entry 637 high" hexmask.long.tbyte 0x3EC 0.--17. 1. "LO,Line offset" line.long 0x3F0 "GFXMMU_LUT638L,GFXMMU LUT entry 638 low" hexmask.long.byte 0x3F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x3F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3F4 "GFXMMU_LUT638H,GFXMMU LUT entry 638 high" hexmask.long.tbyte 0x3F4 0.--17. 1. "LO,Line offset" line.long 0x3F8 "GFXMMU_LUT639L,GFXMMU LUT entry 639 low" hexmask.long.byte 0x3F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x3F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x3F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x3FC "GFXMMU_LUT639H,GFXMMU LUT entry 639 high" hexmask.long.tbyte 0x3FC 0.--17. 1. "LO,Line offset" line.long 0x400 "GFXMMU_LUT640L,GFXMMU LUT entry 640 low" hexmask.long.byte 0x400 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x400 8.--15. 1. "FVB,First valid block" bitfld.long 0x400 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x404 "GFXMMU_LUT640H,GFXMMU LUT entry 640 high" hexmask.long.tbyte 0x404 0.--17. 1. "LO,Line offset" line.long 0x408 "GFXMMU_LUT641L,GFXMMU LUT entry 641 low" hexmask.long.byte 0x408 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x408 8.--15. 1. "FVB,First valid block" bitfld.long 0x408 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x40C "GFXMMU_LUT641H,GFXMMU LUT entry 641 high" hexmask.long.tbyte 0x40C 0.--17. 1. "LO,Line offset" line.long 0x410 "GFXMMU_LUT642L,GFXMMU LUT entry 642 low" hexmask.long.byte 0x410 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x410 8.--15. 1. "FVB,First valid block" bitfld.long 0x410 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x414 "GFXMMU_LUT642H,GFXMMU LUT entry 642 high" hexmask.long.tbyte 0x414 0.--17. 1. "LO,Line offset" line.long 0x418 "GFXMMU_LUT643L,GFXMMU LUT entry 643 low" hexmask.long.byte 0x418 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x418 8.--15. 1. "FVB,First valid block" bitfld.long 0x418 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x41C "GFXMMU_LUT643H,GFXMMU LUT entry 643 high" hexmask.long.tbyte 0x41C 0.--17. 1. "LO,Line offset" line.long 0x420 "GFXMMU_LUT644L,GFXMMU LUT entry 644 low" hexmask.long.byte 0x420 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x420 8.--15. 1. "FVB,First valid block" bitfld.long 0x420 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x424 "GFXMMU_LUT644H,GFXMMU LUT entry 644 high" hexmask.long.tbyte 0x424 0.--17. 1. "LO,Line offset" line.long 0x428 "GFXMMU_LUT645L,GFXMMU LUT entry 645 low" hexmask.long.byte 0x428 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x428 8.--15. 1. "FVB,First valid block" bitfld.long 0x428 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x42C "GFXMMU_LUT645H,GFXMMU LUT entry 645 high" hexmask.long.tbyte 0x42C 0.--17. 1. "LO,Line offset" line.long 0x430 "GFXMMU_LUT646L,GFXMMU LUT entry 646 low" hexmask.long.byte 0x430 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x430 8.--15. 1. "FVB,First valid block" bitfld.long 0x430 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x434 "GFXMMU_LUT646H,GFXMMU LUT entry 646 high" hexmask.long.tbyte 0x434 0.--17. 1. "LO,Line offset" line.long 0x438 "GFXMMU_LUT647L,GFXMMU LUT entry 647 low" hexmask.long.byte 0x438 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x438 8.--15. 1. "FVB,First valid block" bitfld.long 0x438 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x43C "GFXMMU_LUT647H,GFXMMU LUT entry 647 high" hexmask.long.tbyte 0x43C 0.--17. 1. "LO,Line offset" line.long 0x440 "GFXMMU_LUT648L,GFXMMU LUT entry 648 low" hexmask.long.byte 0x440 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x440 8.--15. 1. "FVB,First valid block" bitfld.long 0x440 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x444 "GFXMMU_LUT648H,GFXMMU LUT entry 648 high" hexmask.long.tbyte 0x444 0.--17. 1. "LO,Line offset" line.long 0x448 "GFXMMU_LUT649L,GFXMMU LUT entry 649 low" hexmask.long.byte 0x448 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x448 8.--15. 1. "FVB,First valid block" bitfld.long 0x448 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x44C "GFXMMU_LUT649H,GFXMMU LUT entry 649 high" hexmask.long.tbyte 0x44C 0.--17. 1. "LO,Line offset" line.long 0x450 "GFXMMU_LUT650L,GFXMMU LUT entry 650 low" hexmask.long.byte 0x450 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x450 8.--15. 1. "FVB,First valid block" bitfld.long 0x450 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x454 "GFXMMU_LUT650H,GFXMMU LUT entry 650 high" hexmask.long.tbyte 0x454 0.--17. 1. "LO,Line offset" line.long 0x458 "GFXMMU_LUT651L,GFXMMU LUT entry 651 low" hexmask.long.byte 0x458 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x458 8.--15. 1. "FVB,First valid block" bitfld.long 0x458 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x45C "GFXMMU_LUT651H,GFXMMU LUT entry 651 high" hexmask.long.tbyte 0x45C 0.--17. 1. "LO,Line offset" line.long 0x460 "GFXMMU_LUT652L,GFXMMU LUT entry 652 low" hexmask.long.byte 0x460 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x460 8.--15. 1. "FVB,First valid block" bitfld.long 0x460 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x464 "GFXMMU_LUT652H,GFXMMU LUT entry 652 high" hexmask.long.tbyte 0x464 0.--17. 1. "LO,Line offset" line.long 0x468 "GFXMMU_LUT653L,GFXMMU LUT entry 653 low" hexmask.long.byte 0x468 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x468 8.--15. 1. "FVB,First valid block" bitfld.long 0x468 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x46C "GFXMMU_LUT653H,GFXMMU LUT entry 653 high" hexmask.long.tbyte 0x46C 0.--17. 1. "LO,Line offset" line.long 0x470 "GFXMMU_LUT654L,GFXMMU LUT entry 654 low" hexmask.long.byte 0x470 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x470 8.--15. 1. "FVB,First valid block" bitfld.long 0x470 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x474 "GFXMMU_LUT654H,GFXMMU LUT entry 654 high" hexmask.long.tbyte 0x474 0.--17. 1. "LO,Line offset" line.long 0x478 "GFXMMU_LUT655L,GFXMMU LUT entry 655 low" hexmask.long.byte 0x478 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x478 8.--15. 1. "FVB,First valid block" bitfld.long 0x478 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x47C "GFXMMU_LUT655H,GFXMMU LUT entry 655 high" hexmask.long.tbyte 0x47C 0.--17. 1. "LO,Line offset" line.long 0x480 "GFXMMU_LUT656L,GFXMMU LUT entry 656 low" hexmask.long.byte 0x480 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x480 8.--15. 1. "FVB,First valid block" bitfld.long 0x480 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x484 "GFXMMU_LUT656H,GFXMMU LUT entry 656 high" hexmask.long.tbyte 0x484 0.--17. 1. "LO,Line offset" line.long 0x488 "GFXMMU_LUT657L,GFXMMU LUT entry 657 low" hexmask.long.byte 0x488 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x488 8.--15. 1. "FVB,First valid block" bitfld.long 0x488 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x48C "GFXMMU_LUT657H,GFXMMU LUT entry 657 high" hexmask.long.tbyte 0x48C 0.--17. 1. "LO,Line offset" line.long 0x490 "GFXMMU_LUT658L,GFXMMU LUT entry 658 low" hexmask.long.byte 0x490 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x490 8.--15. 1. "FVB,First valid block" bitfld.long 0x490 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x494 "GFXMMU_LUT658H,GFXMMU LUT entry 658 high" hexmask.long.tbyte 0x494 0.--17. 1. "LO,Line offset" line.long 0x498 "GFXMMU_LUT659L,GFXMMU LUT entry 659 low" hexmask.long.byte 0x498 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x498 8.--15. 1. "FVB,First valid block" bitfld.long 0x498 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x49C "GFXMMU_LUT659H,GFXMMU LUT entry 659 high" hexmask.long.tbyte 0x49C 0.--17. 1. "LO,Line offset" line.long 0x4A0 "GFXMMU_LUT660L,GFXMMU LUT entry 660 low" hexmask.long.byte 0x4A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4A4 "GFXMMU_LUT660H,GFXMMU LUT entry 660 high" hexmask.long.tbyte 0x4A4 0.--17. 1. "LO,Line offset" line.long 0x4A8 "GFXMMU_LUT661L,GFXMMU LUT entry 661 low" hexmask.long.byte 0x4A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4AC "GFXMMU_LUT661H,GFXMMU LUT entry 661 high" hexmask.long.tbyte 0x4AC 0.--17. 1. "LO,Line offset" line.long 0x4B0 "GFXMMU_LUT662L,GFXMMU LUT entry 662 low" hexmask.long.byte 0x4B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4B4 "GFXMMU_LUT662H,GFXMMU LUT entry 662 high" hexmask.long.tbyte 0x4B4 0.--17. 1. "LO,Line offset" line.long 0x4B8 "GFXMMU_LUT663L,GFXMMU LUT entry 663 low" hexmask.long.byte 0x4B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4BC "GFXMMU_LUT663H,GFXMMU LUT entry 663 high" hexmask.long.tbyte 0x4BC 0.--17. 1. "LO,Line offset" line.long 0x4C0 "GFXMMU_LUT664L,GFXMMU LUT entry 664 low" hexmask.long.byte 0x4C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4C4 "GFXMMU_LUT664H,GFXMMU LUT entry 664 high" hexmask.long.tbyte 0x4C4 0.--17. 1. "LO,Line offset" line.long 0x4C8 "GFXMMU_LUT665L,GFXMMU LUT entry 665 low" hexmask.long.byte 0x4C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4CC "GFXMMU_LUT665H,GFXMMU LUT entry 665 high" hexmask.long.tbyte 0x4CC 0.--17. 1. "LO,Line offset" line.long 0x4D0 "GFXMMU_LUT666L,GFXMMU LUT entry 666 low" hexmask.long.byte 0x4D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4D4 "GFXMMU_LUT666H,GFXMMU LUT entry 666 high" hexmask.long.tbyte 0x4D4 0.--17. 1. "LO,Line offset" line.long 0x4D8 "GFXMMU_LUT667L,GFXMMU LUT entry 667 low" hexmask.long.byte 0x4D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4DC "GFXMMU_LUT667H,GFXMMU LUT entry 667 high" hexmask.long.tbyte 0x4DC 0.--17. 1. "LO,Line offset" line.long 0x4E0 "GFXMMU_LUT668L,GFXMMU LUT entry 668 low" hexmask.long.byte 0x4E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4E4 "GFXMMU_LUT668H,GFXMMU LUT entry 668 high" hexmask.long.tbyte 0x4E4 0.--17. 1. "LO,Line offset" line.long 0x4E8 "GFXMMU_LUT669L,GFXMMU LUT entry 669 low" hexmask.long.byte 0x4E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4EC "GFXMMU_LUT669H,GFXMMU LUT entry 669 high" hexmask.long.tbyte 0x4EC 0.--17. 1. "LO,Line offset" line.long 0x4F0 "GFXMMU_LUT670L,GFXMMU LUT entry 670 low" hexmask.long.byte 0x4F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x4F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4F4 "GFXMMU_LUT670H,GFXMMU LUT entry 670 high" hexmask.long.tbyte 0x4F4 0.--17. 1. "LO,Line offset" line.long 0x4F8 "GFXMMU_LUT671L,GFXMMU LUT entry 671 low" hexmask.long.byte 0x4F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x4F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x4F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x4FC "GFXMMU_LUT671H,GFXMMU LUT entry 671 high" hexmask.long.tbyte 0x4FC 0.--17. 1. "LO,Line offset" line.long 0x500 "GFXMMU_LUT672L,GFXMMU LUT entry 672 low" hexmask.long.byte 0x500 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x500 8.--15. 1. "FVB,First valid block" bitfld.long 0x500 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x504 "GFXMMU_LUT672H,GFXMMU LUT entry 672 high" hexmask.long.tbyte 0x504 0.--17. 1. "LO,Line offset" line.long 0x508 "GFXMMU_LUT673L,GFXMMU LUT entry 673 low" hexmask.long.byte 0x508 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x508 8.--15. 1. "FVB,First valid block" bitfld.long 0x508 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x50C "GFXMMU_LUT673H,GFXMMU LUT entry 673 high" hexmask.long.tbyte 0x50C 0.--17. 1. "LO,Line offset" line.long 0x510 "GFXMMU_LUT674L,GFXMMU LUT entry 674 low" hexmask.long.byte 0x510 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x510 8.--15. 1. "FVB,First valid block" bitfld.long 0x510 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x514 "GFXMMU_LUT674H,GFXMMU LUT entry 674 high" hexmask.long.tbyte 0x514 0.--17. 1. "LO,Line offset" line.long 0x518 "GFXMMU_LUT675L,GFXMMU LUT entry 675 low" hexmask.long.byte 0x518 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x518 8.--15. 1. "FVB,First valid block" bitfld.long 0x518 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x51C "GFXMMU_LUT675H,GFXMMU LUT entry 675 high" hexmask.long.tbyte 0x51C 0.--17. 1. "LO,Line offset" line.long 0x520 "GFXMMU_LUT676L,GFXMMU LUT entry 676 low" hexmask.long.byte 0x520 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x520 8.--15. 1. "FVB,First valid block" bitfld.long 0x520 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x524 "GFXMMU_LUT676H,GFXMMU LUT entry 676 high" hexmask.long.tbyte 0x524 0.--17. 1. "LO,Line offset" line.long 0x528 "GFXMMU_LUT677L,GFXMMU LUT entry 677 low" hexmask.long.byte 0x528 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x528 8.--15. 1. "FVB,First valid block" bitfld.long 0x528 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x52C "GFXMMU_LUT677H,GFXMMU LUT entry 677 high" hexmask.long.tbyte 0x52C 0.--17. 1. "LO,Line offset" line.long 0x530 "GFXMMU_LUT678L,GFXMMU LUT entry 678 low" hexmask.long.byte 0x530 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x530 8.--15. 1. "FVB,First valid block" bitfld.long 0x530 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x534 "GFXMMU_LUT678H,GFXMMU LUT entry 678 high" hexmask.long.tbyte 0x534 0.--17. 1. "LO,Line offset" line.long 0x538 "GFXMMU_LUT679L,GFXMMU LUT entry 679 low" hexmask.long.byte 0x538 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x538 8.--15. 1. "FVB,First valid block" bitfld.long 0x538 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x53C "GFXMMU_LUT679H,GFXMMU LUT entry 679 high" hexmask.long.tbyte 0x53C 0.--17. 1. "LO,Line offset" line.long 0x540 "GFXMMU_LUT680L,GFXMMU LUT entry 680 low" hexmask.long.byte 0x540 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x540 8.--15. 1. "FVB,First valid block" bitfld.long 0x540 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x544 "GFXMMU_LUT680H,GFXMMU LUT entry 680 high" hexmask.long.tbyte 0x544 0.--17. 1. "LO,Line offset" line.long 0x548 "GFXMMU_LUT681L,GFXMMU LUT entry 681 low" hexmask.long.byte 0x548 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x548 8.--15. 1. "FVB,First valid block" bitfld.long 0x548 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x54C "GFXMMU_LUT681H,GFXMMU LUT entry 681 high" hexmask.long.tbyte 0x54C 0.--17. 1. "LO,Line offset" line.long 0x550 "GFXMMU_LUT682L,GFXMMU LUT entry 682 low" hexmask.long.byte 0x550 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x550 8.--15. 1. "FVB,First valid block" bitfld.long 0x550 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x554 "GFXMMU_LUT682H,GFXMMU LUT entry 682 high" hexmask.long.tbyte 0x554 0.--17. 1. "LO,Line offset" line.long 0x558 "GFXMMU_LUT683L,GFXMMU LUT entry 683 low" hexmask.long.byte 0x558 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x558 8.--15. 1. "FVB,First valid block" bitfld.long 0x558 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x55C "GFXMMU_LUT683H,GFXMMU LUT entry 683 high" hexmask.long.tbyte 0x55C 0.--17. 1. "LO,Line offset" line.long 0x560 "GFXMMU_LUT684L,GFXMMU LUT entry 684 low" hexmask.long.byte 0x560 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x560 8.--15. 1. "FVB,First valid block" bitfld.long 0x560 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x564 "GFXMMU_LUT684H,GFXMMU LUT entry 684 high" hexmask.long.tbyte 0x564 0.--17. 1. "LO,Line offset" line.long 0x568 "GFXMMU_LUT685L,GFXMMU LUT entry 685 low" hexmask.long.byte 0x568 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x568 8.--15. 1. "FVB,First valid block" bitfld.long 0x568 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x56C "GFXMMU_LUT685H,GFXMMU LUT entry 685 high" hexmask.long.tbyte 0x56C 0.--17. 1. "LO,Line offset" line.long 0x570 "GFXMMU_LUT686L,GFXMMU LUT entry 686 low" hexmask.long.byte 0x570 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x570 8.--15. 1. "FVB,First valid block" bitfld.long 0x570 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x574 "GFXMMU_LUT686H,GFXMMU LUT entry 686 high" hexmask.long.tbyte 0x574 0.--17. 1. "LO,Line offset" line.long 0x578 "GFXMMU_LUT687L,GFXMMU LUT entry 687 low" hexmask.long.byte 0x578 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x578 8.--15. 1. "FVB,First valid block" bitfld.long 0x578 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x57C "GFXMMU_LUT687H,GFXMMU LUT entry 687 high" hexmask.long.tbyte 0x57C 0.--17. 1. "LO,Line offset" line.long 0x580 "GFXMMU_LUT688L,GFXMMU LUT entry 688 low" hexmask.long.byte 0x580 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x580 8.--15. 1. "FVB,First valid block" bitfld.long 0x580 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x584 "GFXMMU_LUT688H,GFXMMU LUT entry 688 high" hexmask.long.tbyte 0x584 0.--17. 1. "LO,Line offset" line.long 0x588 "GFXMMU_LUT689L,GFXMMU LUT entry 689 low" hexmask.long.byte 0x588 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x588 8.--15. 1. "FVB,First valid block" bitfld.long 0x588 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x58C "GFXMMU_LUT689H,GFXMMU LUT entry 689 high" hexmask.long.tbyte 0x58C 0.--17. 1. "LO,Line offset" line.long 0x590 "GFXMMU_LUT690L,GFXMMU LUT entry 690 low" hexmask.long.byte 0x590 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x590 8.--15. 1. "FVB,First valid block" bitfld.long 0x590 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x594 "GFXMMU_LUT690H,GFXMMU LUT entry 690 high" hexmask.long.tbyte 0x594 0.--17. 1. "LO,Line offset" line.long 0x598 "GFXMMU_LUT691L,GFXMMU LUT entry 691 low" hexmask.long.byte 0x598 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x598 8.--15. 1. "FVB,First valid block" bitfld.long 0x598 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x59C "GFXMMU_LUT691H,GFXMMU LUT entry 691 high" hexmask.long.tbyte 0x59C 0.--17. 1. "LO,Line offset" line.long 0x5A0 "GFXMMU_LUT692L,GFXMMU LUT entry 692 low" hexmask.long.byte 0x5A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5A4 "GFXMMU_LUT692H,GFXMMU LUT entry 692 high" hexmask.long.tbyte 0x5A4 0.--17. 1. "LO,Line offset" line.long 0x5A8 "GFXMMU_LUT693L,GFXMMU LUT entry 693 low" hexmask.long.byte 0x5A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5AC "GFXMMU_LUT693H,GFXMMU LUT entry 693 high" hexmask.long.tbyte 0x5AC 0.--17. 1. "LO,Line offset" line.long 0x5B0 "GFXMMU_LUT694L,GFXMMU LUT entry 694 low" hexmask.long.byte 0x5B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5B4 "GFXMMU_LUT694H,GFXMMU LUT entry 694 high" hexmask.long.tbyte 0x5B4 0.--17. 1. "LO,Line offset" line.long 0x5B8 "GFXMMU_LUT695L,GFXMMU LUT entry 695 low" hexmask.long.byte 0x5B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5BC "GFXMMU_LUT695H,GFXMMU LUT entry 695 high" hexmask.long.tbyte 0x5BC 0.--17. 1. "LO,Line offset" line.long 0x5C0 "GFXMMU_LUT696L,GFXMMU LUT entry 696 low" hexmask.long.byte 0x5C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5C4 "GFXMMU_LUT696H,GFXMMU LUT entry 696 high" hexmask.long.tbyte 0x5C4 0.--17. 1. "LO,Line offset" line.long 0x5C8 "GFXMMU_LUT697L,GFXMMU LUT entry 697 low" hexmask.long.byte 0x5C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5CC "GFXMMU_LUT697H,GFXMMU LUT entry 697 high" hexmask.long.tbyte 0x5CC 0.--17. 1. "LO,Line offset" line.long 0x5D0 "GFXMMU_LUT698L,GFXMMU LUT entry 698 low" hexmask.long.byte 0x5D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5D4 "GFXMMU_LUT698H,GFXMMU LUT entry 698 high" hexmask.long.tbyte 0x5D4 0.--17. 1. "LO,Line offset" line.long 0x5D8 "GFXMMU_LUT699L,GFXMMU LUT entry 699 low" hexmask.long.byte 0x5D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5DC "GFXMMU_LUT699H,GFXMMU LUT entry 699 high" hexmask.long.tbyte 0x5DC 0.--17. 1. "LO,Line offset" line.long 0x5E0 "GFXMMU_LUT700L,GFXMMU LUT entry 700 low" hexmask.long.byte 0x5E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5E4 "GFXMMU_LUT700H,GFXMMU LUT entry 700 high" hexmask.long.tbyte 0x5E4 0.--17. 1. "LO,Line offset" line.long 0x5E8 "GFXMMU_LUT701L,GFXMMU LUT entry 701 low" hexmask.long.byte 0x5E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5EC "GFXMMU_LUT701H,GFXMMU LUT entry 701 high" hexmask.long.tbyte 0x5EC 0.--17. 1. "LO,Line offset" line.long 0x5F0 "GFXMMU_LUT702L,GFXMMU LUT entry 702 low" hexmask.long.byte 0x5F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x5F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5F4 "GFXMMU_LUT702H,GFXMMU LUT entry 702 high" hexmask.long.tbyte 0x5F4 0.--17. 1. "LO,Line offset" line.long 0x5F8 "GFXMMU_LUT703L,GFXMMU LUT entry 703 low" hexmask.long.byte 0x5F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x5F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x5F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x5FC "GFXMMU_LUT703H,GFXMMU LUT entry 703 high" hexmask.long.tbyte 0x5FC 0.--17. 1. "LO,Line offset" line.long 0x600 "GFXMMU_LUT704L,GFXMMU LUT entry 704 low" hexmask.long.byte 0x600 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x600 8.--15. 1. "FVB,First valid block" bitfld.long 0x600 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x604 "GFXMMU_LUT704H,GFXMMU LUT entry 704 high" hexmask.long.tbyte 0x604 0.--17. 1. "LO,Line offset" line.long 0x608 "GFXMMU_LUT705L,GFXMMU LUT entry 705 low" hexmask.long.byte 0x608 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x608 8.--15. 1. "FVB,First valid block" bitfld.long 0x608 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x60C "GFXMMU_LUT705H,GFXMMU LUT entry 705 high" hexmask.long.tbyte 0x60C 0.--17. 1. "LO,Line offset" line.long 0x610 "GFXMMU_LUT706L,GFXMMU LUT entry 706 low" hexmask.long.byte 0x610 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x610 8.--15. 1. "FVB,First valid block" bitfld.long 0x610 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x614 "GFXMMU_LUT706H,GFXMMU LUT entry 706 high" hexmask.long.tbyte 0x614 0.--17. 1. "LO,Line offset" line.long 0x618 "GFXMMU_LUT707L,GFXMMU LUT entry 707 low" hexmask.long.byte 0x618 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x618 8.--15. 1. "FVB,First valid block" bitfld.long 0x618 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x61C "GFXMMU_LUT707H,GFXMMU LUT entry 707 high" hexmask.long.tbyte 0x61C 0.--17. 1. "LO,Line offset" line.long 0x620 "GFXMMU_LUT708L,GFXMMU LUT entry 708 low" hexmask.long.byte 0x620 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x620 8.--15. 1. "FVB,First valid block" bitfld.long 0x620 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x624 "GFXMMU_LUT708H,GFXMMU LUT entry 708 high" hexmask.long.tbyte 0x624 0.--17. 1. "LO,Line offset" line.long 0x628 "GFXMMU_LUT709L,GFXMMU LUT entry 709 low" hexmask.long.byte 0x628 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x628 8.--15. 1. "FVB,First valid block" bitfld.long 0x628 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x62C "GFXMMU_LUT709H,GFXMMU LUT entry 709 high" hexmask.long.tbyte 0x62C 0.--17. 1. "LO,Line offset" line.long 0x630 "GFXMMU_LUT710L,GFXMMU LUT entry 710 low" hexmask.long.byte 0x630 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x630 8.--15. 1. "FVB,First valid block" bitfld.long 0x630 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x634 "GFXMMU_LUT710H,GFXMMU LUT entry 710 high" hexmask.long.tbyte 0x634 0.--17. 1. "LO,Line offset" line.long 0x638 "GFXMMU_LUT711L,GFXMMU LUT entry 711 low" hexmask.long.byte 0x638 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x638 8.--15. 1. "FVB,First valid block" bitfld.long 0x638 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x63C "GFXMMU_LUT711H,GFXMMU LUT entry 711 high" hexmask.long.tbyte 0x63C 0.--17. 1. "LO,Line offset" line.long 0x640 "GFXMMU_LUT712L,GFXMMU LUT entry 712 low" hexmask.long.byte 0x640 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x640 8.--15. 1. "FVB,First valid block" bitfld.long 0x640 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x644 "GFXMMU_LUT712H,GFXMMU LUT entry 712 high" hexmask.long.tbyte 0x644 0.--17. 1. "LO,Line offset" line.long 0x648 "GFXMMU_LUT713L,GFXMMU LUT entry 713 low" hexmask.long.byte 0x648 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x648 8.--15. 1. "FVB,First valid block" bitfld.long 0x648 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x64C "GFXMMU_LUT713H,GFXMMU LUT entry 713 high" hexmask.long.tbyte 0x64C 0.--17. 1. "LO,Line offset" line.long 0x650 "GFXMMU_LUT714L,GFXMMU LUT entry 714 low" hexmask.long.byte 0x650 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x650 8.--15. 1. "FVB,First valid block" bitfld.long 0x650 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x654 "GFXMMU_LUT714H,GFXMMU LUT entry 714 high" hexmask.long.tbyte 0x654 0.--17. 1. "LO,Line offset" line.long 0x658 "GFXMMU_LUT715L,GFXMMU LUT entry 715 low" hexmask.long.byte 0x658 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x658 8.--15. 1. "FVB,First valid block" bitfld.long 0x658 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x65C "GFXMMU_LUT715H,GFXMMU LUT entry 715 high" hexmask.long.tbyte 0x65C 0.--17. 1. "LO,Line offset" line.long 0x660 "GFXMMU_LUT716L,GFXMMU LUT entry 716 low" hexmask.long.byte 0x660 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x660 8.--15. 1. "FVB,First valid block" bitfld.long 0x660 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x664 "GFXMMU_LUT716H,GFXMMU LUT entry 716 high" hexmask.long.tbyte 0x664 0.--17. 1. "LO,Line offset" line.long 0x668 "GFXMMU_LUT717L,GFXMMU LUT entry 717 low" hexmask.long.byte 0x668 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x668 8.--15. 1. "FVB,First valid block" bitfld.long 0x668 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x66C "GFXMMU_LUT717H,GFXMMU LUT entry 717 high" hexmask.long.tbyte 0x66C 0.--17. 1. "LO,Line offset" line.long 0x670 "GFXMMU_LUT718L,GFXMMU LUT entry 718 low" hexmask.long.byte 0x670 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x670 8.--15. 1. "FVB,First valid block" bitfld.long 0x670 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x674 "GFXMMU_LUT718H,GFXMMU LUT entry 718 high" hexmask.long.tbyte 0x674 0.--17. 1. "LO,Line offset" line.long 0x678 "GFXMMU_LUT719L,GFXMMU LUT entry 719 low" hexmask.long.byte 0x678 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x678 8.--15. 1. "FVB,First valid block" bitfld.long 0x678 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x67C "GFXMMU_LUT719H,GFXMMU LUT entry 719 high" hexmask.long.tbyte 0x67C 0.--17. 1. "LO,Line offset" line.long 0x680 "GFXMMU_LUT720L,GFXMMU LUT entry 720 low" hexmask.long.byte 0x680 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x680 8.--15. 1. "FVB,First valid block" bitfld.long 0x680 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x684 "GFXMMU_LUT720H,GFXMMU LUT entry 720 high" hexmask.long.tbyte 0x684 0.--17. 1. "LO,Line offset" line.long 0x688 "GFXMMU_LUT721L,GFXMMU LUT entry 721 low" hexmask.long.byte 0x688 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x688 8.--15. 1. "FVB,First valid block" bitfld.long 0x688 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x68C "GFXMMU_LUT721H,GFXMMU LUT entry 721 high" hexmask.long.tbyte 0x68C 0.--17. 1. "LO,Line offset" line.long 0x690 "GFXMMU_LUT722L,GFXMMU LUT entry 722 low" hexmask.long.byte 0x690 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x690 8.--15. 1. "FVB,First valid block" bitfld.long 0x690 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x694 "GFXMMU_LUT722H,GFXMMU LUT entry 722 high" hexmask.long.tbyte 0x694 0.--17. 1. "LO,Line offset" line.long 0x698 "GFXMMU_LUT723L,GFXMMU LUT entry 723 low" hexmask.long.byte 0x698 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x698 8.--15. 1. "FVB,First valid block" bitfld.long 0x698 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x69C "GFXMMU_LUT723H,GFXMMU LUT entry 723 high" hexmask.long.tbyte 0x69C 0.--17. 1. "LO,Line offset" line.long 0x6A0 "GFXMMU_LUT724L,GFXMMU LUT entry 724 low" hexmask.long.byte 0x6A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6A4 "GFXMMU_LUT724H,GFXMMU LUT entry 724 high" hexmask.long.tbyte 0x6A4 0.--17. 1. "LO,Line offset" line.long 0x6A8 "GFXMMU_LUT725L,GFXMMU LUT entry 725 low" hexmask.long.byte 0x6A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6AC "GFXMMU_LUT725H,GFXMMU LUT entry 725 high" hexmask.long.tbyte 0x6AC 0.--17. 1. "LO,Line offset" line.long 0x6B0 "GFXMMU_LUT726L,GFXMMU LUT entry 726 low" hexmask.long.byte 0x6B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6B4 "GFXMMU_LUT726H,GFXMMU LUT entry 726 high" hexmask.long.tbyte 0x6B4 0.--17. 1. "LO,Line offset" line.long 0x6B8 "GFXMMU_LUT727L,GFXMMU LUT entry 727 low" hexmask.long.byte 0x6B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6BC "GFXMMU_LUT727H,GFXMMU LUT entry 727 high" hexmask.long.tbyte 0x6BC 0.--17. 1. "LO,Line offset" line.long 0x6C0 "GFXMMU_LUT728L,GFXMMU LUT entry 728 low" hexmask.long.byte 0x6C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6C4 "GFXMMU_LUT728H,GFXMMU LUT entry 728 high" hexmask.long.tbyte 0x6C4 0.--17. 1. "LO,Line offset" line.long 0x6C8 "GFXMMU_LUT729L,GFXMMU LUT entry 729 low" hexmask.long.byte 0x6C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6CC "GFXMMU_LUT729H,GFXMMU LUT entry 729 high" hexmask.long.tbyte 0x6CC 0.--17. 1. "LO,Line offset" line.long 0x6D0 "GFXMMU_LUT730L,GFXMMU LUT entry 730 low" hexmask.long.byte 0x6D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6D4 "GFXMMU_LUT730H,GFXMMU LUT entry 730 high" hexmask.long.tbyte 0x6D4 0.--17. 1. "LO,Line offset" line.long 0x6D8 "GFXMMU_LUT731L,GFXMMU LUT entry 731 low" hexmask.long.byte 0x6D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6DC "GFXMMU_LUT731H,GFXMMU LUT entry 731 high" hexmask.long.tbyte 0x6DC 0.--17. 1. "LO,Line offset" line.long 0x6E0 "GFXMMU_LUT732L,GFXMMU LUT entry 732 low" hexmask.long.byte 0x6E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6E4 "GFXMMU_LUT732H,GFXMMU LUT entry 732 high" hexmask.long.tbyte 0x6E4 0.--17. 1. "LO,Line offset" line.long 0x6E8 "GFXMMU_LUT733L,GFXMMU LUT entry 733 low" hexmask.long.byte 0x6E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6EC "GFXMMU_LUT733H,GFXMMU LUT entry 733 high" hexmask.long.tbyte 0x6EC 0.--17. 1. "LO,Line offset" line.long 0x6F0 "GFXMMU_LUT734L,GFXMMU LUT entry 734 low" hexmask.long.byte 0x6F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x6F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6F4 "GFXMMU_LUT734H,GFXMMU LUT entry 734 high" hexmask.long.tbyte 0x6F4 0.--17. 1. "LO,Line offset" line.long 0x6F8 "GFXMMU_LUT735L,GFXMMU LUT entry 735 low" hexmask.long.byte 0x6F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x6F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x6F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x6FC "GFXMMU_LUT735H,GFXMMU LUT entry 735 high" hexmask.long.tbyte 0x6FC 0.--17. 1. "LO,Line offset" line.long 0x700 "GFXMMU_LUT736L,GFXMMU LUT entry 736 low" hexmask.long.byte 0x700 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x700 8.--15. 1. "FVB,First valid block" bitfld.long 0x700 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x704 "GFXMMU_LUT736H,GFXMMU LUT entry 736 high" hexmask.long.tbyte 0x704 0.--17. 1. "LO,Line offset" line.long 0x708 "GFXMMU_LUT737L,GFXMMU LUT entry 737 low" hexmask.long.byte 0x708 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x708 8.--15. 1. "FVB,First valid block" bitfld.long 0x708 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x70C "GFXMMU_LUT737H,GFXMMU LUT entry 737 high" hexmask.long.tbyte 0x70C 0.--17. 1. "LO,Line offset" line.long 0x710 "GFXMMU_LUT738L,GFXMMU LUT entry 738 low" hexmask.long.byte 0x710 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x710 8.--15. 1. "FVB,First valid block" bitfld.long 0x710 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x714 "GFXMMU_LUT738H,GFXMMU LUT entry 738 high" hexmask.long.tbyte 0x714 0.--17. 1. "LO,Line offset" line.long 0x718 "GFXMMU_LUT739L,GFXMMU LUT entry 739 low" hexmask.long.byte 0x718 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x718 8.--15. 1. "FVB,First valid block" bitfld.long 0x718 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x71C "GFXMMU_LUT739H,GFXMMU LUT entry 739 high" hexmask.long.tbyte 0x71C 0.--17. 1. "LO,Line offset" line.long 0x720 "GFXMMU_LUT740L,GFXMMU LUT entry 740 low" hexmask.long.byte 0x720 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x720 8.--15. 1. "FVB,First valid block" bitfld.long 0x720 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x724 "GFXMMU_LUT740H,GFXMMU LUT entry 740 high" hexmask.long.tbyte 0x724 0.--17. 1. "LO,Line offset" line.long 0x728 "GFXMMU_LUT741L,GFXMMU LUT entry 741 low" hexmask.long.byte 0x728 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x728 8.--15. 1. "FVB,First valid block" bitfld.long 0x728 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x72C "GFXMMU_LUT741H,GFXMMU LUT entry 741 high" hexmask.long.tbyte 0x72C 0.--17. 1. "LO,Line offset" line.long 0x730 "GFXMMU_LUT742L,GFXMMU LUT entry 742 low" hexmask.long.byte 0x730 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x730 8.--15. 1. "FVB,First valid block" bitfld.long 0x730 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x734 "GFXMMU_LUT742H,GFXMMU LUT entry 742 high" hexmask.long.tbyte 0x734 0.--17. 1. "LO,Line offset" line.long 0x738 "GFXMMU_LUT743L,GFXMMU LUT entry 743 low" hexmask.long.byte 0x738 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x738 8.--15. 1. "FVB,First valid block" bitfld.long 0x738 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x73C "GFXMMU_LUT743H,GFXMMU LUT entry 743 high" hexmask.long.tbyte 0x73C 0.--17. 1. "LO,Line offset" line.long 0x740 "GFXMMU_LUT744L,GFXMMU LUT entry 744 low" hexmask.long.byte 0x740 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x740 8.--15. 1. "FVB,First valid block" bitfld.long 0x740 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x744 "GFXMMU_LUT744H,GFXMMU LUT entry 744 high" hexmask.long.tbyte 0x744 0.--17. 1. "LO,Line offset" line.long 0x748 "GFXMMU_LUT745L,GFXMMU LUT entry 745 low" hexmask.long.byte 0x748 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x748 8.--15. 1. "FVB,First valid block" bitfld.long 0x748 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x74C "GFXMMU_LUT745H,GFXMMU LUT entry 745 high" hexmask.long.tbyte 0x74C 0.--17. 1. "LO,Line offset" line.long 0x750 "GFXMMU_LUT746L,GFXMMU LUT entry 746 low" hexmask.long.byte 0x750 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x750 8.--15. 1. "FVB,First valid block" bitfld.long 0x750 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x754 "GFXMMU_LUT746H,GFXMMU LUT entry 746 high" hexmask.long.tbyte 0x754 0.--17. 1. "LO,Line offset" line.long 0x758 "GFXMMU_LUT747L,GFXMMU LUT entry 747 low" hexmask.long.byte 0x758 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x758 8.--15. 1. "FVB,First valid block" bitfld.long 0x758 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x75C "GFXMMU_LUT747H,GFXMMU LUT entry 747 high" hexmask.long.tbyte 0x75C 0.--17. 1. "LO,Line offset" line.long 0x760 "GFXMMU_LUT748L,GFXMMU LUT entry 748 low" hexmask.long.byte 0x760 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x760 8.--15. 1. "FVB,First valid block" bitfld.long 0x760 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x764 "GFXMMU_LUT748H,GFXMMU LUT entry 748 high" hexmask.long.tbyte 0x764 0.--17. 1. "LO,Line offset" line.long 0x768 "GFXMMU_LUT749L,GFXMMU LUT entry 749 low" hexmask.long.byte 0x768 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x768 8.--15. 1. "FVB,First valid block" bitfld.long 0x768 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x76C "GFXMMU_LUT749H,GFXMMU LUT entry 749 high" hexmask.long.tbyte 0x76C 0.--17. 1. "LO,Line offset" line.long 0x770 "GFXMMU_LUT750L,GFXMMU LUT entry 750 low" hexmask.long.byte 0x770 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x770 8.--15. 1. "FVB,First valid block" bitfld.long 0x770 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x774 "GFXMMU_LUT750H,GFXMMU LUT entry 750 high" hexmask.long.tbyte 0x774 0.--17. 1. "LO,Line offset" line.long 0x778 "GFXMMU_LUT751L,GFXMMU LUT entry 751 low" hexmask.long.byte 0x778 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x778 8.--15. 1. "FVB,First valid block" bitfld.long 0x778 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x77C "GFXMMU_LUT751H,GFXMMU LUT entry 751 high" hexmask.long.tbyte 0x77C 0.--17. 1. "LO,Line offset" line.long 0x780 "GFXMMU_LUT752L,GFXMMU LUT entry 752 low" hexmask.long.byte 0x780 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x780 8.--15. 1. "FVB,First valid block" bitfld.long 0x780 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x784 "GFXMMU_LUT752H,GFXMMU LUT entry 752 high" hexmask.long.tbyte 0x784 0.--17. 1. "LO,Line offset" line.long 0x788 "GFXMMU_LUT753L,GFXMMU LUT entry 753 low" hexmask.long.byte 0x788 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x788 8.--15. 1. "FVB,First valid block" bitfld.long 0x788 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x78C "GFXMMU_LUT753H,GFXMMU LUT entry 753 high" hexmask.long.tbyte 0x78C 0.--17. 1. "LO,Line offset" line.long 0x790 "GFXMMU_LUT754L,GFXMMU LUT entry 754 low" hexmask.long.byte 0x790 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x790 8.--15. 1. "FVB,First valid block" bitfld.long 0x790 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x794 "GFXMMU_LUT754H,GFXMMU LUT entry 754 high" hexmask.long.tbyte 0x794 0.--17. 1. "LO,Line offset" line.long 0x798 "GFXMMU_LUT755L,GFXMMU LUT entry 755 low" hexmask.long.byte 0x798 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x798 8.--15. 1. "FVB,First valid block" bitfld.long 0x798 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x79C "GFXMMU_LUT755H,GFXMMU LUT entry 755 high" hexmask.long.tbyte 0x79C 0.--17. 1. "LO,Line offset" line.long 0x7A0 "GFXMMU_LUT756L,GFXMMU LUT entry 756 low" hexmask.long.byte 0x7A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7A4 "GFXMMU_LUT756H,GFXMMU LUT entry 756 high" hexmask.long.tbyte 0x7A4 0.--17. 1. "LO,Line offset" line.long 0x7A8 "GFXMMU_LUT757L,GFXMMU LUT entry 757 low" hexmask.long.byte 0x7A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7AC "GFXMMU_LUT757H,GFXMMU LUT entry 757 high" hexmask.long.tbyte 0x7AC 0.--17. 1. "LO,Line offset" line.long 0x7B0 "GFXMMU_LUT758L,GFXMMU LUT entry 758 low" hexmask.long.byte 0x7B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7B4 "GFXMMU_LUT758H,GFXMMU LUT entry 758 high" hexmask.long.tbyte 0x7B4 0.--17. 1. "LO,Line offset" line.long 0x7B8 "GFXMMU_LUT759L,GFXMMU LUT entry 759 low" hexmask.long.byte 0x7B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7BC "GFXMMU_LUT759H,GFXMMU LUT entry 759 high" hexmask.long.tbyte 0x7BC 0.--17. 1. "LO,Line offset" line.long 0x7C0 "GFXMMU_LUT760L,GFXMMU LUT entry 760 low" hexmask.long.byte 0x7C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7C4 "GFXMMU_LUT760H,GFXMMU LUT entry 760 high" hexmask.long.tbyte 0x7C4 0.--17. 1. "LO,Line offset" line.long 0x7C8 "GFXMMU_LUT761L,GFXMMU LUT entry 761 low" hexmask.long.byte 0x7C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7CC "GFXMMU_LUT761H,GFXMMU LUT entry 761 high" hexmask.long.tbyte 0x7CC 0.--17. 1. "LO,Line offset" line.long 0x7D0 "GFXMMU_LUT762L,GFXMMU LUT entry 762 low" hexmask.long.byte 0x7D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7D4 "GFXMMU_LUT762H,GFXMMU LUT entry 762 high" hexmask.long.tbyte 0x7D4 0.--17. 1. "LO,Line offset" line.long 0x7D8 "GFXMMU_LUT763L,GFXMMU LUT entry 763 low" hexmask.long.byte 0x7D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7DC "GFXMMU_LUT763H,GFXMMU LUT entry 763 high" hexmask.long.tbyte 0x7DC 0.--17. 1. "LO,Line offset" line.long 0x7E0 "GFXMMU_LUT764L,GFXMMU LUT entry 764 low" hexmask.long.byte 0x7E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7E4 "GFXMMU_LUT764H,GFXMMU LUT entry 764 high" hexmask.long.tbyte 0x7E4 0.--17. 1. "LO,Line offset" line.long 0x7E8 "GFXMMU_LUT765L,GFXMMU LUT entry 765 low" hexmask.long.byte 0x7E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7EC "GFXMMU_LUT765H,GFXMMU LUT entry 765 high" hexmask.long.tbyte 0x7EC 0.--17. 1. "LO,Line offset" line.long 0x7F0 "GFXMMU_LUT766L,GFXMMU LUT entry 766 low" hexmask.long.byte 0x7F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x7F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7F4 "GFXMMU_LUT766H,GFXMMU LUT entry 766 high" hexmask.long.tbyte 0x7F4 0.--17. 1. "LO,Line offset" line.long 0x7F8 "GFXMMU_LUT767L,GFXMMU LUT entry 767 low" hexmask.long.byte 0x7F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x7F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x7F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x7FC "GFXMMU_LUT767H,GFXMMU LUT entry 767 high" hexmask.long.tbyte 0x7FC 0.--17. 1. "LO,Line offset" line.long 0x800 "GFXMMU_LUT768L,GFXMMU LUT entry 768 low" hexmask.long.byte 0x800 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x800 8.--15. 1. "FVB,First valid block" bitfld.long 0x800 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x804 "GFXMMU_LUT768H,GFXMMU LUT entry 768 high" hexmask.long.tbyte 0x804 0.--17. 1. "LO,Line offset" line.long 0x808 "GFXMMU_LUT769L,GFXMMU LUT entry 769 low" hexmask.long.byte 0x808 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x808 8.--15. 1. "FVB,First valid block" bitfld.long 0x808 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x80C "GFXMMU_LUT769H,GFXMMU LUT entry 769 high" hexmask.long.tbyte 0x80C 0.--17. 1. "LO,Line offset" line.long 0x810 "GFXMMU_LUT770L,GFXMMU LUT entry 770 low" hexmask.long.byte 0x810 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x810 8.--15. 1. "FVB,First valid block" bitfld.long 0x810 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x814 "GFXMMU_LUT770H,GFXMMU LUT entry 770 high" hexmask.long.tbyte 0x814 0.--17. 1. "LO,Line offset" line.long 0x818 "GFXMMU_LUT771L,GFXMMU LUT entry 771 low" hexmask.long.byte 0x818 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x818 8.--15. 1. "FVB,First valid block" bitfld.long 0x818 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x81C "GFXMMU_LUT771H,GFXMMU LUT entry 771 high" hexmask.long.tbyte 0x81C 0.--17. 1. "LO,Line offset" line.long 0x820 "GFXMMU_LUT772L,GFXMMU LUT entry 772 low" hexmask.long.byte 0x820 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x820 8.--15. 1. "FVB,First valid block" bitfld.long 0x820 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x824 "GFXMMU_LUT772H,GFXMMU LUT entry 772 high" hexmask.long.tbyte 0x824 0.--17. 1. "LO,Line offset" line.long 0x828 "GFXMMU_LUT773L,GFXMMU LUT entry 773 low" hexmask.long.byte 0x828 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x828 8.--15. 1. "FVB,First valid block" bitfld.long 0x828 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x82C "GFXMMU_LUT773H,GFXMMU LUT entry 773 high" hexmask.long.tbyte 0x82C 0.--17. 1. "LO,Line offset" line.long 0x830 "GFXMMU_LUT774L,GFXMMU LUT entry 774 low" hexmask.long.byte 0x830 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x830 8.--15. 1. "FVB,First valid block" bitfld.long 0x830 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x834 "GFXMMU_LUT774H,GFXMMU LUT entry 774 high" hexmask.long.tbyte 0x834 0.--17. 1. "LO,Line offset" line.long 0x838 "GFXMMU_LUT775L,GFXMMU LUT entry 775 low" hexmask.long.byte 0x838 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x838 8.--15. 1. "FVB,First valid block" bitfld.long 0x838 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x83C "GFXMMU_LUT775H,GFXMMU LUT entry 775 high" hexmask.long.tbyte 0x83C 0.--17. 1. "LO,Line offset" line.long 0x840 "GFXMMU_LUT776L,GFXMMU LUT entry 776 low" hexmask.long.byte 0x840 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x840 8.--15. 1. "FVB,First valid block" bitfld.long 0x840 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x844 "GFXMMU_LUT776H,GFXMMU LUT entry 776 high" hexmask.long.tbyte 0x844 0.--17. 1. "LO,Line offset" line.long 0x848 "GFXMMU_LUT777L,GFXMMU LUT entry 777 low" hexmask.long.byte 0x848 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x848 8.--15. 1. "FVB,First valid block" bitfld.long 0x848 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x84C "GFXMMU_LUT777H,GFXMMU LUT entry 777 high" hexmask.long.tbyte 0x84C 0.--17. 1. "LO,Line offset" line.long 0x850 "GFXMMU_LUT778L,GFXMMU LUT entry 778 low" hexmask.long.byte 0x850 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x850 8.--15. 1. "FVB,First valid block" bitfld.long 0x850 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x854 "GFXMMU_LUT778H,GFXMMU LUT entry 778 high" hexmask.long.tbyte 0x854 0.--17. 1. "LO,Line offset" line.long 0x858 "GFXMMU_LUT779L,GFXMMU LUT entry 779 low" hexmask.long.byte 0x858 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x858 8.--15. 1. "FVB,First valid block" bitfld.long 0x858 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x85C "GFXMMU_LUT779H,GFXMMU LUT entry 779 high" hexmask.long.tbyte 0x85C 0.--17. 1. "LO,Line offset" line.long 0x860 "GFXMMU_LUT780L,GFXMMU LUT entry 780 low" hexmask.long.byte 0x860 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x860 8.--15. 1. "FVB,First valid block" bitfld.long 0x860 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x864 "GFXMMU_LUT780H,GFXMMU LUT entry 780 high" hexmask.long.tbyte 0x864 0.--17. 1. "LO,Line offset" line.long 0x868 "GFXMMU_LUT781L,GFXMMU LUT entry 781 low" hexmask.long.byte 0x868 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x868 8.--15. 1. "FVB,First valid block" bitfld.long 0x868 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x86C "GFXMMU_LUT781H,GFXMMU LUT entry 781 high" hexmask.long.tbyte 0x86C 0.--17. 1. "LO,Line offset" line.long 0x870 "GFXMMU_LUT782L,GFXMMU LUT entry 782 low" hexmask.long.byte 0x870 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x870 8.--15. 1. "FVB,First valid block" bitfld.long 0x870 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x874 "GFXMMU_LUT782H,GFXMMU LUT entry 782 high" hexmask.long.tbyte 0x874 0.--17. 1. "LO,Line offset" line.long 0x878 "GFXMMU_LUT783L,GFXMMU LUT entry 783 low" hexmask.long.byte 0x878 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x878 8.--15. 1. "FVB,First valid block" bitfld.long 0x878 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x87C "GFXMMU_LUT783H,GFXMMU LUT entry 783 high" hexmask.long.tbyte 0x87C 0.--17. 1. "LO,Line offset" line.long 0x880 "GFXMMU_LUT784L,GFXMMU LUT entry 784 low" hexmask.long.byte 0x880 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x880 8.--15. 1. "FVB,First valid block" bitfld.long 0x880 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x884 "GFXMMU_LUT784H,GFXMMU LUT entry 784 high" hexmask.long.tbyte 0x884 0.--17. 1. "LO,Line offset" line.long 0x888 "GFXMMU_LUT785L,GFXMMU LUT entry 785 low" hexmask.long.byte 0x888 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x888 8.--15. 1. "FVB,First valid block" bitfld.long 0x888 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x88C "GFXMMU_LUT785H,GFXMMU LUT entry 785 high" hexmask.long.tbyte 0x88C 0.--17. 1. "LO,Line offset" line.long 0x890 "GFXMMU_LUT786L,GFXMMU LUT entry 786 low" hexmask.long.byte 0x890 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x890 8.--15. 1. "FVB,First valid block" bitfld.long 0x890 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x894 "GFXMMU_LUT786H,GFXMMU LUT entry 786 high" hexmask.long.tbyte 0x894 0.--17. 1. "LO,Line offset" line.long 0x898 "GFXMMU_LUT787L,GFXMMU LUT entry 787 low" hexmask.long.byte 0x898 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x898 8.--15. 1. "FVB,First valid block" bitfld.long 0x898 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x89C "GFXMMU_LUT787H,GFXMMU LUT entry 787 high" hexmask.long.tbyte 0x89C 0.--17. 1. "LO,Line offset" line.long 0x8A0 "GFXMMU_LUT788L,GFXMMU LUT entry 788 low" hexmask.long.byte 0x8A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8A4 "GFXMMU_LUT788H,GFXMMU LUT entry 788 high" hexmask.long.tbyte 0x8A4 0.--17. 1. "LO,Line offset" line.long 0x8A8 "GFXMMU_LUT789L,GFXMMU LUT entry 789 low" hexmask.long.byte 0x8A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8AC "GFXMMU_LUT789H,GFXMMU LUT entry 789 high" hexmask.long.tbyte 0x8AC 0.--17. 1. "LO,Line offset" line.long 0x8B0 "GFXMMU_LUT790L,GFXMMU LUT entry 790 low" hexmask.long.byte 0x8B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8B4 "GFXMMU_LUT790H,GFXMMU LUT entry 790 high" hexmask.long.tbyte 0x8B4 0.--17. 1. "LO,Line offset" line.long 0x8B8 "GFXMMU_LUT791L,GFXMMU LUT entry 791 low" hexmask.long.byte 0x8B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8BC "GFXMMU_LUT791H,GFXMMU LUT entry 791 high" hexmask.long.tbyte 0x8BC 0.--17. 1. "LO,Line offset" line.long 0x8C0 "GFXMMU_LUT792L,GFXMMU LUT entry 792 low" hexmask.long.byte 0x8C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8C4 "GFXMMU_LUT792H,GFXMMU LUT entry 792 high" hexmask.long.tbyte 0x8C4 0.--17. 1. "LO,Line offset" line.long 0x8C8 "GFXMMU_LUT793L,GFXMMU LUT entry 793 low" hexmask.long.byte 0x8C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8CC "GFXMMU_LUT793H,GFXMMU LUT entry 793 high" hexmask.long.tbyte 0x8CC 0.--17. 1. "LO,Line offset" line.long 0x8D0 "GFXMMU_LUT794L,GFXMMU LUT entry 794 low" hexmask.long.byte 0x8D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8D4 "GFXMMU_LUT794H,GFXMMU LUT entry 794 high" hexmask.long.tbyte 0x8D4 0.--17. 1. "LO,Line offset" line.long 0x8D8 "GFXMMU_LUT795L,GFXMMU LUT entry 795 low" hexmask.long.byte 0x8D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8DC "GFXMMU_LUT795H,GFXMMU LUT entry 795 high" hexmask.long.tbyte 0x8DC 0.--17. 1. "LO,Line offset" line.long 0x8E0 "GFXMMU_LUT796L,GFXMMU LUT entry 796 low" hexmask.long.byte 0x8E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8E4 "GFXMMU_LUT796H,GFXMMU LUT entry 796 high" hexmask.long.tbyte 0x8E4 0.--17. 1. "LO,Line offset" line.long 0x8E8 "GFXMMU_LUT797L,GFXMMU LUT entry 797 low" hexmask.long.byte 0x8E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8EC "GFXMMU_LUT797H,GFXMMU LUT entry 797 high" hexmask.long.tbyte 0x8EC 0.--17. 1. "LO,Line offset" line.long 0x8F0 "GFXMMU_LUT798L,GFXMMU LUT entry 798 low" hexmask.long.byte 0x8F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x8F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8F4 "GFXMMU_LUT798H,GFXMMU LUT entry 798 high" hexmask.long.tbyte 0x8F4 0.--17. 1. "LO,Line offset" line.long 0x8F8 "GFXMMU_LUT799L,GFXMMU LUT entry 799 low" hexmask.long.byte 0x8F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x8F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x8F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x8FC "GFXMMU_LUT799H,GFXMMU LUT entry 799 high" hexmask.long.tbyte 0x8FC 0.--17. 1. "LO,Line offset" line.long 0x900 "GFXMMU_LUT800L,GFXMMU LUT entry 800 low" hexmask.long.byte 0x900 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x900 8.--15. 1. "FVB,First valid block" bitfld.long 0x900 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x904 "GFXMMU_LUT800H,GFXMMU LUT entry 800 high" hexmask.long.tbyte 0x904 0.--17. 1. "LO,Line offset" line.long 0x908 "GFXMMU_LUT801L,GFXMMU LUT entry 801 low" hexmask.long.byte 0x908 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x908 8.--15. 1. "FVB,First valid block" bitfld.long 0x908 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x90C "GFXMMU_LUT801H,GFXMMU LUT entry 801 high" hexmask.long.tbyte 0x90C 0.--17. 1. "LO,Line offset" line.long 0x910 "GFXMMU_LUT802L,GFXMMU LUT entry 802 low" hexmask.long.byte 0x910 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x910 8.--15. 1. "FVB,First valid block" bitfld.long 0x910 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x914 "GFXMMU_LUT802H,GFXMMU LUT entry 802 high" hexmask.long.tbyte 0x914 0.--17. 1. "LO,Line offset" line.long 0x918 "GFXMMU_LUT803L,GFXMMU LUT entry 803 low" hexmask.long.byte 0x918 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x918 8.--15. 1. "FVB,First valid block" bitfld.long 0x918 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x91C "GFXMMU_LUT803H,GFXMMU LUT entry 803 high" hexmask.long.tbyte 0x91C 0.--17. 1. "LO,Line offset" line.long 0x920 "GFXMMU_LUT804L,GFXMMU LUT entry 804 low" hexmask.long.byte 0x920 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x920 8.--15. 1. "FVB,First valid block" bitfld.long 0x920 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x924 "GFXMMU_LUT804H,GFXMMU LUT entry 804 high" hexmask.long.tbyte 0x924 0.--17. 1. "LO,Line offset" line.long 0x928 "GFXMMU_LUT805L,GFXMMU LUT entry 805 low" hexmask.long.byte 0x928 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x928 8.--15. 1. "FVB,First valid block" bitfld.long 0x928 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x92C "GFXMMU_LUT805H,GFXMMU LUT entry 805 high" hexmask.long.tbyte 0x92C 0.--17. 1. "LO,Line offset" line.long 0x930 "GFXMMU_LUT806L,GFXMMU LUT entry 806 low" hexmask.long.byte 0x930 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x930 8.--15. 1. "FVB,First valid block" bitfld.long 0x930 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x934 "GFXMMU_LUT806H,GFXMMU LUT entry 806 high" hexmask.long.tbyte 0x934 0.--17. 1. "LO,Line offset" line.long 0x938 "GFXMMU_LUT807L,GFXMMU LUT entry 807 low" hexmask.long.byte 0x938 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x938 8.--15. 1. "FVB,First valid block" bitfld.long 0x938 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x93C "GFXMMU_LUT807H,GFXMMU LUT entry 807 high" hexmask.long.tbyte 0x93C 0.--17. 1. "LO,Line offset" line.long 0x940 "GFXMMU_LUT808L,GFXMMU LUT entry 808 low" hexmask.long.byte 0x940 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x940 8.--15. 1. "FVB,First valid block" bitfld.long 0x940 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x944 "GFXMMU_LUT808H,GFXMMU LUT entry 808 high" hexmask.long.tbyte 0x944 0.--17. 1. "LO,Line offset" line.long 0x948 "GFXMMU_LUT809L,GFXMMU LUT entry 809 low" hexmask.long.byte 0x948 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x948 8.--15. 1. "FVB,First valid block" bitfld.long 0x948 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x94C "GFXMMU_LUT809H,GFXMMU LUT entry 809 high" hexmask.long.tbyte 0x94C 0.--17. 1. "LO,Line offset" line.long 0x950 "GFXMMU_LUT810L,GFXMMU LUT entry 810 low" hexmask.long.byte 0x950 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x950 8.--15. 1. "FVB,First valid block" bitfld.long 0x950 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x954 "GFXMMU_LUT810H,GFXMMU LUT entry 810 high" hexmask.long.tbyte 0x954 0.--17. 1. "LO,Line offset" line.long 0x958 "GFXMMU_LUT811L,GFXMMU LUT entry 811 low" hexmask.long.byte 0x958 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x958 8.--15. 1. "FVB,First valid block" bitfld.long 0x958 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x95C "GFXMMU_LUT811H,GFXMMU LUT entry 811 high" hexmask.long.tbyte 0x95C 0.--17. 1. "LO,Line offset" line.long 0x960 "GFXMMU_LUT812L,GFXMMU LUT entry 812 low" hexmask.long.byte 0x960 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x960 8.--15. 1. "FVB,First valid block" bitfld.long 0x960 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x964 "GFXMMU_LUT812H,GFXMMU LUT entry 812 high" hexmask.long.tbyte 0x964 0.--17. 1. "LO,Line offset" line.long 0x968 "GFXMMU_LUT813L,GFXMMU LUT entry 813 low" hexmask.long.byte 0x968 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x968 8.--15. 1. "FVB,First valid block" bitfld.long 0x968 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x96C "GFXMMU_LUT813H,GFXMMU LUT entry 813 high" hexmask.long.tbyte 0x96C 0.--17. 1. "LO,Line offset" line.long 0x970 "GFXMMU_LUT814L,GFXMMU LUT entry 814 low" hexmask.long.byte 0x970 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x970 8.--15. 1. "FVB,First valid block" bitfld.long 0x970 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x974 "GFXMMU_LUT814H,GFXMMU LUT entry 814 high" hexmask.long.tbyte 0x974 0.--17. 1. "LO,Line offset" line.long 0x978 "GFXMMU_LUT815L,GFXMMU LUT entry 815 low" hexmask.long.byte 0x978 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x978 8.--15. 1. "FVB,First valid block" bitfld.long 0x978 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x97C "GFXMMU_LUT815H,GFXMMU LUT entry 815 high" hexmask.long.tbyte 0x97C 0.--17. 1. "LO,Line offset" line.long 0x980 "GFXMMU_LUT816L,GFXMMU LUT entry 816 low" hexmask.long.byte 0x980 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x980 8.--15. 1. "FVB,First valid block" bitfld.long 0x980 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x984 "GFXMMU_LUT816H,GFXMMU LUT entry 816 high" hexmask.long.tbyte 0x984 0.--17. 1. "LO,Line offset" line.long 0x988 "GFXMMU_LUT817L,GFXMMU LUT entry 817 low" hexmask.long.byte 0x988 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x988 8.--15. 1. "FVB,First valid block" bitfld.long 0x988 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x98C "GFXMMU_LUT817H,GFXMMU LUT entry 817 high" hexmask.long.tbyte 0x98C 0.--17. 1. "LO,Line offset" line.long 0x990 "GFXMMU_LUT818L,GFXMMU LUT entry 818 low" hexmask.long.byte 0x990 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x990 8.--15. 1. "FVB,First valid block" bitfld.long 0x990 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x994 "GFXMMU_LUT818H,GFXMMU LUT entry 818 high" hexmask.long.tbyte 0x994 0.--17. 1. "LO,Line offset" line.long 0x998 "GFXMMU_LUT819L,GFXMMU LUT entry 819 low" hexmask.long.byte 0x998 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x998 8.--15. 1. "FVB,First valid block" bitfld.long 0x998 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x99C "GFXMMU_LUT819H,GFXMMU LUT entry 819 high" hexmask.long.tbyte 0x99C 0.--17. 1. "LO,Line offset" line.long 0x9A0 "GFXMMU_LUT820L,GFXMMU LUT entry 820 low" hexmask.long.byte 0x9A0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9A0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9A4 "GFXMMU_LUT820H,GFXMMU LUT entry 820 high" hexmask.long.tbyte 0x9A4 0.--17. 1. "LO,Line offset" line.long 0x9A8 "GFXMMU_LUT821L,GFXMMU LUT entry 821 low" hexmask.long.byte 0x9A8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9A8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9AC "GFXMMU_LUT821H,GFXMMU LUT entry 821 high" hexmask.long.tbyte 0x9AC 0.--17. 1. "LO,Line offset" line.long 0x9B0 "GFXMMU_LUT822L,GFXMMU LUT entry 822 low" hexmask.long.byte 0x9B0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9B0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9B4 "GFXMMU_LUT822H,GFXMMU LUT entry 822 high" hexmask.long.tbyte 0x9B4 0.--17. 1. "LO,Line offset" line.long 0x9B8 "GFXMMU_LUT823L,GFXMMU LUT entry 823 low" hexmask.long.byte 0x9B8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9B8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9BC "GFXMMU_LUT823H,GFXMMU LUT entry 823 high" hexmask.long.tbyte 0x9BC 0.--17. 1. "LO,Line offset" line.long 0x9C0 "GFXMMU_LUT824L,GFXMMU LUT entry 824 low" hexmask.long.byte 0x9C0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9C0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9C4 "GFXMMU_LUT824H,GFXMMU LUT entry 824 high" hexmask.long.tbyte 0x9C4 0.--17. 1. "LO,Line offset" line.long 0x9C8 "GFXMMU_LUT825L,GFXMMU LUT entry 825 low" hexmask.long.byte 0x9C8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9C8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9CC "GFXMMU_LUT825H,GFXMMU LUT entry 825 high" hexmask.long.tbyte 0x9CC 0.--17. 1. "LO,Line offset" line.long 0x9D0 "GFXMMU_LUT826L,GFXMMU LUT entry 826 low" hexmask.long.byte 0x9D0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9D0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9D4 "GFXMMU_LUT826H,GFXMMU LUT entry 826 high" hexmask.long.tbyte 0x9D4 0.--17. 1. "LO,Line offset" line.long 0x9D8 "GFXMMU_LUT827L,GFXMMU LUT entry 827 low" hexmask.long.byte 0x9D8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9D8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9DC "GFXMMU_LUT827H,GFXMMU LUT entry 827 high" hexmask.long.tbyte 0x9DC 0.--17. 1. "LO,Line offset" line.long 0x9E0 "GFXMMU_LUT828L,GFXMMU LUT entry 828 low" hexmask.long.byte 0x9E0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9E0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9E4 "GFXMMU_LUT828H,GFXMMU LUT entry 828 high" hexmask.long.tbyte 0x9E4 0.--17. 1. "LO,Line offset" line.long 0x9E8 "GFXMMU_LUT829L,GFXMMU LUT entry 829 low" hexmask.long.byte 0x9E8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9E8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9EC "GFXMMU_LUT829H,GFXMMU LUT entry 829 high" hexmask.long.tbyte 0x9EC 0.--17. 1. "LO,Line offset" line.long 0x9F0 "GFXMMU_LUT830L,GFXMMU LUT entry 830 low" hexmask.long.byte 0x9F0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9F0 8.--15. 1. "FVB,First valid block" bitfld.long 0x9F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9F4 "GFXMMU_LUT830H,GFXMMU LUT entry 830 high" hexmask.long.tbyte 0x9F4 0.--17. 1. "LO,Line offset" line.long 0x9F8 "GFXMMU_LUT831L,GFXMMU LUT entry 831 low" hexmask.long.byte 0x9F8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0x9F8 8.--15. 1. "FVB,First valid block" bitfld.long 0x9F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0x9FC "GFXMMU_LUT831H,GFXMMU LUT entry 831 high" hexmask.long.tbyte 0x9FC 0.--17. 1. "LO,Line offset" line.long 0xA00 "GFXMMU_LUT832L,GFXMMU LUT entry 832 low" hexmask.long.byte 0xA00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA00 8.--15. 1. "FVB,First valid block" bitfld.long 0xA00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA04 "GFXMMU_LUT832H,GFXMMU LUT entry 832 high" hexmask.long.tbyte 0xA04 0.--17. 1. "LO,Line offset" line.long 0xA08 "GFXMMU_LUT833L,GFXMMU LUT entry 833 low" hexmask.long.byte 0xA08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA08 8.--15. 1. "FVB,First valid block" bitfld.long 0xA08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA0C "GFXMMU_LUT833H,GFXMMU LUT entry 833 high" hexmask.long.tbyte 0xA0C 0.--17. 1. "LO,Line offset" line.long 0xA10 "GFXMMU_LUT834L,GFXMMU LUT entry 834 low" hexmask.long.byte 0xA10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA10 8.--15. 1. "FVB,First valid block" bitfld.long 0xA10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA14 "GFXMMU_LUT834H,GFXMMU LUT entry 834 high" hexmask.long.tbyte 0xA14 0.--17. 1. "LO,Line offset" line.long 0xA18 "GFXMMU_LUT835L,GFXMMU LUT entry 835 low" hexmask.long.byte 0xA18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA18 8.--15. 1. "FVB,First valid block" bitfld.long 0xA18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA1C "GFXMMU_LUT835H,GFXMMU LUT entry 835 high" hexmask.long.tbyte 0xA1C 0.--17. 1. "LO,Line offset" line.long 0xA20 "GFXMMU_LUT836L,GFXMMU LUT entry 836 low" hexmask.long.byte 0xA20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA20 8.--15. 1. "FVB,First valid block" bitfld.long 0xA20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA24 "GFXMMU_LUT836H,GFXMMU LUT entry 836 high" hexmask.long.tbyte 0xA24 0.--17. 1. "LO,Line offset" line.long 0xA28 "GFXMMU_LUT837L,GFXMMU LUT entry 837 low" hexmask.long.byte 0xA28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA28 8.--15. 1. "FVB,First valid block" bitfld.long 0xA28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA2C "GFXMMU_LUT837H,GFXMMU LUT entry 837 high" hexmask.long.tbyte 0xA2C 0.--17. 1. "LO,Line offset" line.long 0xA30 "GFXMMU_LUT838L,GFXMMU LUT entry 838 low" hexmask.long.byte 0xA30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA30 8.--15. 1. "FVB,First valid block" bitfld.long 0xA30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA34 "GFXMMU_LUT838H,GFXMMU LUT entry 838 high" hexmask.long.tbyte 0xA34 0.--17. 1. "LO,Line offset" line.long 0xA38 "GFXMMU_LUT839L,GFXMMU LUT entry 839 low" hexmask.long.byte 0xA38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA38 8.--15. 1. "FVB,First valid block" bitfld.long 0xA38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA3C "GFXMMU_LUT839H,GFXMMU LUT entry 839 high" hexmask.long.tbyte 0xA3C 0.--17. 1. "LO,Line offset" line.long 0xA40 "GFXMMU_LUT840L,GFXMMU LUT entry 840 low" hexmask.long.byte 0xA40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA40 8.--15. 1. "FVB,First valid block" bitfld.long 0xA40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA44 "GFXMMU_LUT840H,GFXMMU LUT entry 840 high" hexmask.long.tbyte 0xA44 0.--17. 1. "LO,Line offset" line.long 0xA48 "GFXMMU_LUT841L,GFXMMU LUT entry 841 low" hexmask.long.byte 0xA48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA48 8.--15. 1. "FVB,First valid block" bitfld.long 0xA48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA4C "GFXMMU_LUT841H,GFXMMU LUT entry 841 high" hexmask.long.tbyte 0xA4C 0.--17. 1. "LO,Line offset" line.long 0xA50 "GFXMMU_LUT842L,GFXMMU LUT entry 842 low" hexmask.long.byte 0xA50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA50 8.--15. 1. "FVB,First valid block" bitfld.long 0xA50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA54 "GFXMMU_LUT842H,GFXMMU LUT entry 842 high" hexmask.long.tbyte 0xA54 0.--17. 1. "LO,Line offset" line.long 0xA58 "GFXMMU_LUT843L,GFXMMU LUT entry 843 low" hexmask.long.byte 0xA58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA58 8.--15. 1. "FVB,First valid block" bitfld.long 0xA58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA5C "GFXMMU_LUT843H,GFXMMU LUT entry 843 high" hexmask.long.tbyte 0xA5C 0.--17. 1. "LO,Line offset" line.long 0xA60 "GFXMMU_LUT844L,GFXMMU LUT entry 844 low" hexmask.long.byte 0xA60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA60 8.--15. 1. "FVB,First valid block" bitfld.long 0xA60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA64 "GFXMMU_LUT844H,GFXMMU LUT entry 844 high" hexmask.long.tbyte 0xA64 0.--17. 1. "LO,Line offset" line.long 0xA68 "GFXMMU_LUT845L,GFXMMU LUT entry 845 low" hexmask.long.byte 0xA68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA68 8.--15. 1. "FVB,First valid block" bitfld.long 0xA68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA6C "GFXMMU_LUT845H,GFXMMU LUT entry 845 high" hexmask.long.tbyte 0xA6C 0.--17. 1. "LO,Line offset" line.long 0xA70 "GFXMMU_LUT846L,GFXMMU LUT entry 846 low" hexmask.long.byte 0xA70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA70 8.--15. 1. "FVB,First valid block" bitfld.long 0xA70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA74 "GFXMMU_LUT846H,GFXMMU LUT entry 846 high" hexmask.long.tbyte 0xA74 0.--17. 1. "LO,Line offset" line.long 0xA78 "GFXMMU_LUT847L,GFXMMU LUT entry 847 low" hexmask.long.byte 0xA78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA78 8.--15. 1. "FVB,First valid block" bitfld.long 0xA78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA7C "GFXMMU_LUT847H,GFXMMU LUT entry 847 high" hexmask.long.tbyte 0xA7C 0.--17. 1. "LO,Line offset" line.long 0xA80 "GFXMMU_LUT848L,GFXMMU LUT entry 848 low" hexmask.long.byte 0xA80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA80 8.--15. 1. "FVB,First valid block" bitfld.long 0xA80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA84 "GFXMMU_LUT848H,GFXMMU LUT entry 848 high" hexmask.long.tbyte 0xA84 0.--17. 1. "LO,Line offset" line.long 0xA88 "GFXMMU_LUT849L,GFXMMU LUT entry 849 low" hexmask.long.byte 0xA88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA88 8.--15. 1. "FVB,First valid block" bitfld.long 0xA88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA8C "GFXMMU_LUT849H,GFXMMU LUT entry 849 high" hexmask.long.tbyte 0xA8C 0.--17. 1. "LO,Line offset" line.long 0xA90 "GFXMMU_LUT850L,GFXMMU LUT entry 850 low" hexmask.long.byte 0xA90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA90 8.--15. 1. "FVB,First valid block" bitfld.long 0xA90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA94 "GFXMMU_LUT850H,GFXMMU LUT entry 850 high" hexmask.long.tbyte 0xA94 0.--17. 1. "LO,Line offset" line.long 0xA98 "GFXMMU_LUT851L,GFXMMU LUT entry 851 low" hexmask.long.byte 0xA98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xA98 8.--15. 1. "FVB,First valid block" bitfld.long 0xA98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xA9C "GFXMMU_LUT851H,GFXMMU LUT entry 851 high" hexmask.long.tbyte 0xA9C 0.--17. 1. "LO,Line offset" line.long 0xAA0 "GFXMMU_LUT852L,GFXMMU LUT entry 852 low" hexmask.long.byte 0xAA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAA4 "GFXMMU_LUT852H,GFXMMU LUT entry 852 high" hexmask.long.tbyte 0xAA4 0.--17. 1. "LO,Line offset" line.long 0xAA8 "GFXMMU_LUT853L,GFXMMU LUT entry 853 low" hexmask.long.byte 0xAA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAAC "GFXMMU_LUT853H,GFXMMU LUT entry 853 high" hexmask.long.tbyte 0xAAC 0.--17. 1. "LO,Line offset" line.long 0xAB0 "GFXMMU_LUT854L,GFXMMU LUT entry 854 low" hexmask.long.byte 0xAB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAB4 "GFXMMU_LUT854H,GFXMMU LUT entry 854 high" hexmask.long.tbyte 0xAB4 0.--17. 1. "LO,Line offset" line.long 0xAB8 "GFXMMU_LUT855L,GFXMMU LUT entry 855 low" hexmask.long.byte 0xAB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xABC "GFXMMU_LUT855H,GFXMMU LUT entry 855 high" hexmask.long.tbyte 0xABC 0.--17. 1. "LO,Line offset" line.long 0xAC0 "GFXMMU_LUT856L,GFXMMU LUT entry 856 low" hexmask.long.byte 0xAC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAC4 "GFXMMU_LUT856H,GFXMMU LUT entry 856 high" hexmask.long.tbyte 0xAC4 0.--17. 1. "LO,Line offset" line.long 0xAC8 "GFXMMU_LUT857L,GFXMMU LUT entry 857 low" hexmask.long.byte 0xAC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xACC "GFXMMU_LUT857H,GFXMMU LUT entry 857 high" hexmask.long.tbyte 0xACC 0.--17. 1. "LO,Line offset" line.long 0xAD0 "GFXMMU_LUT858L,GFXMMU LUT entry 858 low" hexmask.long.byte 0xAD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAD4 "GFXMMU_LUT858H,GFXMMU LUT entry 858 high" hexmask.long.tbyte 0xAD4 0.--17. 1. "LO,Line offset" line.long 0xAD8 "GFXMMU_LUT859L,GFXMMU LUT entry 859 low" hexmask.long.byte 0xAD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xADC "GFXMMU_LUT859H,GFXMMU LUT entry 859 high" hexmask.long.tbyte 0xADC 0.--17. 1. "LO,Line offset" line.long 0xAE0 "GFXMMU_LUT860L,GFXMMU LUT entry 860 low" hexmask.long.byte 0xAE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAE4 "GFXMMU_LUT860H,GFXMMU LUT entry 860 high" hexmask.long.tbyte 0xAE4 0.--17. 1. "LO,Line offset" line.long 0xAE8 "GFXMMU_LUT861L,GFXMMU LUT entry 861 low" hexmask.long.byte 0xAE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAEC "GFXMMU_LUT861H,GFXMMU LUT entry 861 high" hexmask.long.tbyte 0xAEC 0.--17. 1. "LO,Line offset" line.long 0xAF0 "GFXMMU_LUT862L,GFXMMU LUT entry 862 low" hexmask.long.byte 0xAF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xAF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAF4 "GFXMMU_LUT862H,GFXMMU LUT entry 862 high" hexmask.long.tbyte 0xAF4 0.--17. 1. "LO,Line offset" line.long 0xAF8 "GFXMMU_LUT863L,GFXMMU LUT entry 863 low" hexmask.long.byte 0xAF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xAF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xAF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xAFC "GFXMMU_LUT863H,GFXMMU LUT entry 863 high" hexmask.long.tbyte 0xAFC 0.--17. 1. "LO,Line offset" line.long 0xB00 "GFXMMU_LUT864L,GFXMMU LUT entry 864 low" hexmask.long.byte 0xB00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB00 8.--15. 1. "FVB,First valid block" bitfld.long 0xB00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB04 "GFXMMU_LUT864H,GFXMMU LUT entry 864 high" hexmask.long.tbyte 0xB04 0.--17. 1. "LO,Line offset" line.long 0xB08 "GFXMMU_LUT865L,GFXMMU LUT entry 865 low" hexmask.long.byte 0xB08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB08 8.--15. 1. "FVB,First valid block" bitfld.long 0xB08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB0C "GFXMMU_LUT865H,GFXMMU LUT entry 865 high" hexmask.long.tbyte 0xB0C 0.--17. 1. "LO,Line offset" line.long 0xB10 "GFXMMU_LUT866L,GFXMMU LUT entry 866 low" hexmask.long.byte 0xB10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB10 8.--15. 1. "FVB,First valid block" bitfld.long 0xB10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB14 "GFXMMU_LUT866H,GFXMMU LUT entry 866 high" hexmask.long.tbyte 0xB14 0.--17. 1. "LO,Line offset" line.long 0xB18 "GFXMMU_LUT867L,GFXMMU LUT entry 867 low" hexmask.long.byte 0xB18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB18 8.--15. 1. "FVB,First valid block" bitfld.long 0xB18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB1C "GFXMMU_LUT867H,GFXMMU LUT entry 867 high" hexmask.long.tbyte 0xB1C 0.--17. 1. "LO,Line offset" line.long 0xB20 "GFXMMU_LUT868L,GFXMMU LUT entry 868 low" hexmask.long.byte 0xB20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB20 8.--15. 1. "FVB,First valid block" bitfld.long 0xB20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB24 "GFXMMU_LUT868H,GFXMMU LUT entry 868 high" hexmask.long.tbyte 0xB24 0.--17. 1. "LO,Line offset" line.long 0xB28 "GFXMMU_LUT869L,GFXMMU LUT entry 869 low" hexmask.long.byte 0xB28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB28 8.--15. 1. "FVB,First valid block" bitfld.long 0xB28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB2C "GFXMMU_LUT869H,GFXMMU LUT entry 869 high" hexmask.long.tbyte 0xB2C 0.--17. 1. "LO,Line offset" line.long 0xB30 "GFXMMU_LUT870L,GFXMMU LUT entry 870 low" hexmask.long.byte 0xB30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB30 8.--15. 1. "FVB,First valid block" bitfld.long 0xB30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB34 "GFXMMU_LUT870H,GFXMMU LUT entry 870 high" hexmask.long.tbyte 0xB34 0.--17. 1. "LO,Line offset" line.long 0xB38 "GFXMMU_LUT871L,GFXMMU LUT entry 871 low" hexmask.long.byte 0xB38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB38 8.--15. 1. "FVB,First valid block" bitfld.long 0xB38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB3C "GFXMMU_LUT871H,GFXMMU LUT entry 871 high" hexmask.long.tbyte 0xB3C 0.--17. 1. "LO,Line offset" line.long 0xB40 "GFXMMU_LUT872L,GFXMMU LUT entry 872 low" hexmask.long.byte 0xB40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB40 8.--15. 1. "FVB,First valid block" bitfld.long 0xB40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB44 "GFXMMU_LUT872H,GFXMMU LUT entry 872 high" hexmask.long.tbyte 0xB44 0.--17. 1. "LO,Line offset" line.long 0xB48 "GFXMMU_LUT873L,GFXMMU LUT entry 873 low" hexmask.long.byte 0xB48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB48 8.--15. 1. "FVB,First valid block" bitfld.long 0xB48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB4C "GFXMMU_LUT873H,GFXMMU LUT entry 873 high" hexmask.long.tbyte 0xB4C 0.--17. 1. "LO,Line offset" line.long 0xB50 "GFXMMU_LUT874L,GFXMMU LUT entry 874 low" hexmask.long.byte 0xB50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB50 8.--15. 1. "FVB,First valid block" bitfld.long 0xB50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB54 "GFXMMU_LUT874H,GFXMMU LUT entry 874 high" hexmask.long.tbyte 0xB54 0.--17. 1. "LO,Line offset" line.long 0xB58 "GFXMMU_LUT875L,GFXMMU LUT entry 875 low" hexmask.long.byte 0xB58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB58 8.--15. 1. "FVB,First valid block" bitfld.long 0xB58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB5C "GFXMMU_LUT875H,GFXMMU LUT entry 875 high" hexmask.long.tbyte 0xB5C 0.--17. 1. "LO,Line offset" line.long 0xB60 "GFXMMU_LUT876L,GFXMMU LUT entry 876 low" hexmask.long.byte 0xB60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB60 8.--15. 1. "FVB,First valid block" bitfld.long 0xB60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB64 "GFXMMU_LUT876H,GFXMMU LUT entry 876 high" hexmask.long.tbyte 0xB64 0.--17. 1. "LO,Line offset" line.long 0xB68 "GFXMMU_LUT877L,GFXMMU LUT entry 877 low" hexmask.long.byte 0xB68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB68 8.--15. 1. "FVB,First valid block" bitfld.long 0xB68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB6C "GFXMMU_LUT877H,GFXMMU LUT entry 877 high" hexmask.long.tbyte 0xB6C 0.--17. 1. "LO,Line offset" line.long 0xB70 "GFXMMU_LUT878L,GFXMMU LUT entry 878 low" hexmask.long.byte 0xB70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB70 8.--15. 1. "FVB,First valid block" bitfld.long 0xB70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB74 "GFXMMU_LUT878H,GFXMMU LUT entry 878 high" hexmask.long.tbyte 0xB74 0.--17. 1. "LO,Line offset" line.long 0xB78 "GFXMMU_LUT879L,GFXMMU LUT entry 879 low" hexmask.long.byte 0xB78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB78 8.--15. 1. "FVB,First valid block" bitfld.long 0xB78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB7C "GFXMMU_LUT879H,GFXMMU LUT entry 879 high" hexmask.long.tbyte 0xB7C 0.--17. 1. "LO,Line offset" line.long 0xB80 "GFXMMU_LUT880L,GFXMMU LUT entry 880 low" hexmask.long.byte 0xB80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB80 8.--15. 1. "FVB,First valid block" bitfld.long 0xB80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB84 "GFXMMU_LUT880H,GFXMMU LUT entry 880 high" hexmask.long.tbyte 0xB84 0.--17. 1. "LO,Line offset" line.long 0xB88 "GFXMMU_LUT881L,GFXMMU LUT entry 881 low" hexmask.long.byte 0xB88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB88 8.--15. 1. "FVB,First valid block" bitfld.long 0xB88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB8C "GFXMMU_LUT881H,GFXMMU LUT entry 881 high" hexmask.long.tbyte 0xB8C 0.--17. 1. "LO,Line offset" line.long 0xB90 "GFXMMU_LUT882L,GFXMMU LUT entry 882 low" hexmask.long.byte 0xB90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB90 8.--15. 1. "FVB,First valid block" bitfld.long 0xB90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB94 "GFXMMU_LUT882H,GFXMMU LUT entry 882 high" hexmask.long.tbyte 0xB94 0.--17. 1. "LO,Line offset" line.long 0xB98 "GFXMMU_LUT883L,GFXMMU LUT entry 883 low" hexmask.long.byte 0xB98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xB98 8.--15. 1. "FVB,First valid block" bitfld.long 0xB98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xB9C "GFXMMU_LUT883H,GFXMMU LUT entry 883 high" hexmask.long.tbyte 0xB9C 0.--17. 1. "LO,Line offset" line.long 0xBA0 "GFXMMU_LUT884L,GFXMMU LUT entry 884 low" hexmask.long.byte 0xBA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBA4 "GFXMMU_LUT884H,GFXMMU LUT entry 884 high" hexmask.long.tbyte 0xBA4 0.--17. 1. "LO,Line offset" line.long 0xBA8 "GFXMMU_LUT885L,GFXMMU LUT entry 885 low" hexmask.long.byte 0xBA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBAC "GFXMMU_LUT885H,GFXMMU LUT entry 885 high" hexmask.long.tbyte 0xBAC 0.--17. 1. "LO,Line offset" line.long 0xBB0 "GFXMMU_LUT886L,GFXMMU LUT entry 886 low" hexmask.long.byte 0xBB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBB4 "GFXMMU_LUT886H,GFXMMU LUT entry 886 high" hexmask.long.tbyte 0xBB4 0.--17. 1. "LO,Line offset" line.long 0xBB8 "GFXMMU_LUT887L,GFXMMU LUT entry 887 low" hexmask.long.byte 0xBB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBBC "GFXMMU_LUT887H,GFXMMU LUT entry 887 high" hexmask.long.tbyte 0xBBC 0.--17. 1. "LO,Line offset" line.long 0xBC0 "GFXMMU_LUT888L,GFXMMU LUT entry 888 low" hexmask.long.byte 0xBC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBC4 "GFXMMU_LUT888H,GFXMMU LUT entry 888 high" hexmask.long.tbyte 0xBC4 0.--17. 1. "LO,Line offset" line.long 0xBC8 "GFXMMU_LUT889L,GFXMMU LUT entry 889 low" hexmask.long.byte 0xBC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBCC "GFXMMU_LUT889H,GFXMMU LUT entry 889 high" hexmask.long.tbyte 0xBCC 0.--17. 1. "LO,Line offset" line.long 0xBD0 "GFXMMU_LUT890L,GFXMMU LUT entry 890 low" hexmask.long.byte 0xBD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBD4 "GFXMMU_LUT890H,GFXMMU LUT entry 890 high" hexmask.long.tbyte 0xBD4 0.--17. 1. "LO,Line offset" line.long 0xBD8 "GFXMMU_LUT891L,GFXMMU LUT entry 891 low" hexmask.long.byte 0xBD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBDC "GFXMMU_LUT891H,GFXMMU LUT entry 891 high" hexmask.long.tbyte 0xBDC 0.--17. 1. "LO,Line offset" line.long 0xBE0 "GFXMMU_LUT892L,GFXMMU LUT entry 892 low" hexmask.long.byte 0xBE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBE4 "GFXMMU_LUT892H,GFXMMU LUT entry 892 high" hexmask.long.tbyte 0xBE4 0.--17. 1. "LO,Line offset" line.long 0xBE8 "GFXMMU_LUT893L,GFXMMU LUT entry 893 low" hexmask.long.byte 0xBE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBEC "GFXMMU_LUT893H,GFXMMU LUT entry 893 high" hexmask.long.tbyte 0xBEC 0.--17. 1. "LO,Line offset" line.long 0xBF0 "GFXMMU_LUT894L,GFXMMU LUT entry 894 low" hexmask.long.byte 0xBF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xBF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBF4 "GFXMMU_LUT894H,GFXMMU LUT entry 894 high" hexmask.long.tbyte 0xBF4 0.--17. 1. "LO,Line offset" line.long 0xBF8 "GFXMMU_LUT895L,GFXMMU LUT entry 895 low" hexmask.long.byte 0xBF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xBF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xBF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xBFC "GFXMMU_LUT895H,GFXMMU LUT entry 895 high" hexmask.long.tbyte 0xBFC 0.--17. 1. "LO,Line offset" line.long 0xC00 "GFXMMU_LUT896L,GFXMMU LUT entry 896 low" hexmask.long.byte 0xC00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC00 8.--15. 1. "FVB,First valid block" bitfld.long 0xC00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC04 "GFXMMU_LUT896H,GFXMMU LUT entry 896 high" hexmask.long.tbyte 0xC04 0.--17. 1. "LO,Line offset" line.long 0xC08 "GFXMMU_LUT897L,GFXMMU LUT entry 897 low" hexmask.long.byte 0xC08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC08 8.--15. 1. "FVB,First valid block" bitfld.long 0xC08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC0C "GFXMMU_LUT897H,GFXMMU LUT entry 897 high" hexmask.long.tbyte 0xC0C 0.--17. 1. "LO,Line offset" line.long 0xC10 "GFXMMU_LUT898L,GFXMMU LUT entry 898 low" hexmask.long.byte 0xC10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC10 8.--15. 1. "FVB,First valid block" bitfld.long 0xC10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC14 "GFXMMU_LUT898H,GFXMMU LUT entry 898 high" hexmask.long.tbyte 0xC14 0.--17. 1. "LO,Line offset" line.long 0xC18 "GFXMMU_LUT899L,GFXMMU LUT entry 899 low" hexmask.long.byte 0xC18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC18 8.--15. 1. "FVB,First valid block" bitfld.long 0xC18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC1C "GFXMMU_LUT899H,GFXMMU LUT entry 899 high" hexmask.long.tbyte 0xC1C 0.--17. 1. "LO,Line offset" line.long 0xC20 "GFXMMU_LUT900L,GFXMMU LUT entry 900 low" hexmask.long.byte 0xC20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC20 8.--15. 1. "FVB,First valid block" bitfld.long 0xC20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC24 "GFXMMU_LUT900H,GFXMMU LUT entry 900 high" hexmask.long.tbyte 0xC24 0.--17. 1. "LO,Line offset" line.long 0xC28 "GFXMMU_LUT901L,GFXMMU LUT entry 901 low" hexmask.long.byte 0xC28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC28 8.--15. 1. "FVB,First valid block" bitfld.long 0xC28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC2C "GFXMMU_LUT901H,GFXMMU LUT entry 901 high" hexmask.long.tbyte 0xC2C 0.--17. 1. "LO,Line offset" line.long 0xC30 "GFXMMU_LUT902L,GFXMMU LUT entry 902 low" hexmask.long.byte 0xC30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC30 8.--15. 1. "FVB,First valid block" bitfld.long 0xC30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC34 "GFXMMU_LUT902H,GFXMMU LUT entry 902 high" hexmask.long.tbyte 0xC34 0.--17. 1. "LO,Line offset" line.long 0xC38 "GFXMMU_LUT903L,GFXMMU LUT entry 903 low" hexmask.long.byte 0xC38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC38 8.--15. 1. "FVB,First valid block" bitfld.long 0xC38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC3C "GFXMMU_LUT903H,GFXMMU LUT entry 903 high" hexmask.long.tbyte 0xC3C 0.--17. 1. "LO,Line offset" line.long 0xC40 "GFXMMU_LUT904L,GFXMMU LUT entry 904 low" hexmask.long.byte 0xC40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC40 8.--15. 1. "FVB,First valid block" bitfld.long 0xC40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC44 "GFXMMU_LUT904H,GFXMMU LUT entry 904 high" hexmask.long.tbyte 0xC44 0.--17. 1. "LO,Line offset" line.long 0xC48 "GFXMMU_LUT905L,GFXMMU LUT entry 905 low" hexmask.long.byte 0xC48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC48 8.--15. 1. "FVB,First valid block" bitfld.long 0xC48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC4C "GFXMMU_LUT905H,GFXMMU LUT entry 905 high" hexmask.long.tbyte 0xC4C 0.--17. 1. "LO,Line offset" line.long 0xC50 "GFXMMU_LUT906L,GFXMMU LUT entry 906 low" hexmask.long.byte 0xC50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC50 8.--15. 1. "FVB,First valid block" bitfld.long 0xC50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC54 "GFXMMU_LUT906H,GFXMMU LUT entry 906 high" hexmask.long.tbyte 0xC54 0.--17. 1. "LO,Line offset" line.long 0xC58 "GFXMMU_LUT907L,GFXMMU LUT entry 907 low" hexmask.long.byte 0xC58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC58 8.--15. 1. "FVB,First valid block" bitfld.long 0xC58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC5C "GFXMMU_LUT907H,GFXMMU LUT entry 907 high" hexmask.long.tbyte 0xC5C 0.--17. 1. "LO,Line offset" line.long 0xC60 "GFXMMU_LUT908L,GFXMMU LUT entry 908 low" hexmask.long.byte 0xC60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC60 8.--15. 1. "FVB,First valid block" bitfld.long 0xC60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC64 "GFXMMU_LUT908H,GFXMMU LUT entry 908 high" hexmask.long.tbyte 0xC64 0.--17. 1. "LO,Line offset" line.long 0xC68 "GFXMMU_LUT909L,GFXMMU LUT entry 909 low" hexmask.long.byte 0xC68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC68 8.--15. 1. "FVB,First valid block" bitfld.long 0xC68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC6C "GFXMMU_LUT909H,GFXMMU LUT entry 909 high" hexmask.long.tbyte 0xC6C 0.--17. 1. "LO,Line offset" line.long 0xC70 "GFXMMU_LUT910L,GFXMMU LUT entry 910 low" hexmask.long.byte 0xC70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC70 8.--15. 1. "FVB,First valid block" bitfld.long 0xC70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC74 "GFXMMU_LUT910H,GFXMMU LUT entry 910 high" hexmask.long.tbyte 0xC74 0.--17. 1. "LO,Line offset" line.long 0xC78 "GFXMMU_LUT911L,GFXMMU LUT entry 911 low" hexmask.long.byte 0xC78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC78 8.--15. 1. "FVB,First valid block" bitfld.long 0xC78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC7C "GFXMMU_LUT911H,GFXMMU LUT entry 911 high" hexmask.long.tbyte 0xC7C 0.--17. 1. "LO,Line offset" line.long 0xC80 "GFXMMU_LUT912L,GFXMMU LUT entry 912 low" hexmask.long.byte 0xC80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC80 8.--15. 1. "FVB,First valid block" bitfld.long 0xC80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC84 "GFXMMU_LUT912H,GFXMMU LUT entry 912 high" hexmask.long.tbyte 0xC84 0.--17. 1. "LO,Line offset" line.long 0xC88 "GFXMMU_LUT913L,GFXMMU LUT entry 913 low" hexmask.long.byte 0xC88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC88 8.--15. 1. "FVB,First valid block" bitfld.long 0xC88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC8C "GFXMMU_LUT913H,GFXMMU LUT entry 913 high" hexmask.long.tbyte 0xC8C 0.--17. 1. "LO,Line offset" line.long 0xC90 "GFXMMU_LUT914L,GFXMMU LUT entry 914 low" hexmask.long.byte 0xC90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC90 8.--15. 1. "FVB,First valid block" bitfld.long 0xC90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC94 "GFXMMU_LUT914H,GFXMMU LUT entry 914 high" hexmask.long.tbyte 0xC94 0.--17. 1. "LO,Line offset" line.long 0xC98 "GFXMMU_LUT915L,GFXMMU LUT entry 915 low" hexmask.long.byte 0xC98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xC98 8.--15. 1. "FVB,First valid block" bitfld.long 0xC98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xC9C "GFXMMU_LUT915H,GFXMMU LUT entry 915 high" hexmask.long.tbyte 0xC9C 0.--17. 1. "LO,Line offset" line.long 0xCA0 "GFXMMU_LUT916L,GFXMMU LUT entry 916 low" hexmask.long.byte 0xCA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCA4 "GFXMMU_LUT916H,GFXMMU LUT entry 916 high" hexmask.long.tbyte 0xCA4 0.--17. 1. "LO,Line offset" line.long 0xCA8 "GFXMMU_LUT917L,GFXMMU LUT entry 917 low" hexmask.long.byte 0xCA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCAC "GFXMMU_LUT917H,GFXMMU LUT entry 917 high" hexmask.long.tbyte 0xCAC 0.--17. 1. "LO,Line offset" line.long 0xCB0 "GFXMMU_LUT918L,GFXMMU LUT entry 918 low" hexmask.long.byte 0xCB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCB4 "GFXMMU_LUT918H,GFXMMU LUT entry 918 high" hexmask.long.tbyte 0xCB4 0.--17. 1. "LO,Line offset" line.long 0xCB8 "GFXMMU_LUT919L,GFXMMU LUT entry 919 low" hexmask.long.byte 0xCB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCBC "GFXMMU_LUT919H,GFXMMU LUT entry 919 high" hexmask.long.tbyte 0xCBC 0.--17. 1. "LO,Line offset" line.long 0xCC0 "GFXMMU_LUT920L,GFXMMU LUT entry 920 low" hexmask.long.byte 0xCC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCC4 "GFXMMU_LUT920H,GFXMMU LUT entry 920 high" hexmask.long.tbyte 0xCC4 0.--17. 1. "LO,Line offset" line.long 0xCC8 "GFXMMU_LUT921L,GFXMMU LUT entry 921 low" hexmask.long.byte 0xCC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCCC "GFXMMU_LUT921H,GFXMMU LUT entry 921 high" hexmask.long.tbyte 0xCCC 0.--17. 1. "LO,Line offset" line.long 0xCD0 "GFXMMU_LUT922L,GFXMMU LUT entry 922 low" hexmask.long.byte 0xCD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCD4 "GFXMMU_LUT922H,GFXMMU LUT entry 922 high" hexmask.long.tbyte 0xCD4 0.--17. 1. "LO,Line offset" line.long 0xCD8 "GFXMMU_LUT923L,GFXMMU LUT entry 923 low" hexmask.long.byte 0xCD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCDC "GFXMMU_LUT923H,GFXMMU LUT entry 923 high" hexmask.long.tbyte 0xCDC 0.--17. 1. "LO,Line offset" line.long 0xCE0 "GFXMMU_LUT924L,GFXMMU LUT entry 924 low" hexmask.long.byte 0xCE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCE4 "GFXMMU_LUT924H,GFXMMU LUT entry 924 high" hexmask.long.tbyte 0xCE4 0.--17. 1. "LO,Line offset" line.long 0xCE8 "GFXMMU_LUT925L,GFXMMU LUT entry 925 low" hexmask.long.byte 0xCE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCEC "GFXMMU_LUT925H,GFXMMU LUT entry 925 high" hexmask.long.tbyte 0xCEC 0.--17. 1. "LO,Line offset" line.long 0xCF0 "GFXMMU_LUT926L,GFXMMU LUT entry 926 low" hexmask.long.byte 0xCF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xCF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCF4 "GFXMMU_LUT926H,GFXMMU LUT entry 926 high" hexmask.long.tbyte 0xCF4 0.--17. 1. "LO,Line offset" line.long 0xCF8 "GFXMMU_LUT927L,GFXMMU LUT entry 927 low" hexmask.long.byte 0xCF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xCF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xCF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xCFC "GFXMMU_LUT927H,GFXMMU LUT entry 927 high" hexmask.long.tbyte 0xCFC 0.--17. 1. "LO,Line offset" line.long 0xD00 "GFXMMU_LUT928L,GFXMMU LUT entry 928 low" hexmask.long.byte 0xD00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD00 8.--15. 1. "FVB,First valid block" bitfld.long 0xD00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD04 "GFXMMU_LUT928H,GFXMMU LUT entry 928 high" hexmask.long.tbyte 0xD04 0.--17. 1. "LO,Line offset" line.long 0xD08 "GFXMMU_LUT929L,GFXMMU LUT entry 929 low" hexmask.long.byte 0xD08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD08 8.--15. 1. "FVB,First valid block" bitfld.long 0xD08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD0C "GFXMMU_LUT929H,GFXMMU LUT entry 929 high" hexmask.long.tbyte 0xD0C 0.--17. 1. "LO,Line offset" line.long 0xD10 "GFXMMU_LUT930L,GFXMMU LUT entry 930 low" hexmask.long.byte 0xD10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD10 8.--15. 1. "FVB,First valid block" bitfld.long 0xD10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD14 "GFXMMU_LUT930H,GFXMMU LUT entry 930 high" hexmask.long.tbyte 0xD14 0.--17. 1. "LO,Line offset" line.long 0xD18 "GFXMMU_LUT931L,GFXMMU LUT entry 931 low" hexmask.long.byte 0xD18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD18 8.--15. 1. "FVB,First valid block" bitfld.long 0xD18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD1C "GFXMMU_LUT931H,GFXMMU LUT entry 931 high" hexmask.long.tbyte 0xD1C 0.--17. 1. "LO,Line offset" line.long 0xD20 "GFXMMU_LUT932L,GFXMMU LUT entry 932 low" hexmask.long.byte 0xD20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD20 8.--15. 1. "FVB,First valid block" bitfld.long 0xD20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD24 "GFXMMU_LUT932H,GFXMMU LUT entry 932 high" hexmask.long.tbyte 0xD24 0.--17. 1. "LO,Line offset" line.long 0xD28 "GFXMMU_LUT933L,GFXMMU LUT entry 933 low" hexmask.long.byte 0xD28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD28 8.--15. 1. "FVB,First valid block" bitfld.long 0xD28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD2C "GFXMMU_LUT933H,GFXMMU LUT entry 933 high" hexmask.long.tbyte 0xD2C 0.--17. 1. "LO,Line offset" line.long 0xD30 "GFXMMU_LUT934L,GFXMMU LUT entry 934 low" hexmask.long.byte 0xD30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD30 8.--15. 1. "FVB,First valid block" bitfld.long 0xD30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD34 "GFXMMU_LUT934H,GFXMMU LUT entry 934 high" hexmask.long.tbyte 0xD34 0.--17. 1. "LO,Line offset" line.long 0xD38 "GFXMMU_LUT935L,GFXMMU LUT entry 935 low" hexmask.long.byte 0xD38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD38 8.--15. 1. "FVB,First valid block" bitfld.long 0xD38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD3C "GFXMMU_LUT935H,GFXMMU LUT entry 935 high" hexmask.long.tbyte 0xD3C 0.--17. 1. "LO,Line offset" line.long 0xD40 "GFXMMU_LUT936L,GFXMMU LUT entry 936 low" hexmask.long.byte 0xD40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD40 8.--15. 1. "FVB,First valid block" bitfld.long 0xD40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD44 "GFXMMU_LUT936H,GFXMMU LUT entry 936 high" hexmask.long.tbyte 0xD44 0.--17. 1. "LO,Line offset" line.long 0xD48 "GFXMMU_LUT937L,GFXMMU LUT entry 937 low" hexmask.long.byte 0xD48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD48 8.--15. 1. "FVB,First valid block" bitfld.long 0xD48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD4C "GFXMMU_LUT937H,GFXMMU LUT entry 937 high" hexmask.long.tbyte 0xD4C 0.--17. 1. "LO,Line offset" line.long 0xD50 "GFXMMU_LUT938L,GFXMMU LUT entry 938 low" hexmask.long.byte 0xD50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD50 8.--15. 1. "FVB,First valid block" bitfld.long 0xD50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD54 "GFXMMU_LUT938H,GFXMMU LUT entry 938 high" hexmask.long.tbyte 0xD54 0.--17. 1. "LO,Line offset" line.long 0xD58 "GFXMMU_LUT939L,GFXMMU LUT entry 939 low" hexmask.long.byte 0xD58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD58 8.--15. 1. "FVB,First valid block" bitfld.long 0xD58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD5C "GFXMMU_LUT939H,GFXMMU LUT entry 939 high" hexmask.long.tbyte 0xD5C 0.--17. 1. "LO,Line offset" line.long 0xD60 "GFXMMU_LUT940L,GFXMMU LUT entry 940 low" hexmask.long.byte 0xD60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD60 8.--15. 1. "FVB,First valid block" bitfld.long 0xD60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD64 "GFXMMU_LUT940H,GFXMMU LUT entry 940 high" hexmask.long.tbyte 0xD64 0.--17. 1. "LO,Line offset" line.long 0xD68 "GFXMMU_LUT941L,GFXMMU LUT entry 941 low" hexmask.long.byte 0xD68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD68 8.--15. 1. "FVB,First valid block" bitfld.long 0xD68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD6C "GFXMMU_LUT941H,GFXMMU LUT entry 941 high" hexmask.long.tbyte 0xD6C 0.--17. 1. "LO,Line offset" line.long 0xD70 "GFXMMU_LUT942L,GFXMMU LUT entry 942 low" hexmask.long.byte 0xD70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD70 8.--15. 1. "FVB,First valid block" bitfld.long 0xD70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD74 "GFXMMU_LUT942H,GFXMMU LUT entry 942 high" hexmask.long.tbyte 0xD74 0.--17. 1. "LO,Line offset" line.long 0xD78 "GFXMMU_LUT943L,GFXMMU LUT entry 943 low" hexmask.long.byte 0xD78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD78 8.--15. 1. "FVB,First valid block" bitfld.long 0xD78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD7C "GFXMMU_LUT943H,GFXMMU LUT entry 943 high" hexmask.long.tbyte 0xD7C 0.--17. 1. "LO,Line offset" line.long 0xD80 "GFXMMU_LUT944L,GFXMMU LUT entry 944 low" hexmask.long.byte 0xD80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD80 8.--15. 1. "FVB,First valid block" bitfld.long 0xD80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD84 "GFXMMU_LUT944H,GFXMMU LUT entry 944 high" hexmask.long.tbyte 0xD84 0.--17. 1. "LO,Line offset" line.long 0xD88 "GFXMMU_LUT945L,GFXMMU LUT entry 945 low" hexmask.long.byte 0xD88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD88 8.--15. 1. "FVB,First valid block" bitfld.long 0xD88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD8C "GFXMMU_LUT945H,GFXMMU LUT entry 945 high" hexmask.long.tbyte 0xD8C 0.--17. 1. "LO,Line offset" line.long 0xD90 "GFXMMU_LUT946L,GFXMMU LUT entry 946 low" hexmask.long.byte 0xD90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD90 8.--15. 1. "FVB,First valid block" bitfld.long 0xD90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD94 "GFXMMU_LUT946H,GFXMMU LUT entry 946 high" hexmask.long.tbyte 0xD94 0.--17. 1. "LO,Line offset" line.long 0xD98 "GFXMMU_LUT947L,GFXMMU LUT entry 947 low" hexmask.long.byte 0xD98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xD98 8.--15. 1. "FVB,First valid block" bitfld.long 0xD98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xD9C "GFXMMU_LUT947H,GFXMMU LUT entry 947 high" hexmask.long.tbyte 0xD9C 0.--17. 1. "LO,Line offset" line.long 0xDA0 "GFXMMU_LUT948L,GFXMMU LUT entry 948 low" hexmask.long.byte 0xDA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDA4 "GFXMMU_LUT948H,GFXMMU LUT entry 948 high" hexmask.long.tbyte 0xDA4 0.--17. 1. "LO,Line offset" line.long 0xDA8 "GFXMMU_LUT949L,GFXMMU LUT entry 949 low" hexmask.long.byte 0xDA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDAC "GFXMMU_LUT949H,GFXMMU LUT entry 949 high" hexmask.long.tbyte 0xDAC 0.--17. 1. "LO,Line offset" line.long 0xDB0 "GFXMMU_LUT950L,GFXMMU LUT entry 950 low" hexmask.long.byte 0xDB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDB4 "GFXMMU_LUT950H,GFXMMU LUT entry 950 high" hexmask.long.tbyte 0xDB4 0.--17. 1. "LO,Line offset" line.long 0xDB8 "GFXMMU_LUT951L,GFXMMU LUT entry 951 low" hexmask.long.byte 0xDB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDBC "GFXMMU_LUT951H,GFXMMU LUT entry 951 high" hexmask.long.tbyte 0xDBC 0.--17. 1. "LO,Line offset" line.long 0xDC0 "GFXMMU_LUT952L,GFXMMU LUT entry 952 low" hexmask.long.byte 0xDC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDC4 "GFXMMU_LUT952H,GFXMMU LUT entry 952 high" hexmask.long.tbyte 0xDC4 0.--17. 1. "LO,Line offset" line.long 0xDC8 "GFXMMU_LUT953L,GFXMMU LUT entry 953 low" hexmask.long.byte 0xDC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDCC "GFXMMU_LUT953H,GFXMMU LUT entry 953 high" hexmask.long.tbyte 0xDCC 0.--17. 1. "LO,Line offset" line.long 0xDD0 "GFXMMU_LUT954L,GFXMMU LUT entry 954 low" hexmask.long.byte 0xDD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDD4 "GFXMMU_LUT954H,GFXMMU LUT entry 954 high" hexmask.long.tbyte 0xDD4 0.--17. 1. "LO,Line offset" line.long 0xDD8 "GFXMMU_LUT955L,GFXMMU LUT entry 955 low" hexmask.long.byte 0xDD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDDC "GFXMMU_LUT955H,GFXMMU LUT entry 955 high" hexmask.long.tbyte 0xDDC 0.--17. 1. "LO,Line offset" line.long 0xDE0 "GFXMMU_LUT956L,GFXMMU LUT entry 956 low" hexmask.long.byte 0xDE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDE4 "GFXMMU_LUT956H,GFXMMU LUT entry 956 high" hexmask.long.tbyte 0xDE4 0.--17. 1. "LO,Line offset" line.long 0xDE8 "GFXMMU_LUT957L,GFXMMU LUT entry 957 low" hexmask.long.byte 0xDE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDEC "GFXMMU_LUT957H,GFXMMU LUT entry 957 high" hexmask.long.tbyte 0xDEC 0.--17. 1. "LO,Line offset" line.long 0xDF0 "GFXMMU_LUT958L,GFXMMU LUT entry 958 low" hexmask.long.byte 0xDF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xDF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDF4 "GFXMMU_LUT958H,GFXMMU LUT entry 958 high" hexmask.long.tbyte 0xDF4 0.--17. 1. "LO,Line offset" line.long 0xDF8 "GFXMMU_LUT959L,GFXMMU LUT entry 959 low" hexmask.long.byte 0xDF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xDF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xDF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xDFC "GFXMMU_LUT959H,GFXMMU LUT entry 959 high" hexmask.long.tbyte 0xDFC 0.--17. 1. "LO,Line offset" line.long 0xE00 "GFXMMU_LUT960L,GFXMMU LUT entry 960 low" hexmask.long.byte 0xE00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE00 8.--15. 1. "FVB,First valid block" bitfld.long 0xE00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE04 "GFXMMU_LUT960H,GFXMMU LUT entry 960 high" hexmask.long.tbyte 0xE04 0.--17. 1. "LO,Line offset" line.long 0xE08 "GFXMMU_LUT961L,GFXMMU LUT entry 961 low" hexmask.long.byte 0xE08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE08 8.--15. 1. "FVB,First valid block" bitfld.long 0xE08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE0C "GFXMMU_LUT961H,GFXMMU LUT entry 961 high" hexmask.long.tbyte 0xE0C 0.--17. 1. "LO,Line offset" line.long 0xE10 "GFXMMU_LUT962L,GFXMMU LUT entry 962 low" hexmask.long.byte 0xE10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE10 8.--15. 1. "FVB,First valid block" bitfld.long 0xE10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE14 "GFXMMU_LUT962H,GFXMMU LUT entry 962 high" hexmask.long.tbyte 0xE14 0.--17. 1. "LO,Line offset" line.long 0xE18 "GFXMMU_LUT963L,GFXMMU LUT entry 963 low" hexmask.long.byte 0xE18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE18 8.--15. 1. "FVB,First valid block" bitfld.long 0xE18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE1C "GFXMMU_LUT963H,GFXMMU LUT entry 963 high" hexmask.long.tbyte 0xE1C 0.--17. 1. "LO,Line offset" line.long 0xE20 "GFXMMU_LUT964L,GFXMMU LUT entry 964 low" hexmask.long.byte 0xE20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE20 8.--15. 1. "FVB,First valid block" bitfld.long 0xE20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE24 "GFXMMU_LUT964H,GFXMMU LUT entry 964 high" hexmask.long.tbyte 0xE24 0.--17. 1. "LO,Line offset" line.long 0xE28 "GFXMMU_LUT965L,GFXMMU LUT entry 965 low" hexmask.long.byte 0xE28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE28 8.--15. 1. "FVB,First valid block" bitfld.long 0xE28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE2C "GFXMMU_LUT965H,GFXMMU LUT entry 965 high" hexmask.long.tbyte 0xE2C 0.--17. 1. "LO,Line offset" line.long 0xE30 "GFXMMU_LUT966L,GFXMMU LUT entry 966 low" hexmask.long.byte 0xE30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE30 8.--15. 1. "FVB,First valid block" bitfld.long 0xE30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE34 "GFXMMU_LUT966H,GFXMMU LUT entry 966 high" hexmask.long.tbyte 0xE34 0.--17. 1. "LO,Line offset" line.long 0xE38 "GFXMMU_LUT967L,GFXMMU LUT entry 967 low" hexmask.long.byte 0xE38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE38 8.--15. 1. "FVB,First valid block" bitfld.long 0xE38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE3C "GFXMMU_LUT967H,GFXMMU LUT entry 967 high" hexmask.long.tbyte 0xE3C 0.--17. 1. "LO,Line offset" line.long 0xE40 "GFXMMU_LUT968L,GFXMMU LUT entry 968 low" hexmask.long.byte 0xE40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE40 8.--15. 1. "FVB,First valid block" bitfld.long 0xE40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE44 "GFXMMU_LUT968H,GFXMMU LUT entry 968 high" hexmask.long.tbyte 0xE44 0.--17. 1. "LO,Line offset" line.long 0xE48 "GFXMMU_LUT969L,GFXMMU LUT entry 969 low" hexmask.long.byte 0xE48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE48 8.--15. 1. "FVB,First valid block" bitfld.long 0xE48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE4C "GFXMMU_LUT969H,GFXMMU LUT entry 969 high" hexmask.long.tbyte 0xE4C 0.--17. 1. "LO,Line offset" line.long 0xE50 "GFXMMU_LUT970L,GFXMMU LUT entry 970 low" hexmask.long.byte 0xE50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE50 8.--15. 1. "FVB,First valid block" bitfld.long 0xE50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE54 "GFXMMU_LUT970H,GFXMMU LUT entry 970 high" hexmask.long.tbyte 0xE54 0.--17. 1. "LO,Line offset" line.long 0xE58 "GFXMMU_LUT971L,GFXMMU LUT entry 971 low" hexmask.long.byte 0xE58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE58 8.--15. 1. "FVB,First valid block" bitfld.long 0xE58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE5C "GFXMMU_LUT971H,GFXMMU LUT entry 971 high" hexmask.long.tbyte 0xE5C 0.--17. 1. "LO,Line offset" line.long 0xE60 "GFXMMU_LUT972L,GFXMMU LUT entry 972 low" hexmask.long.byte 0xE60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE60 8.--15. 1. "FVB,First valid block" bitfld.long 0xE60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE64 "GFXMMU_LUT972H,GFXMMU LUT entry 972 high" hexmask.long.tbyte 0xE64 0.--17. 1. "LO,Line offset" line.long 0xE68 "GFXMMU_LUT973L,GFXMMU LUT entry 973 low" hexmask.long.byte 0xE68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE68 8.--15. 1. "FVB,First valid block" bitfld.long 0xE68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE6C "GFXMMU_LUT973H,GFXMMU LUT entry 973 high" hexmask.long.tbyte 0xE6C 0.--17. 1. "LO,Line offset" line.long 0xE70 "GFXMMU_LUT974L,GFXMMU LUT entry 974 low" hexmask.long.byte 0xE70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE70 8.--15. 1. "FVB,First valid block" bitfld.long 0xE70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE74 "GFXMMU_LUT974H,GFXMMU LUT entry 974 high" hexmask.long.tbyte 0xE74 0.--17. 1. "LO,Line offset" line.long 0xE78 "GFXMMU_LUT975L,GFXMMU LUT entry 975 low" hexmask.long.byte 0xE78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE78 8.--15. 1. "FVB,First valid block" bitfld.long 0xE78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE7C "GFXMMU_LUT975H,GFXMMU LUT entry 975 high" hexmask.long.tbyte 0xE7C 0.--17. 1. "LO,Line offset" line.long 0xE80 "GFXMMU_LUT976L,GFXMMU LUT entry 976 low" hexmask.long.byte 0xE80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE80 8.--15. 1. "FVB,First valid block" bitfld.long 0xE80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE84 "GFXMMU_LUT976H,GFXMMU LUT entry 976 high" hexmask.long.tbyte 0xE84 0.--17. 1. "LO,Line offset" line.long 0xE88 "GFXMMU_LUT977L,GFXMMU LUT entry 977 low" hexmask.long.byte 0xE88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE88 8.--15. 1. "FVB,First valid block" bitfld.long 0xE88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE8C "GFXMMU_LUT977H,GFXMMU LUT entry 977 high" hexmask.long.tbyte 0xE8C 0.--17. 1. "LO,Line offset" line.long 0xE90 "GFXMMU_LUT978L,GFXMMU LUT entry 978 low" hexmask.long.byte 0xE90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE90 8.--15. 1. "FVB,First valid block" bitfld.long 0xE90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE94 "GFXMMU_LUT978H,GFXMMU LUT entry 978 high" hexmask.long.tbyte 0xE94 0.--17. 1. "LO,Line offset" line.long 0xE98 "GFXMMU_LUT979L,GFXMMU LUT entry 979 low" hexmask.long.byte 0xE98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xE98 8.--15. 1. "FVB,First valid block" bitfld.long 0xE98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xE9C "GFXMMU_LUT979H,GFXMMU LUT entry 979 high" hexmask.long.tbyte 0xE9C 0.--17. 1. "LO,Line offset" line.long 0xEA0 "GFXMMU_LUT980L,GFXMMU LUT entry 980 low" hexmask.long.byte 0xEA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEA4 "GFXMMU_LUT980H,GFXMMU LUT entry 980 high" hexmask.long.tbyte 0xEA4 0.--17. 1. "LO,Line offset" line.long 0xEA8 "GFXMMU_LUT981L,GFXMMU LUT entry 981 low" hexmask.long.byte 0xEA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEAC "GFXMMU_LUT981H,GFXMMU LUT entry 981 high" hexmask.long.tbyte 0xEAC 0.--17. 1. "LO,Line offset" line.long 0xEB0 "GFXMMU_LUT982L,GFXMMU LUT entry 982 low" hexmask.long.byte 0xEB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEB4 "GFXMMU_LUT982H,GFXMMU LUT entry 982 high" hexmask.long.tbyte 0xEB4 0.--17. 1. "LO,Line offset" line.long 0xEB8 "GFXMMU_LUT983L,GFXMMU LUT entry 983 low" hexmask.long.byte 0xEB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEBC "GFXMMU_LUT983H,GFXMMU LUT entry 983 high" hexmask.long.tbyte 0xEBC 0.--17. 1. "LO,Line offset" line.long 0xEC0 "GFXMMU_LUT984L,GFXMMU LUT entry 984 low" hexmask.long.byte 0xEC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEC4 "GFXMMU_LUT984H,GFXMMU LUT entry 984 high" hexmask.long.tbyte 0xEC4 0.--17. 1. "LO,Line offset" line.long 0xEC8 "GFXMMU_LUT985L,GFXMMU LUT entry 985 low" hexmask.long.byte 0xEC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xECC "GFXMMU_LUT985H,GFXMMU LUT entry 985 high" hexmask.long.tbyte 0xECC 0.--17. 1. "LO,Line offset" line.long 0xED0 "GFXMMU_LUT986L,GFXMMU LUT entry 986 low" hexmask.long.byte 0xED0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xED0 8.--15. 1. "FVB,First valid block" bitfld.long 0xED0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xED4 "GFXMMU_LUT986H,GFXMMU LUT entry 986 high" hexmask.long.tbyte 0xED4 0.--17. 1. "LO,Line offset" line.long 0xED8 "GFXMMU_LUT987L,GFXMMU LUT entry 987 low" hexmask.long.byte 0xED8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xED8 8.--15. 1. "FVB,First valid block" bitfld.long 0xED8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEDC "GFXMMU_LUT987H,GFXMMU LUT entry 987 high" hexmask.long.tbyte 0xEDC 0.--17. 1. "LO,Line offset" line.long 0xEE0 "GFXMMU_LUT988L,GFXMMU LUT entry 988 low" hexmask.long.byte 0xEE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEE4 "GFXMMU_LUT988H,GFXMMU LUT entry 988 high" hexmask.long.tbyte 0xEE4 0.--17. 1. "LO,Line offset" line.long 0xEE8 "GFXMMU_LUT989L,GFXMMU LUT entry 989 low" hexmask.long.byte 0xEE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEEC "GFXMMU_LUT989H,GFXMMU LUT entry 989 high" hexmask.long.tbyte 0xEEC 0.--17. 1. "LO,Line offset" line.long 0xEF0 "GFXMMU_LUT990L,GFXMMU LUT entry 990 low" hexmask.long.byte 0xEF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xEF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEF4 "GFXMMU_LUT990H,GFXMMU LUT entry 990 high" hexmask.long.tbyte 0xEF4 0.--17. 1. "LO,Line offset" line.long 0xEF8 "GFXMMU_LUT991L,GFXMMU LUT entry 991 low" hexmask.long.byte 0xEF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xEF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xEF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xEFC "GFXMMU_LUT991H,GFXMMU LUT entry 991 high" hexmask.long.tbyte 0xEFC 0.--17. 1. "LO,Line offset" line.long 0xF00 "GFXMMU_LUT992L,GFXMMU LUT entry 992 low" hexmask.long.byte 0xF00 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF00 8.--15. 1. "FVB,First valid block" bitfld.long 0xF00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF04 "GFXMMU_LUT992H,GFXMMU LUT entry 992 high" hexmask.long.tbyte 0xF04 0.--17. 1. "LO,Line offset" line.long 0xF08 "GFXMMU_LUT993L,GFXMMU LUT entry 993 low" hexmask.long.byte 0xF08 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF08 8.--15. 1. "FVB,First valid block" bitfld.long 0xF08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF0C "GFXMMU_LUT993H,GFXMMU LUT entry 993 high" hexmask.long.tbyte 0xF0C 0.--17. 1. "LO,Line offset" line.long 0xF10 "GFXMMU_LUT994L,GFXMMU LUT entry 994 low" hexmask.long.byte 0xF10 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF10 8.--15. 1. "FVB,First valid block" bitfld.long 0xF10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF14 "GFXMMU_LUT994H,GFXMMU LUT entry 994 high" hexmask.long.tbyte 0xF14 0.--17. 1. "LO,Line offset" line.long 0xF18 "GFXMMU_LUT995L,GFXMMU LUT entry 995 low" hexmask.long.byte 0xF18 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF18 8.--15. 1. "FVB,First valid block" bitfld.long 0xF18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF1C "GFXMMU_LUT995H,GFXMMU LUT entry 995 high" hexmask.long.tbyte 0xF1C 0.--17. 1. "LO,Line offset" line.long 0xF20 "GFXMMU_LUT996L,GFXMMU LUT entry 996 low" hexmask.long.byte 0xF20 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF20 8.--15. 1. "FVB,First valid block" bitfld.long 0xF20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF24 "GFXMMU_LUT996H,GFXMMU LUT entry 996 high" hexmask.long.tbyte 0xF24 0.--17. 1. "LO,Line offset" line.long 0xF28 "GFXMMU_LUT997L,GFXMMU LUT entry 997 low" hexmask.long.byte 0xF28 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF28 8.--15. 1. "FVB,First valid block" bitfld.long 0xF28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF2C "GFXMMU_LUT997H,GFXMMU LUT entry 997 high" hexmask.long.tbyte 0xF2C 0.--17. 1. "LO,Line offset" line.long 0xF30 "GFXMMU_LUT998L,GFXMMU LUT entry 998 low" hexmask.long.byte 0xF30 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF30 8.--15. 1. "FVB,First valid block" bitfld.long 0xF30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF34 "GFXMMU_LUT998H,GFXMMU LUT entry 998 high" hexmask.long.tbyte 0xF34 0.--17. 1. "LO,Line offset" line.long 0xF38 "GFXMMU_LUT999L,GFXMMU LUT entry 999 low" hexmask.long.byte 0xF38 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF38 8.--15. 1. "FVB,First valid block" bitfld.long 0xF38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF3C "GFXMMU_LUT999H,GFXMMU LUT entry 999 high" hexmask.long.tbyte 0xF3C 0.--17. 1. "LO,Line offset" line.long 0xF40 "GFXMMU_LUT1000L,GFXMMU LUT entry 1000 low" hexmask.long.byte 0xF40 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF40 8.--15. 1. "FVB,First valid block" bitfld.long 0xF40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF44 "GFXMMU_LUT1000H,GFXMMU LUT entry 1000 high" hexmask.long.tbyte 0xF44 0.--17. 1. "LO,Line offset" line.long 0xF48 "GFXMMU_LUT1001L,GFXMMU LUT entry 1001 low" hexmask.long.byte 0xF48 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF48 8.--15. 1. "FVB,First valid block" bitfld.long 0xF48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF4C "GFXMMU_LUT1001H,GFXMMU LUT entry 1001 high" hexmask.long.tbyte 0xF4C 0.--17. 1. "LO,Line offset" line.long 0xF50 "GFXMMU_LUT1002L,GFXMMU LUT entry 1002 low" hexmask.long.byte 0xF50 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF50 8.--15. 1. "FVB,First valid block" bitfld.long 0xF50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF54 "GFXMMU_LUT1002H,GFXMMU LUT entry 1002 high" hexmask.long.tbyte 0xF54 0.--17. 1. "LO,Line offset" line.long 0xF58 "GFXMMU_LUT1003L,GFXMMU LUT entry 1003 low" hexmask.long.byte 0xF58 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF58 8.--15. 1. "FVB,First valid block" bitfld.long 0xF58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF5C "GFXMMU_LUT1003H,GFXMMU LUT entry 1003 high" hexmask.long.tbyte 0xF5C 0.--17. 1. "LO,Line offset" line.long 0xF60 "GFXMMU_LUT1004L,GFXMMU LUT entry 1004 low" hexmask.long.byte 0xF60 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF60 8.--15. 1. "FVB,First valid block" bitfld.long 0xF60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF64 "GFXMMU_LUT1004H,GFXMMU LUT entry 1004 high" hexmask.long.tbyte 0xF64 0.--17. 1. "LO,Line offset" line.long 0xF68 "GFXMMU_LUT1005L,GFXMMU LUT entry 1005 low" hexmask.long.byte 0xF68 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF68 8.--15. 1. "FVB,First valid block" bitfld.long 0xF68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF6C "GFXMMU_LUT1005H,GFXMMU LUT entry 1005 high" hexmask.long.tbyte 0xF6C 0.--17. 1. "LO,Line offset" line.long 0xF70 "GFXMMU_LUT1006L,GFXMMU LUT entry 1006 low" hexmask.long.byte 0xF70 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF70 8.--15. 1. "FVB,First valid block" bitfld.long 0xF70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF74 "GFXMMU_LUT1006H,GFXMMU LUT entry 1006 high" hexmask.long.tbyte 0xF74 0.--17. 1. "LO,Line offset" line.long 0xF78 "GFXMMU_LUT1007L,GFXMMU LUT entry 1007 low" hexmask.long.byte 0xF78 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF78 8.--15. 1. "FVB,First valid block" bitfld.long 0xF78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF7C "GFXMMU_LUT1007H,GFXMMU LUT entry 1007 high" hexmask.long.tbyte 0xF7C 0.--17. 1. "LO,Line offset" line.long 0xF80 "GFXMMU_LUT1008L,GFXMMU LUT entry 1008 low" hexmask.long.byte 0xF80 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF80 8.--15. 1. "FVB,First valid block" bitfld.long 0xF80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF84 "GFXMMU_LUT1008H,GFXMMU LUT entry 1008 high" hexmask.long.tbyte 0xF84 0.--17. 1. "LO,Line offset" line.long 0xF88 "GFXMMU_LUT1009L,GFXMMU LUT entry 1009 low" hexmask.long.byte 0xF88 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF88 8.--15. 1. "FVB,First valid block" bitfld.long 0xF88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF8C "GFXMMU_LUT1009H,GFXMMU LUT entry 1009 high" hexmask.long.tbyte 0xF8C 0.--17. 1. "LO,Line offset" line.long 0xF90 "GFXMMU_LUT1010L,GFXMMU LUT entry 1010 low" hexmask.long.byte 0xF90 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF90 8.--15. 1. "FVB,First valid block" bitfld.long 0xF90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF94 "GFXMMU_LUT1010H,GFXMMU LUT entry 1010 high" hexmask.long.tbyte 0xF94 0.--17. 1. "LO,Line offset" line.long 0xF98 "GFXMMU_LUT1011L,GFXMMU LUT entry 1011 low" hexmask.long.byte 0xF98 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xF98 8.--15. 1. "FVB,First valid block" bitfld.long 0xF98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xF9C "GFXMMU_LUT1011H,GFXMMU LUT entry 1011 high" hexmask.long.tbyte 0xF9C 0.--17. 1. "LO,Line offset" line.long 0xFA0 "GFXMMU_LUT1012L,GFXMMU LUT entry 1012 low" hexmask.long.byte 0xFA0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFA0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFA4 "GFXMMU_LUT1012H,GFXMMU LUT entry 1012 high" hexmask.long.tbyte 0xFA4 0.--17. 1. "LO,Line offset" line.long 0xFA8 "GFXMMU_LUT1013L,GFXMMU LUT entry 1013 low" hexmask.long.byte 0xFA8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFA8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFAC "GFXMMU_LUT1013H,GFXMMU LUT entry 1013 high" hexmask.long.tbyte 0xFAC 0.--17. 1. "LO,Line offset" line.long 0xFB0 "GFXMMU_LUT1014L,GFXMMU LUT entry 1014 low" hexmask.long.byte 0xFB0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFB0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFB4 "GFXMMU_LUT1014H,GFXMMU LUT entry 1014 high" hexmask.long.tbyte 0xFB4 0.--17. 1. "LO,Line offset" line.long 0xFB8 "GFXMMU_LUT1015L,GFXMMU LUT entry 1015 low" hexmask.long.byte 0xFB8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFB8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFBC "GFXMMU_LUT1015H,GFXMMU LUT entry 1015 high" hexmask.long.tbyte 0xFBC 0.--17. 1. "LO,Line offset" line.long 0xFC0 "GFXMMU_LUT1016L,GFXMMU LUT entry 1016 low" hexmask.long.byte 0xFC0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFC0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFC4 "GFXMMU_LUT1016H,GFXMMU LUT entry 1016 high" hexmask.long.tbyte 0xFC4 0.--17. 1. "LO,Line offset" line.long 0xFC8 "GFXMMU_LUT1017L,GFXMMU LUT entry 1017 low" hexmask.long.byte 0xFC8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFC8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFCC "GFXMMU_LUT1017H,GFXMMU LUT entry 1017 high" hexmask.long.tbyte 0xFCC 0.--17. 1. "LO,Line offset" line.long 0xFD0 "GFXMMU_LUT1018L,GFXMMU LUT entry 1018 low" hexmask.long.byte 0xFD0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFD0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFD4 "GFXMMU_LUT1018H,GFXMMU LUT entry 1018 high" hexmask.long.tbyte 0xFD4 0.--17. 1. "LO,Line offset" line.long 0xFD8 "GFXMMU_LUT1019L,GFXMMU LUT entry 1019 low" hexmask.long.byte 0xFD8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFD8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFDC "GFXMMU_LUT1019H,GFXMMU LUT entry 1019 high" hexmask.long.tbyte 0xFDC 0.--17. 1. "LO,Line offset" line.long 0xFE0 "GFXMMU_LUT1020L,GFXMMU LUT entry 1020 low" hexmask.long.byte 0xFE0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFE0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFE4 "GFXMMU_LUT1020H,GFXMMU LUT entry 1020 high" hexmask.long.tbyte 0xFE4 0.--17. 1. "LO,Line offset" line.long 0xFE8 "GFXMMU_LUT1021L,GFXMMU LUT entry 1021 low" hexmask.long.byte 0xFE8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFE8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFEC "GFXMMU_LUT1021H,GFXMMU LUT entry 1021 high" hexmask.long.tbyte 0xFEC 0.--17. 1. "LO,Line offset" line.long 0xFF0 "GFXMMU_LUT1022L,GFXMMU LUT entry 1022 low" hexmask.long.byte 0xFF0 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFF0 8.--15. 1. "FVB,First valid block" bitfld.long 0xFF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFF4 "GFXMMU_LUT1022H,GFXMMU LUT entry 1022 high" hexmask.long.tbyte 0xFF4 0.--17. 1. "LO,Line offset" line.long 0xFF8 "GFXMMU_LUT1023L,GFXMMU LUT entry 1023 low" hexmask.long.byte 0xFF8 16.--23. 1. "LVB,Last valid block" hexmask.long.byte 0xFF8 8.--15. 1. "FVB,First valid block" bitfld.long 0xFF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)" line.long 0xFFC "GFXMMU_LUT1023H,GFXMMU LUT entry 1023 high" hexmask.long.tbyte 0xFFC 0.--17. 1. "LO,Line offset" tree.end tree.end tree "GFXTIM (Graphic Timer)" base ad:0x0 tree "GFXTIM" base ad:0x48004000 group.long 0x0++0xB line.long 0x0 "GFXTIM_CR,GFXTIM configuration register" bitfld.long 0x0 17. "LCCOE,line-clock calibration output enable" "0: line-clock output disabled,1: line-clock output enabled" bitfld.long 0x0 16. "FCCOE,frame-clock calibration output enable" "0: frame-clock output disabled,1: frame-clock output enabled" newline bitfld.long 0x0 8.--9. "SYNCS,synchronization source" "0: gfxtim_hsync[0] and gfxtim_vsync[0] selected,1: gfxtim_hsync[1] and gfxtim_vsync[1] selected,2: gfxtim_hsync[2] and gfxtim_vsync[2] selected,3: gfxtim_hsync[3] and gfxtim_vsync[3] selected" bitfld.long 0x0 4. "TEPOL,tearing--effect polarity" "0: tearing effect active on rising edge,1: tearing effect active on falling edge" newline bitfld.long 0x0 0.--1. "TES,tearing source" "0: TE input pad selected,1: gfxtim_ite selected,2: HSYNC input selected by SYNCS[1:0],3: VSYNC input selected by SYNCS[1:0]" line.long 0x4 "GFXTIM_CGCR,GFXTIM clock generator configuration register" bitfld.long 0x4 28.--30. "FCCHRS,frame- -clock counter hardware reload source" "0: no hardware reload,1: line- -clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 24. "FCCFR,frame clock counter force reload" "0: No effect,1: frame clock counter reload forced" newline bitfld.long 0x4 20.--22. "FCCCS,frame clock counter clock source" "0: frame clock counter disabled,1: line clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 16.--18. "FCS,frame clock source" "0: line clock counter underflow,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" newline bitfld.long 0x4 12.--14. "LCCHRS,line clock counter hardware reload source" "0: no hardware reload,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 8. "LCCFR,line clock counter force reload" "0: no effect,1: line clock counter reload forced" newline bitfld.long 0x4 4. "LCCCS,line clock counter clock source" "0: line clock counter disabled,1: system clock selected" bitfld.long 0x4 0.--2. "LCS,line clock source" "0: line clock counter underflow,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" line.long 0x8 "GFXTIM_TCR,GFXTIM timers configuration register" bitfld.long 0x8 22. "FRFC2R,force relative frame counter 2 reload" "0: no effect,1: relative frame counter 2 reload forced" bitfld.long 0x8 21. "RFC2CM,relative frame counter 2 continuous mode" "0: relative frame counter 2 is one shot.,1: relative frame counter 2 is in continuous mode." newline bitfld.long 0x8 20. "RFC2EN,relative frame counter 2 enable" "0: no effect,1: relative frame counter 2 enabled" bitfld.long 0x8 18. "FRFC1R,force relative frame counter 1 reload" "0: no effect,1: relative frame counter 1 reload forced" newline bitfld.long 0x8 17. "RFC1CM,relative frame counter 1 continuous mode" "0: relative frame counter 1 is one shot.,1: relative frame counter 1 is in continuous mode." bitfld.long 0x8 16. "RFC1EN,relative frame counter 1 enable" "0: no effect,1: relative frame counter enabled" newline bitfld.long 0x8 5. "FALCR,force absolute line counter reset" "0: no effect,1: absolute line counter reset forced" bitfld.long 0x8 4. "ALCEN,absolute line counter enable" "0: no effect,1: absolute line counter enabled" newline bitfld.long 0x8 1. "FAFCR,force absolute frame counter reset" "0: no effect,1: absolute frame counter reset forced" bitfld.long 0x8 0. "AFCEN,absolute frame counter enable" "0: no effect,1: absolute frame counter enabled" wgroup.long 0xC++0x3 line.long 0x0 "GFXTIM_TDR,GFXTIM timers disable register" bitfld.long 0x0 20. "RFC2DIS,relative frame counter 2 disable" "0: no effect,1: relative frame counter 2 disabled" bitfld.long 0x0 16. "RFC1DIS,relative frame counter 1 disable" "0: no effect,1: relative frame counter 1 disabled" newline bitfld.long 0x0 4. "ALCDIS,absolute line counter disable" "0: no effect,1: absolute line counter disabled" bitfld.long 0x0 0. "AFCDIS,absolute frame counter disable" "0: no effect,1: absolute frame counter disabled" group.long 0x10++0x7 line.long 0x0 "GFXTIM_EVCR,GFXTIM events control register" bitfld.long 0x0 3. "EV4EN,event 4 enable" "0: event 4 generation disabled,1: event 4 generation enabled" bitfld.long 0x0 2. "EV3EN,event 3 enable" "0: event 3 generation disabled,1: event 3 generation enabled" newline bitfld.long 0x0 1. "EV2EN,event 2 enable" "0: event 2 generation disabled,1: event 2 generation enabled" bitfld.long 0x0 0. "EV1EN,event 1 enable" "0: event 1 generation disabled,1: event 1 generation enabled" line.long 0x4 "GFXTIM_EVSR,GFXTIM events selection register" bitfld.long 0x4 28.--30. "FES4,frame-event selection 4" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 24.--26. "LES4,line-event selection 4" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 20.--22. "FES3,frame-event selection 3" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 16.--18. "LES3,line-event selection 3" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 12.--14. "FES2,frame-event selection 2" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 8.--10. "LES2,line-event selection 2" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 4.--6. "FES1,frame-event selection 1" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 0.--2. "LES1,line-event selection 1" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" group.long 0x20++0x3 line.long 0x0 "GFXTIM_WDGTCR,GFXTIM watchdog timer configuration register" bitfld.long 0x0 16. "FWDGR,force watchdog reload" "0: no effect,1: graphic watchdog reload forced" hexmask.long.byte 0x0 8.--11. 1. "WDGCS,watchdog clock source" newline bitfld.long 0x0 4.--5. "WDGHRC,watchdog hardware reload configuration" "0: watchdog hardware reload disabled,1: watchdog reloaded a rising edge of gfxtim_wrld,2: watchdog reloaded a falling edge of gfxtim_wrld,?" rbitfld.long 0x0 2. "WDGS,watchdog status" "0: graphic watchdog disabled,1: graphic watchdog enabled" newline bitfld.long 0x0 1. "WDGDIS,watchdog disable" "0: no effect,1: graphic watchdog disabled" bitfld.long 0x0 0. "WDGEN,watchdog enable" "0: no effect,1: graphic watchdog enabled" rgroup.long 0x30++0x3 line.long 0x0 "GFXTIM_ISR,GFXTIM interrupt status register" bitfld.long 0x0 25. "WDGPF,watchdog pre-alarm flag" "0: no graphic watchdog pre-alarm occurred.,1: a graphic watchdog pre-alarm occurred." bitfld.long 0x0 24. "WDGAF,watchdog alarm flag" "0: no graphic watchdog alarm occurred.,1: a graphic watchdog alarm occurred." newline bitfld.long 0x0 19. "EV4F,event 4 flag" "0: no complex event 4 occurred.,1: a complex event 4 occurred." bitfld.long 0x0 18. "EV3F,event 3 flag" "0: no complex event 3 occurred.,1: a complex event 3 occurred." newline bitfld.long 0x0 17. "EV2F,event 2 flag" "0: no complex event 2 occurred.,1: a complex event 2 occurred." bitfld.long 0x0 16. "EV1F,event 1 flag" "0: No complex event 1 occurred.,1: Complex event 1 occurred." newline bitfld.long 0x0 13. "RFC2RF,relative frame counter 2 reload flag" "0: no reload occurred on relative frame counter 2.,1: a reload on relative frame counter 2 occurred." bitfld.long 0x0 12. "RFC1RF,relative frame counter 1 reload flag" "0: no reload occurred on relative frame counter 1.,1: a reload on relative frame counter 1 occurred." newline bitfld.long 0x0 9. "ALCC2F,absolute line counter compare 2 flag" "0: no match occurred on compare 2 of the absolute..,1: a match on compare 2 of the absolute line.." bitfld.long 0x0 8. "ALCC1F,absolute line counter compare 1 flag" "0: no match occurred on compare 1 of the absolute..,1: a match on compare 1 of the absolute line.." newline bitfld.long 0x0 4. "AFCC1F,absolute frame counter compare 1 flag" "0: no match occurred on compare 1 of the absolute..,1: a match on compare 1 of the absolute frame.." bitfld.long 0x0 2. "TEF,tearing-effect flag" "0: no tearing effect occurred.,1: a tearing effect occurred." newline bitfld.long 0x0 1. "ALCOF,absolute line counter overflow flag" "0: no overflow occurred on the absolute line counter.,1: a overflow on the absolute line counter occurred." bitfld.long 0x0 0. "AFCOF,absolute frame counter overflow flag" "0: no overflow occurred on the absolute frame..,1: a overflow on the absolute frame counter occurred." wgroup.long 0x34++0x3 line.long 0x0 "GFXTIM_ICR,GFXTIM interrupt clear register" bitfld.long 0x0 25. "CWDGPF,clear watchdog pre-alarm flag" "0: no effect,1: WDGPF cleared" bitfld.long 0x0 24. "CWDGAF,clear watchdog alarm flag" "0: no effect,1: WDGAF cleared" newline bitfld.long 0x0 19. "CEV4F,clear event 4 flag" "0: no effect,1: EV4F cleared" bitfld.long 0x0 18. "CEV3F,clear event 3 flag" "0: no effect,1: EV3F cleared" newline bitfld.long 0x0 17. "CEV2F,clear event 2 flag" "0: no effect,1: EV2F cleared" bitfld.long 0x0 16. "CEV1F,clear event 1 flag" "0: no effect,1: EV1F cleared" newline bitfld.long 0x0 13. "CRFC2RF,clear relative frame counter 2 reload flag" "0: no effect,1: RFC2RF cleared" bitfld.long 0x0 12. "CRFC1RF,clear relative frame counter 1 reload flag" "0: no effect,1: RFC1RF cleared" newline bitfld.long 0x0 9. "CALCC2F,clear absolute line counter compare 2 flag" "0: no effect,1: ALCC2F cleared" bitfld.long 0x0 8. "CALCC1F,clear absolute line counter compare 1 flag" "0: no effect,1: ALCC1F cleared" newline bitfld.long 0x0 4. "CAFCC1F,clear absolute frame counter compare 1 flag" "0: no effect,1: AFCC1F cleared" bitfld.long 0x0 2. "CTEF,clear tearing-effect flag" "0: no effect,1: TEF cleared" newline bitfld.long 0x0 1. "CALCOF,clear absolute line counter overflow flag" "0: no effect,1: ALCOF cleared" bitfld.long 0x0 0. "CAFCOF,clear absolute frame counter overflow flag" "0: no effect,1: AFCOF cleared" group.long 0x38++0x3 line.long 0x0 "GFXTIM_IER,GFXTIM interrupt enable register" bitfld.long 0x0 25. "WDGPIE,watchdog pre-alarm interrupt enable" "0: watchdog pre-alarm interrupt disabled,1: watchdog pre-alarm interrupt enabled" bitfld.long 0x0 24. "WDGAIE,watchdog alarm interrupt enable" "0: watchdog alarm interrupt disabled,1: watchdog alarm interrupt enabled" newline bitfld.long 0x0 19. "EV4IE,event 4 interrupt enable" "0: event 4 interrupt disabled,1: event 4 interrupt enabled" bitfld.long 0x0 18. "EV3IE,event 3 interrupt enable" "0: event 3 interrupt disabled,1: event 3 interrupt enabled" newline bitfld.long 0x0 17. "EV2IE,event 2 interrupt enable" "0: event 2 interrupt disabled,1: event 2 interrupt enabled" bitfld.long 0x0 16. "EV1IE,event 1 interrupt enable" "0: event 1 interrupt disabled,1: event 1 interrupt enabled" newline bitfld.long 0x0 13. "RFC2RIE,relative frame counter 2 reload interrupt enable" "0: relative frame counter 2 reload interrupt disabled,1: relative frame counter 2 reload interrupt enabled" bitfld.long 0x0 12. "RFC1RIE,relative frame counter 1 reload interrupt enable" "0: relative frame counter 1 reload interrupt disabled,1: relative frame counter 1 reload interrupt enabled" newline bitfld.long 0x0 9. "ALCC2IE,absolute line counter compare 2 interrupt enable" "0: absolute line counter compare 2 interrupt disabled,1: absolute line counter compare 2 interrupt enabled" bitfld.long 0x0 8. "ALCC1IE,absolute line counter compare 1 interrupt enable" "0: absolute line counter compare 1 interrupt disabled,1: absolute line counter compare 1 interrupt enabled" newline bitfld.long 0x0 4. "AFCC1IE,absolute frame counter compare 1 interrupt enable" "0: absolute frame counter compare 1 interrupt..,1: absolute frame counter compare 1 interrupt enabled" bitfld.long 0x0 2. "TEIE,tearing-effect interrupt enable" "0: tearing-effect interrupt disabled,1: tearing-effect interrupt enabled" newline bitfld.long 0x0 1. "ALCOIE,absolute line counter overflow interrupt enable" "0: absolute line counter overflow interrupt disabled,1: absolute line counter overflow interrupt enabled" bitfld.long 0x0 0. "AFCOIE,absolute frame counter overflow interrupt enable" "0: absolute frame counter overflow interrupt disabled,1: absolute frame counter overflow interrupt enabled" rgroup.long 0x3C++0x3 line.long 0x0 "GFXTIM_TSR,GFXTIM timers status register" bitfld.long 0x0 20. "RFC2S,relative frame counter 2 status" "0: relative frame counter 2 disabled,1: relative frame counter 2 enabled" bitfld.long 0x0 16. "RFC1S,relative frame counter 1 status" "0: relative frame counter 1 disabled,1: relative frame counter 1 enabled" newline bitfld.long 0x0 4. "ALCS,absolute line counter status" "0: absolute line counter disabled,1: absolute line counter enabled" bitfld.long 0x0 0. "AFCS,absolute frame counter status" "0: absolute frame counter disabled,1: absolute frame counter enabled" group.long 0x40++0x7 line.long 0x0 "GFXTIM_LCCRR,GFXTIM line clock counter reload register" hexmask.long.tbyte 0x0 0.--21. 1. "RELOAD,reload value" line.long 0x4 "GFXTIM_FCCRR,GFXTIM frame clock counter reload register" hexmask.long.word 0x4 0.--11. 1. "RELOAD,reload value" rgroup.long 0x50++0x3 line.long 0x0 "GFXTIM_ATR,GFXTIM absolute time register" hexmask.long.tbyte 0x0 12.--31. 1. "FRAME,fame number" hexmask.long.word 0x0 0.--11. 1. "LINE,line number" group.long 0x54++0x7 line.long 0x0 "GFXTIM_AFCR,GFXTIM absolute frame counter register" hexmask.long.tbyte 0x0 0.--19. 1. "FRAME,frame number" line.long 0x4 "GFXTIM_ALCR,GFXTIM absolute line counter register" hexmask.long.word 0x4 0.--11. 1. "LINE,line number" group.long 0x60++0x3 line.long 0x0 "GFXTIM_AFCC1R,GFXTIM absolute frame counter compare 1 register" hexmask.long.tbyte 0x0 0.--19. 1. "FRAME,frame number" group.long 0x70++0x7 line.long 0x0 "GFXTIM_ALCC1R,GFXTIM absolute line counter compare 1 register" hexmask.long.word 0x0 0.--11. 1. "LINE,line number" line.long 0x4 "GFXTIM_ALCC2R,GFXTIM absolute line counter compare 2 register" hexmask.long.word 0x4 0.--11. 1. "LINE,line number" rgroup.long 0x80++0x3 line.long 0x0 "GFXTIM_RFC1R,GFXTIM relative frame counter 1 register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame number" group.long 0x84++0x3 line.long 0x0 "GFXTIM_RFC1RR,GFXTIM relative frame counter 1 reload register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame reload value" rgroup.long 0x88++0x3 line.long 0x0 "GFXTIM_RFC2R,GFXTIM relative frame counter 2 register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame number" group.long 0x8C++0x3 line.long 0x0 "GFXTIM_RFC2RR,GFXTIM relative frame counter 2 reload register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame reload value" rgroup.long 0xA0++0x3 line.long 0x0 "GFXTIM_WDGCR,GFXTIM watchdog counter register" hexmask.long.word 0x0 0.--15. 1. "VALUE,value" group.long 0xA4++0x7 line.long 0x0 "GFXTIM_WDGRR,GFXTIM watchdog reload register" hexmask.long.word 0x0 0.--15. 1. "RELOAD,reload value" line.long 0x4 "GFXTIM_WDGPAR,GFXTIM watchdog pre-alarm register" hexmask.long.word 0x4 0.--15. 1. "PREALARM,pre-alarm value" tree.end tree "GFXTIM_S" base ad:0x58004000 group.long 0x0++0xB line.long 0x0 "GFXTIM_CR,GFXTIM configuration register" bitfld.long 0x0 17. "LCCOE,line-clock calibration output enable" "0: line-clock output disabled,1: line-clock output enabled" bitfld.long 0x0 16. "FCCOE,frame-clock calibration output enable" "0: frame-clock output disabled,1: frame-clock output enabled" newline bitfld.long 0x0 8.--9. "SYNCS,synchronization source" "0: gfxtim_hsync[0] and gfxtim_vsync[0] selected,1: gfxtim_hsync[1] and gfxtim_vsync[1] selected,2: gfxtim_hsync[2] and gfxtim_vsync[2] selected,3: gfxtim_hsync[3] and gfxtim_vsync[3] selected" bitfld.long 0x0 4. "TEPOL,tearing--effect polarity" "0: tearing effect active on rising edge,1: tearing effect active on falling edge" newline bitfld.long 0x0 0.--1. "TES,tearing source" "0: TE input pad selected,1: gfxtim_ite selected,2: HSYNC input selected by SYNCS[1:0],3: VSYNC input selected by SYNCS[1:0]" line.long 0x4 "GFXTIM_CGCR,GFXTIM clock generator configuration register" bitfld.long 0x4 28.--30. "FCCHRS,frame- -clock counter hardware reload source" "0: no hardware reload,1: line- -clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 24. "FCCFR,frame clock counter force reload" "0: No effect,1: frame clock counter reload forced" newline bitfld.long 0x4 20.--22. "FCCCS,frame clock counter clock source" "0: frame clock counter disabled,1: line clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 16.--18. "FCS,frame clock source" "0: line clock counter underflow,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" newline bitfld.long 0x4 12.--14. "LCCHRS,line clock counter hardware reload source" "0: no hardware reload,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" bitfld.long 0x4 8. "LCCFR,line clock counter force reload" "0: no effect,1: line clock counter reload forced" newline bitfld.long 0x4 4. "LCCCS,line clock counter clock source" "0: line clock counter disabled,1: system clock selected" bitfld.long 0x4 0.--2. "LCS,line clock source" "0: line clock counter underflow,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge" line.long 0x8 "GFXTIM_TCR,GFXTIM timers configuration register" bitfld.long 0x8 22. "FRFC2R,force relative frame counter 2 reload" "0: no effect,1: relative frame counter 2 reload forced" bitfld.long 0x8 21. "RFC2CM,relative frame counter 2 continuous mode" "0: relative frame counter 2 is one shot.,1: relative frame counter 2 is in continuous mode." newline bitfld.long 0x8 20. "RFC2EN,relative frame counter 2 enable" "0: no effect,1: relative frame counter 2 enabled" bitfld.long 0x8 18. "FRFC1R,force relative frame counter 1 reload" "0: no effect,1: relative frame counter 1 reload forced" newline bitfld.long 0x8 17. "RFC1CM,relative frame counter 1 continuous mode" "0: relative frame counter 1 is one shot.,1: relative frame counter 1 is in continuous mode." bitfld.long 0x8 16. "RFC1EN,relative frame counter 1 enable" "0: no effect,1: relative frame counter enabled" newline bitfld.long 0x8 5. "FALCR,force absolute line counter reset" "0: no effect,1: absolute line counter reset forced" bitfld.long 0x8 4. "ALCEN,absolute line counter enable" "0: no effect,1: absolute line counter enabled" newline bitfld.long 0x8 1. "FAFCR,force absolute frame counter reset" "0: no effect,1: absolute frame counter reset forced" bitfld.long 0x8 0. "AFCEN,absolute frame counter enable" "0: no effect,1: absolute frame counter enabled" wgroup.long 0xC++0x3 line.long 0x0 "GFXTIM_TDR,GFXTIM timers disable register" bitfld.long 0x0 20. "RFC2DIS,relative frame counter 2 disable" "0: no effect,1: relative frame counter 2 disabled" bitfld.long 0x0 16. "RFC1DIS,relative frame counter 1 disable" "0: no effect,1: relative frame counter 1 disabled" newline bitfld.long 0x0 4. "ALCDIS,absolute line counter disable" "0: no effect,1: absolute line counter disabled" bitfld.long 0x0 0. "AFCDIS,absolute frame counter disable" "0: no effect,1: absolute frame counter disabled" group.long 0x10++0x7 line.long 0x0 "GFXTIM_EVCR,GFXTIM events control register" bitfld.long 0x0 3. "EV4EN,event 4 enable" "0: event 4 generation disabled,1: event 4 generation enabled" bitfld.long 0x0 2. "EV3EN,event 3 enable" "0: event 3 generation disabled,1: event 3 generation enabled" newline bitfld.long 0x0 1. "EV2EN,event 2 enable" "0: event 2 generation disabled,1: event 2 generation enabled" bitfld.long 0x0 0. "EV1EN,event 1 enable" "0: event 1 generation disabled,1: event 1 generation enabled" line.long 0x4 "GFXTIM_EVSR,GFXTIM events selection register" bitfld.long 0x4 28.--30. "FES4,frame-event selection 4" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 24.--26. "LES4,line-event selection 4" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 20.--22. "FES3,frame-event selection 3" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 16.--18. "LES3,line-event selection 3" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 12.--14. "FES2,frame-event selection 2" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 8.--10. "LES2,line-event selection 2" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" newline bitfld.long 0x4 4.--6. "FES1,frame-event selection 1" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?" bitfld.long 0x4 0.--2. "LES1,line-event selection 1" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?" group.long 0x20++0x3 line.long 0x0 "GFXTIM_WDGTCR,GFXTIM watchdog timer configuration register" bitfld.long 0x0 16. "FWDGR,force watchdog reload" "0: no effect,1: graphic watchdog reload forced" hexmask.long.byte 0x0 8.--11. 1. "WDGCS,watchdog clock source" newline bitfld.long 0x0 4.--5. "WDGHRC,watchdog hardware reload configuration" "0: watchdog hardware reload disabled,1: watchdog reloaded a rising edge of gfxtim_wrld,2: watchdog reloaded a falling edge of gfxtim_wrld,?" rbitfld.long 0x0 2. "WDGS,watchdog status" "0: graphic watchdog disabled,1: graphic watchdog enabled" newline bitfld.long 0x0 1. "WDGDIS,watchdog disable" "0: no effect,1: graphic watchdog disabled" bitfld.long 0x0 0. "WDGEN,watchdog enable" "0: no effect,1: graphic watchdog enabled" rgroup.long 0x30++0x3 line.long 0x0 "GFXTIM_ISR,GFXTIM interrupt status register" bitfld.long 0x0 25. "WDGPF,watchdog pre-alarm flag" "0: no graphic watchdog pre-alarm occurred.,1: a graphic watchdog pre-alarm occurred." bitfld.long 0x0 24. "WDGAF,watchdog alarm flag" "0: no graphic watchdog alarm occurred.,1: a graphic watchdog alarm occurred." newline bitfld.long 0x0 19. "EV4F,event 4 flag" "0: no complex event 4 occurred.,1: a complex event 4 occurred." bitfld.long 0x0 18. "EV3F,event 3 flag" "0: no complex event 3 occurred.,1: a complex event 3 occurred." newline bitfld.long 0x0 17. "EV2F,event 2 flag" "0: no complex event 2 occurred.,1: a complex event 2 occurred." bitfld.long 0x0 16. "EV1F,event 1 flag" "0: No complex event 1 occurred.,1: Complex event 1 occurred." newline bitfld.long 0x0 13. "RFC2RF,relative frame counter 2 reload flag" "0: no reload occurred on relative frame counter 2.,1: a reload on relative frame counter 2 occurred." bitfld.long 0x0 12. "RFC1RF,relative frame counter 1 reload flag" "0: no reload occurred on relative frame counter 1.,1: a reload on relative frame counter 1 occurred." newline bitfld.long 0x0 9. "ALCC2F,absolute line counter compare 2 flag" "0: no match occurred on compare 2 of the absolute..,1: a match on compare 2 of the absolute line.." bitfld.long 0x0 8. "ALCC1F,absolute line counter compare 1 flag" "0: no match occurred on compare 1 of the absolute..,1: a match on compare 1 of the absolute line.." newline bitfld.long 0x0 4. "AFCC1F,absolute frame counter compare 1 flag" "0: no match occurred on compare 1 of the absolute..,1: a match on compare 1 of the absolute frame.." bitfld.long 0x0 2. "TEF,tearing-effect flag" "0: no tearing effect occurred.,1: a tearing effect occurred." newline bitfld.long 0x0 1. "ALCOF,absolute line counter overflow flag" "0: no overflow occurred on the absolute line counter.,1: a overflow on the absolute line counter occurred." bitfld.long 0x0 0. "AFCOF,absolute frame counter overflow flag" "0: no overflow occurred on the absolute frame..,1: a overflow on the absolute frame counter occurred." wgroup.long 0x34++0x3 line.long 0x0 "GFXTIM_ICR,GFXTIM interrupt clear register" bitfld.long 0x0 25. "CWDGPF,clear watchdog pre-alarm flag" "0: no effect,1: WDGPF cleared" bitfld.long 0x0 24. "CWDGAF,clear watchdog alarm flag" "0: no effect,1: WDGAF cleared" newline bitfld.long 0x0 19. "CEV4F,clear event 4 flag" "0: no effect,1: EV4F cleared" bitfld.long 0x0 18. "CEV3F,clear event 3 flag" "0: no effect,1: EV3F cleared" newline bitfld.long 0x0 17. "CEV2F,clear event 2 flag" "0: no effect,1: EV2F cleared" bitfld.long 0x0 16. "CEV1F,clear event 1 flag" "0: no effect,1: EV1F cleared" newline bitfld.long 0x0 13. "CRFC2RF,clear relative frame counter 2 reload flag" "0: no effect,1: RFC2RF cleared" bitfld.long 0x0 12. "CRFC1RF,clear relative frame counter 1 reload flag" "0: no effect,1: RFC1RF cleared" newline bitfld.long 0x0 9. "CALCC2F,clear absolute line counter compare 2 flag" "0: no effect,1: ALCC2F cleared" bitfld.long 0x0 8. "CALCC1F,clear absolute line counter compare 1 flag" "0: no effect,1: ALCC1F cleared" newline bitfld.long 0x0 4. "CAFCC1F,clear absolute frame counter compare 1 flag" "0: no effect,1: AFCC1F cleared" bitfld.long 0x0 2. "CTEF,clear tearing-effect flag" "0: no effect,1: TEF cleared" newline bitfld.long 0x0 1. "CALCOF,clear absolute line counter overflow flag" "0: no effect,1: ALCOF cleared" bitfld.long 0x0 0. "CAFCOF,clear absolute frame counter overflow flag" "0: no effect,1: AFCOF cleared" group.long 0x38++0x3 line.long 0x0 "GFXTIM_IER,GFXTIM interrupt enable register" bitfld.long 0x0 25. "WDGPIE,watchdog pre-alarm interrupt enable" "0: watchdog pre-alarm interrupt disabled,1: watchdog pre-alarm interrupt enabled" bitfld.long 0x0 24. "WDGAIE,watchdog alarm interrupt enable" "0: watchdog alarm interrupt disabled,1: watchdog alarm interrupt enabled" newline bitfld.long 0x0 19. "EV4IE,event 4 interrupt enable" "0: event 4 interrupt disabled,1: event 4 interrupt enabled" bitfld.long 0x0 18. "EV3IE,event 3 interrupt enable" "0: event 3 interrupt disabled,1: event 3 interrupt enabled" newline bitfld.long 0x0 17. "EV2IE,event 2 interrupt enable" "0: event 2 interrupt disabled,1: event 2 interrupt enabled" bitfld.long 0x0 16. "EV1IE,event 1 interrupt enable" "0: event 1 interrupt disabled,1: event 1 interrupt enabled" newline bitfld.long 0x0 13. "RFC2RIE,relative frame counter 2 reload interrupt enable" "0: relative frame counter 2 reload interrupt disabled,1: relative frame counter 2 reload interrupt enabled" bitfld.long 0x0 12. "RFC1RIE,relative frame counter 1 reload interrupt enable" "0: relative frame counter 1 reload interrupt disabled,1: relative frame counter 1 reload interrupt enabled" newline bitfld.long 0x0 9. "ALCC2IE,absolute line counter compare 2 interrupt enable" "0: absolute line counter compare 2 interrupt disabled,1: absolute line counter compare 2 interrupt enabled" bitfld.long 0x0 8. "ALCC1IE,absolute line counter compare 1 interrupt enable" "0: absolute line counter compare 1 interrupt disabled,1: absolute line counter compare 1 interrupt enabled" newline bitfld.long 0x0 4. "AFCC1IE,absolute frame counter compare 1 interrupt enable" "0: absolute frame counter compare 1 interrupt..,1: absolute frame counter compare 1 interrupt enabled" bitfld.long 0x0 2. "TEIE,tearing-effect interrupt enable" "0: tearing-effect interrupt disabled,1: tearing-effect interrupt enabled" newline bitfld.long 0x0 1. "ALCOIE,absolute line counter overflow interrupt enable" "0: absolute line counter overflow interrupt disabled,1: absolute line counter overflow interrupt enabled" bitfld.long 0x0 0. "AFCOIE,absolute frame counter overflow interrupt enable" "0: absolute frame counter overflow interrupt disabled,1: absolute frame counter overflow interrupt enabled" rgroup.long 0x3C++0x3 line.long 0x0 "GFXTIM_TSR,GFXTIM timers status register" bitfld.long 0x0 20. "RFC2S,relative frame counter 2 status" "0: relative frame counter 2 disabled,1: relative frame counter 2 enabled" bitfld.long 0x0 16. "RFC1S,relative frame counter 1 status" "0: relative frame counter 1 disabled,1: relative frame counter 1 enabled" newline bitfld.long 0x0 4. "ALCS,absolute line counter status" "0: absolute line counter disabled,1: absolute line counter enabled" bitfld.long 0x0 0. "AFCS,absolute frame counter status" "0: absolute frame counter disabled,1: absolute frame counter enabled" group.long 0x40++0x7 line.long 0x0 "GFXTIM_LCCRR,GFXTIM line clock counter reload register" hexmask.long.tbyte 0x0 0.--21. 1. "RELOAD,reload value" line.long 0x4 "GFXTIM_FCCRR,GFXTIM frame clock counter reload register" hexmask.long.word 0x4 0.--11. 1. "RELOAD,reload value" rgroup.long 0x50++0x3 line.long 0x0 "GFXTIM_ATR,GFXTIM absolute time register" hexmask.long.tbyte 0x0 12.--31. 1. "FRAME,fame number" hexmask.long.word 0x0 0.--11. 1. "LINE,line number" group.long 0x54++0x7 line.long 0x0 "GFXTIM_AFCR,GFXTIM absolute frame counter register" hexmask.long.tbyte 0x0 0.--19. 1. "FRAME,frame number" line.long 0x4 "GFXTIM_ALCR,GFXTIM absolute line counter register" hexmask.long.word 0x4 0.--11. 1. "LINE,line number" group.long 0x60++0x3 line.long 0x0 "GFXTIM_AFCC1R,GFXTIM absolute frame counter compare 1 register" hexmask.long.tbyte 0x0 0.--19. 1. "FRAME,frame number" group.long 0x70++0x7 line.long 0x0 "GFXTIM_ALCC1R,GFXTIM absolute line counter compare 1 register" hexmask.long.word 0x0 0.--11. 1. "LINE,line number" line.long 0x4 "GFXTIM_ALCC2R,GFXTIM absolute line counter compare 2 register" hexmask.long.word 0x4 0.--11. 1. "LINE,line number" rgroup.long 0x80++0x3 line.long 0x0 "GFXTIM_RFC1R,GFXTIM relative frame counter 1 register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame number" group.long 0x84++0x3 line.long 0x0 "GFXTIM_RFC1RR,GFXTIM relative frame counter 1 reload register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame reload value" rgroup.long 0x88++0x3 line.long 0x0 "GFXTIM_RFC2R,GFXTIM relative frame counter 2 register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame number" group.long 0x8C++0x3 line.long 0x0 "GFXTIM_RFC2RR,GFXTIM relative frame counter 2 reload register" hexmask.long.word 0x0 0.--11. 1. "FRAME,frame reload value" rgroup.long 0xA0++0x3 line.long 0x0 "GFXTIM_WDGCR,GFXTIM watchdog counter register" hexmask.long.word 0x0 0.--15. 1. "VALUE,value" group.long 0xA4++0x7 line.long 0x0 "GFXTIM_WDGRR,GFXTIM watchdog reload register" hexmask.long.word 0x0 0.--15. 1. "RELOAD,reload value" line.long 0x4 "GFXTIM_WDGPAR,GFXTIM watchdog pre-alarm register" hexmask.long.word 0x4 0.--15. 1. "PREALARM,pre-alarm value" tree.end tree.end tree "GPDMA (General Purpose Direct Memory Access Controller)" base ad:0x0 sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "GPDMA" base ad:0x40021000 group.long 0x0++0xB line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "GPDMA_RCFGLOCKR,GPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 14. "LOCK14,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 12. "LOCK12,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 10. "LOCK10,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 8. "LOCK8,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 6. "LOCK6,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 4. "LOCK4,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 2. "LOCK2,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 0. "LOCK0,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." rgroup.long 0xC++0x7 line.long 0x0 "GPDMA_MISR,GPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "GPDMA_SMISR,GPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,GPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,GPDMA channel 0 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,GPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C0TR2,GPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C0BR1,GPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C1LBAR,GPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,GPDMA channel 1 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,GPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C1TR2,GPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C1BR1,GPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C2LBAR,GPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,GPDMA channel 2 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,GPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C2TR2,GPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C2BR1,GPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C3LBAR,GPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,GPDMA channel 3 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,GPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "GPDMA_C3TR1,GPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C3TR2,GPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C3BR1,GPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C3SAR,GPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C3DAR,GPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x7 line.long 0x0 "GPDMA_C3LLR,GPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C4LBAR,GPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,GPDMA channel 4 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,GPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "GPDMA_C4TR1,GPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C4TR2,GPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C4BR1,GPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C4SAR,GPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C4DAR,GPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0x7 line.long 0x0 "GPDMA_C4LLR,GPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C5LBAR,GPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,GPDMA channel 5 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,GPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "GPDMA_C5TR1,GPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C5TR2,GPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C5BR1,GPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C5SAR,GPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C5DAR,GPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0x7 line.long 0x0 "GPDMA_C5LLR,GPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C6LBAR,GPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,GPDMA channel 6 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,GPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "GPDMA_C6TR1,GPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C6TR2,GPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C6BR1,GPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C6SAR,GPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C6DAR,GPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0x7 line.long 0x0 "GPDMA_C6LLR,GPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C7LBAR,GPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,GPDMA channel 7 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,GPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "GPDMA_C7TR1,GPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C7TR2,GPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C7BR1,GPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C7SAR,GPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C7DAR,GPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0x7 line.long 0x0 "GPDMA_C7LLR,GPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C8LBAR,GPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,GPDMA channel 8 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,GPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "GPDMA_C8TR1,GPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C8TR2,GPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C8BR1,GPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C8SAR,GPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C8DAR,GPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0x7 line.long 0x0 "GPDMA_C8LLR,GPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C9LBAR,GPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,GPDMA channel 9 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,GPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "GPDMA_C9TR1,GPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C9TR2,GPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C9BR1,GPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C9SAR,GPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C9DAR,GPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0x7 line.long 0x0 "GPDMA_C9LLR,GPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C10LBAR,GPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,GPDMA channel 10 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,GPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "GPDMA_C10TR1,GPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C10TR2,GPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C10BR1,GPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C10SAR,GPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C10DAR,GPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0x7 line.long 0x0 "GPDMA_C10LLR,GPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C11LBAR,GPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,GPDMA channel 11 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,GPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "GPDMA_C11TR1,GPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C11TR2,GPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C11BR1,GPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C11SAR,GPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C11DAR,GPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0x7 line.long 0x0 "GPDMA_C11LLR,GPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C12LBAR,GPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,GPDMA channel 12 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,GPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "GPDMA_C12TR1,GPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C12TR2,GPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C12BR1,GPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C12SAR,GPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C12DAR,GPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C12TR3,GPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C12BR2,GPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0x7 line.long 0x0 "GPDMA_C12LLR,GPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C13LBAR,GPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,GPDMA channel 13 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,GPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "GPDMA_C13TR1,GPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C13TR2,GPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C13BR1,GPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C13SAR,GPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C13DAR,GPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C13TR3,GPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C13BR2,GPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0x7 line.long 0x0 "GPDMA_C13LLR,GPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C14LBAR,GPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,GPDMA channel 14 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,GPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "GPDMA_C14TR1,GPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C14TR2,GPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C14BR1,GPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C14SAR,GPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C14DAR,GPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C14TR3,GPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C14BR2,GPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0x7 line.long 0x0 "GPDMA_C14LLR,GPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C15LBAR,GPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,GPDMA channel 15 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,GPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "GPDMA_C15TR1,GPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C15TR2,GPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C15BR1,GPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C15SAR,GPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C15DAR,GPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C15TR3,GPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C15BR2,GPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32N655*")) tree "GPDMA" base ad:0x40021000 group.long 0x0++0xB line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "GPDMA_RCFGLOCKR,GPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 14. "LOCK14,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 12. "LOCK12,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 10. "LOCK10,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 8. "LOCK8,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 6. "LOCK6,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 4. "LOCK4,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 2. "LOCK2,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 0. "LOCK0,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." rgroup.long 0xC++0x7 line.long 0x0 "GPDMA_MISR,GPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "GPDMA_SMISR,GPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,GPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,GPDMA channel 0 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,GPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C0TR2,GPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C0BR1,GPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C1LBAR,GPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,GPDMA channel 1 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,GPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C1TR2,GPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C1BR1,GPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C2LBAR,GPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,GPDMA channel 2 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,GPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C2TR2,GPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C2BR1,GPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C3LBAR,GPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,GPDMA channel 3 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,GPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "GPDMA_C3TR1,GPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C3TR2,GPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C3BR1,GPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C3SAR,GPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C3DAR,GPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x7 line.long 0x0 "GPDMA_C3LLR,GPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C4LBAR,GPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,GPDMA channel 4 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,GPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "GPDMA_C4TR1,GPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C4TR2,GPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C4BR1,GPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C4SAR,GPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C4DAR,GPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0x7 line.long 0x0 "GPDMA_C4LLR,GPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C5LBAR,GPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,GPDMA channel 5 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,GPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "GPDMA_C5TR1,GPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C5TR2,GPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C5BR1,GPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C5SAR,GPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C5DAR,GPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0x7 line.long 0x0 "GPDMA_C5LLR,GPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C6LBAR,GPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,GPDMA channel 6 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,GPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "GPDMA_C6TR1,GPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C6TR2,GPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C6BR1,GPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C6SAR,GPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C6DAR,GPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0x7 line.long 0x0 "GPDMA_C6LLR,GPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C7LBAR,GPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,GPDMA channel 7 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,GPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "GPDMA_C7TR1,GPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C7TR2,GPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C7BR1,GPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C7SAR,GPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C7DAR,GPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0x7 line.long 0x0 "GPDMA_C7LLR,GPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C8LBAR,GPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,GPDMA channel 8 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,GPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "GPDMA_C8TR1,GPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C8TR2,GPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C8BR1,GPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C8SAR,GPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C8DAR,GPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0x7 line.long 0x0 "GPDMA_C8LLR,GPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C9LBAR,GPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,GPDMA channel 9 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,GPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "GPDMA_C9TR1,GPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C9TR2,GPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C9BR1,GPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C9SAR,GPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C9DAR,GPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0x7 line.long 0x0 "GPDMA_C9LLR,GPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C10LBAR,GPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,GPDMA channel 10 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,GPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "GPDMA_C10TR1,GPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C10TR2,GPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C10BR1,GPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C10SAR,GPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C10DAR,GPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0x7 line.long 0x0 "GPDMA_C10LLR,GPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C11LBAR,GPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,GPDMA channel 11 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,GPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "GPDMA_C11TR1,GPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C11TR2,GPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C11BR1,GPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C11SAR,GPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C11DAR,GPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0x7 line.long 0x0 "GPDMA_C11LLR,GPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C12LBAR,GPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,GPDMA channel 12 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,GPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "GPDMA_C12TR1,GPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C12TR2,GPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C12BR1,GPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C12SAR,GPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C12DAR,GPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C12TR3,GPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C12BR2,GPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0x7 line.long 0x0 "GPDMA_C12LLR,GPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C13LBAR,GPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,GPDMA channel 13 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,GPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "GPDMA_C13TR1,GPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C13TR2,GPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C13BR1,GPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C13SAR,GPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C13DAR,GPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C13TR3,GPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C13BR2,GPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0x7 line.long 0x0 "GPDMA_C13LLR,GPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C14LBAR,GPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,GPDMA channel 14 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,GPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "GPDMA_C14TR1,GPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C14TR2,GPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C14BR1,GPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C14SAR,GPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C14DAR,GPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C14TR3,GPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C14BR2,GPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0x7 line.long 0x0 "GPDMA_C14LLR,GPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C15LBAR,GPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,GPDMA channel 15 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,GPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "GPDMA_C15TR1,GPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C15TR2,GPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C15BR1,GPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C15SAR,GPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C15DAR,GPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C15TR3,GPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C15BR2,GPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32N657*")) tree "GPDMA" base ad:0x40021000 group.long 0x0++0xB line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "GPDMA_RCFGLOCKR,GPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 14. "LOCK14,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 12. "LOCK12,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 10. "LOCK10,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 8. "LOCK8,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 6. "LOCK6,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 4. "LOCK4,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 2. "LOCK2,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 0. "LOCK0,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." rgroup.long 0xC++0x7 line.long 0x0 "GPDMA_MISR,GPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "GPDMA_SMISR,GPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,GPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,GPDMA channel 0 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,GPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C0TR2,GPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C0BR1,GPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C1LBAR,GPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,GPDMA channel 1 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,GPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C1TR2,GPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C1BR1,GPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C2LBAR,GPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,GPDMA channel 2 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,GPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C2TR2,GPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C2BR1,GPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C3LBAR,GPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,GPDMA channel 3 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,GPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "GPDMA_C3TR1,GPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C3TR2,GPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C3BR1,GPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C3SAR,GPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C3DAR,GPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x7 line.long 0x0 "GPDMA_C3LLR,GPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C4LBAR,GPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,GPDMA channel 4 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,GPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "GPDMA_C4TR1,GPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C4TR2,GPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C4BR1,GPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C4SAR,GPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C4DAR,GPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0x7 line.long 0x0 "GPDMA_C4LLR,GPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C5LBAR,GPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,GPDMA channel 5 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,GPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "GPDMA_C5TR1,GPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C5TR2,GPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C5BR1,GPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C5SAR,GPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C5DAR,GPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0x7 line.long 0x0 "GPDMA_C5LLR,GPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C6LBAR,GPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,GPDMA channel 6 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,GPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "GPDMA_C6TR1,GPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C6TR2,GPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C6BR1,GPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C6SAR,GPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C6DAR,GPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0x7 line.long 0x0 "GPDMA_C6LLR,GPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C7LBAR,GPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,GPDMA channel 7 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,GPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "GPDMA_C7TR1,GPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C7TR2,GPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C7BR1,GPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C7SAR,GPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C7DAR,GPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0x7 line.long 0x0 "GPDMA_C7LLR,GPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C8LBAR,GPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,GPDMA channel 8 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,GPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "GPDMA_C8TR1,GPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C8TR2,GPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C8BR1,GPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C8SAR,GPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C8DAR,GPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0x7 line.long 0x0 "GPDMA_C8LLR,GPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C9LBAR,GPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,GPDMA channel 9 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,GPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "GPDMA_C9TR1,GPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C9TR2,GPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C9BR1,GPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C9SAR,GPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C9DAR,GPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0x7 line.long 0x0 "GPDMA_C9LLR,GPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C10LBAR,GPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,GPDMA channel 10 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,GPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "GPDMA_C10TR1,GPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C10TR2,GPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C10BR1,GPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C10SAR,GPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C10DAR,GPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0x7 line.long 0x0 "GPDMA_C10LLR,GPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C11LBAR,GPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,GPDMA channel 11 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,GPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "GPDMA_C11TR1,GPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C11TR2,GPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C11BR1,GPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C11SAR,GPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C11DAR,GPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0x7 line.long 0x0 "GPDMA_C11LLR,GPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C12LBAR,GPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,GPDMA channel 12 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,GPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "GPDMA_C12TR1,GPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C12TR2,GPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C12BR1,GPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C12SAR,GPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C12DAR,GPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C12TR3,GPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C12BR2,GPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0x7 line.long 0x0 "GPDMA_C12LLR,GPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C13LBAR,GPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,GPDMA channel 13 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,GPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "GPDMA_C13TR1,GPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C13TR2,GPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C13BR1,GPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C13SAR,GPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C13DAR,GPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C13TR3,GPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C13BR2,GPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0x7 line.long 0x0 "GPDMA_C13LLR,GPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C14LBAR,GPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,GPDMA channel 14 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,GPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "GPDMA_C14TR1,GPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C14TR2,GPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C14BR1,GPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C14SAR,GPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C14DAR,GPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C14TR3,GPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C14BR2,GPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0x7 line.long 0x0 "GPDMA_C14LLR,GPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C15LBAR,GPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,GPDMA channel 15 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,GPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "GPDMA_C15TR1,GPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C15TR2,GPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C15BR1,GPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C15SAR,GPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C15DAR,GPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C15TR3,GPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C15BR2,GPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "GPDMA_S" base ad:0x50021000 group.long 0x0++0xB line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "GPDMA_RCFGLOCKR,GPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 14. "LOCK14,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 12. "LOCK12,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 10. "LOCK10,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 8. "LOCK8,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 6. "LOCK6,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 4. "LOCK4,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 2. "LOCK2,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 0. "LOCK0,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." rgroup.long 0xC++0x7 line.long 0x0 "GPDMA_MISR,GPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "GPDMA_SMISR,GPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,GPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,GPDMA channel 0 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,GPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C0TR2,GPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C0BR1,GPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C1LBAR,GPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,GPDMA channel 1 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,GPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C1TR2,GPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C1BR1,GPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C2LBAR,GPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,GPDMA channel 2 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,GPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C2TR2,GPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C2BR1,GPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C3LBAR,GPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,GPDMA channel 3 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,GPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "GPDMA_C3TR1,GPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C3TR2,GPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C3BR1,GPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C3SAR,GPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C3DAR,GPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x7 line.long 0x0 "GPDMA_C3LLR,GPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C4LBAR,GPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,GPDMA channel 4 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,GPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "GPDMA_C4TR1,GPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C4TR2,GPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C4BR1,GPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C4SAR,GPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C4DAR,GPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0x7 line.long 0x0 "GPDMA_C4LLR,GPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C5LBAR,GPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,GPDMA channel 5 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,GPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "GPDMA_C5TR1,GPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C5TR2,GPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C5BR1,GPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C5SAR,GPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C5DAR,GPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0x7 line.long 0x0 "GPDMA_C5LLR,GPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C6LBAR,GPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,GPDMA channel 6 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,GPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "GPDMA_C6TR1,GPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C6TR2,GPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C6BR1,GPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C6SAR,GPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C6DAR,GPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0x7 line.long 0x0 "GPDMA_C6LLR,GPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C7LBAR,GPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,GPDMA channel 7 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,GPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "GPDMA_C7TR1,GPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C7TR2,GPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C7BR1,GPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C7SAR,GPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C7DAR,GPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0x7 line.long 0x0 "GPDMA_C7LLR,GPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C8LBAR,GPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,GPDMA channel 8 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,GPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "GPDMA_C8TR1,GPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C8TR2,GPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C8BR1,GPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C8SAR,GPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C8DAR,GPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0x7 line.long 0x0 "GPDMA_C8LLR,GPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C9LBAR,GPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,GPDMA channel 9 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,GPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "GPDMA_C9TR1,GPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C9TR2,GPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C9BR1,GPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C9SAR,GPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C9DAR,GPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0x7 line.long 0x0 "GPDMA_C9LLR,GPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C10LBAR,GPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,GPDMA channel 10 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,GPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "GPDMA_C10TR1,GPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C10TR2,GPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C10BR1,GPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C10SAR,GPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C10DAR,GPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0x7 line.long 0x0 "GPDMA_C10LLR,GPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C11LBAR,GPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,GPDMA channel 11 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,GPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "GPDMA_C11TR1,GPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C11TR2,GPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C11BR1,GPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C11SAR,GPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C11DAR,GPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0x7 line.long 0x0 "GPDMA_C11LLR,GPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C12LBAR,GPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,GPDMA channel 12 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,GPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "GPDMA_C12TR1,GPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C12TR2,GPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C12BR1,GPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C12SAR,GPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C12DAR,GPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C12TR3,GPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C12BR2,GPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0x7 line.long 0x0 "GPDMA_C12LLR,GPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C13LBAR,GPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,GPDMA channel 13 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,GPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "GPDMA_C13TR1,GPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C13TR2,GPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C13BR1,GPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C13SAR,GPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C13DAR,GPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C13TR3,GPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C13BR2,GPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0x7 line.long 0x0 "GPDMA_C13LLR,GPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C14LBAR,GPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,GPDMA channel 14 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,GPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "GPDMA_C14TR1,GPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C14TR2,GPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C14BR1,GPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C14SAR,GPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C14DAR,GPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C14TR3,GPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C14BR2,GPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0x7 line.long 0x0 "GPDMA_C14LLR,GPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C15LBAR,GPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,GPDMA channel 15 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,GPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "GPDMA_C15TR1,GPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C15TR2,GPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C15BR1,GPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C15SAR,GPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C15DAR,GPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C15TR3,GPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C15BR2,GPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32N655*")) tree "GPDMA_S" base ad:0x50021000 group.long 0x0++0xB line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "GPDMA_RCFGLOCKR,GPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 14. "LOCK14,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 12. "LOCK12,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 10. "LOCK10,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 8. "LOCK8,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 6. "LOCK6,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 4. "LOCK4,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 2. "LOCK2,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 0. "LOCK0,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." rgroup.long 0xC++0x7 line.long 0x0 "GPDMA_MISR,GPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "GPDMA_SMISR,GPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,GPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,GPDMA channel 0 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,GPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C0TR2,GPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C0BR1,GPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C1LBAR,GPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,GPDMA channel 1 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,GPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C1TR2,GPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C1BR1,GPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C2LBAR,GPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,GPDMA channel 2 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,GPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C2TR2,GPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C2BR1,GPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C3LBAR,GPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,GPDMA channel 3 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,GPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "GPDMA_C3TR1,GPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C3TR2,GPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C3BR1,GPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C3SAR,GPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C3DAR,GPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x7 line.long 0x0 "GPDMA_C3LLR,GPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C4LBAR,GPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,GPDMA channel 4 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,GPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "GPDMA_C4TR1,GPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C4TR2,GPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C4BR1,GPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C4SAR,GPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C4DAR,GPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0x7 line.long 0x0 "GPDMA_C4LLR,GPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C5LBAR,GPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,GPDMA channel 5 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,GPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "GPDMA_C5TR1,GPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C5TR2,GPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C5BR1,GPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C5SAR,GPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C5DAR,GPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0x7 line.long 0x0 "GPDMA_C5LLR,GPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C6LBAR,GPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,GPDMA channel 6 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,GPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "GPDMA_C6TR1,GPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C6TR2,GPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C6BR1,GPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C6SAR,GPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C6DAR,GPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0x7 line.long 0x0 "GPDMA_C6LLR,GPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C7LBAR,GPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,GPDMA channel 7 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,GPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "GPDMA_C7TR1,GPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C7TR2,GPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C7BR1,GPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C7SAR,GPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C7DAR,GPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0x7 line.long 0x0 "GPDMA_C7LLR,GPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C8LBAR,GPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,GPDMA channel 8 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,GPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "GPDMA_C8TR1,GPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C8TR2,GPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C8BR1,GPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C8SAR,GPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C8DAR,GPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0x7 line.long 0x0 "GPDMA_C8LLR,GPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C9LBAR,GPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,GPDMA channel 9 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,GPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "GPDMA_C9TR1,GPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C9TR2,GPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C9BR1,GPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C9SAR,GPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C9DAR,GPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0x7 line.long 0x0 "GPDMA_C9LLR,GPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C10LBAR,GPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,GPDMA channel 10 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,GPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "GPDMA_C10TR1,GPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C10TR2,GPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C10BR1,GPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C10SAR,GPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C10DAR,GPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0x7 line.long 0x0 "GPDMA_C10LLR,GPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C11LBAR,GPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,GPDMA channel 11 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,GPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "GPDMA_C11TR1,GPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C11TR2,GPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C11BR1,GPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C11SAR,GPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C11DAR,GPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0x7 line.long 0x0 "GPDMA_C11LLR,GPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C12LBAR,GPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,GPDMA channel 12 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,GPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "GPDMA_C12TR1,GPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C12TR2,GPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C12BR1,GPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C12SAR,GPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C12DAR,GPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C12TR3,GPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C12BR2,GPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0x7 line.long 0x0 "GPDMA_C12LLR,GPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C13LBAR,GPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,GPDMA channel 13 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,GPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "GPDMA_C13TR1,GPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C13TR2,GPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C13BR1,GPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C13SAR,GPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C13DAR,GPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C13TR3,GPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C13BR2,GPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0x7 line.long 0x0 "GPDMA_C13LLR,GPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C14LBAR,GPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,GPDMA channel 14 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,GPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "GPDMA_C14TR1,GPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C14TR2,GPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C14BR1,GPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C14SAR,GPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C14DAR,GPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C14TR3,GPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C14BR2,GPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0x7 line.long 0x0 "GPDMA_C14LLR,GPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C15LBAR,GPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,GPDMA channel 15 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,GPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "GPDMA_C15TR1,GPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C15TR2,GPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C15BR1,GPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C15SAR,GPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C15DAR,GPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C15TR3,GPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C15BR2,GPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32N657*")) tree "GPDMA_S" base ad:0x50021000 group.long 0x0++0xB line.long 0x0 "GPDMA_SECCFGR,GPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "GPDMA_PRIVCFGR,GPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "GPDMA_RCFGLOCKR,GPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 14. "LOCK14,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 12. "LOCK12,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 10. "LOCK10,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 8. "LOCK8,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 6. "LOCK6,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 4. "LOCK4,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 2. "LOCK2,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." bitfld.long 0x8 0. "LOCK0,lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: secure privilege configuration of the channel x..,1: secure privilege configuration of the channel x.." rgroup.long 0xC++0x7 line.long 0x0 "GPDMA_MISR,GPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "GPDMA_SMISR,GPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0x3 line.long 0x0 "GPDMA_C0LBAR,GPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5C++0x3 line.long 0x0 "GPDMA_C0FCR,GPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "GPDMA_C0SR,GPDMA channel 0 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "GPDMA_C0CR,GPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "GPDMA_C0TR1,GPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C0TR2,GPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C0BR1,GPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C0SAR,GPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C0DAR,GPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0x7 line.long 0x0 "GPDMA_C0LLR,GPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C1LBAR,GPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0xDC++0x3 line.long 0x0 "GPDMA_C1FCR,GPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "GPDMA_C1SR,GPDMA channel 1 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "GPDMA_C1CR,GPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "GPDMA_C1TR1,GPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C1TR2,GPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C1BR1,GPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C1SAR,GPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C1DAR,GPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0x7 line.long 0x0 "GPDMA_C1LLR,GPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C2LBAR,GPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x15C++0x3 line.long 0x0 "GPDMA_C2FCR,GPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "GPDMA_C2SR,GPDMA channel 2 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "GPDMA_C2CR,GPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "GPDMA_C2TR1,GPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C2TR2,GPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C2BR1,GPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C2SAR,GPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C2DAR,GPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0x7 line.long 0x0 "GPDMA_C2LLR,GPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C3LBAR,GPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x1DC++0x3 line.long 0x0 "GPDMA_C3FCR,GPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "GPDMA_C3SR,GPDMA channel 3 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "GPDMA_C3CR,GPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "GPDMA_C3TR1,GPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C3TR2,GPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C3BR1,GPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C3SAR,GPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C3DAR,GPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0x7 line.long 0x0 "GPDMA_C3LLR,GPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C4LBAR,GPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x25C++0x3 line.long 0x0 "GPDMA_C4FCR,GPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "GPDMA_C4SR,GPDMA channel 4 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "GPDMA_C4CR,GPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "GPDMA_C4TR1,GPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C4TR2,GPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C4BR1,GPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C4SAR,GPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C4DAR,GPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0x7 line.long 0x0 "GPDMA_C4LLR,GPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C5LBAR,GPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x2DC++0x3 line.long 0x0 "GPDMA_C5FCR,GPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "GPDMA_C5SR,GPDMA channel 5 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "GPDMA_C5CR,GPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "GPDMA_C5TR1,GPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C5TR2,GPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C5BR1,GPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C5SAR,GPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C5DAR,GPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0x7 line.long 0x0 "GPDMA_C5LLR,GPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C6LBAR,GPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x35C++0x3 line.long 0x0 "GPDMA_C6FCR,GPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "GPDMA_C6SR,GPDMA channel 6 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "GPDMA_C6CR,GPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "GPDMA_C6TR1,GPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C6TR2,GPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C6BR1,GPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C6SAR,GPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C6DAR,GPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0x7 line.long 0x0 "GPDMA_C6LLR,GPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C7LBAR,GPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x3DC++0x3 line.long 0x0 "GPDMA_C7FCR,GPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "GPDMA_C7SR,GPDMA channel 7 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "GPDMA_C7CR,GPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "GPDMA_C7TR1,GPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C7TR2,GPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C7BR1,GPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C7SAR,GPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C7DAR,GPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0x7 line.long 0x0 "GPDMA_C7LLR,GPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C8LBAR,GPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x45C++0x3 line.long 0x0 "GPDMA_C8FCR,GPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "GPDMA_C8SR,GPDMA channel 8 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "GPDMA_C8CR,GPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "GPDMA_C8TR1,GPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C8TR2,GPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C8BR1,GPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C8SAR,GPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C8DAR,GPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0x7 line.long 0x0 "GPDMA_C8LLR,GPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C9LBAR,GPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x4DC++0x3 line.long 0x0 "GPDMA_C9FCR,GPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "GPDMA_C9SR,GPDMA channel 9 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "GPDMA_C9CR,GPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "GPDMA_C9TR1,GPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C9TR2,GPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C9BR1,GPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C9SAR,GPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C9DAR,GPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0x7 line.long 0x0 "GPDMA_C9LLR,GPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C10LBAR,GPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x55C++0x3 line.long 0x0 "GPDMA_C10FCR,GPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "GPDMA_C10SR,GPDMA channel 10 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "GPDMA_C10CR,GPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "GPDMA_C10TR1,GPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C10TR2,GPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C10BR1,GPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C10SAR,GPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C10DAR,GPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0x7 line.long 0x0 "GPDMA_C10LLR,GPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C11LBAR,GPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x5DC++0x3 line.long 0x0 "GPDMA_C11FCR,GPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "GPDMA_C11SR,GPDMA channel 11 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "GPDMA_C11CR,GPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "GPDMA_C11TR1,GPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C11TR2,GPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C11BR1,GPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C11SAR,GPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C11DAR,GPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0x7 line.long 0x0 "GPDMA_C11LLR,GPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C12LBAR,GPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x65C++0x3 line.long 0x0 "GPDMA_C12FCR,GPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "GPDMA_C12SR,GPDMA channel 12 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "GPDMA_C12CR,GPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "GPDMA_C12TR1,GPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C12TR2,GPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C12BR1,GPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C12SAR,GPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C12DAR,GPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C12TR3,GPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C12BR2,GPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0x7 line.long 0x0 "GPDMA_C12LLR,GPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C13LBAR,GPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x6DC++0x3 line.long 0x0 "GPDMA_C13FCR,GPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "GPDMA_C13SR,GPDMA channel 13 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "GPDMA_C13CR,GPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "GPDMA_C13TR1,GPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C13TR2,GPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C13BR1,GPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C13SAR,GPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C13DAR,GPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C13TR3,GPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C13BR2,GPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0x7 line.long 0x0 "GPDMA_C13LLR,GPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C14LBAR,GPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x75C++0x3 line.long 0x0 "GPDMA_C14FCR,GPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "GPDMA_C14SR,GPDMA channel 14 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "GPDMA_C14CR,GPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "GPDMA_C14TR1,GPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C14TR2,GPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C14BR1,GPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C14SAR,GPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C14DAR,GPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C14TR3,GPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C14BR2,GPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0x7 line.long 0x0 "GPDMA_C14LLR,GPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "GPDMA_C15LBAR,GPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x" wgroup.long 0x7DC++0x3 line.long 0x0 "GPDMA_C15FCR,GPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "GPDMA_C15SR,GPDMA channel 15 status register" hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "GPDMA_C15CR,GPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "GPDMA_C15TR1,GPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the GPDMA transfer to the destination" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.." bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." newline hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" bitfld.long 0x0 15. "SSEC,security attribute of the GPDMA transfer from the source" "0: GPDMA transfer non-secure,1: GPDMA transfer secure" newline bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated" bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." newline bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued" line.long 0x4 "GPDMA_C15TR2,GPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (x = 0 to 11) same as 00 channel x (x..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x (x = 0 to 11) same as 00; channel x (x..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,GPDMA hardware request selection" line.long 0x8 "GPDMA_C15BR1,GPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "GPDMA_C15SAR,GPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "GPDMA_C15DAR,GPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "GPDMA_C15TR3,GPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "GPDMA_C15BR2,GPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "GPDMA_C15LLR,GPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif tree.end tree "GPIO (General-Purpose I/Os)" base ad:0x0 tree "GPIOA" base ad:0x46020000 group.long 0x0++0xF line.long 0x0 "GPIOA_MODER,GPIO port A mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOA_OTYPER,GPIO port A output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOA_OSPEEDR,GPIO port A output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOA_PUPDR,GPIO port A pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_IDR,GPIO port A input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOA_ODR,GPIO port A output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOA_BSRR,GPIO port A bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOA_LCKR,GPIO port A configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOA_AFRL,GPIO port A alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOA_AFRH,GPIO port A alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_BRR,GPIO port A bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOA_SECCFGR,GPIO port A secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOA_PRIVCFGR,GPIO port A privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOA_RCFGLOCKR,GPIO port A resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOA_DELAYRL,GPIO port A delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOA_DELAYRH,GPIO port A delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOA_PIOCFGRL,GPIO port A PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOA_PIOCFGRH,GPIO port A PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOA_HWCFGR10,GPIO port A hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOA_HWCFGR9,GPIO port A hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOA_HWCFGR8,GPIO port A hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOA_HWCFGR7,GPIO port A hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOA_HWCFGR6,GPIO port A hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOA_HWCFGR5,GPIO port A hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOA_HWCFGR4,GPIO port A hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOA_HWCFGR3,GPIO port A hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOA_HWCFGR2,GPIO port A hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOA_HWCFGR1,GPIO port A hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOA_HWCFGR0,GPIO port A hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOA_VERR,GPIO port A version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOA_IPIDR,GPIO port A identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOA_SIDR,GPIO port A size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOA_S" base ad:0x56020000 group.long 0x0++0xF line.long 0x0 "GPIOA_MODER,GPIO port A mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOA_OTYPER,GPIO port A output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOA_OSPEEDR,GPIO port A output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOA_PUPDR,GPIO port A pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_IDR,GPIO port A input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOA_ODR,GPIO port A output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOA_BSRR,GPIO port A bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOA_LCKR,GPIO port A configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOA_AFRL,GPIO port A alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOA_AFRH,GPIO port A alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_BRR,GPIO port A bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOA_SECCFGR,GPIO port A secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOA_PRIVCFGR,GPIO port A privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOA_RCFGLOCKR,GPIO port A resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOA_DELAYRL,GPIO port A delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOA_DELAYRH,GPIO port A delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOA_PIOCFGRL,GPIO port A PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOA_PIOCFGRH,GPIO port A PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOA_HWCFGR10,GPIO port A hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOA_HWCFGR9,GPIO port A hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOA_HWCFGR8,GPIO port A hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOA_HWCFGR7,GPIO port A hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOA_HWCFGR6,GPIO port A hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOA_HWCFGR5,GPIO port A hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOA_HWCFGR4,GPIO port A hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOA_HWCFGR3,GPIO port A hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOA_HWCFGR2,GPIO port A hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOA_HWCFGR1,GPIO port A hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOA_HWCFGR0,GPIO port A hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOA_VERR,GPIO port A version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOA_IPIDR,GPIO port A identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOA_SIDR,GPIO port A size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOB" base ad:0x46020400 group.long 0x0++0xF line.long 0x0 "GPIOB_MODER,GPIO port B mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOB_OTYPER,GPIO port B output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOB_OSPEEDR,GPIO port B output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOB_PUPDR,GPIO port B pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_IDR,GPIO port B input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOB_ODR,GPIO port B output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOB_BSRR,GPIO port B bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOB_LCKR,GPIO port B configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOB_AFRL,GPIO port B alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOB_AFRH,GPIO port B alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_BRR,GPIO port B bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOB_SECCFGR,GPIO port B secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOB_PRIVCFGR,GPIO port B privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOB_RCFGLOCKR,GPIO port B resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOB_DELAYRL,GPIO port B delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOB_DELAYRH,GPIO port B delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOB_PIOCFGRL,GPIO port B PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOB_PIOCFGRH,GPIO port B PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOB_HWCFGR10,GPIO port B hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOB_HWCFGR9,GPIO port B hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOB_HWCFGR8,GPIO port B hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOB_HWCFGR7,GPIO port B hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOB_HWCFGR6,GPIO port B hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOB_HWCFGR5,GPIO port B hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOB_HWCFGR4,GPIO port B hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOB_HWCFGR3,GPIO port B hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOB_HWCFGR2,GPIO port B hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOB_HWCFGR1,GPIO port B hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOB_HWCFGR0,GPIO port B hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOB_VERR,GPIO port B version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOB_IPIDR,GPIO port B identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOB_SIDR,GPIO port B size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOB_S" base ad:0x56020400 group.long 0x0++0xF line.long 0x0 "GPIOB_MODER,GPIO port B mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOB_OTYPER,GPIO port B output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOB_OSPEEDR,GPIO port B output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOB_PUPDR,GPIO port B pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_IDR,GPIO port B input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOB_ODR,GPIO port B output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOB_BSRR,GPIO port B bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOB_LCKR,GPIO port B configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOB_AFRL,GPIO port B alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOB_AFRH,GPIO port B alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_BRR,GPIO port B bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOB_SECCFGR,GPIO port B secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOB_PRIVCFGR,GPIO port B privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOB_RCFGLOCKR,GPIO port B resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOB_DELAYRL,GPIO port B delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOB_DELAYRH,GPIO port B delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOB_PIOCFGRL,GPIO port B PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOB_PIOCFGRH,GPIO port B PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOB_HWCFGR10,GPIO port B hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOB_HWCFGR9,GPIO port B hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOB_HWCFGR8,GPIO port B hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOB_HWCFGR7,GPIO port B hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOB_HWCFGR6,GPIO port B hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOB_HWCFGR5,GPIO port B hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOB_HWCFGR4,GPIO port B hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOB_HWCFGR3,GPIO port B hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOB_HWCFGR2,GPIO port B hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOB_HWCFGR1,GPIO port B hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOB_HWCFGR0,GPIO port B hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOB_VERR,GPIO port B version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOB_IPIDR,GPIO port B identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOB_SIDR,GPIO port B size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOC" base ad:0x46020800 group.long 0x0++0xF line.long 0x0 "GPIOC_MODER,GPIO port C mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOC_OTYPER,GPIO port C output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOC_OSPEEDR,GPIO port C output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOC_PUPDR,GPIO port C pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOC_IDR,GPIO port C input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOC_ODR,GPIO port C output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOC_BSRR,GPIO port C bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOC_LCKR,GPIO port C configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOC_AFRL,GPIO port C alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOC_AFRH,GPIO port C alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOC_BRR,GPIO port C bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOC_SECCFGR,GPIO port C secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOC_PRIVCFGR,GPIO port C privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOC_RCFGLOCKR,GPIO port C resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOC_DELAYRL,GPIO port C delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOC_DELAYRH,GPIO port C delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOC_PIOCFGRL,GPIO port C PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOC_PIOCFGRH,GPIO port C PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOC_HWCFGR10,GPIO port C hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOC_HWCFGR9,GPIO port C hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOC_HWCFGR8,GPIO port C hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOC_HWCFGR7,GPIO port C hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOC_HWCFGR6,GPIO port C hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOC_HWCFGR5,GPIO port C hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOC_HWCFGR4,GPIO port C hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOC_HWCFGR3,GPIO port C hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOC_HWCFGR2,GPIO port C hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOC_HWCFGR1,GPIO port C hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOC_HWCFGR0,GPIO port C hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOC_VERR,GPIO port C version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOC_IPIDR,GPIO port C identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOC_SIDR,GPIO port C size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOC_S" base ad:0x56020800 group.long 0x0++0xF line.long 0x0 "GPIOC_MODER,GPIO port C mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOC_OTYPER,GPIO port C output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOC_OSPEEDR,GPIO port C output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOC_PUPDR,GPIO port C pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOC_IDR,GPIO port C input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOC_ODR,GPIO port C output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOC_BSRR,GPIO port C bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOC_LCKR,GPIO port C configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOC_AFRL,GPIO port C alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOC_AFRH,GPIO port C alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOC_BRR,GPIO port C bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOC_SECCFGR,GPIO port C secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOC_PRIVCFGR,GPIO port C privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOC_RCFGLOCKR,GPIO port C resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOC_DELAYRL,GPIO port C delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOC_DELAYRH,GPIO port C delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOC_PIOCFGRL,GPIO port C PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOC_PIOCFGRH,GPIO port C PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOC_HWCFGR10,GPIO port C hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOC_HWCFGR9,GPIO port C hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOC_HWCFGR8,GPIO port C hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOC_HWCFGR7,GPIO port C hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOC_HWCFGR6,GPIO port C hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOC_HWCFGR5,GPIO port C hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOC_HWCFGR4,GPIO port C hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOC_HWCFGR3,GPIO port C hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOC_HWCFGR2,GPIO port C hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOC_HWCFGR1,GPIO port C hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOC_HWCFGR0,GPIO port C hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOC_VERR,GPIO port C version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOC_IPIDR,GPIO port C identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOC_SIDR,GPIO port C size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOD" base ad:0x46020C00 group.long 0x0++0xF line.long 0x0 "GPIOD_MODER,GPIO port D mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOD_OTYPER,GPIO port D output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOD_OSPEEDR,GPIO port D output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOD_PUPDR,GPIO port D pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOD_IDR,GPIO port D input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOD_ODR,GPIO port D output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOD_BSRR,GPIO port D bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOD_LCKR,GPIO port D configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOD_AFRL,GPIO port D alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOD_AFRH,GPIO port D alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOD_BRR,GPIO port D bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOD_SECCFGR,GPIO port D secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOD_PRIVCFGR,GPIO port D privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOD_RCFGLOCKR,GPIO port D resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOD_DELAYRL,GPIO port D delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOD_DELAYRH,GPIO port D delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOD_PIOCFGRL,GPIO port D PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOD_PIOCFGRH,GPIO port D PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOD_HWCFGR10,GPIO port D hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOD_HWCFGR9,GPIO port D hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOD_HWCFGR8,GPIO port D hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOD_HWCFGR7,GPIO port D hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOD_HWCFGR6,GPIO port D hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOD_HWCFGR5,GPIO port D hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOD_HWCFGR4,GPIO port D hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOD_HWCFGR3,GPIO port D hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOD_HWCFGR2,GPIO port D hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOD_HWCFGR1,GPIO port D hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOD_HWCFGR0,GPIO port D hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOD_VERR,GPIO port D version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOD_IPIDR,GPIO port D identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOD_SIDR,GPIO port D size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOD_S" base ad:0x56020C00 group.long 0x0++0xF line.long 0x0 "GPIOD_MODER,GPIO port D mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOD_OTYPER,GPIO port D output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOD_OSPEEDR,GPIO port D output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOD_PUPDR,GPIO port D pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOD_IDR,GPIO port D input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOD_ODR,GPIO port D output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOD_BSRR,GPIO port D bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOD_LCKR,GPIO port D configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOD_AFRL,GPIO port D alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOD_AFRH,GPIO port D alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOD_BRR,GPIO port D bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOD_SECCFGR,GPIO port D secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOD_PRIVCFGR,GPIO port D privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOD_RCFGLOCKR,GPIO port D resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOD_DELAYRL,GPIO port D delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOD_DELAYRH,GPIO port D delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOD_PIOCFGRL,GPIO port D PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOD_PIOCFGRH,GPIO port D PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOD_HWCFGR10,GPIO port D hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOD_HWCFGR9,GPIO port D hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOD_HWCFGR8,GPIO port D hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOD_HWCFGR7,GPIO port D hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOD_HWCFGR6,GPIO port D hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOD_HWCFGR5,GPIO port D hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOD_HWCFGR4,GPIO port D hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOD_HWCFGR3,GPIO port D hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOD_HWCFGR2,GPIO port D hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOD_HWCFGR1,GPIO port D hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOD_HWCFGR0,GPIO port D hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOD_VERR,GPIO port D version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOD_IPIDR,GPIO port D identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOD_SIDR,GPIO port D size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOE" base ad:0x46021000 group.long 0x0++0xF line.long 0x0 "GPIOE_MODER,GPIO port E mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOE_OTYPER,GPIO port E output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOE_OSPEEDR,GPIO port E output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOE_PUPDR,GPIO port E pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOE_IDR,GPIO port E input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOE_ODR,GPIO port E output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOE_BSRR,GPIO port E bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOE_LCKR,GPIO port E configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOE_AFRL,GPIO port E alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOE_AFRH,GPIO port E alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOE_BRR,GPIO port E bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOE_SECCFGR,GPIO port E secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOE_PRIVCFGR,GPIO port E privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOE_RCFGLOCKR,GPIO port E resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOE_DELAYRL,GPIO port E delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOE_DELAYRH,GPIO port E delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOE_PIOCFGRL,GPIO port E PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOE_PIOCFGRH,GPIO port E PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOE_HWCFGR10,GPIO port E hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOE_HWCFGR9,GPIO port E hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOE_HWCFGR8,GPIO port E hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOE_HWCFGR7,GPIO port E hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOE_HWCFGR6,GPIO port E hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOE_HWCFGR5,GPIO port E hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOE_HWCFGR4,GPIO port E hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOE_HWCFGR3,GPIO port E hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOE_HWCFGR2,GPIO port E hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOE_HWCFGR1,GPIO port E hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOE_HWCFGR0,GPIO port E hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOE_VERR,GPIO port E version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOE_IPIDR,GPIO port E identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOE_SIDR,GPIO port E size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOE_S" base ad:0x56021000 group.long 0x0++0xF line.long 0x0 "GPIOE_MODER,GPIO port E mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOE_OTYPER,GPIO port E output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOE_OSPEEDR,GPIO port E output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOE_PUPDR,GPIO port E pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOE_IDR,GPIO port E input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOE_ODR,GPIO port E output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOE_BSRR,GPIO port E bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOE_LCKR,GPIO port E configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOE_AFRL,GPIO port E alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOE_AFRH,GPIO port E alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOE_BRR,GPIO port E bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOE_SECCFGR,GPIO port E secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOE_PRIVCFGR,GPIO port E privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOE_RCFGLOCKR,GPIO port E resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOE_DELAYRL,GPIO port E delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOE_DELAYRH,GPIO port E delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOE_PIOCFGRL,GPIO port E PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOE_PIOCFGRH,GPIO port E PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOE_HWCFGR10,GPIO port E hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOE_HWCFGR9,GPIO port E hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOE_HWCFGR8,GPIO port E hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOE_HWCFGR7,GPIO port E hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOE_HWCFGR6,GPIO port E hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOE_HWCFGR5,GPIO port E hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOE_HWCFGR4,GPIO port E hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOE_HWCFGR3,GPIO port E hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOE_HWCFGR2,GPIO port E hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOE_HWCFGR1,GPIO port E hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOE_HWCFGR0,GPIO port E hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOE_VERR,GPIO port E version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOE_IPIDR,GPIO port E identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOE_SIDR,GPIO port E size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOF" base ad:0x46021400 group.long 0x0++0xF line.long 0x0 "GPIOF_MODER,GPIO port F mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOF_OTYPER,GPIO port F output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOF_OSPEEDR,GPIO port F output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOF_PUPDR,GPIO port F pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOF_IDR,GPIO port F input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOF_ODR,GPIO port F output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOF_BSRR,GPIO port F bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOF_LCKR,GPIO port F configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOF_AFRL,GPIO port F alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOF_AFRH,GPIO port F alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOF_BRR,GPIO port F bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOF_SECCFGR,GPIO port F secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOF_PRIVCFGR,GPIO port F privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOF_RCFGLOCKR,GPIO port F resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOF_DELAYRL,GPIO port F delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOF_DELAYRH,GPIO port F delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOF_PIOCFGRL,GPIO port F PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOF_PIOCFGRH,GPIO port F PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOF_HWCFGR10,GPIO port F hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOF_HWCFGR9,GPIO port F hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOF_HWCFGR8,GPIO port F hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOF_HWCFGR7,GPIO port F hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOF_HWCFGR6,GPIO port F hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOF_HWCFGR5,GPIO port F hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOF_HWCFGR4,GPIO port F hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOF_HWCFGR3,GPIO port F hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOF_HWCFGR2,GPIO port F hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOF_HWCFGR1,GPIO port F hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOF_HWCFGR0,GPIO port F hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOF_VERR,GPIO port F version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOF_IPIDR,GPIO port F identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOF_SIDR,GPIO port F size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOF_S" base ad:0x56021400 group.long 0x0++0xF line.long 0x0 "GPIOF_MODER,GPIO port F mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOF_OTYPER,GPIO port F output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOF_OSPEEDR,GPIO port F output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOF_PUPDR,GPIO port F pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOF_IDR,GPIO port F input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOF_ODR,GPIO port F output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOF_BSRR,GPIO port F bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOF_LCKR,GPIO port F configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOF_AFRL,GPIO port F alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOF_AFRH,GPIO port F alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOF_BRR,GPIO port F bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOF_SECCFGR,GPIO port F secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOF_PRIVCFGR,GPIO port F privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOF_RCFGLOCKR,GPIO port F resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOF_DELAYRL,GPIO port F delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOF_DELAYRH,GPIO port F delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOF_PIOCFGRL,GPIO port F PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOF_PIOCFGRH,GPIO port F PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOF_HWCFGR10,GPIO port F hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOF_HWCFGR9,GPIO port F hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOF_HWCFGR8,GPIO port F hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOF_HWCFGR7,GPIO port F hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOF_HWCFGR6,GPIO port F hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOF_HWCFGR5,GPIO port F hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOF_HWCFGR4,GPIO port F hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOF_HWCFGR3,GPIO port F hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOF_HWCFGR2,GPIO port F hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOF_HWCFGR1,GPIO port F hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOF_HWCFGR0,GPIO port F hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOF_VERR,GPIO port F version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOF_IPIDR,GPIO port F identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOF_SIDR,GPIO port F size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOG" base ad:0x46021800 group.long 0x0++0xF line.long 0x0 "GPIOG_MODER,GPIO port G mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOG_OTYPER,GPIO port G output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOG_OSPEEDR,GPIO port G output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOG_PUPDR,GPIO port G pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOG_IDR,GPIO port G input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOG_ODR,GPIO port G output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOG_BSRR,GPIO port G bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOG_LCKR,GPIO port G configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOG_AFRL,GPIO port G alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOG_AFRH,GPIO port G alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOG_BRR,GPIO port G bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOG_SECCFGR,GPIO port G secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOG_PRIVCFGR,GPIO port G privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOG_RCFGLOCKR,GPIO port G resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOG_DELAYRL,GPIO port G delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOG_DELAYRH,GPIO port G delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOG_PIOCFGRL,GPIO port G PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOG_PIOCFGRH,GPIO port G PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOG_HWCFGR10,GPIO port G hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOG_HWCFGR9,GPIO port G hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOG_HWCFGR8,GPIO port G hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOG_HWCFGR7,GPIO port G hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOG_HWCFGR6,GPIO port G hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOG_HWCFGR5,GPIO port G hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOG_HWCFGR4,GPIO port G hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOG_HWCFGR3,GPIO port G hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOG_HWCFGR2,GPIO port G hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOG_HWCFGR1,GPIO port G hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOG_HWCFGR0,GPIO port G hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOG_VERR,GPIO port G version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOG_IPIDR,GPIO port G identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOG_SIDR,GPIO port G size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOG_S" base ad:0x56021800 group.long 0x0++0xF line.long 0x0 "GPIOG_MODER,GPIO port G mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOG_OTYPER,GPIO port G output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOG_OSPEEDR,GPIO port G output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOG_PUPDR,GPIO port G pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOG_IDR,GPIO port G input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOG_ODR,GPIO port G output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOG_BSRR,GPIO port G bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOG_LCKR,GPIO port G configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOG_AFRL,GPIO port G alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOG_AFRH,GPIO port G alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOG_BRR,GPIO port G bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOG_SECCFGR,GPIO port G secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOG_PRIVCFGR,GPIO port G privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOG_RCFGLOCKR,GPIO port G resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOG_DELAYRL,GPIO port G delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOG_DELAYRH,GPIO port G delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOG_PIOCFGRL,GPIO port G PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOG_PIOCFGRH,GPIO port G PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOG_HWCFGR10,GPIO port G hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOG_HWCFGR9,GPIO port G hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOG_HWCFGR8,GPIO port G hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOG_HWCFGR7,GPIO port G hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOG_HWCFGR6,GPIO port G hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOG_HWCFGR5,GPIO port G hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOG_HWCFGR4,GPIO port G hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOG_HWCFGR3,GPIO port G hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOG_HWCFGR2,GPIO port G hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOG_HWCFGR1,GPIO port G hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOG_HWCFGR0,GPIO port G hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOG_VERR,GPIO port G version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOG_IPIDR,GPIO port G identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOG_SIDR,GPIO port G size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOH" base ad:0x46021C00 group.long 0x0++0xF line.long 0x0 "GPIOH_MODER,GPIO port H mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOH_OTYPER,GPIO port H output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOH_OSPEEDR,GPIO port H output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOH_PUPDR,GPIO port H pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOH_IDR,GPIO port H input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOH_ODR,GPIO port H output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOH_BSRR,GPIO port H bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOH_LCKR,GPIO port H configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOH_AFRL,GPIO port H alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOH_AFRH,GPIO port H alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOH_BRR,GPIO port H bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOH_SECCFGR,GPIO port H secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOH_PRIVCFGR,GPIO port H privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOH_RCFGLOCKR,GPIO port H resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOH_DELAYRL,GPIO port H delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOH_DELAYRH,GPIO port H delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOH_PIOCFGRL,GPIO port H PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOH_PIOCFGRH,GPIO port H PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOH_HWCFGR10,GPIO port H hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOH_HWCFGR9,GPIO port H hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOH_HWCFGR8,GPIO port H hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOH_HWCFGR7,GPIO port H hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOH_HWCFGR6,GPIO port H hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOH_HWCFGR5,GPIO port H hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOH_HWCFGR4,GPIO port H hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOH_HWCFGR3,GPIO port H hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOH_HWCFGR2,GPIO port H hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOH_HWCFGR1,GPIO port H hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOH_HWCFGR0,GPIO port H hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOH_VERR,GPIO port H version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOH_IPIDR,GPIO port H identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOH_SIDR,GPIO port H size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOH_S" base ad:0x56021C00 group.long 0x0++0xF line.long 0x0 "GPIOH_MODER,GPIO port H mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOH_OTYPER,GPIO port H output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOH_OSPEEDR,GPIO port H output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOH_PUPDR,GPIO port H pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOH_IDR,GPIO port H input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOH_ODR,GPIO port H output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOH_BSRR,GPIO port H bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOH_LCKR,GPIO port H configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOH_AFRL,GPIO port H alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOH_AFRH,GPIO port H alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOH_BRR,GPIO port H bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOH_SECCFGR,GPIO port H secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOH_PRIVCFGR,GPIO port H privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOH_RCFGLOCKR,GPIO port H resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOH_DELAYRL,GPIO port H delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOH_DELAYRH,GPIO port H delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOH_PIOCFGRL,GPIO port H PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOH_PIOCFGRH,GPIO port H PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOH_HWCFGR10,GPIO port H hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOH_HWCFGR9,GPIO port H hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOH_HWCFGR8,GPIO port H hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOH_HWCFGR7,GPIO port H hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOH_HWCFGR6,GPIO port H hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOH_HWCFGR5,GPIO port H hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOH_HWCFGR4,GPIO port H hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOH_HWCFGR3,GPIO port H hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOH_HWCFGR2,GPIO port H hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOH_HWCFGR1,GPIO port H hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOH_HWCFGR0,GPIO port H hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOH_VERR,GPIO port H version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOH_IPIDR,GPIO port H identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOH_SIDR,GPIO port H size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPION" base ad:0x46023400 group.long 0x0++0xF line.long 0x0 "GPION_MODER,GPIO port N mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPION_OTYPER,GPIO port N output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPION_OSPEEDR,GPIO port N output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPION_PUPDR,GPIO port N pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPION_IDR,GPIO port N input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPION_ODR,GPIO port N output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPION_BSRR,GPIO port N bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPION_LCKR,GPIO port N configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPION_AFRL,GPIO port N alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPION_AFRH,GPIO port N alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPION_BRR,GPIO port N bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPION_SECCFGR,GPIO port N secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPION_PRIVCFGR,GPIO port N privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPION_RCFGLOCKR,GPIO port N resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPION_DELAYRL,GPIO port N delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPION_DELAYRH,GPIO port N delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPION_PIOCFGRL,GPIO port N PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPION_PIOCFGRH,GPIO port N PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPION_HWCFGR10,GPIO port N hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPION_HWCFGR9,GPIO port N hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPION_HWCFGR8,GPIO port N hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPION_HWCFGR7,GPIO port N hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPION_HWCFGR6,GPIO port N hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPION_HWCFGR5,GPIO port N hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPION_HWCFGR4,GPIO port N hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPION_HWCFGR3,GPIO port N hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPION_HWCFGR2,GPIO port N hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPION_HWCFGR1,GPIO port N hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPION_HWCFGR0,GPIO port N hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPION_VERR,GPIO port N version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPION_IPIDR,GPIO port N identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPION_SIDR,GPIO port N size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPION_S" base ad:0x56023400 group.long 0x0++0xF line.long 0x0 "GPION_MODER,GPIO port N mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPION_OTYPER,GPIO port N output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPION_OSPEEDR,GPIO port N output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPION_PUPDR,GPIO port N pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPION_IDR,GPIO port N input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPION_ODR,GPIO port N output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPION_BSRR,GPIO port N bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPION_LCKR,GPIO port N configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPION_AFRL,GPIO port N alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPION_AFRH,GPIO port N alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPION_BRR,GPIO port N bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPION_SECCFGR,GPIO port N secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPION_PRIVCFGR,GPIO port N privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPION_RCFGLOCKR,GPIO port N resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPION_DELAYRL,GPIO port N delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPION_DELAYRH,GPIO port N delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPION_PIOCFGRL,GPIO port N PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPION_PIOCFGRH,GPIO port N PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPION_HWCFGR10,GPIO port N hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPION_HWCFGR9,GPIO port N hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPION_HWCFGR8,GPIO port N hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPION_HWCFGR7,GPIO port N hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPION_HWCFGR6,GPIO port N hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPION_HWCFGR5,GPIO port N hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPION_HWCFGR4,GPIO port N hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPION_HWCFGR3,GPIO port N hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPION_HWCFGR2,GPIO port N hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPION_HWCFGR1,GPIO port N hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPION_HWCFGR0,GPIO port N hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPION_VERR,GPIO port N version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPION_IPIDR,GPIO port N identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPION_SIDR,GPIO port N size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOO" base ad:0x46023800 group.long 0x0++0xF line.long 0x0 "GPIOO_MODER,GPIO port O mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOO_OTYPER,GPIO port O output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOO_OSPEEDR,GPIO port O output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOO_PUPDR,GPIO port O pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOO_IDR,GPIO port O input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOO_ODR,GPIO port O output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOO_BSRR,GPIO port O bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOO_LCKR,GPIO port O configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOO_AFRL,GPIO port O alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOO_AFRH,GPIO port O alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOO_BRR,GPIO port O bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOO_SECCFGR,GPIO port O secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOO_PRIVCFGR,GPIO port O privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOO_RCFGLOCKR,GPIO port O resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOO_DELAYRL,GPIO port O delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOO_DELAYRH,GPIO port O delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOO_PIOCFGRL,GPIO port O PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOO_PIOCFGRH,GPIO port O PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOO_HWCFGR10,GPIO port O hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOO_HWCFGR9,GPIO port O hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOO_HWCFGR8,GPIO port O hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOO_HWCFGR7,GPIO port O hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOO_HWCFGR6,GPIO port O hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOO_HWCFGR5,GPIO port O hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOO_HWCFGR4,GPIO port O hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOO_HWCFGR3,GPIO port O hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOO_HWCFGR2,GPIO port O hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOO_HWCFGR1,GPIO port O hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOO_HWCFGR0,GPIO port O hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOO_VERR,GPIO port O version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOO_IPIDR,GPIO port O identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOO_SIDR,GPIO port O size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOO_S" base ad:0x56023800 group.long 0x0++0xF line.long 0x0 "GPIOO_MODER,GPIO port O mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOO_OTYPER,GPIO port O output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOO_OSPEEDR,GPIO port O output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOO_PUPDR,GPIO port O pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOO_IDR,GPIO port O input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOO_ODR,GPIO port O output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOO_BSRR,GPIO port O bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOO_LCKR,GPIO port O configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOO_AFRL,GPIO port O alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOO_AFRH,GPIO port O alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOO_BRR,GPIO port O bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOO_SECCFGR,GPIO port O secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOO_PRIVCFGR,GPIO port O privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOO_RCFGLOCKR,GPIO port O resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOO_DELAYRL,GPIO port O delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOO_DELAYRH,GPIO port O delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOO_PIOCFGRL,GPIO port O PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOO_PIOCFGRH,GPIO port O PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOO_HWCFGR10,GPIO port O hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOO_HWCFGR9,GPIO port O hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOO_HWCFGR8,GPIO port O hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOO_HWCFGR7,GPIO port O hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOO_HWCFGR6,GPIO port O hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOO_HWCFGR5,GPIO port O hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOO_HWCFGR4,GPIO port O hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOO_HWCFGR3,GPIO port O hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOO_HWCFGR2,GPIO port O hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOO_HWCFGR1,GPIO port O hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOO_HWCFGR0,GPIO port O hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOO_VERR,GPIO port O version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOO_IPIDR,GPIO port O identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOO_SIDR,GPIO port O size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOP" base ad:0x46023C00 group.long 0x0++0xF line.long 0x0 "GPIOP_MODER,GPIO port P mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOP_OTYPER,GPIO port P output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOP_OSPEEDR,GPIO port P output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOP_PUPDR,GPIO port P pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOP_IDR,GPIO port P input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOP_ODR,GPIO port P output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOP_BSRR,GPIO port P bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOP_LCKR,GPIO port P configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOP_AFRL,GPIO port P alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOP_AFRH,GPIO port P alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOP_BRR,GPIO port P bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOP_SECCFGR,GPIO port P secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOP_PRIVCFGR,GPIO port P privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOP_RCFGLOCKR,GPIO port P resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOP_DELAYRL,GPIO port P delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOP_DELAYRH,GPIO port P delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOP_PIOCFGRL,GPIO port P PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOP_PIOCFGRH,GPIO port P PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOP_HWCFGR10,GPIO port P hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOP_HWCFGR9,GPIO port P hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOP_HWCFGR8,GPIO port P hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOP_HWCFGR7,GPIO port P hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOP_HWCFGR6,GPIO port P hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOP_HWCFGR5,GPIO port P hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOP_HWCFGR4,GPIO port P hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOP_HWCFGR3,GPIO port P hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOP_HWCFGR2,GPIO port P hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOP_HWCFGR1,GPIO port P hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOP_HWCFGR0,GPIO port P hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOP_VERR,GPIO port P version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOP_IPIDR,GPIO port P identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOP_SIDR,GPIO port P size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOP_S" base ad:0x56023C00 group.long 0x0++0xF line.long 0x0 "GPIOP_MODER,GPIO port P mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOP_OTYPER,GPIO port P output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOP_OSPEEDR,GPIO port P output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOP_PUPDR,GPIO port P pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOP_IDR,GPIO port P input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOP_ODR,GPIO port P output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOP_BSRR,GPIO port P bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOP_LCKR,GPIO port P configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOP_AFRL,GPIO port P alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOP_AFRH,GPIO port P alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOP_BRR,GPIO port P bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOP_SECCFGR,GPIO port P secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOP_PRIVCFGR,GPIO port P privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOP_RCFGLOCKR,GPIO port P resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOP_DELAYRL,GPIO port P delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOP_DELAYRH,GPIO port P delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOP_PIOCFGRL,GPIO port P PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOP_PIOCFGRH,GPIO port P PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOP_HWCFGR10,GPIO port P hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOP_HWCFGR9,GPIO port P hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOP_HWCFGR8,GPIO port P hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOP_HWCFGR7,GPIO port P hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOP_HWCFGR6,GPIO port P hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOP_HWCFGR5,GPIO port P hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOP_HWCFGR4,GPIO port P hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOP_HWCFGR3,GPIO port P hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOP_HWCFGR2,GPIO port P hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOP_HWCFGR1,GPIO port P hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOP_HWCFGR0,GPIO port P hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOP_VERR,GPIO port P version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOP_IPIDR,GPIO port P identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOP_SIDR,GPIO port P size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOQ" base ad:0x46024000 group.long 0x0++0xF line.long 0x0 "GPIOQ_MODER,GPIO port Q mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOQ_OTYPER,GPIO port Q output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOQ_OSPEEDR,GPIO port Q output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOQ_PUPDR,GPIO port Q pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOQ_IDR,GPIO port Q input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOQ_ODR,GPIO port Q output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOQ_BSRR,GPIO port Q bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOQ_LCKR,GPIO port Q configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOQ_AFRL,GPIO port Q alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOQ_AFRH,GPIO port Q alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOQ_BRR,GPIO port Q bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOQ_SECCFGR,GPIO port Q secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOQ_PRIVCFGR,GPIO port Q privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOQ_RCFGLOCKR,GPIO port Q resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOQ_DELAYRL,GPIO port Q delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOQ_DELAYRH,GPIO port Q delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOQ_PIOCFGRL,GPIO port Q PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOQ_PIOCFGRH,GPIO port Q PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOQ_HWCFGR10,GPIO port Q hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOQ_HWCFGR9,GPIO port Q hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOQ_HWCFGR8,GPIO port Q hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOQ_HWCFGR7,GPIO port Q hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOQ_HWCFGR6,GPIO port Q hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOQ_HWCFGR5,GPIO port Q hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOQ_HWCFGR4,GPIO port Q hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOQ_HWCFGR3,GPIO port Q hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOQ_HWCFGR2,GPIO port Q hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOQ_HWCFGR1,GPIO port Q hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOQ_HWCFGR0,GPIO port Q hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOQ_VERR,GPIO port Q version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOQ_IPIDR,GPIO port Q identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOQ_SIDR,GPIO port Q size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree "GPIOQ_S" base ad:0x56024000 group.long 0x0++0xF line.long 0x0 "GPIOQ_MODER,GPIO port Q mode register" bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" newline bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: General-purpose input mode,1: General-purpose output mode,2: Alternate function mode (refer to device..,3: Analog mode (reset state)" line.long 0x4 "GPIOQ_OTYPER,GPIO port Q output type register" bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" newline bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain" line.long 0x8 "GPIOQ_OSPEEDR,GPIO port Q output speed register" bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" newline bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed" line.long 0xC "GPIOQ_PUPDR,GPIO port Q pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" newline bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?" rgroup.long 0x10++0x3 line.long 0x0 "GPIOQ_IDR,GPIO port Q input data register" bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1" bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1" bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1" bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1" bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1" bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1" bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1" bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1" newline bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1" bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOQ_ODR,GPIO port Q output data register" bitfld.long 0x0 15. "OD15,Port x output data I/O pin y" "0,1" bitfld.long 0x0 14. "OD14,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 13. "OD13,Port x output data I/O pin y" "0,1" bitfld.long 0x0 12. "OD12,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 11. "OD11,Port x output data I/O pin y" "0,1" bitfld.long 0x0 10. "OD10,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 9. "OD9,Port x output data I/O pin y" "0,1" bitfld.long 0x0 8. "OD8,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 7. "OD7,Port x output data I/O pin y" "0,1" bitfld.long 0x0 6. "OD6,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 5. "OD5,Port x output data I/O pin y" "0,1" bitfld.long 0x0 4. "OD4,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 3. "OD3,Port x output data I/O pin y" "0,1" bitfld.long 0x0 2. "OD2,Port x output data I/O pin y" "0,1" newline bitfld.long 0x0 1. "OD1,Port x output data I/O pin y" "0,1" bitfld.long 0x0 0. "OD0,Port x output data I/O pin y" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOQ_BSRR,GPIO port Q bit set/reset register" bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit" newline bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" newline bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit" group.long 0x1C++0xB line.long 0x0 "GPIOQ_LCKR,GPIO port Q configuration lock register" bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.." bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" newline bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked" line.long 0x4 "GPIOQ_AFRL,GPIO port Q alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y" line.long 0x8 "GPIOQ_AFRH,GPIO port Q alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y" wgroup.long 0x28++0x3 line.long 0x0 "GPIOQ_BRR,GPIO port Q bit reset register" bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" newline bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit" group.long 0x30++0xB line.long 0x0 "GPIOQ_SECCFGR,GPIO port Q secure configuration register" bitfld.long 0x0 15. "SEC15,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 14. "SEC14,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 13. "SEC13,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 12. "SEC12,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 11. "SEC11,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 10. "SEC10,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 9. "SEC9,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 8. "SEC8,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 7. "SEC7,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 6. "SEC6,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 5. "SEC5,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 4. "SEC4,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 3. "SEC3,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 2. "SEC2,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." newline bitfld.long 0x0 1. "SEC1,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." bitfld.long 0x0 0. "SEC0,I/O pin y of Port x security configuration" "0: The I/O pin y is non-secure. Secure access is..,1: The I/O pin y is secure (see Table 70 for all.." line.long 0x4 "GPIOQ_PRIVCFGR,GPIO port Q privileged configuration register" bitfld.long 0x4 15. "PRIV15,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 14. "PRIV14,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 13. "PRIV13,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 12. "PRIV12,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 11. "PRIV11,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 10. "PRIV10,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 9. "PRIV9,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 8. "PRIV8,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 7. "PRIV7,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 6. "PRIV6,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 5. "PRIV5,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 4. "PRIV4,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 3. "PRIV3,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 2. "PRIV2,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." newline bitfld.long 0x4 1. "PRIV1,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." bitfld.long 0x4 0. "PRIV0,I/O pin y of Port x privilege configuration" "0: The I/O pin y is unprivileged. Privileged access..,1: The I/O pin y is privileged only (see Table 70.." line.long 0x8 "GPIOQ_RCFGLOCKR,GPIO port Q resource configuration lock register" bitfld.long 0x8 15. "RLOCK15,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 14. "RLOCK14,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 13. "RLOCK13,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 12. "RLOCK12,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 11. "RLOCK11,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 10. "RLOCK10,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 9. "RLOCK9,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 8. "RLOCK8,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 7. "RLOCK7,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 6. "RLOCK6,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 5. "RLOCK5,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 4. "RLOCK4,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 3. "RLOCK3,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 2. "RLOCK2,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." newline bitfld.long 0x8 1. "RLOCK1,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." bitfld.long 0x8 0. "RLOCK0,I/O pin y of port x resource lock" "0: SECy in GPIOx_SECCFGR and PRIVy in..,1: Writes to SECy in GPIOx_SECCFGR and PRIVy in.." group.long 0x40++0xF line.long 0x0 "GPIOQ_DELAYRL,GPIO port Q delay low register" hexmask.long.byte 0x0 28.--31. 1. "DELAY7,Port x IO pin y delay setup" hexmask.long.byte 0x0 24.--27. 1. "DELAY6,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 20.--23. 1. "DELAY5,Port x IO pin y delay setup" hexmask.long.byte 0x0 16.--19. 1. "DELAY4,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 12.--15. 1. "DELAY3,Port x IO pin y delay setup" hexmask.long.byte 0x0 8.--11. 1. "DELAY2,Port x IO pin y delay setup" newline hexmask.long.byte 0x0 4.--7. 1. "DELAY1,Port x IO pin y delay setup" hexmask.long.byte 0x0 0.--3. 1. "DELAY0,Port x IO pin y delay setup" line.long 0x4 "GPIOQ_DELAYRH,GPIO port Q delay high register" hexmask.long.byte 0x4 28.--31. 1. "DELAY15,Port x I/O pin y delay setup" hexmask.long.byte 0x4 24.--27. 1. "DELAY14,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 20.--23. 1. "DELAY13,Port x I/O pin y delay setup" hexmask.long.byte 0x4 16.--19. 1. "DELAY12,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 12.--15. 1. "DELAY11,Port x I/O pin y delay setup" hexmask.long.byte 0x4 8.--11. 1. "DELAY10,Port x I/O pin y delay setup" newline hexmask.long.byte 0x4 4.--7. 1. "DELAY9,Port x I/O pin y delay setup" hexmask.long.byte 0x4 0.--3. 1. "DELAY8,Port x I/O pin y delay setup" line.long 0x8 "GPIOQ_PIOCFGRL,GPIO port Q PIO control low register" hexmask.long.byte 0x8 28.--31. 1. "PIOCFG7,Port x I/O pin y configuration" hexmask.long.byte 0x8 24.--27. 1. "PIOCFG6,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 20.--23. 1. "PIOCFG5,Port x I/O pin y configuration" hexmask.long.byte 0x8 16.--19. 1. "PIOCFG4,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 12.--15. 1. "PIOCFG3,Port x I/O pin y configuration" hexmask.long.byte 0x8 8.--11. 1. "PIOCFG2,Port x I/O pin y configuration" newline hexmask.long.byte 0x8 4.--7. 1. "PIOCFG1,Port x I/O pin y configuration" hexmask.long.byte 0x8 0.--3. 1. "PIOCFG0,Port x I/O pin y configuration" line.long 0xC "GPIOQ_PIOCFGRH,GPIO port Q PIO control high register" hexmask.long.byte 0xC 28.--31. 1. "PIOCFG15,Port x I/O pin y configuration" hexmask.long.byte 0xC 24.--27. 1. "PIOCFG14,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 20.--23. 1. "PIOCFG13,Port x I/O pin y configuration" hexmask.long.byte 0xC 16.--19. 1. "PIOCFG12,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 12.--15. 1. "PIOCFG11,Port x I/O pin y configuration" hexmask.long.byte 0xC 8.--11. 1. "PIOCFG10,Port x I/O pin y configuration" newline hexmask.long.byte 0xC 4.--7. 1. "PIOCFG9,Port x I/O pin y configuration" hexmask.long.byte 0xC 0.--3. 1. "PIOCFG8,Port x I/O pin y configuration" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOQ_HWCFGR10,GPIO port Q hardware configuration register 10" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,Option register configuration" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,Security activation" newline hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,Lock mechanism activation" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,Number of speed lines for each I/O" newline hexmask.long.byte 0x0 4.--7. 1. "AFSIZE_CFG,Number of AF available for each I/O (accepted value: 1 to 4)" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,Bus interface selection" line.long 0x4 "GPIOQ_HWCFGR9,GPIO port Q hardware configuration register 9" hexmask.long.word 0x4 0.--15. 1. "EN_IO,Presence granularity each bit indicate the I/O presence" line.long 0x8 "GPIOQ_HWCFGR8,GPIO port Q hardware configuration register 8" hexmask.long.byte 0x8 28.--31. 1. "FAST_AF_IO15,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 24.--27. 1. "FAST_AF_IO14,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 20.--23. 1. "FAST_AF_IO13,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 16.--19. 1. "FAST_AF_IO12,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 12.--15. 1. "FAST_AF_IO11,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 8.--11. 1. "FAST_AF_IO10,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0x8 4.--7. 1. "FAST_AF_IO9,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0x8 0.--3. 1. "FAST_AF_IO8,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0xC "GPIOQ_HWCFGR7,GPIO port Q hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "FAST_AF_IO7,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 24.--27. 1. "FAST_AF_IO6,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 20.--23. 1. "FAST_AF_IO5,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 16.--19. 1. "FAST_AF_IO4,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 12.--15. 1. "FAST_AF_IO3,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 8.--11. 1. "FAST_AF_IO2,Indicate which is the fastest AF for I/Oy (0 to F)" newline hexmask.long.byte 0xC 4.--7. 1. "FAST_AF_IO1,Indicate which is the fastest AF for I/Oy (0 to F)" hexmask.long.byte 0xC 0.--3. 1. "FAST_AF_IO0,Indicate which is the fastest AF for I/Oy (0 to F)" line.long 0x10 "GPIOQ_HWCFGR6,GPIO port Q hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER register reset value" line.long 0x14 "GPIOQ_HWCFGR5,GPIO port Q hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,Pull-up/pull-down register reset value" line.long 0x18 "GPIOQ_HWCFGR4,GPIO port Q hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED register reset value" line.long 0x1C "GPIOQ_HWCFGR3,GPIO port Q hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,Output type register reset value" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,Output data register reset value" line.long 0x20 "GPIOQ_HWCFGR2,GPIO port Q hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AF register low reset value" line.long 0x24 "GPIOQ_HWCFGR1,GPIO port Q hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AF register high reset value" line.long 0x28 "GPIOQ_HWCFGR0,GPIO port Q hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,Option register reset value" line.long 0x2C "GPIOQ_VERR,GPIO port Q version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,GPIO major revision" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,GPIO minor revision" line.long 0x30 "GPIOQ_IPIDR,GPIO port Q identification register" hexmask.long 0x30 0.--31. 1. "IPID,GPIO identifier" line.long 0x34 "GPIOQ_SIDR,GPIO port Q size identification register" hexmask.long 0x34 0.--31. 1. "SID,Size of the memory region allocated to GPIO registers" tree.end tree.end tree "HASH (Hash Processor)" base ad:0x0 tree "HASH" base ad:0x44020400 group.long 0x0++0x3 line.long 0x0 "HASH_CR,HASH control register" hexmask.long.byte 0x0 17.--20. 1. "ALGO,Algorithm selection" bitfld.long 0x0 16. "LKEY,Long key selection" "0: HMAC key is shorter or equal to the block size..,1: HMAC key is longer than the block size (long.." newline bitfld.long 0x0 13. "MDMAT,Multiple DMA transfers" "0: DCAL is automatically set at the end of a DMA..,1: DCAL is not automatically set at the end of a.." rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0: Hash mode selected,1: HMAC mode selected. LKEY bit must be set if the.." newline bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0: 32-bit data. The data written into HASH_DIN are..,1: 16-bit data or half-word. The data written into..,2: 8-bit data or bytes. The data written into..,3: bit data or bit string. The data written into.." bitfld.long 0x0 3. "DMAE,DMA enable" "0: DMA transfers disabled,1: DMA transfers enabled. A DMA request is sent as.." newline bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "HASH_DIN,HASH data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "HASH_STR,HASH start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word" rgroup.long 0xC++0x13 line.long 0x0 "HASH_HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,Hash data x" line.long 0x4 "HASH_HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,Hash data x" line.long 0x8 "HASH_HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,Hash data x" line.long 0xC "HASH_HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,Hash data x" line.long 0x10 "HASH_HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,Hash data x" group.long 0x20++0x7 line.long 0x0 "HASH_IMR,HASH interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0: Digest calculation completion interrupt disabled,1: Digest calculation completion interrupt enabled." bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0: Data input interrupt disabled,1: Data input interrupt enabled" line.long 0x4 "HASH_SR,HASH status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0: No data are present in the data input buffer,1: The input buffer contains at least one word of.." newline hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0: No block is currently being processed,1: The hash core is processing a block of data" newline rbitfld.long 0x4 2. "DMAS,DMA Status" "0: DMA interface is disabled (DMAE = 0) and no..,1: DMA interface is enabled (DMAE = 1) or a.." bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0: No digest available in the HASH_HRx registers..,1: Digest calculation complete a digest is.." newline bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0: Less than 16 locations are free in the input..,1: A new block can be entered into the input.." group.long 0xF8++0x19B line.long 0x0 "HASH_CSR0,HASH context swap register 0" hexmask.long 0x0 0.--31. 1. "CS0,Context swap x" line.long 0x4 "HASH_CSR1,HASH context swap register 1" hexmask.long 0x4 0.--31. 1. "CS1,Context swap x" line.long 0x8 "HASH_CSR2,HASH context swap register 2" hexmask.long 0x8 0.--31. 1. "CS2,Context swap x" line.long 0xC "HASH_CSR3,HASH context swap register 3" hexmask.long 0xC 0.--31. 1. "CS3,Context swap x" line.long 0x10 "HASH_CSR4,HASH context swap register 4" hexmask.long 0x10 0.--31. 1. "CS4,Context swap x" line.long 0x14 "HASH_CSR5,HASH context swap register 5" hexmask.long 0x14 0.--31. 1. "CS5,Context swap x" line.long 0x18 "HASH_CSR6,HASH context swap register 6" hexmask.long 0x18 0.--31. 1. "CS6,Context swap x" line.long 0x1C "HASH_CSR7,HASH context swap register 7" hexmask.long 0x1C 0.--31. 1. "CS7,Context swap x" line.long 0x20 "HASH_CSR8,HASH context swap register 8" hexmask.long 0x20 0.--31. 1. "CS8,Context swap x" line.long 0x24 "HASH_CSR9,HASH context swap register 9" hexmask.long 0x24 0.--31. 1. "CS9,Context swap x" line.long 0x28 "HASH_CSR10,HASH context swap register 10" hexmask.long 0x28 0.--31. 1. "CS10,Context swap x" line.long 0x2C "HASH_CSR11,HASH context swap register 11" hexmask.long 0x2C 0.--31. 1. "CS11,Context swap x" line.long 0x30 "HASH_CSR12,HASH context swap register 12" hexmask.long 0x30 0.--31. 1. "CS12,Context swap x" line.long 0x34 "HASH_CSR13,HASH context swap register 13" hexmask.long 0x34 0.--31. 1. "CS13,Context swap x" line.long 0x38 "HASH_CSR14,HASH context swap register 14" hexmask.long 0x38 0.--31. 1. "CS14,Context swap x" line.long 0x3C "HASH_CSR15,HASH context swap register 15" hexmask.long 0x3C 0.--31. 1. "CS15,Context swap x" line.long 0x40 "HASH_CSR16,HASH context swap register 16" hexmask.long 0x40 0.--31. 1. "CS16,Context swap x" line.long 0x44 "HASH_CSR17,HASH context swap register 17" hexmask.long 0x44 0.--31. 1. "CS17,Context swap x" line.long 0x48 "HASH_CSR18,HASH context swap register 18" hexmask.long 0x48 0.--31. 1. "CS18,Context swap x" line.long 0x4C "HASH_CSR19,HASH context swap register 19" hexmask.long 0x4C 0.--31. 1. "CS19,Context swap x" line.long 0x50 "HASH_CSR20,HASH context swap register 20" hexmask.long 0x50 0.--31. 1. "CS20,Context swap x" line.long 0x54 "HASH_CSR21,HASH context swap register 21" hexmask.long 0x54 0.--31. 1. "CS21,Context swap x" line.long 0x58 "HASH_CSR22,HASH context swap register 22" hexmask.long 0x58 0.--31. 1. "CS22,Context swap x" line.long 0x5C "HASH_CSR23,HASH context swap register 23" hexmask.long 0x5C 0.--31. 1. "CS23,Context swap x" line.long 0x60 "HASH_CSR24,HASH context swap register 24" hexmask.long 0x60 0.--31. 1. "CS24,Context swap x" line.long 0x64 "HASH_CSR25,HASH context swap register 25" hexmask.long 0x64 0.--31. 1. "CS25,Context swap x" line.long 0x68 "HASH_CSR26,HASH context swap register 26" hexmask.long 0x68 0.--31. 1. "CS26,Context swap x" line.long 0x6C "HASH_CSR27,HASH context swap register 27" hexmask.long 0x6C 0.--31. 1. "CS27,Context swap x" line.long 0x70 "HASH_CSR28,HASH context swap register 28" hexmask.long 0x70 0.--31. 1. "CS28,Context swap x" line.long 0x74 "HASH_CSR29,HASH context swap register 29" hexmask.long 0x74 0.--31. 1. "CS29,Context swap x" line.long 0x78 "HASH_CSR30,HASH context swap register 30" hexmask.long 0x78 0.--31. 1. "CS30,Context swap x" line.long 0x7C "HASH_CSR31,HASH context swap register 31" hexmask.long 0x7C 0.--31. 1. "CS31,Context swap x" line.long 0x80 "HASH_CSR32,HASH context swap register 32" hexmask.long 0x80 0.--31. 1. "CS32,Context swap x" line.long 0x84 "HASH_CSR33,HASH context swap register 33" hexmask.long 0x84 0.--31. 1. "CS33,Context swap x" line.long 0x88 "HASH_CSR34,HASH context swap register 34" hexmask.long 0x88 0.--31. 1. "CS34,Context swap x" line.long 0x8C "HASH_CSR35,HASH context swap register 35" hexmask.long 0x8C 0.--31. 1. "CS35,Context swap x" line.long 0x90 "HASH_CSR36,HASH context swap register 36" hexmask.long 0x90 0.--31. 1. "CS36,Context swap x" line.long 0x94 "HASH_CSR37,HASH context swap register 37" hexmask.long 0x94 0.--31. 1. "CS37,Context swap x" line.long 0x98 "HASH_CSR38,HASH context swap register 38" hexmask.long 0x98 0.--31. 1. "CS38,Context swap x" line.long 0x9C "HASH_CSR39,HASH context swap register 39" hexmask.long 0x9C 0.--31. 1. "CS39,Context swap x" line.long 0xA0 "HASH_CSR40,HASH context swap register 40" hexmask.long 0xA0 0.--31. 1. "CS40,Context swap x" line.long 0xA4 "HASH_CSR41,HASH context swap register 41" hexmask.long 0xA4 0.--31. 1. "CS41,Context swap x" line.long 0xA8 "HASH_CSR42,HASH context swap register 42" hexmask.long 0xA8 0.--31. 1. "CS42,Context swap x" line.long 0xAC "HASH_CSR43,HASH context swap register 43" hexmask.long 0xAC 0.--31. 1. "CS43,Context swap x" line.long 0xB0 "HASH_CSR44,HASH context swap register 44" hexmask.long 0xB0 0.--31. 1. "CS44,Context swap x" line.long 0xB4 "HASH_CSR45,HASH context swap register 45" hexmask.long 0xB4 0.--31. 1. "CS45,Context swap x" line.long 0xB8 "HASH_CSR46,HASH context swap register 46" hexmask.long 0xB8 0.--31. 1. "CS46,Context swap x" line.long 0xBC "HASH_CSR47,HASH context swap register 47" hexmask.long 0xBC 0.--31. 1. "CS47,Context swap x" line.long 0xC0 "HASH_CSR48,HASH context swap register 48" hexmask.long 0xC0 0.--31. 1. "CS48,Context swap x" line.long 0xC4 "HASH_CSR49,HASH context swap register 49" hexmask.long 0xC4 0.--31. 1. "CS49,Context swap x" line.long 0xC8 "HASH_CSR50,HASH context swap register 50" hexmask.long 0xC8 0.--31. 1. "CS50,Context swap x" line.long 0xCC "HASH_CSR51,HASH context swap register 51" hexmask.long 0xCC 0.--31. 1. "CS51,Context swap x" line.long 0xD0 "HASH_CSR52,HASH context swap register 52" hexmask.long 0xD0 0.--31. 1. "CS52,Context swap x" line.long 0xD4 "HASH_CSR53,HASH context swap register 53" hexmask.long 0xD4 0.--31. 1. "CS53,Context swap x" line.long 0xD8 "HASH_CSR54,HASH context swap register 54" hexmask.long 0xD8 0.--31. 1. "CS54,Context swap x" line.long 0xDC "HASH_CSR55,HASH context swap register 55" hexmask.long 0xDC 0.--31. 1. "CS55,Context swap x" line.long 0xE0 "HASH_CSR56,HASH context swap register 56" hexmask.long 0xE0 0.--31. 1. "CS56,Context swap x" line.long 0xE4 "HASH_CSR57,HASH context swap register 57" hexmask.long 0xE4 0.--31. 1. "CS57,Context swap x" line.long 0xE8 "HASH_CSR58,HASH context swap register 58" hexmask.long 0xE8 0.--31. 1. "CS58,Context swap x" line.long 0xEC "HASH_CSR59,HASH context swap register 59" hexmask.long 0xEC 0.--31. 1. "CS59,Context swap x" line.long 0xF0 "HASH_CSR60,HASH context swap register 60" hexmask.long 0xF0 0.--31. 1. "CS60,Context swap x" line.long 0xF4 "HASH_CSR61,HASH context swap register 61" hexmask.long 0xF4 0.--31. 1. "CS61,Context swap x" line.long 0xF8 "HASH_CSR62,HASH context swap register 62" hexmask.long 0xF8 0.--31. 1. "CS62,Context swap x" line.long 0xFC "HASH_CSR63,HASH context swap register 63" hexmask.long 0xFC 0.--31. 1. "CS63,Context swap x" line.long 0x100 "HASH_CSR64,HASH context swap register 64" hexmask.long 0x100 0.--31. 1. "CS64,Context swap x" line.long 0x104 "HASH_CSR65,HASH context swap register 65" hexmask.long 0x104 0.--31. 1. "CS65,Context swap x" line.long 0x108 "HASH_CSR66,HASH context swap register 66" hexmask.long 0x108 0.--31. 1. "CS66,Context swap x" line.long 0x10C "HASH_CSR67,HASH context swap register 67" hexmask.long 0x10C 0.--31. 1. "CS67,Context swap x" line.long 0x110 "HASH_CSR68,HASH context swap register 68" hexmask.long 0x110 0.--31. 1. "CS68,Context swap x" line.long 0x114 "HASH_CSR69,HASH context swap register 69" hexmask.long 0x114 0.--31. 1. "CS69,Context swap x" line.long 0x118 "HASH_CSR70,HASH context swap register 70" hexmask.long 0x118 0.--31. 1. "CS70,Context swap x" line.long 0x11C "HASH_CSR71,HASH context swap register 71" hexmask.long 0x11C 0.--31. 1. "CS71,Context swap x" line.long 0x120 "HASH_CSR72,HASH context swap register 72" hexmask.long 0x120 0.--31. 1. "CS72,Context swap x" line.long 0x124 "HASH_CSR73,HASH context swap register 73" hexmask.long 0x124 0.--31. 1. "CS73,Context swap x" line.long 0x128 "HASH_CSR74,HASH context swap register 74" hexmask.long 0x128 0.--31. 1. "CS74,Context swap x" line.long 0x12C "HASH_CSR75,HASH context swap register 75" hexmask.long 0x12C 0.--31. 1. "CS75,Context swap x" line.long 0x130 "HASH_CSR76,HASH context swap register 76" hexmask.long 0x130 0.--31. 1. "CS76,Context swap x" line.long 0x134 "HASH_CSR77,HASH context swap register 77" hexmask.long 0x134 0.--31. 1. "CS77,Context swap x" line.long 0x138 "HASH_CSR78,HASH context swap register 78" hexmask.long 0x138 0.--31. 1. "CS78,Context swap x" line.long 0x13C "HASH_CSR79,HASH context swap register 79" hexmask.long 0x13C 0.--31. 1. "CS79,Context swap x" line.long 0x140 "HASH_CSR80,HASH context swap register 80" hexmask.long 0x140 0.--31. 1. "CS80,Context swap x" line.long 0x144 "HASH_CSR81,HASH context swap register 81" hexmask.long 0x144 0.--31. 1. "CS81,Context swap x" line.long 0x148 "HASH_CSR82,HASH context swap register 82" hexmask.long 0x148 0.--31. 1. "CS82,Context swap x" line.long 0x14C "HASH_CSR83,HASH context swap register 83" hexmask.long 0x14C 0.--31. 1. "CS83,Context swap x" line.long 0x150 "HASH_CSR84,HASH context swap register 84" hexmask.long 0x150 0.--31. 1. "CS84,Context swap x" line.long 0x154 "HASH_CSR85,HASH context swap register 85" hexmask.long 0x154 0.--31. 1. "CS85,Context swap x" line.long 0x158 "HASH_CSR86,HASH context swap register 86" hexmask.long 0x158 0.--31. 1. "CS86,Context swap x" line.long 0x15C "HASH_CSR87,HASH context swap register 87" hexmask.long 0x15C 0.--31. 1. "CS87,Context swap x" line.long 0x160 "HASH_CSR88,HASH context swap register 88" hexmask.long 0x160 0.--31. 1. "CS88,Context swap x" line.long 0x164 "HASH_CSR89,HASH context swap register 89" hexmask.long 0x164 0.--31. 1. "CS89,Context swap x" line.long 0x168 "HASH_CSR90,HASH context swap register 90" hexmask.long 0x168 0.--31. 1. "CS90,Context swap x" line.long 0x16C "HASH_CSR91,HASH context swap register 91" hexmask.long 0x16C 0.--31. 1. "CS91,Context swap x" line.long 0x170 "HASH_CSR92,HASH context swap register 92" hexmask.long 0x170 0.--31. 1. "CS92,Context swap x" line.long 0x174 "HASH_CSR93,HASH context swap register 93" hexmask.long 0x174 0.--31. 1. "CS93,Context swap x" line.long 0x178 "HASH_CSR94,HASH context swap register 94" hexmask.long 0x178 0.--31. 1. "CS94,Context swap x" line.long 0x17C "HASH_CSR95,HASH context swap register 95" hexmask.long 0x17C 0.--31. 1. "CS95,Context swap x" line.long 0x180 "HASH_CSR96,HASH context swap register 96" hexmask.long 0x180 0.--31. 1. "CS96,Context swap x" line.long 0x184 "HASH_CSR97,HASH context swap register 97" hexmask.long 0x184 0.--31. 1. "CS97,Context swap x" line.long 0x188 "HASH_CSR98,HASH context swap register 98" hexmask.long 0x188 0.--31. 1. "CS98,Context swap x" line.long 0x18C "HASH_CSR99,HASH context swap register 99" hexmask.long 0x18C 0.--31. 1. "CS99,Context swap x" line.long 0x190 "HASH_CSR100,HASH context swap register 100" hexmask.long 0x190 0.--31. 1. "CS100,Context swap x" line.long 0x194 "HASH_CSR101,HASH context swap register 101" hexmask.long 0x194 0.--31. 1. "CS101,Context swap x" line.long 0x198 "HASH_CSR102,HASH context swap register 102" hexmask.long 0x198 0.--31. 1. "CS102,Context swap x" rgroup.long 0x310++0x3F line.long 0x0 "HASH_HR0,HASH digest register 0" hexmask.long 0x0 0.--31. 1. "H0,Hash data x" line.long 0x4 "HASH_HR1,HASH digest register 1" hexmask.long 0x4 0.--31. 1. "H1,Hash data x" line.long 0x8 "HASH_HR2,HASH digest register 2" hexmask.long 0x8 0.--31. 1. "H2,Hash data x" line.long 0xC "HASH_HR3,HASH digest register 3" hexmask.long 0xC 0.--31. 1. "H3,Hash data x" line.long 0x10 "HASH_HR4,HASH digest register 4" hexmask.long 0x10 0.--31. 1. "H4,Hash data x" line.long 0x14 "HASH_HR5,HASH supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,Hash data x" line.long 0x18 "HASH_HR6,HASH supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,Hash data x" line.long 0x1C "HASH_HR7,HASH supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,Hash data x" line.long 0x20 "HASH_HR8,HASH supplementary digest register 8" hexmask.long 0x20 0.--31. 1. "H8,Hash data x" line.long 0x24 "HASH_HR9,HASH supplementary digest register 9" hexmask.long 0x24 0.--31. 1. "H9,Hash data x" line.long 0x28 "HASH_HR10,HASH supplementary digest register 10" hexmask.long 0x28 0.--31. 1. "H10,Hash data x" line.long 0x2C "HASH_HR11,HASH supplementary digest register 11" hexmask.long 0x2C 0.--31. 1. "H11,Hash data x" line.long 0x30 "HASH_HR12,HASH supplementary digest register 12" hexmask.long 0x30 0.--31. 1. "H12,Hash data x" line.long 0x34 "HASH_HR13,HASH supplementary digest register 13" hexmask.long 0x34 0.--31. 1. "H13,Hash data x" line.long 0x38 "HASH_HR14,HASH supplementary digest register 14" hexmask.long 0x38 0.--31. 1. "H14,Hash data x" line.long 0x3C "HASH_HR15,HASH supplementary digest register 15" hexmask.long 0x3C 0.--31. 1. "H15,Hash data x" tree.end tree "HASH_S" base ad:0x54020400 group.long 0x0++0x3 line.long 0x0 "HASH_CR,HASH control register" hexmask.long.byte 0x0 17.--20. 1. "ALGO,Algorithm selection" bitfld.long 0x0 16. "LKEY,Long key selection" "0: HMAC key is shorter or equal to the block size..,1: HMAC key is longer than the block size (long.." newline bitfld.long 0x0 13. "MDMAT,Multiple DMA transfers" "0: DCAL is automatically set at the end of a DMA..,1: DCAL is not automatically set at the end of a.." rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" bitfld.long 0x0 6. "MODE,Mode selection" "0: Hash mode selected,1: HMAC mode selected. LKEY bit must be set if the.." newline bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0: 32-bit data. The data written into HASH_DIN are..,1: 16-bit data or half-word. The data written into..,2: 8-bit data or bytes. The data written into..,3: bit data or bit string. The data written into.." bitfld.long 0x0 3. "DMAE,DMA enable" "0: DMA transfers disabled,1: DMA transfers enabled. A DMA request is sent as.." newline bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "HASH_DIN,HASH data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "HASH_STR,HASH start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word" rgroup.long 0xC++0x13 line.long 0x0 "HASH_HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H0,Hash data x" line.long 0x4 "HASH_HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H1,Hash data x" line.long 0x8 "HASH_HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H2,Hash data x" line.long 0xC "HASH_HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H3,Hash data x" line.long 0x10 "HASH_HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H4,Hash data x" group.long 0x20++0x7 line.long 0x0 "HASH_IMR,HASH interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0: Digest calculation completion interrupt disabled,1: Digest calculation completion interrupt enabled." bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0: Data input interrupt disabled,1: Data input interrupt enabled" line.long 0x4 "HASH_SR,HASH status register" hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0: No data are present in the data input buffer,1: The input buffer contains at least one word of.." newline hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0: No block is currently being processed,1: The hash core is processing a block of data" newline rbitfld.long 0x4 2. "DMAS,DMA Status" "0: DMA interface is disabled (DMAE = 0) and no..,1: DMA interface is enabled (DMAE = 1) or a.." bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0: No digest available in the HASH_HRx registers..,1: Digest calculation complete a digest is.." newline bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0: Less than 16 locations are free in the input..,1: A new block can be entered into the input.." group.long 0xF8++0x19B line.long 0x0 "HASH_CSR0,HASH context swap register 0" hexmask.long 0x0 0.--31. 1. "CS0,Context swap x" line.long 0x4 "HASH_CSR1,HASH context swap register 1" hexmask.long 0x4 0.--31. 1. "CS1,Context swap x" line.long 0x8 "HASH_CSR2,HASH context swap register 2" hexmask.long 0x8 0.--31. 1. "CS2,Context swap x" line.long 0xC "HASH_CSR3,HASH context swap register 3" hexmask.long 0xC 0.--31. 1. "CS3,Context swap x" line.long 0x10 "HASH_CSR4,HASH context swap register 4" hexmask.long 0x10 0.--31. 1. "CS4,Context swap x" line.long 0x14 "HASH_CSR5,HASH context swap register 5" hexmask.long 0x14 0.--31. 1. "CS5,Context swap x" line.long 0x18 "HASH_CSR6,HASH context swap register 6" hexmask.long 0x18 0.--31. 1. "CS6,Context swap x" line.long 0x1C "HASH_CSR7,HASH context swap register 7" hexmask.long 0x1C 0.--31. 1. "CS7,Context swap x" line.long 0x20 "HASH_CSR8,HASH context swap register 8" hexmask.long 0x20 0.--31. 1. "CS8,Context swap x" line.long 0x24 "HASH_CSR9,HASH context swap register 9" hexmask.long 0x24 0.--31. 1. "CS9,Context swap x" line.long 0x28 "HASH_CSR10,HASH context swap register 10" hexmask.long 0x28 0.--31. 1. "CS10,Context swap x" line.long 0x2C "HASH_CSR11,HASH context swap register 11" hexmask.long 0x2C 0.--31. 1. "CS11,Context swap x" line.long 0x30 "HASH_CSR12,HASH context swap register 12" hexmask.long 0x30 0.--31. 1. "CS12,Context swap x" line.long 0x34 "HASH_CSR13,HASH context swap register 13" hexmask.long 0x34 0.--31. 1. "CS13,Context swap x" line.long 0x38 "HASH_CSR14,HASH context swap register 14" hexmask.long 0x38 0.--31. 1. "CS14,Context swap x" line.long 0x3C "HASH_CSR15,HASH context swap register 15" hexmask.long 0x3C 0.--31. 1. "CS15,Context swap x" line.long 0x40 "HASH_CSR16,HASH context swap register 16" hexmask.long 0x40 0.--31. 1. "CS16,Context swap x" line.long 0x44 "HASH_CSR17,HASH context swap register 17" hexmask.long 0x44 0.--31. 1. "CS17,Context swap x" line.long 0x48 "HASH_CSR18,HASH context swap register 18" hexmask.long 0x48 0.--31. 1. "CS18,Context swap x" line.long 0x4C "HASH_CSR19,HASH context swap register 19" hexmask.long 0x4C 0.--31. 1. "CS19,Context swap x" line.long 0x50 "HASH_CSR20,HASH context swap register 20" hexmask.long 0x50 0.--31. 1. "CS20,Context swap x" line.long 0x54 "HASH_CSR21,HASH context swap register 21" hexmask.long 0x54 0.--31. 1. "CS21,Context swap x" line.long 0x58 "HASH_CSR22,HASH context swap register 22" hexmask.long 0x58 0.--31. 1. "CS22,Context swap x" line.long 0x5C "HASH_CSR23,HASH context swap register 23" hexmask.long 0x5C 0.--31. 1. "CS23,Context swap x" line.long 0x60 "HASH_CSR24,HASH context swap register 24" hexmask.long 0x60 0.--31. 1. "CS24,Context swap x" line.long 0x64 "HASH_CSR25,HASH context swap register 25" hexmask.long 0x64 0.--31. 1. "CS25,Context swap x" line.long 0x68 "HASH_CSR26,HASH context swap register 26" hexmask.long 0x68 0.--31. 1. "CS26,Context swap x" line.long 0x6C "HASH_CSR27,HASH context swap register 27" hexmask.long 0x6C 0.--31. 1. "CS27,Context swap x" line.long 0x70 "HASH_CSR28,HASH context swap register 28" hexmask.long 0x70 0.--31. 1. "CS28,Context swap x" line.long 0x74 "HASH_CSR29,HASH context swap register 29" hexmask.long 0x74 0.--31. 1. "CS29,Context swap x" line.long 0x78 "HASH_CSR30,HASH context swap register 30" hexmask.long 0x78 0.--31. 1. "CS30,Context swap x" line.long 0x7C "HASH_CSR31,HASH context swap register 31" hexmask.long 0x7C 0.--31. 1. "CS31,Context swap x" line.long 0x80 "HASH_CSR32,HASH context swap register 32" hexmask.long 0x80 0.--31. 1. "CS32,Context swap x" line.long 0x84 "HASH_CSR33,HASH context swap register 33" hexmask.long 0x84 0.--31. 1. "CS33,Context swap x" line.long 0x88 "HASH_CSR34,HASH context swap register 34" hexmask.long 0x88 0.--31. 1. "CS34,Context swap x" line.long 0x8C "HASH_CSR35,HASH context swap register 35" hexmask.long 0x8C 0.--31. 1. "CS35,Context swap x" line.long 0x90 "HASH_CSR36,HASH context swap register 36" hexmask.long 0x90 0.--31. 1. "CS36,Context swap x" line.long 0x94 "HASH_CSR37,HASH context swap register 37" hexmask.long 0x94 0.--31. 1. "CS37,Context swap x" line.long 0x98 "HASH_CSR38,HASH context swap register 38" hexmask.long 0x98 0.--31. 1. "CS38,Context swap x" line.long 0x9C "HASH_CSR39,HASH context swap register 39" hexmask.long 0x9C 0.--31. 1. "CS39,Context swap x" line.long 0xA0 "HASH_CSR40,HASH context swap register 40" hexmask.long 0xA0 0.--31. 1. "CS40,Context swap x" line.long 0xA4 "HASH_CSR41,HASH context swap register 41" hexmask.long 0xA4 0.--31. 1. "CS41,Context swap x" line.long 0xA8 "HASH_CSR42,HASH context swap register 42" hexmask.long 0xA8 0.--31. 1. "CS42,Context swap x" line.long 0xAC "HASH_CSR43,HASH context swap register 43" hexmask.long 0xAC 0.--31. 1. "CS43,Context swap x" line.long 0xB0 "HASH_CSR44,HASH context swap register 44" hexmask.long 0xB0 0.--31. 1. "CS44,Context swap x" line.long 0xB4 "HASH_CSR45,HASH context swap register 45" hexmask.long 0xB4 0.--31. 1. "CS45,Context swap x" line.long 0xB8 "HASH_CSR46,HASH context swap register 46" hexmask.long 0xB8 0.--31. 1. "CS46,Context swap x" line.long 0xBC "HASH_CSR47,HASH context swap register 47" hexmask.long 0xBC 0.--31. 1. "CS47,Context swap x" line.long 0xC0 "HASH_CSR48,HASH context swap register 48" hexmask.long 0xC0 0.--31. 1. "CS48,Context swap x" line.long 0xC4 "HASH_CSR49,HASH context swap register 49" hexmask.long 0xC4 0.--31. 1. "CS49,Context swap x" line.long 0xC8 "HASH_CSR50,HASH context swap register 50" hexmask.long 0xC8 0.--31. 1. "CS50,Context swap x" line.long 0xCC "HASH_CSR51,HASH context swap register 51" hexmask.long 0xCC 0.--31. 1. "CS51,Context swap x" line.long 0xD0 "HASH_CSR52,HASH context swap register 52" hexmask.long 0xD0 0.--31. 1. "CS52,Context swap x" line.long 0xD4 "HASH_CSR53,HASH context swap register 53" hexmask.long 0xD4 0.--31. 1. "CS53,Context swap x" line.long 0xD8 "HASH_CSR54,HASH context swap register 54" hexmask.long 0xD8 0.--31. 1. "CS54,Context swap x" line.long 0xDC "HASH_CSR55,HASH context swap register 55" hexmask.long 0xDC 0.--31. 1. "CS55,Context swap x" line.long 0xE0 "HASH_CSR56,HASH context swap register 56" hexmask.long 0xE0 0.--31. 1. "CS56,Context swap x" line.long 0xE4 "HASH_CSR57,HASH context swap register 57" hexmask.long 0xE4 0.--31. 1. "CS57,Context swap x" line.long 0xE8 "HASH_CSR58,HASH context swap register 58" hexmask.long 0xE8 0.--31. 1. "CS58,Context swap x" line.long 0xEC "HASH_CSR59,HASH context swap register 59" hexmask.long 0xEC 0.--31. 1. "CS59,Context swap x" line.long 0xF0 "HASH_CSR60,HASH context swap register 60" hexmask.long 0xF0 0.--31. 1. "CS60,Context swap x" line.long 0xF4 "HASH_CSR61,HASH context swap register 61" hexmask.long 0xF4 0.--31. 1. "CS61,Context swap x" line.long 0xF8 "HASH_CSR62,HASH context swap register 62" hexmask.long 0xF8 0.--31. 1. "CS62,Context swap x" line.long 0xFC "HASH_CSR63,HASH context swap register 63" hexmask.long 0xFC 0.--31. 1. "CS63,Context swap x" line.long 0x100 "HASH_CSR64,HASH context swap register 64" hexmask.long 0x100 0.--31. 1. "CS64,Context swap x" line.long 0x104 "HASH_CSR65,HASH context swap register 65" hexmask.long 0x104 0.--31. 1. "CS65,Context swap x" line.long 0x108 "HASH_CSR66,HASH context swap register 66" hexmask.long 0x108 0.--31. 1. "CS66,Context swap x" line.long 0x10C "HASH_CSR67,HASH context swap register 67" hexmask.long 0x10C 0.--31. 1. "CS67,Context swap x" line.long 0x110 "HASH_CSR68,HASH context swap register 68" hexmask.long 0x110 0.--31. 1. "CS68,Context swap x" line.long 0x114 "HASH_CSR69,HASH context swap register 69" hexmask.long 0x114 0.--31. 1. "CS69,Context swap x" line.long 0x118 "HASH_CSR70,HASH context swap register 70" hexmask.long 0x118 0.--31. 1. "CS70,Context swap x" line.long 0x11C "HASH_CSR71,HASH context swap register 71" hexmask.long 0x11C 0.--31. 1. "CS71,Context swap x" line.long 0x120 "HASH_CSR72,HASH context swap register 72" hexmask.long 0x120 0.--31. 1. "CS72,Context swap x" line.long 0x124 "HASH_CSR73,HASH context swap register 73" hexmask.long 0x124 0.--31. 1. "CS73,Context swap x" line.long 0x128 "HASH_CSR74,HASH context swap register 74" hexmask.long 0x128 0.--31. 1. "CS74,Context swap x" line.long 0x12C "HASH_CSR75,HASH context swap register 75" hexmask.long 0x12C 0.--31. 1. "CS75,Context swap x" line.long 0x130 "HASH_CSR76,HASH context swap register 76" hexmask.long 0x130 0.--31. 1. "CS76,Context swap x" line.long 0x134 "HASH_CSR77,HASH context swap register 77" hexmask.long 0x134 0.--31. 1. "CS77,Context swap x" line.long 0x138 "HASH_CSR78,HASH context swap register 78" hexmask.long 0x138 0.--31. 1. "CS78,Context swap x" line.long 0x13C "HASH_CSR79,HASH context swap register 79" hexmask.long 0x13C 0.--31. 1. "CS79,Context swap x" line.long 0x140 "HASH_CSR80,HASH context swap register 80" hexmask.long 0x140 0.--31. 1. "CS80,Context swap x" line.long 0x144 "HASH_CSR81,HASH context swap register 81" hexmask.long 0x144 0.--31. 1. "CS81,Context swap x" line.long 0x148 "HASH_CSR82,HASH context swap register 82" hexmask.long 0x148 0.--31. 1. "CS82,Context swap x" line.long 0x14C "HASH_CSR83,HASH context swap register 83" hexmask.long 0x14C 0.--31. 1. "CS83,Context swap x" line.long 0x150 "HASH_CSR84,HASH context swap register 84" hexmask.long 0x150 0.--31. 1. "CS84,Context swap x" line.long 0x154 "HASH_CSR85,HASH context swap register 85" hexmask.long 0x154 0.--31. 1. "CS85,Context swap x" line.long 0x158 "HASH_CSR86,HASH context swap register 86" hexmask.long 0x158 0.--31. 1. "CS86,Context swap x" line.long 0x15C "HASH_CSR87,HASH context swap register 87" hexmask.long 0x15C 0.--31. 1. "CS87,Context swap x" line.long 0x160 "HASH_CSR88,HASH context swap register 88" hexmask.long 0x160 0.--31. 1. "CS88,Context swap x" line.long 0x164 "HASH_CSR89,HASH context swap register 89" hexmask.long 0x164 0.--31. 1. "CS89,Context swap x" line.long 0x168 "HASH_CSR90,HASH context swap register 90" hexmask.long 0x168 0.--31. 1. "CS90,Context swap x" line.long 0x16C "HASH_CSR91,HASH context swap register 91" hexmask.long 0x16C 0.--31. 1. "CS91,Context swap x" line.long 0x170 "HASH_CSR92,HASH context swap register 92" hexmask.long 0x170 0.--31. 1. "CS92,Context swap x" line.long 0x174 "HASH_CSR93,HASH context swap register 93" hexmask.long 0x174 0.--31. 1. "CS93,Context swap x" line.long 0x178 "HASH_CSR94,HASH context swap register 94" hexmask.long 0x178 0.--31. 1. "CS94,Context swap x" line.long 0x17C "HASH_CSR95,HASH context swap register 95" hexmask.long 0x17C 0.--31. 1. "CS95,Context swap x" line.long 0x180 "HASH_CSR96,HASH context swap register 96" hexmask.long 0x180 0.--31. 1. "CS96,Context swap x" line.long 0x184 "HASH_CSR97,HASH context swap register 97" hexmask.long 0x184 0.--31. 1. "CS97,Context swap x" line.long 0x188 "HASH_CSR98,HASH context swap register 98" hexmask.long 0x188 0.--31. 1. "CS98,Context swap x" line.long 0x18C "HASH_CSR99,HASH context swap register 99" hexmask.long 0x18C 0.--31. 1. "CS99,Context swap x" line.long 0x190 "HASH_CSR100,HASH context swap register 100" hexmask.long 0x190 0.--31. 1. "CS100,Context swap x" line.long 0x194 "HASH_CSR101,HASH context swap register 101" hexmask.long 0x194 0.--31. 1. "CS101,Context swap x" line.long 0x198 "HASH_CSR102,HASH context swap register 102" hexmask.long 0x198 0.--31. 1. "CS102,Context swap x" rgroup.long 0x310++0x3F line.long 0x0 "HASH_HR0,HASH digest register 0" hexmask.long 0x0 0.--31. 1. "H0,Hash data x" line.long 0x4 "HASH_HR1,HASH digest register 1" hexmask.long 0x4 0.--31. 1. "H1,Hash data x" line.long 0x8 "HASH_HR2,HASH digest register 2" hexmask.long 0x8 0.--31. 1. "H2,Hash data x" line.long 0xC "HASH_HR3,HASH digest register 3" hexmask.long 0xC 0.--31. 1. "H3,Hash data x" line.long 0x10 "HASH_HR4,HASH digest register 4" hexmask.long 0x10 0.--31. 1. "H4,Hash data x" line.long 0x14 "HASH_HR5,HASH supplementary digest register 5" hexmask.long 0x14 0.--31. 1. "H5,Hash data x" line.long 0x18 "HASH_HR6,HASH supplementary digest register 6" hexmask.long 0x18 0.--31. 1. "H6,Hash data x" line.long 0x1C "HASH_HR7,HASH supplementary digest register 7" hexmask.long 0x1C 0.--31. 1. "H7,Hash data x" line.long 0x20 "HASH_HR8,HASH supplementary digest register 8" hexmask.long 0x20 0.--31. 1. "H8,Hash data x" line.long 0x24 "HASH_HR9,HASH supplementary digest register 9" hexmask.long 0x24 0.--31. 1. "H9,Hash data x" line.long 0x28 "HASH_HR10,HASH supplementary digest register 10" hexmask.long 0x28 0.--31. 1. "H10,Hash data x" line.long 0x2C "HASH_HR11,HASH supplementary digest register 11" hexmask.long 0x2C 0.--31. 1. "H11,Hash data x" line.long 0x30 "HASH_HR12,HASH supplementary digest register 12" hexmask.long 0x30 0.--31. 1. "H12,Hash data x" line.long 0x34 "HASH_HR13,HASH supplementary digest register 13" hexmask.long 0x34 0.--31. 1. "H13,Hash data x" line.long 0x38 "HASH_HR14,HASH supplementary digest register 14" hexmask.long 0x38 0.--31. 1. "H14,Hash data x" line.long 0x3C "HASH_HR15,HASH supplementary digest register 15" hexmask.long 0x3C 0.--31. 1. "H15,Hash data x" tree.end tree.end tree "HDP (Hardware Debug Port)" base ad:0x0 tree "HDP" base ad:0x46000800 group.long 0x0++0x7 line.long 0x0 "HDP_CTRL,HDP control register" bitfld.long 0x0 0. "EN,Enable HDP valid if enabled in BSEC" "0,1" line.long 0x4 "HDP_MUX,HDP multiplexer control register" hexmask.long.byte 0x4 28.--31. 1. "MUX7,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 24.--27. 1. "MUX6,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 20.--23. 1. "MUX5,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 16.--19. 1. "MUX4,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 12.--15. 1. "MUX3,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 8.--11. 1. "MUX2,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 4.--7. 1. "MUX1,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 0.--3. 1. "MUX0,Select the HDPy output among the 16 available signals" rgroup.long 0x10++0x3 line.long 0x0 "HDP_VAL,HDP read back value register" hexmask.long.byte 0x0 0.--7. 1. "HDPVAL,Value of the HDP signals" wgroup.long 0x14++0x7 line.long 0x0 "HDP_GPOSET,HDP general-purpose output set register" hexmask.long.byte 0x0 0.--7. 1. "HDPGPOSET,When a bit is written to 1 the corresponding HDP GPO is set" line.long 0x4 "HDP_GPOCLR,HDP general purpose output clear register" hexmask.long.byte 0x4 0.--7. 1. "HDPGPOCLR,When a bit is written to 1 the corresponding HDP GPO is cleared." group.long 0x1C++0x3 line.long 0x0 "HDP_GPOVAL,HDP general purpose output value register" hexmask.long.byte 0x0 0.--7. 1. "HDPGPOVAL,When written define the value of the HDP GPO." tree.end tree "HDP_S" base ad:0x56000800 group.long 0x0++0x7 line.long 0x0 "HDP_CTRL,HDP control register" bitfld.long 0x0 0. "EN,Enable HDP valid if enabled in BSEC" "0,1" line.long 0x4 "HDP_MUX,HDP multiplexer control register" hexmask.long.byte 0x4 28.--31. 1. "MUX7,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 24.--27. 1. "MUX6,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 20.--23. 1. "MUX5,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 16.--19. 1. "MUX4,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 12.--15. 1. "MUX3,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 8.--11. 1. "MUX2,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 4.--7. 1. "MUX1,Select the HDPy output among the 16 available signals" hexmask.long.byte 0x4 0.--3. 1. "MUX0,Select the HDPy output among the 16 available signals" rgroup.long 0x10++0x3 line.long 0x0 "HDP_VAL,HDP read back value register" hexmask.long.byte 0x0 0.--7. 1. "HDPVAL,Value of the HDP signals" wgroup.long 0x14++0x7 line.long 0x0 "HDP_GPOSET,HDP general-purpose output set register" hexmask.long.byte 0x0 0.--7. 1. "HDPGPOSET,When a bit is written to 1 the corresponding HDP GPO is set" line.long 0x4 "HDP_GPOCLR,HDP general purpose output clear register" hexmask.long.byte 0x4 0.--7. 1. "HDPGPOCLR,When a bit is written to 1 the corresponding HDP GPO is cleared." group.long 0x1C++0x3 line.long 0x0 "HDP_GPOVAL,HDP general purpose output value register" hexmask.long.byte 0x0 0.--7. 1. "HDPGPOVAL,When written define the value of the HDP GPO." tree.end tree.end tree "HPDMA (High-performance Direct Memory Access Controller)" base ad:0x0 sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "HPDMA" base ad:0x48020000 group.long 0x0++0xB line.long 0x0 "HPDMA_SECCFGR,HPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "HPDMA_PRIVCFGR,HPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "HPDMA_RCFGLOCKR,HPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 14. "LOCK14,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 12. "LOCK12,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 10. "LOCK10,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 8. "LOCK8,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 6. "LOCK6,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 4. "LOCK4,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 2. "LOCK2,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 0. "LOCK0,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." rgroup.long 0xC++0x7 line.long 0x0 "HPDMA_MISR,HPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "HPDMA_SMISR,HPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0xB line.long 0x0 "HPDMA_C0LBAR,HPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x4 "HPDMA_C0CIDCFGR,HPDMA channel 0 CID register" bitfld.long 0x4 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x4 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x4 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x4 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x4 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x4 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x4 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0x8 "HPDMA_C0SEMCR,HPDMA channel 0 semaphore control register" rbitfld.long 0x8 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0x8 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5C++0x3 line.long 0x0 "HPDMA_C0FCR,HPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "HPDMA_C0SR,HPDMA channel 0 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "HPDMA_C0CR,HPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "HPDMA_C0TR1,HPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C0TR2,HPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C0BR1,HPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C0SAR,HPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C0DAR,HPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0xF line.long 0x0 "HPDMA_C0LLR,HPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C1LBAR,HPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C1CIDCFGR,HPDMA channel 1 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C1SEMCR,HPDMA channel 1 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0xDC++0x3 line.long 0x0 "HPDMA_C1FCR,HPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "HPDMA_C1SR,HPDMA channel 1 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "HPDMA_C1CR,HPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "HPDMA_C1TR1,HPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C1TR2,HPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C1BR1,HPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C1SAR,HPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C1DAR,HPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0xF line.long 0x0 "HPDMA_C1LLR,HPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C2LBAR,HPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C2CIDCFGR,HPDMA channel 2 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C2SEMCR,HPDMA channel 2 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x15C++0x3 line.long 0x0 "HPDMA_C2FCR,HPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "HPDMA_C2SR,HPDMA channel 2 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "HPDMA_C2CR,HPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "HPDMA_C2TR1,HPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C2TR2,HPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C2BR1,HPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C2SAR,HPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C2DAR,HPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0xF line.long 0x0 "HPDMA_C2LLR,HPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C3LBAR,HPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C3CIDCFGR,HPDMA channel 3 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C3SEMCR,HPDMA channel 3 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x1DC++0x3 line.long 0x0 "HPDMA_C3FCR,HPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "HPDMA_C3SR,HPDMA channel 3 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "HPDMA_C3CR,HPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "HPDMA_C3TR1,HPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C3TR2,HPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C3BR1,HPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C3SAR,HPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C3DAR,HPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0xF line.long 0x0 "HPDMA_C3LLR,HPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C4LBAR,HPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C4CIDCFGR,HPDMA channel 4 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C4SEMCR,HPDMA channel 4 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x25C++0x3 line.long 0x0 "HPDMA_C4FCR,HPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "HPDMA_C4SR,HPDMA channel 4 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "HPDMA_C4CR,HPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "HPDMA_C4TR1,HPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C4TR2,HPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C4BR1,HPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C4SAR,HPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C4DAR,HPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0xF line.long 0x0 "HPDMA_C4LLR,HPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C5LBAR,HPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C5CIDCFGR,HPDMA channel 5 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C5SEMCR,HPDMA channel 5 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x2DC++0x3 line.long 0x0 "HPDMA_C5FCR,HPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "HPDMA_C5SR,HPDMA channel 5 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "HPDMA_C5CR,HPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "HPDMA_C5TR1,HPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C5TR2,HPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C5BR1,HPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C5SAR,HPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C5DAR,HPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0xF line.long 0x0 "HPDMA_C5LLR,HPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C6LBAR,HPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C6CIDCFGR,HPDMA channel 6 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C6SEMCR,HPDMA channel 6 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x35C++0x3 line.long 0x0 "HPDMA_C6FCR,HPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "HPDMA_C6SR,HPDMA channel 6 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "HPDMA_C6CR,HPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "HPDMA_C6TR1,HPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C6TR2,HPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C6BR1,HPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C6SAR,HPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C6DAR,HPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0xF line.long 0x0 "HPDMA_C6LLR,HPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C7LBAR,HPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C7CIDCFGR,HPDMA channel 7 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C7SEMCR,HPDMA channel 7 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x3DC++0x3 line.long 0x0 "HPDMA_C7FCR,HPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "HPDMA_C7SR,HPDMA channel 7 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "HPDMA_C7CR,HPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "HPDMA_C7TR1,HPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C7TR2,HPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C7BR1,HPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C7SAR,HPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C7DAR,HPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0xF line.long 0x0 "HPDMA_C7LLR,HPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C8LBAR,HPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C8CIDCFGR,HPDMA channel 8 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C8SEMCR,HPDMA channel 8 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x45C++0x3 line.long 0x0 "HPDMA_C8FCR,HPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "HPDMA_C8SR,HPDMA channel 8 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "HPDMA_C8CR,HPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "HPDMA_C8TR1,HPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C8TR2,HPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C8BR1,HPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C8SAR,HPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C8DAR,HPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0xF line.long 0x0 "HPDMA_C8LLR,HPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C9LBAR,HPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C9CIDCFGR,HPDMA channel 9 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C9SEMCR,HPDMA channel 9 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x4DC++0x3 line.long 0x0 "HPDMA_C9FCR,HPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "HPDMA_C9SR,HPDMA channel 9 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "HPDMA_C9CR,HPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "HPDMA_C9TR1,HPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C9TR2,HPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C9BR1,HPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C9SAR,HPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C9DAR,HPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0xF line.long 0x0 "HPDMA_C9LLR,HPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C10LBAR,HPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C10CIDCFGR,HPDMA channel 10 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C10SEMCR,HPDMA channel 10 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x55C++0x3 line.long 0x0 "HPDMA_C10FCR,HPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "HPDMA_C10SR,HPDMA channel 10 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "HPDMA_C10CR,HPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "HPDMA_C10TR1,HPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C10TR2,HPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C10BR1,HPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C10SAR,HPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C10DAR,HPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0xF line.long 0x0 "HPDMA_C10LLR,HPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C11LBAR,HPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C11CIDCFGR,HPDMA channel 11 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C11SEMCR,HPDMA channel 11 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5DC++0x3 line.long 0x0 "HPDMA_C11FCR,HPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "HPDMA_C11SR,HPDMA channel 11 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "HPDMA_C11CR,HPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "HPDMA_C11TR1,HPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C11TR2,HPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C11BR1,HPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C11SAR,HPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C11DAR,HPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0xF line.long 0x0 "HPDMA_C11LLR,HPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C12LBAR,HPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C12CIDCFGR,HPDMA channel 12 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C12SEMCR,HPDMA channel 12 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x65C++0x3 line.long 0x0 "HPDMA_C12FCR,HPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "HPDMA_C12SR,HPDMA channel 12 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "HPDMA_C12CR,HPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "HPDMA_C12TR1,HPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C12TR2,HPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C12BR1,HPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C12SAR,HPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C12DAR,HPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C12TR3,HPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C12BR2,HPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0xF line.long 0x0 "HPDMA_C12LLR,HPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C13LBAR,HPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C13CIDCFGR,HPDMA channel 13 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C13SEMCR,HPDMA channel 13 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x6DC++0x3 line.long 0x0 "HPDMA_C13FCR,HPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "HPDMA_C13SR,HPDMA channel 13 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "HPDMA_C13CR,HPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "HPDMA_C13TR1,HPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C13TR2,HPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C13BR1,HPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C13SAR,HPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C13DAR,HPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C13TR3,HPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C13BR2,HPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0xF line.long 0x0 "HPDMA_C13LLR,HPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C14LBAR,HPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C14CIDCFGR,HPDMA channel 14 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C14SEMCR,HPDMA channel 14 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x75C++0x3 line.long 0x0 "HPDMA_C14FCR,HPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "HPDMA_C14SR,HPDMA channel 14 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "HPDMA_C14CR,HPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "HPDMA_C14TR1,HPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C14TR2,HPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C14BR1,HPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C14SAR,HPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C14DAR,HPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C14TR3,HPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C14BR2,HPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0xF line.long 0x0 "HPDMA_C14LLR,HPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C15LBAR,HPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C15CIDCFGR,HPDMA channel 15 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C15SEMCR,HPDMA channel 15 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x7DC++0x3 line.long 0x0 "HPDMA_C15FCR,HPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "HPDMA_C15SR,HPDMA channel 15 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "HPDMA_C15CR,HPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "HPDMA_C15TR1,HPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C15TR2,HPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C15BR1,HPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C15SAR,HPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C15DAR,HPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C15TR3,HPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C15BR2,HPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "HPDMA_C15LLR,HPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32N655*")) tree "HPDMA" base ad:0x48020000 group.long 0x0++0xB line.long 0x0 "HPDMA_SECCFGR,HPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "HPDMA_PRIVCFGR,HPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "HPDMA_RCFGLOCKR,HPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 14. "LOCK14,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 12. "LOCK12,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 10. "LOCK10,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 8. "LOCK8,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 6. "LOCK6,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 4. "LOCK4,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 2. "LOCK2,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 0. "LOCK0,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." rgroup.long 0xC++0x7 line.long 0x0 "HPDMA_MISR,HPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "HPDMA_SMISR,HPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0xB line.long 0x0 "HPDMA_C0LBAR,HPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x4 "HPDMA_C0CIDCFGR,HPDMA channel 0 CID register" bitfld.long 0x4 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x4 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x4 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x4 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x4 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x4 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x4 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0x8 "HPDMA_C0SEMCR,HPDMA channel 0 semaphore control register" rbitfld.long 0x8 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0x8 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5C++0x3 line.long 0x0 "HPDMA_C0FCR,HPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "HPDMA_C0SR,HPDMA channel 0 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "HPDMA_C0CR,HPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "HPDMA_C0TR1,HPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C0TR2,HPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C0BR1,HPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C0SAR,HPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C0DAR,HPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0xF line.long 0x0 "HPDMA_C0LLR,HPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C1LBAR,HPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C1CIDCFGR,HPDMA channel 1 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C1SEMCR,HPDMA channel 1 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0xDC++0x3 line.long 0x0 "HPDMA_C1FCR,HPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "HPDMA_C1SR,HPDMA channel 1 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "HPDMA_C1CR,HPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "HPDMA_C1TR1,HPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C1TR2,HPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C1BR1,HPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C1SAR,HPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C1DAR,HPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0xF line.long 0x0 "HPDMA_C1LLR,HPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C2LBAR,HPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C2CIDCFGR,HPDMA channel 2 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C2SEMCR,HPDMA channel 2 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x15C++0x3 line.long 0x0 "HPDMA_C2FCR,HPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "HPDMA_C2SR,HPDMA channel 2 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "HPDMA_C2CR,HPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "HPDMA_C2TR1,HPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C2TR2,HPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C2BR1,HPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C2SAR,HPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C2DAR,HPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0xF line.long 0x0 "HPDMA_C2LLR,HPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C3LBAR,HPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C3CIDCFGR,HPDMA channel 3 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C3SEMCR,HPDMA channel 3 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x1DC++0x3 line.long 0x0 "HPDMA_C3FCR,HPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "HPDMA_C3SR,HPDMA channel 3 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "HPDMA_C3CR,HPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "HPDMA_C3TR1,HPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C3TR2,HPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C3BR1,HPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C3SAR,HPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C3DAR,HPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0xF line.long 0x0 "HPDMA_C3LLR,HPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C4LBAR,HPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C4CIDCFGR,HPDMA channel 4 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C4SEMCR,HPDMA channel 4 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x25C++0x3 line.long 0x0 "HPDMA_C4FCR,HPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "HPDMA_C4SR,HPDMA channel 4 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "HPDMA_C4CR,HPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "HPDMA_C4TR1,HPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C4TR2,HPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C4BR1,HPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C4SAR,HPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C4DAR,HPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0xF line.long 0x0 "HPDMA_C4LLR,HPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C5LBAR,HPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C5CIDCFGR,HPDMA channel 5 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C5SEMCR,HPDMA channel 5 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x2DC++0x3 line.long 0x0 "HPDMA_C5FCR,HPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "HPDMA_C5SR,HPDMA channel 5 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "HPDMA_C5CR,HPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "HPDMA_C5TR1,HPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C5TR2,HPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C5BR1,HPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C5SAR,HPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C5DAR,HPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0xF line.long 0x0 "HPDMA_C5LLR,HPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C6LBAR,HPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C6CIDCFGR,HPDMA channel 6 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C6SEMCR,HPDMA channel 6 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x35C++0x3 line.long 0x0 "HPDMA_C6FCR,HPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "HPDMA_C6SR,HPDMA channel 6 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "HPDMA_C6CR,HPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "HPDMA_C6TR1,HPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C6TR2,HPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C6BR1,HPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C6SAR,HPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C6DAR,HPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0xF line.long 0x0 "HPDMA_C6LLR,HPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C7LBAR,HPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C7CIDCFGR,HPDMA channel 7 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C7SEMCR,HPDMA channel 7 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x3DC++0x3 line.long 0x0 "HPDMA_C7FCR,HPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "HPDMA_C7SR,HPDMA channel 7 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "HPDMA_C7CR,HPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "HPDMA_C7TR1,HPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C7TR2,HPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C7BR1,HPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C7SAR,HPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C7DAR,HPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0xF line.long 0x0 "HPDMA_C7LLR,HPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C8LBAR,HPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C8CIDCFGR,HPDMA channel 8 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C8SEMCR,HPDMA channel 8 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x45C++0x3 line.long 0x0 "HPDMA_C8FCR,HPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "HPDMA_C8SR,HPDMA channel 8 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "HPDMA_C8CR,HPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "HPDMA_C8TR1,HPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C8TR2,HPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C8BR1,HPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C8SAR,HPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C8DAR,HPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0xF line.long 0x0 "HPDMA_C8LLR,HPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C9LBAR,HPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C9CIDCFGR,HPDMA channel 9 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C9SEMCR,HPDMA channel 9 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x4DC++0x3 line.long 0x0 "HPDMA_C9FCR,HPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "HPDMA_C9SR,HPDMA channel 9 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "HPDMA_C9CR,HPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "HPDMA_C9TR1,HPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C9TR2,HPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C9BR1,HPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C9SAR,HPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C9DAR,HPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0xF line.long 0x0 "HPDMA_C9LLR,HPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C10LBAR,HPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C10CIDCFGR,HPDMA channel 10 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C10SEMCR,HPDMA channel 10 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x55C++0x3 line.long 0x0 "HPDMA_C10FCR,HPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "HPDMA_C10SR,HPDMA channel 10 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "HPDMA_C10CR,HPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "HPDMA_C10TR1,HPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C10TR2,HPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C10BR1,HPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C10SAR,HPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C10DAR,HPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0xF line.long 0x0 "HPDMA_C10LLR,HPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C11LBAR,HPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C11CIDCFGR,HPDMA channel 11 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C11SEMCR,HPDMA channel 11 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5DC++0x3 line.long 0x0 "HPDMA_C11FCR,HPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "HPDMA_C11SR,HPDMA channel 11 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "HPDMA_C11CR,HPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "HPDMA_C11TR1,HPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C11TR2,HPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C11BR1,HPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C11SAR,HPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C11DAR,HPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0xF line.long 0x0 "HPDMA_C11LLR,HPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C12LBAR,HPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C12CIDCFGR,HPDMA channel 12 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C12SEMCR,HPDMA channel 12 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x65C++0x3 line.long 0x0 "HPDMA_C12FCR,HPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "HPDMA_C12SR,HPDMA channel 12 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "HPDMA_C12CR,HPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "HPDMA_C12TR1,HPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C12TR2,HPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C12BR1,HPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C12SAR,HPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C12DAR,HPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C12TR3,HPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C12BR2,HPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0xF line.long 0x0 "HPDMA_C12LLR,HPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C13LBAR,HPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C13CIDCFGR,HPDMA channel 13 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C13SEMCR,HPDMA channel 13 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x6DC++0x3 line.long 0x0 "HPDMA_C13FCR,HPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "HPDMA_C13SR,HPDMA channel 13 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "HPDMA_C13CR,HPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "HPDMA_C13TR1,HPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C13TR2,HPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C13BR1,HPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C13SAR,HPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C13DAR,HPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C13TR3,HPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C13BR2,HPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0xF line.long 0x0 "HPDMA_C13LLR,HPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C14LBAR,HPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C14CIDCFGR,HPDMA channel 14 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C14SEMCR,HPDMA channel 14 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x75C++0x3 line.long 0x0 "HPDMA_C14FCR,HPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "HPDMA_C14SR,HPDMA channel 14 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "HPDMA_C14CR,HPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "HPDMA_C14TR1,HPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C14TR2,HPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C14BR1,HPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C14SAR,HPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C14DAR,HPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C14TR3,HPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C14BR2,HPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0xF line.long 0x0 "HPDMA_C14LLR,HPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C15LBAR,HPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C15CIDCFGR,HPDMA channel 15 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C15SEMCR,HPDMA channel 15 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x7DC++0x3 line.long 0x0 "HPDMA_C15FCR,HPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "HPDMA_C15SR,HPDMA channel 15 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "HPDMA_C15CR,HPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "HPDMA_C15TR1,HPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C15TR2,HPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C15BR1,HPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C15SAR,HPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C15DAR,HPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C15TR3,HPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C15BR2,HPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "HPDMA_C15LLR,HPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32N657*")) tree "HPDMA" base ad:0x48020000 group.long 0x0++0xB line.long 0x0 "HPDMA_SECCFGR,HPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "HPDMA_PRIVCFGR,HPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "HPDMA_RCFGLOCKR,HPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 14. "LOCK14,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 12. "LOCK12,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 10. "LOCK10,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 8. "LOCK8,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 6. "LOCK6,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 4. "LOCK4,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 2. "LOCK2,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 0. "LOCK0,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." rgroup.long 0xC++0x7 line.long 0x0 "HPDMA_MISR,HPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "HPDMA_SMISR,HPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0xB line.long 0x0 "HPDMA_C0LBAR,HPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x4 "HPDMA_C0CIDCFGR,HPDMA channel 0 CID register" bitfld.long 0x4 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x4 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x4 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x4 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x4 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x4 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x4 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0x8 "HPDMA_C0SEMCR,HPDMA channel 0 semaphore control register" rbitfld.long 0x8 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0x8 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5C++0x3 line.long 0x0 "HPDMA_C0FCR,HPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "HPDMA_C0SR,HPDMA channel 0 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "HPDMA_C0CR,HPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "HPDMA_C0TR1,HPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C0TR2,HPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C0BR1,HPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C0SAR,HPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C0DAR,HPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0xF line.long 0x0 "HPDMA_C0LLR,HPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C1LBAR,HPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C1CIDCFGR,HPDMA channel 1 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C1SEMCR,HPDMA channel 1 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0xDC++0x3 line.long 0x0 "HPDMA_C1FCR,HPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "HPDMA_C1SR,HPDMA channel 1 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "HPDMA_C1CR,HPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "HPDMA_C1TR1,HPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C1TR2,HPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C1BR1,HPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C1SAR,HPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C1DAR,HPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0xF line.long 0x0 "HPDMA_C1LLR,HPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C2LBAR,HPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C2CIDCFGR,HPDMA channel 2 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C2SEMCR,HPDMA channel 2 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x15C++0x3 line.long 0x0 "HPDMA_C2FCR,HPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "HPDMA_C2SR,HPDMA channel 2 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "HPDMA_C2CR,HPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "HPDMA_C2TR1,HPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C2TR2,HPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C2BR1,HPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C2SAR,HPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C2DAR,HPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0xF line.long 0x0 "HPDMA_C2LLR,HPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C3LBAR,HPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C3CIDCFGR,HPDMA channel 3 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C3SEMCR,HPDMA channel 3 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x1DC++0x3 line.long 0x0 "HPDMA_C3FCR,HPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "HPDMA_C3SR,HPDMA channel 3 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "HPDMA_C3CR,HPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "HPDMA_C3TR1,HPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C3TR2,HPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C3BR1,HPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C3SAR,HPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C3DAR,HPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0xF line.long 0x0 "HPDMA_C3LLR,HPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C4LBAR,HPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C4CIDCFGR,HPDMA channel 4 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C4SEMCR,HPDMA channel 4 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x25C++0x3 line.long 0x0 "HPDMA_C4FCR,HPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "HPDMA_C4SR,HPDMA channel 4 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "HPDMA_C4CR,HPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "HPDMA_C4TR1,HPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C4TR2,HPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C4BR1,HPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C4SAR,HPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C4DAR,HPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0xF line.long 0x0 "HPDMA_C4LLR,HPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C5LBAR,HPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C5CIDCFGR,HPDMA channel 5 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C5SEMCR,HPDMA channel 5 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x2DC++0x3 line.long 0x0 "HPDMA_C5FCR,HPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "HPDMA_C5SR,HPDMA channel 5 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "HPDMA_C5CR,HPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "HPDMA_C5TR1,HPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C5TR2,HPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C5BR1,HPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C5SAR,HPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C5DAR,HPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0xF line.long 0x0 "HPDMA_C5LLR,HPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C6LBAR,HPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C6CIDCFGR,HPDMA channel 6 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C6SEMCR,HPDMA channel 6 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x35C++0x3 line.long 0x0 "HPDMA_C6FCR,HPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "HPDMA_C6SR,HPDMA channel 6 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "HPDMA_C6CR,HPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "HPDMA_C6TR1,HPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C6TR2,HPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C6BR1,HPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C6SAR,HPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C6DAR,HPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0xF line.long 0x0 "HPDMA_C6LLR,HPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C7LBAR,HPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C7CIDCFGR,HPDMA channel 7 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C7SEMCR,HPDMA channel 7 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x3DC++0x3 line.long 0x0 "HPDMA_C7FCR,HPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "HPDMA_C7SR,HPDMA channel 7 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "HPDMA_C7CR,HPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "HPDMA_C7TR1,HPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C7TR2,HPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C7BR1,HPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C7SAR,HPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C7DAR,HPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0xF line.long 0x0 "HPDMA_C7LLR,HPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C8LBAR,HPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C8CIDCFGR,HPDMA channel 8 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C8SEMCR,HPDMA channel 8 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x45C++0x3 line.long 0x0 "HPDMA_C8FCR,HPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "HPDMA_C8SR,HPDMA channel 8 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "HPDMA_C8CR,HPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "HPDMA_C8TR1,HPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C8TR2,HPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C8BR1,HPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C8SAR,HPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C8DAR,HPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0xF line.long 0x0 "HPDMA_C8LLR,HPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C9LBAR,HPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C9CIDCFGR,HPDMA channel 9 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C9SEMCR,HPDMA channel 9 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x4DC++0x3 line.long 0x0 "HPDMA_C9FCR,HPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "HPDMA_C9SR,HPDMA channel 9 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "HPDMA_C9CR,HPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "HPDMA_C9TR1,HPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C9TR2,HPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C9BR1,HPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C9SAR,HPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C9DAR,HPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0xF line.long 0x0 "HPDMA_C9LLR,HPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C10LBAR,HPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C10CIDCFGR,HPDMA channel 10 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C10SEMCR,HPDMA channel 10 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x55C++0x3 line.long 0x0 "HPDMA_C10FCR,HPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "HPDMA_C10SR,HPDMA channel 10 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "HPDMA_C10CR,HPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "HPDMA_C10TR1,HPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C10TR2,HPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C10BR1,HPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C10SAR,HPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C10DAR,HPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0xF line.long 0x0 "HPDMA_C10LLR,HPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C11LBAR,HPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C11CIDCFGR,HPDMA channel 11 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C11SEMCR,HPDMA channel 11 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5DC++0x3 line.long 0x0 "HPDMA_C11FCR,HPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "HPDMA_C11SR,HPDMA channel 11 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "HPDMA_C11CR,HPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "HPDMA_C11TR1,HPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C11TR2,HPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C11BR1,HPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C11SAR,HPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C11DAR,HPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0xF line.long 0x0 "HPDMA_C11LLR,HPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C12LBAR,HPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C12CIDCFGR,HPDMA channel 12 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C12SEMCR,HPDMA channel 12 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x65C++0x3 line.long 0x0 "HPDMA_C12FCR,HPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "HPDMA_C12SR,HPDMA channel 12 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "HPDMA_C12CR,HPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "HPDMA_C12TR1,HPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C12TR2,HPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C12BR1,HPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C12SAR,HPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C12DAR,HPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C12TR3,HPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C12BR2,HPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0xF line.long 0x0 "HPDMA_C12LLR,HPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C13LBAR,HPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C13CIDCFGR,HPDMA channel 13 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C13SEMCR,HPDMA channel 13 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x6DC++0x3 line.long 0x0 "HPDMA_C13FCR,HPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "HPDMA_C13SR,HPDMA channel 13 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "HPDMA_C13CR,HPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "HPDMA_C13TR1,HPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C13TR2,HPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C13BR1,HPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C13SAR,HPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C13DAR,HPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C13TR3,HPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C13BR2,HPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0xF line.long 0x0 "HPDMA_C13LLR,HPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C14LBAR,HPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C14CIDCFGR,HPDMA channel 14 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C14SEMCR,HPDMA channel 14 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x75C++0x3 line.long 0x0 "HPDMA_C14FCR,HPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "HPDMA_C14SR,HPDMA channel 14 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "HPDMA_C14CR,HPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "HPDMA_C14TR1,HPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C14TR2,HPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C14BR1,HPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C14SAR,HPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C14DAR,HPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C14TR3,HPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C14BR2,HPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0xF line.long 0x0 "HPDMA_C14LLR,HPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C15LBAR,HPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C15CIDCFGR,HPDMA channel 15 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C15SEMCR,HPDMA channel 15 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x7DC++0x3 line.long 0x0 "HPDMA_C15FCR,HPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "HPDMA_C15SR,HPDMA channel 15 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "HPDMA_C15CR,HPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "HPDMA_C15TR1,HPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C15TR2,HPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C15BR1,HPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C15SAR,HPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C15DAR,HPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C15TR3,HPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C15BR2,HPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "HPDMA_C15LLR,HPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "HPDMA_S" base ad:0x58020000 group.long 0x0++0xB line.long 0x0 "HPDMA_SECCFGR,HPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "HPDMA_PRIVCFGR,HPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "HPDMA_RCFGLOCKR,HPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 14. "LOCK14,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 12. "LOCK12,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 10. "LOCK10,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 8. "LOCK8,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 6. "LOCK6,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 4. "LOCK4,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 2. "LOCK2,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 0. "LOCK0,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." rgroup.long 0xC++0x7 line.long 0x0 "HPDMA_MISR,HPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "HPDMA_SMISR,HPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0xB line.long 0x0 "HPDMA_C0LBAR,HPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x4 "HPDMA_C0CIDCFGR,HPDMA channel 0 CID register" bitfld.long 0x4 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x4 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x4 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x4 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x4 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x4 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x4 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0x8 "HPDMA_C0SEMCR,HPDMA channel 0 semaphore control register" rbitfld.long 0x8 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0x8 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5C++0x3 line.long 0x0 "HPDMA_C0FCR,HPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "HPDMA_C0SR,HPDMA channel 0 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "HPDMA_C0CR,HPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "HPDMA_C0TR1,HPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C0TR2,HPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C0BR1,HPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C0SAR,HPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C0DAR,HPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0xF line.long 0x0 "HPDMA_C0LLR,HPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C1LBAR,HPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C1CIDCFGR,HPDMA channel 1 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C1SEMCR,HPDMA channel 1 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0xDC++0x3 line.long 0x0 "HPDMA_C1FCR,HPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "HPDMA_C1SR,HPDMA channel 1 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "HPDMA_C1CR,HPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "HPDMA_C1TR1,HPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C1TR2,HPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C1BR1,HPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C1SAR,HPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C1DAR,HPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0xF line.long 0x0 "HPDMA_C1LLR,HPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C2LBAR,HPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C2CIDCFGR,HPDMA channel 2 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C2SEMCR,HPDMA channel 2 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x15C++0x3 line.long 0x0 "HPDMA_C2FCR,HPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "HPDMA_C2SR,HPDMA channel 2 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "HPDMA_C2CR,HPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "HPDMA_C2TR1,HPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C2TR2,HPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C2BR1,HPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C2SAR,HPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C2DAR,HPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0xF line.long 0x0 "HPDMA_C2LLR,HPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C3LBAR,HPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C3CIDCFGR,HPDMA channel 3 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C3SEMCR,HPDMA channel 3 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x1DC++0x3 line.long 0x0 "HPDMA_C3FCR,HPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "HPDMA_C3SR,HPDMA channel 3 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "HPDMA_C3CR,HPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "HPDMA_C3TR1,HPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C3TR2,HPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C3BR1,HPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C3SAR,HPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C3DAR,HPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0xF line.long 0x0 "HPDMA_C3LLR,HPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C4LBAR,HPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C4CIDCFGR,HPDMA channel 4 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C4SEMCR,HPDMA channel 4 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x25C++0x3 line.long 0x0 "HPDMA_C4FCR,HPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "HPDMA_C4SR,HPDMA channel 4 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "HPDMA_C4CR,HPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "HPDMA_C4TR1,HPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C4TR2,HPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C4BR1,HPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C4SAR,HPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C4DAR,HPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0xF line.long 0x0 "HPDMA_C4LLR,HPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C5LBAR,HPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C5CIDCFGR,HPDMA channel 5 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C5SEMCR,HPDMA channel 5 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x2DC++0x3 line.long 0x0 "HPDMA_C5FCR,HPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "HPDMA_C5SR,HPDMA channel 5 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "HPDMA_C5CR,HPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "HPDMA_C5TR1,HPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C5TR2,HPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C5BR1,HPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C5SAR,HPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C5DAR,HPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0xF line.long 0x0 "HPDMA_C5LLR,HPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C6LBAR,HPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C6CIDCFGR,HPDMA channel 6 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C6SEMCR,HPDMA channel 6 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x35C++0x3 line.long 0x0 "HPDMA_C6FCR,HPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "HPDMA_C6SR,HPDMA channel 6 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "HPDMA_C6CR,HPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "HPDMA_C6TR1,HPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C6TR2,HPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C6BR1,HPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C6SAR,HPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C6DAR,HPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0xF line.long 0x0 "HPDMA_C6LLR,HPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C7LBAR,HPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C7CIDCFGR,HPDMA channel 7 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C7SEMCR,HPDMA channel 7 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x3DC++0x3 line.long 0x0 "HPDMA_C7FCR,HPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "HPDMA_C7SR,HPDMA channel 7 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "HPDMA_C7CR,HPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "HPDMA_C7TR1,HPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C7TR2,HPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C7BR1,HPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C7SAR,HPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C7DAR,HPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0xF line.long 0x0 "HPDMA_C7LLR,HPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C8LBAR,HPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C8CIDCFGR,HPDMA channel 8 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C8SEMCR,HPDMA channel 8 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x45C++0x3 line.long 0x0 "HPDMA_C8FCR,HPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "HPDMA_C8SR,HPDMA channel 8 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "HPDMA_C8CR,HPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "HPDMA_C8TR1,HPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C8TR2,HPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C8BR1,HPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C8SAR,HPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C8DAR,HPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0xF line.long 0x0 "HPDMA_C8LLR,HPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C9LBAR,HPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C9CIDCFGR,HPDMA channel 9 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C9SEMCR,HPDMA channel 9 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x4DC++0x3 line.long 0x0 "HPDMA_C9FCR,HPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "HPDMA_C9SR,HPDMA channel 9 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "HPDMA_C9CR,HPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "HPDMA_C9TR1,HPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C9TR2,HPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C9BR1,HPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C9SAR,HPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C9DAR,HPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0xF line.long 0x0 "HPDMA_C9LLR,HPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C10LBAR,HPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C10CIDCFGR,HPDMA channel 10 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C10SEMCR,HPDMA channel 10 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x55C++0x3 line.long 0x0 "HPDMA_C10FCR,HPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "HPDMA_C10SR,HPDMA channel 10 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "HPDMA_C10CR,HPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "HPDMA_C10TR1,HPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." sif (cpuis("STM32N645*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,?,?" newline endif sif (cpuis("STM32N647*")) bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." endif hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" newline bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C10TR2,HPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C10BR1,HPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C10SAR,HPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C10DAR,HPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0xF line.long 0x0 "HPDMA_C10LLR,HPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C11LBAR,HPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C11CIDCFGR,HPDMA channel 11 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C11SEMCR,HPDMA channel 11 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5DC++0x3 line.long 0x0 "HPDMA_C11FCR,HPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "HPDMA_C11SR,HPDMA channel 11 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "HPDMA_C11CR,HPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "HPDMA_C11TR1,HPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C11TR2,HPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C11BR1,HPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C11SAR,HPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C11DAR,HPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0xF line.long 0x0 "HPDMA_C11LLR,HPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C12LBAR,HPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C12CIDCFGR,HPDMA channel 12 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C12SEMCR,HPDMA channel 12 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x65C++0x3 line.long 0x0 "HPDMA_C12FCR,HPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "HPDMA_C12SR,HPDMA channel 12 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "HPDMA_C12CR,HPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "HPDMA_C12TR1,HPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C12TR2,HPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C12BR1,HPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C12SAR,HPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C12DAR,HPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C12TR3,HPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C12BR2,HPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0xF line.long 0x0 "HPDMA_C12LLR,HPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C13LBAR,HPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C13CIDCFGR,HPDMA channel 13 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C13SEMCR,HPDMA channel 13 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x6DC++0x3 line.long 0x0 "HPDMA_C13FCR,HPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "HPDMA_C13SR,HPDMA channel 13 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "HPDMA_C13CR,HPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "HPDMA_C13TR1,HPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C13TR2,HPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C13BR1,HPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C13SAR,HPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C13DAR,HPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C13TR3,HPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C13BR2,HPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0xF line.long 0x0 "HPDMA_C13LLR,HPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C14LBAR,HPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C14CIDCFGR,HPDMA channel 14 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C14SEMCR,HPDMA channel 14 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x75C++0x3 line.long 0x0 "HPDMA_C14FCR,HPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "HPDMA_C14SR,HPDMA channel 14 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "HPDMA_C14CR,HPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "HPDMA_C14TR1,HPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C14TR2,HPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C14BR1,HPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C14SAR,HPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C14DAR,HPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C14TR3,HPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C14BR2,HPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0xF line.long 0x0 "HPDMA_C14LLR,HPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C15LBAR,HPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C15CIDCFGR,HPDMA channel 15 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C15SEMCR,HPDMA channel 15 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x7DC++0x3 line.long 0x0 "HPDMA_C15FCR,HPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "HPDMA_C15SR,HPDMA channel 15 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "HPDMA_C15CR,HPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "HPDMA_C15TR1,HPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C15TR2,HPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C15BR1,HPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C15SAR,HPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C15DAR,HPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C15TR3,HPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C15BR2,HPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "HPDMA_C15LLR,HPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32N655*")) tree "HPDMA_S" base ad:0x58020000 group.long 0x0++0xB line.long 0x0 "HPDMA_SECCFGR,HPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "HPDMA_PRIVCFGR,HPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "HPDMA_RCFGLOCKR,HPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 14. "LOCK14,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 12. "LOCK12,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 10. "LOCK10,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 8. "LOCK8,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 6. "LOCK6,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 4. "LOCK4,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 2. "LOCK2,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 0. "LOCK0,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." rgroup.long 0xC++0x7 line.long 0x0 "HPDMA_MISR,HPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "HPDMA_SMISR,HPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0xB line.long 0x0 "HPDMA_C0LBAR,HPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x4 "HPDMA_C0CIDCFGR,HPDMA channel 0 CID register" bitfld.long 0x4 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x4 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x4 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x4 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x4 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x4 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x4 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0x8 "HPDMA_C0SEMCR,HPDMA channel 0 semaphore control register" rbitfld.long 0x8 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0x8 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5C++0x3 line.long 0x0 "HPDMA_C0FCR,HPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "HPDMA_C0SR,HPDMA channel 0 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "HPDMA_C0CR,HPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "HPDMA_C0TR1,HPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C0TR2,HPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C0BR1,HPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C0SAR,HPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C0DAR,HPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0xF line.long 0x0 "HPDMA_C0LLR,HPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C1LBAR,HPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C1CIDCFGR,HPDMA channel 1 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C1SEMCR,HPDMA channel 1 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0xDC++0x3 line.long 0x0 "HPDMA_C1FCR,HPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "HPDMA_C1SR,HPDMA channel 1 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "HPDMA_C1CR,HPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "HPDMA_C1TR1,HPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C1TR2,HPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C1BR1,HPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C1SAR,HPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C1DAR,HPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0xF line.long 0x0 "HPDMA_C1LLR,HPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C2LBAR,HPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C2CIDCFGR,HPDMA channel 2 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C2SEMCR,HPDMA channel 2 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x15C++0x3 line.long 0x0 "HPDMA_C2FCR,HPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "HPDMA_C2SR,HPDMA channel 2 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "HPDMA_C2CR,HPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "HPDMA_C2TR1,HPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C2TR2,HPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C2BR1,HPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C2SAR,HPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C2DAR,HPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0xF line.long 0x0 "HPDMA_C2LLR,HPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C3LBAR,HPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C3CIDCFGR,HPDMA channel 3 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C3SEMCR,HPDMA channel 3 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x1DC++0x3 line.long 0x0 "HPDMA_C3FCR,HPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "HPDMA_C3SR,HPDMA channel 3 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "HPDMA_C3CR,HPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "HPDMA_C3TR1,HPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C3TR2,HPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C3BR1,HPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C3SAR,HPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C3DAR,HPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0xF line.long 0x0 "HPDMA_C3LLR,HPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C4LBAR,HPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C4CIDCFGR,HPDMA channel 4 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C4SEMCR,HPDMA channel 4 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x25C++0x3 line.long 0x0 "HPDMA_C4FCR,HPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "HPDMA_C4SR,HPDMA channel 4 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "HPDMA_C4CR,HPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "HPDMA_C4TR1,HPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C4TR2,HPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C4BR1,HPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C4SAR,HPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C4DAR,HPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0xF line.long 0x0 "HPDMA_C4LLR,HPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C5LBAR,HPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C5CIDCFGR,HPDMA channel 5 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C5SEMCR,HPDMA channel 5 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x2DC++0x3 line.long 0x0 "HPDMA_C5FCR,HPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "HPDMA_C5SR,HPDMA channel 5 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "HPDMA_C5CR,HPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "HPDMA_C5TR1,HPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C5TR2,HPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C5BR1,HPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C5SAR,HPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C5DAR,HPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0xF line.long 0x0 "HPDMA_C5LLR,HPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C6LBAR,HPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C6CIDCFGR,HPDMA channel 6 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C6SEMCR,HPDMA channel 6 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x35C++0x3 line.long 0x0 "HPDMA_C6FCR,HPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "HPDMA_C6SR,HPDMA channel 6 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "HPDMA_C6CR,HPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "HPDMA_C6TR1,HPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C6TR2,HPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C6BR1,HPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C6SAR,HPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C6DAR,HPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0xF line.long 0x0 "HPDMA_C6LLR,HPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C7LBAR,HPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C7CIDCFGR,HPDMA channel 7 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C7SEMCR,HPDMA channel 7 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x3DC++0x3 line.long 0x0 "HPDMA_C7FCR,HPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "HPDMA_C7SR,HPDMA channel 7 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "HPDMA_C7CR,HPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "HPDMA_C7TR1,HPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C7TR2,HPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C7BR1,HPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C7SAR,HPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C7DAR,HPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0xF line.long 0x0 "HPDMA_C7LLR,HPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C8LBAR,HPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C8CIDCFGR,HPDMA channel 8 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C8SEMCR,HPDMA channel 8 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x45C++0x3 line.long 0x0 "HPDMA_C8FCR,HPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "HPDMA_C8SR,HPDMA channel 8 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "HPDMA_C8CR,HPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "HPDMA_C8TR1,HPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C8TR2,HPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C8BR1,HPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C8SAR,HPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C8DAR,HPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0xF line.long 0x0 "HPDMA_C8LLR,HPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C9LBAR,HPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C9CIDCFGR,HPDMA channel 9 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C9SEMCR,HPDMA channel 9 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x4DC++0x3 line.long 0x0 "HPDMA_C9FCR,HPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "HPDMA_C9SR,HPDMA channel 9 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "HPDMA_C9CR,HPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "HPDMA_C9TR1,HPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C9TR2,HPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C9BR1,HPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C9SAR,HPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C9DAR,HPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0xF line.long 0x0 "HPDMA_C9LLR,HPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C10LBAR,HPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C10CIDCFGR,HPDMA channel 10 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C10SEMCR,HPDMA channel 10 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x55C++0x3 line.long 0x0 "HPDMA_C10FCR,HPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "HPDMA_C10SR,HPDMA channel 10 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "HPDMA_C10CR,HPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "HPDMA_C10TR1,HPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C10TR2,HPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C10BR1,HPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C10SAR,HPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C10DAR,HPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0xF line.long 0x0 "HPDMA_C10LLR,HPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C11LBAR,HPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C11CIDCFGR,HPDMA channel 11 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C11SEMCR,HPDMA channel 11 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5DC++0x3 line.long 0x0 "HPDMA_C11FCR,HPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "HPDMA_C11SR,HPDMA channel 11 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "HPDMA_C11CR,HPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "HPDMA_C11TR1,HPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C11TR2,HPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C11BR1,HPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C11SAR,HPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C11DAR,HPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0xF line.long 0x0 "HPDMA_C11LLR,HPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C12LBAR,HPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C12CIDCFGR,HPDMA channel 12 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C12SEMCR,HPDMA channel 12 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x65C++0x3 line.long 0x0 "HPDMA_C12FCR,HPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "HPDMA_C12SR,HPDMA channel 12 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "HPDMA_C12CR,HPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "HPDMA_C12TR1,HPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C12TR2,HPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C12BR1,HPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C12SAR,HPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C12DAR,HPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C12TR3,HPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C12BR2,HPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0xF line.long 0x0 "HPDMA_C12LLR,HPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C13LBAR,HPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C13CIDCFGR,HPDMA channel 13 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C13SEMCR,HPDMA channel 13 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x6DC++0x3 line.long 0x0 "HPDMA_C13FCR,HPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "HPDMA_C13SR,HPDMA channel 13 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "HPDMA_C13CR,HPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "HPDMA_C13TR1,HPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C13TR2,HPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C13BR1,HPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C13SAR,HPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C13DAR,HPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C13TR3,HPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C13BR2,HPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0xF line.long 0x0 "HPDMA_C13LLR,HPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C14LBAR,HPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C14CIDCFGR,HPDMA channel 14 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C14SEMCR,HPDMA channel 14 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x75C++0x3 line.long 0x0 "HPDMA_C14FCR,HPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "HPDMA_C14SR,HPDMA channel 14 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "HPDMA_C14CR,HPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "HPDMA_C14TR1,HPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C14TR2,HPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C14BR1,HPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C14SAR,HPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C14DAR,HPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C14TR3,HPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C14BR2,HPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0xF line.long 0x0 "HPDMA_C14LLR,HPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C15LBAR,HPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C15CIDCFGR,HPDMA channel 15 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C15SEMCR,HPDMA channel 15 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x7DC++0x3 line.long 0x0 "HPDMA_C15FCR,HPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "HPDMA_C15SR,HPDMA channel 15 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "HPDMA_C15CR,HPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "HPDMA_C15TR1,HPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C15TR2,HPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C15BR1,HPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C15SAR,HPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C15DAR,HPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C15TR3,HPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C15BR2,HPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "HPDMA_C15LLR,HPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif sif (cpuis("STM32N657*")) tree "HPDMA_S" base ad:0x58020000 group.long 0x0++0xB line.long 0x0 "HPDMA_SECCFGR,HPDMA secure configuration register" bitfld.long 0x0 15. "SEC15,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 14. "SEC14,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 13. "SEC13,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 12. "SEC12,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 11. "SEC11,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 10. "SEC10,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 9. "SEC9,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 8. "SEC8,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 7. "SEC7,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 6. "SEC6,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 5. "SEC5,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 4. "SEC4,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 3. "SEC3,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 2. "SEC2,secure state of channel x" "0: non-secure,1: secure" newline bitfld.long 0x0 1. "SEC1,secure state of channel x" "0: non-secure,1: secure" bitfld.long 0x0 0. "SEC0,secure state of channel x" "0: non-secure,1: secure" line.long 0x4 "HPDMA_PRIVCFGR,HPDMA privileged configuration register" bitfld.long 0x4 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged" newline bitfld.long 0x4 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged" bitfld.long 0x4 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged" line.long 0x8 "HPDMA_RCFGLOCKR,HPDMA configuration lock register" bitfld.long 0x8 15. "LOCK15,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 14. "LOCK14,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 13. "LOCK13,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 12. "LOCK12,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 11. "LOCK11,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 10. "LOCK10,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 9. "LOCK9,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 8. "LOCK8,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 7. "LOCK7,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 6. "LOCK6,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 5. "LOCK5,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 4. "LOCK4,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 3. "LOCK3,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 2. "LOCK2,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." newline bitfld.long 0x8 1. "LOCK1,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." bitfld.long 0x8 0. "LOCK0,lock the configuration of HPDMA_SECCFGR.SECx HPDMA_PRIVCFGR.PRIVx and HPDMA_CxCIDCFGR until a global HPDMA reset" "0: secure privilege and CID configuration of the..,1: secure privilege and CID configuration of the.." rgroup.long 0xC++0x7 line.long 0x0 "HPDMA_MISR,HPDMA non-secure masked interrupt status register" bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" newline bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x" line.long 0x4 "HPDMA_SMISR,HPDMA secure masked interrupt status register" bitfld.long 0x4 15. "MIS15,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 14. "MIS14,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 13. "MIS13,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 12. "MIS12,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 11. "MIS11,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 10. "MIS10,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 9. "MIS9,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 8. "MIS8,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 7. "MIS7,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 6. "MIS6,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 5. "MIS5,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 4. "MIS4,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 3. "MIS3,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 2. "MIS2,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" newline bitfld.long 0x4 1. "MIS1,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" bitfld.long 0x4 0. "MIS0,masked interrupt status of the secure channel x" "0: no interrupt occurred on the secure channel x,1: an interrupt occurred on the secure channel x" group.long 0x50++0xB line.long 0x0 "HPDMA_C0LBAR,HPDMA channel 0 linked-list base address register" hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x4 "HPDMA_C0CIDCFGR,HPDMA channel 0 CID register" bitfld.long 0x4 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x4 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x4 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x4 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x4 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x4 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x4 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x4 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0x8 "HPDMA_C0SEMCR,HPDMA channel 0 semaphore control register" rbitfld.long 0x8 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0x8 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5C++0x3 line.long 0x0 "HPDMA_C0FCR,HPDMA channel 0 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x60++0x3 line.long 0x0 "HPDMA_C0SR,HPDMA channel 0 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x64++0x3 line.long 0x0 "HPDMA_C0CR,HPDMA channel 0 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x90++0x13 line.long 0x0 "HPDMA_C0TR1,HPDMA channel 0 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C0TR2,HPDMA channel 0 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C0BR1,HPDMA channel 0 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C0SAR,HPDMA channel 0 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C0DAR,HPDMA channel 0 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0xCC++0xF line.long 0x0 "HPDMA_C0LLR,HPDMA channel 0 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C1LBAR,HPDMA channel 1 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C1CIDCFGR,HPDMA channel 1 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C1SEMCR,HPDMA channel 1 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0xDC++0x3 line.long 0x0 "HPDMA_C1FCR,HPDMA channel 1 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0xE0++0x3 line.long 0x0 "HPDMA_C1SR,HPDMA channel 1 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0xE4++0x3 line.long 0x0 "HPDMA_C1CR,HPDMA channel 1 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x110++0x13 line.long 0x0 "HPDMA_C1TR1,HPDMA channel 1 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C1TR2,HPDMA channel 1 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C1BR1,HPDMA channel 1 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C1SAR,HPDMA channel 1 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C1DAR,HPDMA channel 1 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x14C++0xF line.long 0x0 "HPDMA_C1LLR,HPDMA channel 1 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C2LBAR,HPDMA channel 2 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C2CIDCFGR,HPDMA channel 2 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C2SEMCR,HPDMA channel 2 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x15C++0x3 line.long 0x0 "HPDMA_C2FCR,HPDMA channel 2 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x160++0x3 line.long 0x0 "HPDMA_C2SR,HPDMA channel 2 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x164++0x3 line.long 0x0 "HPDMA_C2CR,HPDMA channel 2 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x190++0x13 line.long 0x0 "HPDMA_C2TR1,HPDMA channel 2 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C2TR2,HPDMA channel 2 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C2BR1,HPDMA channel 2 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C2SAR,HPDMA channel 2 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C2DAR,HPDMA channel 2 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x1CC++0xF line.long 0x0 "HPDMA_C2LLR,HPDMA channel 2 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C3LBAR,HPDMA channel 3 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C3CIDCFGR,HPDMA channel 3 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C3SEMCR,HPDMA channel 3 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x1DC++0x3 line.long 0x0 "HPDMA_C3FCR,HPDMA channel 3 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x1E0++0x3 line.long 0x0 "HPDMA_C3SR,HPDMA channel 3 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x1E4++0x3 line.long 0x0 "HPDMA_C3CR,HPDMA channel 3 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x210++0x13 line.long 0x0 "HPDMA_C3TR1,HPDMA channel 3 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C3TR2,HPDMA channel 3 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C3BR1,HPDMA channel 3 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C3SAR,HPDMA channel 3 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C3DAR,HPDMA channel 3 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x24C++0xF line.long 0x0 "HPDMA_C3LLR,HPDMA channel 3 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C4LBAR,HPDMA channel 4 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C4CIDCFGR,HPDMA channel 4 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C4SEMCR,HPDMA channel 4 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x25C++0x3 line.long 0x0 "HPDMA_C4FCR,HPDMA channel 4 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x260++0x3 line.long 0x0 "HPDMA_C4SR,HPDMA channel 4 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x264++0x3 line.long 0x0 "HPDMA_C4CR,HPDMA channel 4 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x290++0x13 line.long 0x0 "HPDMA_C4TR1,HPDMA channel 4 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C4TR2,HPDMA channel 4 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C4BR1,HPDMA channel 4 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C4SAR,HPDMA channel 4 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C4DAR,HPDMA channel 4 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x2CC++0xF line.long 0x0 "HPDMA_C4LLR,HPDMA channel 4 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C5LBAR,HPDMA channel 5 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C5CIDCFGR,HPDMA channel 5 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C5SEMCR,HPDMA channel 5 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x2DC++0x3 line.long 0x0 "HPDMA_C5FCR,HPDMA channel 5 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x2E0++0x3 line.long 0x0 "HPDMA_C5SR,HPDMA channel 5 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x2E4++0x3 line.long 0x0 "HPDMA_C5CR,HPDMA channel 5 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x310++0x13 line.long 0x0 "HPDMA_C5TR1,HPDMA channel 5 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C5TR2,HPDMA channel 5 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C5BR1,HPDMA channel 5 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C5SAR,HPDMA channel 5 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C5DAR,HPDMA channel 5 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x34C++0xF line.long 0x0 "HPDMA_C5LLR,HPDMA channel 5 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C6LBAR,HPDMA channel 6 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C6CIDCFGR,HPDMA channel 6 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C6SEMCR,HPDMA channel 6 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x35C++0x3 line.long 0x0 "HPDMA_C6FCR,HPDMA channel 6 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x360++0x3 line.long 0x0 "HPDMA_C6SR,HPDMA channel 6 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x364++0x3 line.long 0x0 "HPDMA_C6CR,HPDMA channel 6 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x390++0x13 line.long 0x0 "HPDMA_C6TR1,HPDMA channel 6 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C6TR2,HPDMA channel 6 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C6BR1,HPDMA channel 6 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C6SAR,HPDMA channel 6 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C6DAR,HPDMA channel 6 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x3CC++0xF line.long 0x0 "HPDMA_C6LLR,HPDMA channel 6 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C7LBAR,HPDMA channel 7 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C7CIDCFGR,HPDMA channel 7 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C7SEMCR,HPDMA channel 7 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x3DC++0x3 line.long 0x0 "HPDMA_C7FCR,HPDMA channel 7 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x3E0++0x3 line.long 0x0 "HPDMA_C7SR,HPDMA channel 7 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x3E4++0x3 line.long 0x0 "HPDMA_C7CR,HPDMA channel 7 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x410++0x13 line.long 0x0 "HPDMA_C7TR1,HPDMA channel 7 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C7TR2,HPDMA channel 7 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C7BR1,HPDMA channel 7 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C7SAR,HPDMA channel 7 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C7DAR,HPDMA channel 7 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x44C++0xF line.long 0x0 "HPDMA_C7LLR,HPDMA channel 7 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C8LBAR,HPDMA channel 8 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C8CIDCFGR,HPDMA channel 8 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C8SEMCR,HPDMA channel 8 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x45C++0x3 line.long 0x0 "HPDMA_C8FCR,HPDMA channel 8 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x460++0x3 line.long 0x0 "HPDMA_C8SR,HPDMA channel 8 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x464++0x3 line.long 0x0 "HPDMA_C8CR,HPDMA channel 8 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x490++0x13 line.long 0x0 "HPDMA_C8TR1,HPDMA channel 8 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C8TR2,HPDMA channel 8 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C8BR1,HPDMA channel 8 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C8SAR,HPDMA channel 8 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C8DAR,HPDMA channel 8 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x4CC++0xF line.long 0x0 "HPDMA_C8LLR,HPDMA channel 8 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C9LBAR,HPDMA channel 9 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C9CIDCFGR,HPDMA channel 9 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C9SEMCR,HPDMA channel 9 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x4DC++0x3 line.long 0x0 "HPDMA_C9FCR,HPDMA channel 9 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x4E0++0x3 line.long 0x0 "HPDMA_C9SR,HPDMA channel 9 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x4E4++0x3 line.long 0x0 "HPDMA_C9CR,HPDMA channel 9 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x510++0x13 line.long 0x0 "HPDMA_C9TR1,HPDMA channel 9 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C9TR2,HPDMA channel 9 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C9BR1,HPDMA channel 9 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C9SAR,HPDMA channel 9 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C9DAR,HPDMA channel 9 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x54C++0xF line.long 0x0 "HPDMA_C9LLR,HPDMA channel 9 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C10LBAR,HPDMA channel 10 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C10CIDCFGR,HPDMA channel 10 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C10SEMCR,HPDMA channel 10 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x55C++0x3 line.long 0x0 "HPDMA_C10FCR,HPDMA channel 10 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x560++0x3 line.long 0x0 "HPDMA_C10SR,HPDMA channel 10 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x564++0x3 line.long 0x0 "HPDMA_C10CR,HPDMA channel 10 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x590++0x13 line.long 0x0 "HPDMA_C10TR1,HPDMA channel 10 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C10TR2,HPDMA channel 10 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C10BR1,HPDMA channel 10 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C10SAR,HPDMA channel 10 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C10DAR,HPDMA channel 10 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x5CC++0xF line.long 0x0 "HPDMA_C10LLR,HPDMA channel 10 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C11LBAR,HPDMA channel 11 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C11CIDCFGR,HPDMA channel 11 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C11SEMCR,HPDMA channel 11 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x5DC++0x3 line.long 0x0 "HPDMA_C11FCR,HPDMA channel 11 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x5E0++0x3 line.long 0x0 "HPDMA_C11SR,HPDMA channel 11 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x5E4++0x3 line.long 0x0 "HPDMA_C11CR,HPDMA channel 11 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x610++0x13 line.long 0x0 "HPDMA_C11TR1,HPDMA channel 11 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C11TR2,HPDMA channel 11 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C11BR1,HPDMA channel 11 block register 1" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C11SAR,HPDMA channel 11 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C11DAR,HPDMA channel 11 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" group.long 0x64C++0xF line.long 0x0 "HPDMA_C11LLR,HPDMA channel 11 linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C12LBAR,HPDMA channel 12 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C12CIDCFGR,HPDMA channel 12 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C12SEMCR,HPDMA channel 12 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x65C++0x3 line.long 0x0 "HPDMA_C12FCR,HPDMA channel 12 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x660++0x3 line.long 0x0 "HPDMA_C12SR,HPDMA channel 12 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x664++0x3 line.long 0x0 "HPDMA_C12CR,HPDMA channel 12 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x690++0x1B line.long 0x0 "HPDMA_C12TR1,HPDMA channel 12 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C12TR2,HPDMA channel 12 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C12BR1,HPDMA channel 12 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C12SAR,HPDMA channel 12 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C12DAR,HPDMA channel 12 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C12TR3,HPDMA channel 12 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C12BR2,HPDMA channel 12 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x6CC++0xF line.long 0x0 "HPDMA_C12LLR,HPDMA channel 12 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C13LBAR,HPDMA channel 13 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C13CIDCFGR,HPDMA channel 13 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C13SEMCR,HPDMA channel 13 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x6DC++0x3 line.long 0x0 "HPDMA_C13FCR,HPDMA channel 13 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x6E0++0x3 line.long 0x0 "HPDMA_C13SR,HPDMA channel 13 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x6E4++0x3 line.long 0x0 "HPDMA_C13CR,HPDMA channel 13 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x710++0x1B line.long 0x0 "HPDMA_C13TR1,HPDMA channel 13 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C13TR2,HPDMA channel 13 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C13BR1,HPDMA channel 13 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C13SAR,HPDMA channel 13 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C13DAR,HPDMA channel 13 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C13TR3,HPDMA channel 13 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C13BR2,HPDMA channel 13 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x74C++0xF line.long 0x0 "HPDMA_C13LLR,HPDMA channel 13 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C14LBAR,HPDMA channel 14 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C14CIDCFGR,HPDMA channel 14 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C14SEMCR,HPDMA channel 14 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x75C++0x3 line.long 0x0 "HPDMA_C14FCR,HPDMA channel 14 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x760++0x3 line.long 0x0 "HPDMA_C14SR,HPDMA channel 14 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x764++0x3 line.long 0x0 "HPDMA_C14CR,HPDMA channel 14 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x790++0x1B line.long 0x0 "HPDMA_C14TR1,HPDMA channel 14 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C14TR2,HPDMA channel 14 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C14BR1,HPDMA channel 14 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C14SAR,HPDMA channel 14 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C14DAR,HPDMA channel 14 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C14TR3,HPDMA channel 14 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C14BR2,HPDMA channel 14 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x7CC++0xF line.long 0x0 "HPDMA_C14LLR,HPDMA channel 14 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" line.long 0x4 "HPDMA_C15LBAR,HPDMA channel 15 linked-list base address register" hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x" line.long 0x8 "HPDMA_C15CIDCFGR,HPDMA channel 15 CID register" bitfld.long 0x8 22. "SEM_WLIST_CID6,white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID6 black-listed in the semaphore-based CID..,1: CID6 white-listed in the semaphore-based CID.." bitfld.long 0x8 21. "SEM_WLIST_CID5,white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID5 black-listed in the semaphore-based CID..,1: CID5 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 20. "SEM_WLIST_CID4,white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID4 black-listed in the semaphore-based CID..,1: CID4 white-listed in the semaphore-based CID.." bitfld.long 0x8 19. "SEM_WLIST_CID3,white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID3 black-listed in the semaphore-based CID..,1: CID3 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 18. "SEM_WLIST_CID2,white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID2 black-listed in the semaphore-based CID..,1: CID2 white-listed in the semaphore-based CID.." bitfld.long 0x8 17. "SEM_WLIST_CID1,white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID1 black-listed in the semaphore-based CID..,1: CID1 white-listed in the semaphore-based CID.." newline bitfld.long 0x8 16. "SEM_WLIST_CID0,white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" "0: CID0 black-listed in the semaphore-based CID..,1: CID0 white-listed in the semaphore-based CID.." bitfld.long 0x8 4.--6. "SCID,allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" "0: CID0 allocated to the channel x,1: CID1 allocated to the channel x,2: CID2 allocated to the channel x,3: CID3 allocated to the channel x,4: CID4 allocated to the channel x,5: CID5 allocated to the channel x,6: CID6 allocated to the channel x,?" newline bitfld.long 0x8 1. "SEM_EN,semaphore mode enable (for the CID allocation policy to the channel x)" "0: semaphore mode disabled. CID allocation policy..,1: semaphore mode enabled. CID allocation policy to.." bitfld.long 0x8 0. "CFEN,CID filtering enable of the channel x" "0: CID filtering disabled for when accessing a..,1: CID filtering enabled for when accessing a.." line.long 0xC "HPDMA_C15SEMCR,HPDMA channel 15 semaphore control register" rbitfld.long 0xC 4.--6. "SEM_CCID,current CID allocated to the channel x (in semaphore mode)" "0: CID0 is the last white-listed CID that took the..,1: CID1 is the last white-listed CID that took the..,2: CID2 is the last white-listed CID that took the..,3: CID3 is the last white-listed CID that took the..,4: CID4 is the last white-listed CID that took the..,5: CID5 is the last white-listed CID that took the..,6: CID6 is the last white-listed CID that took the..,?" bitfld.long 0xC 0. "SEM_MUTEX,mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" "0: release the control of the channel x (in..,1: take the control of the channel x (in semaphore.." wgroup.long 0x7DC++0x3 line.long 0x0 "HPDMA_C15FCR,HPDMA channel 15 flag clear register" bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared" bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared" newline bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared" bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared" newline bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared" bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared" newline bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared" rgroup.long 0x7E0++0x3 line.long 0x0 "HPDMA_C15SR,HPDMA channel 15 status register" hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level" bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred" newline bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred" bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred" newline bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.." bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.." newline bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred" bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred" newline bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state" group.long 0x7E4++0x3 line.long 0x0 "HPDMA_C15CR,HPDMA channel 15 control register" bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority" bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI" bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended." bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset" newline bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled" group.long 0x810++0x1B line.long 0x0 "HPDMA_C15TR1,HPDMA channel 15 transfer register 1" bitfld.long 0x0 31. "DSEC,security attribute of the HPDMA transfer to the destination" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.." bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.." newline bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.." hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63" newline bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst" bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)" newline bitfld.long 0x0 15. "SSEC,security attribute of the HPDMA transfer from the source" "0: HPDMA transfer non-secure,1: HPDMA transfer secure" bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated" newline bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.." bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.." newline hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63" bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst" newline bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)" line.long 0x4 "HPDMA_C15TR2,HPDMA channel 15 transfer register 2" bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.." bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00" newline hexmask.long.byte 0x4 16.--22. 1. "TRIGSEL,trigger event input selection" bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.." newline bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.." newline bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.." bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.." newline hexmask.long.byte 0x4 0.--7. 1. "REQSEL,hardware request selection" line.long 0x8 "HPDMA_C15BR1,HPDMA channel 15 alternate block register 1" bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.." bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.." newline bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.." bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.." newline hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter" hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source" line.long 0xC "HPDMA_C15SAR,HPDMA channel 15 source address register" hexmask.long 0xC 0.--31. 1. "SA,source address" line.long 0x10 "HPDMA_C15DAR,HPDMA channel 15 destination address register" hexmask.long 0x10 0.--31. 1. "DA,destination address" line.long 0x14 "HPDMA_C15TR3,HPDMA channel 15 transfer register 3" hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment" hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment" line.long 0x18 "HPDMA_C15BR2,HPDMA channel 15 block register 2" hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset" hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset" group.long 0x84C++0x3 line.long 0x0 "HPDMA_C15LLR,HPDMA channel 15 alternate linked-list address register" bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update" bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update" newline bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update" bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update" newline bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update" bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update" newline bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update" bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update" newline hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure" tree.end endif tree.end tree "I2C (Inter-Integrated Circuit)" base ad:0x0 tree "I2C1" base ad:0x40005400 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware and cleared by..,1: STOPF flag remains cleared by hardware. This.." bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware and cleared by..,1: ADDR flag remains cleared by hardware. This mode.." newline bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" newline bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." newline bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." newline bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" newline bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" newline hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" newline bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" newline bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" newline bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or t less than sub>LOW less than /sub> detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" tree.end tree "I2C1_S" base ad:0x50005400 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware and cleared by..,1: STOPF flag remains cleared by hardware. This.." bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware and cleared by..,1: ADDR flag remains cleared by hardware. This mode.." newline bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" newline bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." newline bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." newline bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" newline bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" newline hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" newline bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" newline bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" newline bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or t less than sub>LOW less than /sub> detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" tree.end tree "I2C2" base ad:0x40005800 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware and cleared by..,1: STOPF flag remains cleared by hardware. This.." bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware and cleared by..,1: ADDR flag remains cleared by hardware. This mode.." newline bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" newline bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." newline bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." newline bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" newline bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" newline hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" newline bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" newline bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" newline bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or t less than sub>LOW less than /sub> detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" tree.end tree "I2C2_S" base ad:0x50005800 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware and cleared by..,1: STOPF flag remains cleared by hardware. This.." bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware and cleared by..,1: ADDR flag remains cleared by hardware. This mode.." newline bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" newline bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." newline bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." newline bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" newline bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" newline hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" newline bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" newline bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" newline bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or t less than sub>LOW less than /sub> detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" tree.end tree "I2C3" base ad:0x40005C00 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware and cleared by..,1: STOPF flag remains cleared by hardware. This.." bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware and cleared by..,1: ADDR flag remains cleared by hardware. This mode.." newline bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" newline bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." newline bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." newline bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" newline bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" newline hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" newline bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" newline bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" newline bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or t less than sub>LOW less than /sub> detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" tree.end tree "I2C3_S" base ad:0x50005C00 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware and cleared by..,1: STOPF flag remains cleared by hardware. This.." bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware and cleared by..,1: ADDR flag remains cleared by hardware. This mode.." newline bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" newline bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." newline bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." newline bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" newline bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" newline hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" newline bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" newline bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" newline bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or t less than sub>LOW less than /sub> detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" tree.end tree "I2C4" base ad:0x46001C00 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware and cleared by..,1: STOPF flag remains cleared by hardware. This.." bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware and cleared by..,1: ADDR flag remains cleared by hardware. This mode.." newline bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" newline bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." newline bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." newline bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" newline bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" newline hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" newline bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" newline bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" newline bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or t less than sub>LOW less than /sub> detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" tree.end tree "I2C4_S" base ad:0x56001C00 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware and cleared by..,1: STOPF flag remains cleared by hardware. This.." bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware and cleared by..,1: ADDR flag remains cleared by hardware. This mode.." newline bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" newline bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." newline bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." newline bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" newline bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" newline hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" newline bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" newline bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" newline bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" newline bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or t less than sub>LOW less than /sub> detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" tree.end tree.end tree "I3C (Improved Inter-Integrated Circuit)" base ad:0x0 tree "I3C1" base ad:0x40006000 wgroup.long 0x0++0x3 line.long 0x0 "I3C_CR,I3C message control register" bitfld.long 0x0 31. "MEND,Message end type / last message of a frame (when the I3C acts as controller)" "0: this message from controller is followed by a..,1: this message from controller ends with a stop.." hexmask.long.byte 0x0 27.--30. 1. "MTYPE,Message type (whatever I3C acts as controller/target)" newline hexmask.long.byte 0x0 17.--23. 1. "ADD,7-bit I3C dynamic / I less than sup>2 less than /sup>C static target address (when I3C acts as controller)" bitfld.long 0x0 16. "RNW,Read / non-write message (when I3C acts as controller)" "0: write message,1: read message" newline hexmask.long.word 0x0 0.--15. 1. "DCNT,Count of data to transfer during a read or write message in bytes (whatever I3C acts as controller/target)" wgroup.long 0x0++0x3 line.long 0x0 "I3C_CR_alternate,I3C message control register" bitfld.long 0x0 31. "MEND,Message end type / last message of a frame (when I3C acts as controller)" "0: this message from controller is followed by a..,1: the message from the controller ends with a stop.." hexmask.long.byte 0x0 27.--30. 1. "MTYPE,Message type (when I3C acts as controller)" newline hexmask.long.byte 0x0 16.--23. 1. "CCC,8-bit CCC code (when I3C acts as controller)" hexmask.long.word 0x0 0.--15. 1. "DCNT,Count of related data to the CCC command to transfer as CCC defining bytes or CCC sub-command bytes or CCC data bytes in bytes" group.long 0x4++0x3 line.long 0x0 "I3C_CFGR,I3C configuration register" bitfld.long 0x0 30. "TSFSET,Frame transfer set (software trigger) (when I3C acts as controller)" "0: no action,1: setting this bit initiates a frame transfer by.." bitfld.long 0x0 21. "CFLUSH,C-FIFO flush (when I3C acts as controller)" "0: no action,1: flush C-FIFO" newline bitfld.long 0x0 20. "CDMAEN,C-FIFO DMA request enable (when I3C acts as controller)" "0: DMA mode is disabled for C-FIFO,1: DMA mode is enabled for C-FIFO" bitfld.long 0x0 19. "TMODE,Transmit mode (when I3C acts as controller)" "0: C-FIFO and TX-FIFO are not preloaded before..,1: C-FIFO and TX-FIFO are first preloaded (also.." newline bitfld.long 0x0 18. "SMODE,S-FIFO enable / status receive mode (when I3C acts as controller)" "0: S-FIFO is disabled,1: S-FIFO is enabled." bitfld.long 0x0 17. "SFLUSH,S-FIFO flush (when I3C acts as controller)" "0: no action,1: flush S-FIFO" newline bitfld.long 0x0 16. "SDMAEN,S-FIFO DMA request enable (when I3C acts as controller)" "0: DMA mode is disabled for reading status register..,1: DMA mode is enabled for reading status register.." bitfld.long 0x0 14. "TXTHRES,TX-FIFO threshold (whatever I3C acts as controller/target)" "0: 1-byte threshold,1: 1-word / 4-byte threshold" newline bitfld.long 0x0 13. "TXFLUSH,TX-FIFO flush (whatever I3C acts as controller/target)" "0: no action,1: flush TX-FIFO" bitfld.long 0x0 12. "TXDMAEN,TX-FIFO DMA request enable (whatever I3C acts as controller/target)" "0: DMA mode is disabled for TX-FIFO,1: DMA mode is enabled for TX-FIFO" newline bitfld.long 0x0 10. "RXTHRES,RX-FIFO threshold (whatever I3C acts as controller/target)" "0: 1-byte threshold,1: 1-word/4-bytes threshold" bitfld.long 0x0 9. "RXFLUSH,RX-FIFO flush (whatever I3C acts as controller/target)" "0: no action,1: flush RX-FIFO" newline bitfld.long 0x0 8. "RXDMAEN,RX-FIFO DMA request enable (whatever I3C acts as controller/target)" "0: DMA mode is disabled for RX-FIFO,1: DMA mode is enabled for RX-FIFO" bitfld.long 0x0 7. "HJACK,Hot-join request acknowledge (when I3C acts as a controller)" "0: hot-join request is not acknowledged,1: hot-join request is acknowledged" newline bitfld.long 0x0 5. "HKSDAEN,High-keeper enable on SDA line (when I3C acts as a controller)" "0: High-keeper is disabled,1: High-keeper is enabled and the weak pull-up is.." bitfld.long 0x0 4. "EXITPTRN,HDR exit pattern enable (when I3C acts as a controller)" "0: HDR exit pattern is not sent after the issued..,1: HDR exit pattern is sent after the issued.." newline bitfld.long 0x0 3. "RSTPTRN,HDR reset pattern enable (when I3C acts as a controller)" "0: standard stop emitted at the end of a frame,1: HDR reset pattern is inserted before the stop of.." bitfld.long 0x0 2. "NOARBH,No arbitrable header after a start (when I3C acts as a controller)" "0: An arbitrable header (0b111_1110 + RnW = 0) is..,1: No arbitrable header" newline bitfld.long 0x0 1. "CRINIT,Initial controller/target role" "0: target role,1: controller role" bitfld.long 0x0 0. "EN,I3C enable (whatever I3C acts as controller/target)" "0: I3C is disabled,1: I3C is enabled" rgroup.long 0x10++0x7 line.long 0x0 "I3C_RDR,I3C receive data byte register" hexmask.long.byte 0x0 0.--7. 1. "RDB0,8-bit received data on I3C bus." line.long 0x4 "I3C_RDWR,I3C receive data word register" hexmask.long.byte 0x4 24.--31. 1. "RDB3,8-bit received data (latest byte on I3C bus)." hexmask.long.byte 0x4 16.--23. 1. "RDB2,8-bit received data (next byte after RDB1 on I3C bus)." newline hexmask.long.byte 0x4 8.--15. 1. "RDB1,8-bit received data (next byte after RDB0 on I3C bus)." hexmask.long.byte 0x4 0.--7. 1. "RDB0,8-bit received data (earliest byte on I3C bus)." wgroup.long 0x18++0x7 line.long 0x0 "I3C_TDR,I3C transmit data byte register" hexmask.long.byte 0x0 0.--7. 1. "TDB0,8-bit data to transmit on I3C bus." line.long 0x4 "I3C_TDWR,I3C transmit data word register" hexmask.long.byte 0x4 24.--31. 1. "TDB3,8-bit transmit data (latest byte on I3C bus)." hexmask.long.byte 0x4 16.--23. 1. "TDB2,8-bit transmit data (next byte after TDB1[7:0] on I3C bus)." newline hexmask.long.byte 0x4 8.--15. 1. "TDB1,8-bit transmit data (next byte after TDB0[7:0] on I3C bus)." hexmask.long.byte 0x4 0.--7. 1. "TDB0,8-bit transmit data (earliest byte on I3C bus)" group.long 0x20++0x7 line.long 0x0 "I3C_IBIDR,I3C IBI payload data register" hexmask.long.byte 0x0 24.--31. 1. "IBIDB3,8-bit IBI payload data (latest byte on I3C bus)." hexmask.long.byte 0x0 16.--23. 1. "IBIDB2,8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0])." newline hexmask.long.byte 0x0 8.--15. 1. "IBIDB1,8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0])." hexmask.long.byte 0x0 0.--7. 1. "IBIDB0,8-bit IBI payload data (earliest byte on I3C bus MDB[7:0] mandatory data byte)." line.long 0x4 "I3C_TGTTDR,I3C target transmit configuration register" bitfld.long 0x4 16. "PRELOAD,Preload of the TX-FIFO (when I3C is configured as target)" "0: no TX-FIFO preload,1: TX-FIFO preload" hexmask.long.word 0x4 0.--15. 1. "TGTTDCNT,Transmit data counter in bytes (when I3C is configured as target)" rgroup.long 0x30++0x7 line.long 0x0 "I3C_SR,I3C status register" hexmask.long.byte 0x0 24.--31. 1. "MID,Message identifier/counter of a given frame (when the I3C acts as controller)" bitfld.long 0x0 18. "DIR,Message direction" "0: write,1: read" newline bitfld.long 0x0 17. "ABT,A private read message is ended prematurely by the target (when the I3C acts as controller)" "0: no early completion from the target,1: early completion from the target" hexmask.long.word 0x0 0.--15. 1. "XDCNT,Data counter" line.long 0x4 "I3C_SER,I3C status error register" bitfld.long 0x4 10. "DERR,Data error (when the I3C acts as controller)" "0: no detected error,1: controller detected a data error during the.." bitfld.long 0x4 9. "DNACK,Data not acknowledged (when the I3C acts as controller)" "0: no detected error,1: controller detected that a data byte is not.." newline bitfld.long 0x4 8. "ANACK,Address not acknowledged (when the I3C is configured as controller)" "0: no detected error,1: controller detected that the static/dynamic.." bitfld.long 0x4 7. "COVR,C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller)" "0: no detected error,1: controller detected either:" newline bitfld.long 0x4 6. "DOVR,RX-FIFO overrun or TX-FIFO underrun" "0: no detected error,1: whatever controller or target hardware detected.." bitfld.long 0x4 5. "STALL,SCL stall error (when the I3C acts as target)" "0: no detected error,1: target detected that SCL was stable for more.." newline bitfld.long 0x4 4. "PERR,Protocol error" "0: no detected error,1: whatever controller or target hardware detected.." hexmask.long.byte 0x4 0.--3. 1. "CODERR,Protocol error code/type" rgroup.long 0x40++0x3 line.long 0x0 "I3C_RMR,I3C received message register" hexmask.long.byte 0x0 17.--23. 1. "RADD,Received target address (when the I3C is configured as controller)" hexmask.long.byte 0x0 8.--15. 1. "RCODE,Received CCC code (when the I3C is configured as target)" newline bitfld.long 0x0 0.--2. "IBIRDCNT,IBI received payload data count (when the I3C is configured as controller)" "0,1,2,3,4,5,6,7" rgroup.long 0x50++0x7 line.long 0x0 "I3C_EVR,I3C event register" bitfld.long 0x0 31. "GRPF,Group addressing flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 30. "DEFF,DEFTGTS flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 29. "INTUPDF,Interrupt/controller-role/hot-join update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 28. "ASUPDF,Activity state update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 27. "RSTF,Reset pattern flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 26. "MRLUPDF,Maximum read length update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 25. "MWLUPDF,Maximum write length update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 24. "DAUPDF,Dynamic address update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 23. "STAF,Get status flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 22. "GETF,Get flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 21. "WKPF,Wake-up/missed start flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 19. "HJF,Hot-join flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 18. "CRUPDF,Controller-role update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 17. "CRF,Controller-role request flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 16. "IBIENDF,IBI end flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 15. "IBIF,IBI flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 11. "ERRF,Flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 10. "RXTGTENDF,Target-initiated read end flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 9. "FCF,Frame complete flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 7. "RXLASTF,Last read data byte/word flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 6. "TXLASTF,Last written data byte/word flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 5. "RXFNEF,RX-FIFO not empty flag (whatever the I3C acts as controller/target)" "0,1" newline bitfld.long 0x0 4. "TXFNFF,TX-FIFO not full flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 3. "SFNEF,S-FIFO not empty flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 2. "CFNFF,C-FIFO not full flag (when the I3C acts as controller)" "0,1" bitfld.long 0x0 1. "TXFEF,TX-FIFO empty flag (whatever the I3C acts as controller/target)" "0,1" newline bitfld.long 0x0 0. "CFEF,C-FIFO empty flag (whatever the I3C acts as controller)" "0,1" line.long 0x4 "I3C_IER,I3C interrupt enable register" bitfld.long 0x4 31. "GRPIE,DEFGRPA CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 30. "DEFIE,DEFTGTS CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 29. "INTUPDIE,ENEC/DISEC CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 28. "ASUPDIE,ENTASx CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 27. "RSTIE,reset pattern interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 26. "MRLUPDIE,SETMRL CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 25. "MWLUPDIE,SETMWL CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 24. "DAUPDIE,ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 23. "STAIE,format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 22. "GETIE,GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 21. "WKPIE,Wake-up interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 19. "HJIE,Hot-join interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 18. "CRUPDIE,Controller-role update interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 17. "CRIE,Controller-role request interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 16. "IBIENDIE,IBI end interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 15. "IBIIE,IBI request interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 11. "ERRIE,error interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 10. "RXTGTENDIE,target-initiated read end interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 9. "FCIE,frame complete interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 5. "RXFNEIE,RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 4. "TXFNFIE,TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 3. "SFNEIE,S-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 2. "CFNFIE,C-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" wgroup.long 0x58++0x3 line.long 0x0 "I3C_CEVR,I3C clear event register" bitfld.long 0x0 31. "CGRPF,Clear DEFGRPA CCC flag (when the I3C acts as target)" "0: no effect,1: clear GRPF" bitfld.long 0x0 30. "CDEFF,Clear DEFTGTS CCC flag (when the I3C acts as target)" "0: no effect,1: clear DEFF" newline bitfld.long 0x0 29. "CINTUPDF,Clear ENEC/DISEC CCC flag (when the I3C acts as target)" "0: no effect,1: clear CINTUPDF" bitfld.long 0x0 28. "CASUPDF,Clear ENTASx CCC flag (when the I3C acts as target)" "0: no effect,1: clear ASUPDF" newline bitfld.long 0x0 27. "CRSTF,Clear reset pattern flag (when the I3C acts as target)" "0: no effect,1: clear RSTF" bitfld.long 0x0 26. "CMRLUPDF,Clear SETMRL CCC flag (when the I3C acts as target)" "0: no effect,1: clear MRLUPDF" newline bitfld.long 0x0 25. "CMWLUPDF,Clear SETMWL CCC flag (when the I3C acts as target)" "0: no effect,1: clear MWLUPDF" bitfld.long 0x0 24. "CDAUPDF,Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target)" "0: no effect,1: clear DAUPDF" newline bitfld.long 0x0 23. "CSTAF,Clear format 1 GETSTATUS CCC flag (when the I3C acts as target)" "0: no effect,1: clear STAF" bitfld.long 0x0 22. "CGETF,Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target)" "0: no effect,1: clear GETF" newline bitfld.long 0x0 21. "CWKPF,Clear wake-up flag (when the I3C acts as target)" "0: no effect,1: clear WKPF" bitfld.long 0x0 19. "CHJF,Clear hot-join flag (when the I3C acts as controller)" "0: no effect,1: clear HJF" newline bitfld.long 0x0 18. "CCRUPDF,Clear controller-role update flag (when the I3C acts as target)" "0: no effect,1: clear CRUPDF" bitfld.long 0x0 17. "CCRF,Clear controller-role request flag (when the I3C acts as controller)" "0: no effect,1: clear CRF" newline bitfld.long 0x0 16. "CIBIENDF,Clear IBI end flag (when the I3C acts as target)" "0: no effect,1: clear IBIENDF" bitfld.long 0x0 15. "CIBIF,Clear IBI request flag (when the I3C acts as controller)" "0: no effect,1: clear IBIF" newline bitfld.long 0x0 11. "CERRF,Clear error flag (whatever the I3C acts as controller/target)" "0: no effect,1: clear ERRF" bitfld.long 0x0 10. "CRXTGTENDF,Clear target-initiated read end flag (when the I3C acts as controller)" "0: no effect,1: clear RXTGTENDF" newline bitfld.long 0x0 9. "CFCF,Clear frame complete flag (whatever the I3C acts as controller/target)" "0: no effect,1: clear FCF" group.long 0x60++0x13 line.long 0x0 "I3C_DEVR0,I3C own device characteristics register" rbitfld.long 0x0 24. "RSTVAL,Reset action is valid (when the I3C acts as target)" "0,1" rbitfld.long 0x0 22.--23. "RSTACT,Reset action/level on received reset pattern (when the I3C acts as target)" "0: no reset action,1: first level of reset: the application software..,2: second level of reset: the application software..,3: no reset action" newline rbitfld.long 0x0 20.--21. "AS,Activity state (when the I3C acts as target)" "0: activity state 0,1: activity state 1,2: activity state 2,3: activity state 3" bitfld.long 0x0 19. "HJEN,Hot-join request enable (when the I3C acts as target)" "0: hot-join request disabled,1: hot-join request enabled" newline bitfld.long 0x0 17. "CREN,Controller-role request enable (when the I3C acts as target)" "0: controller-role request disabled,1: controller-role request enabled" bitfld.long 0x0 16. "IBIEN,IBI request enable (when the I3C acts as target)" "0: IBI request disabled,1: IBI request enabled" newline hexmask.long.byte 0x0 1.--7. 1. "DA,7-bit dynamic address" bitfld.long 0x0 0. "DAVAL,Dynamic address is valid (when the I3C acts as target)" "0,1" line.long 0x4 "I3C_DEVR1,I3C device 1 characteristics register" rbitfld.long 0x4 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x4 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x4 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x4 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x4 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x4 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0x8 "I3C_DEVR2,I3C device 2 characteristics register" rbitfld.long 0x8 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x8 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x8 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x8 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x8 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x8 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0xC "I3C_DEVR3,I3C device 3 characteristics register" rbitfld.long 0xC 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0xC 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0xC 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0xC 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0xC 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0xC 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0x10 "I3C_DEVR4,I3C device 4 characteristics register" rbitfld.long 0x10 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x10 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x10 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x10 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x10 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x10 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" group.long 0x90++0x7 line.long 0x0 "I3C_MAXRLR,I3C maximum read length register" bitfld.long 0x0 16.--18. "IBIP,IBI payload data maximum size in bytes (when I3C acts as target)" "0: null payload data size (only allowed when BCR2 =..,1: 1 byte (mandatory data byte MDB[7:0],2: 2 bytes (including first MDB[7:0]),3: 3 bytes (including first MDB[7:0]),4: 4 bytes (including first MDB[7:0]),?,?,?" hexmask.long.word 0x0 0.--15. 1. "MRL,Maximum data read length (when I3C acts as target)" line.long 0x4 "I3C_MAXWLR,I3C maximum write length register" hexmask.long.word 0x4 0.--15. 1. "MWL,Maximum data write length (when I3C acts as target)" group.long 0xA0++0xB line.long 0x0 "I3C_TIMINGR0,I3C timing register 0" hexmask.long.byte 0x0 24.--31. 1. "SCLH_I2C,SCL high duration used for legacy I less than sup>2 less than /sup>C messages in number of kernel clocks cycles:" hexmask.long.byte 0x0 16.--23. 1. "SCLL_OD,SCL low duration in open-drain phases used for legacy I less than sup>2 less than /sup>C messages and for I3C open-drain phases (address phase following a start ACK phase during controller-initiated messages and T bit phase during.." newline hexmask.long.byte 0x0 8.--15. 1. "SCLH_I3C,SCL high duration used for I3C messages (both in push-pull and open-drain phases) in number of kernel clocks cycles:" hexmask.long.byte 0x0 0.--7. 1. "SCLL_PP,SCL low duration in I3C push-pull phases in number of kernel clocks cycles:" line.long 0x4 "I3C_TIMINGR1,I3C timing register 1" bitfld.long 0x4 28. "SDA_HD,SDA hold time (when the I3C acts as controller) in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull t less than sub>HD_PP less than /sub>):" "0,1" hexmask.long.byte 0x4 16.--22. 1. "FREE,Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller)" newline bitfld.long 0x4 8.--9. "ASNCR,Activity state of the new controller (when I3C acts as active controller)" "0,1,2,3" hexmask.long.byte 0x4 0.--7. 1. "AVAL,Number of kernel clock cycles to set a time unit of 1 s whatever I3C acts as controller or target." line.long 0x8 "I3C_TIMINGR2,I3C timing register 2" hexmask.long.byte 0x8 8.--15. 1. "STALL,Controller clock stall time in number of kernel clock cycles" bitfld.long 0x8 3. "STALLA,Controller clock stall enable on ACK phase" "0: no stall,1: stall enabled" newline bitfld.long 0x8 2. "STALLC,Controller clock stall enable on PAR phase of CCC" "0: no stall,1: stall enabled" bitfld.long 0x8 1. "STALLD,Controller clock stall enable on PAR phase of Data" "0: no stall,1: stall enabled" newline bitfld.long 0x8 0. "STALLT,Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy I less than sup>2 less than /sup>C read)" "0: no stall,1: stall enabled" group.long 0xC0++0x17 line.long 0x0 "I3C_BCR,I3C bus characteristics register" bitfld.long 0x0 6. "BCR6,Controller capable" "0: I3C target (no controller capable),1: I3C controller capable" bitfld.long 0x0 2. "BCR2,in-band interrupt (IBI) payload" "0: no data byte follows the accepted IBI,1: at least one mandatory data byte follows the.." newline bitfld.long 0x0 0. "BCR0,max data speed limitation" "0: no limitation,1: limitation as described by I3C_GETMXDSR." line.long 0x4 "I3C_DCR,I3C device characteristics register" hexmask.long.byte 0x4 0.--7. 1. "DCR,device characteristics ID" line.long 0x8 "I3C_GETCAPR,I3C get capability register" bitfld.long 0x8 14. "CAPPEND,IBI MDB support for pending read notification" "0: this I3C when acting as target sends an IBI..,1: this I3C when acting as target sends an IBI.." line.long 0xC "I3C_CRCAPR,I3C controller-role capability register" bitfld.long 0xC 9. "CAPGRP,group management support (when acting as controller)" "0: this I3C does not support group address..,1: this I3C supports group address capabilities.." bitfld.long 0xC 3. "CAPDHOFF,delayed controller-role hand-off" "0: this I3C does not needs additional time to..,1: this I3C needs additional time to process a.." line.long 0x10 "I3C_GETMXDSR,I3C get capability register" bitfld.long 0x10 24. "TSCO,clock-to-data turnaround time (t less than sub>SCO less than /sub>)" "0: t less than sub>SCO less than /sub> less than or..,1: t less than sub>SCO less than /sub> > 12 ns.." hexmask.long.byte 0x10 16.--23. 1. "RDTURN,programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte)" newline bitfld.long 0x10 8.--9. "FMT,GETMXDS CCC format" "0: format 1 (2 bytes with MaxWr with no defining..,1: format 2: (5 bytes w.ith MaxWr with no defining..,2: format 2 (5 bytes with MaxWr with no defining..,3: format 2 (5 bytes with MaxWr with no defining.." bitfld.long 0x10 0.--1. "HOFFAS,Controller hand-off activity state" "0: activity state 0 is the initial activity state..,1: activity state 1 is the initial activity state..,2: activity state 2 is the initial activity state..,3: activity state 3 is the initial activity state.." line.long 0x14 "I3C_EPIDR,I3C extended provisioned ID register" hexmask.long.word 0x14 17.--31. 1. "MIPIMID,15-bit MIPI manufacturer ID" rbitfld.long 0x14 16. "IDTSEL,provisioned ID type selector" "0,1" newline hexmask.long.byte 0x14 12.--15. 1. "MIPIID,4-bit MIPI Instance ID" tree.end tree "I3C1_S" base ad:0x50006000 wgroup.long 0x0++0x3 line.long 0x0 "I3C_CR,I3C message control register" bitfld.long 0x0 31. "MEND,Message end type / last message of a frame (when the I3C acts as controller)" "0: this message from controller is followed by a..,1: this message from controller ends with a stop.." hexmask.long.byte 0x0 27.--30. 1. "MTYPE,Message type (whatever I3C acts as controller/target)" newline hexmask.long.byte 0x0 17.--23. 1. "ADD,7-bit I3C dynamic / I less than sup>2 less than /sup>C static target address (when I3C acts as controller)" bitfld.long 0x0 16. "RNW,Read / non-write message (when I3C acts as controller)" "0: write message,1: read message" newline hexmask.long.word 0x0 0.--15. 1. "DCNT,Count of data to transfer during a read or write message in bytes (whatever I3C acts as controller/target)" wgroup.long 0x0++0x3 line.long 0x0 "I3C_CR_alternate,I3C message control register" bitfld.long 0x0 31. "MEND,Message end type / last message of a frame (when I3C acts as controller)" "0: this message from controller is followed by a..,1: the message from the controller ends with a stop.." hexmask.long.byte 0x0 27.--30. 1. "MTYPE,Message type (when I3C acts as controller)" newline hexmask.long.byte 0x0 16.--23. 1. "CCC,8-bit CCC code (when I3C acts as controller)" hexmask.long.word 0x0 0.--15. 1. "DCNT,Count of related data to the CCC command to transfer as CCC defining bytes or CCC sub-command bytes or CCC data bytes in bytes" group.long 0x4++0x3 line.long 0x0 "I3C_CFGR,I3C configuration register" bitfld.long 0x0 30. "TSFSET,Frame transfer set (software trigger) (when I3C acts as controller)" "0: no action,1: setting this bit initiates a frame transfer by.." bitfld.long 0x0 21. "CFLUSH,C-FIFO flush (when I3C acts as controller)" "0: no action,1: flush C-FIFO" newline bitfld.long 0x0 20. "CDMAEN,C-FIFO DMA request enable (when I3C acts as controller)" "0: DMA mode is disabled for C-FIFO,1: DMA mode is enabled for C-FIFO" bitfld.long 0x0 19. "TMODE,Transmit mode (when I3C acts as controller)" "0: C-FIFO and TX-FIFO are not preloaded before..,1: C-FIFO and TX-FIFO are first preloaded (also.." newline bitfld.long 0x0 18. "SMODE,S-FIFO enable / status receive mode (when I3C acts as controller)" "0: S-FIFO is disabled,1: S-FIFO is enabled." bitfld.long 0x0 17. "SFLUSH,S-FIFO flush (when I3C acts as controller)" "0: no action,1: flush S-FIFO" newline bitfld.long 0x0 16. "SDMAEN,S-FIFO DMA request enable (when I3C acts as controller)" "0: DMA mode is disabled for reading status register..,1: DMA mode is enabled for reading status register.." bitfld.long 0x0 14. "TXTHRES,TX-FIFO threshold (whatever I3C acts as controller/target)" "0: 1-byte threshold,1: 1-word / 4-byte threshold" newline bitfld.long 0x0 13. "TXFLUSH,TX-FIFO flush (whatever I3C acts as controller/target)" "0: no action,1: flush TX-FIFO" bitfld.long 0x0 12. "TXDMAEN,TX-FIFO DMA request enable (whatever I3C acts as controller/target)" "0: DMA mode is disabled for TX-FIFO,1: DMA mode is enabled for TX-FIFO" newline bitfld.long 0x0 10. "RXTHRES,RX-FIFO threshold (whatever I3C acts as controller/target)" "0: 1-byte threshold,1: 1-word/4-bytes threshold" bitfld.long 0x0 9. "RXFLUSH,RX-FIFO flush (whatever I3C acts as controller/target)" "0: no action,1: flush RX-FIFO" newline bitfld.long 0x0 8. "RXDMAEN,RX-FIFO DMA request enable (whatever I3C acts as controller/target)" "0: DMA mode is disabled for RX-FIFO,1: DMA mode is enabled for RX-FIFO" bitfld.long 0x0 7. "HJACK,Hot-join request acknowledge (when I3C acts as a controller)" "0: hot-join request is not acknowledged,1: hot-join request is acknowledged" newline bitfld.long 0x0 5. "HKSDAEN,High-keeper enable on SDA line (when I3C acts as a controller)" "0: High-keeper is disabled,1: High-keeper is enabled and the weak pull-up is.." bitfld.long 0x0 4. "EXITPTRN,HDR exit pattern enable (when I3C acts as a controller)" "0: HDR exit pattern is not sent after the issued..,1: HDR exit pattern is sent after the issued.." newline bitfld.long 0x0 3. "RSTPTRN,HDR reset pattern enable (when I3C acts as a controller)" "0: standard stop emitted at the end of a frame,1: HDR reset pattern is inserted before the stop of.." bitfld.long 0x0 2. "NOARBH,No arbitrable header after a start (when I3C acts as a controller)" "0: An arbitrable header (0b111_1110 + RnW = 0) is..,1: No arbitrable header" newline bitfld.long 0x0 1. "CRINIT,Initial controller/target role" "0: target role,1: controller role" bitfld.long 0x0 0. "EN,I3C enable (whatever I3C acts as controller/target)" "0: I3C is disabled,1: I3C is enabled" rgroup.long 0x10++0x7 line.long 0x0 "I3C_RDR,I3C receive data byte register" hexmask.long.byte 0x0 0.--7. 1. "RDB0,8-bit received data on I3C bus." line.long 0x4 "I3C_RDWR,I3C receive data word register" hexmask.long.byte 0x4 24.--31. 1. "RDB3,8-bit received data (latest byte on I3C bus)." hexmask.long.byte 0x4 16.--23. 1. "RDB2,8-bit received data (next byte after RDB1 on I3C bus)." newline hexmask.long.byte 0x4 8.--15. 1. "RDB1,8-bit received data (next byte after RDB0 on I3C bus)." hexmask.long.byte 0x4 0.--7. 1. "RDB0,8-bit received data (earliest byte on I3C bus)." wgroup.long 0x18++0x7 line.long 0x0 "I3C_TDR,I3C transmit data byte register" hexmask.long.byte 0x0 0.--7. 1. "TDB0,8-bit data to transmit on I3C bus." line.long 0x4 "I3C_TDWR,I3C transmit data word register" hexmask.long.byte 0x4 24.--31. 1. "TDB3,8-bit transmit data (latest byte on I3C bus)." hexmask.long.byte 0x4 16.--23. 1. "TDB2,8-bit transmit data (next byte after TDB1[7:0] on I3C bus)." newline hexmask.long.byte 0x4 8.--15. 1. "TDB1,8-bit transmit data (next byte after TDB0[7:0] on I3C bus)." hexmask.long.byte 0x4 0.--7. 1. "TDB0,8-bit transmit data (earliest byte on I3C bus)" group.long 0x20++0x7 line.long 0x0 "I3C_IBIDR,I3C IBI payload data register" hexmask.long.byte 0x0 24.--31. 1. "IBIDB3,8-bit IBI payload data (latest byte on I3C bus)." hexmask.long.byte 0x0 16.--23. 1. "IBIDB2,8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0])." newline hexmask.long.byte 0x0 8.--15. 1. "IBIDB1,8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0])." hexmask.long.byte 0x0 0.--7. 1. "IBIDB0,8-bit IBI payload data (earliest byte on I3C bus MDB[7:0] mandatory data byte)." line.long 0x4 "I3C_TGTTDR,I3C target transmit configuration register" bitfld.long 0x4 16. "PRELOAD,Preload of the TX-FIFO (when I3C is configured as target)" "0: no TX-FIFO preload,1: TX-FIFO preload" hexmask.long.word 0x4 0.--15. 1. "TGTTDCNT,Transmit data counter in bytes (when I3C is configured as target)" rgroup.long 0x30++0x7 line.long 0x0 "I3C_SR,I3C status register" hexmask.long.byte 0x0 24.--31. 1. "MID,Message identifier/counter of a given frame (when the I3C acts as controller)" bitfld.long 0x0 18. "DIR,Message direction" "0: write,1: read" newline bitfld.long 0x0 17. "ABT,A private read message is ended prematurely by the target (when the I3C acts as controller)" "0: no early completion from the target,1: early completion from the target" hexmask.long.word 0x0 0.--15. 1. "XDCNT,Data counter" line.long 0x4 "I3C_SER,I3C status error register" bitfld.long 0x4 10. "DERR,Data error (when the I3C acts as controller)" "0: no detected error,1: controller detected a data error during the.." bitfld.long 0x4 9. "DNACK,Data not acknowledged (when the I3C acts as controller)" "0: no detected error,1: controller detected that a data byte is not.." newline bitfld.long 0x4 8. "ANACK,Address not acknowledged (when the I3C is configured as controller)" "0: no detected error,1: controller detected that the static/dynamic.." bitfld.long 0x4 7. "COVR,C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller)" "0: no detected error,1: controller detected either:" newline bitfld.long 0x4 6. "DOVR,RX-FIFO overrun or TX-FIFO underrun" "0: no detected error,1: whatever controller or target hardware detected.." bitfld.long 0x4 5. "STALL,SCL stall error (when the I3C acts as target)" "0: no detected error,1: target detected that SCL was stable for more.." newline bitfld.long 0x4 4. "PERR,Protocol error" "0: no detected error,1: whatever controller or target hardware detected.." hexmask.long.byte 0x4 0.--3. 1. "CODERR,Protocol error code/type" rgroup.long 0x40++0x3 line.long 0x0 "I3C_RMR,I3C received message register" hexmask.long.byte 0x0 17.--23. 1. "RADD,Received target address (when the I3C is configured as controller)" hexmask.long.byte 0x0 8.--15. 1. "RCODE,Received CCC code (when the I3C is configured as target)" newline bitfld.long 0x0 0.--2. "IBIRDCNT,IBI received payload data count (when the I3C is configured as controller)" "0,1,2,3,4,5,6,7" rgroup.long 0x50++0x7 line.long 0x0 "I3C_EVR,I3C event register" bitfld.long 0x0 31. "GRPF,Group addressing flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 30. "DEFF,DEFTGTS flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 29. "INTUPDF,Interrupt/controller-role/hot-join update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 28. "ASUPDF,Activity state update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 27. "RSTF,Reset pattern flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 26. "MRLUPDF,Maximum read length update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 25. "MWLUPDF,Maximum write length update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 24. "DAUPDF,Dynamic address update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 23. "STAF,Get status flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 22. "GETF,Get flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 21. "WKPF,Wake-up/missed start flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 19. "HJF,Hot-join flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 18. "CRUPDF,Controller-role update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 17. "CRF,Controller-role request flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 16. "IBIENDF,IBI end flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 15. "IBIF,IBI flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 11. "ERRF,Flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 10. "RXTGTENDF,Target-initiated read end flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 9. "FCF,Frame complete flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 7. "RXLASTF,Last read data byte/word flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 6. "TXLASTF,Last written data byte/word flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 5. "RXFNEF,RX-FIFO not empty flag (whatever the I3C acts as controller/target)" "0,1" newline bitfld.long 0x0 4. "TXFNFF,TX-FIFO not full flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 3. "SFNEF,S-FIFO not empty flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 2. "CFNFF,C-FIFO not full flag (when the I3C acts as controller)" "0,1" bitfld.long 0x0 1. "TXFEF,TX-FIFO empty flag (whatever the I3C acts as controller/target)" "0,1" newline bitfld.long 0x0 0. "CFEF,C-FIFO empty flag (whatever the I3C acts as controller)" "0,1" line.long 0x4 "I3C_IER,I3C interrupt enable register" bitfld.long 0x4 31. "GRPIE,DEFGRPA CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 30. "DEFIE,DEFTGTS CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 29. "INTUPDIE,ENEC/DISEC CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 28. "ASUPDIE,ENTASx CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 27. "RSTIE,reset pattern interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 26. "MRLUPDIE,SETMRL CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 25. "MWLUPDIE,SETMWL CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 24. "DAUPDIE,ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 23. "STAIE,format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 22. "GETIE,GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 21. "WKPIE,Wake-up interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 19. "HJIE,Hot-join interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 18. "CRUPDIE,Controller-role update interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 17. "CRIE,Controller-role request interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 16. "IBIENDIE,IBI end interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 15. "IBIIE,IBI request interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 11. "ERRIE,error interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 10. "RXTGTENDIE,target-initiated read end interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 9. "FCIE,frame complete interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 5. "RXFNEIE,RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 4. "TXFNFIE,TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 3. "SFNEIE,S-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 2. "CFNFIE,C-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" wgroup.long 0x58++0x3 line.long 0x0 "I3C_CEVR,I3C clear event register" bitfld.long 0x0 31. "CGRPF,Clear DEFGRPA CCC flag (when the I3C acts as target)" "0: no effect,1: clear GRPF" bitfld.long 0x0 30. "CDEFF,Clear DEFTGTS CCC flag (when the I3C acts as target)" "0: no effect,1: clear DEFF" newline bitfld.long 0x0 29. "CINTUPDF,Clear ENEC/DISEC CCC flag (when the I3C acts as target)" "0: no effect,1: clear CINTUPDF" bitfld.long 0x0 28. "CASUPDF,Clear ENTASx CCC flag (when the I3C acts as target)" "0: no effect,1: clear ASUPDF" newline bitfld.long 0x0 27. "CRSTF,Clear reset pattern flag (when the I3C acts as target)" "0: no effect,1: clear RSTF" bitfld.long 0x0 26. "CMRLUPDF,Clear SETMRL CCC flag (when the I3C acts as target)" "0: no effect,1: clear MRLUPDF" newline bitfld.long 0x0 25. "CMWLUPDF,Clear SETMWL CCC flag (when the I3C acts as target)" "0: no effect,1: clear MWLUPDF" bitfld.long 0x0 24. "CDAUPDF,Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target)" "0: no effect,1: clear DAUPDF" newline bitfld.long 0x0 23. "CSTAF,Clear format 1 GETSTATUS CCC flag (when the I3C acts as target)" "0: no effect,1: clear STAF" bitfld.long 0x0 22. "CGETF,Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target)" "0: no effect,1: clear GETF" newline bitfld.long 0x0 21. "CWKPF,Clear wake-up flag (when the I3C acts as target)" "0: no effect,1: clear WKPF" bitfld.long 0x0 19. "CHJF,Clear hot-join flag (when the I3C acts as controller)" "0: no effect,1: clear HJF" newline bitfld.long 0x0 18. "CCRUPDF,Clear controller-role update flag (when the I3C acts as target)" "0: no effect,1: clear CRUPDF" bitfld.long 0x0 17. "CCRF,Clear controller-role request flag (when the I3C acts as controller)" "0: no effect,1: clear CRF" newline bitfld.long 0x0 16. "CIBIENDF,Clear IBI end flag (when the I3C acts as target)" "0: no effect,1: clear IBIENDF" bitfld.long 0x0 15. "CIBIF,Clear IBI request flag (when the I3C acts as controller)" "0: no effect,1: clear IBIF" newline bitfld.long 0x0 11. "CERRF,Clear error flag (whatever the I3C acts as controller/target)" "0: no effect,1: clear ERRF" bitfld.long 0x0 10. "CRXTGTENDF,Clear target-initiated read end flag (when the I3C acts as controller)" "0: no effect,1: clear RXTGTENDF" newline bitfld.long 0x0 9. "CFCF,Clear frame complete flag (whatever the I3C acts as controller/target)" "0: no effect,1: clear FCF" group.long 0x60++0x13 line.long 0x0 "I3C_DEVR0,I3C own device characteristics register" rbitfld.long 0x0 24. "RSTVAL,Reset action is valid (when the I3C acts as target)" "0,1" rbitfld.long 0x0 22.--23. "RSTACT,Reset action/level on received reset pattern (when the I3C acts as target)" "0: no reset action,1: first level of reset: the application software..,2: second level of reset: the application software..,3: no reset action" newline rbitfld.long 0x0 20.--21. "AS,Activity state (when the I3C acts as target)" "0: activity state 0,1: activity state 1,2: activity state 2,3: activity state 3" bitfld.long 0x0 19. "HJEN,Hot-join request enable (when the I3C acts as target)" "0: hot-join request disabled,1: hot-join request enabled" newline bitfld.long 0x0 17. "CREN,Controller-role request enable (when the I3C acts as target)" "0: controller-role request disabled,1: controller-role request enabled" bitfld.long 0x0 16. "IBIEN,IBI request enable (when the I3C acts as target)" "0: IBI request disabled,1: IBI request enabled" newline hexmask.long.byte 0x0 1.--7. 1. "DA,7-bit dynamic address" bitfld.long 0x0 0. "DAVAL,Dynamic address is valid (when the I3C acts as target)" "0,1" line.long 0x4 "I3C_DEVR1,I3C device 1 characteristics register" rbitfld.long 0x4 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x4 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x4 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x4 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x4 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x4 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0x8 "I3C_DEVR2,I3C device 2 characteristics register" rbitfld.long 0x8 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x8 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x8 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x8 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x8 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x8 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0xC "I3C_DEVR3,I3C device 3 characteristics register" rbitfld.long 0xC 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0xC 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0xC 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0xC 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0xC 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0xC 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0x10 "I3C_DEVR4,I3C device 4 characteristics register" rbitfld.long 0x10 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x10 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x10 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x10 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x10 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x10 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" group.long 0x90++0x7 line.long 0x0 "I3C_MAXRLR,I3C maximum read length register" bitfld.long 0x0 16.--18. "IBIP,IBI payload data maximum size in bytes (when I3C acts as target)" "0: null payload data size (only allowed when BCR2 =..,1: 1 byte (mandatory data byte MDB[7:0],2: 2 bytes (including first MDB[7:0]),3: 3 bytes (including first MDB[7:0]),4: 4 bytes (including first MDB[7:0]),?,?,?" hexmask.long.word 0x0 0.--15. 1. "MRL,Maximum data read length (when I3C acts as target)" line.long 0x4 "I3C_MAXWLR,I3C maximum write length register" hexmask.long.word 0x4 0.--15. 1. "MWL,Maximum data write length (when I3C acts as target)" group.long 0xA0++0xB line.long 0x0 "I3C_TIMINGR0,I3C timing register 0" hexmask.long.byte 0x0 24.--31. 1. "SCLH_I2C,SCL high duration used for legacy I less than sup>2 less than /sup>C messages in number of kernel clocks cycles:" hexmask.long.byte 0x0 16.--23. 1. "SCLL_OD,SCL low duration in open-drain phases used for legacy I less than sup>2 less than /sup>C messages and for I3C open-drain phases (address phase following a start ACK phase during controller-initiated messages and T bit phase during.." newline hexmask.long.byte 0x0 8.--15. 1. "SCLH_I3C,SCL high duration used for I3C messages (both in push-pull and open-drain phases) in number of kernel clocks cycles:" hexmask.long.byte 0x0 0.--7. 1. "SCLL_PP,SCL low duration in I3C push-pull phases in number of kernel clocks cycles:" line.long 0x4 "I3C_TIMINGR1,I3C timing register 1" bitfld.long 0x4 28. "SDA_HD,SDA hold time (when the I3C acts as controller) in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull t less than sub>HD_PP less than /sub>):" "0,1" hexmask.long.byte 0x4 16.--22. 1. "FREE,Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller)" newline bitfld.long 0x4 8.--9. "ASNCR,Activity state of the new controller (when I3C acts as active controller)" "0,1,2,3" hexmask.long.byte 0x4 0.--7. 1. "AVAL,Number of kernel clock cycles to set a time unit of 1 s whatever I3C acts as controller or target." line.long 0x8 "I3C_TIMINGR2,I3C timing register 2" hexmask.long.byte 0x8 8.--15. 1. "STALL,Controller clock stall time in number of kernel clock cycles" bitfld.long 0x8 3. "STALLA,Controller clock stall enable on ACK phase" "0: no stall,1: stall enabled" newline bitfld.long 0x8 2. "STALLC,Controller clock stall enable on PAR phase of CCC" "0: no stall,1: stall enabled" bitfld.long 0x8 1. "STALLD,Controller clock stall enable on PAR phase of Data" "0: no stall,1: stall enabled" newline bitfld.long 0x8 0. "STALLT,Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy I less than sup>2 less than /sup>C read)" "0: no stall,1: stall enabled" group.long 0xC0++0x17 line.long 0x0 "I3C_BCR,I3C bus characteristics register" bitfld.long 0x0 6. "BCR6,Controller capable" "0: I3C target (no controller capable),1: I3C controller capable" bitfld.long 0x0 2. "BCR2,in-band interrupt (IBI) payload" "0: no data byte follows the accepted IBI,1: at least one mandatory data byte follows the.." newline bitfld.long 0x0 0. "BCR0,max data speed limitation" "0: no limitation,1: limitation as described by I3C_GETMXDSR." line.long 0x4 "I3C_DCR,I3C device characteristics register" hexmask.long.byte 0x4 0.--7. 1. "DCR,device characteristics ID" line.long 0x8 "I3C_GETCAPR,I3C get capability register" bitfld.long 0x8 14. "CAPPEND,IBI MDB support for pending read notification" "0: this I3C when acting as target sends an IBI..,1: this I3C when acting as target sends an IBI.." line.long 0xC "I3C_CRCAPR,I3C controller-role capability register" bitfld.long 0xC 9. "CAPGRP,group management support (when acting as controller)" "0: this I3C does not support group address..,1: this I3C supports group address capabilities.." bitfld.long 0xC 3. "CAPDHOFF,delayed controller-role hand-off" "0: this I3C does not needs additional time to..,1: this I3C needs additional time to process a.." line.long 0x10 "I3C_GETMXDSR,I3C get capability register" bitfld.long 0x10 24. "TSCO,clock-to-data turnaround time (t less than sub>SCO less than /sub>)" "0: t less than sub>SCO less than /sub> less than or..,1: t less than sub>SCO less than /sub> > 12 ns.." hexmask.long.byte 0x10 16.--23. 1. "RDTURN,programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte)" newline bitfld.long 0x10 8.--9. "FMT,GETMXDS CCC format" "0: format 1 (2 bytes with MaxWr with no defining..,1: format 2: (5 bytes w.ith MaxWr with no defining..,2: format 2 (5 bytes with MaxWr with no defining..,3: format 2 (5 bytes with MaxWr with no defining.." bitfld.long 0x10 0.--1. "HOFFAS,Controller hand-off activity state" "0: activity state 0 is the initial activity state..,1: activity state 1 is the initial activity state..,2: activity state 2 is the initial activity state..,3: activity state 3 is the initial activity state.." line.long 0x14 "I3C_EPIDR,I3C extended provisioned ID register" hexmask.long.word 0x14 17.--31. 1. "MIPIMID,15-bit MIPI manufacturer ID" rbitfld.long 0x14 16. "IDTSEL,provisioned ID type selector" "0,1" newline hexmask.long.byte 0x14 12.--15. 1. "MIPIID,4-bit MIPI Instance ID" tree.end tree "I3C2" base ad:0x40006400 wgroup.long 0x0++0x3 line.long 0x0 "I3C_CR,I3C message control register" bitfld.long 0x0 31. "MEND,Message end type / last message of a frame (when the I3C acts as controller)" "0: this message from controller is followed by a..,1: this message from controller ends with a stop.." hexmask.long.byte 0x0 27.--30. 1. "MTYPE,Message type (whatever I3C acts as controller/target)" newline hexmask.long.byte 0x0 17.--23. 1. "ADD,7-bit I3C dynamic / I less than sup>2 less than /sup>C static target address (when I3C acts as controller)" bitfld.long 0x0 16. "RNW,Read / non-write message (when I3C acts as controller)" "0: write message,1: read message" newline hexmask.long.word 0x0 0.--15. 1. "DCNT,Count of data to transfer during a read or write message in bytes (whatever I3C acts as controller/target)" wgroup.long 0x0++0x3 line.long 0x0 "I3C_CR_alternate,I3C message control register" bitfld.long 0x0 31. "MEND,Message end type / last message of a frame (when I3C acts as controller)" "0: this message from controller is followed by a..,1: the message from the controller ends with a stop.." hexmask.long.byte 0x0 27.--30. 1. "MTYPE,Message type (when I3C acts as controller)" newline hexmask.long.byte 0x0 16.--23. 1. "CCC,8-bit CCC code (when I3C acts as controller)" hexmask.long.word 0x0 0.--15. 1. "DCNT,Count of related data to the CCC command to transfer as CCC defining bytes or CCC sub-command bytes or CCC data bytes in bytes" group.long 0x4++0x3 line.long 0x0 "I3C_CFGR,I3C configuration register" bitfld.long 0x0 30. "TSFSET,Frame transfer set (software trigger) (when I3C acts as controller)" "0: no action,1: setting this bit initiates a frame transfer by.." bitfld.long 0x0 21. "CFLUSH,C-FIFO flush (when I3C acts as controller)" "0: no action,1: flush C-FIFO" newline bitfld.long 0x0 20. "CDMAEN,C-FIFO DMA request enable (when I3C acts as controller)" "0: DMA mode is disabled for C-FIFO,1: DMA mode is enabled for C-FIFO" bitfld.long 0x0 19. "TMODE,Transmit mode (when I3C acts as controller)" "0: C-FIFO and TX-FIFO are not preloaded before..,1: C-FIFO and TX-FIFO are first preloaded (also.." newline bitfld.long 0x0 18. "SMODE,S-FIFO enable / status receive mode (when I3C acts as controller)" "0: S-FIFO is disabled,1: S-FIFO is enabled." bitfld.long 0x0 17. "SFLUSH,S-FIFO flush (when I3C acts as controller)" "0: no action,1: flush S-FIFO" newline bitfld.long 0x0 16. "SDMAEN,S-FIFO DMA request enable (when I3C acts as controller)" "0: DMA mode is disabled for reading status register..,1: DMA mode is enabled for reading status register.." bitfld.long 0x0 14. "TXTHRES,TX-FIFO threshold (whatever I3C acts as controller/target)" "0: 1-byte threshold,1: 1-word / 4-byte threshold" newline bitfld.long 0x0 13. "TXFLUSH,TX-FIFO flush (whatever I3C acts as controller/target)" "0: no action,1: flush TX-FIFO" bitfld.long 0x0 12. "TXDMAEN,TX-FIFO DMA request enable (whatever I3C acts as controller/target)" "0: DMA mode is disabled for TX-FIFO,1: DMA mode is enabled for TX-FIFO" newline bitfld.long 0x0 10. "RXTHRES,RX-FIFO threshold (whatever I3C acts as controller/target)" "0: 1-byte threshold,1: 1-word/4-bytes threshold" bitfld.long 0x0 9. "RXFLUSH,RX-FIFO flush (whatever I3C acts as controller/target)" "0: no action,1: flush RX-FIFO" newline bitfld.long 0x0 8. "RXDMAEN,RX-FIFO DMA request enable (whatever I3C acts as controller/target)" "0: DMA mode is disabled for RX-FIFO,1: DMA mode is enabled for RX-FIFO" bitfld.long 0x0 7. "HJACK,Hot-join request acknowledge (when I3C acts as a controller)" "0: hot-join request is not acknowledged,1: hot-join request is acknowledged" newline bitfld.long 0x0 5. "HKSDAEN,High-keeper enable on SDA line (when I3C acts as a controller)" "0: High-keeper is disabled,1: High-keeper is enabled and the weak pull-up is.." bitfld.long 0x0 4. "EXITPTRN,HDR exit pattern enable (when I3C acts as a controller)" "0: HDR exit pattern is not sent after the issued..,1: HDR exit pattern is sent after the issued.." newline bitfld.long 0x0 3. "RSTPTRN,HDR reset pattern enable (when I3C acts as a controller)" "0: standard stop emitted at the end of a frame,1: HDR reset pattern is inserted before the stop of.." bitfld.long 0x0 2. "NOARBH,No arbitrable header after a start (when I3C acts as a controller)" "0: An arbitrable header (0b111_1110 + RnW = 0) is..,1: No arbitrable header" newline bitfld.long 0x0 1. "CRINIT,Initial controller/target role" "0: target role,1: controller role" bitfld.long 0x0 0. "EN,I3C enable (whatever I3C acts as controller/target)" "0: I3C is disabled,1: I3C is enabled" rgroup.long 0x10++0x7 line.long 0x0 "I3C_RDR,I3C receive data byte register" hexmask.long.byte 0x0 0.--7. 1. "RDB0,8-bit received data on I3C bus." line.long 0x4 "I3C_RDWR,I3C receive data word register" hexmask.long.byte 0x4 24.--31. 1. "RDB3,8-bit received data (latest byte on I3C bus)." hexmask.long.byte 0x4 16.--23. 1. "RDB2,8-bit received data (next byte after RDB1 on I3C bus)." newline hexmask.long.byte 0x4 8.--15. 1. "RDB1,8-bit received data (next byte after RDB0 on I3C bus)." hexmask.long.byte 0x4 0.--7. 1. "RDB0,8-bit received data (earliest byte on I3C bus)." wgroup.long 0x18++0x7 line.long 0x0 "I3C_TDR,I3C transmit data byte register" hexmask.long.byte 0x0 0.--7. 1. "TDB0,8-bit data to transmit on I3C bus." line.long 0x4 "I3C_TDWR,I3C transmit data word register" hexmask.long.byte 0x4 24.--31. 1. "TDB3,8-bit transmit data (latest byte on I3C bus)." hexmask.long.byte 0x4 16.--23. 1. "TDB2,8-bit transmit data (next byte after TDB1[7:0] on I3C bus)." newline hexmask.long.byte 0x4 8.--15. 1. "TDB1,8-bit transmit data (next byte after TDB0[7:0] on I3C bus)." hexmask.long.byte 0x4 0.--7. 1. "TDB0,8-bit transmit data (earliest byte on I3C bus)" group.long 0x20++0x7 line.long 0x0 "I3C_IBIDR,I3C IBI payload data register" hexmask.long.byte 0x0 24.--31. 1. "IBIDB3,8-bit IBI payload data (latest byte on I3C bus)." hexmask.long.byte 0x0 16.--23. 1. "IBIDB2,8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0])." newline hexmask.long.byte 0x0 8.--15. 1. "IBIDB1,8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0])." hexmask.long.byte 0x0 0.--7. 1. "IBIDB0,8-bit IBI payload data (earliest byte on I3C bus MDB[7:0] mandatory data byte)." line.long 0x4 "I3C_TGTTDR,I3C target transmit configuration register" bitfld.long 0x4 16. "PRELOAD,Preload of the TX-FIFO (when I3C is configured as target)" "0: no TX-FIFO preload,1: TX-FIFO preload" hexmask.long.word 0x4 0.--15. 1. "TGTTDCNT,Transmit data counter in bytes (when I3C is configured as target)" rgroup.long 0x30++0x7 line.long 0x0 "I3C_SR,I3C status register" hexmask.long.byte 0x0 24.--31. 1. "MID,Message identifier/counter of a given frame (when the I3C acts as controller)" bitfld.long 0x0 18. "DIR,Message direction" "0: write,1: read" newline bitfld.long 0x0 17. "ABT,A private read message is ended prematurely by the target (when the I3C acts as controller)" "0: no early completion from the target,1: early completion from the target" hexmask.long.word 0x0 0.--15. 1. "XDCNT,Data counter" line.long 0x4 "I3C_SER,I3C status error register" bitfld.long 0x4 10. "DERR,Data error (when the I3C acts as controller)" "0: no detected error,1: controller detected a data error during the.." bitfld.long 0x4 9. "DNACK,Data not acknowledged (when the I3C acts as controller)" "0: no detected error,1: controller detected that a data byte is not.." newline bitfld.long 0x4 8. "ANACK,Address not acknowledged (when the I3C is configured as controller)" "0: no detected error,1: controller detected that the static/dynamic.." bitfld.long 0x4 7. "COVR,C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller)" "0: no detected error,1: controller detected either:" newline bitfld.long 0x4 6. "DOVR,RX-FIFO overrun or TX-FIFO underrun" "0: no detected error,1: whatever controller or target hardware detected.." bitfld.long 0x4 5. "STALL,SCL stall error (when the I3C acts as target)" "0: no detected error,1: target detected that SCL was stable for more.." newline bitfld.long 0x4 4. "PERR,Protocol error" "0: no detected error,1: whatever controller or target hardware detected.." hexmask.long.byte 0x4 0.--3. 1. "CODERR,Protocol error code/type" rgroup.long 0x40++0x3 line.long 0x0 "I3C_RMR,I3C received message register" hexmask.long.byte 0x0 17.--23. 1. "RADD,Received target address (when the I3C is configured as controller)" hexmask.long.byte 0x0 8.--15. 1. "RCODE,Received CCC code (when the I3C is configured as target)" newline bitfld.long 0x0 0.--2. "IBIRDCNT,IBI received payload data count (when the I3C is configured as controller)" "0,1,2,3,4,5,6,7" rgroup.long 0x50++0x7 line.long 0x0 "I3C_EVR,I3C event register" bitfld.long 0x0 31. "GRPF,Group addressing flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 30. "DEFF,DEFTGTS flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 29. "INTUPDF,Interrupt/controller-role/hot-join update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 28. "ASUPDF,Activity state update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 27. "RSTF,Reset pattern flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 26. "MRLUPDF,Maximum read length update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 25. "MWLUPDF,Maximum write length update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 24. "DAUPDF,Dynamic address update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 23. "STAF,Get status flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 22. "GETF,Get flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 21. "WKPF,Wake-up/missed start flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 19. "HJF,Hot-join flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 18. "CRUPDF,Controller-role update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 17. "CRF,Controller-role request flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 16. "IBIENDF,IBI end flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 15. "IBIF,IBI flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 11. "ERRF,Flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 10. "RXTGTENDF,Target-initiated read end flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 9. "FCF,Frame complete flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 7. "RXLASTF,Last read data byte/word flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 6. "TXLASTF,Last written data byte/word flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 5. "RXFNEF,RX-FIFO not empty flag (whatever the I3C acts as controller/target)" "0,1" newline bitfld.long 0x0 4. "TXFNFF,TX-FIFO not full flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 3. "SFNEF,S-FIFO not empty flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 2. "CFNFF,C-FIFO not full flag (when the I3C acts as controller)" "0,1" bitfld.long 0x0 1. "TXFEF,TX-FIFO empty flag (whatever the I3C acts as controller/target)" "0,1" newline bitfld.long 0x0 0. "CFEF,C-FIFO empty flag (whatever the I3C acts as controller)" "0,1" line.long 0x4 "I3C_IER,I3C interrupt enable register" bitfld.long 0x4 31. "GRPIE,DEFGRPA CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 30. "DEFIE,DEFTGTS CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 29. "INTUPDIE,ENEC/DISEC CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 28. "ASUPDIE,ENTASx CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 27. "RSTIE,reset pattern interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 26. "MRLUPDIE,SETMRL CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 25. "MWLUPDIE,SETMWL CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 24. "DAUPDIE,ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 23. "STAIE,format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 22. "GETIE,GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 21. "WKPIE,Wake-up interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 19. "HJIE,Hot-join interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 18. "CRUPDIE,Controller-role update interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 17. "CRIE,Controller-role request interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 16. "IBIENDIE,IBI end interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 15. "IBIIE,IBI request interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 11. "ERRIE,error interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 10. "RXTGTENDIE,target-initiated read end interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 9. "FCIE,frame complete interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 5. "RXFNEIE,RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 4. "TXFNFIE,TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 3. "SFNEIE,S-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 2. "CFNFIE,C-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" wgroup.long 0x58++0x3 line.long 0x0 "I3C_CEVR,I3C clear event register" bitfld.long 0x0 31. "CGRPF,Clear DEFGRPA CCC flag (when the I3C acts as target)" "0: no effect,1: clear GRPF" bitfld.long 0x0 30. "CDEFF,Clear DEFTGTS CCC flag (when the I3C acts as target)" "0: no effect,1: clear DEFF" newline bitfld.long 0x0 29. "CINTUPDF,Clear ENEC/DISEC CCC flag (when the I3C acts as target)" "0: no effect,1: clear CINTUPDF" bitfld.long 0x0 28. "CASUPDF,Clear ENTASx CCC flag (when the I3C acts as target)" "0: no effect,1: clear ASUPDF" newline bitfld.long 0x0 27. "CRSTF,Clear reset pattern flag (when the I3C acts as target)" "0: no effect,1: clear RSTF" bitfld.long 0x0 26. "CMRLUPDF,Clear SETMRL CCC flag (when the I3C acts as target)" "0: no effect,1: clear MRLUPDF" newline bitfld.long 0x0 25. "CMWLUPDF,Clear SETMWL CCC flag (when the I3C acts as target)" "0: no effect,1: clear MWLUPDF" bitfld.long 0x0 24. "CDAUPDF,Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target)" "0: no effect,1: clear DAUPDF" newline bitfld.long 0x0 23. "CSTAF,Clear format 1 GETSTATUS CCC flag (when the I3C acts as target)" "0: no effect,1: clear STAF" bitfld.long 0x0 22. "CGETF,Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target)" "0: no effect,1: clear GETF" newline bitfld.long 0x0 21. "CWKPF,Clear wake-up flag (when the I3C acts as target)" "0: no effect,1: clear WKPF" bitfld.long 0x0 19. "CHJF,Clear hot-join flag (when the I3C acts as controller)" "0: no effect,1: clear HJF" newline bitfld.long 0x0 18. "CCRUPDF,Clear controller-role update flag (when the I3C acts as target)" "0: no effect,1: clear CRUPDF" bitfld.long 0x0 17. "CCRF,Clear controller-role request flag (when the I3C acts as controller)" "0: no effect,1: clear CRF" newline bitfld.long 0x0 16. "CIBIENDF,Clear IBI end flag (when the I3C acts as target)" "0: no effect,1: clear IBIENDF" bitfld.long 0x0 15. "CIBIF,Clear IBI request flag (when the I3C acts as controller)" "0: no effect,1: clear IBIF" newline bitfld.long 0x0 11. "CERRF,Clear error flag (whatever the I3C acts as controller/target)" "0: no effect,1: clear ERRF" bitfld.long 0x0 10. "CRXTGTENDF,Clear target-initiated read end flag (when the I3C acts as controller)" "0: no effect,1: clear RXTGTENDF" newline bitfld.long 0x0 9. "CFCF,Clear frame complete flag (whatever the I3C acts as controller/target)" "0: no effect,1: clear FCF" group.long 0x60++0x13 line.long 0x0 "I3C_DEVR0,I3C own device characteristics register" rbitfld.long 0x0 24. "RSTVAL,Reset action is valid (when the I3C acts as target)" "0,1" rbitfld.long 0x0 22.--23. "RSTACT,Reset action/level on received reset pattern (when the I3C acts as target)" "0: no reset action,1: first level of reset: the application software..,2: second level of reset: the application software..,3: no reset action" newline rbitfld.long 0x0 20.--21. "AS,Activity state (when the I3C acts as target)" "0: activity state 0,1: activity state 1,2: activity state 2,3: activity state 3" bitfld.long 0x0 19. "HJEN,Hot-join request enable (when the I3C acts as target)" "0: hot-join request disabled,1: hot-join request enabled" newline bitfld.long 0x0 17. "CREN,Controller-role request enable (when the I3C acts as target)" "0: controller-role request disabled,1: controller-role request enabled" bitfld.long 0x0 16. "IBIEN,IBI request enable (when the I3C acts as target)" "0: IBI request disabled,1: IBI request enabled" newline hexmask.long.byte 0x0 1.--7. 1. "DA,7-bit dynamic address" bitfld.long 0x0 0. "DAVAL,Dynamic address is valid (when the I3C acts as target)" "0,1" line.long 0x4 "I3C_DEVR1,I3C device 1 characteristics register" rbitfld.long 0x4 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x4 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x4 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x4 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x4 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x4 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0x8 "I3C_DEVR2,I3C device 2 characteristics register" rbitfld.long 0x8 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x8 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x8 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x8 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x8 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x8 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0xC "I3C_DEVR3,I3C device 3 characteristics register" rbitfld.long 0xC 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0xC 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0xC 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0xC 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0xC 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0xC 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0x10 "I3C_DEVR4,I3C device 4 characteristics register" rbitfld.long 0x10 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x10 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x10 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x10 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x10 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x10 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" group.long 0x90++0x7 line.long 0x0 "I3C_MAXRLR,I3C maximum read length register" bitfld.long 0x0 16.--18. "IBIP,IBI payload data maximum size in bytes (when I3C acts as target)" "0: null payload data size (only allowed when BCR2 =..,1: 1 byte (mandatory data byte MDB[7:0],2: 2 bytes (including first MDB[7:0]),3: 3 bytes (including first MDB[7:0]),4: 4 bytes (including first MDB[7:0]),?,?,?" hexmask.long.word 0x0 0.--15. 1. "MRL,Maximum data read length (when I3C acts as target)" line.long 0x4 "I3C_MAXWLR,I3C maximum write length register" hexmask.long.word 0x4 0.--15. 1. "MWL,Maximum data write length (when I3C acts as target)" group.long 0xA0++0xB line.long 0x0 "I3C_TIMINGR0,I3C timing register 0" hexmask.long.byte 0x0 24.--31. 1. "SCLH_I2C,SCL high duration used for legacy I less than sup>2 less than /sup>C messages in number of kernel clocks cycles:" hexmask.long.byte 0x0 16.--23. 1. "SCLL_OD,SCL low duration in open-drain phases used for legacy I less than sup>2 less than /sup>C messages and for I3C open-drain phases (address phase following a start ACK phase during controller-initiated messages and T bit phase during.." newline hexmask.long.byte 0x0 8.--15. 1. "SCLH_I3C,SCL high duration used for I3C messages (both in push-pull and open-drain phases) in number of kernel clocks cycles:" hexmask.long.byte 0x0 0.--7. 1. "SCLL_PP,SCL low duration in I3C push-pull phases in number of kernel clocks cycles:" line.long 0x4 "I3C_TIMINGR1,I3C timing register 1" bitfld.long 0x4 28. "SDA_HD,SDA hold time (when the I3C acts as controller) in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull t less than sub>HD_PP less than /sub>):" "0,1" hexmask.long.byte 0x4 16.--22. 1. "FREE,Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller)" newline bitfld.long 0x4 8.--9. "ASNCR,Activity state of the new controller (when I3C acts as active controller)" "0,1,2,3" hexmask.long.byte 0x4 0.--7. 1. "AVAL,Number of kernel clock cycles to set a time unit of 1 s whatever I3C acts as controller or target." line.long 0x8 "I3C_TIMINGR2,I3C timing register 2" hexmask.long.byte 0x8 8.--15. 1. "STALL,Controller clock stall time in number of kernel clock cycles" bitfld.long 0x8 3. "STALLA,Controller clock stall enable on ACK phase" "0: no stall,1: stall enabled" newline bitfld.long 0x8 2. "STALLC,Controller clock stall enable on PAR phase of CCC" "0: no stall,1: stall enabled" bitfld.long 0x8 1. "STALLD,Controller clock stall enable on PAR phase of Data" "0: no stall,1: stall enabled" newline bitfld.long 0x8 0. "STALLT,Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy I less than sup>2 less than /sup>C read)" "0: no stall,1: stall enabled" group.long 0xC0++0x17 line.long 0x0 "I3C_BCR,I3C bus characteristics register" bitfld.long 0x0 6. "BCR6,Controller capable" "0: I3C target (no controller capable),1: I3C controller capable" bitfld.long 0x0 2. "BCR2,in-band interrupt (IBI) payload" "0: no data byte follows the accepted IBI,1: at least one mandatory data byte follows the.." newline bitfld.long 0x0 0. "BCR0,max data speed limitation" "0: no limitation,1: limitation as described by I3C_GETMXDSR." line.long 0x4 "I3C_DCR,I3C device characteristics register" hexmask.long.byte 0x4 0.--7. 1. "DCR,device characteristics ID" line.long 0x8 "I3C_GETCAPR,I3C get capability register" bitfld.long 0x8 14. "CAPPEND,IBI MDB support for pending read notification" "0: this I3C when acting as target sends an IBI..,1: this I3C when acting as target sends an IBI.." line.long 0xC "I3C_CRCAPR,I3C controller-role capability register" bitfld.long 0xC 9. "CAPGRP,group management support (when acting as controller)" "0: this I3C does not support group address..,1: this I3C supports group address capabilities.." bitfld.long 0xC 3. "CAPDHOFF,delayed controller-role hand-off" "0: this I3C does not needs additional time to..,1: this I3C needs additional time to process a.." line.long 0x10 "I3C_GETMXDSR,I3C get capability register" bitfld.long 0x10 24. "TSCO,clock-to-data turnaround time (t less than sub>SCO less than /sub>)" "0: t less than sub>SCO less than /sub> less than or..,1: t less than sub>SCO less than /sub> > 12 ns.." hexmask.long.byte 0x10 16.--23. 1. "RDTURN,programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte)" newline bitfld.long 0x10 8.--9. "FMT,GETMXDS CCC format" "0: format 1 (2 bytes with MaxWr with no defining..,1: format 2: (5 bytes w.ith MaxWr with no defining..,2: format 2 (5 bytes with MaxWr with no defining..,3: format 2 (5 bytes with MaxWr with no defining.." bitfld.long 0x10 0.--1. "HOFFAS,Controller hand-off activity state" "0: activity state 0 is the initial activity state..,1: activity state 1 is the initial activity state..,2: activity state 2 is the initial activity state..,3: activity state 3 is the initial activity state.." line.long 0x14 "I3C_EPIDR,I3C extended provisioned ID register" hexmask.long.word 0x14 17.--31. 1. "MIPIMID,15-bit MIPI manufacturer ID" rbitfld.long 0x14 16. "IDTSEL,provisioned ID type selector" "0,1" newline hexmask.long.byte 0x14 12.--15. 1. "MIPIID,4-bit MIPI Instance ID" tree.end tree "I3C2_S" base ad:0x50006400 wgroup.long 0x0++0x3 line.long 0x0 "I3C_CR,I3C message control register" bitfld.long 0x0 31. "MEND,Message end type / last message of a frame (when the I3C acts as controller)" "0: this message from controller is followed by a..,1: this message from controller ends with a stop.." hexmask.long.byte 0x0 27.--30. 1. "MTYPE,Message type (whatever I3C acts as controller/target)" newline hexmask.long.byte 0x0 17.--23. 1. "ADD,7-bit I3C dynamic / I less than sup>2 less than /sup>C static target address (when I3C acts as controller)" bitfld.long 0x0 16. "RNW,Read / non-write message (when I3C acts as controller)" "0: write message,1: read message" newline hexmask.long.word 0x0 0.--15. 1. "DCNT,Count of data to transfer during a read or write message in bytes (whatever I3C acts as controller/target)" wgroup.long 0x0++0x3 line.long 0x0 "I3C_CR_alternate,I3C message control register" bitfld.long 0x0 31. "MEND,Message end type / last message of a frame (when I3C acts as controller)" "0: this message from controller is followed by a..,1: the message from the controller ends with a stop.." hexmask.long.byte 0x0 27.--30. 1. "MTYPE,Message type (when I3C acts as controller)" newline hexmask.long.byte 0x0 16.--23. 1. "CCC,8-bit CCC code (when I3C acts as controller)" hexmask.long.word 0x0 0.--15. 1. "DCNT,Count of related data to the CCC command to transfer as CCC defining bytes or CCC sub-command bytes or CCC data bytes in bytes" group.long 0x4++0x3 line.long 0x0 "I3C_CFGR,I3C configuration register" bitfld.long 0x0 30. "TSFSET,Frame transfer set (software trigger) (when I3C acts as controller)" "0: no action,1: setting this bit initiates a frame transfer by.." bitfld.long 0x0 21. "CFLUSH,C-FIFO flush (when I3C acts as controller)" "0: no action,1: flush C-FIFO" newline bitfld.long 0x0 20. "CDMAEN,C-FIFO DMA request enable (when I3C acts as controller)" "0: DMA mode is disabled for C-FIFO,1: DMA mode is enabled for C-FIFO" bitfld.long 0x0 19. "TMODE,Transmit mode (when I3C acts as controller)" "0: C-FIFO and TX-FIFO are not preloaded before..,1: C-FIFO and TX-FIFO are first preloaded (also.." newline bitfld.long 0x0 18. "SMODE,S-FIFO enable / status receive mode (when I3C acts as controller)" "0: S-FIFO is disabled,1: S-FIFO is enabled." bitfld.long 0x0 17. "SFLUSH,S-FIFO flush (when I3C acts as controller)" "0: no action,1: flush S-FIFO" newline bitfld.long 0x0 16. "SDMAEN,S-FIFO DMA request enable (when I3C acts as controller)" "0: DMA mode is disabled for reading status register..,1: DMA mode is enabled for reading status register.." bitfld.long 0x0 14. "TXTHRES,TX-FIFO threshold (whatever I3C acts as controller/target)" "0: 1-byte threshold,1: 1-word / 4-byte threshold" newline bitfld.long 0x0 13. "TXFLUSH,TX-FIFO flush (whatever I3C acts as controller/target)" "0: no action,1: flush TX-FIFO" bitfld.long 0x0 12. "TXDMAEN,TX-FIFO DMA request enable (whatever I3C acts as controller/target)" "0: DMA mode is disabled for TX-FIFO,1: DMA mode is enabled for TX-FIFO" newline bitfld.long 0x0 10. "RXTHRES,RX-FIFO threshold (whatever I3C acts as controller/target)" "0: 1-byte threshold,1: 1-word/4-bytes threshold" bitfld.long 0x0 9. "RXFLUSH,RX-FIFO flush (whatever I3C acts as controller/target)" "0: no action,1: flush RX-FIFO" newline bitfld.long 0x0 8. "RXDMAEN,RX-FIFO DMA request enable (whatever I3C acts as controller/target)" "0: DMA mode is disabled for RX-FIFO,1: DMA mode is enabled for RX-FIFO" bitfld.long 0x0 7. "HJACK,Hot-join request acknowledge (when I3C acts as a controller)" "0: hot-join request is not acknowledged,1: hot-join request is acknowledged" newline bitfld.long 0x0 5. "HKSDAEN,High-keeper enable on SDA line (when I3C acts as a controller)" "0: High-keeper is disabled,1: High-keeper is enabled and the weak pull-up is.." bitfld.long 0x0 4. "EXITPTRN,HDR exit pattern enable (when I3C acts as a controller)" "0: HDR exit pattern is not sent after the issued..,1: HDR exit pattern is sent after the issued.." newline bitfld.long 0x0 3. "RSTPTRN,HDR reset pattern enable (when I3C acts as a controller)" "0: standard stop emitted at the end of a frame,1: HDR reset pattern is inserted before the stop of.." bitfld.long 0x0 2. "NOARBH,No arbitrable header after a start (when I3C acts as a controller)" "0: An arbitrable header (0b111_1110 + RnW = 0) is..,1: No arbitrable header" newline bitfld.long 0x0 1. "CRINIT,Initial controller/target role" "0: target role,1: controller role" bitfld.long 0x0 0. "EN,I3C enable (whatever I3C acts as controller/target)" "0: I3C is disabled,1: I3C is enabled" rgroup.long 0x10++0x7 line.long 0x0 "I3C_RDR,I3C receive data byte register" hexmask.long.byte 0x0 0.--7. 1. "RDB0,8-bit received data on I3C bus." line.long 0x4 "I3C_RDWR,I3C receive data word register" hexmask.long.byte 0x4 24.--31. 1. "RDB3,8-bit received data (latest byte on I3C bus)." hexmask.long.byte 0x4 16.--23. 1. "RDB2,8-bit received data (next byte after RDB1 on I3C bus)." newline hexmask.long.byte 0x4 8.--15. 1. "RDB1,8-bit received data (next byte after RDB0 on I3C bus)." hexmask.long.byte 0x4 0.--7. 1. "RDB0,8-bit received data (earliest byte on I3C bus)." wgroup.long 0x18++0x7 line.long 0x0 "I3C_TDR,I3C transmit data byte register" hexmask.long.byte 0x0 0.--7. 1. "TDB0,8-bit data to transmit on I3C bus." line.long 0x4 "I3C_TDWR,I3C transmit data word register" hexmask.long.byte 0x4 24.--31. 1. "TDB3,8-bit transmit data (latest byte on I3C bus)." hexmask.long.byte 0x4 16.--23. 1. "TDB2,8-bit transmit data (next byte after TDB1[7:0] on I3C bus)." newline hexmask.long.byte 0x4 8.--15. 1. "TDB1,8-bit transmit data (next byte after TDB0[7:0] on I3C bus)." hexmask.long.byte 0x4 0.--7. 1. "TDB0,8-bit transmit data (earliest byte on I3C bus)" group.long 0x20++0x7 line.long 0x0 "I3C_IBIDR,I3C IBI payload data register" hexmask.long.byte 0x0 24.--31. 1. "IBIDB3,8-bit IBI payload data (latest byte on I3C bus)." hexmask.long.byte 0x0 16.--23. 1. "IBIDB2,8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0])." newline hexmask.long.byte 0x0 8.--15. 1. "IBIDB1,8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0])." hexmask.long.byte 0x0 0.--7. 1. "IBIDB0,8-bit IBI payload data (earliest byte on I3C bus MDB[7:0] mandatory data byte)." line.long 0x4 "I3C_TGTTDR,I3C target transmit configuration register" bitfld.long 0x4 16. "PRELOAD,Preload of the TX-FIFO (when I3C is configured as target)" "0: no TX-FIFO preload,1: TX-FIFO preload" hexmask.long.word 0x4 0.--15. 1. "TGTTDCNT,Transmit data counter in bytes (when I3C is configured as target)" rgroup.long 0x30++0x7 line.long 0x0 "I3C_SR,I3C status register" hexmask.long.byte 0x0 24.--31. 1. "MID,Message identifier/counter of a given frame (when the I3C acts as controller)" bitfld.long 0x0 18. "DIR,Message direction" "0: write,1: read" newline bitfld.long 0x0 17. "ABT,A private read message is ended prematurely by the target (when the I3C acts as controller)" "0: no early completion from the target,1: early completion from the target" hexmask.long.word 0x0 0.--15. 1. "XDCNT,Data counter" line.long 0x4 "I3C_SER,I3C status error register" bitfld.long 0x4 10. "DERR,Data error (when the I3C acts as controller)" "0: no detected error,1: controller detected a data error during the.." bitfld.long 0x4 9. "DNACK,Data not acknowledged (when the I3C acts as controller)" "0: no detected error,1: controller detected that a data byte is not.." newline bitfld.long 0x4 8. "ANACK,Address not acknowledged (when the I3C is configured as controller)" "0: no detected error,1: controller detected that the static/dynamic.." bitfld.long 0x4 7. "COVR,C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller)" "0: no detected error,1: controller detected either:" newline bitfld.long 0x4 6. "DOVR,RX-FIFO overrun or TX-FIFO underrun" "0: no detected error,1: whatever controller or target hardware detected.." bitfld.long 0x4 5. "STALL,SCL stall error (when the I3C acts as target)" "0: no detected error,1: target detected that SCL was stable for more.." newline bitfld.long 0x4 4. "PERR,Protocol error" "0: no detected error,1: whatever controller or target hardware detected.." hexmask.long.byte 0x4 0.--3. 1. "CODERR,Protocol error code/type" rgroup.long 0x40++0x3 line.long 0x0 "I3C_RMR,I3C received message register" hexmask.long.byte 0x0 17.--23. 1. "RADD,Received target address (when the I3C is configured as controller)" hexmask.long.byte 0x0 8.--15. 1. "RCODE,Received CCC code (when the I3C is configured as target)" newline bitfld.long 0x0 0.--2. "IBIRDCNT,IBI received payload data count (when the I3C is configured as controller)" "0,1,2,3,4,5,6,7" rgroup.long 0x50++0x7 line.long 0x0 "I3C_EVR,I3C event register" bitfld.long 0x0 31. "GRPF,Group addressing flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 30. "DEFF,DEFTGTS flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 29. "INTUPDF,Interrupt/controller-role/hot-join update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 28. "ASUPDF,Activity state update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 27. "RSTF,Reset pattern flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 26. "MRLUPDF,Maximum read length update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 25. "MWLUPDF,Maximum write length update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 24. "DAUPDF,Dynamic address update flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 23. "STAF,Get status flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 22. "GETF,Get flag (when the I3C acts as target)" "0,1" newline bitfld.long 0x0 21. "WKPF,Wake-up/missed start flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 19. "HJF,Hot-join flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 18. "CRUPDF,Controller-role update flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 17. "CRF,Controller-role request flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 16. "IBIENDF,IBI end flag (when the I3C acts as target)" "0,1" bitfld.long 0x0 15. "IBIF,IBI flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 11. "ERRF,Flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 10. "RXTGTENDF,Target-initiated read end flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 9. "FCF,Frame complete flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 7. "RXLASTF,Last read data byte/word flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 6. "TXLASTF,Last written data byte/word flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 5. "RXFNEF,RX-FIFO not empty flag (whatever the I3C acts as controller/target)" "0,1" newline bitfld.long 0x0 4. "TXFNFF,TX-FIFO not full flag (whatever the I3C acts as controller/target)" "0,1" bitfld.long 0x0 3. "SFNEF,S-FIFO not empty flag (when the I3C acts as controller)" "0,1" newline bitfld.long 0x0 2. "CFNFF,C-FIFO not full flag (when the I3C acts as controller)" "0,1" bitfld.long 0x0 1. "TXFEF,TX-FIFO empty flag (whatever the I3C acts as controller/target)" "0,1" newline bitfld.long 0x0 0. "CFEF,C-FIFO empty flag (whatever the I3C acts as controller)" "0,1" line.long 0x4 "I3C_IER,I3C interrupt enable register" bitfld.long 0x4 31. "GRPIE,DEFGRPA CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 30. "DEFIE,DEFTGTS CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 29. "INTUPDIE,ENEC/DISEC CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 28. "ASUPDIE,ENTASx CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 27. "RSTIE,reset pattern interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 26. "MRLUPDIE,SETMRL CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 25. "MWLUPDIE,SETMWL CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 24. "DAUPDIE,ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 23. "STAIE,format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 22. "GETIE,GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 21. "WKPIE,Wake-up interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 19. "HJIE,Hot-join interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 18. "CRUPDIE,Controller-role update interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 17. "CRIE,Controller-role request interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 16. "IBIENDIE,IBI end interrupt enable (when the I3C acts as target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 15. "IBIIE,IBI request interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 11. "ERRIE,error interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 10. "RXTGTENDIE,target-initiated read end interrupt enable (when the I3C acts as controller)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 9. "FCIE,frame complete interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 5. "RXFNEIE,RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 4. "TXFNFIE,TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x4 3. "SFNEIE,S-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x4 2. "CFNFIE,C-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" "0: interrupt disabled,1: interrupt enabled" wgroup.long 0x58++0x3 line.long 0x0 "I3C_CEVR,I3C clear event register" bitfld.long 0x0 31. "CGRPF,Clear DEFGRPA CCC flag (when the I3C acts as target)" "0: no effect,1: clear GRPF" bitfld.long 0x0 30. "CDEFF,Clear DEFTGTS CCC flag (when the I3C acts as target)" "0: no effect,1: clear DEFF" newline bitfld.long 0x0 29. "CINTUPDF,Clear ENEC/DISEC CCC flag (when the I3C acts as target)" "0: no effect,1: clear CINTUPDF" bitfld.long 0x0 28. "CASUPDF,Clear ENTASx CCC flag (when the I3C acts as target)" "0: no effect,1: clear ASUPDF" newline bitfld.long 0x0 27. "CRSTF,Clear reset pattern flag (when the I3C acts as target)" "0: no effect,1: clear RSTF" bitfld.long 0x0 26. "CMRLUPDF,Clear SETMRL CCC flag (when the I3C acts as target)" "0: no effect,1: clear MRLUPDF" newline bitfld.long 0x0 25. "CMWLUPDF,Clear SETMWL CCC flag (when the I3C acts as target)" "0: no effect,1: clear MWLUPDF" bitfld.long 0x0 24. "CDAUPDF,Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target)" "0: no effect,1: clear DAUPDF" newline bitfld.long 0x0 23. "CSTAF,Clear format 1 GETSTATUS CCC flag (when the I3C acts as target)" "0: no effect,1: clear STAF" bitfld.long 0x0 22. "CGETF,Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target)" "0: no effect,1: clear GETF" newline bitfld.long 0x0 21. "CWKPF,Clear wake-up flag (when the I3C acts as target)" "0: no effect,1: clear WKPF" bitfld.long 0x0 19. "CHJF,Clear hot-join flag (when the I3C acts as controller)" "0: no effect,1: clear HJF" newline bitfld.long 0x0 18. "CCRUPDF,Clear controller-role update flag (when the I3C acts as target)" "0: no effect,1: clear CRUPDF" bitfld.long 0x0 17. "CCRF,Clear controller-role request flag (when the I3C acts as controller)" "0: no effect,1: clear CRF" newline bitfld.long 0x0 16. "CIBIENDF,Clear IBI end flag (when the I3C acts as target)" "0: no effect,1: clear IBIENDF" bitfld.long 0x0 15. "CIBIF,Clear IBI request flag (when the I3C acts as controller)" "0: no effect,1: clear IBIF" newline bitfld.long 0x0 11. "CERRF,Clear error flag (whatever the I3C acts as controller/target)" "0: no effect,1: clear ERRF" bitfld.long 0x0 10. "CRXTGTENDF,Clear target-initiated read end flag (when the I3C acts as controller)" "0: no effect,1: clear RXTGTENDF" newline bitfld.long 0x0 9. "CFCF,Clear frame complete flag (whatever the I3C acts as controller/target)" "0: no effect,1: clear FCF" group.long 0x60++0x13 line.long 0x0 "I3C_DEVR0,I3C own device characteristics register" rbitfld.long 0x0 24. "RSTVAL,Reset action is valid (when the I3C acts as target)" "0,1" rbitfld.long 0x0 22.--23. "RSTACT,Reset action/level on received reset pattern (when the I3C acts as target)" "0: no reset action,1: first level of reset: the application software..,2: second level of reset: the application software..,3: no reset action" newline rbitfld.long 0x0 20.--21. "AS,Activity state (when the I3C acts as target)" "0: activity state 0,1: activity state 1,2: activity state 2,3: activity state 3" bitfld.long 0x0 19. "HJEN,Hot-join request enable (when the I3C acts as target)" "0: hot-join request disabled,1: hot-join request enabled" newline bitfld.long 0x0 17. "CREN,Controller-role request enable (when the I3C acts as target)" "0: controller-role request disabled,1: controller-role request enabled" bitfld.long 0x0 16. "IBIEN,IBI request enable (when the I3C acts as target)" "0: IBI request disabled,1: IBI request enabled" newline hexmask.long.byte 0x0 1.--7. 1. "DA,7-bit dynamic address" bitfld.long 0x0 0. "DAVAL,Dynamic address is valid (when the I3C acts as target)" "0,1" line.long 0x4 "I3C_DEVR1,I3C device 1 characteristics register" rbitfld.long 0x4 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x4 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x4 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x4 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x4 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x4 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0x8 "I3C_DEVR2,I3C device 2 characteristics register" rbitfld.long 0x8 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x8 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x8 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x8 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x8 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x8 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0xC "I3C_DEVR3,I3C device 3 characteristics register" rbitfld.long 0xC 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0xC 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0xC 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0xC 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0xC 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0xC 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" line.long 0x10 "I3C_DEVR4,I3C device 4 characteristics register" rbitfld.long 0x10 31. "DIS,DA[6:0] write disabled (when the I3C acts as controller)" "0: write to DA[7:0] and to IBIDEN in the I3C_DEVRx..,1: write to DA[7:0] and to IBIDEN is disabled/locked" bitfld.long 0x10 19. "SUSP,Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" "0: C-FIFO and TX-FIFO are not flushed after an IBI..,1: I3C transfer is stopped and both C-FIFO and.." newline bitfld.long 0x10 18. "IBIDEN,IBI data enable (when the I3C acts as controller)" "0: no data byte follows the acknowledged IBI from..,1: the mandatory data byte MDB[7:0] follows the.." bitfld.long 0x10 17. "CRACK,Controller-role request acknowledge (when the I3C acts as controller)" "0: a controller-role request from target x must be..,1: a controller-role request (with 7-bit dynamic.." newline bitfld.long 0x10 16. "IBIACK,IBI request acknowledge (when the I3C acts as controller)" "0: an IBI request from target x must be NACK-ed,1: an IBI request (with 7-bit dynamic address.." hexmask.long.byte 0x10 1.--7. 1. "DA,Assigned I3C dynamic address to target x (when the I3C acts as controller)" group.long 0x90++0x7 line.long 0x0 "I3C_MAXRLR,I3C maximum read length register" bitfld.long 0x0 16.--18. "IBIP,IBI payload data maximum size in bytes (when I3C acts as target)" "0: null payload data size (only allowed when BCR2 =..,1: 1 byte (mandatory data byte MDB[7:0],2: 2 bytes (including first MDB[7:0]),3: 3 bytes (including first MDB[7:0]),4: 4 bytes (including first MDB[7:0]),?,?,?" hexmask.long.word 0x0 0.--15. 1. "MRL,Maximum data read length (when I3C acts as target)" line.long 0x4 "I3C_MAXWLR,I3C maximum write length register" hexmask.long.word 0x4 0.--15. 1. "MWL,Maximum data write length (when I3C acts as target)" group.long 0xA0++0xB line.long 0x0 "I3C_TIMINGR0,I3C timing register 0" hexmask.long.byte 0x0 24.--31. 1. "SCLH_I2C,SCL high duration used for legacy I less than sup>2 less than /sup>C messages in number of kernel clocks cycles:" hexmask.long.byte 0x0 16.--23. 1. "SCLL_OD,SCL low duration in open-drain phases used for legacy I less than sup>2 less than /sup>C messages and for I3C open-drain phases (address phase following a start ACK phase during controller-initiated messages and T bit phase during.." newline hexmask.long.byte 0x0 8.--15. 1. "SCLH_I3C,SCL high duration used for I3C messages (both in push-pull and open-drain phases) in number of kernel clocks cycles:" hexmask.long.byte 0x0 0.--7. 1. "SCLL_PP,SCL low duration in I3C push-pull phases in number of kernel clocks cycles:" line.long 0x4 "I3C_TIMINGR1,I3C timing register 1" bitfld.long 0x4 28. "SDA_HD,SDA hold time (when the I3C acts as controller) in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull t less than sub>HD_PP less than /sub>):" "0,1" hexmask.long.byte 0x4 16.--22. 1. "FREE,Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller)" newline bitfld.long 0x4 8.--9. "ASNCR,Activity state of the new controller (when I3C acts as active controller)" "0,1,2,3" hexmask.long.byte 0x4 0.--7. 1. "AVAL,Number of kernel clock cycles to set a time unit of 1 s whatever I3C acts as controller or target." line.long 0x8 "I3C_TIMINGR2,I3C timing register 2" hexmask.long.byte 0x8 8.--15. 1. "STALL,Controller clock stall time in number of kernel clock cycles" bitfld.long 0x8 3. "STALLA,Controller clock stall enable on ACK phase" "0: no stall,1: stall enabled" newline bitfld.long 0x8 2. "STALLC,Controller clock stall enable on PAR phase of CCC" "0: no stall,1: stall enabled" bitfld.long 0x8 1. "STALLD,Controller clock stall enable on PAR phase of Data" "0: no stall,1: stall enabled" newline bitfld.long 0x8 0. "STALLT,Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy I less than sup>2 less than /sup>C read)" "0: no stall,1: stall enabled" group.long 0xC0++0x17 line.long 0x0 "I3C_BCR,I3C bus characteristics register" bitfld.long 0x0 6. "BCR6,Controller capable" "0: I3C target (no controller capable),1: I3C controller capable" bitfld.long 0x0 2. "BCR2,in-band interrupt (IBI) payload" "0: no data byte follows the accepted IBI,1: at least one mandatory data byte follows the.." newline bitfld.long 0x0 0. "BCR0,max data speed limitation" "0: no limitation,1: limitation as described by I3C_GETMXDSR." line.long 0x4 "I3C_DCR,I3C device characteristics register" hexmask.long.byte 0x4 0.--7. 1. "DCR,device characteristics ID" line.long 0x8 "I3C_GETCAPR,I3C get capability register" bitfld.long 0x8 14. "CAPPEND,IBI MDB support for pending read notification" "0: this I3C when acting as target sends an IBI..,1: this I3C when acting as target sends an IBI.." line.long 0xC "I3C_CRCAPR,I3C controller-role capability register" bitfld.long 0xC 9. "CAPGRP,group management support (when acting as controller)" "0: this I3C does not support group address..,1: this I3C supports group address capabilities.." bitfld.long 0xC 3. "CAPDHOFF,delayed controller-role hand-off" "0: this I3C does not needs additional time to..,1: this I3C needs additional time to process a.." line.long 0x10 "I3C_GETMXDSR,I3C get capability register" bitfld.long 0x10 24. "TSCO,clock-to-data turnaround time (t less than sub>SCO less than /sub>)" "0: t less than sub>SCO less than /sub> less than or..,1: t less than sub>SCO less than /sub> > 12 ns.." hexmask.long.byte 0x10 16.--23. 1. "RDTURN,programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte)" newline bitfld.long 0x10 8.--9. "FMT,GETMXDS CCC format" "0: format 1 (2 bytes with MaxWr with no defining..,1: format 2: (5 bytes w.ith MaxWr with no defining..,2: format 2 (5 bytes with MaxWr with no defining..,3: format 2 (5 bytes with MaxWr with no defining.." bitfld.long 0x10 0.--1. "HOFFAS,Controller hand-off activity state" "0: activity state 0 is the initial activity state..,1: activity state 1 is the initial activity state..,2: activity state 2 is the initial activity state..,3: activity state 3 is the initial activity state.." line.long 0x14 "I3C_EPIDR,I3C extended provisioned ID register" hexmask.long.word 0x14 17.--31. 1. "MIPIMID,15-bit MIPI manufacturer ID" rbitfld.long 0x14 16. "IDTSEL,provisioned ID type selector" "0,1" newline hexmask.long.byte 0x14 12.--15. 1. "MIPIID,4-bit MIPI Instance ID" tree.end tree.end tree "IAC (Illegal Access Controller)" base ad:0x0 tree "IAC" base ad:0x44025000 group.long 0x0++0x17 line.long 0x0 "IAC_IER0,IAC interrupt enable register 0" bitfld.long 0x0 31. "IAIE31,illegal access interrupt enable for peripheral 31" "0: Illegal access event from peripheral 31 does not..,1: Illegal access event from peripheral 31 can.." bitfld.long 0x0 30. "IAIE30,illegal access interrupt enable for peripheral 30" "0: Illegal access event from peripheral 30 does not..,1: Illegal access event from peripheral 30 can.." newline bitfld.long 0x0 29. "IAIE29,illegal access interrupt enable for peripheral 29" "0: Illegal access event from peripheral 29 does not..,1: Illegal access event from peripheral 29 can.." bitfld.long 0x0 28. "IAIE28,illegal access interrupt enable for peripheral 28" "0: Illegal access event from peripheral 28 does not..,1: Illegal access event from peripheral 28 can.." newline bitfld.long 0x0 27. "IAIE27,illegal access interrupt enable for peripheral 27" "0: Illegal access event from peripheral 27 does not..,1: Illegal access event from peripheral 27 can.." bitfld.long 0x0 26. "IAIE26,illegal access interrupt enable for peripheral 26" "0: Illegal access event from peripheral 26 does not..,1: Illegal access event from peripheral 26 can.." newline bitfld.long 0x0 25. "IAIE25,illegal access interrupt enable for peripheral 25" "0: Illegal access event from peripheral 25 does not..,1: Illegal access event from peripheral 25 can.." bitfld.long 0x0 24. "IAIE24,illegal access interrupt enable for peripheral 24" "0: Illegal access event from peripheral 24 does not..,1: Illegal access event from peripheral 24 can.." newline bitfld.long 0x0 23. "IAIE23,illegal access interrupt enable for peripheral 23" "0: Illegal access event from peripheral 23 does not..,1: Illegal access event from peripheral 23 can.." bitfld.long 0x0 22. "IAIE22,illegal access interrupt enable for peripheral 22" "0: Illegal access event from peripheral 22 does not..,1: Illegal access event from peripheral 22 can.." newline bitfld.long 0x0 21. "IAIE21,illegal access interrupt enable for peripheral 21" "0: Illegal access event from peripheral 21 does not..,1: Illegal access event from peripheral 21 can.." bitfld.long 0x0 20. "IAIE20,illegal access interrupt enable for peripheral 20" "0: Illegal access event from peripheral 20 does not..,1: Illegal access event from peripheral 20 can.." newline bitfld.long 0x0 19. "IAIE19,illegal access interrupt enable for peripheral 19" "0: Illegal access event from peripheral 19 does not..,1: Illegal access event from peripheral 19 can.." bitfld.long 0x0 18. "IAIE18,illegal access interrupt enable for peripheral 18" "0: Illegal access event from peripheral 18 does not..,1: Illegal access event from peripheral 18 can.." newline bitfld.long 0x0 17. "IAIE17,illegal access interrupt enable for peripheral 17" "0: Illegal access event from peripheral 17 does not..,1: Illegal access event from peripheral 17 can.." bitfld.long 0x0 16. "IAIE16,illegal access interrupt enable for peripheral 16" "0: Illegal access event from peripheral 16 does not..,1: Illegal access event from peripheral 16 can.." newline bitfld.long 0x0 15. "IAIE15,illegal access interrupt enable for peripheral 15" "0: Illegal access event from peripheral 15 does not..,1: Illegal access event from peripheral 15 can.." bitfld.long 0x0 14. "IAIE14,illegal access interrupt enable for peripheral 14" "0: Illegal access event from peripheral 14 does not..,1: Illegal access event from peripheral 14 can.." newline bitfld.long 0x0 13. "IAIE13,illegal access interrupt enable for peripheral 13" "0: Illegal access event from peripheral 13 does not..,1: Illegal access event from peripheral 13 can.." bitfld.long 0x0 12. "IAIE12,illegal access interrupt enable for peripheral 12" "0: Illegal access event from peripheral 12 does not..,1: Illegal access event from peripheral 12 can.." newline bitfld.long 0x0 11. "IAIE11,illegal access interrupt enable for peripheral 11" "0: Illegal access event from peripheral 11 does not..,1: Illegal access event from peripheral 11 can.." bitfld.long 0x0 10. "IAIE10,illegal access interrupt enable for peripheral 10" "0: Illegal access event from peripheral 10 does not..,1: Illegal access event from peripheral 10 can.." newline bitfld.long 0x0 9. "IAIE9,illegal access interrupt enable for peripheral 9" "0: Illegal access event from peripheral 9 does not..,1: Illegal access event from peripheral 9 can.." bitfld.long 0x0 8. "IAIE8,illegal access interrupt enable for peripheral 8" "0: Illegal access event from peripheral 8 does not..,1: Illegal access event from peripheral 8 can.." newline bitfld.long 0x0 7. "IAIE7,illegal access interrupt enable for peripheral 7" "0: Illegal access event from peripheral 7 does not..,1: Illegal access event from peripheral 7 can.." bitfld.long 0x0 6. "IAIE6,illegal access interrupt enable for peripheral 6" "0: Illegal access event from peripheral 6 does not..,1: Illegal access event from peripheral 6 can.." newline bitfld.long 0x0 5. "IAIE5,illegal access interrupt enable for peripheral 5" "0: Illegal access event from peripheral 5 does not..,1: Illegal access event from peripheral 5 can.." bitfld.long 0x0 4. "IAIE4,illegal access interrupt enable for peripheral 4" "0: Illegal access event from peripheral 4 does not..,1: Illegal access event from peripheral 4 can.." newline bitfld.long 0x0 3. "IAIE3,illegal access interrupt enable for peripheral 3" "0: Illegal access event from peripheral 3 does not..,1: Illegal access event from peripheral 3 can.." bitfld.long 0x0 2. "IAIE2,illegal access interrupt enable for peripheral 2" "0: Illegal access event from peripheral 2 does not..,1: Illegal access event from peripheral 2 can.." newline bitfld.long 0x0 1. "IAIE1,illegal access interrupt enable for peripheral 1" "0: Illegal access event from peripheral 1 does not..,1: Illegal access event from peripheral 1 can.." bitfld.long 0x0 0. "IAIE0,illegal access interrupt enable for peripheral 0" "0: Illegal access event from peripheral 0 does not..,1: Illegal access event from peripheral 0 can.." line.long 0x4 "IAC_IER1,IAC interrupt enable register 1" bitfld.long 0x4 31. "IAIE63,illegal access interrupt enable for peripheral 63" "0: Illegal access event from peripheral 63 does not..,1: Illegal access event from peripheral 63 can.." bitfld.long 0x4 30. "IAIE62,illegal access interrupt enable for peripheral 62" "0: Illegal access event from peripheral 62 does not..,1: Illegal access event from peripheral 62 can.." newline bitfld.long 0x4 29. "IAIE61,illegal access interrupt enable for peripheral 61" "0: Illegal access event from peripheral 61 does not..,1: Illegal access event from peripheral 61 can.." bitfld.long 0x4 28. "IAIE60,illegal access interrupt enable for peripheral 60" "0: Illegal access event from peripheral 60 does not..,1: Illegal access event from peripheral 60 can.." newline bitfld.long 0x4 27. "IAIE59,illegal access interrupt enable for peripheral 59" "0: Illegal access event from peripheral 59 does not..,1: Illegal access event from peripheral 59 can.." bitfld.long 0x4 26. "IAIE58,illegal access interrupt enable for peripheral 58" "0: Illegal access event from peripheral 58 does not..,1: Illegal access event from peripheral 58 can.." newline bitfld.long 0x4 25. "IAIE57,illegal access interrupt enable for peripheral 57" "0: Illegal access event from peripheral 57 does not..,1: Illegal access event from peripheral 57 can.." bitfld.long 0x4 24. "IAIE56,illegal access interrupt enable for peripheral 56" "0: Illegal access event from peripheral 56 does not..,1: Illegal access event from peripheral 56 can.." newline bitfld.long 0x4 23. "IAIE55,illegal access interrupt enable for peripheral 55" "0: Illegal access event from peripheral 55 does not..,1: Illegal access event from peripheral 55 can.." bitfld.long 0x4 22. "IAIE54,illegal access interrupt enable for peripheral 54" "0: Illegal access event from peripheral 54 does not..,1: Illegal access event from peripheral 54 can.." newline bitfld.long 0x4 21. "IAIE53,illegal access interrupt enable for peripheral 53" "0: Illegal access event from peripheral 53 does not..,1: Illegal access event from peripheral 53 can.." bitfld.long 0x4 20. "IAIE52,illegal access interrupt enable for peripheral 52" "0: Illegal access event from peripheral 52 does not..,1: Illegal access event from peripheral 52 can.." newline bitfld.long 0x4 19. "IAIE51,illegal access interrupt enable for peripheral 51" "0: Illegal access event from peripheral 51 does not..,1: Illegal access event from peripheral 51 can.." bitfld.long 0x4 18. "IAIE50,illegal access interrupt enable for peripheral 50" "0: Illegal access event from peripheral 50 does not..,1: Illegal access event from peripheral 50 can.." newline bitfld.long 0x4 17. "IAIE49,illegal access interrupt enable for peripheral 49" "0: Illegal access event from peripheral 49 does not..,1: Illegal access event from peripheral 49 can.." bitfld.long 0x4 16. "IAIE48,illegal access interrupt enable for peripheral 48" "0: Illegal access event from peripheral 48 does not..,1: Illegal access event from peripheral 48 can.." newline bitfld.long 0x4 15. "IAIE47,illegal access interrupt enable for peripheral 47" "0: Illegal access event from peripheral 47 does not..,1: Illegal access event from peripheral 47 can.." bitfld.long 0x4 14. "IAIE46,illegal access interrupt enable for peripheral 46" "0: Illegal access event from peripheral 46 does not..,1: Illegal access event from peripheral 46 can.." newline bitfld.long 0x4 13. "IAIE45,illegal access interrupt enable for peripheral 45" "0: Illegal access event from peripheral 45 does not..,1: Illegal access event from peripheral 45 can.." bitfld.long 0x4 12. "IAIE44,illegal access interrupt enable for peripheral 44" "0: Illegal access event from peripheral 44 does not..,1: Illegal access event from peripheral 44 can.." newline bitfld.long 0x4 11. "IAIE43,illegal access interrupt enable for peripheral 43" "0: Illegal access event from peripheral 43 does not..,1: Illegal access event from peripheral 43 can.." bitfld.long 0x4 10. "IAIE42,illegal access interrupt enable for peripheral 42" "0: Illegal access event from peripheral 42 does not..,1: Illegal access event from peripheral 42 can.." newline bitfld.long 0x4 9. "IAIE41,illegal access interrupt enable for peripheral 41" "0: Illegal access event from peripheral 41 does not..,1: Illegal access event from peripheral 41 can.." bitfld.long 0x4 8. "IAIE40,illegal access interrupt enable for peripheral 40" "0: Illegal access event from peripheral 40 does not..,1: Illegal access event from peripheral 40 can.." newline bitfld.long 0x4 7. "IAIE39,illegal access interrupt enable for peripheral 39" "0: Illegal access event from peripheral 39 does not..,1: Illegal access event from peripheral 39 can.." bitfld.long 0x4 6. "IAIE38,illegal access interrupt enable for peripheral 38" "0: Illegal access event from peripheral 38 does not..,1: Illegal access event from peripheral 38 can.." newline bitfld.long 0x4 5. "IAIE37,illegal access interrupt enable for peripheral 37" "0: Illegal access event from peripheral 37 does not..,1: Illegal access event from peripheral 37 can.." bitfld.long 0x4 4. "IAIE36,illegal access interrupt enable for peripheral 36" "0: Illegal access event from peripheral 36 does not..,1: Illegal access event from peripheral 36 can.." newline bitfld.long 0x4 3. "IAIE35,illegal access interrupt enable for peripheral 35" "0: Illegal access event from peripheral 35 does not..,1: Illegal access event from peripheral 35 can.." bitfld.long 0x4 2. "IAIE34,illegal access interrupt enable for peripheral 34" "0: Illegal access event from peripheral 34 does not..,1: Illegal access event from peripheral 34 can.." newline bitfld.long 0x4 1. "IAIE33,illegal access interrupt enable for peripheral 33" "0: Illegal access event from peripheral 33 does not..,1: Illegal access event from peripheral 33 can.." bitfld.long 0x4 0. "IAIE32,illegal access interrupt enable for peripheral 32" "0: Illegal access event from peripheral 32 does not..,1: Illegal access event from peripheral 32 can.." line.long 0x8 "IAC_IER2,IAC interrupt enable register 2" bitfld.long 0x8 31. "IAIE95,illegal access interrupt enable for peripheral 95" "0: Illegal access event from peripheral 95 does not..,1: Illegal access event from peripheral 95 can.." bitfld.long 0x8 30. "IAIE94,illegal access interrupt enable for peripheral 94" "0: Illegal access event from peripheral 94 does not..,1: Illegal access event from peripheral 94 can.." newline bitfld.long 0x8 29. "IAIE93,illegal access interrupt enable for peripheral 93" "0: Illegal access event from peripheral 93 does not..,1: Illegal access event from peripheral 93 can.." bitfld.long 0x8 28. "IAIE92,illegal access interrupt enable for peripheral 92" "0: Illegal access event from peripheral 92 does not..,1: Illegal access event from peripheral 92 can.." newline bitfld.long 0x8 27. "IAIE91,illegal access interrupt enable for peripheral 91" "0: Illegal access event from peripheral 91 does not..,1: Illegal access event from peripheral 91 can.." bitfld.long 0x8 26. "IAIE90,illegal access interrupt enable for peripheral 90" "0: Illegal access event from peripheral 90 does not..,1: Illegal access event from peripheral 90 can.." newline bitfld.long 0x8 25. "IAIE89,illegal access interrupt enable for peripheral 89" "0: Illegal access event from peripheral 89 does not..,1: Illegal access event from peripheral 89 can.." bitfld.long 0x8 24. "IAIE88,illegal access interrupt enable for peripheral 88" "0: Illegal access event from peripheral 88 does not..,1: Illegal access event from peripheral 88 can.." newline bitfld.long 0x8 23. "IAIE87,illegal access interrupt enable for peripheral 87" "0: Illegal access event from peripheral 87 does not..,1: Illegal access event from peripheral 87 can.." bitfld.long 0x8 22. "IAIE86,illegal access interrupt enable for peripheral 86" "0: Illegal access event from peripheral 86 does not..,1: Illegal access event from peripheral 86 can.." newline bitfld.long 0x8 21. "IAIE85,illegal access interrupt enable for peripheral 85" "0: Illegal access event from peripheral 85 does not..,1: Illegal access event from peripheral 85 can.." bitfld.long 0x8 20. "IAIE84,illegal access interrupt enable for peripheral 84" "0: Illegal access event from peripheral 84 does not..,1: Illegal access event from peripheral 84 can.." newline bitfld.long 0x8 19. "IAIE83,illegal access interrupt enable for peripheral 83" "0: Illegal access event from peripheral 83 does not..,1: Illegal access event from peripheral 83 can.." bitfld.long 0x8 18. "IAIE82,illegal access interrupt enable for peripheral 82" "0: Illegal access event from peripheral 82 does not..,1: Illegal access event from peripheral 82 can.." newline bitfld.long 0x8 17. "IAIE81,illegal access interrupt enable for peripheral 81" "0: Illegal access event from peripheral 81 does not..,1: Illegal access event from peripheral 81 can.." bitfld.long 0x8 16. "IAIE80,illegal access interrupt enable for peripheral 80" "0: Illegal access event from peripheral 80 does not..,1: Illegal access event from peripheral 80 can.." newline bitfld.long 0x8 15. "IAIE79,illegal access interrupt enable for peripheral 79" "0: Illegal access event from peripheral 79 does not..,1: Illegal access event from peripheral 79 can.." bitfld.long 0x8 14. "IAIE78,illegal access interrupt enable for peripheral 78" "0: Illegal access event from peripheral 78 does not..,1: Illegal access event from peripheral 78 can.." newline bitfld.long 0x8 13. "IAIE77,illegal access interrupt enable for peripheral 77" "0: Illegal access event from peripheral 77 does not..,1: Illegal access event from peripheral 77 can.." bitfld.long 0x8 12. "IAIE76,illegal access interrupt enable for peripheral 76" "0: Illegal access event from peripheral 76 does not..,1: Illegal access event from peripheral 76 can.." newline bitfld.long 0x8 11. "IAIE75,illegal access interrupt enable for peripheral 75" "0: Illegal access event from peripheral 75 does not..,1: Illegal access event from peripheral 75 can.." bitfld.long 0x8 10. "IAIE74,illegal access interrupt enable for peripheral 74" "0: Illegal access event from peripheral 74 does not..,1: Illegal access event from peripheral 74 can.." newline bitfld.long 0x8 9. "IAIE73,illegal access interrupt enable for peripheral 73" "0: Illegal access event from peripheral 73 does not..,1: Illegal access event from peripheral 73 can.." bitfld.long 0x8 8. "IAIE72,illegal access interrupt enable for peripheral 72" "0: Illegal access event from peripheral 72 does not..,1: Illegal access event from peripheral 72 can.." newline bitfld.long 0x8 7. "IAIE71,illegal access interrupt enable for peripheral 71" "0: Illegal access event from peripheral 71 does not..,1: Illegal access event from peripheral 71 can.." bitfld.long 0x8 6. "IAIE70,illegal access interrupt enable for peripheral 70" "0: Illegal access event from peripheral 70 does not..,1: Illegal access event from peripheral 70 can.." newline bitfld.long 0x8 5. "IAIE69,illegal access interrupt enable for peripheral 69" "0: Illegal access event from peripheral 69 does not..,1: Illegal access event from peripheral 69 can.." bitfld.long 0x8 4. "IAIE68,illegal access interrupt enable for peripheral 68" "0: Illegal access event from peripheral 68 does not..,1: Illegal access event from peripheral 68 can.." newline bitfld.long 0x8 3. "IAIE67,illegal access interrupt enable for peripheral 67" "0: Illegal access event from peripheral 67 does not..,1: Illegal access event from peripheral 67 can.." bitfld.long 0x8 2. "IAIE66,illegal access interrupt enable for peripheral 66" "0: Illegal access event from peripheral 66 does not..,1: Illegal access event from peripheral 66 can.." newline bitfld.long 0x8 1. "IAIE65,illegal access interrupt enable for peripheral 65" "0: Illegal access event from peripheral 65 does not..,1: Illegal access event from peripheral 65 can.." bitfld.long 0x8 0. "IAIE64,illegal access interrupt enable for peripheral 64" "0: Illegal access event from peripheral 64 does not..,1: Illegal access event from peripheral 64 can.." line.long 0xC "IAC_IER3,IAC interrupt enable register 3" bitfld.long 0xC 31. "IAIE127,illegal access interrupt enable for peripheral 127" "0: Illegal access event from peripheral 127 does..,1: Illegal access event from peripheral 127 can.." bitfld.long 0xC 30. "IAIE126,illegal access interrupt enable for peripheral 126" "0: Illegal access event from peripheral 126 does..,1: Illegal access event from peripheral 126 can.." newline bitfld.long 0xC 29. "IAIE125,illegal access interrupt enable for peripheral 125" "0: Illegal access event from peripheral 125 does..,1: Illegal access event from peripheral 125 can.." bitfld.long 0xC 28. "IAIE124,illegal access interrupt enable for peripheral 124" "0: Illegal access event from peripheral 124 does..,1: Illegal access event from peripheral 124 can.." newline bitfld.long 0xC 27. "IAIE123,illegal access interrupt enable for peripheral 123" "0: Illegal access event from peripheral 123 does..,1: Illegal access event from peripheral 123 can.." bitfld.long 0xC 26. "IAIE122,illegal access interrupt enable for peripheral 122" "0: Illegal access event from peripheral 122 does..,1: Illegal access event from peripheral 122 can.." newline bitfld.long 0xC 25. "IAIE121,illegal access interrupt enable for peripheral 121" "0: Illegal access event from peripheral 121 does..,1: Illegal access event from peripheral 121 can.." bitfld.long 0xC 24. "IAIE120,illegal access interrupt enable for peripheral 120" "0: Illegal access event from peripheral 120 does..,1: Illegal access event from peripheral 120 can.." newline bitfld.long 0xC 23. "IAIE119,illegal access interrupt enable for peripheral 119" "0: Illegal access event from peripheral 119 does..,1: Illegal access event from peripheral 119 can.." bitfld.long 0xC 22. "IAIE118,illegal access interrupt enable for peripheral 118" "0: Illegal access event from peripheral 118 does..,1: Illegal access event from peripheral 118 can.." newline bitfld.long 0xC 21. "IAIE117,illegal access interrupt enable for peripheral 117" "0: Illegal access event from peripheral 117 does..,1: Illegal access event from peripheral 117 can.." bitfld.long 0xC 20. "IAIE116,illegal access interrupt enable for peripheral 116" "0: Illegal access event from peripheral 116 does..,1: Illegal access event from peripheral 116 can.." newline bitfld.long 0xC 19. "IAIE115,illegal access interrupt enable for peripheral 115" "0: Illegal access event from peripheral 115 does..,1: Illegal access event from peripheral 115 can.." bitfld.long 0xC 18. "IAIE114,illegal access interrupt enable for peripheral 114" "0: Illegal access event from peripheral 114 does..,1: Illegal access event from peripheral 114 can.." newline bitfld.long 0xC 17. "IAIE113,illegal access interrupt enable for peripheral 113" "0: Illegal access event from peripheral 113 does..,1: Illegal access event from peripheral 113 can.." bitfld.long 0xC 16. "IAIE112,illegal access interrupt enable for peripheral 112" "0: Illegal access event from peripheral 112 does..,1: Illegal access event from peripheral 112 can.." newline bitfld.long 0xC 15. "IAIE111,illegal access interrupt enable for peripheral 111" "0: Illegal access event from peripheral 111 does..,1: Illegal access event from peripheral 111 can.." bitfld.long 0xC 14. "IAIE110,illegal access interrupt enable for peripheral 110" "0: Illegal access event from peripheral 110 does..,1: Illegal access event from peripheral 110 can.." newline bitfld.long 0xC 13. "IAIE109,illegal access interrupt enable for peripheral 109" "0: Illegal access event from peripheral 109 does..,1: Illegal access event from peripheral 109 can.." bitfld.long 0xC 12. "IAIE108,illegal access interrupt enable for peripheral 108" "0: Illegal access event from peripheral 108 does..,1: Illegal access event from peripheral 108 can.." newline bitfld.long 0xC 11. "IAIE107,illegal access interrupt enable for peripheral 107" "0: Illegal access event from peripheral 107 does..,1: Illegal access event from peripheral 107 can.." bitfld.long 0xC 10. "IAIE106,illegal access interrupt enable for peripheral 106" "0: Illegal access event from peripheral 106 does..,1: Illegal access event from peripheral 106 can.." newline bitfld.long 0xC 9. "IAIE105,illegal access interrupt enable for peripheral 105" "0: Illegal access event from peripheral 105 does..,1: Illegal access event from peripheral 105 can.." bitfld.long 0xC 8. "IAIE104,illegal access interrupt enable for peripheral 104" "0: Illegal access event from peripheral 104 does..,1: Illegal access event from peripheral 104 can.." newline bitfld.long 0xC 7. "IAIE103,illegal access interrupt enable for peripheral 103" "0: Illegal access event from peripheral 103 does..,1: Illegal access event from peripheral 103 can.." bitfld.long 0xC 6. "IAIE102,illegal access interrupt enable for peripheral 102" "0: Illegal access event from peripheral 102 does..,1: Illegal access event from peripheral 102 can.." newline bitfld.long 0xC 5. "IAIE101,illegal access interrupt enable for peripheral 101" "0: Illegal access event from peripheral 101 does..,1: Illegal access event from peripheral 101 can.." bitfld.long 0xC 4. "IAIE100,illegal access interrupt enable for peripheral 100" "0: Illegal access event from peripheral 100 does..,1: Illegal access event from peripheral 100 can.." newline bitfld.long 0xC 3. "IAIE99,illegal access interrupt enable for peripheral 99" "0: Illegal access event from peripheral 99 does not..,1: Illegal access event from peripheral 99 can.." bitfld.long 0xC 2. "IAIE98,illegal access interrupt enable for peripheral 98" "0: Illegal access event from peripheral 98 does not..,1: Illegal access event from peripheral 98 can.." newline bitfld.long 0xC 1. "IAIE97,illegal access interrupt enable for peripheral 97" "0: Illegal access event from peripheral 97 does not..,1: Illegal access event from peripheral 97 can.." bitfld.long 0xC 0. "IAIE96,illegal access interrupt enable for peripheral 96" "0: Illegal access event from peripheral 96 does not..,1: Illegal access event from peripheral 96 can.." line.long 0x10 "IAC_IER4,IAC interrupt enable register 4" bitfld.long 0x10 31. "IAIE159,illegal access interrupt enable for peripheral 159" "0: Illegal access event from peripheral 159 does..,1: Illegal access event from peripheral 159 can.." bitfld.long 0x10 30. "IAIE158,illegal access interrupt enable for peripheral 158" "0: Illegal access event from peripheral 158 does..,1: Illegal access event from peripheral 158 can.." newline bitfld.long 0x10 29. "IAIE157,illegal access interrupt enable for peripheral 157" "0: Illegal access event from peripheral 157 does..,1: Illegal access event from peripheral 157 can.." bitfld.long 0x10 28. "IAIE156,illegal access interrupt enable for peripheral 156" "0: Illegal access event from peripheral 156 does..,1: Illegal access event from peripheral 156 can.." newline bitfld.long 0x10 27. "IAIE155,illegal access interrupt enable for peripheral 155" "0: Illegal access event from peripheral 155 does..,1: Illegal access event from peripheral 155 can.." bitfld.long 0x10 26. "IAIE154,illegal access interrupt enable for peripheral 154" "0: Illegal access event from peripheral 154 does..,1: Illegal access event from peripheral 154 can.." newline bitfld.long 0x10 25. "IAIE153,illegal access interrupt enable for peripheral 153" "0: Illegal access event from peripheral 153 does..,1: Illegal access event from peripheral 153 can.." bitfld.long 0x10 24. "IAIE152,illegal access interrupt enable for peripheral 152" "0: Illegal access event from peripheral 152 does..,1: Illegal access event from peripheral 152 can.." newline bitfld.long 0x10 23. "IAIE151,illegal access interrupt enable for peripheral 151" "0: Illegal access event from peripheral 151 does..,1: Illegal access event from peripheral 151 can.." bitfld.long 0x10 22. "IAIE150,illegal access interrupt enable for peripheral 150" "0: Illegal access event from peripheral 150 does..,1: Illegal access event from peripheral 150 can.." newline bitfld.long 0x10 21. "IAIE149,illegal access interrupt enable for peripheral 149" "0: Illegal access event from peripheral 149 does..,1: Illegal access event from peripheral 149 can.." bitfld.long 0x10 20. "IAIE148,illegal access interrupt enable for peripheral 148" "0: Illegal access event from peripheral 148 does..,1: Illegal access event from peripheral 148 can.." newline bitfld.long 0x10 19. "IAIE147,illegal access interrupt enable for peripheral 147" "0: Illegal access event from peripheral 147 does..,1: Illegal access event from peripheral 147 can.." bitfld.long 0x10 18. "IAIE146,illegal access interrupt enable for peripheral 146" "0: Illegal access event from peripheral 146 does..,1: Illegal access event from peripheral 146 can.." newline bitfld.long 0x10 17. "IAIE145,illegal access interrupt enable for peripheral 145" "0: Illegal access event from peripheral 145 does..,1: Illegal access event from peripheral 145 can.." bitfld.long 0x10 16. "IAIE144,illegal access interrupt enable for peripheral 144" "0: Illegal access event from peripheral 144 does..,1: Illegal access event from peripheral 144 can.." newline bitfld.long 0x10 15. "IAIE143,illegal access interrupt enable for peripheral 143" "0: Illegal access event from peripheral 143 does..,1: Illegal access event from peripheral 143 can.." bitfld.long 0x10 14. "IAIE142,illegal access interrupt enable for peripheral 142" "0: Illegal access event from peripheral 142 does..,1: Illegal access event from peripheral 142 can.." newline bitfld.long 0x10 13. "IAIE141,illegal access interrupt enable for peripheral 141" "0: Illegal access event from peripheral 141 does..,1: Illegal access event from peripheral 141 can.." bitfld.long 0x10 12. "IAIE140,illegal access interrupt enable for peripheral 140" "0: Illegal access event from peripheral 140 does..,1: Illegal access event from peripheral 140 can.." newline bitfld.long 0x10 11. "IAIE139,illegal access interrupt enable for peripheral 139" "0: Illegal access event from peripheral 139 does..,1: Illegal access event from peripheral 139 can.." bitfld.long 0x10 10. "IAIE138,illegal access interrupt enable for peripheral 138" "0: Illegal access event from peripheral 138 does..,1: Illegal access event from peripheral 138 can.." newline bitfld.long 0x10 9. "IAIE137,illegal access interrupt enable for peripheral 137" "0: Illegal access event from peripheral 137 does..,1: Illegal access event from peripheral 137 can.." bitfld.long 0x10 8. "IAIE136,illegal access interrupt enable for peripheral 136" "0: Illegal access event from peripheral 136 does..,1: Illegal access event from peripheral 136 can.." newline bitfld.long 0x10 7. "IAIE135,illegal access interrupt enable for peripheral 135" "0: Illegal access event from peripheral 135 does..,1: Illegal access event from peripheral 135 can.." bitfld.long 0x10 6. "IAIE134,illegal access interrupt enable for peripheral 134" "0: Illegal access event from peripheral 134 does..,1: Illegal access event from peripheral 134 can.." newline bitfld.long 0x10 5. "IAIE133,illegal access interrupt enable for peripheral 133" "0: Illegal access event from peripheral 133 does..,1: Illegal access event from peripheral 133 can.." bitfld.long 0x10 4. "IAIE132,illegal access interrupt enable for peripheral 132" "0: Illegal access event from peripheral 132 does..,1: Illegal access event from peripheral 132 can.." newline bitfld.long 0x10 3. "IAIE131,illegal access interrupt enable for peripheral 131" "0: Illegal access event from peripheral 131 does..,1: Illegal access event from peripheral 131 can.." bitfld.long 0x10 2. "IAIE130,illegal access interrupt enable for peripheral 130" "0: Illegal access event from peripheral 130 does..,1: Illegal access event from peripheral 130 can.." newline bitfld.long 0x10 1. "IAIE129,illegal access interrupt enable for peripheral 129" "0: Illegal access event from peripheral 129 does..,1: Illegal access event from peripheral 129 can.." bitfld.long 0x10 0. "IAIE128,illegal access interrupt enable for peripheral 128" "0: Illegal access event from peripheral 128 does..,1: Illegal access event from peripheral 128 can.." line.long 0x14 "IAC_IER5,IAC interrupt enable register 5" bitfld.long 0x14 31. "IAIE191,illegal access interrupt enable for peripheral 191" "0: Illegal access event from peripheral 191 does..,1: Illegal access event from peripheral 191 can.." bitfld.long 0x14 30. "IAIE190,illegal access interrupt enable for peripheral 190" "0: Illegal access event from peripheral 190 does..,1: Illegal access event from peripheral 190 can.." newline bitfld.long 0x14 29. "IAIE189,illegal access interrupt enable for peripheral 189" "0: Illegal access event from peripheral 189 does..,1: Illegal access event from peripheral 189 can.." bitfld.long 0x14 28. "IAIE188,illegal access interrupt enable for peripheral 188" "0: Illegal access event from peripheral 188 does..,1: Illegal access event from peripheral 188 can.." newline bitfld.long 0x14 27. "IAIE187,illegal access interrupt enable for peripheral 187" "0: Illegal access event from peripheral 187 does..,1: Illegal access event from peripheral 187 can.." bitfld.long 0x14 26. "IAIE186,illegal access interrupt enable for peripheral 186" "0: Illegal access event from peripheral 186 does..,1: Illegal access event from peripheral 186 can.." newline bitfld.long 0x14 25. "IAIE185,illegal access interrupt enable for peripheral 185" "0: Illegal access event from peripheral 185 does..,1: Illegal access event from peripheral 185 can.." bitfld.long 0x14 24. "IAIE184,illegal access interrupt enable for peripheral 184" "0: Illegal access event from peripheral 184 does..,1: Illegal access event from peripheral 184 can.." newline bitfld.long 0x14 23. "IAIE183,illegal access interrupt enable for peripheral 183" "0: Illegal access event from peripheral 183 does..,1: Illegal access event from peripheral 183 can.." bitfld.long 0x14 22. "IAIE182,illegal access interrupt enable for peripheral 182" "0: Illegal access event from peripheral 182 does..,1: Illegal access event from peripheral 182 can.." newline bitfld.long 0x14 21. "IAIE181,illegal access interrupt enable for peripheral 181" "0: Illegal access event from peripheral 181 does..,1: Illegal access event from peripheral 181 can.." bitfld.long 0x14 20. "IAIE180,illegal access interrupt enable for peripheral 180" "0: Illegal access event from peripheral 180 does..,1: Illegal access event from peripheral 180 can.." newline bitfld.long 0x14 19. "IAIE179,illegal access interrupt enable for peripheral 179" "0: Illegal access event from peripheral 179 does..,1: Illegal access event from peripheral 179 can.." bitfld.long 0x14 18. "IAIE178,illegal access interrupt enable for peripheral 178" "0: Illegal access event from peripheral 178 does..,1: Illegal access event from peripheral 178 can.." newline bitfld.long 0x14 17. "IAIE177,illegal access interrupt enable for peripheral 177" "0: Illegal access event from peripheral 177 does..,1: Illegal access event from peripheral 177 can.." bitfld.long 0x14 16. "IAIE176,illegal access interrupt enable for peripheral 176" "0: Illegal access event from peripheral 176 does..,1: Illegal access event from peripheral 176 can.." newline bitfld.long 0x14 15. "IAIE175,illegal access interrupt enable for peripheral 175" "0: Illegal access event from peripheral 175 does..,1: Illegal access event from peripheral 175 can.." bitfld.long 0x14 14. "IAIE174,illegal access interrupt enable for peripheral 174" "0: Illegal access event from peripheral 174 does..,1: Illegal access event from peripheral 174 can.." newline bitfld.long 0x14 13. "IAIE173,illegal access interrupt enable for peripheral 173" "0: Illegal access event from peripheral 173 does..,1: Illegal access event from peripheral 173 can.." bitfld.long 0x14 12. "IAIE172,illegal access interrupt enable for peripheral 172" "0: Illegal access event from peripheral 172 does..,1: Illegal access event from peripheral 172 can.." newline bitfld.long 0x14 11. "IAIE171,illegal access interrupt enable for peripheral 171" "0: Illegal access event from peripheral 171 does..,1: Illegal access event from peripheral 171 can.." bitfld.long 0x14 10. "IAIE170,illegal access interrupt enable for peripheral 170" "0: Illegal access event from peripheral 170 does..,1: Illegal access event from peripheral 170 can.." newline bitfld.long 0x14 9. "IAIE169,illegal access interrupt enable for peripheral 169" "0: Illegal access event from peripheral 169 does..,1: Illegal access event from peripheral 169 can.." bitfld.long 0x14 8. "IAIE168,illegal access interrupt enable for peripheral 168" "0: Illegal access event from peripheral 168 does..,1: Illegal access event from peripheral 168 can.." newline bitfld.long 0x14 7. "IAIE167,illegal access interrupt enable for peripheral 167" "0: Illegal access event from peripheral 167 does..,1: Illegal access event from peripheral 167 can.." bitfld.long 0x14 6. "IAIE166,illegal access interrupt enable for peripheral 166" "0: Illegal access event from peripheral 166 does..,1: Illegal access event from peripheral 166 can.." newline bitfld.long 0x14 5. "IAIE165,illegal access interrupt enable for peripheral 165" "0: Illegal access event from peripheral 165 does..,1: Illegal access event from peripheral 165 can.." bitfld.long 0x14 4. "IAIE164,illegal access interrupt enable for peripheral 164" "0: Illegal access event from peripheral 164 does..,1: Illegal access event from peripheral 164 can.." newline bitfld.long 0x14 3. "IAIE163,illegal access interrupt enable for peripheral 163" "0: Illegal access event from peripheral 163 does..,1: Illegal access event from peripheral 163 can.." bitfld.long 0x14 2. "IAIE162,illegal access interrupt enable for peripheral 162" "0: Illegal access event from peripheral 162 does..,1: Illegal access event from peripheral 162 can.." newline bitfld.long 0x14 1. "IAIE161,illegal access interrupt enable for peripheral 161" "0: Illegal access event from peripheral 161 does..,1: Illegal access event from peripheral 161 can.." bitfld.long 0x14 0. "IAIE160,illegal access interrupt enable for peripheral 160" "0: Illegal access event from peripheral 160 does..,1: Illegal access event from peripheral 160 can.." rgroup.long 0x80++0x17 line.long 0x0 "IAC_ISR0,IAC interrupt status register 0" bitfld.long 0x0 31. "IAF31,illegal access interrupt enable for peripheral 31" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 30. "IAF30,illegal access interrupt enable for peripheral 30" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 29. "IAF29,illegal access interrupt enable for peripheral 29" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 28. "IAF28,illegal access interrupt enable for peripheral 28" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 27. "IAF27,illegal access interrupt enable for peripheral 27" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 26. "IAF26,illegal access interrupt enable for peripheral 26" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 25. "IAF25,illegal access interrupt enable for peripheral 25" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 24. "IAF24,illegal access interrupt enable for peripheral 24" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 23. "IAF23,illegal access interrupt enable for peripheral 23" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 22. "IAF22,illegal access interrupt enable for peripheral 22" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 21. "IAF21,illegal access interrupt enable for peripheral 21" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 20. "IAF20,illegal access interrupt enable for peripheral 20" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 19. "IAF19,illegal access interrupt enable for peripheral 19" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 18. "IAF18,illegal access interrupt enable for peripheral 18" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 17. "IAF17,illegal access interrupt enable for peripheral 17" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 16. "IAF16,illegal access interrupt enable for peripheral 16" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 15. "IAF15,illegal access interrupt enable for peripheral 15" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 14. "IAF14,illegal access interrupt enable for peripheral 14" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 13. "IAF13,illegal access interrupt enable for peripheral 13" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 12. "IAF12,illegal access interrupt enable for peripheral 12" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 11. "IAF11,illegal access interrupt enable for peripheral 11" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 10. "IAF10,illegal access interrupt enable for peripheral 10" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 9. "IAF9,illegal access interrupt enable for peripheral 9" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 8. "IAF8,illegal access interrupt enable for peripheral 8" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 7. "IAF7,illegal access interrupt enable for peripheral 7" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 6. "IAF6,illegal access interrupt enable for peripheral 6" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 5. "IAF5,illegal access interrupt enable for peripheral 5" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 4. "IAF4,illegal access interrupt enable for peripheral 4" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 3. "IAF3,illegal access interrupt enable for peripheral 3" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 2. "IAF2,illegal access interrupt enable for peripheral 2" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 1. "IAF1,illegal access interrupt enable for peripheral 1" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 0. "IAF0,illegal access interrupt enable for peripheral 0" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." line.long 0x4 "IAC_ISR1,IAC interrupt status register 1" bitfld.long 0x4 31. "IAF63,illegal access interrupt enable for peripheral 63" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 30. "IAF62,illegal access interrupt enable for peripheral 62" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 29. "IAF61,illegal access interrupt enable for peripheral 61" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 28. "IAF60,illegal access interrupt enable for peripheral 60" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 27. "IAF59,illegal access interrupt enable for peripheral 59" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 26. "IAF58,illegal access interrupt enable for peripheral 58" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 25. "IAF57,illegal access interrupt enable for peripheral 57" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 24. "IAF56,illegal access interrupt enable for peripheral 56" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 23. "IAF55,illegal access interrupt enable for peripheral 55" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 22. "IAF54,illegal access interrupt enable for peripheral 54" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 21. "IAF53,illegal access interrupt enable for peripheral 53" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 20. "IAF52,illegal access interrupt enable for peripheral 52" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 19. "IAF51,illegal access interrupt enable for peripheral 51" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 18. "IAF50,illegal access interrupt enable for peripheral 50" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 17. "IAF49,illegal access interrupt enable for peripheral 49" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 16. "IAF48,illegal access interrupt enable for peripheral 48" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 15. "IAF47,illegal access interrupt enable for peripheral 47" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 14. "IAF46,illegal access interrupt enable for peripheral 46" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 13. "IAF45,illegal access interrupt enable for peripheral 45" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 12. "IAF44,illegal access interrupt enable for peripheral 44" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 11. "IAF43,illegal access interrupt enable for peripheral 43" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 10. "IAF42,illegal access interrupt enable for peripheral 42" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 9. "IAF41,illegal access interrupt enable for peripheral 41" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 8. "IAF40,illegal access interrupt enable for peripheral 40" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 7. "IAF39,illegal access interrupt enable for peripheral 39" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 6. "IAF38,illegal access interrupt enable for peripheral 38" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 5. "IAF37,illegal access interrupt enable for peripheral 37" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 4. "IAF36,illegal access interrupt enable for peripheral 36" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 3. "IAF35,illegal access interrupt enable for peripheral 35" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 2. "IAF34,illegal access interrupt enable for peripheral 34" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 1. "IAF33,illegal access interrupt enable for peripheral 33" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 0. "IAF32,illegal access interrupt enable for peripheral 32" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." line.long 0x8 "IAC_ISR2,IAC interrupt status register 2" bitfld.long 0x8 31. "IAF95,illegal access interrupt enable for peripheral 95" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 30. "IAF94,illegal access interrupt enable for peripheral 94" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 29. "IAF93,illegal access interrupt enable for peripheral 93" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 28. "IAF92,illegal access interrupt enable for peripheral 92" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 27. "IAF91,illegal access interrupt enable for peripheral 91" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 26. "IAF90,illegal access interrupt enable for peripheral 90" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 25. "IAF89,illegal access interrupt enable for peripheral 89" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 24. "IAF88,illegal access interrupt enable for peripheral 88" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 23. "IAF87,illegal access interrupt enable for peripheral 87" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 22. "IAF86,illegal access interrupt enable for peripheral 86" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 21. "IAF85,illegal access interrupt enable for peripheral 85" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 20. "IAF84,illegal access interrupt enable for peripheral 84" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 19. "IAF83,illegal access interrupt enable for peripheral 83" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 18. "IAF82,illegal access interrupt enable for peripheral 82" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 17. "IAF81,illegal access interrupt enable for peripheral 81" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 16. "IAF80,illegal access interrupt enable for peripheral 80" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 15. "IAF79,illegal access interrupt enable for peripheral 79" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 14. "IAF78,illegal access interrupt enable for peripheral 78" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 13. "IAF77,illegal access interrupt enable for peripheral 77" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 12. "IAF76,illegal access interrupt enable for peripheral 76" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 11. "IAF75,illegal access interrupt enable for peripheral 75" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 10. "IAF74,illegal access interrupt enable for peripheral 74" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 9. "IAF73,illegal access interrupt enable for peripheral 73" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 8. "IAF72,illegal access interrupt enable for peripheral 72" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 7. "IAF71,illegal access interrupt enable for peripheral 71" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 6. "IAF70,illegal access interrupt enable for peripheral 70" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 5. "IAF69,illegal access interrupt enable for peripheral 69" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 4. "IAF68,illegal access interrupt enable for peripheral 68" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 3. "IAF67,illegal access interrupt enable for peripheral 67" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 2. "IAF66,illegal access interrupt enable for peripheral 66" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 1. "IAF65,illegal access interrupt enable for peripheral 65" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 0. "IAF64,illegal access interrupt enable for peripheral 64" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." line.long 0xC "IAC_ISR3,IAC interrupt status register 3" bitfld.long 0xC 31. "IAF127,illegal access interrupt enable for peripheral 127" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 30. "IAF126,illegal access interrupt enable for peripheral 126" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 29. "IAF125,illegal access interrupt enable for peripheral 125" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 28. "IAF124,illegal access interrupt enable for peripheral 124" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 27. "IAF123,illegal access interrupt enable for peripheral 123" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 26. "IAF122,illegal access interrupt enable for peripheral 122" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 25. "IAF121,illegal access interrupt enable for peripheral 121" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 24. "IAF120,illegal access interrupt enable for peripheral 120" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 23. "IAF119,illegal access interrupt enable for peripheral 119" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 22. "IAF118,illegal access interrupt enable for peripheral 118" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 21. "IAF117,illegal access interrupt enable for peripheral 117" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 20. "IAF116,illegal access interrupt enable for peripheral 116" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 19. "IAF115,illegal access interrupt enable for peripheral 115" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 18. "IAF114,illegal access interrupt enable for peripheral 114" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 17. "IAF113,illegal access interrupt enable for peripheral 113" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 16. "IAF112,illegal access interrupt enable for peripheral 112" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 15. "IAF111,illegal access interrupt enable for peripheral 111" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 14. "IAF110,illegal access interrupt enable for peripheral 110" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 13. "IAF109,illegal access interrupt enable for peripheral 109" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 12. "IAF108,illegal access interrupt enable for peripheral 108" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 11. "IAF107,illegal access interrupt enable for peripheral 107" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 10. "IAF106,illegal access interrupt enable for peripheral 106" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 9. "IAF105,illegal access interrupt enable for peripheral 105" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 8. "IAF104,illegal access interrupt enable for peripheral 104" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 7. "IAF103,illegal access interrupt enable for peripheral 103" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 6. "IAF102,illegal access interrupt enable for peripheral 102" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 5. "IAF101,illegal access interrupt enable for peripheral 101" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 4. "IAF100,illegal access interrupt enable for peripheral 100" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 3. "IAF99,illegal access interrupt enable for peripheral 99" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 2. "IAF98,illegal access interrupt enable for peripheral 98" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 1. "IAF97,illegal access interrupt enable for peripheral 97" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 0. "IAF96,illegal access interrupt enable for peripheral 96" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." line.long 0x10 "IAC_ISR4,IAC interrupt status register 4" bitfld.long 0x10 31. "IAF159,illegal access interrupt enable for peripheral 159" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 30. "IAF158,illegal access interrupt enable for peripheral 158" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 29. "IAF157,illegal access interrupt enable for peripheral 157" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 28. "IAF156,illegal access interrupt enable for peripheral 156" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 27. "IAF155,illegal access interrupt enable for peripheral 155" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 26. "IAF154,illegal access interrupt enable for peripheral 154" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 25. "IAF153,illegal access interrupt enable for peripheral 153" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 24. "IAF152,illegal access interrupt enable for peripheral 152" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 23. "IAF151,illegal access interrupt enable for peripheral 151" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 22. "IAF150,illegal access interrupt enable for peripheral 150" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 21. "IAF149,illegal access interrupt enable for peripheral 149" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 20. "IAF148,illegal access interrupt enable for peripheral 148" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 19. "IAF147,illegal access interrupt enable for peripheral 147" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 18. "IAF146,illegal access interrupt enable for peripheral 146" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 17. "IAF145,illegal access interrupt enable for peripheral 145" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 16. "IAF144,illegal access interrupt enable for peripheral 144" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 15. "IAF143,illegal access interrupt enable for peripheral 143" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 14. "IAF142,illegal access interrupt enable for peripheral 142" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 13. "IAF141,illegal access interrupt enable for peripheral 141" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 12. "IAF140,illegal access interrupt enable for peripheral 140" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 11. "IAF139,illegal access interrupt enable for peripheral 139" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 10. "IAF138,illegal access interrupt enable for peripheral 138" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 9. "IAF137,illegal access interrupt enable for peripheral 137" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 8. "IAF136,illegal access interrupt enable for peripheral 136" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 7. "IAF135,illegal access interrupt enable for peripheral 135" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 6. "IAF134,illegal access interrupt enable for peripheral 134" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 5. "IAF133,illegal access interrupt enable for peripheral 133" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 4. "IAF132,illegal access interrupt enable for peripheral 132" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 3. "IAF131,illegal access interrupt enable for peripheral 131" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 2. "IAF130,illegal access interrupt enable for peripheral 130" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 1. "IAF129,illegal access interrupt enable for peripheral 129" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 0. "IAF128,illegal access interrupt enable for peripheral 128" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." line.long 0x14 "IAC_ISR5,IAC interrupt status register 5" bitfld.long 0x14 31. "IAF191,illegal access interrupt enable for peripheral 191" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 30. "IAF190,illegal access interrupt enable for peripheral 190" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 29. "IAF189,illegal access interrupt enable for peripheral 189" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 28. "IAF188,illegal access interrupt enable for peripheral 188" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 27. "IAF187,illegal access interrupt enable for peripheral 187" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 26. "IAF186,illegal access interrupt enable for peripheral 186" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 25. "IAF185,illegal access interrupt enable for peripheral 185" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 24. "IAF184,illegal access interrupt enable for peripheral 184" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 23. "IAF183,illegal access interrupt enable for peripheral 183" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 22. "IAF182,illegal access interrupt enable for peripheral 182" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 21. "IAF181,illegal access interrupt enable for peripheral 181" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 20. "IAF180,illegal access interrupt enable for peripheral 180" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 19. "IAF179,illegal access interrupt enable for peripheral 179" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 18. "IAF178,illegal access interrupt enable for peripheral 178" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 17. "IAF177,illegal access interrupt enable for peripheral 177" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 16. "IAF176,illegal access interrupt enable for peripheral 176" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 15. "IAF175,illegal access interrupt enable for peripheral 175" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 14. "IAF174,illegal access interrupt enable for peripheral 174" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 13. "IAF173,illegal access interrupt enable for peripheral 173" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 12. "IAF172,illegal access interrupt enable for peripheral 172" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 11. "IAF171,illegal access interrupt enable for peripheral 171" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 10. "IAF170,illegal access interrupt enable for peripheral 170" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 9. "IAF169,illegal access interrupt enable for peripheral 169" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 8. "IAF168,illegal access interrupt enable for peripheral 168" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 7. "IAF167,illegal access interrupt enable for peripheral 167" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 6. "IAF166,illegal access interrupt enable for peripheral 166" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 5. "IAF165,illegal access interrupt enable for peripheral 165" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 4. "IAF164,illegal access interrupt enable for peripheral 164" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 3. "IAF163,illegal access interrupt enable for peripheral 163" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 2. "IAF162,illegal access interrupt enable for peripheral 162" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 1. "IAF161,illegal access interrupt enable for peripheral 161" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 0. "IAF160,illegal access interrupt enable for peripheral 160" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." wgroup.long 0x100++0x17 line.long 0x0 "IAC_ICR0,IAC interrupt clear register 0" bitfld.long 0x0 31. "IAF31,illegal access flag clear for peripheral 31" "0: IAF 31 flag status not affected,1: IAF 31 flag status cleared in IAC_ISRx" bitfld.long 0x0 30. "IAF30,illegal access flag clear for peripheral 30" "0: IAF 30 flag status not affected,1: IAF 30 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 29. "IAF29,illegal access flag clear for peripheral 29" "0: IAF 29 flag status not affected,1: IAF 29 flag status cleared in IAC_ISRx" bitfld.long 0x0 28. "IAF28,illegal access flag clear for peripheral 28" "0: IAF 28 flag status not affected,1: IAF 28 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 27. "IAF27,illegal access flag clear for peripheral 27" "0: IAF 27 flag status not affected,1: IAF 27 flag status cleared in IAC_ISRx" bitfld.long 0x0 26. "IAF26,illegal access flag clear for peripheral 26" "0: IAF 26 flag status not affected,1: IAF 26 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 25. "IAF25,illegal access flag clear for peripheral 25" "0: IAF 25 flag status not affected,1: IAF 25 flag status cleared in IAC_ISRx" bitfld.long 0x0 24. "IAF24,illegal access flag clear for peripheral 24" "0: IAF 24 flag status not affected,1: IAF 24 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 23. "IAF23,illegal access flag clear for peripheral 23" "0: IAF 23 flag status not affected,1: IAF 23 flag status cleared in IAC_ISRx" bitfld.long 0x0 22. "IAF22,illegal access flag clear for peripheral 22" "0: IAF 22 flag status not affected,1: IAF 22 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 21. "IAF21,illegal access flag clear for peripheral 21" "0: IAF 21 flag status not affected,1: IAF 21 flag status cleared in IAC_ISRx" bitfld.long 0x0 20. "IAF20,illegal access flag clear for peripheral 20" "0: IAF 20 flag status not affected,1: IAF 20 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 19. "IAF19,illegal access flag clear for peripheral 19" "0: IAF 19 flag status not affected,1: IAF 19 flag status cleared in IAC_ISRx" bitfld.long 0x0 18. "IAF18,illegal access flag clear for peripheral 18" "0: IAF 18 flag status not affected,1: IAF 18 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 17. "IAF17,illegal access flag clear for peripheral 17" "0: IAF 17 flag status not affected,1: IAF 17 flag status cleared in IAC_ISRx" bitfld.long 0x0 16. "IAF16,illegal access flag clear for peripheral 16" "0: IAF 16 flag status not affected,1: IAF 16 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 15. "IAF15,illegal access flag clear for peripheral 15" "0: IAF 15 flag status not affected,1: IAF 15 flag status cleared in IAC_ISRx" bitfld.long 0x0 14. "IAF14,illegal access flag clear for peripheral 14" "0: IAF 14 flag status not affected,1: IAF 14 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 13. "IAF13,illegal access flag clear for peripheral 13" "0: IAF 13 flag status not affected,1: IAF 13 flag status cleared in IAC_ISRx" bitfld.long 0x0 12. "IAF12,illegal access flag clear for peripheral 12" "0: IAF 12 flag status not affected,1: IAF 12 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 11. "IAF11,illegal access flag clear for peripheral 11" "0: IAF 11 flag status not affected,1: IAF 11 flag status cleared in IAC_ISRx" bitfld.long 0x0 10. "IAF10,illegal access flag clear for peripheral 10" "0: IAF 10 flag status not affected,1: IAF 10 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 9. "IAF9,illegal access flag clear for peripheral 9" "0: IAF 9 flag status not affected,1: IAF 9 flag status cleared in IAC_ISRx" bitfld.long 0x0 8. "IAF8,illegal access flag clear for peripheral 8" "0: IAF 8 flag status not affected,1: IAF 8 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 7. "IAF7,illegal access flag clear for peripheral 7" "0: IAF 7 flag status not affected,1: IAF 7 flag status cleared in IAC_ISRx" bitfld.long 0x0 6. "IAF6,illegal access flag clear for peripheral 6" "0: IAF 6 flag status not affected,1: IAF 6 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 5. "IAF5,illegal access flag clear for peripheral 5" "0: IAF 5 flag status not affected,1: IAF 5 flag status cleared in IAC_ISRx" bitfld.long 0x0 4. "IAF4,illegal access flag clear for peripheral 4" "0: IAF 4 flag status not affected,1: IAF 4 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 3. "IAF3,illegal access flag clear for peripheral 3" "0: IAF 3 flag status not affected,1: IAF 3 flag status cleared in IAC_ISRx" bitfld.long 0x0 2. "IAF2,illegal access flag clear for peripheral 2" "0: IAF 2 flag status not affected,1: IAF 2 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 1. "IAF1,illegal access flag clear for peripheral 1" "0: IAF 1 flag status not affected,1: IAF 1 flag status cleared in IAC_ISRx" bitfld.long 0x0 0. "IAF0,illegal access flag clear for peripheral 0" "0: IAF 0 flag status not affected,1: IAF 0 flag status cleared in IAC_ISRx" line.long 0x4 "IAC_ICR1,IAC interrupt clear register 1" bitfld.long 0x4 31. "IAF63,illegal access flag clear for peripheral 63" "0: IAF 63 flag status not affected,1: IAF 63 flag status cleared in IAC_ISRx" bitfld.long 0x4 30. "IAF62,illegal access flag clear for peripheral 62" "0: IAF 62 flag status not affected,1: IAF 62 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 29. "IAF61,illegal access flag clear for peripheral 61" "0: IAF 61 flag status not affected,1: IAF 61 flag status cleared in IAC_ISRx" bitfld.long 0x4 28. "IAF60,illegal access flag clear for peripheral 60" "0: IAF 60 flag status not affected,1: IAF 60 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 27. "IAF59,illegal access flag clear for peripheral 59" "0: IAF 59 flag status not affected,1: IAF 59 flag status cleared in IAC_ISRx" bitfld.long 0x4 26. "IAF58,illegal access flag clear for peripheral 58" "0: IAF 58 flag status not affected,1: IAF 58 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 25. "IAF57,illegal access flag clear for peripheral 57" "0: IAF 57 flag status not affected,1: IAF 57 flag status cleared in IAC_ISRx" bitfld.long 0x4 24. "IAF56,illegal access flag clear for peripheral 56" "0: IAF 56 flag status not affected,1: IAF 56 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 23. "IAF55,illegal access flag clear for peripheral 55" "0: IAF 55 flag status not affected,1: IAF 55 flag status cleared in IAC_ISRx" bitfld.long 0x4 22. "IAF54,illegal access flag clear for peripheral 54" "0: IAF 54 flag status not affected,1: IAF 54 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 21. "IAF53,illegal access flag clear for peripheral 53" "0: IAF 53 flag status not affected,1: IAF 53 flag status cleared in IAC_ISRx" bitfld.long 0x4 20. "IAF52,illegal access flag clear for peripheral 52" "0: IAF 52 flag status not affected,1: IAF 52 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 19. "IAF51,illegal access flag clear for peripheral 51" "0: IAF 51 flag status not affected,1: IAF 51 flag status cleared in IAC_ISRx" bitfld.long 0x4 18. "IAF50,illegal access flag clear for peripheral 50" "0: IAF 50 flag status not affected,1: IAF 50 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 17. "IAF49,illegal access flag clear for peripheral 49" "0: IAF 49 flag status not affected,1: IAF 49 flag status cleared in IAC_ISRx" bitfld.long 0x4 16. "IAF48,illegal access flag clear for peripheral 48" "0: IAF 48 flag status not affected,1: IAF 48 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 15. "IAF47,illegal access flag clear for peripheral 47" "0: IAF 47 flag status not affected,1: IAF 47 flag status cleared in IAC_ISRx" bitfld.long 0x4 14. "IAF46,illegal access flag clear for peripheral 46" "0: IAF 46 flag status not affected,1: IAF 46 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 13. "IAF45,illegal access flag clear for peripheral 45" "0: IAF 45 flag status not affected,1: IAF 45 flag status cleared in IAC_ISRx" bitfld.long 0x4 12. "IAF44,illegal access flag clear for peripheral 44" "0: IAF 44 flag status not affected,1: IAF 44 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 11. "IAF43,illegal access flag clear for peripheral 43" "0: IAF 43 flag status not affected,1: IAF 43 flag status cleared in IAC_ISRx" bitfld.long 0x4 10. "IAF42,illegal access flag clear for peripheral 42" "0: IAF 42 flag status not affected,1: IAF 42 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 9. "IAF41,illegal access flag clear for peripheral 41" "0: IAF 41 flag status not affected,1: IAF 41 flag status cleared in IAC_ISRx" bitfld.long 0x4 8. "IAF40,illegal access flag clear for peripheral 40" "0: IAF 40 flag status not affected,1: IAF 40 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 7. "IAF39,illegal access flag clear for peripheral 39" "0: IAF 39 flag status not affected,1: IAF 39 flag status cleared in IAC_ISRx" bitfld.long 0x4 6. "IAF38,illegal access flag clear for peripheral 38" "0: IAF 38 flag status not affected,1: IAF 38 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 5. "IAF37,illegal access flag clear for peripheral 37" "0: IAF 37 flag status not affected,1: IAF 37 flag status cleared in IAC_ISRx" bitfld.long 0x4 4. "IAF36,illegal access flag clear for peripheral 36" "0: IAF 36 flag status not affected,1: IAF 36 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 3. "IAF35,illegal access flag clear for peripheral 35" "0: IAF 35 flag status not affected,1: IAF 35 flag status cleared in IAC_ISRx" bitfld.long 0x4 2. "IAF34,illegal access flag clear for peripheral 34" "0: IAF 34 flag status not affected,1: IAF 34 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 1. "IAF33,illegal access flag clear for peripheral 33" "0: IAF 33 flag status not affected,1: IAF 33 flag status cleared in IAC_ISRx" bitfld.long 0x4 0. "IAF32,illegal access flag clear for peripheral 32" "0: IAF 32 flag status not affected,1: IAF 32 flag status cleared in IAC_ISRx" line.long 0x8 "IAC_ICR2,IAC interrupt clear register 2" bitfld.long 0x8 31. "IAF95,illegal access flag clear for peripheral 95" "0: IAF 95 flag status not affected,1: IAF 95 flag status cleared in IAC_ISRx" bitfld.long 0x8 30. "IAF94,illegal access flag clear for peripheral 94" "0: IAF 94 flag status not affected,1: IAF 94 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 29. "IAF93,illegal access flag clear for peripheral 93" "0: IAF 93 flag status not affected,1: IAF 93 flag status cleared in IAC_ISRx" bitfld.long 0x8 28. "IAF92,illegal access flag clear for peripheral 92" "0: IAF 92 flag status not affected,1: IAF 92 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 27. "IAF91,illegal access flag clear for peripheral 91" "0: IAF 91 flag status not affected,1: IAF 91 flag status cleared in IAC_ISRx" bitfld.long 0x8 26. "IAF90,illegal access flag clear for peripheral 90" "0: IAF 90 flag status not affected,1: IAF 90 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 25. "IAF89,illegal access flag clear for peripheral 89" "0: IAF 89 flag status not affected,1: IAF 89 flag status cleared in IAC_ISRx" bitfld.long 0x8 24. "IAF88,illegal access flag clear for peripheral 88" "0: IAF 88 flag status not affected,1: IAF 88 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 23. "IAF87,illegal access flag clear for peripheral 87" "0: IAF 87 flag status not affected,1: IAF 87 flag status cleared in IAC_ISRx" bitfld.long 0x8 22. "IAF86,illegal access flag clear for peripheral 86" "0: IAF 86 flag status not affected,1: IAF 86 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 21. "IAF85,illegal access flag clear for peripheral 85" "0: IAF 85 flag status not affected,1: IAF 85 flag status cleared in IAC_ISRx" bitfld.long 0x8 20. "IAF84,illegal access flag clear for peripheral 84" "0: IAF 84 flag status not affected,1: IAF 84 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 19. "IAF83,illegal access flag clear for peripheral 83" "0: IAF 83 flag status not affected,1: IAF 83 flag status cleared in IAC_ISRx" bitfld.long 0x8 18. "IAF82,illegal access flag clear for peripheral 82" "0: IAF 82 flag status not affected,1: IAF 82 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 17. "IAF81,illegal access flag clear for peripheral 81" "0: IAF 81 flag status not affected,1: IAF 81 flag status cleared in IAC_ISRx" bitfld.long 0x8 16. "IAF80,illegal access flag clear for peripheral 80" "0: IAF 80 flag status not affected,1: IAF 80 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 15. "IAF79,illegal access flag clear for peripheral 79" "0: IAF 79 flag status not affected,1: IAF 79 flag status cleared in IAC_ISRx" bitfld.long 0x8 14. "IAF78,illegal access flag clear for peripheral 78" "0: IAF 78 flag status not affected,1: IAF 78 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 13. "IAF77,illegal access flag clear for peripheral 77" "0: IAF 77 flag status not affected,1: IAF 77 flag status cleared in IAC_ISRx" bitfld.long 0x8 12. "IAF76,illegal access flag clear for peripheral 76" "0: IAF 76 flag status not affected,1: IAF 76 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 11. "IAF75,illegal access flag clear for peripheral 75" "0: IAF 75 flag status not affected,1: IAF 75 flag status cleared in IAC_ISRx" bitfld.long 0x8 10. "IAF74,illegal access flag clear for peripheral 74" "0: IAF 74 flag status not affected,1: IAF 74 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 9. "IAF73,illegal access flag clear for peripheral 73" "0: IAF 73 flag status not affected,1: IAF 73 flag status cleared in IAC_ISRx" bitfld.long 0x8 8. "IAF72,illegal access flag clear for peripheral 72" "0: IAF 72 flag status not affected,1: IAF 72 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 7. "IAF71,illegal access flag clear for peripheral 71" "0: IAF 71 flag status not affected,1: IAF 71 flag status cleared in IAC_ISRx" bitfld.long 0x8 6. "IAF70,illegal access flag clear for peripheral 70" "0: IAF 70 flag status not affected,1: IAF 70 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 5. "IAF69,illegal access flag clear for peripheral 69" "0: IAF 69 flag status not affected,1: IAF 69 flag status cleared in IAC_ISRx" bitfld.long 0x8 4. "IAF68,illegal access flag clear for peripheral 68" "0: IAF 68 flag status not affected,1: IAF 68 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 3. "IAF67,illegal access flag clear for peripheral 67" "0: IAF 67 flag status not affected,1: IAF 67 flag status cleared in IAC_ISRx" bitfld.long 0x8 2. "IAF66,illegal access flag clear for peripheral 66" "0: IAF 66 flag status not affected,1: IAF 66 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 1. "IAF65,illegal access flag clear for peripheral 65" "0: IAF 65 flag status not affected,1: IAF 65 flag status cleared in IAC_ISRx" bitfld.long 0x8 0. "IAF64,illegal access flag clear for peripheral 64" "0: IAF 64 flag status not affected,1: IAF 64 flag status cleared in IAC_ISRx" line.long 0xC "IAC_ICR3,IAC interrupt clear register 3" bitfld.long 0xC 31. "IAF127,illegal access flag clear for peripheral 127" "0: IAF 127 flag status not affected,1: IAF 127 flag status cleared in IAC_ISRx" bitfld.long 0xC 30. "IAF126,illegal access flag clear for peripheral 126" "0: IAF 126 flag status not affected,1: IAF 126 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 29. "IAF125,illegal access flag clear for peripheral 125" "0: IAF 125 flag status not affected,1: IAF 125 flag status cleared in IAC_ISRx" bitfld.long 0xC 28. "IAF124,illegal access flag clear for peripheral 124" "0: IAF 124 flag status not affected,1: IAF 124 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 27. "IAF123,illegal access flag clear for peripheral 123" "0: IAF 123 flag status not affected,1: IAF 123 flag status cleared in IAC_ISRx" bitfld.long 0xC 26. "IAF122,illegal access flag clear for peripheral 122" "0: IAF 122 flag status not affected,1: IAF 122 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 25. "IAF121,illegal access flag clear for peripheral 121" "0: IAF 121 flag status not affected,1: IAF 121 flag status cleared in IAC_ISRx" bitfld.long 0xC 24. "IAF120,illegal access flag clear for peripheral 120" "0: IAF 120 flag status not affected,1: IAF 120 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 23. "IAF119,illegal access flag clear for peripheral 119" "0: IAF 119 flag status not affected,1: IAF 119 flag status cleared in IAC_ISRx" bitfld.long 0xC 22. "IAF118,illegal access flag clear for peripheral 118" "0: IAF 118 flag status not affected,1: IAF 118 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 21. "IAF117,illegal access flag clear for peripheral 117" "0: IAF 117 flag status not affected,1: IAF 117 flag status cleared in IAC_ISRx" bitfld.long 0xC 20. "IAF116,illegal access flag clear for peripheral 116" "0: IAF 116 flag status not affected,1: IAF 116 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 19. "IAF115,illegal access flag clear for peripheral 115" "0: IAF 115 flag status not affected,1: IAF 115 flag status cleared in IAC_ISRx" bitfld.long 0xC 18. "IAF114,illegal access flag clear for peripheral 114" "0: IAF 114 flag status not affected,1: IAF 114 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 17. "IAF113,illegal access flag clear for peripheral 113" "0: IAF 113 flag status not affected,1: IAF 113 flag status cleared in IAC_ISRx" bitfld.long 0xC 16. "IAF112,illegal access flag clear for peripheral 112" "0: IAF 112 flag status not affected,1: IAF 112 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 15. "IAF111,illegal access flag clear for peripheral 111" "0: IAF 111 flag status not affected,1: IAF 111 flag status cleared in IAC_ISRx" bitfld.long 0xC 14. "IAF110,illegal access flag clear for peripheral 110" "0: IAF 110 flag status not affected,1: IAF 110 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 13. "IAF109,illegal access flag clear for peripheral 109" "0: IAF 109 flag status not affected,1: IAF 109 flag status cleared in IAC_ISRx" bitfld.long 0xC 12. "IAF108,illegal access flag clear for peripheral 108" "0: IAF 108 flag status not affected,1: IAF 108 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 11. "IAF107,illegal access flag clear for peripheral 107" "0: IAF 107 flag status not affected,1: IAF 107 flag status cleared in IAC_ISRx" bitfld.long 0xC 10. "IAF106,illegal access flag clear for peripheral 106" "0: IAF 106 flag status not affected,1: IAF 106 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 9. "IAF105,illegal access flag clear for peripheral 105" "0: IAF 105 flag status not affected,1: IAF 105 flag status cleared in IAC_ISRx" bitfld.long 0xC 8. "IAF104,illegal access flag clear for peripheral 104" "0: IAF 104 flag status not affected,1: IAF 104 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 7. "IAF103,illegal access flag clear for peripheral 103" "0: IAF 103 flag status not affected,1: IAF 103 flag status cleared in IAC_ISRx" bitfld.long 0xC 6. "IAF102,illegal access flag clear for peripheral 102" "0: IAF 102 flag status not affected,1: IAF 102 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 5. "IAF101,illegal access flag clear for peripheral 101" "0: IAF 101 flag status not affected,1: IAF 101 flag status cleared in IAC_ISRx" bitfld.long 0xC 4. "IAF100,illegal access flag clear for peripheral 100" "0: IAF 100 flag status not affected,1: IAF 100 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 3. "IAF99,illegal access flag clear for peripheral 99" "0: IAF 99 flag status not affected,1: IAF 99 flag status cleared in IAC_ISRx" bitfld.long 0xC 2. "IAF98,illegal access flag clear for peripheral 98" "0: IAF 98 flag status not affected,1: IAF 98 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 1. "IAF97,illegal access flag clear for peripheral 97" "0: IAF 97 flag status not affected,1: IAF 97 flag status cleared in IAC_ISRx" bitfld.long 0xC 0. "IAF96,illegal access flag clear for peripheral 96" "0: IAF 96 flag status not affected,1: IAF 96 flag status cleared in IAC_ISRx" line.long 0x10 "IAC_ICR4,IAC interrupt clear register 4" bitfld.long 0x10 31. "IAF159,illegal access flag clear for peripheral 159" "0: IAF 159 flag status not affected,1: IAF 159 flag status cleared in IAC_ISRx" bitfld.long 0x10 30. "IAF158,illegal access flag clear for peripheral 158" "0: IAF 158 flag status not affected,1: IAF 158 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 29. "IAF157,illegal access flag clear for peripheral 157" "0: IAF 157 flag status not affected,1: IAF 157 flag status cleared in IAC_ISRx" bitfld.long 0x10 28. "IAF156,illegal access flag clear for peripheral 156" "0: IAF 156 flag status not affected,1: IAF 156 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 27. "IAF155,illegal access flag clear for peripheral 155" "0: IAF 155 flag status not affected,1: IAF 155 flag status cleared in IAC_ISRx" bitfld.long 0x10 26. "IAF154,illegal access flag clear for peripheral 154" "0: IAF 154 flag status not affected,1: IAF 154 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 25. "IAF153,illegal access flag clear for peripheral 153" "0: IAF 153 flag status not affected,1: IAF 153 flag status cleared in IAC_ISRx" bitfld.long 0x10 24. "IAF152,illegal access flag clear for peripheral 152" "0: IAF 152 flag status not affected,1: IAF 152 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 23. "IAF151,illegal access flag clear for peripheral 151" "0: IAF 151 flag status not affected,1: IAF 151 flag status cleared in IAC_ISRx" bitfld.long 0x10 22. "IAF150,illegal access flag clear for peripheral 150" "0: IAF 150 flag status not affected,1: IAF 150 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 21. "IAF149,illegal access flag clear for peripheral 149" "0: IAF 149 flag status not affected,1: IAF 149 flag status cleared in IAC_ISRx" bitfld.long 0x10 20. "IAF148,illegal access flag clear for peripheral 148" "0: IAF 148 flag status not affected,1: IAF 148 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 19. "IAF147,illegal access flag clear for peripheral 147" "0: IAF 147 flag status not affected,1: IAF 147 flag status cleared in IAC_ISRx" bitfld.long 0x10 18. "IAF146,illegal access flag clear for peripheral 146" "0: IAF 146 flag status not affected,1: IAF 146 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 17. "IAF145,illegal access flag clear for peripheral 145" "0: IAF 145 flag status not affected,1: IAF 145 flag status cleared in IAC_ISRx" bitfld.long 0x10 16. "IAF144,illegal access flag clear for peripheral 144" "0: IAF 144 flag status not affected,1: IAF 144 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 15. "IAF143,illegal access flag clear for peripheral 143" "0: IAF 143 flag status not affected,1: IAF 143 flag status cleared in IAC_ISRx" bitfld.long 0x10 14. "IAF142,illegal access flag clear for peripheral 142" "0: IAF 142 flag status not affected,1: IAF 142 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 13. "IAF141,illegal access flag clear for peripheral 141" "0: IAF 141 flag status not affected,1: IAF 141 flag status cleared in IAC_ISRx" bitfld.long 0x10 12. "IAF140,illegal access flag clear for peripheral 140" "0: IAF 140 flag status not affected,1: IAF 140 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 11. "IAF139,illegal access flag clear for peripheral 139" "0: IAF 139 flag status not affected,1: IAF 139 flag status cleared in IAC_ISRx" bitfld.long 0x10 10. "IAF138,illegal access flag clear for peripheral 138" "0: IAF 138 flag status not affected,1: IAF 138 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 9. "IAF137,illegal access flag clear for peripheral 137" "0: IAF 137 flag status not affected,1: IAF 137 flag status cleared in IAC_ISRx" bitfld.long 0x10 8. "IAF136,illegal access flag clear for peripheral 136" "0: IAF 136 flag status not affected,1: IAF 136 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 7. "IAF135,illegal access flag clear for peripheral 135" "0: IAF 135 flag status not affected,1: IAF 135 flag status cleared in IAC_ISRx" bitfld.long 0x10 6. "IAF134,illegal access flag clear for peripheral 134" "0: IAF 134 flag status not affected,1: IAF 134 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 5. "IAF133,illegal access flag clear for peripheral 133" "0: IAF 133 flag status not affected,1: IAF 133 flag status cleared in IAC_ISRx" bitfld.long 0x10 4. "IAF132,illegal access flag clear for peripheral 132" "0: IAF 132 flag status not affected,1: IAF 132 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 3. "IAF131,illegal access flag clear for peripheral 131" "0: IAF 131 flag status not affected,1: IAF 131 flag status cleared in IAC_ISRx" bitfld.long 0x10 2. "IAF130,illegal access flag clear for peripheral 130" "0: IAF 130 flag status not affected,1: IAF 130 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 1. "IAF129,illegal access flag clear for peripheral 129" "0: IAF 129 flag status not affected,1: IAF 129 flag status cleared in IAC_ISRx" bitfld.long 0x10 0. "IAF128,illegal access flag clear for peripheral 128" "0: IAF 128 flag status not affected,1: IAF 128 flag status cleared in IAC_ISRx" line.long 0x14 "IAC_ICR5,IAC interrupt clear register 5" bitfld.long 0x14 31. "IAF191,illegal access flag clear for peripheral 191" "0: IAF 191 flag status not affected,1: IAF 191 flag status cleared in IAC_ISRx" bitfld.long 0x14 30. "IAF190,illegal access flag clear for peripheral 190" "0: IAF 190 flag status not affected,1: IAF 190 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 29. "IAF189,illegal access flag clear for peripheral 189" "0: IAF 189 flag status not affected,1: IAF 189 flag status cleared in IAC_ISRx" bitfld.long 0x14 28. "IAF188,illegal access flag clear for peripheral 188" "0: IAF 188 flag status not affected,1: IAF 188 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 27. "IAF187,illegal access flag clear for peripheral 187" "0: IAF 187 flag status not affected,1: IAF 187 flag status cleared in IAC_ISRx" bitfld.long 0x14 26. "IAF186,illegal access flag clear for peripheral 186" "0: IAF 186 flag status not affected,1: IAF 186 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 25. "IAF185,illegal access flag clear for peripheral 185" "0: IAF 185 flag status not affected,1: IAF 185 flag status cleared in IAC_ISRx" bitfld.long 0x14 24. "IAF184,illegal access flag clear for peripheral 184" "0: IAF 184 flag status not affected,1: IAF 184 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 23. "IAF183,illegal access flag clear for peripheral 183" "0: IAF 183 flag status not affected,1: IAF 183 flag status cleared in IAC_ISRx" bitfld.long 0x14 22. "IAF182,illegal access flag clear for peripheral 182" "0: IAF 182 flag status not affected,1: IAF 182 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 21. "IAF181,illegal access flag clear for peripheral 181" "0: IAF 181 flag status not affected,1: IAF 181 flag status cleared in IAC_ISRx" bitfld.long 0x14 20. "IAF180,illegal access flag clear for peripheral 180" "0: IAF 180 flag status not affected,1: IAF 180 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 19. "IAF179,illegal access flag clear for peripheral 179" "0: IAF 179 flag status not affected,1: IAF 179 flag status cleared in IAC_ISRx" bitfld.long 0x14 18. "IAF178,illegal access flag clear for peripheral 178" "0: IAF 178 flag status not affected,1: IAF 178 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 17. "IAF177,illegal access flag clear for peripheral 177" "0: IAF 177 flag status not affected,1: IAF 177 flag status cleared in IAC_ISRx" bitfld.long 0x14 16. "IAF176,illegal access flag clear for peripheral 176" "0: IAF 176 flag status not affected,1: IAF 176 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 15. "IAF175,illegal access flag clear for peripheral 175" "0: IAF 175 flag status not affected,1: IAF 175 flag status cleared in IAC_ISRx" bitfld.long 0x14 14. "IAF174,illegal access flag clear for peripheral 174" "0: IAF 174 flag status not affected,1: IAF 174 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 13. "IAF173,illegal access flag clear for peripheral 173" "0: IAF 173 flag status not affected,1: IAF 173 flag status cleared in IAC_ISRx" bitfld.long 0x14 12. "IAF172,illegal access flag clear for peripheral 172" "0: IAF 172 flag status not affected,1: IAF 172 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 11. "IAF171,illegal access flag clear for peripheral 171" "0: IAF 171 flag status not affected,1: IAF 171 flag status cleared in IAC_ISRx" bitfld.long 0x14 10. "IAF170,illegal access flag clear for peripheral 170" "0: IAF 170 flag status not affected,1: IAF 170 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 9. "IAF169,illegal access flag clear for peripheral 169" "0: IAF 169 flag status not affected,1: IAF 169 flag status cleared in IAC_ISRx" bitfld.long 0x14 8. "IAF168,illegal access flag clear for peripheral 168" "0: IAF 168 flag status not affected,1: IAF 168 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 7. "IAF167,illegal access flag clear for peripheral 167" "0: IAF 167 flag status not affected,1: IAF 167 flag status cleared in IAC_ISRx" bitfld.long 0x14 6. "IAF166,illegal access flag clear for peripheral 166" "0: IAF 166 flag status not affected,1: IAF 166 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 5. "IAF165,illegal access flag clear for peripheral 165" "0: IAF 165 flag status not affected,1: IAF 165 flag status cleared in IAC_ISRx" bitfld.long 0x14 4. "IAF164,illegal access flag clear for peripheral 164" "0: IAF 164 flag status not affected,1: IAF 164 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 3. "IAF163,illegal access flag clear for peripheral 163" "0: IAF 163 flag status not affected,1: IAF 163 flag status cleared in IAC_ISRx" bitfld.long 0x14 2. "IAF162,illegal access flag clear for peripheral 162" "0: IAF 162 flag status not affected,1: IAF 162 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 1. "IAF161,illegal access flag clear for peripheral 161" "0: IAF 161 flag status not affected,1: IAF 161 flag status cleared in IAC_ISRx" bitfld.long 0x14 0. "IAF160,illegal access flag clear for peripheral 160" "0: IAF 160 flag status not affected,1: IAF 160 flag status cleared in IAC_ISRx" rgroup.long 0x36C++0x13 line.long 0x0 "IAC_IISR0,IAC ILAC input status register 0" bitfld.long 0x0 31. "ILACIN31,illegal access input 31" "0: ILAC input 31 to IAC not present,1: ILAC input 31 to IAC present" bitfld.long 0x0 30. "ILACIN30,illegal access input 30" "0: ILAC input 30 to IAC not present,1: ILAC input 30 to IAC present" newline bitfld.long 0x0 29. "ILACIN29,illegal access input 29" "0: ILAC input 29 to IAC not present,1: ILAC input 29 to IAC present" bitfld.long 0x0 28. "ILACIN28,illegal access input 28" "0: ILAC input 28 to IAC not present,1: ILAC input 28 to IAC present" newline bitfld.long 0x0 27. "ILACIN27,illegal access input 27" "0: ILAC input 27 to IAC not present,1: ILAC input 27 to IAC present" bitfld.long 0x0 26. "ILACIN26,illegal access input 26" "0: ILAC input 26 to IAC not present,1: ILAC input 26 to IAC present" newline bitfld.long 0x0 25. "ILACIN25,illegal access input 25" "0: ILAC input 25 to IAC not present,1: ILAC input 25 to IAC present" bitfld.long 0x0 24. "ILACIN24,illegal access input 24" "0: ILAC input 24 to IAC not present,1: ILAC input 24 to IAC present" newline bitfld.long 0x0 23. "ILACIN23,illegal access input 23" "0: ILAC input 23 to IAC not present,1: ILAC input 23 to IAC present" bitfld.long 0x0 22. "ILACIN22,illegal access input 22" "0: ILAC input 22 to IAC not present,1: ILAC input 22 to IAC present" newline bitfld.long 0x0 21. "ILACIN21,illegal access input 21" "0: ILAC input 21 to IAC not present,1: ILAC input 21 to IAC present" bitfld.long 0x0 20. "ILACIN20,illegal access input 20" "0: ILAC input 20 to IAC not present,1: ILAC input 20 to IAC present" newline bitfld.long 0x0 19. "ILACIN19,illegal access input 19" "0: ILAC input 19 to IAC not present,1: ILAC input 19 to IAC present" bitfld.long 0x0 18. "ILACIN18,illegal access input 18" "0: ILAC input 18 to IAC not present,1: ILAC input 18 to IAC present" newline bitfld.long 0x0 17. "ILACIN17,illegal access input 17" "0: ILAC input 17 to IAC not present,1: ILAC input 17 to IAC present" bitfld.long 0x0 16. "ILACIN16,illegal access input 16" "0: ILAC input 16 to IAC not present,1: ILAC input 16 to IAC present" newline bitfld.long 0x0 15. "ILACIN15,illegal access input 15" "0: ILAC input 15 to IAC not present,1: ILAC input 15 to IAC present" bitfld.long 0x0 14. "ILACIN14,illegal access input 14" "0: ILAC input 14 to IAC not present,1: ILAC input 14 to IAC present" newline bitfld.long 0x0 13. "ILACIN13,illegal access input 13" "0: ILAC input 13 to IAC not present,1: ILAC input 13 to IAC present" bitfld.long 0x0 12. "ILACIN12,illegal access input 12" "0: ILAC input 12 to IAC not present,1: ILAC input 12 to IAC present" newline bitfld.long 0x0 11. "ILACIN11,illegal access input 11" "0: ILAC input 11 to IAC not present,1: ILAC input 11 to IAC present" bitfld.long 0x0 10. "ILACIN10,illegal access input 10" "0: ILAC input 10 to IAC not present,1: ILAC input 10 to IAC present" newline bitfld.long 0x0 9. "ILACIN9,illegal access input 9" "0: ILAC input 9 to IAC not present,1: ILAC input 9 to IAC present" bitfld.long 0x0 8. "ILACIN8,illegal access input 8" "0: ILAC input 8 to IAC not present,1: ILAC input 8 to IAC present" newline bitfld.long 0x0 7. "ILACIN7,illegal access input 7" "0: ILAC input 7 to IAC not present,1: ILAC input 7 to IAC present" bitfld.long 0x0 6. "ILACIN6,illegal access input 6" "0: ILAC input 6 to IAC not present,1: ILAC input 6 to IAC present" newline bitfld.long 0x0 5. "ILACIN5,illegal access input 5" "0: ILAC input 5 to IAC not present,1: ILAC input 5 to IAC present" bitfld.long 0x0 4. "ILACIN4,illegal access input 4" "0: ILAC input 4 to IAC not present,1: ILAC input 4 to IAC present" newline bitfld.long 0x0 3. "ILACIN3,illegal access input 3" "0: ILAC input 3 to IAC not present,1: ILAC input 3 to IAC present" bitfld.long 0x0 2. "ILACIN2,illegal access input 2" "0: ILAC input 2 to IAC not present,1: ILAC input 2 to IAC present" newline bitfld.long 0x0 1. "ILACIN1,illegal access input 1" "0: ILAC input 1 to IAC not present,1: ILAC input 1 to IAC present" bitfld.long 0x0 0. "ILACIN0,illegal access input 0" "0: ILAC input 0 to IAC not present,1: ILAC input 0 to IAC present" line.long 0x4 "IAC_IISR1,IAC ILAC input status register 1" bitfld.long 0x4 31. "ILACIN63,illegal access input 63" "0: ILAC input 63 to IAC not present,1: ILAC input 63 to IAC present" bitfld.long 0x4 30. "ILACIN62,illegal access input 62" "0: ILAC input 62 to IAC not present,1: ILAC input 62 to IAC present" newline bitfld.long 0x4 29. "ILACIN61,illegal access input 61" "0: ILAC input 61 to IAC not present,1: ILAC input 61 to IAC present" bitfld.long 0x4 28. "ILACIN60,illegal access input 60" "0: ILAC input 60 to IAC not present,1: ILAC input 60 to IAC present" newline bitfld.long 0x4 27. "ILACIN59,illegal access input 59" "0: ILAC input 59 to IAC not present,1: ILAC input 59 to IAC present" bitfld.long 0x4 26. "ILACIN58,illegal access input 58" "0: ILAC input 58 to IAC not present,1: ILAC input 58 to IAC present" newline bitfld.long 0x4 25. "ILACIN57,illegal access input 57" "0: ILAC input 57 to IAC not present,1: ILAC input 57 to IAC present" bitfld.long 0x4 24. "ILACIN56,illegal access input 56" "0: ILAC input 56 to IAC not present,1: ILAC input 56 to IAC present" newline bitfld.long 0x4 23. "ILACIN55,illegal access input 55" "0: ILAC input 55 to IAC not present,1: ILAC input 55 to IAC present" bitfld.long 0x4 22. "ILACIN54,illegal access input 54" "0: ILAC input 54 to IAC not present,1: ILAC input 54 to IAC present" newline bitfld.long 0x4 21. "ILACIN53,illegal access input 53" "0: ILAC input 53 to IAC not present,1: ILAC input 53 to IAC present" bitfld.long 0x4 20. "ILACIN52,illegal access input 52" "0: ILAC input 52 to IAC not present,1: ILAC input 52 to IAC present" newline bitfld.long 0x4 19. "ILACIN51,illegal access input 51" "0: ILAC input 51 to IAC not present,1: ILAC input 51 to IAC present" bitfld.long 0x4 18. "ILACIN50,illegal access input 50" "0: ILAC input 50 to IAC not present,1: ILAC input 50 to IAC present" newline bitfld.long 0x4 17. "ILACIN49,illegal access input 49" "0: ILAC input 49 to IAC not present,1: ILAC input 49 to IAC present" bitfld.long 0x4 16. "ILACIN48,illegal access input 48" "0: ILAC input 48 to IAC not present,1: ILAC input 48 to IAC present" newline bitfld.long 0x4 15. "ILACIN47,illegal access input 47" "0: ILAC input 47 to IAC not present,1: ILAC input 47 to IAC present" bitfld.long 0x4 14. "ILACIN46,illegal access input 46" "0: ILAC input 46 to IAC not present,1: ILAC input 46 to IAC present" newline bitfld.long 0x4 13. "ILACIN45,illegal access input 45" "0: ILAC input 45 to IAC not present,1: ILAC input 45 to IAC present" bitfld.long 0x4 12. "ILACIN44,illegal access input 44" "0: ILAC input 44 to IAC not present,1: ILAC input 44 to IAC present" newline bitfld.long 0x4 11. "ILACIN43,illegal access input 43" "0: ILAC input 43 to IAC not present,1: ILAC input 43 to IAC present" bitfld.long 0x4 10. "ILACIN42,illegal access input 42" "0: ILAC input 42 to IAC not present,1: ILAC input 42 to IAC present" newline bitfld.long 0x4 9. "ILACIN41,illegal access input 41" "0: ILAC input 41 to IAC not present,1: ILAC input 41 to IAC present" bitfld.long 0x4 8. "ILACIN40,illegal access input 40" "0: ILAC input 40 to IAC not present,1: ILAC input 40 to IAC present" newline bitfld.long 0x4 7. "ILACIN39,illegal access input 39" "0: ILAC input 39 to IAC not present,1: ILAC input 39 to IAC present" bitfld.long 0x4 6. "ILACIN38,illegal access input 38" "0: ILAC input 38 to IAC not present,1: ILAC input 38 to IAC present" newline bitfld.long 0x4 5. "ILACIN37,illegal access input 37" "0: ILAC input 37 to IAC not present,1: ILAC input 37 to IAC present" bitfld.long 0x4 4. "ILACIN36,illegal access input 36" "0: ILAC input 36 to IAC not present,1: ILAC input 36 to IAC present" newline bitfld.long 0x4 3. "ILACIN35,illegal access input 35" "0: ILAC input 35 to IAC not present,1: ILAC input 35 to IAC present" bitfld.long 0x4 2. "ILACIN34,illegal access input 34" "0: ILAC input 34 to IAC not present,1: ILAC input 34 to IAC present" newline bitfld.long 0x4 1. "ILACIN33,illegal access input 33" "0: ILAC input 33 to IAC not present,1: ILAC input 33 to IAC present" bitfld.long 0x4 0. "ILACIN32,illegal access input 32" "0: ILAC input 32 to IAC not present,1: ILAC input 32 to IAC present" line.long 0x8 "IAC_IISR2,IAC ILAC input status register 2" bitfld.long 0x8 31. "ILACIN95,illegal access input 95" "0: ILAC input 95 to IAC not present,1: ILAC input 95 to IAC present" bitfld.long 0x8 30. "ILACIN94,illegal access input 94" "0: ILAC input 94 to IAC not present,1: ILAC input 94 to IAC present" newline bitfld.long 0x8 29. "ILACIN93,illegal access input 93" "0: ILAC input 93 to IAC not present,1: ILAC input 93 to IAC present" bitfld.long 0x8 28. "ILACIN92,illegal access input 92" "0: ILAC input 92 to IAC not present,1: ILAC input 92 to IAC present" newline bitfld.long 0x8 27. "ILACIN91,illegal access input 91" "0: ILAC input 91 to IAC not present,1: ILAC input 91 to IAC present" bitfld.long 0x8 26. "ILACIN90,illegal access input 90" "0: ILAC input 90 to IAC not present,1: ILAC input 90 to IAC present" newline bitfld.long 0x8 25. "ILACIN89,illegal access input 89" "0: ILAC input 89 to IAC not present,1: ILAC input 89 to IAC present" bitfld.long 0x8 24. "ILACIN88,illegal access input 88" "0: ILAC input 88 to IAC not present,1: ILAC input 88 to IAC present" newline bitfld.long 0x8 23. "ILACIN87,illegal access input 87" "0: ILAC input 87 to IAC not present,1: ILAC input 87 to IAC present" bitfld.long 0x8 22. "ILACIN86,illegal access input 86" "0: ILAC input 86 to IAC not present,1: ILAC input 86 to IAC present" newline bitfld.long 0x8 21. "ILACIN85,illegal access input 85" "0: ILAC input 85 to IAC not present,1: ILAC input 85 to IAC present" bitfld.long 0x8 20. "ILACIN84,illegal access input 84" "0: ILAC input 84 to IAC not present,1: ILAC input 84 to IAC present" newline bitfld.long 0x8 19. "ILACIN83,illegal access input 83" "0: ILAC input 83 to IAC not present,1: ILAC input 83 to IAC present" bitfld.long 0x8 18. "ILACIN82,illegal access input 82" "0: ILAC input 82 to IAC not present,1: ILAC input 82 to IAC present" newline bitfld.long 0x8 17. "ILACIN81,illegal access input 81" "0: ILAC input 81 to IAC not present,1: ILAC input 81 to IAC present" bitfld.long 0x8 16. "ILACIN80,illegal access input 80" "0: ILAC input 80 to IAC not present,1: ILAC input 80 to IAC present" newline bitfld.long 0x8 15. "ILACIN79,illegal access input 79" "0: ILAC input 79 to IAC not present,1: ILAC input 79 to IAC present" bitfld.long 0x8 14. "ILACIN78,illegal access input 78" "0: ILAC input 78 to IAC not present,1: ILAC input 78 to IAC present" newline bitfld.long 0x8 13. "ILACIN77,illegal access input 77" "0: ILAC input 77 to IAC not present,1: ILAC input 77 to IAC present" bitfld.long 0x8 12. "ILACIN76,illegal access input 76" "0: ILAC input 76 to IAC not present,1: ILAC input 76 to IAC present" newline bitfld.long 0x8 11. "ILACIN75,illegal access input 75" "0: ILAC input 75 to IAC not present,1: ILAC input 75 to IAC present" bitfld.long 0x8 10. "ILACIN74,illegal access input 74" "0: ILAC input 74 to IAC not present,1: ILAC input 74 to IAC present" newline bitfld.long 0x8 9. "ILACIN73,illegal access input 73" "0: ILAC input 73 to IAC not present,1: ILAC input 73 to IAC present" bitfld.long 0x8 8. "ILACIN72,illegal access input 72" "0: ILAC input 72 to IAC not present,1: ILAC input 72 to IAC present" newline bitfld.long 0x8 7. "ILACIN71,illegal access input 71" "0: ILAC input 71 to IAC not present,1: ILAC input 71 to IAC present" bitfld.long 0x8 6. "ILACIN70,illegal access input 70" "0: ILAC input 70 to IAC not present,1: ILAC input 70 to IAC present" newline bitfld.long 0x8 5. "ILACIN69,illegal access input 69" "0: ILAC input 69 to IAC not present,1: ILAC input 69 to IAC present" bitfld.long 0x8 4. "ILACIN68,illegal access input 68" "0: ILAC input 68 to IAC not present,1: ILAC input 68 to IAC present" newline bitfld.long 0x8 3. "ILACIN67,illegal access input 67" "0: ILAC input 67 to IAC not present,1: ILAC input 67 to IAC present" bitfld.long 0x8 2. "ILACIN66,illegal access input 66" "0: ILAC input 66 to IAC not present,1: ILAC input 66 to IAC present" newline bitfld.long 0x8 1. "ILACIN65,illegal access input 65" "0: ILAC input 65 to IAC not present,1: ILAC input 65 to IAC present" bitfld.long 0x8 0. "ILACIN64,illegal access input 64" "0: ILAC input 64 to IAC not present,1: ILAC input 64 to IAC present" line.long 0xC "IAC_IISR3,IAC ILAC input status register 3" bitfld.long 0xC 31. "ILACIN127,illegal access input 127" "0: ILAC input 127 to IAC not present,1: ILAC input 127 to IAC present" bitfld.long 0xC 30. "ILACIN126,illegal access input 126" "0: ILAC input 126 to IAC not present,1: ILAC input 126 to IAC present" newline bitfld.long 0xC 29. "ILACIN125,illegal access input 125" "0: ILAC input 125 to IAC not present,1: ILAC input 125 to IAC present" bitfld.long 0xC 28. "ILACIN124,illegal access input 124" "0: ILAC input 124 to IAC not present,1: ILAC input 124 to IAC present" newline bitfld.long 0xC 27. "ILACIN123,illegal access input 123" "0: ILAC input 123 to IAC not present,1: ILAC input 123 to IAC present" bitfld.long 0xC 26. "ILACIN122,illegal access input 122" "0: ILAC input 122 to IAC not present,1: ILAC input 122 to IAC present" newline bitfld.long 0xC 25. "ILACIN121,illegal access input 121" "0: ILAC input 121 to IAC not present,1: ILAC input 121 to IAC present" bitfld.long 0xC 24. "ILACIN120,illegal access input 120" "0: ILAC input 120 to IAC not present,1: ILAC input 120 to IAC present" newline bitfld.long 0xC 23. "ILACIN119,illegal access input 119" "0: ILAC input 119 to IAC not present,1: ILAC input 119 to IAC present" bitfld.long 0xC 22. "ILACIN118,illegal access input 118" "0: ILAC input 118 to IAC not present,1: ILAC input 118 to IAC present" newline bitfld.long 0xC 21. "ILACIN117,illegal access input 117" "0: ILAC input 117 to IAC not present,1: ILAC input 117 to IAC present" bitfld.long 0xC 20. "ILACIN116,illegal access input 116" "0: ILAC input 116 to IAC not present,1: ILAC input 116 to IAC present" newline bitfld.long 0xC 19. "ILACIN115,illegal access input 115" "0: ILAC input 115 to IAC not present,1: ILAC input 115 to IAC present" bitfld.long 0xC 18. "ILACIN114,illegal access input 114" "0: ILAC input 114 to IAC not present,1: ILAC input 114 to IAC present" newline bitfld.long 0xC 17. "ILACIN113,illegal access input 113" "0: ILAC input 113 to IAC not present,1: ILAC input 113 to IAC present" bitfld.long 0xC 16. "ILACIN112,illegal access input 112" "0: ILAC input 112 to IAC not present,1: ILAC input 112 to IAC present" newline bitfld.long 0xC 15. "ILACIN111,illegal access input 111" "0: ILAC input 111 to IAC not present,1: ILAC input 111 to IAC present" bitfld.long 0xC 14. "ILACIN110,illegal access input 110" "0: ILAC input 110 to IAC not present,1: ILAC input 110 to IAC present" newline bitfld.long 0xC 13. "ILACIN109,illegal access input 109" "0: ILAC input 109 to IAC not present,1: ILAC input 109 to IAC present" bitfld.long 0xC 12. "ILACIN108,illegal access input 108" "0: ILAC input 108 to IAC not present,1: ILAC input 108 to IAC present" newline bitfld.long 0xC 11. "ILACIN107,illegal access input 107" "0: ILAC input 107 to IAC not present,1: ILAC input 107 to IAC present" bitfld.long 0xC 10. "ILACIN106,illegal access input 106" "0: ILAC input 106 to IAC not present,1: ILAC input 106 to IAC present" newline bitfld.long 0xC 9. "ILACIN105,illegal access input 105" "0: ILAC input 105 to IAC not present,1: ILAC input 105 to IAC present" bitfld.long 0xC 8. "ILACIN104,illegal access input 104" "0: ILAC input 104 to IAC not present,1: ILAC input 104 to IAC present" newline bitfld.long 0xC 7. "ILACIN103,illegal access input 103" "0: ILAC input 103 to IAC not present,1: ILAC input 103 to IAC present" bitfld.long 0xC 6. "ILACIN102,illegal access input 102" "0: ILAC input 102 to IAC not present,1: ILAC input 102 to IAC present" newline bitfld.long 0xC 5. "ILACIN101,illegal access input 101" "0: ILAC input 101 to IAC not present,1: ILAC input 101 to IAC present" bitfld.long 0xC 4. "ILACIN100,illegal access input 100" "0: ILAC input 100 to IAC not present,1: ILAC input 100 to IAC present" newline bitfld.long 0xC 3. "ILACIN99,illegal access input 99" "0: ILAC input 99 to IAC not present,1: ILAC input 99 to IAC present" bitfld.long 0xC 2. "ILACIN98,illegal access input 98" "0: ILAC input 98 to IAC not present,1: ILAC input 98 to IAC present" newline bitfld.long 0xC 1. "ILACIN97,illegal access input 97" "0: ILAC input 97 to IAC not present,1: ILAC input 97 to IAC present" bitfld.long 0xC 0. "ILACIN96,illegal access input 96" "0: ILAC input 96 to IAC not present,1: ILAC input 96 to IAC present" line.long 0x10 "IAC_IISR4,IAC ILAC input status register 4" bitfld.long 0x10 31. "ILACIN159,illegal access input 159" "0: ILAC input 159 to IAC not present,1: ILAC input 159 to IAC present" bitfld.long 0x10 30. "ILACIN158,illegal access input 158" "0: ILAC input 158 to IAC not present,1: ILAC input 158 to IAC present" newline bitfld.long 0x10 29. "ILACIN157,illegal access input 157" "0: ILAC input 157 to IAC not present,1: ILAC input 157 to IAC present" bitfld.long 0x10 28. "ILACIN156,illegal access input 156" "0: ILAC input 156 to IAC not present,1: ILAC input 156 to IAC present" newline bitfld.long 0x10 27. "ILACIN155,illegal access input 155" "0: ILAC input 155 to IAC not present,1: ILAC input 155 to IAC present" bitfld.long 0x10 26. "ILACIN154,illegal access input 154" "0: ILAC input 154 to IAC not present,1: ILAC input 154 to IAC present" newline bitfld.long 0x10 25. "ILACIN153,illegal access input 153" "0: ILAC input 153 to IAC not present,1: ILAC input 153 to IAC present" bitfld.long 0x10 24. "ILACIN152,illegal access input 152" "0: ILAC input 152 to IAC not present,1: ILAC input 152 to IAC present" newline bitfld.long 0x10 23. "ILACIN151,illegal access input 151" "0: ILAC input 151 to IAC not present,1: ILAC input 151 to IAC present" bitfld.long 0x10 22. "ILACIN150,illegal access input 150" "0: ILAC input 150 to IAC not present,1: ILAC input 150 to IAC present" newline bitfld.long 0x10 21. "ILACIN149,illegal access input 149" "0: ILAC input 149 to IAC not present,1: ILAC input 149 to IAC present" bitfld.long 0x10 20. "ILACIN148,illegal access input 148" "0: ILAC input 148 to IAC not present,1: ILAC input 148 to IAC present" newline bitfld.long 0x10 19. "ILACIN147,illegal access input 147" "0: ILAC input 147 to IAC not present,1: ILAC input 147 to IAC present" bitfld.long 0x10 18. "ILACIN146,illegal access input 146" "0: ILAC input 146 to IAC not present,1: ILAC input 146 to IAC present" newline bitfld.long 0x10 17. "ILACIN145,illegal access input 145" "0: ILAC input 145 to IAC not present,1: ILAC input 145 to IAC present" bitfld.long 0x10 16. "ILACIN144,illegal access input 144" "0: ILAC input 144 to IAC not present,1: ILAC input 144 to IAC present" newline bitfld.long 0x10 15. "ILACIN143,illegal access input 143" "0: ILAC input 143 to IAC not present,1: ILAC input 143 to IAC present" bitfld.long 0x10 14. "ILACIN142,illegal access input 142" "0: ILAC input 142 to IAC not present,1: ILAC input 142 to IAC present" newline bitfld.long 0x10 13. "ILACIN141,illegal access input 141" "0: ILAC input 141 to IAC not present,1: ILAC input 141 to IAC present" bitfld.long 0x10 12. "ILACIN140,illegal access input 140" "0: ILAC input 140 to IAC not present,1: ILAC input 140 to IAC present" newline bitfld.long 0x10 11. "ILACIN139,illegal access input 139" "0: ILAC input 139 to IAC not present,1: ILAC input 139 to IAC present" bitfld.long 0x10 10. "ILACIN138,illegal access input 138" "0: ILAC input 138 to IAC not present,1: ILAC input 138 to IAC present" newline bitfld.long 0x10 9. "ILACIN137,illegal access input 137" "0: ILAC input 137 to IAC not present,1: ILAC input 137 to IAC present" bitfld.long 0x10 8. "ILACIN136,illegal access input 136" "0: ILAC input 136 to IAC not present,1: ILAC input 136 to IAC present" newline bitfld.long 0x10 7. "ILACIN135,illegal access input 135" "0: ILAC input 135 to IAC not present,1: ILAC input 135 to IAC present" bitfld.long 0x10 6. "ILACIN134,illegal access input 134" "0: ILAC input 134 to IAC not present,1: ILAC input 134 to IAC present" newline bitfld.long 0x10 5. "ILACIN133,illegal access input 133" "0: ILAC input 133 to IAC not present,1: ILAC input 133 to IAC present" bitfld.long 0x10 4. "ILACIN132,illegal access input 132" "0: ILAC input 132 to IAC not present,1: ILAC input 132 to IAC present" newline bitfld.long 0x10 3. "ILACIN131,illegal access input 131" "0: ILAC input 131 to IAC not present,1: ILAC input 131 to IAC present" bitfld.long 0x10 2. "ILACIN130,illegal access input 130" "0: ILAC input 130 to IAC not present,1: ILAC input 130 to IAC present" newline bitfld.long 0x10 1. "ILACIN129,illegal access input 129" "0: ILAC input 129 to IAC not present,1: ILAC input 129 to IAC present" bitfld.long 0x10 0. "ILACIN128,illegal access input 128" "0: ILAC input 128 to IAC not present,1: ILAC input 128 to IAC present" rgroup.long 0x384++0x3 line.long 0x0 "IAC_IISR5,IAC ILAC input status register 5" bitfld.long 0x0 31. "ILACIN159,illegal access input 159" "0: ILAC input 159 to IAC not present,1: ILAC input 159 to IAC present" bitfld.long 0x0 30. "ILACIN158,illegal access input 158" "0: ILAC input 158 to IAC not present,1: ILAC input 158 to IAC present" newline bitfld.long 0x0 29. "ILACIN157,illegal access input 157" "0: ILAC input 157 to IAC not present,1: ILAC input 157 to IAC present" bitfld.long 0x0 28. "ILACIN156,illegal access input 156" "0: ILAC input 156 to IAC not present,1: ILAC input 156 to IAC present" newline bitfld.long 0x0 27. "ILACIN155,illegal access input 155" "0: ILAC input 155 to IAC not present,1: ILAC input 155 to IAC present" bitfld.long 0x0 26. "ILACIN154,illegal access input 154" "0: ILAC input 154 to IAC not present,1: ILAC input 154 to IAC present" newline bitfld.long 0x0 25. "ILACIN153,illegal access input 153" "0: ILAC input 153 to IAC not present,1: ILAC input 153 to IAC present" bitfld.long 0x0 24. "ILACIN152,illegal access input 152" "0: ILAC input 152 to IAC not present,1: ILAC input 152 to IAC present" newline bitfld.long 0x0 23. "ILACIN151,illegal access input 151" "0: ILAC input 151 to IAC not present,1: ILAC input 151 to IAC present" bitfld.long 0x0 22. "ILACIN150,illegal access input 150" "0: ILAC input 150 to IAC not present,1: ILAC input 150 to IAC present" newline bitfld.long 0x0 21. "ILACIN149,illegal access input 149" "0: ILAC input 149 to IAC not present,1: ILAC input 149 to IAC present" bitfld.long 0x0 20. "ILACIN148,illegal access input 148" "0: ILAC input 148 to IAC not present,1: ILAC input 148 to IAC present" newline bitfld.long 0x0 19. "ILACIN147,illegal access input 147" "0: ILAC input 147 to IAC not present,1: ILAC input 147 to IAC present" bitfld.long 0x0 18. "ILACIN146,illegal access input 146" "0: ILAC input 146 to IAC not present,1: ILAC input 146 to IAC present" newline bitfld.long 0x0 17. "ILACIN145,illegal access input 145" "0: ILAC input 145 to IAC not present,1: ILAC input 145 to IAC present" bitfld.long 0x0 16. "ILACIN144,illegal access input 144" "0: ILAC input 144 to IAC not present,1: ILAC input 144 to IAC present" newline bitfld.long 0x0 15. "ILACIN143,illegal access input 143" "0: ILAC input 143 to IAC not present,1: ILAC input 143 to IAC present" bitfld.long 0x0 14. "ILACIN142,illegal access input 142" "0: ILAC input 142 to IAC not present,1: ILAC input 142 to IAC present" newline bitfld.long 0x0 13. "ILACIN141,illegal access input 141" "0: ILAC input 141 to IAC not present,1: ILAC input 141 to IAC present" bitfld.long 0x0 12. "ILACIN140,illegal access input 140" "0: ILAC input 140 to IAC not present,1: ILAC input 140 to IAC present" newline bitfld.long 0x0 11. "ILACIN139,illegal access input 139" "0: ILAC input 139 to IAC not present,1: ILAC input 139 to IAC present" bitfld.long 0x0 10. "ILACIN138,illegal access input 138" "0: ILAC input 138 to IAC not present,1: ILAC input 138 to IAC present" newline bitfld.long 0x0 9. "ILACIN137,illegal access input 137" "0: ILAC input 137 to IAC not present,1: ILAC input 137 to IAC present" bitfld.long 0x0 8. "ILACIN136,illegal access input 136" "0: ILAC input 136 to IAC not present,1: ILAC input 136 to IAC present" newline bitfld.long 0x0 7. "ILACIN135,illegal access input 135" "0: ILAC input 135 to IAC not present,1: ILAC input 135 to IAC present" bitfld.long 0x0 6. "ILACIN134,illegal access input 134" "0: ILAC input 134 to IAC not present,1: ILAC input 134 to IAC present" newline bitfld.long 0x0 5. "ILACIN133,illegal access input 133" "0: ILAC input 133 to IAC not present,1: ILAC input 133 to IAC present" bitfld.long 0x0 4. "ILACIN132,illegal access input 132" "0: ILAC input 132 to IAC not present,1: ILAC input 132 to IAC present" newline bitfld.long 0x0 3. "ILACIN131,illegal access input 131" "0: ILAC input 131 to IAC not present,1: ILAC input 131 to IAC present" bitfld.long 0x0 2. "ILACIN130,illegal access input 130" "0: ILAC input 130 to IAC not present,1: ILAC input 130 to IAC present" newline bitfld.long 0x0 1. "ILACIN129,illegal access input 129" "0: ILAC input 129 to IAC not present,1: ILAC input 129 to IAC present" bitfld.long 0x0 0. "ILACIN128,illegal access input 128" "0: ILAC input 128 to IAC not present,1: ILAC input 128 to IAC present" tree.end tree "IAC_S" base ad:0x54025000 group.long 0x0++0x17 line.long 0x0 "IAC_IER0,IAC interrupt enable register 0" bitfld.long 0x0 31. "IAIE31,illegal access interrupt enable for peripheral 31" "0: Illegal access event from peripheral 31 does not..,1: Illegal access event from peripheral 31 can.." bitfld.long 0x0 30. "IAIE30,illegal access interrupt enable for peripheral 30" "0: Illegal access event from peripheral 30 does not..,1: Illegal access event from peripheral 30 can.." newline bitfld.long 0x0 29. "IAIE29,illegal access interrupt enable for peripheral 29" "0: Illegal access event from peripheral 29 does not..,1: Illegal access event from peripheral 29 can.." bitfld.long 0x0 28. "IAIE28,illegal access interrupt enable for peripheral 28" "0: Illegal access event from peripheral 28 does not..,1: Illegal access event from peripheral 28 can.." newline bitfld.long 0x0 27. "IAIE27,illegal access interrupt enable for peripheral 27" "0: Illegal access event from peripheral 27 does not..,1: Illegal access event from peripheral 27 can.." bitfld.long 0x0 26. "IAIE26,illegal access interrupt enable for peripheral 26" "0: Illegal access event from peripheral 26 does not..,1: Illegal access event from peripheral 26 can.." newline bitfld.long 0x0 25. "IAIE25,illegal access interrupt enable for peripheral 25" "0: Illegal access event from peripheral 25 does not..,1: Illegal access event from peripheral 25 can.." bitfld.long 0x0 24. "IAIE24,illegal access interrupt enable for peripheral 24" "0: Illegal access event from peripheral 24 does not..,1: Illegal access event from peripheral 24 can.." newline bitfld.long 0x0 23. "IAIE23,illegal access interrupt enable for peripheral 23" "0: Illegal access event from peripheral 23 does not..,1: Illegal access event from peripheral 23 can.." bitfld.long 0x0 22. "IAIE22,illegal access interrupt enable for peripheral 22" "0: Illegal access event from peripheral 22 does not..,1: Illegal access event from peripheral 22 can.." newline bitfld.long 0x0 21. "IAIE21,illegal access interrupt enable for peripheral 21" "0: Illegal access event from peripheral 21 does not..,1: Illegal access event from peripheral 21 can.." bitfld.long 0x0 20. "IAIE20,illegal access interrupt enable for peripheral 20" "0: Illegal access event from peripheral 20 does not..,1: Illegal access event from peripheral 20 can.." newline bitfld.long 0x0 19. "IAIE19,illegal access interrupt enable for peripheral 19" "0: Illegal access event from peripheral 19 does not..,1: Illegal access event from peripheral 19 can.." bitfld.long 0x0 18. "IAIE18,illegal access interrupt enable for peripheral 18" "0: Illegal access event from peripheral 18 does not..,1: Illegal access event from peripheral 18 can.." newline bitfld.long 0x0 17. "IAIE17,illegal access interrupt enable for peripheral 17" "0: Illegal access event from peripheral 17 does not..,1: Illegal access event from peripheral 17 can.." bitfld.long 0x0 16. "IAIE16,illegal access interrupt enable for peripheral 16" "0: Illegal access event from peripheral 16 does not..,1: Illegal access event from peripheral 16 can.." newline bitfld.long 0x0 15. "IAIE15,illegal access interrupt enable for peripheral 15" "0: Illegal access event from peripheral 15 does not..,1: Illegal access event from peripheral 15 can.." bitfld.long 0x0 14. "IAIE14,illegal access interrupt enable for peripheral 14" "0: Illegal access event from peripheral 14 does not..,1: Illegal access event from peripheral 14 can.." newline bitfld.long 0x0 13. "IAIE13,illegal access interrupt enable for peripheral 13" "0: Illegal access event from peripheral 13 does not..,1: Illegal access event from peripheral 13 can.." bitfld.long 0x0 12. "IAIE12,illegal access interrupt enable for peripheral 12" "0: Illegal access event from peripheral 12 does not..,1: Illegal access event from peripheral 12 can.." newline bitfld.long 0x0 11. "IAIE11,illegal access interrupt enable for peripheral 11" "0: Illegal access event from peripheral 11 does not..,1: Illegal access event from peripheral 11 can.." bitfld.long 0x0 10. "IAIE10,illegal access interrupt enable for peripheral 10" "0: Illegal access event from peripheral 10 does not..,1: Illegal access event from peripheral 10 can.." newline bitfld.long 0x0 9. "IAIE9,illegal access interrupt enable for peripheral 9" "0: Illegal access event from peripheral 9 does not..,1: Illegal access event from peripheral 9 can.." bitfld.long 0x0 8. "IAIE8,illegal access interrupt enable for peripheral 8" "0: Illegal access event from peripheral 8 does not..,1: Illegal access event from peripheral 8 can.." newline bitfld.long 0x0 7. "IAIE7,illegal access interrupt enable for peripheral 7" "0: Illegal access event from peripheral 7 does not..,1: Illegal access event from peripheral 7 can.." bitfld.long 0x0 6. "IAIE6,illegal access interrupt enable for peripheral 6" "0: Illegal access event from peripheral 6 does not..,1: Illegal access event from peripheral 6 can.." newline bitfld.long 0x0 5. "IAIE5,illegal access interrupt enable for peripheral 5" "0: Illegal access event from peripheral 5 does not..,1: Illegal access event from peripheral 5 can.." bitfld.long 0x0 4. "IAIE4,illegal access interrupt enable for peripheral 4" "0: Illegal access event from peripheral 4 does not..,1: Illegal access event from peripheral 4 can.." newline bitfld.long 0x0 3. "IAIE3,illegal access interrupt enable for peripheral 3" "0: Illegal access event from peripheral 3 does not..,1: Illegal access event from peripheral 3 can.." bitfld.long 0x0 2. "IAIE2,illegal access interrupt enable for peripheral 2" "0: Illegal access event from peripheral 2 does not..,1: Illegal access event from peripheral 2 can.." newline bitfld.long 0x0 1. "IAIE1,illegal access interrupt enable for peripheral 1" "0: Illegal access event from peripheral 1 does not..,1: Illegal access event from peripheral 1 can.." bitfld.long 0x0 0. "IAIE0,illegal access interrupt enable for peripheral 0" "0: Illegal access event from peripheral 0 does not..,1: Illegal access event from peripheral 0 can.." line.long 0x4 "IAC_IER1,IAC interrupt enable register 1" bitfld.long 0x4 31. "IAIE63,illegal access interrupt enable for peripheral 63" "0: Illegal access event from peripheral 63 does not..,1: Illegal access event from peripheral 63 can.." bitfld.long 0x4 30. "IAIE62,illegal access interrupt enable for peripheral 62" "0: Illegal access event from peripheral 62 does not..,1: Illegal access event from peripheral 62 can.." newline bitfld.long 0x4 29. "IAIE61,illegal access interrupt enable for peripheral 61" "0: Illegal access event from peripheral 61 does not..,1: Illegal access event from peripheral 61 can.." bitfld.long 0x4 28. "IAIE60,illegal access interrupt enable for peripheral 60" "0: Illegal access event from peripheral 60 does not..,1: Illegal access event from peripheral 60 can.." newline bitfld.long 0x4 27. "IAIE59,illegal access interrupt enable for peripheral 59" "0: Illegal access event from peripheral 59 does not..,1: Illegal access event from peripheral 59 can.." bitfld.long 0x4 26. "IAIE58,illegal access interrupt enable for peripheral 58" "0: Illegal access event from peripheral 58 does not..,1: Illegal access event from peripheral 58 can.." newline bitfld.long 0x4 25. "IAIE57,illegal access interrupt enable for peripheral 57" "0: Illegal access event from peripheral 57 does not..,1: Illegal access event from peripheral 57 can.." bitfld.long 0x4 24. "IAIE56,illegal access interrupt enable for peripheral 56" "0: Illegal access event from peripheral 56 does not..,1: Illegal access event from peripheral 56 can.." newline bitfld.long 0x4 23. "IAIE55,illegal access interrupt enable for peripheral 55" "0: Illegal access event from peripheral 55 does not..,1: Illegal access event from peripheral 55 can.." bitfld.long 0x4 22. "IAIE54,illegal access interrupt enable for peripheral 54" "0: Illegal access event from peripheral 54 does not..,1: Illegal access event from peripheral 54 can.." newline bitfld.long 0x4 21. "IAIE53,illegal access interrupt enable for peripheral 53" "0: Illegal access event from peripheral 53 does not..,1: Illegal access event from peripheral 53 can.." bitfld.long 0x4 20. "IAIE52,illegal access interrupt enable for peripheral 52" "0: Illegal access event from peripheral 52 does not..,1: Illegal access event from peripheral 52 can.." newline bitfld.long 0x4 19. "IAIE51,illegal access interrupt enable for peripheral 51" "0: Illegal access event from peripheral 51 does not..,1: Illegal access event from peripheral 51 can.." bitfld.long 0x4 18. "IAIE50,illegal access interrupt enable for peripheral 50" "0: Illegal access event from peripheral 50 does not..,1: Illegal access event from peripheral 50 can.." newline bitfld.long 0x4 17. "IAIE49,illegal access interrupt enable for peripheral 49" "0: Illegal access event from peripheral 49 does not..,1: Illegal access event from peripheral 49 can.." bitfld.long 0x4 16. "IAIE48,illegal access interrupt enable for peripheral 48" "0: Illegal access event from peripheral 48 does not..,1: Illegal access event from peripheral 48 can.." newline bitfld.long 0x4 15. "IAIE47,illegal access interrupt enable for peripheral 47" "0: Illegal access event from peripheral 47 does not..,1: Illegal access event from peripheral 47 can.." bitfld.long 0x4 14. "IAIE46,illegal access interrupt enable for peripheral 46" "0: Illegal access event from peripheral 46 does not..,1: Illegal access event from peripheral 46 can.." newline bitfld.long 0x4 13. "IAIE45,illegal access interrupt enable for peripheral 45" "0: Illegal access event from peripheral 45 does not..,1: Illegal access event from peripheral 45 can.." bitfld.long 0x4 12. "IAIE44,illegal access interrupt enable for peripheral 44" "0: Illegal access event from peripheral 44 does not..,1: Illegal access event from peripheral 44 can.." newline bitfld.long 0x4 11. "IAIE43,illegal access interrupt enable for peripheral 43" "0: Illegal access event from peripheral 43 does not..,1: Illegal access event from peripheral 43 can.." bitfld.long 0x4 10. "IAIE42,illegal access interrupt enable for peripheral 42" "0: Illegal access event from peripheral 42 does not..,1: Illegal access event from peripheral 42 can.." newline bitfld.long 0x4 9. "IAIE41,illegal access interrupt enable for peripheral 41" "0: Illegal access event from peripheral 41 does not..,1: Illegal access event from peripheral 41 can.." bitfld.long 0x4 8. "IAIE40,illegal access interrupt enable for peripheral 40" "0: Illegal access event from peripheral 40 does not..,1: Illegal access event from peripheral 40 can.." newline bitfld.long 0x4 7. "IAIE39,illegal access interrupt enable for peripheral 39" "0: Illegal access event from peripheral 39 does not..,1: Illegal access event from peripheral 39 can.." bitfld.long 0x4 6. "IAIE38,illegal access interrupt enable for peripheral 38" "0: Illegal access event from peripheral 38 does not..,1: Illegal access event from peripheral 38 can.." newline bitfld.long 0x4 5. "IAIE37,illegal access interrupt enable for peripheral 37" "0: Illegal access event from peripheral 37 does not..,1: Illegal access event from peripheral 37 can.." bitfld.long 0x4 4. "IAIE36,illegal access interrupt enable for peripheral 36" "0: Illegal access event from peripheral 36 does not..,1: Illegal access event from peripheral 36 can.." newline bitfld.long 0x4 3. "IAIE35,illegal access interrupt enable for peripheral 35" "0: Illegal access event from peripheral 35 does not..,1: Illegal access event from peripheral 35 can.." bitfld.long 0x4 2. "IAIE34,illegal access interrupt enable for peripheral 34" "0: Illegal access event from peripheral 34 does not..,1: Illegal access event from peripheral 34 can.." newline bitfld.long 0x4 1. "IAIE33,illegal access interrupt enable for peripheral 33" "0: Illegal access event from peripheral 33 does not..,1: Illegal access event from peripheral 33 can.." bitfld.long 0x4 0. "IAIE32,illegal access interrupt enable for peripheral 32" "0: Illegal access event from peripheral 32 does not..,1: Illegal access event from peripheral 32 can.." line.long 0x8 "IAC_IER2,IAC interrupt enable register 2" bitfld.long 0x8 31. "IAIE95,illegal access interrupt enable for peripheral 95" "0: Illegal access event from peripheral 95 does not..,1: Illegal access event from peripheral 95 can.." bitfld.long 0x8 30. "IAIE94,illegal access interrupt enable for peripheral 94" "0: Illegal access event from peripheral 94 does not..,1: Illegal access event from peripheral 94 can.." newline bitfld.long 0x8 29. "IAIE93,illegal access interrupt enable for peripheral 93" "0: Illegal access event from peripheral 93 does not..,1: Illegal access event from peripheral 93 can.." bitfld.long 0x8 28. "IAIE92,illegal access interrupt enable for peripheral 92" "0: Illegal access event from peripheral 92 does not..,1: Illegal access event from peripheral 92 can.." newline bitfld.long 0x8 27. "IAIE91,illegal access interrupt enable for peripheral 91" "0: Illegal access event from peripheral 91 does not..,1: Illegal access event from peripheral 91 can.." bitfld.long 0x8 26. "IAIE90,illegal access interrupt enable for peripheral 90" "0: Illegal access event from peripheral 90 does not..,1: Illegal access event from peripheral 90 can.." newline bitfld.long 0x8 25. "IAIE89,illegal access interrupt enable for peripheral 89" "0: Illegal access event from peripheral 89 does not..,1: Illegal access event from peripheral 89 can.." bitfld.long 0x8 24. "IAIE88,illegal access interrupt enable for peripheral 88" "0: Illegal access event from peripheral 88 does not..,1: Illegal access event from peripheral 88 can.." newline bitfld.long 0x8 23. "IAIE87,illegal access interrupt enable for peripheral 87" "0: Illegal access event from peripheral 87 does not..,1: Illegal access event from peripheral 87 can.." bitfld.long 0x8 22. "IAIE86,illegal access interrupt enable for peripheral 86" "0: Illegal access event from peripheral 86 does not..,1: Illegal access event from peripheral 86 can.." newline bitfld.long 0x8 21. "IAIE85,illegal access interrupt enable for peripheral 85" "0: Illegal access event from peripheral 85 does not..,1: Illegal access event from peripheral 85 can.." bitfld.long 0x8 20. "IAIE84,illegal access interrupt enable for peripheral 84" "0: Illegal access event from peripheral 84 does not..,1: Illegal access event from peripheral 84 can.." newline bitfld.long 0x8 19. "IAIE83,illegal access interrupt enable for peripheral 83" "0: Illegal access event from peripheral 83 does not..,1: Illegal access event from peripheral 83 can.." bitfld.long 0x8 18. "IAIE82,illegal access interrupt enable for peripheral 82" "0: Illegal access event from peripheral 82 does not..,1: Illegal access event from peripheral 82 can.." newline bitfld.long 0x8 17. "IAIE81,illegal access interrupt enable for peripheral 81" "0: Illegal access event from peripheral 81 does not..,1: Illegal access event from peripheral 81 can.." bitfld.long 0x8 16. "IAIE80,illegal access interrupt enable for peripheral 80" "0: Illegal access event from peripheral 80 does not..,1: Illegal access event from peripheral 80 can.." newline bitfld.long 0x8 15. "IAIE79,illegal access interrupt enable for peripheral 79" "0: Illegal access event from peripheral 79 does not..,1: Illegal access event from peripheral 79 can.." bitfld.long 0x8 14. "IAIE78,illegal access interrupt enable for peripheral 78" "0: Illegal access event from peripheral 78 does not..,1: Illegal access event from peripheral 78 can.." newline bitfld.long 0x8 13. "IAIE77,illegal access interrupt enable for peripheral 77" "0: Illegal access event from peripheral 77 does not..,1: Illegal access event from peripheral 77 can.." bitfld.long 0x8 12. "IAIE76,illegal access interrupt enable for peripheral 76" "0: Illegal access event from peripheral 76 does not..,1: Illegal access event from peripheral 76 can.." newline bitfld.long 0x8 11. "IAIE75,illegal access interrupt enable for peripheral 75" "0: Illegal access event from peripheral 75 does not..,1: Illegal access event from peripheral 75 can.." bitfld.long 0x8 10. "IAIE74,illegal access interrupt enable for peripheral 74" "0: Illegal access event from peripheral 74 does not..,1: Illegal access event from peripheral 74 can.." newline bitfld.long 0x8 9. "IAIE73,illegal access interrupt enable for peripheral 73" "0: Illegal access event from peripheral 73 does not..,1: Illegal access event from peripheral 73 can.." bitfld.long 0x8 8. "IAIE72,illegal access interrupt enable for peripheral 72" "0: Illegal access event from peripheral 72 does not..,1: Illegal access event from peripheral 72 can.." newline bitfld.long 0x8 7. "IAIE71,illegal access interrupt enable for peripheral 71" "0: Illegal access event from peripheral 71 does not..,1: Illegal access event from peripheral 71 can.." bitfld.long 0x8 6. "IAIE70,illegal access interrupt enable for peripheral 70" "0: Illegal access event from peripheral 70 does not..,1: Illegal access event from peripheral 70 can.." newline bitfld.long 0x8 5. "IAIE69,illegal access interrupt enable for peripheral 69" "0: Illegal access event from peripheral 69 does not..,1: Illegal access event from peripheral 69 can.." bitfld.long 0x8 4. "IAIE68,illegal access interrupt enable for peripheral 68" "0: Illegal access event from peripheral 68 does not..,1: Illegal access event from peripheral 68 can.." newline bitfld.long 0x8 3. "IAIE67,illegal access interrupt enable for peripheral 67" "0: Illegal access event from peripheral 67 does not..,1: Illegal access event from peripheral 67 can.." bitfld.long 0x8 2. "IAIE66,illegal access interrupt enable for peripheral 66" "0: Illegal access event from peripheral 66 does not..,1: Illegal access event from peripheral 66 can.." newline bitfld.long 0x8 1. "IAIE65,illegal access interrupt enable for peripheral 65" "0: Illegal access event from peripheral 65 does not..,1: Illegal access event from peripheral 65 can.." bitfld.long 0x8 0. "IAIE64,illegal access interrupt enable for peripheral 64" "0: Illegal access event from peripheral 64 does not..,1: Illegal access event from peripheral 64 can.." line.long 0xC "IAC_IER3,IAC interrupt enable register 3" bitfld.long 0xC 31. "IAIE127,illegal access interrupt enable for peripheral 127" "0: Illegal access event from peripheral 127 does..,1: Illegal access event from peripheral 127 can.." bitfld.long 0xC 30. "IAIE126,illegal access interrupt enable for peripheral 126" "0: Illegal access event from peripheral 126 does..,1: Illegal access event from peripheral 126 can.." newline bitfld.long 0xC 29. "IAIE125,illegal access interrupt enable for peripheral 125" "0: Illegal access event from peripheral 125 does..,1: Illegal access event from peripheral 125 can.." bitfld.long 0xC 28. "IAIE124,illegal access interrupt enable for peripheral 124" "0: Illegal access event from peripheral 124 does..,1: Illegal access event from peripheral 124 can.." newline bitfld.long 0xC 27. "IAIE123,illegal access interrupt enable for peripheral 123" "0: Illegal access event from peripheral 123 does..,1: Illegal access event from peripheral 123 can.." bitfld.long 0xC 26. "IAIE122,illegal access interrupt enable for peripheral 122" "0: Illegal access event from peripheral 122 does..,1: Illegal access event from peripheral 122 can.." newline bitfld.long 0xC 25. "IAIE121,illegal access interrupt enable for peripheral 121" "0: Illegal access event from peripheral 121 does..,1: Illegal access event from peripheral 121 can.." bitfld.long 0xC 24. "IAIE120,illegal access interrupt enable for peripheral 120" "0: Illegal access event from peripheral 120 does..,1: Illegal access event from peripheral 120 can.." newline bitfld.long 0xC 23. "IAIE119,illegal access interrupt enable for peripheral 119" "0: Illegal access event from peripheral 119 does..,1: Illegal access event from peripheral 119 can.." bitfld.long 0xC 22. "IAIE118,illegal access interrupt enable for peripheral 118" "0: Illegal access event from peripheral 118 does..,1: Illegal access event from peripheral 118 can.." newline bitfld.long 0xC 21. "IAIE117,illegal access interrupt enable for peripheral 117" "0: Illegal access event from peripheral 117 does..,1: Illegal access event from peripheral 117 can.." bitfld.long 0xC 20. "IAIE116,illegal access interrupt enable for peripheral 116" "0: Illegal access event from peripheral 116 does..,1: Illegal access event from peripheral 116 can.." newline bitfld.long 0xC 19. "IAIE115,illegal access interrupt enable for peripheral 115" "0: Illegal access event from peripheral 115 does..,1: Illegal access event from peripheral 115 can.." bitfld.long 0xC 18. "IAIE114,illegal access interrupt enable for peripheral 114" "0: Illegal access event from peripheral 114 does..,1: Illegal access event from peripheral 114 can.." newline bitfld.long 0xC 17. "IAIE113,illegal access interrupt enable for peripheral 113" "0: Illegal access event from peripheral 113 does..,1: Illegal access event from peripheral 113 can.." bitfld.long 0xC 16. "IAIE112,illegal access interrupt enable for peripheral 112" "0: Illegal access event from peripheral 112 does..,1: Illegal access event from peripheral 112 can.." newline bitfld.long 0xC 15. "IAIE111,illegal access interrupt enable for peripheral 111" "0: Illegal access event from peripheral 111 does..,1: Illegal access event from peripheral 111 can.." bitfld.long 0xC 14. "IAIE110,illegal access interrupt enable for peripheral 110" "0: Illegal access event from peripheral 110 does..,1: Illegal access event from peripheral 110 can.." newline bitfld.long 0xC 13. "IAIE109,illegal access interrupt enable for peripheral 109" "0: Illegal access event from peripheral 109 does..,1: Illegal access event from peripheral 109 can.." bitfld.long 0xC 12. "IAIE108,illegal access interrupt enable for peripheral 108" "0: Illegal access event from peripheral 108 does..,1: Illegal access event from peripheral 108 can.." newline bitfld.long 0xC 11. "IAIE107,illegal access interrupt enable for peripheral 107" "0: Illegal access event from peripheral 107 does..,1: Illegal access event from peripheral 107 can.." bitfld.long 0xC 10. "IAIE106,illegal access interrupt enable for peripheral 106" "0: Illegal access event from peripheral 106 does..,1: Illegal access event from peripheral 106 can.." newline bitfld.long 0xC 9. "IAIE105,illegal access interrupt enable for peripheral 105" "0: Illegal access event from peripheral 105 does..,1: Illegal access event from peripheral 105 can.." bitfld.long 0xC 8. "IAIE104,illegal access interrupt enable for peripheral 104" "0: Illegal access event from peripheral 104 does..,1: Illegal access event from peripheral 104 can.." newline bitfld.long 0xC 7. "IAIE103,illegal access interrupt enable for peripheral 103" "0: Illegal access event from peripheral 103 does..,1: Illegal access event from peripheral 103 can.." bitfld.long 0xC 6. "IAIE102,illegal access interrupt enable for peripheral 102" "0: Illegal access event from peripheral 102 does..,1: Illegal access event from peripheral 102 can.." newline bitfld.long 0xC 5. "IAIE101,illegal access interrupt enable for peripheral 101" "0: Illegal access event from peripheral 101 does..,1: Illegal access event from peripheral 101 can.." bitfld.long 0xC 4. "IAIE100,illegal access interrupt enable for peripheral 100" "0: Illegal access event from peripheral 100 does..,1: Illegal access event from peripheral 100 can.." newline bitfld.long 0xC 3. "IAIE99,illegal access interrupt enable for peripheral 99" "0: Illegal access event from peripheral 99 does not..,1: Illegal access event from peripheral 99 can.." bitfld.long 0xC 2. "IAIE98,illegal access interrupt enable for peripheral 98" "0: Illegal access event from peripheral 98 does not..,1: Illegal access event from peripheral 98 can.." newline bitfld.long 0xC 1. "IAIE97,illegal access interrupt enable for peripheral 97" "0: Illegal access event from peripheral 97 does not..,1: Illegal access event from peripheral 97 can.." bitfld.long 0xC 0. "IAIE96,illegal access interrupt enable for peripheral 96" "0: Illegal access event from peripheral 96 does not..,1: Illegal access event from peripheral 96 can.." line.long 0x10 "IAC_IER4,IAC interrupt enable register 4" bitfld.long 0x10 31. "IAIE159,illegal access interrupt enable for peripheral 159" "0: Illegal access event from peripheral 159 does..,1: Illegal access event from peripheral 159 can.." bitfld.long 0x10 30. "IAIE158,illegal access interrupt enable for peripheral 158" "0: Illegal access event from peripheral 158 does..,1: Illegal access event from peripheral 158 can.." newline bitfld.long 0x10 29. "IAIE157,illegal access interrupt enable for peripheral 157" "0: Illegal access event from peripheral 157 does..,1: Illegal access event from peripheral 157 can.." bitfld.long 0x10 28. "IAIE156,illegal access interrupt enable for peripheral 156" "0: Illegal access event from peripheral 156 does..,1: Illegal access event from peripheral 156 can.." newline bitfld.long 0x10 27. "IAIE155,illegal access interrupt enable for peripheral 155" "0: Illegal access event from peripheral 155 does..,1: Illegal access event from peripheral 155 can.." bitfld.long 0x10 26. "IAIE154,illegal access interrupt enable for peripheral 154" "0: Illegal access event from peripheral 154 does..,1: Illegal access event from peripheral 154 can.." newline bitfld.long 0x10 25. "IAIE153,illegal access interrupt enable for peripheral 153" "0: Illegal access event from peripheral 153 does..,1: Illegal access event from peripheral 153 can.." bitfld.long 0x10 24. "IAIE152,illegal access interrupt enable for peripheral 152" "0: Illegal access event from peripheral 152 does..,1: Illegal access event from peripheral 152 can.." newline bitfld.long 0x10 23. "IAIE151,illegal access interrupt enable for peripheral 151" "0: Illegal access event from peripheral 151 does..,1: Illegal access event from peripheral 151 can.." bitfld.long 0x10 22. "IAIE150,illegal access interrupt enable for peripheral 150" "0: Illegal access event from peripheral 150 does..,1: Illegal access event from peripheral 150 can.." newline bitfld.long 0x10 21. "IAIE149,illegal access interrupt enable for peripheral 149" "0: Illegal access event from peripheral 149 does..,1: Illegal access event from peripheral 149 can.." bitfld.long 0x10 20. "IAIE148,illegal access interrupt enable for peripheral 148" "0: Illegal access event from peripheral 148 does..,1: Illegal access event from peripheral 148 can.." newline bitfld.long 0x10 19. "IAIE147,illegal access interrupt enable for peripheral 147" "0: Illegal access event from peripheral 147 does..,1: Illegal access event from peripheral 147 can.." bitfld.long 0x10 18. "IAIE146,illegal access interrupt enable for peripheral 146" "0: Illegal access event from peripheral 146 does..,1: Illegal access event from peripheral 146 can.." newline bitfld.long 0x10 17. "IAIE145,illegal access interrupt enable for peripheral 145" "0: Illegal access event from peripheral 145 does..,1: Illegal access event from peripheral 145 can.." bitfld.long 0x10 16. "IAIE144,illegal access interrupt enable for peripheral 144" "0: Illegal access event from peripheral 144 does..,1: Illegal access event from peripheral 144 can.." newline bitfld.long 0x10 15. "IAIE143,illegal access interrupt enable for peripheral 143" "0: Illegal access event from peripheral 143 does..,1: Illegal access event from peripheral 143 can.." bitfld.long 0x10 14. "IAIE142,illegal access interrupt enable for peripheral 142" "0: Illegal access event from peripheral 142 does..,1: Illegal access event from peripheral 142 can.." newline bitfld.long 0x10 13. "IAIE141,illegal access interrupt enable for peripheral 141" "0: Illegal access event from peripheral 141 does..,1: Illegal access event from peripheral 141 can.." bitfld.long 0x10 12. "IAIE140,illegal access interrupt enable for peripheral 140" "0: Illegal access event from peripheral 140 does..,1: Illegal access event from peripheral 140 can.." newline bitfld.long 0x10 11. "IAIE139,illegal access interrupt enable for peripheral 139" "0: Illegal access event from peripheral 139 does..,1: Illegal access event from peripheral 139 can.." bitfld.long 0x10 10. "IAIE138,illegal access interrupt enable for peripheral 138" "0: Illegal access event from peripheral 138 does..,1: Illegal access event from peripheral 138 can.." newline bitfld.long 0x10 9. "IAIE137,illegal access interrupt enable for peripheral 137" "0: Illegal access event from peripheral 137 does..,1: Illegal access event from peripheral 137 can.." bitfld.long 0x10 8. "IAIE136,illegal access interrupt enable for peripheral 136" "0: Illegal access event from peripheral 136 does..,1: Illegal access event from peripheral 136 can.." newline bitfld.long 0x10 7. "IAIE135,illegal access interrupt enable for peripheral 135" "0: Illegal access event from peripheral 135 does..,1: Illegal access event from peripheral 135 can.." bitfld.long 0x10 6. "IAIE134,illegal access interrupt enable for peripheral 134" "0: Illegal access event from peripheral 134 does..,1: Illegal access event from peripheral 134 can.." newline bitfld.long 0x10 5. "IAIE133,illegal access interrupt enable for peripheral 133" "0: Illegal access event from peripheral 133 does..,1: Illegal access event from peripheral 133 can.." bitfld.long 0x10 4. "IAIE132,illegal access interrupt enable for peripheral 132" "0: Illegal access event from peripheral 132 does..,1: Illegal access event from peripheral 132 can.." newline bitfld.long 0x10 3. "IAIE131,illegal access interrupt enable for peripheral 131" "0: Illegal access event from peripheral 131 does..,1: Illegal access event from peripheral 131 can.." bitfld.long 0x10 2. "IAIE130,illegal access interrupt enable for peripheral 130" "0: Illegal access event from peripheral 130 does..,1: Illegal access event from peripheral 130 can.." newline bitfld.long 0x10 1. "IAIE129,illegal access interrupt enable for peripheral 129" "0: Illegal access event from peripheral 129 does..,1: Illegal access event from peripheral 129 can.." bitfld.long 0x10 0. "IAIE128,illegal access interrupt enable for peripheral 128" "0: Illegal access event from peripheral 128 does..,1: Illegal access event from peripheral 128 can.." line.long 0x14 "IAC_IER5,IAC interrupt enable register 5" bitfld.long 0x14 31. "IAIE191,illegal access interrupt enable for peripheral 191" "0: Illegal access event from peripheral 191 does..,1: Illegal access event from peripheral 191 can.." bitfld.long 0x14 30. "IAIE190,illegal access interrupt enable for peripheral 190" "0: Illegal access event from peripheral 190 does..,1: Illegal access event from peripheral 190 can.." newline bitfld.long 0x14 29. "IAIE189,illegal access interrupt enable for peripheral 189" "0: Illegal access event from peripheral 189 does..,1: Illegal access event from peripheral 189 can.." bitfld.long 0x14 28. "IAIE188,illegal access interrupt enable for peripheral 188" "0: Illegal access event from peripheral 188 does..,1: Illegal access event from peripheral 188 can.." newline bitfld.long 0x14 27. "IAIE187,illegal access interrupt enable for peripheral 187" "0: Illegal access event from peripheral 187 does..,1: Illegal access event from peripheral 187 can.." bitfld.long 0x14 26. "IAIE186,illegal access interrupt enable for peripheral 186" "0: Illegal access event from peripheral 186 does..,1: Illegal access event from peripheral 186 can.." newline bitfld.long 0x14 25. "IAIE185,illegal access interrupt enable for peripheral 185" "0: Illegal access event from peripheral 185 does..,1: Illegal access event from peripheral 185 can.." bitfld.long 0x14 24. "IAIE184,illegal access interrupt enable for peripheral 184" "0: Illegal access event from peripheral 184 does..,1: Illegal access event from peripheral 184 can.." newline bitfld.long 0x14 23. "IAIE183,illegal access interrupt enable for peripheral 183" "0: Illegal access event from peripheral 183 does..,1: Illegal access event from peripheral 183 can.." bitfld.long 0x14 22. "IAIE182,illegal access interrupt enable for peripheral 182" "0: Illegal access event from peripheral 182 does..,1: Illegal access event from peripheral 182 can.." newline bitfld.long 0x14 21. "IAIE181,illegal access interrupt enable for peripheral 181" "0: Illegal access event from peripheral 181 does..,1: Illegal access event from peripheral 181 can.." bitfld.long 0x14 20. "IAIE180,illegal access interrupt enable for peripheral 180" "0: Illegal access event from peripheral 180 does..,1: Illegal access event from peripheral 180 can.." newline bitfld.long 0x14 19. "IAIE179,illegal access interrupt enable for peripheral 179" "0: Illegal access event from peripheral 179 does..,1: Illegal access event from peripheral 179 can.." bitfld.long 0x14 18. "IAIE178,illegal access interrupt enable for peripheral 178" "0: Illegal access event from peripheral 178 does..,1: Illegal access event from peripheral 178 can.." newline bitfld.long 0x14 17. "IAIE177,illegal access interrupt enable for peripheral 177" "0: Illegal access event from peripheral 177 does..,1: Illegal access event from peripheral 177 can.." bitfld.long 0x14 16. "IAIE176,illegal access interrupt enable for peripheral 176" "0: Illegal access event from peripheral 176 does..,1: Illegal access event from peripheral 176 can.." newline bitfld.long 0x14 15. "IAIE175,illegal access interrupt enable for peripheral 175" "0: Illegal access event from peripheral 175 does..,1: Illegal access event from peripheral 175 can.." bitfld.long 0x14 14. "IAIE174,illegal access interrupt enable for peripheral 174" "0: Illegal access event from peripheral 174 does..,1: Illegal access event from peripheral 174 can.." newline bitfld.long 0x14 13. "IAIE173,illegal access interrupt enable for peripheral 173" "0: Illegal access event from peripheral 173 does..,1: Illegal access event from peripheral 173 can.." bitfld.long 0x14 12. "IAIE172,illegal access interrupt enable for peripheral 172" "0: Illegal access event from peripheral 172 does..,1: Illegal access event from peripheral 172 can.." newline bitfld.long 0x14 11. "IAIE171,illegal access interrupt enable for peripheral 171" "0: Illegal access event from peripheral 171 does..,1: Illegal access event from peripheral 171 can.." bitfld.long 0x14 10. "IAIE170,illegal access interrupt enable for peripheral 170" "0: Illegal access event from peripheral 170 does..,1: Illegal access event from peripheral 170 can.." newline bitfld.long 0x14 9. "IAIE169,illegal access interrupt enable for peripheral 169" "0: Illegal access event from peripheral 169 does..,1: Illegal access event from peripheral 169 can.." bitfld.long 0x14 8. "IAIE168,illegal access interrupt enable for peripheral 168" "0: Illegal access event from peripheral 168 does..,1: Illegal access event from peripheral 168 can.." newline bitfld.long 0x14 7. "IAIE167,illegal access interrupt enable for peripheral 167" "0: Illegal access event from peripheral 167 does..,1: Illegal access event from peripheral 167 can.." bitfld.long 0x14 6. "IAIE166,illegal access interrupt enable for peripheral 166" "0: Illegal access event from peripheral 166 does..,1: Illegal access event from peripheral 166 can.." newline bitfld.long 0x14 5. "IAIE165,illegal access interrupt enable for peripheral 165" "0: Illegal access event from peripheral 165 does..,1: Illegal access event from peripheral 165 can.." bitfld.long 0x14 4. "IAIE164,illegal access interrupt enable for peripheral 164" "0: Illegal access event from peripheral 164 does..,1: Illegal access event from peripheral 164 can.." newline bitfld.long 0x14 3. "IAIE163,illegal access interrupt enable for peripheral 163" "0: Illegal access event from peripheral 163 does..,1: Illegal access event from peripheral 163 can.." bitfld.long 0x14 2. "IAIE162,illegal access interrupt enable for peripheral 162" "0: Illegal access event from peripheral 162 does..,1: Illegal access event from peripheral 162 can.." newline bitfld.long 0x14 1. "IAIE161,illegal access interrupt enable for peripheral 161" "0: Illegal access event from peripheral 161 does..,1: Illegal access event from peripheral 161 can.." bitfld.long 0x14 0. "IAIE160,illegal access interrupt enable for peripheral 160" "0: Illegal access event from peripheral 160 does..,1: Illegal access event from peripheral 160 can.." rgroup.long 0x80++0x17 line.long 0x0 "IAC_ISR0,IAC interrupt status register 0" bitfld.long 0x0 31. "IAF31,illegal access interrupt enable for peripheral 31" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 30. "IAF30,illegal access interrupt enable for peripheral 30" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 29. "IAF29,illegal access interrupt enable for peripheral 29" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 28. "IAF28,illegal access interrupt enable for peripheral 28" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 27. "IAF27,illegal access interrupt enable for peripheral 27" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 26. "IAF26,illegal access interrupt enable for peripheral 26" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 25. "IAF25,illegal access interrupt enable for peripheral 25" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 24. "IAF24,illegal access interrupt enable for peripheral 24" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 23. "IAF23,illegal access interrupt enable for peripheral 23" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 22. "IAF22,illegal access interrupt enable for peripheral 22" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 21. "IAF21,illegal access interrupt enable for peripheral 21" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 20. "IAF20,illegal access interrupt enable for peripheral 20" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 19. "IAF19,illegal access interrupt enable for peripheral 19" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 18. "IAF18,illegal access interrupt enable for peripheral 18" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 17. "IAF17,illegal access interrupt enable for peripheral 17" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 16. "IAF16,illegal access interrupt enable for peripheral 16" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 15. "IAF15,illegal access interrupt enable for peripheral 15" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 14. "IAF14,illegal access interrupt enable for peripheral 14" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 13. "IAF13,illegal access interrupt enable for peripheral 13" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 12. "IAF12,illegal access interrupt enable for peripheral 12" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 11. "IAF11,illegal access interrupt enable for peripheral 11" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 10. "IAF10,illegal access interrupt enable for peripheral 10" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 9. "IAF9,illegal access interrupt enable for peripheral 9" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 8. "IAF8,illegal access interrupt enable for peripheral 8" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 7. "IAF7,illegal access interrupt enable for peripheral 7" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 6. "IAF6,illegal access interrupt enable for peripheral 6" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 5. "IAF5,illegal access interrupt enable for peripheral 5" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 4. "IAF4,illegal access interrupt enable for peripheral 4" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 3. "IAF3,illegal access interrupt enable for peripheral 3" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 2. "IAF2,illegal access interrupt enable for peripheral 2" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x0 1. "IAF1,illegal access interrupt enable for peripheral 1" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x0 0. "IAF0,illegal access interrupt enable for peripheral 0" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." line.long 0x4 "IAC_ISR1,IAC interrupt status register 1" bitfld.long 0x4 31. "IAF63,illegal access interrupt enable for peripheral 63" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 30. "IAF62,illegal access interrupt enable for peripheral 62" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 29. "IAF61,illegal access interrupt enable for peripheral 61" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 28. "IAF60,illegal access interrupt enable for peripheral 60" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 27. "IAF59,illegal access interrupt enable for peripheral 59" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 26. "IAF58,illegal access interrupt enable for peripheral 58" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 25. "IAF57,illegal access interrupt enable for peripheral 57" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 24. "IAF56,illegal access interrupt enable for peripheral 56" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 23. "IAF55,illegal access interrupt enable for peripheral 55" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 22. "IAF54,illegal access interrupt enable for peripheral 54" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 21. "IAF53,illegal access interrupt enable for peripheral 53" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 20. "IAF52,illegal access interrupt enable for peripheral 52" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 19. "IAF51,illegal access interrupt enable for peripheral 51" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 18. "IAF50,illegal access interrupt enable for peripheral 50" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 17. "IAF49,illegal access interrupt enable for peripheral 49" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 16. "IAF48,illegal access interrupt enable for peripheral 48" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 15. "IAF47,illegal access interrupt enable for peripheral 47" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 14. "IAF46,illegal access interrupt enable for peripheral 46" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 13. "IAF45,illegal access interrupt enable for peripheral 45" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 12. "IAF44,illegal access interrupt enable for peripheral 44" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 11. "IAF43,illegal access interrupt enable for peripheral 43" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 10. "IAF42,illegal access interrupt enable for peripheral 42" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 9. "IAF41,illegal access interrupt enable for peripheral 41" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 8. "IAF40,illegal access interrupt enable for peripheral 40" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 7. "IAF39,illegal access interrupt enable for peripheral 39" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 6. "IAF38,illegal access interrupt enable for peripheral 38" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 5. "IAF37,illegal access interrupt enable for peripheral 37" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 4. "IAF36,illegal access interrupt enable for peripheral 36" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 3. "IAF35,illegal access interrupt enable for peripheral 35" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 2. "IAF34,illegal access interrupt enable for peripheral 34" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x4 1. "IAF33,illegal access interrupt enable for peripheral 33" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x4 0. "IAF32,illegal access interrupt enable for peripheral 32" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." line.long 0x8 "IAC_ISR2,IAC interrupt status register 2" bitfld.long 0x8 31. "IAF95,illegal access interrupt enable for peripheral 95" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 30. "IAF94,illegal access interrupt enable for peripheral 94" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 29. "IAF93,illegal access interrupt enable for peripheral 93" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 28. "IAF92,illegal access interrupt enable for peripheral 92" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 27. "IAF91,illegal access interrupt enable for peripheral 91" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 26. "IAF90,illegal access interrupt enable for peripheral 90" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 25. "IAF89,illegal access interrupt enable for peripheral 89" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 24. "IAF88,illegal access interrupt enable for peripheral 88" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 23. "IAF87,illegal access interrupt enable for peripheral 87" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 22. "IAF86,illegal access interrupt enable for peripheral 86" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 21. "IAF85,illegal access interrupt enable for peripheral 85" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 20. "IAF84,illegal access interrupt enable for peripheral 84" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 19. "IAF83,illegal access interrupt enable for peripheral 83" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 18. "IAF82,illegal access interrupt enable for peripheral 82" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 17. "IAF81,illegal access interrupt enable for peripheral 81" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 16. "IAF80,illegal access interrupt enable for peripheral 80" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 15. "IAF79,illegal access interrupt enable for peripheral 79" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 14. "IAF78,illegal access interrupt enable for peripheral 78" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 13. "IAF77,illegal access interrupt enable for peripheral 77" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 12. "IAF76,illegal access interrupt enable for peripheral 76" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 11. "IAF75,illegal access interrupt enable for peripheral 75" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 10. "IAF74,illegal access interrupt enable for peripheral 74" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 9. "IAF73,illegal access interrupt enable for peripheral 73" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 8. "IAF72,illegal access interrupt enable for peripheral 72" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 7. "IAF71,illegal access interrupt enable for peripheral 71" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 6. "IAF70,illegal access interrupt enable for peripheral 70" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 5. "IAF69,illegal access interrupt enable for peripheral 69" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 4. "IAF68,illegal access interrupt enable for peripheral 68" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 3. "IAF67,illegal access interrupt enable for peripheral 67" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 2. "IAF66,illegal access interrupt enable for peripheral 66" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x8 1. "IAF65,illegal access interrupt enable for peripheral 65" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x8 0. "IAF64,illegal access interrupt enable for peripheral 64" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." line.long 0xC "IAC_ISR3,IAC interrupt status register 3" bitfld.long 0xC 31. "IAF127,illegal access interrupt enable for peripheral 127" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 30. "IAF126,illegal access interrupt enable for peripheral 126" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 29. "IAF125,illegal access interrupt enable for peripheral 125" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 28. "IAF124,illegal access interrupt enable for peripheral 124" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 27. "IAF123,illegal access interrupt enable for peripheral 123" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 26. "IAF122,illegal access interrupt enable for peripheral 122" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 25. "IAF121,illegal access interrupt enable for peripheral 121" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 24. "IAF120,illegal access interrupt enable for peripheral 120" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 23. "IAF119,illegal access interrupt enable for peripheral 119" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 22. "IAF118,illegal access interrupt enable for peripheral 118" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 21. "IAF117,illegal access interrupt enable for peripheral 117" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 20. "IAF116,illegal access interrupt enable for peripheral 116" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 19. "IAF115,illegal access interrupt enable for peripheral 115" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 18. "IAF114,illegal access interrupt enable for peripheral 114" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 17. "IAF113,illegal access interrupt enable for peripheral 113" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 16. "IAF112,illegal access interrupt enable for peripheral 112" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 15. "IAF111,illegal access interrupt enable for peripheral 111" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 14. "IAF110,illegal access interrupt enable for peripheral 110" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 13. "IAF109,illegal access interrupt enable for peripheral 109" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 12. "IAF108,illegal access interrupt enable for peripheral 108" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 11. "IAF107,illegal access interrupt enable for peripheral 107" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 10. "IAF106,illegal access interrupt enable for peripheral 106" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 9. "IAF105,illegal access interrupt enable for peripheral 105" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 8. "IAF104,illegal access interrupt enable for peripheral 104" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 7. "IAF103,illegal access interrupt enable for peripheral 103" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 6. "IAF102,illegal access interrupt enable for peripheral 102" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 5. "IAF101,illegal access interrupt enable for peripheral 101" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 4. "IAF100,illegal access interrupt enable for peripheral 100" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 3. "IAF99,illegal access interrupt enable for peripheral 99" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 2. "IAF98,illegal access interrupt enable for peripheral 98" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0xC 1. "IAF97,illegal access interrupt enable for peripheral 97" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0xC 0. "IAF96,illegal access interrupt enable for peripheral 96" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." line.long 0x10 "IAC_ISR4,IAC interrupt status register 4" bitfld.long 0x10 31. "IAF159,illegal access interrupt enable for peripheral 159" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 30. "IAF158,illegal access interrupt enable for peripheral 158" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 29. "IAF157,illegal access interrupt enable for peripheral 157" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 28. "IAF156,illegal access interrupt enable for peripheral 156" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 27. "IAF155,illegal access interrupt enable for peripheral 155" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 26. "IAF154,illegal access interrupt enable for peripheral 154" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 25. "IAF153,illegal access interrupt enable for peripheral 153" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 24. "IAF152,illegal access interrupt enable for peripheral 152" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 23. "IAF151,illegal access interrupt enable for peripheral 151" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 22. "IAF150,illegal access interrupt enable for peripheral 150" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 21. "IAF149,illegal access interrupt enable for peripheral 149" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 20. "IAF148,illegal access interrupt enable for peripheral 148" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 19. "IAF147,illegal access interrupt enable for peripheral 147" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 18. "IAF146,illegal access interrupt enable for peripheral 146" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 17. "IAF145,illegal access interrupt enable for peripheral 145" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 16. "IAF144,illegal access interrupt enable for peripheral 144" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 15. "IAF143,illegal access interrupt enable for peripheral 143" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 14. "IAF142,illegal access interrupt enable for peripheral 142" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 13. "IAF141,illegal access interrupt enable for peripheral 141" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 12. "IAF140,illegal access interrupt enable for peripheral 140" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 11. "IAF139,illegal access interrupt enable for peripheral 139" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 10. "IAF138,illegal access interrupt enable for peripheral 138" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 9. "IAF137,illegal access interrupt enable for peripheral 137" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 8. "IAF136,illegal access interrupt enable for peripheral 136" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 7. "IAF135,illegal access interrupt enable for peripheral 135" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 6. "IAF134,illegal access interrupt enable for peripheral 134" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 5. "IAF133,illegal access interrupt enable for peripheral 133" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 4. "IAF132,illegal access interrupt enable for peripheral 132" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 3. "IAF131,illegal access interrupt enable for peripheral 131" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 2. "IAF130,illegal access interrupt enable for peripheral 130" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x10 1. "IAF129,illegal access interrupt enable for peripheral 129" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x10 0. "IAF128,illegal access interrupt enable for peripheral 128" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." line.long 0x14 "IAC_ISR5,IAC interrupt status register 5" bitfld.long 0x14 31. "IAF191,illegal access interrupt enable for peripheral 191" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 30. "IAF190,illegal access interrupt enable for peripheral 190" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 29. "IAF189,illegal access interrupt enable for peripheral 189" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 28. "IAF188,illegal access interrupt enable for peripheral 188" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 27. "IAF187,illegal access interrupt enable for peripheral 187" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 26. "IAF186,illegal access interrupt enable for peripheral 186" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 25. "IAF185,illegal access interrupt enable for peripheral 185" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 24. "IAF184,illegal access interrupt enable for peripheral 184" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 23. "IAF183,illegal access interrupt enable for peripheral 183" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 22. "IAF182,illegal access interrupt enable for peripheral 182" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 21. "IAF181,illegal access interrupt enable for peripheral 181" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 20. "IAF180,illegal access interrupt enable for peripheral 180" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 19. "IAF179,illegal access interrupt enable for peripheral 179" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 18. "IAF178,illegal access interrupt enable for peripheral 178" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 17. "IAF177,illegal access interrupt enable for peripheral 177" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 16. "IAF176,illegal access interrupt enable for peripheral 176" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 15. "IAF175,illegal access interrupt enable for peripheral 175" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 14. "IAF174,illegal access interrupt enable for peripheral 174" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 13. "IAF173,illegal access interrupt enable for peripheral 173" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 12. "IAF172,illegal access interrupt enable for peripheral 172" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 11. "IAF171,illegal access interrupt enable for peripheral 171" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 10. "IAF170,illegal access interrupt enable for peripheral 170" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 9. "IAF169,illegal access interrupt enable for peripheral 169" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 8. "IAF168,illegal access interrupt enable for peripheral 168" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 7. "IAF167,illegal access interrupt enable for peripheral 167" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 6. "IAF166,illegal access interrupt enable for peripheral 166" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 5. "IAF165,illegal access interrupt enable for peripheral 165" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 4. "IAF164,illegal access interrupt enable for peripheral 164" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 3. "IAF163,illegal access interrupt enable for peripheral 163" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 2. "IAF162,illegal access interrupt enable for peripheral 162" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." newline bitfld.long 0x14 1. "IAF161,illegal access interrupt enable for peripheral 161" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." bitfld.long 0x14 0. "IAF160,illegal access interrupt enable for peripheral 160" "0: No illegal access event detected for peripheral..,1: At least one illegal access event has been.." wgroup.long 0x100++0x17 line.long 0x0 "IAC_ICR0,IAC interrupt clear register 0" bitfld.long 0x0 31. "IAF31,illegal access flag clear for peripheral 31" "0: IAF 31 flag status not affected,1: IAF 31 flag status cleared in IAC_ISRx" bitfld.long 0x0 30. "IAF30,illegal access flag clear for peripheral 30" "0: IAF 30 flag status not affected,1: IAF 30 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 29. "IAF29,illegal access flag clear for peripheral 29" "0: IAF 29 flag status not affected,1: IAF 29 flag status cleared in IAC_ISRx" bitfld.long 0x0 28. "IAF28,illegal access flag clear for peripheral 28" "0: IAF 28 flag status not affected,1: IAF 28 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 27. "IAF27,illegal access flag clear for peripheral 27" "0: IAF 27 flag status not affected,1: IAF 27 flag status cleared in IAC_ISRx" bitfld.long 0x0 26. "IAF26,illegal access flag clear for peripheral 26" "0: IAF 26 flag status not affected,1: IAF 26 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 25. "IAF25,illegal access flag clear for peripheral 25" "0: IAF 25 flag status not affected,1: IAF 25 flag status cleared in IAC_ISRx" bitfld.long 0x0 24. "IAF24,illegal access flag clear for peripheral 24" "0: IAF 24 flag status not affected,1: IAF 24 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 23. "IAF23,illegal access flag clear for peripheral 23" "0: IAF 23 flag status not affected,1: IAF 23 flag status cleared in IAC_ISRx" bitfld.long 0x0 22. "IAF22,illegal access flag clear for peripheral 22" "0: IAF 22 flag status not affected,1: IAF 22 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 21. "IAF21,illegal access flag clear for peripheral 21" "0: IAF 21 flag status not affected,1: IAF 21 flag status cleared in IAC_ISRx" bitfld.long 0x0 20. "IAF20,illegal access flag clear for peripheral 20" "0: IAF 20 flag status not affected,1: IAF 20 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 19. "IAF19,illegal access flag clear for peripheral 19" "0: IAF 19 flag status not affected,1: IAF 19 flag status cleared in IAC_ISRx" bitfld.long 0x0 18. "IAF18,illegal access flag clear for peripheral 18" "0: IAF 18 flag status not affected,1: IAF 18 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 17. "IAF17,illegal access flag clear for peripheral 17" "0: IAF 17 flag status not affected,1: IAF 17 flag status cleared in IAC_ISRx" bitfld.long 0x0 16. "IAF16,illegal access flag clear for peripheral 16" "0: IAF 16 flag status not affected,1: IAF 16 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 15. "IAF15,illegal access flag clear for peripheral 15" "0: IAF 15 flag status not affected,1: IAF 15 flag status cleared in IAC_ISRx" bitfld.long 0x0 14. "IAF14,illegal access flag clear for peripheral 14" "0: IAF 14 flag status not affected,1: IAF 14 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 13. "IAF13,illegal access flag clear for peripheral 13" "0: IAF 13 flag status not affected,1: IAF 13 flag status cleared in IAC_ISRx" bitfld.long 0x0 12. "IAF12,illegal access flag clear for peripheral 12" "0: IAF 12 flag status not affected,1: IAF 12 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 11. "IAF11,illegal access flag clear for peripheral 11" "0: IAF 11 flag status not affected,1: IAF 11 flag status cleared in IAC_ISRx" bitfld.long 0x0 10. "IAF10,illegal access flag clear for peripheral 10" "0: IAF 10 flag status not affected,1: IAF 10 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 9. "IAF9,illegal access flag clear for peripheral 9" "0: IAF 9 flag status not affected,1: IAF 9 flag status cleared in IAC_ISRx" bitfld.long 0x0 8. "IAF8,illegal access flag clear for peripheral 8" "0: IAF 8 flag status not affected,1: IAF 8 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 7. "IAF7,illegal access flag clear for peripheral 7" "0: IAF 7 flag status not affected,1: IAF 7 flag status cleared in IAC_ISRx" bitfld.long 0x0 6. "IAF6,illegal access flag clear for peripheral 6" "0: IAF 6 flag status not affected,1: IAF 6 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 5. "IAF5,illegal access flag clear for peripheral 5" "0: IAF 5 flag status not affected,1: IAF 5 flag status cleared in IAC_ISRx" bitfld.long 0x0 4. "IAF4,illegal access flag clear for peripheral 4" "0: IAF 4 flag status not affected,1: IAF 4 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 3. "IAF3,illegal access flag clear for peripheral 3" "0: IAF 3 flag status not affected,1: IAF 3 flag status cleared in IAC_ISRx" bitfld.long 0x0 2. "IAF2,illegal access flag clear for peripheral 2" "0: IAF 2 flag status not affected,1: IAF 2 flag status cleared in IAC_ISRx" newline bitfld.long 0x0 1. "IAF1,illegal access flag clear for peripheral 1" "0: IAF 1 flag status not affected,1: IAF 1 flag status cleared in IAC_ISRx" bitfld.long 0x0 0. "IAF0,illegal access flag clear for peripheral 0" "0: IAF 0 flag status not affected,1: IAF 0 flag status cleared in IAC_ISRx" line.long 0x4 "IAC_ICR1,IAC interrupt clear register 1" bitfld.long 0x4 31. "IAF63,illegal access flag clear for peripheral 63" "0: IAF 63 flag status not affected,1: IAF 63 flag status cleared in IAC_ISRx" bitfld.long 0x4 30. "IAF62,illegal access flag clear for peripheral 62" "0: IAF 62 flag status not affected,1: IAF 62 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 29. "IAF61,illegal access flag clear for peripheral 61" "0: IAF 61 flag status not affected,1: IAF 61 flag status cleared in IAC_ISRx" bitfld.long 0x4 28. "IAF60,illegal access flag clear for peripheral 60" "0: IAF 60 flag status not affected,1: IAF 60 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 27. "IAF59,illegal access flag clear for peripheral 59" "0: IAF 59 flag status not affected,1: IAF 59 flag status cleared in IAC_ISRx" bitfld.long 0x4 26. "IAF58,illegal access flag clear for peripheral 58" "0: IAF 58 flag status not affected,1: IAF 58 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 25. "IAF57,illegal access flag clear for peripheral 57" "0: IAF 57 flag status not affected,1: IAF 57 flag status cleared in IAC_ISRx" bitfld.long 0x4 24. "IAF56,illegal access flag clear for peripheral 56" "0: IAF 56 flag status not affected,1: IAF 56 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 23. "IAF55,illegal access flag clear for peripheral 55" "0: IAF 55 flag status not affected,1: IAF 55 flag status cleared in IAC_ISRx" bitfld.long 0x4 22. "IAF54,illegal access flag clear for peripheral 54" "0: IAF 54 flag status not affected,1: IAF 54 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 21. "IAF53,illegal access flag clear for peripheral 53" "0: IAF 53 flag status not affected,1: IAF 53 flag status cleared in IAC_ISRx" bitfld.long 0x4 20. "IAF52,illegal access flag clear for peripheral 52" "0: IAF 52 flag status not affected,1: IAF 52 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 19. "IAF51,illegal access flag clear for peripheral 51" "0: IAF 51 flag status not affected,1: IAF 51 flag status cleared in IAC_ISRx" bitfld.long 0x4 18. "IAF50,illegal access flag clear for peripheral 50" "0: IAF 50 flag status not affected,1: IAF 50 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 17. "IAF49,illegal access flag clear for peripheral 49" "0: IAF 49 flag status not affected,1: IAF 49 flag status cleared in IAC_ISRx" bitfld.long 0x4 16. "IAF48,illegal access flag clear for peripheral 48" "0: IAF 48 flag status not affected,1: IAF 48 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 15. "IAF47,illegal access flag clear for peripheral 47" "0: IAF 47 flag status not affected,1: IAF 47 flag status cleared in IAC_ISRx" bitfld.long 0x4 14. "IAF46,illegal access flag clear for peripheral 46" "0: IAF 46 flag status not affected,1: IAF 46 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 13. "IAF45,illegal access flag clear for peripheral 45" "0: IAF 45 flag status not affected,1: IAF 45 flag status cleared in IAC_ISRx" bitfld.long 0x4 12. "IAF44,illegal access flag clear for peripheral 44" "0: IAF 44 flag status not affected,1: IAF 44 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 11. "IAF43,illegal access flag clear for peripheral 43" "0: IAF 43 flag status not affected,1: IAF 43 flag status cleared in IAC_ISRx" bitfld.long 0x4 10. "IAF42,illegal access flag clear for peripheral 42" "0: IAF 42 flag status not affected,1: IAF 42 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 9. "IAF41,illegal access flag clear for peripheral 41" "0: IAF 41 flag status not affected,1: IAF 41 flag status cleared in IAC_ISRx" bitfld.long 0x4 8. "IAF40,illegal access flag clear for peripheral 40" "0: IAF 40 flag status not affected,1: IAF 40 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 7. "IAF39,illegal access flag clear for peripheral 39" "0: IAF 39 flag status not affected,1: IAF 39 flag status cleared in IAC_ISRx" bitfld.long 0x4 6. "IAF38,illegal access flag clear for peripheral 38" "0: IAF 38 flag status not affected,1: IAF 38 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 5. "IAF37,illegal access flag clear for peripheral 37" "0: IAF 37 flag status not affected,1: IAF 37 flag status cleared in IAC_ISRx" bitfld.long 0x4 4. "IAF36,illegal access flag clear for peripheral 36" "0: IAF 36 flag status not affected,1: IAF 36 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 3. "IAF35,illegal access flag clear for peripheral 35" "0: IAF 35 flag status not affected,1: IAF 35 flag status cleared in IAC_ISRx" bitfld.long 0x4 2. "IAF34,illegal access flag clear for peripheral 34" "0: IAF 34 flag status not affected,1: IAF 34 flag status cleared in IAC_ISRx" newline bitfld.long 0x4 1. "IAF33,illegal access flag clear for peripheral 33" "0: IAF 33 flag status not affected,1: IAF 33 flag status cleared in IAC_ISRx" bitfld.long 0x4 0. "IAF32,illegal access flag clear for peripheral 32" "0: IAF 32 flag status not affected,1: IAF 32 flag status cleared in IAC_ISRx" line.long 0x8 "IAC_ICR2,IAC interrupt clear register 2" bitfld.long 0x8 31. "IAF95,illegal access flag clear for peripheral 95" "0: IAF 95 flag status not affected,1: IAF 95 flag status cleared in IAC_ISRx" bitfld.long 0x8 30. "IAF94,illegal access flag clear for peripheral 94" "0: IAF 94 flag status not affected,1: IAF 94 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 29. "IAF93,illegal access flag clear for peripheral 93" "0: IAF 93 flag status not affected,1: IAF 93 flag status cleared in IAC_ISRx" bitfld.long 0x8 28. "IAF92,illegal access flag clear for peripheral 92" "0: IAF 92 flag status not affected,1: IAF 92 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 27. "IAF91,illegal access flag clear for peripheral 91" "0: IAF 91 flag status not affected,1: IAF 91 flag status cleared in IAC_ISRx" bitfld.long 0x8 26. "IAF90,illegal access flag clear for peripheral 90" "0: IAF 90 flag status not affected,1: IAF 90 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 25. "IAF89,illegal access flag clear for peripheral 89" "0: IAF 89 flag status not affected,1: IAF 89 flag status cleared in IAC_ISRx" bitfld.long 0x8 24. "IAF88,illegal access flag clear for peripheral 88" "0: IAF 88 flag status not affected,1: IAF 88 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 23. "IAF87,illegal access flag clear for peripheral 87" "0: IAF 87 flag status not affected,1: IAF 87 flag status cleared in IAC_ISRx" bitfld.long 0x8 22. "IAF86,illegal access flag clear for peripheral 86" "0: IAF 86 flag status not affected,1: IAF 86 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 21. "IAF85,illegal access flag clear for peripheral 85" "0: IAF 85 flag status not affected,1: IAF 85 flag status cleared in IAC_ISRx" bitfld.long 0x8 20. "IAF84,illegal access flag clear for peripheral 84" "0: IAF 84 flag status not affected,1: IAF 84 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 19. "IAF83,illegal access flag clear for peripheral 83" "0: IAF 83 flag status not affected,1: IAF 83 flag status cleared in IAC_ISRx" bitfld.long 0x8 18. "IAF82,illegal access flag clear for peripheral 82" "0: IAF 82 flag status not affected,1: IAF 82 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 17. "IAF81,illegal access flag clear for peripheral 81" "0: IAF 81 flag status not affected,1: IAF 81 flag status cleared in IAC_ISRx" bitfld.long 0x8 16. "IAF80,illegal access flag clear for peripheral 80" "0: IAF 80 flag status not affected,1: IAF 80 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 15. "IAF79,illegal access flag clear for peripheral 79" "0: IAF 79 flag status not affected,1: IAF 79 flag status cleared in IAC_ISRx" bitfld.long 0x8 14. "IAF78,illegal access flag clear for peripheral 78" "0: IAF 78 flag status not affected,1: IAF 78 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 13. "IAF77,illegal access flag clear for peripheral 77" "0: IAF 77 flag status not affected,1: IAF 77 flag status cleared in IAC_ISRx" bitfld.long 0x8 12. "IAF76,illegal access flag clear for peripheral 76" "0: IAF 76 flag status not affected,1: IAF 76 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 11. "IAF75,illegal access flag clear for peripheral 75" "0: IAF 75 flag status not affected,1: IAF 75 flag status cleared in IAC_ISRx" bitfld.long 0x8 10. "IAF74,illegal access flag clear for peripheral 74" "0: IAF 74 flag status not affected,1: IAF 74 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 9. "IAF73,illegal access flag clear for peripheral 73" "0: IAF 73 flag status not affected,1: IAF 73 flag status cleared in IAC_ISRx" bitfld.long 0x8 8. "IAF72,illegal access flag clear for peripheral 72" "0: IAF 72 flag status not affected,1: IAF 72 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 7. "IAF71,illegal access flag clear for peripheral 71" "0: IAF 71 flag status not affected,1: IAF 71 flag status cleared in IAC_ISRx" bitfld.long 0x8 6. "IAF70,illegal access flag clear for peripheral 70" "0: IAF 70 flag status not affected,1: IAF 70 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 5. "IAF69,illegal access flag clear for peripheral 69" "0: IAF 69 flag status not affected,1: IAF 69 flag status cleared in IAC_ISRx" bitfld.long 0x8 4. "IAF68,illegal access flag clear for peripheral 68" "0: IAF 68 flag status not affected,1: IAF 68 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 3. "IAF67,illegal access flag clear for peripheral 67" "0: IAF 67 flag status not affected,1: IAF 67 flag status cleared in IAC_ISRx" bitfld.long 0x8 2. "IAF66,illegal access flag clear for peripheral 66" "0: IAF 66 flag status not affected,1: IAF 66 flag status cleared in IAC_ISRx" newline bitfld.long 0x8 1. "IAF65,illegal access flag clear for peripheral 65" "0: IAF 65 flag status not affected,1: IAF 65 flag status cleared in IAC_ISRx" bitfld.long 0x8 0. "IAF64,illegal access flag clear for peripheral 64" "0: IAF 64 flag status not affected,1: IAF 64 flag status cleared in IAC_ISRx" line.long 0xC "IAC_ICR3,IAC interrupt clear register 3" bitfld.long 0xC 31. "IAF127,illegal access flag clear for peripheral 127" "0: IAF 127 flag status not affected,1: IAF 127 flag status cleared in IAC_ISRx" bitfld.long 0xC 30. "IAF126,illegal access flag clear for peripheral 126" "0: IAF 126 flag status not affected,1: IAF 126 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 29. "IAF125,illegal access flag clear for peripheral 125" "0: IAF 125 flag status not affected,1: IAF 125 flag status cleared in IAC_ISRx" bitfld.long 0xC 28. "IAF124,illegal access flag clear for peripheral 124" "0: IAF 124 flag status not affected,1: IAF 124 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 27. "IAF123,illegal access flag clear for peripheral 123" "0: IAF 123 flag status not affected,1: IAF 123 flag status cleared in IAC_ISRx" bitfld.long 0xC 26. "IAF122,illegal access flag clear for peripheral 122" "0: IAF 122 flag status not affected,1: IAF 122 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 25. "IAF121,illegal access flag clear for peripheral 121" "0: IAF 121 flag status not affected,1: IAF 121 flag status cleared in IAC_ISRx" bitfld.long 0xC 24. "IAF120,illegal access flag clear for peripheral 120" "0: IAF 120 flag status not affected,1: IAF 120 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 23. "IAF119,illegal access flag clear for peripheral 119" "0: IAF 119 flag status not affected,1: IAF 119 flag status cleared in IAC_ISRx" bitfld.long 0xC 22. "IAF118,illegal access flag clear for peripheral 118" "0: IAF 118 flag status not affected,1: IAF 118 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 21. "IAF117,illegal access flag clear for peripheral 117" "0: IAF 117 flag status not affected,1: IAF 117 flag status cleared in IAC_ISRx" bitfld.long 0xC 20. "IAF116,illegal access flag clear for peripheral 116" "0: IAF 116 flag status not affected,1: IAF 116 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 19. "IAF115,illegal access flag clear for peripheral 115" "0: IAF 115 flag status not affected,1: IAF 115 flag status cleared in IAC_ISRx" bitfld.long 0xC 18. "IAF114,illegal access flag clear for peripheral 114" "0: IAF 114 flag status not affected,1: IAF 114 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 17. "IAF113,illegal access flag clear for peripheral 113" "0: IAF 113 flag status not affected,1: IAF 113 flag status cleared in IAC_ISRx" bitfld.long 0xC 16. "IAF112,illegal access flag clear for peripheral 112" "0: IAF 112 flag status not affected,1: IAF 112 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 15. "IAF111,illegal access flag clear for peripheral 111" "0: IAF 111 flag status not affected,1: IAF 111 flag status cleared in IAC_ISRx" bitfld.long 0xC 14. "IAF110,illegal access flag clear for peripheral 110" "0: IAF 110 flag status not affected,1: IAF 110 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 13. "IAF109,illegal access flag clear for peripheral 109" "0: IAF 109 flag status not affected,1: IAF 109 flag status cleared in IAC_ISRx" bitfld.long 0xC 12. "IAF108,illegal access flag clear for peripheral 108" "0: IAF 108 flag status not affected,1: IAF 108 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 11. "IAF107,illegal access flag clear for peripheral 107" "0: IAF 107 flag status not affected,1: IAF 107 flag status cleared in IAC_ISRx" bitfld.long 0xC 10. "IAF106,illegal access flag clear for peripheral 106" "0: IAF 106 flag status not affected,1: IAF 106 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 9. "IAF105,illegal access flag clear for peripheral 105" "0: IAF 105 flag status not affected,1: IAF 105 flag status cleared in IAC_ISRx" bitfld.long 0xC 8. "IAF104,illegal access flag clear for peripheral 104" "0: IAF 104 flag status not affected,1: IAF 104 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 7. "IAF103,illegal access flag clear for peripheral 103" "0: IAF 103 flag status not affected,1: IAF 103 flag status cleared in IAC_ISRx" bitfld.long 0xC 6. "IAF102,illegal access flag clear for peripheral 102" "0: IAF 102 flag status not affected,1: IAF 102 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 5. "IAF101,illegal access flag clear for peripheral 101" "0: IAF 101 flag status not affected,1: IAF 101 flag status cleared in IAC_ISRx" bitfld.long 0xC 4. "IAF100,illegal access flag clear for peripheral 100" "0: IAF 100 flag status not affected,1: IAF 100 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 3. "IAF99,illegal access flag clear for peripheral 99" "0: IAF 99 flag status not affected,1: IAF 99 flag status cleared in IAC_ISRx" bitfld.long 0xC 2. "IAF98,illegal access flag clear for peripheral 98" "0: IAF 98 flag status not affected,1: IAF 98 flag status cleared in IAC_ISRx" newline bitfld.long 0xC 1. "IAF97,illegal access flag clear for peripheral 97" "0: IAF 97 flag status not affected,1: IAF 97 flag status cleared in IAC_ISRx" bitfld.long 0xC 0. "IAF96,illegal access flag clear for peripheral 96" "0: IAF 96 flag status not affected,1: IAF 96 flag status cleared in IAC_ISRx" line.long 0x10 "IAC_ICR4,IAC interrupt clear register 4" bitfld.long 0x10 31. "IAF159,illegal access flag clear for peripheral 159" "0: IAF 159 flag status not affected,1: IAF 159 flag status cleared in IAC_ISRx" bitfld.long 0x10 30. "IAF158,illegal access flag clear for peripheral 158" "0: IAF 158 flag status not affected,1: IAF 158 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 29. "IAF157,illegal access flag clear for peripheral 157" "0: IAF 157 flag status not affected,1: IAF 157 flag status cleared in IAC_ISRx" bitfld.long 0x10 28. "IAF156,illegal access flag clear for peripheral 156" "0: IAF 156 flag status not affected,1: IAF 156 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 27. "IAF155,illegal access flag clear for peripheral 155" "0: IAF 155 flag status not affected,1: IAF 155 flag status cleared in IAC_ISRx" bitfld.long 0x10 26. "IAF154,illegal access flag clear for peripheral 154" "0: IAF 154 flag status not affected,1: IAF 154 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 25. "IAF153,illegal access flag clear for peripheral 153" "0: IAF 153 flag status not affected,1: IAF 153 flag status cleared in IAC_ISRx" bitfld.long 0x10 24. "IAF152,illegal access flag clear for peripheral 152" "0: IAF 152 flag status not affected,1: IAF 152 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 23. "IAF151,illegal access flag clear for peripheral 151" "0: IAF 151 flag status not affected,1: IAF 151 flag status cleared in IAC_ISRx" bitfld.long 0x10 22. "IAF150,illegal access flag clear for peripheral 150" "0: IAF 150 flag status not affected,1: IAF 150 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 21. "IAF149,illegal access flag clear for peripheral 149" "0: IAF 149 flag status not affected,1: IAF 149 flag status cleared in IAC_ISRx" bitfld.long 0x10 20. "IAF148,illegal access flag clear for peripheral 148" "0: IAF 148 flag status not affected,1: IAF 148 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 19. "IAF147,illegal access flag clear for peripheral 147" "0: IAF 147 flag status not affected,1: IAF 147 flag status cleared in IAC_ISRx" bitfld.long 0x10 18. "IAF146,illegal access flag clear for peripheral 146" "0: IAF 146 flag status not affected,1: IAF 146 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 17. "IAF145,illegal access flag clear for peripheral 145" "0: IAF 145 flag status not affected,1: IAF 145 flag status cleared in IAC_ISRx" bitfld.long 0x10 16. "IAF144,illegal access flag clear for peripheral 144" "0: IAF 144 flag status not affected,1: IAF 144 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 15. "IAF143,illegal access flag clear for peripheral 143" "0: IAF 143 flag status not affected,1: IAF 143 flag status cleared in IAC_ISRx" bitfld.long 0x10 14. "IAF142,illegal access flag clear for peripheral 142" "0: IAF 142 flag status not affected,1: IAF 142 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 13. "IAF141,illegal access flag clear for peripheral 141" "0: IAF 141 flag status not affected,1: IAF 141 flag status cleared in IAC_ISRx" bitfld.long 0x10 12. "IAF140,illegal access flag clear for peripheral 140" "0: IAF 140 flag status not affected,1: IAF 140 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 11. "IAF139,illegal access flag clear for peripheral 139" "0: IAF 139 flag status not affected,1: IAF 139 flag status cleared in IAC_ISRx" bitfld.long 0x10 10. "IAF138,illegal access flag clear for peripheral 138" "0: IAF 138 flag status not affected,1: IAF 138 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 9. "IAF137,illegal access flag clear for peripheral 137" "0: IAF 137 flag status not affected,1: IAF 137 flag status cleared in IAC_ISRx" bitfld.long 0x10 8. "IAF136,illegal access flag clear for peripheral 136" "0: IAF 136 flag status not affected,1: IAF 136 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 7. "IAF135,illegal access flag clear for peripheral 135" "0: IAF 135 flag status not affected,1: IAF 135 flag status cleared in IAC_ISRx" bitfld.long 0x10 6. "IAF134,illegal access flag clear for peripheral 134" "0: IAF 134 flag status not affected,1: IAF 134 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 5. "IAF133,illegal access flag clear for peripheral 133" "0: IAF 133 flag status not affected,1: IAF 133 flag status cleared in IAC_ISRx" bitfld.long 0x10 4. "IAF132,illegal access flag clear for peripheral 132" "0: IAF 132 flag status not affected,1: IAF 132 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 3. "IAF131,illegal access flag clear for peripheral 131" "0: IAF 131 flag status not affected,1: IAF 131 flag status cleared in IAC_ISRx" bitfld.long 0x10 2. "IAF130,illegal access flag clear for peripheral 130" "0: IAF 130 flag status not affected,1: IAF 130 flag status cleared in IAC_ISRx" newline bitfld.long 0x10 1. "IAF129,illegal access flag clear for peripheral 129" "0: IAF 129 flag status not affected,1: IAF 129 flag status cleared in IAC_ISRx" bitfld.long 0x10 0. "IAF128,illegal access flag clear for peripheral 128" "0: IAF 128 flag status not affected,1: IAF 128 flag status cleared in IAC_ISRx" line.long 0x14 "IAC_ICR5,IAC interrupt clear register 5" bitfld.long 0x14 31. "IAF191,illegal access flag clear for peripheral 191" "0: IAF 191 flag status not affected,1: IAF 191 flag status cleared in IAC_ISRx" bitfld.long 0x14 30. "IAF190,illegal access flag clear for peripheral 190" "0: IAF 190 flag status not affected,1: IAF 190 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 29. "IAF189,illegal access flag clear for peripheral 189" "0: IAF 189 flag status not affected,1: IAF 189 flag status cleared in IAC_ISRx" bitfld.long 0x14 28. "IAF188,illegal access flag clear for peripheral 188" "0: IAF 188 flag status not affected,1: IAF 188 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 27. "IAF187,illegal access flag clear for peripheral 187" "0: IAF 187 flag status not affected,1: IAF 187 flag status cleared in IAC_ISRx" bitfld.long 0x14 26. "IAF186,illegal access flag clear for peripheral 186" "0: IAF 186 flag status not affected,1: IAF 186 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 25. "IAF185,illegal access flag clear for peripheral 185" "0: IAF 185 flag status not affected,1: IAF 185 flag status cleared in IAC_ISRx" bitfld.long 0x14 24. "IAF184,illegal access flag clear for peripheral 184" "0: IAF 184 flag status not affected,1: IAF 184 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 23. "IAF183,illegal access flag clear for peripheral 183" "0: IAF 183 flag status not affected,1: IAF 183 flag status cleared in IAC_ISRx" bitfld.long 0x14 22. "IAF182,illegal access flag clear for peripheral 182" "0: IAF 182 flag status not affected,1: IAF 182 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 21. "IAF181,illegal access flag clear for peripheral 181" "0: IAF 181 flag status not affected,1: IAF 181 flag status cleared in IAC_ISRx" bitfld.long 0x14 20. "IAF180,illegal access flag clear for peripheral 180" "0: IAF 180 flag status not affected,1: IAF 180 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 19. "IAF179,illegal access flag clear for peripheral 179" "0: IAF 179 flag status not affected,1: IAF 179 flag status cleared in IAC_ISRx" bitfld.long 0x14 18. "IAF178,illegal access flag clear for peripheral 178" "0: IAF 178 flag status not affected,1: IAF 178 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 17. "IAF177,illegal access flag clear for peripheral 177" "0: IAF 177 flag status not affected,1: IAF 177 flag status cleared in IAC_ISRx" bitfld.long 0x14 16. "IAF176,illegal access flag clear for peripheral 176" "0: IAF 176 flag status not affected,1: IAF 176 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 15. "IAF175,illegal access flag clear for peripheral 175" "0: IAF 175 flag status not affected,1: IAF 175 flag status cleared in IAC_ISRx" bitfld.long 0x14 14. "IAF174,illegal access flag clear for peripheral 174" "0: IAF 174 flag status not affected,1: IAF 174 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 13. "IAF173,illegal access flag clear for peripheral 173" "0: IAF 173 flag status not affected,1: IAF 173 flag status cleared in IAC_ISRx" bitfld.long 0x14 12. "IAF172,illegal access flag clear for peripheral 172" "0: IAF 172 flag status not affected,1: IAF 172 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 11. "IAF171,illegal access flag clear for peripheral 171" "0: IAF 171 flag status not affected,1: IAF 171 flag status cleared in IAC_ISRx" bitfld.long 0x14 10. "IAF170,illegal access flag clear for peripheral 170" "0: IAF 170 flag status not affected,1: IAF 170 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 9. "IAF169,illegal access flag clear for peripheral 169" "0: IAF 169 flag status not affected,1: IAF 169 flag status cleared in IAC_ISRx" bitfld.long 0x14 8. "IAF168,illegal access flag clear for peripheral 168" "0: IAF 168 flag status not affected,1: IAF 168 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 7. "IAF167,illegal access flag clear for peripheral 167" "0: IAF 167 flag status not affected,1: IAF 167 flag status cleared in IAC_ISRx" bitfld.long 0x14 6. "IAF166,illegal access flag clear for peripheral 166" "0: IAF 166 flag status not affected,1: IAF 166 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 5. "IAF165,illegal access flag clear for peripheral 165" "0: IAF 165 flag status not affected,1: IAF 165 flag status cleared in IAC_ISRx" bitfld.long 0x14 4. "IAF164,illegal access flag clear for peripheral 164" "0: IAF 164 flag status not affected,1: IAF 164 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 3. "IAF163,illegal access flag clear for peripheral 163" "0: IAF 163 flag status not affected,1: IAF 163 flag status cleared in IAC_ISRx" bitfld.long 0x14 2. "IAF162,illegal access flag clear for peripheral 162" "0: IAF 162 flag status not affected,1: IAF 162 flag status cleared in IAC_ISRx" newline bitfld.long 0x14 1. "IAF161,illegal access flag clear for peripheral 161" "0: IAF 161 flag status not affected,1: IAF 161 flag status cleared in IAC_ISRx" bitfld.long 0x14 0. "IAF160,illegal access flag clear for peripheral 160" "0: IAF 160 flag status not affected,1: IAF 160 flag status cleared in IAC_ISRx" rgroup.long 0x36C++0x13 line.long 0x0 "IAC_IISR0,IAC ILAC input status register 0" bitfld.long 0x0 31. "ILACIN31,illegal access input 31" "0: ILAC input 31 to IAC not present,1: ILAC input 31 to IAC present" bitfld.long 0x0 30. "ILACIN30,illegal access input 30" "0: ILAC input 30 to IAC not present,1: ILAC input 30 to IAC present" newline bitfld.long 0x0 29. "ILACIN29,illegal access input 29" "0: ILAC input 29 to IAC not present,1: ILAC input 29 to IAC present" bitfld.long 0x0 28. "ILACIN28,illegal access input 28" "0: ILAC input 28 to IAC not present,1: ILAC input 28 to IAC present" newline bitfld.long 0x0 27. "ILACIN27,illegal access input 27" "0: ILAC input 27 to IAC not present,1: ILAC input 27 to IAC present" bitfld.long 0x0 26. "ILACIN26,illegal access input 26" "0: ILAC input 26 to IAC not present,1: ILAC input 26 to IAC present" newline bitfld.long 0x0 25. "ILACIN25,illegal access input 25" "0: ILAC input 25 to IAC not present,1: ILAC input 25 to IAC present" bitfld.long 0x0 24. "ILACIN24,illegal access input 24" "0: ILAC input 24 to IAC not present,1: ILAC input 24 to IAC present" newline bitfld.long 0x0 23. "ILACIN23,illegal access input 23" "0: ILAC input 23 to IAC not present,1: ILAC input 23 to IAC present" bitfld.long 0x0 22. "ILACIN22,illegal access input 22" "0: ILAC input 22 to IAC not present,1: ILAC input 22 to IAC present" newline bitfld.long 0x0 21. "ILACIN21,illegal access input 21" "0: ILAC input 21 to IAC not present,1: ILAC input 21 to IAC present" bitfld.long 0x0 20. "ILACIN20,illegal access input 20" "0: ILAC input 20 to IAC not present,1: ILAC input 20 to IAC present" newline bitfld.long 0x0 19. "ILACIN19,illegal access input 19" "0: ILAC input 19 to IAC not present,1: ILAC input 19 to IAC present" bitfld.long 0x0 18. "ILACIN18,illegal access input 18" "0: ILAC input 18 to IAC not present,1: ILAC input 18 to IAC present" newline bitfld.long 0x0 17. "ILACIN17,illegal access input 17" "0: ILAC input 17 to IAC not present,1: ILAC input 17 to IAC present" bitfld.long 0x0 16. "ILACIN16,illegal access input 16" "0: ILAC input 16 to IAC not present,1: ILAC input 16 to IAC present" newline bitfld.long 0x0 15. "ILACIN15,illegal access input 15" "0: ILAC input 15 to IAC not present,1: ILAC input 15 to IAC present" bitfld.long 0x0 14. "ILACIN14,illegal access input 14" "0: ILAC input 14 to IAC not present,1: ILAC input 14 to IAC present" newline bitfld.long 0x0 13. "ILACIN13,illegal access input 13" "0: ILAC input 13 to IAC not present,1: ILAC input 13 to IAC present" bitfld.long 0x0 12. "ILACIN12,illegal access input 12" "0: ILAC input 12 to IAC not present,1: ILAC input 12 to IAC present" newline bitfld.long 0x0 11. "ILACIN11,illegal access input 11" "0: ILAC input 11 to IAC not present,1: ILAC input 11 to IAC present" bitfld.long 0x0 10. "ILACIN10,illegal access input 10" "0: ILAC input 10 to IAC not present,1: ILAC input 10 to IAC present" newline bitfld.long 0x0 9. "ILACIN9,illegal access input 9" "0: ILAC input 9 to IAC not present,1: ILAC input 9 to IAC present" bitfld.long 0x0 8. "ILACIN8,illegal access input 8" "0: ILAC input 8 to IAC not present,1: ILAC input 8 to IAC present" newline bitfld.long 0x0 7. "ILACIN7,illegal access input 7" "0: ILAC input 7 to IAC not present,1: ILAC input 7 to IAC present" bitfld.long 0x0 6. "ILACIN6,illegal access input 6" "0: ILAC input 6 to IAC not present,1: ILAC input 6 to IAC present" newline bitfld.long 0x0 5. "ILACIN5,illegal access input 5" "0: ILAC input 5 to IAC not present,1: ILAC input 5 to IAC present" bitfld.long 0x0 4. "ILACIN4,illegal access input 4" "0: ILAC input 4 to IAC not present,1: ILAC input 4 to IAC present" newline bitfld.long 0x0 3. "ILACIN3,illegal access input 3" "0: ILAC input 3 to IAC not present,1: ILAC input 3 to IAC present" bitfld.long 0x0 2. "ILACIN2,illegal access input 2" "0: ILAC input 2 to IAC not present,1: ILAC input 2 to IAC present" newline bitfld.long 0x0 1. "ILACIN1,illegal access input 1" "0: ILAC input 1 to IAC not present,1: ILAC input 1 to IAC present" bitfld.long 0x0 0. "ILACIN0,illegal access input 0" "0: ILAC input 0 to IAC not present,1: ILAC input 0 to IAC present" line.long 0x4 "IAC_IISR1,IAC ILAC input status register 1" bitfld.long 0x4 31. "ILACIN63,illegal access input 63" "0: ILAC input 63 to IAC not present,1: ILAC input 63 to IAC present" bitfld.long 0x4 30. "ILACIN62,illegal access input 62" "0: ILAC input 62 to IAC not present,1: ILAC input 62 to IAC present" newline bitfld.long 0x4 29. "ILACIN61,illegal access input 61" "0: ILAC input 61 to IAC not present,1: ILAC input 61 to IAC present" bitfld.long 0x4 28. "ILACIN60,illegal access input 60" "0: ILAC input 60 to IAC not present,1: ILAC input 60 to IAC present" newline bitfld.long 0x4 27. "ILACIN59,illegal access input 59" "0: ILAC input 59 to IAC not present,1: ILAC input 59 to IAC present" bitfld.long 0x4 26. "ILACIN58,illegal access input 58" "0: ILAC input 58 to IAC not present,1: ILAC input 58 to IAC present" newline bitfld.long 0x4 25. "ILACIN57,illegal access input 57" "0: ILAC input 57 to IAC not present,1: ILAC input 57 to IAC present" bitfld.long 0x4 24. "ILACIN56,illegal access input 56" "0: ILAC input 56 to IAC not present,1: ILAC input 56 to IAC present" newline bitfld.long 0x4 23. "ILACIN55,illegal access input 55" "0: ILAC input 55 to IAC not present,1: ILAC input 55 to IAC present" bitfld.long 0x4 22. "ILACIN54,illegal access input 54" "0: ILAC input 54 to IAC not present,1: ILAC input 54 to IAC present" newline bitfld.long 0x4 21. "ILACIN53,illegal access input 53" "0: ILAC input 53 to IAC not present,1: ILAC input 53 to IAC present" bitfld.long 0x4 20. "ILACIN52,illegal access input 52" "0: ILAC input 52 to IAC not present,1: ILAC input 52 to IAC present" newline bitfld.long 0x4 19. "ILACIN51,illegal access input 51" "0: ILAC input 51 to IAC not present,1: ILAC input 51 to IAC present" bitfld.long 0x4 18. "ILACIN50,illegal access input 50" "0: ILAC input 50 to IAC not present,1: ILAC input 50 to IAC present" newline bitfld.long 0x4 17. "ILACIN49,illegal access input 49" "0: ILAC input 49 to IAC not present,1: ILAC input 49 to IAC present" bitfld.long 0x4 16. "ILACIN48,illegal access input 48" "0: ILAC input 48 to IAC not present,1: ILAC input 48 to IAC present" newline bitfld.long 0x4 15. "ILACIN47,illegal access input 47" "0: ILAC input 47 to IAC not present,1: ILAC input 47 to IAC present" bitfld.long 0x4 14. "ILACIN46,illegal access input 46" "0: ILAC input 46 to IAC not present,1: ILAC input 46 to IAC present" newline bitfld.long 0x4 13. "ILACIN45,illegal access input 45" "0: ILAC input 45 to IAC not present,1: ILAC input 45 to IAC present" bitfld.long 0x4 12. "ILACIN44,illegal access input 44" "0: ILAC input 44 to IAC not present,1: ILAC input 44 to IAC present" newline bitfld.long 0x4 11. "ILACIN43,illegal access input 43" "0: ILAC input 43 to IAC not present,1: ILAC input 43 to IAC present" bitfld.long 0x4 10. "ILACIN42,illegal access input 42" "0: ILAC input 42 to IAC not present,1: ILAC input 42 to IAC present" newline bitfld.long 0x4 9. "ILACIN41,illegal access input 41" "0: ILAC input 41 to IAC not present,1: ILAC input 41 to IAC present" bitfld.long 0x4 8. "ILACIN40,illegal access input 40" "0: ILAC input 40 to IAC not present,1: ILAC input 40 to IAC present" newline bitfld.long 0x4 7. "ILACIN39,illegal access input 39" "0: ILAC input 39 to IAC not present,1: ILAC input 39 to IAC present" bitfld.long 0x4 6. "ILACIN38,illegal access input 38" "0: ILAC input 38 to IAC not present,1: ILAC input 38 to IAC present" newline bitfld.long 0x4 5. "ILACIN37,illegal access input 37" "0: ILAC input 37 to IAC not present,1: ILAC input 37 to IAC present" bitfld.long 0x4 4. "ILACIN36,illegal access input 36" "0: ILAC input 36 to IAC not present,1: ILAC input 36 to IAC present" newline bitfld.long 0x4 3. "ILACIN35,illegal access input 35" "0: ILAC input 35 to IAC not present,1: ILAC input 35 to IAC present" bitfld.long 0x4 2. "ILACIN34,illegal access input 34" "0: ILAC input 34 to IAC not present,1: ILAC input 34 to IAC present" newline bitfld.long 0x4 1. "ILACIN33,illegal access input 33" "0: ILAC input 33 to IAC not present,1: ILAC input 33 to IAC present" bitfld.long 0x4 0. "ILACIN32,illegal access input 32" "0: ILAC input 32 to IAC not present,1: ILAC input 32 to IAC present" line.long 0x8 "IAC_IISR2,IAC ILAC input status register 2" bitfld.long 0x8 31. "ILACIN95,illegal access input 95" "0: ILAC input 95 to IAC not present,1: ILAC input 95 to IAC present" bitfld.long 0x8 30. "ILACIN94,illegal access input 94" "0: ILAC input 94 to IAC not present,1: ILAC input 94 to IAC present" newline bitfld.long 0x8 29. "ILACIN93,illegal access input 93" "0: ILAC input 93 to IAC not present,1: ILAC input 93 to IAC present" bitfld.long 0x8 28. "ILACIN92,illegal access input 92" "0: ILAC input 92 to IAC not present,1: ILAC input 92 to IAC present" newline bitfld.long 0x8 27. "ILACIN91,illegal access input 91" "0: ILAC input 91 to IAC not present,1: ILAC input 91 to IAC present" bitfld.long 0x8 26. "ILACIN90,illegal access input 90" "0: ILAC input 90 to IAC not present,1: ILAC input 90 to IAC present" newline bitfld.long 0x8 25. "ILACIN89,illegal access input 89" "0: ILAC input 89 to IAC not present,1: ILAC input 89 to IAC present" bitfld.long 0x8 24. "ILACIN88,illegal access input 88" "0: ILAC input 88 to IAC not present,1: ILAC input 88 to IAC present" newline bitfld.long 0x8 23. "ILACIN87,illegal access input 87" "0: ILAC input 87 to IAC not present,1: ILAC input 87 to IAC present" bitfld.long 0x8 22. "ILACIN86,illegal access input 86" "0: ILAC input 86 to IAC not present,1: ILAC input 86 to IAC present" newline bitfld.long 0x8 21. "ILACIN85,illegal access input 85" "0: ILAC input 85 to IAC not present,1: ILAC input 85 to IAC present" bitfld.long 0x8 20. "ILACIN84,illegal access input 84" "0: ILAC input 84 to IAC not present,1: ILAC input 84 to IAC present" newline bitfld.long 0x8 19. "ILACIN83,illegal access input 83" "0: ILAC input 83 to IAC not present,1: ILAC input 83 to IAC present" bitfld.long 0x8 18. "ILACIN82,illegal access input 82" "0: ILAC input 82 to IAC not present,1: ILAC input 82 to IAC present" newline bitfld.long 0x8 17. "ILACIN81,illegal access input 81" "0: ILAC input 81 to IAC not present,1: ILAC input 81 to IAC present" bitfld.long 0x8 16. "ILACIN80,illegal access input 80" "0: ILAC input 80 to IAC not present,1: ILAC input 80 to IAC present" newline bitfld.long 0x8 15. "ILACIN79,illegal access input 79" "0: ILAC input 79 to IAC not present,1: ILAC input 79 to IAC present" bitfld.long 0x8 14. "ILACIN78,illegal access input 78" "0: ILAC input 78 to IAC not present,1: ILAC input 78 to IAC present" newline bitfld.long 0x8 13. "ILACIN77,illegal access input 77" "0: ILAC input 77 to IAC not present,1: ILAC input 77 to IAC present" bitfld.long 0x8 12. "ILACIN76,illegal access input 76" "0: ILAC input 76 to IAC not present,1: ILAC input 76 to IAC present" newline bitfld.long 0x8 11. "ILACIN75,illegal access input 75" "0: ILAC input 75 to IAC not present,1: ILAC input 75 to IAC present" bitfld.long 0x8 10. "ILACIN74,illegal access input 74" "0: ILAC input 74 to IAC not present,1: ILAC input 74 to IAC present" newline bitfld.long 0x8 9. "ILACIN73,illegal access input 73" "0: ILAC input 73 to IAC not present,1: ILAC input 73 to IAC present" bitfld.long 0x8 8. "ILACIN72,illegal access input 72" "0: ILAC input 72 to IAC not present,1: ILAC input 72 to IAC present" newline bitfld.long 0x8 7. "ILACIN71,illegal access input 71" "0: ILAC input 71 to IAC not present,1: ILAC input 71 to IAC present" bitfld.long 0x8 6. "ILACIN70,illegal access input 70" "0: ILAC input 70 to IAC not present,1: ILAC input 70 to IAC present" newline bitfld.long 0x8 5. "ILACIN69,illegal access input 69" "0: ILAC input 69 to IAC not present,1: ILAC input 69 to IAC present" bitfld.long 0x8 4. "ILACIN68,illegal access input 68" "0: ILAC input 68 to IAC not present,1: ILAC input 68 to IAC present" newline bitfld.long 0x8 3. "ILACIN67,illegal access input 67" "0: ILAC input 67 to IAC not present,1: ILAC input 67 to IAC present" bitfld.long 0x8 2. "ILACIN66,illegal access input 66" "0: ILAC input 66 to IAC not present,1: ILAC input 66 to IAC present" newline bitfld.long 0x8 1. "ILACIN65,illegal access input 65" "0: ILAC input 65 to IAC not present,1: ILAC input 65 to IAC present" bitfld.long 0x8 0. "ILACIN64,illegal access input 64" "0: ILAC input 64 to IAC not present,1: ILAC input 64 to IAC present" line.long 0xC "IAC_IISR3,IAC ILAC input status register 3" bitfld.long 0xC 31. "ILACIN127,illegal access input 127" "0: ILAC input 127 to IAC not present,1: ILAC input 127 to IAC present" bitfld.long 0xC 30. "ILACIN126,illegal access input 126" "0: ILAC input 126 to IAC not present,1: ILAC input 126 to IAC present" newline bitfld.long 0xC 29. "ILACIN125,illegal access input 125" "0: ILAC input 125 to IAC not present,1: ILAC input 125 to IAC present" bitfld.long 0xC 28. "ILACIN124,illegal access input 124" "0: ILAC input 124 to IAC not present,1: ILAC input 124 to IAC present" newline bitfld.long 0xC 27. "ILACIN123,illegal access input 123" "0: ILAC input 123 to IAC not present,1: ILAC input 123 to IAC present" bitfld.long 0xC 26. "ILACIN122,illegal access input 122" "0: ILAC input 122 to IAC not present,1: ILAC input 122 to IAC present" newline bitfld.long 0xC 25. "ILACIN121,illegal access input 121" "0: ILAC input 121 to IAC not present,1: ILAC input 121 to IAC present" bitfld.long 0xC 24. "ILACIN120,illegal access input 120" "0: ILAC input 120 to IAC not present,1: ILAC input 120 to IAC present" newline bitfld.long 0xC 23. "ILACIN119,illegal access input 119" "0: ILAC input 119 to IAC not present,1: ILAC input 119 to IAC present" bitfld.long 0xC 22. "ILACIN118,illegal access input 118" "0: ILAC input 118 to IAC not present,1: ILAC input 118 to IAC present" newline bitfld.long 0xC 21. "ILACIN117,illegal access input 117" "0: ILAC input 117 to IAC not present,1: ILAC input 117 to IAC present" bitfld.long 0xC 20. "ILACIN116,illegal access input 116" "0: ILAC input 116 to IAC not present,1: ILAC input 116 to IAC present" newline bitfld.long 0xC 19. "ILACIN115,illegal access input 115" "0: ILAC input 115 to IAC not present,1: ILAC input 115 to IAC present" bitfld.long 0xC 18. "ILACIN114,illegal access input 114" "0: ILAC input 114 to IAC not present,1: ILAC input 114 to IAC present" newline bitfld.long 0xC 17. "ILACIN113,illegal access input 113" "0: ILAC input 113 to IAC not present,1: ILAC input 113 to IAC present" bitfld.long 0xC 16. "ILACIN112,illegal access input 112" "0: ILAC input 112 to IAC not present,1: ILAC input 112 to IAC present" newline bitfld.long 0xC 15. "ILACIN111,illegal access input 111" "0: ILAC input 111 to IAC not present,1: ILAC input 111 to IAC present" bitfld.long 0xC 14. "ILACIN110,illegal access input 110" "0: ILAC input 110 to IAC not present,1: ILAC input 110 to IAC present" newline bitfld.long 0xC 13. "ILACIN109,illegal access input 109" "0: ILAC input 109 to IAC not present,1: ILAC input 109 to IAC present" bitfld.long 0xC 12. "ILACIN108,illegal access input 108" "0: ILAC input 108 to IAC not present,1: ILAC input 108 to IAC present" newline bitfld.long 0xC 11. "ILACIN107,illegal access input 107" "0: ILAC input 107 to IAC not present,1: ILAC input 107 to IAC present" bitfld.long 0xC 10. "ILACIN106,illegal access input 106" "0: ILAC input 106 to IAC not present,1: ILAC input 106 to IAC present" newline bitfld.long 0xC 9. "ILACIN105,illegal access input 105" "0: ILAC input 105 to IAC not present,1: ILAC input 105 to IAC present" bitfld.long 0xC 8. "ILACIN104,illegal access input 104" "0: ILAC input 104 to IAC not present,1: ILAC input 104 to IAC present" newline bitfld.long 0xC 7. "ILACIN103,illegal access input 103" "0: ILAC input 103 to IAC not present,1: ILAC input 103 to IAC present" bitfld.long 0xC 6. "ILACIN102,illegal access input 102" "0: ILAC input 102 to IAC not present,1: ILAC input 102 to IAC present" newline bitfld.long 0xC 5. "ILACIN101,illegal access input 101" "0: ILAC input 101 to IAC not present,1: ILAC input 101 to IAC present" bitfld.long 0xC 4. "ILACIN100,illegal access input 100" "0: ILAC input 100 to IAC not present,1: ILAC input 100 to IAC present" newline bitfld.long 0xC 3. "ILACIN99,illegal access input 99" "0: ILAC input 99 to IAC not present,1: ILAC input 99 to IAC present" bitfld.long 0xC 2. "ILACIN98,illegal access input 98" "0: ILAC input 98 to IAC not present,1: ILAC input 98 to IAC present" newline bitfld.long 0xC 1. "ILACIN97,illegal access input 97" "0: ILAC input 97 to IAC not present,1: ILAC input 97 to IAC present" bitfld.long 0xC 0. "ILACIN96,illegal access input 96" "0: ILAC input 96 to IAC not present,1: ILAC input 96 to IAC present" line.long 0x10 "IAC_IISR4,IAC ILAC input status register 4" bitfld.long 0x10 31. "ILACIN159,illegal access input 159" "0: ILAC input 159 to IAC not present,1: ILAC input 159 to IAC present" bitfld.long 0x10 30. "ILACIN158,illegal access input 158" "0: ILAC input 158 to IAC not present,1: ILAC input 158 to IAC present" newline bitfld.long 0x10 29. "ILACIN157,illegal access input 157" "0: ILAC input 157 to IAC not present,1: ILAC input 157 to IAC present" bitfld.long 0x10 28. "ILACIN156,illegal access input 156" "0: ILAC input 156 to IAC not present,1: ILAC input 156 to IAC present" newline bitfld.long 0x10 27. "ILACIN155,illegal access input 155" "0: ILAC input 155 to IAC not present,1: ILAC input 155 to IAC present" bitfld.long 0x10 26. "ILACIN154,illegal access input 154" "0: ILAC input 154 to IAC not present,1: ILAC input 154 to IAC present" newline bitfld.long 0x10 25. "ILACIN153,illegal access input 153" "0: ILAC input 153 to IAC not present,1: ILAC input 153 to IAC present" bitfld.long 0x10 24. "ILACIN152,illegal access input 152" "0: ILAC input 152 to IAC not present,1: ILAC input 152 to IAC present" newline bitfld.long 0x10 23. "ILACIN151,illegal access input 151" "0: ILAC input 151 to IAC not present,1: ILAC input 151 to IAC present" bitfld.long 0x10 22. "ILACIN150,illegal access input 150" "0: ILAC input 150 to IAC not present,1: ILAC input 150 to IAC present" newline bitfld.long 0x10 21. "ILACIN149,illegal access input 149" "0: ILAC input 149 to IAC not present,1: ILAC input 149 to IAC present" bitfld.long 0x10 20. "ILACIN148,illegal access input 148" "0: ILAC input 148 to IAC not present,1: ILAC input 148 to IAC present" newline bitfld.long 0x10 19. "ILACIN147,illegal access input 147" "0: ILAC input 147 to IAC not present,1: ILAC input 147 to IAC present" bitfld.long 0x10 18. "ILACIN146,illegal access input 146" "0: ILAC input 146 to IAC not present,1: ILAC input 146 to IAC present" newline bitfld.long 0x10 17. "ILACIN145,illegal access input 145" "0: ILAC input 145 to IAC not present,1: ILAC input 145 to IAC present" bitfld.long 0x10 16. "ILACIN144,illegal access input 144" "0: ILAC input 144 to IAC not present,1: ILAC input 144 to IAC present" newline bitfld.long 0x10 15. "ILACIN143,illegal access input 143" "0: ILAC input 143 to IAC not present,1: ILAC input 143 to IAC present" bitfld.long 0x10 14. "ILACIN142,illegal access input 142" "0: ILAC input 142 to IAC not present,1: ILAC input 142 to IAC present" newline bitfld.long 0x10 13. "ILACIN141,illegal access input 141" "0: ILAC input 141 to IAC not present,1: ILAC input 141 to IAC present" bitfld.long 0x10 12. "ILACIN140,illegal access input 140" "0: ILAC input 140 to IAC not present,1: ILAC input 140 to IAC present" newline bitfld.long 0x10 11. "ILACIN139,illegal access input 139" "0: ILAC input 139 to IAC not present,1: ILAC input 139 to IAC present" bitfld.long 0x10 10. "ILACIN138,illegal access input 138" "0: ILAC input 138 to IAC not present,1: ILAC input 138 to IAC present" newline bitfld.long 0x10 9. "ILACIN137,illegal access input 137" "0: ILAC input 137 to IAC not present,1: ILAC input 137 to IAC present" bitfld.long 0x10 8. "ILACIN136,illegal access input 136" "0: ILAC input 136 to IAC not present,1: ILAC input 136 to IAC present" newline bitfld.long 0x10 7. "ILACIN135,illegal access input 135" "0: ILAC input 135 to IAC not present,1: ILAC input 135 to IAC present" bitfld.long 0x10 6. "ILACIN134,illegal access input 134" "0: ILAC input 134 to IAC not present,1: ILAC input 134 to IAC present" newline bitfld.long 0x10 5. "ILACIN133,illegal access input 133" "0: ILAC input 133 to IAC not present,1: ILAC input 133 to IAC present" bitfld.long 0x10 4. "ILACIN132,illegal access input 132" "0: ILAC input 132 to IAC not present,1: ILAC input 132 to IAC present" newline bitfld.long 0x10 3. "ILACIN131,illegal access input 131" "0: ILAC input 131 to IAC not present,1: ILAC input 131 to IAC present" bitfld.long 0x10 2. "ILACIN130,illegal access input 130" "0: ILAC input 130 to IAC not present,1: ILAC input 130 to IAC present" newline bitfld.long 0x10 1. "ILACIN129,illegal access input 129" "0: ILAC input 129 to IAC not present,1: ILAC input 129 to IAC present" bitfld.long 0x10 0. "ILACIN128,illegal access input 128" "0: ILAC input 128 to IAC not present,1: ILAC input 128 to IAC present" rgroup.long 0x384++0x3 line.long 0x0 "IAC_IISR5,IAC ILAC input status register 5" bitfld.long 0x0 31. "ILACIN159,illegal access input 159" "0: ILAC input 159 to IAC not present,1: ILAC input 159 to IAC present" bitfld.long 0x0 30. "ILACIN158,illegal access input 158" "0: ILAC input 158 to IAC not present,1: ILAC input 158 to IAC present" newline bitfld.long 0x0 29. "ILACIN157,illegal access input 157" "0: ILAC input 157 to IAC not present,1: ILAC input 157 to IAC present" bitfld.long 0x0 28. "ILACIN156,illegal access input 156" "0: ILAC input 156 to IAC not present,1: ILAC input 156 to IAC present" newline bitfld.long 0x0 27. "ILACIN155,illegal access input 155" "0: ILAC input 155 to IAC not present,1: ILAC input 155 to IAC present" bitfld.long 0x0 26. "ILACIN154,illegal access input 154" "0: ILAC input 154 to IAC not present,1: ILAC input 154 to IAC present" newline bitfld.long 0x0 25. "ILACIN153,illegal access input 153" "0: ILAC input 153 to IAC not present,1: ILAC input 153 to IAC present" bitfld.long 0x0 24. "ILACIN152,illegal access input 152" "0: ILAC input 152 to IAC not present,1: ILAC input 152 to IAC present" newline bitfld.long 0x0 23. "ILACIN151,illegal access input 151" "0: ILAC input 151 to IAC not present,1: ILAC input 151 to IAC present" bitfld.long 0x0 22. "ILACIN150,illegal access input 150" "0: ILAC input 150 to IAC not present,1: ILAC input 150 to IAC present" newline bitfld.long 0x0 21. "ILACIN149,illegal access input 149" "0: ILAC input 149 to IAC not present,1: ILAC input 149 to IAC present" bitfld.long 0x0 20. "ILACIN148,illegal access input 148" "0: ILAC input 148 to IAC not present,1: ILAC input 148 to IAC present" newline bitfld.long 0x0 19. "ILACIN147,illegal access input 147" "0: ILAC input 147 to IAC not present,1: ILAC input 147 to IAC present" bitfld.long 0x0 18. "ILACIN146,illegal access input 146" "0: ILAC input 146 to IAC not present,1: ILAC input 146 to IAC present" newline bitfld.long 0x0 17. "ILACIN145,illegal access input 145" "0: ILAC input 145 to IAC not present,1: ILAC input 145 to IAC present" bitfld.long 0x0 16. "ILACIN144,illegal access input 144" "0: ILAC input 144 to IAC not present,1: ILAC input 144 to IAC present" newline bitfld.long 0x0 15. "ILACIN143,illegal access input 143" "0: ILAC input 143 to IAC not present,1: ILAC input 143 to IAC present" bitfld.long 0x0 14. "ILACIN142,illegal access input 142" "0: ILAC input 142 to IAC not present,1: ILAC input 142 to IAC present" newline bitfld.long 0x0 13. "ILACIN141,illegal access input 141" "0: ILAC input 141 to IAC not present,1: ILAC input 141 to IAC present" bitfld.long 0x0 12. "ILACIN140,illegal access input 140" "0: ILAC input 140 to IAC not present,1: ILAC input 140 to IAC present" newline bitfld.long 0x0 11. "ILACIN139,illegal access input 139" "0: ILAC input 139 to IAC not present,1: ILAC input 139 to IAC present" bitfld.long 0x0 10. "ILACIN138,illegal access input 138" "0: ILAC input 138 to IAC not present,1: ILAC input 138 to IAC present" newline bitfld.long 0x0 9. "ILACIN137,illegal access input 137" "0: ILAC input 137 to IAC not present,1: ILAC input 137 to IAC present" bitfld.long 0x0 8. "ILACIN136,illegal access input 136" "0: ILAC input 136 to IAC not present,1: ILAC input 136 to IAC present" newline bitfld.long 0x0 7. "ILACIN135,illegal access input 135" "0: ILAC input 135 to IAC not present,1: ILAC input 135 to IAC present" bitfld.long 0x0 6. "ILACIN134,illegal access input 134" "0: ILAC input 134 to IAC not present,1: ILAC input 134 to IAC present" newline bitfld.long 0x0 5. "ILACIN133,illegal access input 133" "0: ILAC input 133 to IAC not present,1: ILAC input 133 to IAC present" bitfld.long 0x0 4. "ILACIN132,illegal access input 132" "0: ILAC input 132 to IAC not present,1: ILAC input 132 to IAC present" newline bitfld.long 0x0 3. "ILACIN131,illegal access input 131" "0: ILAC input 131 to IAC not present,1: ILAC input 131 to IAC present" bitfld.long 0x0 2. "ILACIN130,illegal access input 130" "0: ILAC input 130 to IAC not present,1: ILAC input 130 to IAC present" newline bitfld.long 0x0 1. "ILACIN129,illegal access input 129" "0: ILAC input 129 to IAC not present,1: ILAC input 129 to IAC present" bitfld.long 0x0 0. "ILACIN128,illegal access input 128" "0: ILAC input 128 to IAC not present,1: ILAC input 128 to IAC present" tree.end tree.end tree "ICACHE (Texture Cache)" base ad:0x0 tree "ICACHE" base ad:0x48035000 group.long 0x0++0x3 line.long 0x0 "ICACHE_CR,ICACHE control register" bitfld.long 0x0 19. "MISSMRST,miss monitor reset" "0: no effect,1: reset cache miss monitor" bitfld.long 0x0 18. "HITMRST,hit monitor reset" "0: no effect,1: reset cache hit monitor" newline bitfld.long 0x0 17. "MISSMEN,miss monitor enable" "0: cache miss monitor switched off. Stopping the..,1: cache miss monitor enabled" bitfld.long 0x0 16. "HITMEN,hit monitor enable" "0: cache hit monitor switched off. Stopping the..,1: cache hit monitor enabled" newline bitfld.long 0x0 2. "WAYSEL,cache associativity mode selection" "0: direct mapped cache (1-way cache),1: n-way set associative cache (reset value)" bitfld.long 0x0 1. "CACHEINV,cache invalidation" "0: no effect,1: invalidate entire cache (all cache lines valid.." newline bitfld.long 0x0 0. "EN,enable" "0: cache disabled,1: cache enabled" rgroup.long 0x4++0x3 line.long 0x0 "ICACHE_SR,ICACHE status register" bitfld.long 0x0 2. "ERRF,cache error flag" "0: no error,1: an error occurred during the operation.." bitfld.long 0x0 1. "BSYENDF,busy end flag" "0: cache busy,1: full invalidate CACHEINV operation finished" newline bitfld.long 0x0 0. "BUSYF,busy flag" "0: cache not busy on a CACHEINV operation,1: cache executing a full invalidate CACHEINV.." group.long 0x8++0x3 line.long 0x0 "ICACHE_IER,ICACHE interrupt enable register" bitfld.long 0x0 2. "ERRIE,interrupt enable on cache error" "0: interrupt disabled on error,1: interrupt enabled on error" bitfld.long 0x0 1. "BSYENDIE,interrupt enable on busy end" "0: interrupt disabled on busy end,1: interrupt enabled on busy end" wgroup.long 0xC++0x3 line.long 0x0 "ICACHE_FCR,ICACHE flag clear register" bitfld.long 0x0 2. "CERRF,clear cache error flag" "0: no effect,1: clears ERRF flag in ICACHE_SR" bitfld.long 0x0 1. "CBSYENDF,clear busy end flag" "0: no effect,1: clears BSYENDF flag in ICACHE_SR." rgroup.long 0x10++0x7 line.long 0x0 "ICACHE_HMONR,ICACHE hit monitor register" hexmask.long 0x0 0.--31. 1. "HITMON,cache hit monitor counter" line.long 0x4 "ICACHE_MMONR,ICACHE miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MISSMON,cache miss monitor counter" tree.end tree "ICACHE_S" base ad:0x58035000 group.long 0x0++0x3 line.long 0x0 "ICACHE_CR,ICACHE control register" bitfld.long 0x0 19. "MISSMRST,miss monitor reset" "0: no effect,1: reset cache miss monitor" bitfld.long 0x0 18. "HITMRST,hit monitor reset" "0: no effect,1: reset cache hit monitor" newline bitfld.long 0x0 17. "MISSMEN,miss monitor enable" "0: cache miss monitor switched off. Stopping the..,1: cache miss monitor enabled" bitfld.long 0x0 16. "HITMEN,hit monitor enable" "0: cache hit monitor switched off. Stopping the..,1: cache hit monitor enabled" newline bitfld.long 0x0 2. "WAYSEL,cache associativity mode selection" "0: direct mapped cache (1-way cache),1: n-way set associative cache (reset value)" bitfld.long 0x0 1. "CACHEINV,cache invalidation" "0: no effect,1: invalidate entire cache (all cache lines valid.." newline bitfld.long 0x0 0. "EN,enable" "0: cache disabled,1: cache enabled" rgroup.long 0x4++0x3 line.long 0x0 "ICACHE_SR,ICACHE status register" bitfld.long 0x0 2. "ERRF,cache error flag" "0: no error,1: an error occurred during the operation.." bitfld.long 0x0 1. "BSYENDF,busy end flag" "0: cache busy,1: full invalidate CACHEINV operation finished" newline bitfld.long 0x0 0. "BUSYF,busy flag" "0: cache not busy on a CACHEINV operation,1: cache executing a full invalidate CACHEINV.." group.long 0x8++0x3 line.long 0x0 "ICACHE_IER,ICACHE interrupt enable register" bitfld.long 0x0 2. "ERRIE,interrupt enable on cache error" "0: interrupt disabled on error,1: interrupt enabled on error" bitfld.long 0x0 1. "BSYENDIE,interrupt enable on busy end" "0: interrupt disabled on busy end,1: interrupt enabled on busy end" wgroup.long 0xC++0x3 line.long 0x0 "ICACHE_FCR,ICACHE flag clear register" bitfld.long 0x0 2. "CERRF,clear cache error flag" "0: no effect,1: clears ERRF flag in ICACHE_SR" bitfld.long 0x0 1. "CBSYENDF,clear busy end flag" "0: no effect,1: clears BSYENDF flag in ICACHE_SR." rgroup.long 0x10++0x7 line.long 0x0 "ICACHE_HMONR,ICACHE hit monitor register" hexmask.long 0x0 0.--31. 1. "HITMON,cache hit monitor counter" line.long 0x4 "ICACHE_MMONR,ICACHE miss monitor register" hexmask.long.word 0x4 0.--15. 1. "MISSMON,cache miss monitor counter" tree.end tree.end tree "IWDG (Independent Watchdog)" base ad:0x0 tree "IWDG" base ad:0x46004800 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,IWDG key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,IWDG prescaler register" hexmask.long.byte 0x0 0.--3. 1. "PR,Prescaler divider" line.long 0x4 "IWDG_RLR,IWDG reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,IWDG status register" bitfld.long 0x0 15. "EWIF,Watchdog early interrupt flag" "0,1" bitfld.long 0x0 8. "ONF,Watchdog enable status bit" "0: The IWDG is not activated,1: The IWDG is activated and needs to be refreshed.." bitfld.long 0x0 3. "EWU,Watchdog interrupt comparator value update" "0,1" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" newline bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1" group.long 0x10++0xB line.long 0x0 "IWDG_WINR,IWDG window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value" line.long 0x4 "IWDG_EWCR,IWDG early wake-up interrupt register" bitfld.long 0x4 15. "EWIE,Watchdog early interrupt enable" "0: The early interrupt interface is disabled.,1: The early interrupt interface is enabled." hexmask.long.word 0x4 0.--11. 1. "EWIT,Watchdog counter window value" line.long 0x8 "IWDG_ICR,IWDG interrupt clear register" bitfld.long 0x8 15. "EWIC,Watchdog early interrupt acknowledge" "0,1" tree.end tree "IWDG_S" base ad:0x56004800 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,IWDG key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,IWDG prescaler register" hexmask.long.byte 0x0 0.--3. 1. "PR,Prescaler divider" line.long 0x4 "IWDG_RLR,IWDG reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,IWDG status register" bitfld.long 0x0 15. "EWIF,Watchdog early interrupt flag" "0,1" bitfld.long 0x0 8. "ONF,Watchdog enable status bit" "0: The IWDG is not activated,1: The IWDG is activated and needs to be refreshed.." bitfld.long 0x0 3. "EWU,Watchdog interrupt comparator value update" "0,1" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" newline bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1" group.long 0x10++0xB line.long 0x0 "IWDG_WINR,IWDG window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value" line.long 0x4 "IWDG_EWCR,IWDG early wake-up interrupt register" bitfld.long 0x4 15. "EWIE,Watchdog early interrupt enable" "0: The early interrupt interface is disabled.,1: The early interrupt interface is enabled." hexmask.long.word 0x4 0.--11. 1. "EWIT,Watchdog counter window value" line.long 0x8 "IWDG_ICR,IWDG interrupt clear register" bitfld.long 0x8 15. "EWIC,Watchdog early interrupt acknowledge" "0,1" tree.end tree.end tree "JPEG (JPEG Codec)" base ad:0x0 tree "JPEG" base ad:0x48023000 wgroup.long 0x0++0x3 line.long 0x0 "JPEG_CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start" "0: Stop/abort,1: Start" group.long 0x4++0x1B line.long 0x0 "JPEG_CONFR1,JPEG codec configuration register 1" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size" bitfld.long 0x0 8. "HDR,Header processing" "0: Disable,1: Enable" newline bitfld.long 0x0 6.--7. "NS,Number of components for scan" "0,1,2,3" bitfld.long 0x0 4.--5. "COLSPACE,Color space" "0: Grayscale (1 quantization table),1: YUV (2 quantization tables),2: RGB (3 quantization tables),3: CMYK (4 quantization tables)" newline bitfld.long 0x0 3. "DE,Codec operation as coder or decoder" "0: Code,1: Decode" bitfld.long 0x0 0.--1. "NF,Number of color components" "0: Grayscale (1 color component),1: - (2 color components),2: YUV or RGB (3 color components),3: CMYK (4 color components)" line.long 0x4 "JPEG_CONFR2,JPEG codec configuration register 2" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCUs" line.long 0x8 "JPEG_CONFR3,JPEG codec configuration register 3" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size" line.long 0xC "JPEG_CONFR4,JPEG codec configuration register 4" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of blocks" bitfld.long 0xC 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0xC 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0xC 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x10 "JPEG_CONFR5,JPEG codec configuration register 5" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of blocks" bitfld.long 0x10 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x10 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x10 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x14 "JPEG_CONFR6,JPEG codec configuration register 6" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of blocks" bitfld.long 0x14 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x14 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x14 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x18 "JPEG_CONFR7,JPEG codec configuration register 7" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of blocks" bitfld.long 0x18 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x18 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x18 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" group.long 0x30++0x3 line.long 0x0 "JPEG_CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO flush" "0: No effect,1: Output FIFO is flushed" bitfld.long 0x0 13. "IFF,Input FIFO flush" "0: No effect,1: Input FIFO is flushed" newline bitfld.long 0x0 12. "ODMAEN,Output DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "IDMAEN,Input DMA enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "HPDIE,Header parsing done interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 5. "EOCIE,End of conversion interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO not empty interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 3. "OFTIE,Output FIFO threshold interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO not full interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 1. "IFTIE,Input FIFO threshold interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "JCEN,JPEG core enable" "0: Disabled (internal registers are reset).,1: Enabled (internal registers are accessible)." rgroup.long 0x34++0x3 line.long 0x0 "JPEG_SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec operation flag" "0: Not in progress,1: In progress" bitfld.long 0x0 6. "HPDF,Header parsing done flag" "0: Not completed,1: Completed" newline bitfld.long 0x0 5. "EOCF,End of conversion flag" "0: Not completed,1: Completed" bitfld.long 0x0 4. "OFNEF,Output FIFO not empty flag" "0: Empty (data not available),1: Not empty (data available)" newline bitfld.long 0x0 3. "OFTF,Output FIFO threshold flag" "0: Below threshold,1: At or above threshold" bitfld.long 0x0 2. "IFNFF,Input FIFO not full flag" "0: Full,1: Not full" newline bitfld.long 0x0 1. "IFTF,Input FIFO threshold flag" "0: At or above threshold,1: Below threshold." group.long 0x38++0x3 line.long 0x0 "JPEG_CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear header parsing done flag" "0: No effect,1: Clear" bitfld.long 0x0 5. "CEOCF,Clear end of conversion flag" "0: No effect,1: Clear" wgroup.long 0x40++0x3 line.long 0x0 "JPEG_DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input FIFO" rgroup.long 0x44++0x3 line.long 0x0 "JPEG_DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data output FIFO" group.long 0x50++0x4AB line.long 0x0 "JPEG_QMEM0_0,JPEG quantization memory 0" hexmask.long.byte 0x0 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x0 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x0 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x0 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x4 "JPEG_QMEM0_1,JPEG quantization memory 0" hexmask.long.byte 0x4 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x4 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x4 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x4 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x8 "JPEG_QMEM0_2,JPEG quantization memory 0" hexmask.long.byte 0x8 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x8 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x8 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x8 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0xC "JPEG_QMEM0_3,JPEG quantization memory 0" hexmask.long.byte 0xC 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0xC 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0xC 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0xC 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x10 "JPEG_QMEM0_4,JPEG quantization memory 0" hexmask.long.byte 0x10 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x10 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x10 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x10 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x14 "JPEG_QMEM0_5,JPEG quantization memory 0" hexmask.long.byte 0x14 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x14 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x14 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x14 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x18 "JPEG_QMEM0_6,JPEG quantization memory 0" hexmask.long.byte 0x18 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x18 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x18 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x18 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x1C "JPEG_QMEM0_7,JPEG quantization memory 0" hexmask.long.byte 0x1C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x1C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x1C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x1C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0x20 "JPEG_QMEM0_8,JPEG quantization memory 0" hexmask.long.byte 0x20 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0x20 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0x20 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0x20 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0x24 "JPEG_QMEM0_9,JPEG quantization memory 0" hexmask.long.byte 0x24 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0x24 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0x24 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0x24 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0x28 "JPEG_QMEM0_10,JPEG quantization memory 0" hexmask.long.byte 0x28 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0x28 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0x28 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0x28 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0x2C "JPEG_QMEM0_11,JPEG quantization memory 0" hexmask.long.byte 0x2C 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0x2C 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0x2C 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0x2C 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0x30 "JPEG_QMEM0_12,JPEG quantization memory 0" hexmask.long.byte 0x30 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0x30 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0x30 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0x30 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0x34 "JPEG_QMEM0_13,JPEG quantization memory 0" hexmask.long.byte 0x34 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0x34 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0x34 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0x34 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0x38 "JPEG_QMEM0_14,JPEG quantization memory 0" hexmask.long.byte 0x38 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0x38 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0x38 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0x38 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0x3C "JPEG_QMEM0_15,JPEG quantization memory 0" hexmask.long.byte 0x3C 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0x3C 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0x3C 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0x3C 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x40 "JPEG_QMEM1_0,JPEG quantization memory 1" hexmask.long.byte 0x40 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x40 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x40 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x40 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x44 "JPEG_QMEM1_1,JPEG quantization memory 1" hexmask.long.byte 0x44 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x44 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x44 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x44 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x48 "JPEG_QMEM1_2,JPEG quantization memory 1" hexmask.long.byte 0x48 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x48 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x48 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x48 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0x4C "JPEG_QMEM1_3,JPEG quantization memory 1" hexmask.long.byte 0x4C 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0x4C 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0x4C 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0x4C 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x50 "JPEG_QMEM1_4,JPEG quantization memory 1" hexmask.long.byte 0x50 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x50 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x50 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x50 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x54 "JPEG_QMEM1_5,JPEG quantization memory 1" hexmask.long.byte 0x54 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x54 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x54 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x54 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x58 "JPEG_QMEM1_6,JPEG quantization memory 1" hexmask.long.byte 0x58 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x58 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x58 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x58 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x5C "JPEG_QMEM1_7,JPEG quantization memory 1" hexmask.long.byte 0x5C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x5C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x5C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x5C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0x60 "JPEG_QMEM1_8,JPEG quantization memory 1" hexmask.long.byte 0x60 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0x60 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0x60 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0x60 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0x64 "JPEG_QMEM1_9,JPEG quantization memory 1" hexmask.long.byte 0x64 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0x64 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0x64 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0x64 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0x68 "JPEG_QMEM1_10,JPEG quantization memory 1" hexmask.long.byte 0x68 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0x68 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0x68 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0x68 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0x6C "JPEG_QMEM1_11,JPEG quantization memory 1" hexmask.long.byte 0x6C 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0x6C 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0x6C 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0x6C 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0x70 "JPEG_QMEM1_12,JPEG quantization memory 1" hexmask.long.byte 0x70 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0x70 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0x70 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0x70 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0x74 "JPEG_QMEM1_13,JPEG quantization memory 1" hexmask.long.byte 0x74 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0x74 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0x74 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0x74 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0x78 "JPEG_QMEM1_14,JPEG quantization memory 1" hexmask.long.byte 0x78 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0x78 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0x78 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0x78 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0x7C "JPEG_QMEM1_15,JPEG quantization memory 1" hexmask.long.byte 0x7C 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0x7C 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0x7C 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0x7C 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x80 "JPEG_QMEM2_0,JPEG quantization memory 2" hexmask.long.byte 0x80 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x80 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x80 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x80 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x84 "JPEG_QMEM2_1,JPEG quantization memory 2" hexmask.long.byte 0x84 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x84 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x84 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x84 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x88 "JPEG_QMEM2_2,JPEG quantization memory 2" hexmask.long.byte 0x88 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x88 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x88 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x88 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0x8C "JPEG_QMEM2_3,JPEG quantization memory 2" hexmask.long.byte 0x8C 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0x8C 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0x8C 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0x8C 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x90 "JPEG_QMEM2_4,JPEG quantization memory 2" hexmask.long.byte 0x90 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x90 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x90 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x90 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x94 "JPEG_QMEM2_5,JPEG quantization memory 2" hexmask.long.byte 0x94 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x94 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x94 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x94 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x98 "JPEG_QMEM2_6,JPEG quantization memory 2" hexmask.long.byte 0x98 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x98 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x98 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x98 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x9C "JPEG_QMEM2_7,JPEG quantization memory 2" hexmask.long.byte 0x9C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x9C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x9C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x9C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0xA0 "JPEG_QMEM2_8,JPEG quantization memory 2" hexmask.long.byte 0xA0 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0xA0 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0xA0 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0xA0 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0xA4 "JPEG_QMEM2_9,JPEG quantization memory 2" hexmask.long.byte 0xA4 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0xA4 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0xA4 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0xA4 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0xA8 "JPEG_QMEM2_10,JPEG quantization memory 2" hexmask.long.byte 0xA8 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0xA8 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0xA8 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0xA8 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0xAC "JPEG_QMEM2_11,JPEG quantization memory 2" hexmask.long.byte 0xAC 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0xAC 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0xAC 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0xAC 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0xB0 "JPEG_QMEM2_12,JPEG quantization memory 2" hexmask.long.byte 0xB0 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0xB0 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0xB0 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0xB0 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0xB4 "JPEG_QMEM2_13,JPEG quantization memory 2" hexmask.long.byte 0xB4 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0xB4 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0xB4 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0xB4 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0xB8 "JPEG_QMEM2_14,JPEG quantization memory 2" hexmask.long.byte 0xB8 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0xB8 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0xB8 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0xB8 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0xBC "JPEG_QMEM2_15,JPEG quantization memory 2" hexmask.long.byte 0xBC 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0xBC 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0xBC 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0xBC 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0xC0 "JPEG_QMEM3_0,JPEG quantization memory 3" hexmask.long.byte 0xC0 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0xC0 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0xC0 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0xC0 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0xC4 "JPEG_QMEM3_1,JPEG quantization memory 3" hexmask.long.byte 0xC4 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0xC4 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0xC4 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0xC4 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0xC8 "JPEG_QMEM3_2,JPEG quantization memory 3" hexmask.long.byte 0xC8 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0xC8 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0xC8 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0xC8 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0xCC "JPEG_QMEM3_3,JPEG quantization memory 3" hexmask.long.byte 0xCC 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0xCC 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0xCC 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0xCC 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0xD0 "JPEG_QMEM3_4,JPEG quantization memory 3" hexmask.long.byte 0xD0 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0xD0 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0xD0 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0xD0 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0xD4 "JPEG_QMEM3_5,JPEG quantization memory 3" hexmask.long.byte 0xD4 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0xD4 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0xD4 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0xD4 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0xD8 "JPEG_QMEM3_6,JPEG quantization memory 3" hexmask.long.byte 0xD8 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0xD8 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0xD8 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0xD8 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0xDC "JPEG_QMEM3_7,JPEG quantization memory 3" hexmask.long.byte 0xDC 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0xDC 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0xDC 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0xDC 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0xE0 "JPEG_QMEM3_8,JPEG quantization memory 3" hexmask.long.byte 0xE0 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0xE0 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0xE0 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0xE0 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0xE4 "JPEG_QMEM3_9,JPEG quantization memory 3" hexmask.long.byte 0xE4 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0xE4 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0xE4 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0xE4 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0xE8 "JPEG_QMEM3_10,JPEG quantization memory 3" hexmask.long.byte 0xE8 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0xE8 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0xE8 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0xE8 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0xEC "JPEG_QMEM3_11,JPEG quantization memory 3" hexmask.long.byte 0xEC 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0xEC 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0xEC 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0xEC 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0xF0 "JPEG_QMEM3_12,JPEG quantization memory 3" hexmask.long.byte 0xF0 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0xF0 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0xF0 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0xF0 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0xF4 "JPEG_QMEM3_13,JPEG quantization memory 3" hexmask.long.byte 0xF4 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0xF4 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0xF4 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0xF4 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0xF8 "JPEG_QMEM3_14,JPEG quantization memory 3" hexmask.long.byte 0xF8 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0xF8 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0xF8 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0xF8 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0xFC "JPEG_QMEM3_15,JPEG quantization memory 3" hexmask.long.byte 0xFC 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0xFC 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0xFC 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0xFC 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x100 "JPEG_HUFFMIN0_0,JPEG Huffman min" hexmask.long 0x100 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x104 "JPEG_HUFFMIN0_1,JPEG Huffman min" hexmask.long 0x104 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x108 "JPEG_HUFFMIN0_2,JPEG Huffman min" hexmask.long 0x108 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x10C "JPEG_HUFFMIN0_3,JPEG Huffman min 0" hexmask.long.byte 0x10C 0.--3. 1. "DATA0,Minimum Huffman value" line.long 0x110 "JPEG_HUFFMIN1_0,JPEG Huffman min" hexmask.long 0x110 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x114 "JPEG_HUFFMIN1_1,JPEG Huffman min" hexmask.long 0x114 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x118 "JPEG_HUFFMIN1_2,JPEG Huffman min" hexmask.long 0x118 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x11C "JPEG_HUFFMIN1_3,JPEG Huffman min 1" hexmask.long.byte 0x11C 0.--3. 1. "DATA1,Minimum Huffman value" line.long 0x120 "JPEG_HUFFMIN2_0,JPEG Huffman min" hexmask.long 0x120 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x124 "JPEG_HUFFMIN2_1,JPEG Huffman min" hexmask.long 0x124 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x128 "JPEG_HUFFMIN2_2,JPEG Huffman min" hexmask.long 0x128 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x12C "JPEG_HUFFMIN2_3,JPEG Huffman min 2" hexmask.long.byte 0x12C 0.--3. 1. "DATA2,Minimum Huffman value" line.long 0x130 "JPEG_HUFFMIN3_0,JPEG Huffman min" hexmask.long 0x130 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x134 "JPEG_HUFFMIN3_1,JPEG Huffman min" hexmask.long 0x134 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x138 "JPEG_HUFFMIN3_2,JPEG Huffman min" hexmask.long 0x138 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x13C "JPEG_HUFFMIN3_3,JPEG Huffman min 3" hexmask.long.byte 0x13C 0.--3. 1. "DATA3,Minimum Huffman value" line.long 0x140 "JPEG_HUFFBASE0,JPEG Huffman base" hexmask.long.word 0x140 16.--24. 1. "DATA1,Data 1" hexmask.long.word 0x140 0.--8. 1. "DATA0,Data 0" line.long 0x144 "JPEG_HUFFBASE1,JPEG Huffman base" hexmask.long.word 0x144 16.--24. 1. "DATA3,Data 3" hexmask.long.word 0x144 0.--8. 1. "DATA2,Data 2" line.long 0x148 "JPEG_HUFFBASE2,JPEG Huffman base" hexmask.long.word 0x148 16.--24. 1. "DATA5,Data 5" hexmask.long.word 0x148 0.--8. 1. "DATA4,Data 4" line.long 0x14C "JPEG_HUFFBASE3,JPEG Huffman base" hexmask.long.word 0x14C 16.--24. 1. "DATA7,Data 7" hexmask.long.word 0x14C 0.--8. 1. "DATA6,Data 6" line.long 0x150 "JPEG_HUFFBASE4,JPEG Huffman base" hexmask.long.word 0x150 16.--24. 1. "DATA9,Data 9" hexmask.long.word 0x150 0.--8. 1. "DATA8,Data 8" line.long 0x154 "JPEG_HUFFBASE5,JPEG Huffman base" hexmask.long.word 0x154 16.--24. 1. "DATA11,Data 11" hexmask.long.word 0x154 0.--8. 1. "DATA10,Data 10" line.long 0x158 "JPEG_HUFFBASE6,JPEG Huffman base" hexmask.long.word 0x158 16.--24. 1. "DATA13,Data 13" hexmask.long.word 0x158 0.--8. 1. "DATA12,Data 12" line.long 0x15C "JPEG_HUFFBASE7,JPEG Huffman base" hexmask.long.word 0x15C 16.--24. 1. "DATA15,Data 15" hexmask.long.word 0x15C 0.--8. 1. "DATA14,Data 14" line.long 0x160 "JPEG_HUFFBASE8,JPEG Huffman base" hexmask.long.word 0x160 16.--24. 1. "DATA17,Data 17" hexmask.long.word 0x160 0.--8. 1. "DATA16,Data 16" line.long 0x164 "JPEG_HUFFBASE9,JPEG Huffman base" hexmask.long.word 0x164 16.--24. 1. "DATA19,Data 19" hexmask.long.word 0x164 0.--8. 1. "DATA18,Data 18" line.long 0x168 "JPEG_HUFFBASE10,JPEG Huffman base" hexmask.long.word 0x168 16.--24. 1. "DATA21,Data 21" hexmask.long.word 0x168 0.--8. 1. "DATA20,Data 20" line.long 0x16C "JPEG_HUFFBASE11,JPEG Huffman base" hexmask.long.word 0x16C 16.--24. 1. "DATA23,Data 23" hexmask.long.word 0x16C 0.--8. 1. "DATA22,Data 22" line.long 0x170 "JPEG_HUFFBASE12,JPEG Huffman base" hexmask.long.word 0x170 16.--24. 1. "DATA25,Data 25" hexmask.long.word 0x170 0.--8. 1. "DATA24,Data 24" line.long 0x174 "JPEG_HUFFBASE13,JPEG Huffman base" hexmask.long.word 0x174 16.--24. 1. "DATA27,Data 27" hexmask.long.word 0x174 0.--8. 1. "DATA26,Data 26" line.long 0x178 "JPEG_HUFFBASE14,JPEG Huffman base" hexmask.long.word 0x178 16.--24. 1. "DATA29,Data 29" hexmask.long.word 0x178 0.--8. 1. "DATA28,Data 28" line.long 0x17C "JPEG_HUFFBASE15,JPEG Huffman base" hexmask.long.word 0x17C 16.--24. 1. "DATA31,Data 31" hexmask.long.word 0x17C 0.--8. 1. "DATA30,Data 30" line.long 0x180 "JPEG_HUFFBASE16,JPEG Huffman base" hexmask.long.word 0x180 16.--24. 1. "DATA33,Data 33" hexmask.long.word 0x180 0.--8. 1. "DATA32,Data 32" line.long 0x184 "JPEG_HUFFBASE17,JPEG Huffman base" hexmask.long.word 0x184 16.--24. 1. "DATA35,Data 35" hexmask.long.word 0x184 0.--8. 1. "DATA34,Data 34" line.long 0x188 "JPEG_HUFFBASE18,JPEG Huffman base" hexmask.long.word 0x188 16.--24. 1. "DATA37,Data 37" hexmask.long.word 0x188 0.--8. 1. "DATA36,Data 36" line.long 0x18C "JPEG_HUFFBASE19,JPEG Huffman base" hexmask.long.word 0x18C 16.--24. 1. "DATA39,Data 39" hexmask.long.word 0x18C 0.--8. 1. "DATA38,Data 38" line.long 0x190 "JPEG_HUFFBASE20,JPEG Huffman base" hexmask.long.word 0x190 16.--24. 1. "DATA41,Data 41" hexmask.long.word 0x190 0.--8. 1. "DATA40,Data 40" line.long 0x194 "JPEG_HUFFBASE21,JPEG Huffman base" hexmask.long.word 0x194 16.--24. 1. "DATA43,Data 43" hexmask.long.word 0x194 0.--8. 1. "DATA42,Data 42" line.long 0x198 "JPEG_HUFFBASE22,JPEG Huffman base" hexmask.long.word 0x198 16.--24. 1. "DATA45,Data 45" hexmask.long.word 0x198 0.--8. 1. "DATA44,Data 44" line.long 0x19C "JPEG_HUFFBASE23,JPEG Huffman base" hexmask.long.word 0x19C 16.--24. 1. "DATA47,Data 47" hexmask.long.word 0x19C 0.--8. 1. "DATA46,Data 46" line.long 0x1A0 "JPEG_HUFFBASE24,JPEG Huffman base" hexmask.long.word 0x1A0 16.--24. 1. "DATA49,Data 49" hexmask.long.word 0x1A0 0.--8. 1. "DATA48,Data 48" line.long 0x1A4 "JPEG_HUFFBASE25,JPEG Huffman base" hexmask.long.word 0x1A4 16.--24. 1. "DATA51,Data 51" hexmask.long.word 0x1A4 0.--8. 1. "DATA50,Data 50" line.long 0x1A8 "JPEG_HUFFBASE26,JPEG Huffman base" hexmask.long.word 0x1A8 16.--24. 1. "DATA53,Data 53" hexmask.long.word 0x1A8 0.--8. 1. "DATA52,Data 52" line.long 0x1AC "JPEG_HUFFBASE27,JPEG Huffman base" hexmask.long.word 0x1AC 16.--24. 1. "DATA55,Data 55" hexmask.long.word 0x1AC 0.--8. 1. "DATA54,Data 54" line.long 0x1B0 "JPEG_HUFFBASE28,JPEG Huffman base" hexmask.long.word 0x1B0 16.--24. 1. "DATA57,Data 57" hexmask.long.word 0x1B0 0.--8. 1. "DATA56,Data 56" line.long 0x1B4 "JPEG_HUFFBASE29,JPEG Huffman base" hexmask.long.word 0x1B4 16.--24. 1. "DATA59,Data 59" hexmask.long.word 0x1B4 0.--8. 1. "DATA58,Data 58" line.long 0x1B8 "JPEG_HUFFBASE30,JPEG Huffman base" hexmask.long.word 0x1B8 16.--24. 1. "DATA61,Data 61" hexmask.long.word 0x1B8 0.--8. 1. "DATA60,Data 60" line.long 0x1BC "JPEG_HUFFBASE31,JPEG Huffman base" hexmask.long.word 0x1BC 16.--24. 1. "DATA63,Data 63" hexmask.long.word 0x1BC 0.--8. 1. "DATA62,Data 62" line.long 0x1C0 "JPEG_HUFFSYMB0,JPEG Huffman symbol" hexmask.long.byte 0x1C0 24.--31. 1. "DATA3,Data 3" hexmask.long.byte 0x1C0 16.--23. 1. "DATA2,Data 2" newline hexmask.long.byte 0x1C0 8.--15. 1. "DATA1,Data 1" hexmask.long.byte 0x1C0 0.--7. 1. "DATA0,Data 0" line.long 0x1C4 "JPEG_HUFFSYMB1,JPEG Huffman symbol" hexmask.long.byte 0x1C4 24.--31. 1. "DATA7,Data 7" hexmask.long.byte 0x1C4 16.--23. 1. "DATA6,Data 6" newline hexmask.long.byte 0x1C4 8.--15. 1. "DATA5,Data 5" hexmask.long.byte 0x1C4 0.--7. 1. "DATA4,Data 4" line.long 0x1C8 "JPEG_HUFFSYMB2,JPEG Huffman symbol" hexmask.long.byte 0x1C8 24.--31. 1. "DATA11,Data 11" hexmask.long.byte 0x1C8 16.--23. 1. "DATA10,Data 10" newline hexmask.long.byte 0x1C8 8.--15. 1. "DATA9,Data 9" hexmask.long.byte 0x1C8 0.--7. 1. "DATA8,Data 8" line.long 0x1CC "JPEG_HUFFSYMB3,JPEG Huffman symbol" hexmask.long.byte 0x1CC 24.--31. 1. "DATA15,Data 15" hexmask.long.byte 0x1CC 16.--23. 1. "DATA14,Data 14" newline hexmask.long.byte 0x1CC 8.--15. 1. "DATA13,Data 13" hexmask.long.byte 0x1CC 0.--7. 1. "DATA12,Data 12" line.long 0x1D0 "JPEG_HUFFSYMB4,JPEG Huffman symbol" hexmask.long.byte 0x1D0 24.--31. 1. "DATA19,Data 19" hexmask.long.byte 0x1D0 16.--23. 1. "DATA18,Data 18" newline hexmask.long.byte 0x1D0 8.--15. 1. "DATA17,Data 17" hexmask.long.byte 0x1D0 0.--7. 1. "DATA16,Data 16" line.long 0x1D4 "JPEG_HUFFSYMB5,JPEG Huffman symbol" hexmask.long.byte 0x1D4 24.--31. 1. "DATA23,Data 23" hexmask.long.byte 0x1D4 16.--23. 1. "DATA22,Data 22" newline hexmask.long.byte 0x1D4 8.--15. 1. "DATA21,Data 21" hexmask.long.byte 0x1D4 0.--7. 1. "DATA20,Data 20" line.long 0x1D8 "JPEG_HUFFSYMB6,JPEG Huffman symbol" hexmask.long.byte 0x1D8 24.--31. 1. "DATA27,Data 27" hexmask.long.byte 0x1D8 16.--23. 1. "DATA26,Data 26" newline hexmask.long.byte 0x1D8 8.--15. 1. "DATA25,Data 25" hexmask.long.byte 0x1D8 0.--7. 1. "DATA24,Data 24" line.long 0x1DC "JPEG_HUFFSYMB7,JPEG Huffman symbol" hexmask.long.byte 0x1DC 24.--31. 1. "DATA31,Data 31" hexmask.long.byte 0x1DC 16.--23. 1. "DATA30,Data 30" newline hexmask.long.byte 0x1DC 8.--15. 1. "DATA29,Data 29" hexmask.long.byte 0x1DC 0.--7. 1. "DATA28,Data 28" line.long 0x1E0 "JPEG_HUFFSYMB8,JPEG Huffman symbol" hexmask.long.byte 0x1E0 24.--31. 1. "DATA35,Data 35" hexmask.long.byte 0x1E0 16.--23. 1. "DATA34,Data 34" newline hexmask.long.byte 0x1E0 8.--15. 1. "DATA33,Data 33" hexmask.long.byte 0x1E0 0.--7. 1. "DATA32,Data 32" line.long 0x1E4 "JPEG_HUFFSYMB9,JPEG Huffman symbol" hexmask.long.byte 0x1E4 24.--31. 1. "DATA39,Data 39" hexmask.long.byte 0x1E4 16.--23. 1. "DATA38,Data 38" newline hexmask.long.byte 0x1E4 8.--15. 1. "DATA37,Data 37" hexmask.long.byte 0x1E4 0.--7. 1. "DATA36,Data 36" line.long 0x1E8 "JPEG_HUFFSYMB10,JPEG Huffman symbol" hexmask.long.byte 0x1E8 24.--31. 1. "DATA43,Data 43" hexmask.long.byte 0x1E8 16.--23. 1. "DATA42,Data 42" newline hexmask.long.byte 0x1E8 8.--15. 1. "DATA41,Data 41" hexmask.long.byte 0x1E8 0.--7. 1. "DATA40,Data 40" line.long 0x1EC "JPEG_HUFFSYMB11,JPEG Huffman symbol" hexmask.long.byte 0x1EC 24.--31. 1. "DATA47,Data 47" hexmask.long.byte 0x1EC 16.--23. 1. "DATA46,Data 46" newline hexmask.long.byte 0x1EC 8.--15. 1. "DATA45,Data 45" hexmask.long.byte 0x1EC 0.--7. 1. "DATA44,Data 44" line.long 0x1F0 "JPEG_HUFFSYMB12,JPEG Huffman symbol" hexmask.long.byte 0x1F0 24.--31. 1. "DATA51,Data 51" hexmask.long.byte 0x1F0 16.--23. 1. "DATA50,Data 50" newline hexmask.long.byte 0x1F0 8.--15. 1. "DATA49,Data 49" hexmask.long.byte 0x1F0 0.--7. 1. "DATA48,Data 48" line.long 0x1F4 "JPEG_HUFFSYMB13,JPEG Huffman symbol" hexmask.long.byte 0x1F4 24.--31. 1. "DATA55,Data 55" hexmask.long.byte 0x1F4 16.--23. 1. "DATA54,Data 54" newline hexmask.long.byte 0x1F4 8.--15. 1. "DATA53,Data 53" hexmask.long.byte 0x1F4 0.--7. 1. "DATA52,Data 52" line.long 0x1F8 "JPEG_HUFFSYMB14,JPEG Huffman symbol" hexmask.long.byte 0x1F8 24.--31. 1. "DATA59,Data 59" hexmask.long.byte 0x1F8 16.--23. 1. "DATA58,Data 58" newline hexmask.long.byte 0x1F8 8.--15. 1. "DATA57,Data 57" hexmask.long.byte 0x1F8 0.--7. 1. "DATA56,Data 56" line.long 0x1FC "JPEG_HUFFSYMB15,JPEG Huffman symbol" hexmask.long.byte 0x1FC 24.--31. 1. "DATA63,Data 63" hexmask.long.byte 0x1FC 16.--23. 1. "DATA62,Data 62" newline hexmask.long.byte 0x1FC 8.--15. 1. "DATA61,Data 61" hexmask.long.byte 0x1FC 0.--7. 1. "DATA60,Data 60" line.long 0x200 "JPEG_HUFFSYMB16,JPEG Huffman symbol" hexmask.long.byte 0x200 24.--31. 1. "DATA67,Data 67" hexmask.long.byte 0x200 16.--23. 1. "DATA66,Data 66" newline hexmask.long.byte 0x200 8.--15. 1. "DATA65,Data 65" hexmask.long.byte 0x200 0.--7. 1. "DATA64,Data 64" line.long 0x204 "JPEG_HUFFSYMB17,JPEG Huffman symbol" hexmask.long.byte 0x204 24.--31. 1. "DATA71,Data 71" hexmask.long.byte 0x204 16.--23. 1. "DATA70,Data 70" newline hexmask.long.byte 0x204 8.--15. 1. "DATA69,Data 69" hexmask.long.byte 0x204 0.--7. 1. "DATA68,Data 68" line.long 0x208 "JPEG_HUFFSYMB18,JPEG Huffman symbol" hexmask.long.byte 0x208 24.--31. 1. "DATA75,Data 75" hexmask.long.byte 0x208 16.--23. 1. "DATA74,Data 74" newline hexmask.long.byte 0x208 8.--15. 1. "DATA73,Data 73" hexmask.long.byte 0x208 0.--7. 1. "DATA72,Data 72" line.long 0x20C "JPEG_HUFFSYMB19,JPEG Huffman symbol" hexmask.long.byte 0x20C 24.--31. 1. "DATA79,Data 79" hexmask.long.byte 0x20C 16.--23. 1. "DATA78,Data 78" newline hexmask.long.byte 0x20C 8.--15. 1. "DATA77,Data 77" hexmask.long.byte 0x20C 0.--7. 1. "DATA76,Data 76" line.long 0x210 "JPEG_HUFFSYMB20,JPEG Huffman symbol" hexmask.long.byte 0x210 24.--31. 1. "DATA83,Data 83" hexmask.long.byte 0x210 16.--23. 1. "DATA82,Data 82" newline hexmask.long.byte 0x210 8.--15. 1. "DATA81,Data 81" hexmask.long.byte 0x210 0.--7. 1. "DATA80,Data 80" line.long 0x214 "JPEG_HUFFSYMB21,JPEG Huffman symbol" hexmask.long.byte 0x214 24.--31. 1. "DATA87,Data 87" hexmask.long.byte 0x214 16.--23. 1. "DATA86,Data 86" newline hexmask.long.byte 0x214 8.--15. 1. "DATA85,Data 85" hexmask.long.byte 0x214 0.--7. 1. "DATA84,Data 84" line.long 0x218 "JPEG_HUFFSYMB22,JPEG Huffman symbol" hexmask.long.byte 0x218 24.--31. 1. "DATA91,Data 91" hexmask.long.byte 0x218 16.--23. 1. "DATA90,Data 90" newline hexmask.long.byte 0x218 8.--15. 1. "DATA89,Data 89" hexmask.long.byte 0x218 0.--7. 1. "DATA88,Data 88" line.long 0x21C "JPEG_HUFFSYMB23,JPEG Huffman symbol" hexmask.long.byte 0x21C 24.--31. 1. "DATA95,Data 95" hexmask.long.byte 0x21C 16.--23. 1. "DATA94,Data 94" newline hexmask.long.byte 0x21C 8.--15. 1. "DATA93,Data 93" hexmask.long.byte 0x21C 0.--7. 1. "DATA92,Data 92" line.long 0x220 "JPEG_HUFFSYMB24,JPEG Huffman symbol" hexmask.long.byte 0x220 24.--31. 1. "DATA99,Data 99" hexmask.long.byte 0x220 16.--23. 1. "DATA98,Data 98" newline hexmask.long.byte 0x220 8.--15. 1. "DATA97,Data 97" hexmask.long.byte 0x220 0.--7. 1. "DATA96,Data 96" line.long 0x224 "JPEG_HUFFSYMB25,JPEG Huffman symbol" hexmask.long.byte 0x224 24.--31. 1. "DATA103,Data 103" hexmask.long.byte 0x224 16.--23. 1. "DATA102,Data 102" newline hexmask.long.byte 0x224 8.--15. 1. "DATA101,Data 101" hexmask.long.byte 0x224 0.--7. 1. "DATA100,Data 100" line.long 0x228 "JPEG_HUFFSYMB26,JPEG Huffman symbol" hexmask.long.byte 0x228 24.--31. 1. "DATA107,Data 107" hexmask.long.byte 0x228 16.--23. 1. "DATA106,Data 106" newline hexmask.long.byte 0x228 8.--15. 1. "DATA105,Data 105" hexmask.long.byte 0x228 0.--7. 1. "DATA104,Data 104" line.long 0x22C "JPEG_HUFFSYMB27,JPEG Huffman symbol" hexmask.long.byte 0x22C 24.--31. 1. "DATA111,Data 111" hexmask.long.byte 0x22C 16.--23. 1. "DATA110,Data 110" newline hexmask.long.byte 0x22C 8.--15. 1. "DATA109,Data 109" hexmask.long.byte 0x22C 0.--7. 1. "DATA108,Data 108" line.long 0x230 "JPEG_HUFFSYMB28,JPEG Huffman symbol" hexmask.long.byte 0x230 24.--31. 1. "DATA115,Data 115" hexmask.long.byte 0x230 16.--23. 1. "DATA114,Data 114" newline hexmask.long.byte 0x230 8.--15. 1. "DATA113,Data 113" hexmask.long.byte 0x230 0.--7. 1. "DATA112,Data 112" line.long 0x234 "JPEG_HUFFSYMB29,JPEG Huffman symbol" hexmask.long.byte 0x234 24.--31. 1. "DATA119,Data 119" hexmask.long.byte 0x234 16.--23. 1. "DATA118,Data 118" newline hexmask.long.byte 0x234 8.--15. 1. "DATA117,Data 117" hexmask.long.byte 0x234 0.--7. 1. "DATA116,Data 116" line.long 0x238 "JPEG_HUFFSYMB30,JPEG Huffman symbol" hexmask.long.byte 0x238 24.--31. 1. "DATA123,Data 123" hexmask.long.byte 0x238 16.--23. 1. "DATA122,Data 122" newline hexmask.long.byte 0x238 8.--15. 1. "DATA121,Data 121" hexmask.long.byte 0x238 0.--7. 1. "DATA120,Data 120" line.long 0x23C "JPEG_HUFFSYMB31,JPEG Huffman symbol" hexmask.long.byte 0x23C 24.--31. 1. "DATA127,Data 127" hexmask.long.byte 0x23C 16.--23. 1. "DATA126,Data 126" newline hexmask.long.byte 0x23C 8.--15. 1. "DATA125,Data 125" hexmask.long.byte 0x23C 0.--7. 1. "DATA124,Data 124" line.long 0x240 "JPEG_HUFFSYMB32,JPEG Huffman symbol" hexmask.long.byte 0x240 24.--31. 1. "DATA131,Data 131" hexmask.long.byte 0x240 16.--23. 1. "DATA130,Data 130" newline hexmask.long.byte 0x240 8.--15. 1. "DATA129,Data 129" hexmask.long.byte 0x240 0.--7. 1. "DATA128,Data 128" line.long 0x244 "JPEG_HUFFSYMB33,JPEG Huffman symbol" hexmask.long.byte 0x244 24.--31. 1. "DATA135,Data 135" hexmask.long.byte 0x244 16.--23. 1. "DATA134,Data 134" newline hexmask.long.byte 0x244 8.--15. 1. "DATA133,Data 133" hexmask.long.byte 0x244 0.--7. 1. "DATA132,Data 132" line.long 0x248 "JPEG_HUFFSYMB34,JPEG Huffman symbol" hexmask.long.byte 0x248 24.--31. 1. "DATA139,Data 139" hexmask.long.byte 0x248 16.--23. 1. "DATA138,Data 138" newline hexmask.long.byte 0x248 8.--15. 1. "DATA137,Data 137" hexmask.long.byte 0x248 0.--7. 1. "DATA136,Data 136" line.long 0x24C "JPEG_HUFFSYMB35,JPEG Huffman symbol" hexmask.long.byte 0x24C 24.--31. 1. "DATA143,Data 143" hexmask.long.byte 0x24C 16.--23. 1. "DATA142,Data 142" newline hexmask.long.byte 0x24C 8.--15. 1. "DATA141,Data 141" hexmask.long.byte 0x24C 0.--7. 1. "DATA140,Data 140" line.long 0x250 "JPEG_HUFFSYMB36,JPEG Huffman symbol" hexmask.long.byte 0x250 24.--31. 1. "DATA147,Data 147" hexmask.long.byte 0x250 16.--23. 1. "DATA146,Data 146" newline hexmask.long.byte 0x250 8.--15. 1. "DATA145,Data 145" hexmask.long.byte 0x250 0.--7. 1. "DATA144,Data 144" line.long 0x254 "JPEG_HUFFSYMB37,JPEG Huffman symbol" hexmask.long.byte 0x254 24.--31. 1. "DATA151,Data 151" hexmask.long.byte 0x254 16.--23. 1. "DATA150,Data 150" newline hexmask.long.byte 0x254 8.--15. 1. "DATA149,Data 149" hexmask.long.byte 0x254 0.--7. 1. "DATA148,Data 148" line.long 0x258 "JPEG_HUFFSYMB38,JPEG Huffman symbol" hexmask.long.byte 0x258 24.--31. 1. "DATA155,Data 155" hexmask.long.byte 0x258 16.--23. 1. "DATA154,Data 154" newline hexmask.long.byte 0x258 8.--15. 1. "DATA153,Data 153" hexmask.long.byte 0x258 0.--7. 1. "DATA152,Data 152" line.long 0x25C "JPEG_HUFFSYMB39,JPEG Huffman symbol" hexmask.long.byte 0x25C 24.--31. 1. "DATA159,Data 159" hexmask.long.byte 0x25C 16.--23. 1. "DATA158,Data 158" newline hexmask.long.byte 0x25C 8.--15. 1. "DATA157,Data 157" hexmask.long.byte 0x25C 0.--7. 1. "DATA156,Data 156" line.long 0x260 "JPEG_HUFFSYMB40,JPEG Huffman symbol" hexmask.long.byte 0x260 24.--31. 1. "DATA163,Data 163" hexmask.long.byte 0x260 16.--23. 1. "DATA162,Data 162" newline hexmask.long.byte 0x260 8.--15. 1. "DATA161,Data 161" hexmask.long.byte 0x260 0.--7. 1. "DATA160,Data 160" line.long 0x264 "JPEG_HUFFSYMB41,JPEG Huffman symbol" hexmask.long.byte 0x264 24.--31. 1. "DATA167,Data 167" hexmask.long.byte 0x264 16.--23. 1. "DATA166,Data 166" newline hexmask.long.byte 0x264 8.--15. 1. "DATA165,Data 165" hexmask.long.byte 0x264 0.--7. 1. "DATA164,Data 164" line.long 0x268 "JPEG_HUFFSYMB42,JPEG Huffman symbol" hexmask.long.byte 0x268 24.--31. 1. "DATA171,Data 171" hexmask.long.byte 0x268 16.--23. 1. "DATA170,Data 170" newline hexmask.long.byte 0x268 8.--15. 1. "DATA169,Data 169" hexmask.long.byte 0x268 0.--7. 1. "DATA168,Data 168" line.long 0x26C "JPEG_HUFFSYMB43,JPEG Huffman symbol" hexmask.long.byte 0x26C 24.--31. 1. "DATA175,Data 175" hexmask.long.byte 0x26C 16.--23. 1. "DATA174,Data 174" newline hexmask.long.byte 0x26C 8.--15. 1. "DATA173,Data 173" hexmask.long.byte 0x26C 0.--7. 1. "DATA172,Data 172" line.long 0x270 "JPEG_HUFFSYMB44,JPEG Huffman symbol" hexmask.long.byte 0x270 24.--31. 1. "DATA179,Data 179" hexmask.long.byte 0x270 16.--23. 1. "DATA178,Data 178" newline hexmask.long.byte 0x270 8.--15. 1. "DATA177,Data 177" hexmask.long.byte 0x270 0.--7. 1. "DATA176,Data 176" line.long 0x274 "JPEG_HUFFSYMB45,JPEG Huffman symbol" hexmask.long.byte 0x274 24.--31. 1. "DATA183,Data 183" hexmask.long.byte 0x274 16.--23. 1. "DATA182,Data 182" newline hexmask.long.byte 0x274 8.--15. 1. "DATA181,Data 181" hexmask.long.byte 0x274 0.--7. 1. "DATA180,Data 180" line.long 0x278 "JPEG_HUFFSYMB46,JPEG Huffman symbol" hexmask.long.byte 0x278 24.--31. 1. "DATA187,Data 187" hexmask.long.byte 0x278 16.--23. 1. "DATA186,Data 186" newline hexmask.long.byte 0x278 8.--15. 1. "DATA185,Data 185" hexmask.long.byte 0x278 0.--7. 1. "DATA184,Data 184" line.long 0x27C "JPEG_HUFFSYMB47,JPEG Huffman symbol" hexmask.long.byte 0x27C 24.--31. 1. "DATA191,Data 191" hexmask.long.byte 0x27C 16.--23. 1. "DATA190,Data 190" newline hexmask.long.byte 0x27C 8.--15. 1. "DATA189,Data 189" hexmask.long.byte 0x27C 0.--7. 1. "DATA188,Data 188" line.long 0x280 "JPEG_HUFFSYMB48,JPEG Huffman symbol" hexmask.long.byte 0x280 24.--31. 1. "DATA195,Data 195" hexmask.long.byte 0x280 16.--23. 1. "DATA194,Data 194" newline hexmask.long.byte 0x280 8.--15. 1. "DATA193,Data 193" hexmask.long.byte 0x280 0.--7. 1. "DATA192,Data 192" line.long 0x284 "JPEG_HUFFSYMB49,JPEG Huffman symbol" hexmask.long.byte 0x284 24.--31. 1. "DATA199,Data 199" hexmask.long.byte 0x284 16.--23. 1. "DATA198,Data 198" newline hexmask.long.byte 0x284 8.--15. 1. "DATA197,Data 197" hexmask.long.byte 0x284 0.--7. 1. "DATA196,Data 196" line.long 0x288 "JPEG_HUFFSYMB50,JPEG Huffman symbol" hexmask.long.byte 0x288 24.--31. 1. "DATA203,Data 203" hexmask.long.byte 0x288 16.--23. 1. "DATA202,Data 202" newline hexmask.long.byte 0x288 8.--15. 1. "DATA201,Data 201" hexmask.long.byte 0x288 0.--7. 1. "DATA200,Data 200" line.long 0x28C "JPEG_HUFFSYMB51,JPEG Huffman symbol" hexmask.long.byte 0x28C 24.--31. 1. "DATA207,Data 207" hexmask.long.byte 0x28C 16.--23. 1. "DATA206,Data 206" newline hexmask.long.byte 0x28C 8.--15. 1. "DATA205,Data 205" hexmask.long.byte 0x28C 0.--7. 1. "DATA204,Data 204" line.long 0x290 "JPEG_HUFFSYMB52,JPEG Huffman symbol" hexmask.long.byte 0x290 24.--31. 1. "DATA211,Data 211" hexmask.long.byte 0x290 16.--23. 1. "DATA210,Data 210" newline hexmask.long.byte 0x290 8.--15. 1. "DATA209,Data 209" hexmask.long.byte 0x290 0.--7. 1. "DATA208,Data 208" line.long 0x294 "JPEG_HUFFSYMB53,JPEG Huffman symbol" hexmask.long.byte 0x294 24.--31. 1. "DATA215,Data 215" hexmask.long.byte 0x294 16.--23. 1. "DATA214,Data 214" newline hexmask.long.byte 0x294 8.--15. 1. "DATA213,Data 213" hexmask.long.byte 0x294 0.--7. 1. "DATA212,Data 212" line.long 0x298 "JPEG_HUFFSYMB54,JPEG Huffman symbol" hexmask.long.byte 0x298 24.--31. 1. "DATA219,Data 219" hexmask.long.byte 0x298 16.--23. 1. "DATA218,Data 218" newline hexmask.long.byte 0x298 8.--15. 1. "DATA217,Data 217" hexmask.long.byte 0x298 0.--7. 1. "DATA216,Data 216" line.long 0x29C "JPEG_HUFFSYMB55,JPEG Huffman symbol" hexmask.long.byte 0x29C 24.--31. 1. "DATA223,Data 223" hexmask.long.byte 0x29C 16.--23. 1. "DATA222,Data 222" newline hexmask.long.byte 0x29C 8.--15. 1. "DATA221,Data 221" hexmask.long.byte 0x29C 0.--7. 1. "DATA220,Data 220" line.long 0x2A0 "JPEG_HUFFSYMB56,JPEG Huffman symbol" hexmask.long.byte 0x2A0 24.--31. 1. "DATA227,Data 227" hexmask.long.byte 0x2A0 16.--23. 1. "DATA226,Data 226" newline hexmask.long.byte 0x2A0 8.--15. 1. "DATA225,Data 225" hexmask.long.byte 0x2A0 0.--7. 1. "DATA224,Data 224" line.long 0x2A4 "JPEG_HUFFSYMB57,JPEG Huffman symbol" hexmask.long.byte 0x2A4 24.--31. 1. "DATA231,Data 231" hexmask.long.byte 0x2A4 16.--23. 1. "DATA230,Data 230" newline hexmask.long.byte 0x2A4 8.--15. 1. "DATA229,Data 229" hexmask.long.byte 0x2A4 0.--7. 1. "DATA228,Data 228" line.long 0x2A8 "JPEG_HUFFSYMB58,JPEG Huffman symbol" hexmask.long.byte 0x2A8 24.--31. 1. "DATA235,Data 235" hexmask.long.byte 0x2A8 16.--23. 1. "DATA234,Data 234" newline hexmask.long.byte 0x2A8 8.--15. 1. "DATA233,Data 233" hexmask.long.byte 0x2A8 0.--7. 1. "DATA232,Data 232" line.long 0x2AC "JPEG_HUFFSYMB59,JPEG Huffman symbol" hexmask.long.byte 0x2AC 24.--31. 1. "DATA239,Data 239" hexmask.long.byte 0x2AC 16.--23. 1. "DATA238,Data 238" newline hexmask.long.byte 0x2AC 8.--15. 1. "DATA237,Data 237" hexmask.long.byte 0x2AC 0.--7. 1. "DATA236,Data 236" line.long 0x2B0 "JPEG_HUFFSYMB60,JPEG Huffman symbol" hexmask.long.byte 0x2B0 24.--31. 1. "DATA243,Data 243" hexmask.long.byte 0x2B0 16.--23. 1. "DATA242,Data 242" newline hexmask.long.byte 0x2B0 8.--15. 1. "DATA241,Data 241" hexmask.long.byte 0x2B0 0.--7. 1. "DATA240,Data 240" line.long 0x2B4 "JPEG_HUFFSYMB61,JPEG Huffman symbol" hexmask.long.byte 0x2B4 24.--31. 1. "DATA247,Data 247" hexmask.long.byte 0x2B4 16.--23. 1. "DATA246,Data 246" newline hexmask.long.byte 0x2B4 8.--15. 1. "DATA245,Data 245" hexmask.long.byte 0x2B4 0.--7. 1. "DATA244,Data 244" line.long 0x2B8 "JPEG_HUFFSYMB62,JPEG Huffman symbol" hexmask.long.byte 0x2B8 24.--31. 1. "DATA251,Data 251" hexmask.long.byte 0x2B8 16.--23. 1. "DATA250,Data 250" newline hexmask.long.byte 0x2B8 8.--15. 1. "DATA249,Data 249" hexmask.long.byte 0x2B8 0.--7. 1. "DATA248,Data 248" line.long 0x2BC "JPEG_HUFFSYMB63,JPEG Huffman symbol" hexmask.long.byte 0x2BC 24.--31. 1. "DATA255,Data 255" hexmask.long.byte 0x2BC 16.--23. 1. "DATA254,Data 254" newline hexmask.long.byte 0x2BC 8.--15. 1. "DATA253,Data 253" hexmask.long.byte 0x2BC 0.--7. 1. "DATA252,Data 252" line.long 0x2C0 "JPEG_HUFFSYMB64,JPEG Huffman symbol" hexmask.long.byte 0x2C0 24.--31. 1. "DATA259,Data 259" hexmask.long.byte 0x2C0 16.--23. 1. "DATA258,Data 258" newline hexmask.long.byte 0x2C0 8.--15. 1. "DATA257,Data 257" hexmask.long.byte 0x2C0 0.--7. 1. "DATA256,Data 256" line.long 0x2C4 "JPEG_HUFFSYMB65,JPEG Huffman symbol" hexmask.long.byte 0x2C4 24.--31. 1. "DATA263,Data 263" hexmask.long.byte 0x2C4 16.--23. 1. "DATA262,Data 262" newline hexmask.long.byte 0x2C4 8.--15. 1. "DATA261,Data 261" hexmask.long.byte 0x2C4 0.--7. 1. "DATA260,Data 260" line.long 0x2C8 "JPEG_HUFFSYMB66,JPEG Huffman symbol" hexmask.long.byte 0x2C8 24.--31. 1. "DATA267,Data 267" hexmask.long.byte 0x2C8 16.--23. 1. "DATA266,Data 266" newline hexmask.long.byte 0x2C8 8.--15. 1. "DATA265,Data 265" hexmask.long.byte 0x2C8 0.--7. 1. "DATA264,Data 264" line.long 0x2CC "JPEG_HUFFSYMB67,JPEG Huffman symbol" hexmask.long.byte 0x2CC 24.--31. 1. "DATA271,Data 271" hexmask.long.byte 0x2CC 16.--23. 1. "DATA270,Data 270" newline hexmask.long.byte 0x2CC 8.--15. 1. "DATA269,Data 269" hexmask.long.byte 0x2CC 0.--7. 1. "DATA268,Data 268" line.long 0x2D0 "JPEG_HUFFSYMB68,JPEG Huffman symbol" hexmask.long.byte 0x2D0 24.--31. 1. "DATA275,Data 275" hexmask.long.byte 0x2D0 16.--23. 1. "DATA274,Data 274" newline hexmask.long.byte 0x2D0 8.--15. 1. "DATA273,Data 273" hexmask.long.byte 0x2D0 0.--7. 1. "DATA272,Data 272" line.long 0x2D4 "JPEG_HUFFSYMB69,JPEG Huffman symbol" hexmask.long.byte 0x2D4 24.--31. 1. "DATA279,Data 279" hexmask.long.byte 0x2D4 16.--23. 1. "DATA278,Data 278" newline hexmask.long.byte 0x2D4 8.--15. 1. "DATA277,Data 277" hexmask.long.byte 0x2D4 0.--7. 1. "DATA276,Data 276" line.long 0x2D8 "JPEG_HUFFSYMB70,JPEG Huffman symbol" hexmask.long.byte 0x2D8 24.--31. 1. "DATA283,Data 283" hexmask.long.byte 0x2D8 16.--23. 1. "DATA282,Data 282" newline hexmask.long.byte 0x2D8 8.--15. 1. "DATA281,Data 281" hexmask.long.byte 0x2D8 0.--7. 1. "DATA280,Data 280" line.long 0x2DC "JPEG_HUFFSYMB71,JPEG Huffman symbol" hexmask.long.byte 0x2DC 24.--31. 1. "DATA287,Data 287" hexmask.long.byte 0x2DC 16.--23. 1. "DATA286,Data 286" newline hexmask.long.byte 0x2DC 8.--15. 1. "DATA285,Data 285" hexmask.long.byte 0x2DC 0.--7. 1. "DATA284,Data 284" line.long 0x2E0 "JPEG_HUFFSYMB72,JPEG Huffman symbol" hexmask.long.byte 0x2E0 24.--31. 1. "DATA291,Data 291" hexmask.long.byte 0x2E0 16.--23. 1. "DATA290,Data 290" newline hexmask.long.byte 0x2E0 8.--15. 1. "DATA289,Data 289" hexmask.long.byte 0x2E0 0.--7. 1. "DATA288,Data 288" line.long 0x2E4 "JPEG_HUFFSYMB73,JPEG Huffman symbol" hexmask.long.byte 0x2E4 24.--31. 1. "DATA295,Data 295" hexmask.long.byte 0x2E4 16.--23. 1. "DATA294,Data 294" newline hexmask.long.byte 0x2E4 8.--15. 1. "DATA293,Data 293" hexmask.long.byte 0x2E4 0.--7. 1. "DATA292,Data 292" line.long 0x2E8 "JPEG_HUFFSYMB74,JPEG Huffman symbol" hexmask.long.byte 0x2E8 24.--31. 1. "DATA299,Data 299" hexmask.long.byte 0x2E8 16.--23. 1. "DATA298,Data 298" newline hexmask.long.byte 0x2E8 8.--15. 1. "DATA297,Data 297" hexmask.long.byte 0x2E8 0.--7. 1. "DATA296,Data 296" line.long 0x2EC "JPEG_HUFFSYMB75,JPEG Huffman symbol" hexmask.long.byte 0x2EC 24.--31. 1. "DATA303,Data 303" hexmask.long.byte 0x2EC 16.--23. 1. "DATA302,Data 302" newline hexmask.long.byte 0x2EC 8.--15. 1. "DATA301,Data 301" hexmask.long.byte 0x2EC 0.--7. 1. "DATA300,Data 300" line.long 0x2F0 "JPEG_HUFFSYMB76,JPEG Huffman symbol" hexmask.long.byte 0x2F0 24.--31. 1. "DATA307,Data 307" hexmask.long.byte 0x2F0 16.--23. 1. "DATA306,Data 306" newline hexmask.long.byte 0x2F0 8.--15. 1. "DATA305,Data 305" hexmask.long.byte 0x2F0 0.--7. 1. "DATA304,Data 304" line.long 0x2F4 "JPEG_HUFFSYMB77,JPEG Huffman symbol" hexmask.long.byte 0x2F4 24.--31. 1. "DATA311,Data 311" hexmask.long.byte 0x2F4 16.--23. 1. "DATA310,Data 310" newline hexmask.long.byte 0x2F4 8.--15. 1. "DATA309,Data 309" hexmask.long.byte 0x2F4 0.--7. 1. "DATA308,Data 308" line.long 0x2F8 "JPEG_HUFFSYMB78,JPEG Huffman symbol" hexmask.long.byte 0x2F8 24.--31. 1. "DATA315,Data 315" hexmask.long.byte 0x2F8 16.--23. 1. "DATA314,Data 314" newline hexmask.long.byte 0x2F8 8.--15. 1. "DATA313,Data 313" hexmask.long.byte 0x2F8 0.--7. 1. "DATA312,Data 312" line.long 0x2FC "JPEG_HUFFSYMB79,JPEG Huffman symbol" hexmask.long.byte 0x2FC 24.--31. 1. "DATA319,Data 319" hexmask.long.byte 0x2FC 16.--23. 1. "DATA318,Data 318" newline hexmask.long.byte 0x2FC 8.--15. 1. "DATA317,Data 317" hexmask.long.byte 0x2FC 0.--7. 1. "DATA316,Data 316" line.long 0x300 "JPEG_HUFFSYMB80,JPEG Huffman symbol" hexmask.long.byte 0x300 24.--31. 1. "DATA323,Data 323" hexmask.long.byte 0x300 16.--23. 1. "DATA322,Data 322" newline hexmask.long.byte 0x300 8.--15. 1. "DATA321,Data 321" hexmask.long.byte 0x300 0.--7. 1. "DATA320,Data 320" line.long 0x304 "JPEG_HUFFSYMB81,JPEG Huffman symbol" hexmask.long.byte 0x304 24.--31. 1. "DATA327,Data 327" hexmask.long.byte 0x304 16.--23. 1. "DATA326,Data 326" newline hexmask.long.byte 0x304 8.--15. 1. "DATA325,Data 325" hexmask.long.byte 0x304 0.--7. 1. "DATA324,Data 324" line.long 0x308 "JPEG_HUFFSYMB82,JPEG Huffman symbol" hexmask.long.byte 0x308 24.--31. 1. "DATA331,Data 331" hexmask.long.byte 0x308 16.--23. 1. "DATA330,Data 330" newline hexmask.long.byte 0x308 8.--15. 1. "DATA329,Data 329" hexmask.long.byte 0x308 0.--7. 1. "DATA328,Data 328" line.long 0x30C "JPEG_HUFFSYMB83,JPEG Huffman symbol" hexmask.long.byte 0x30C 24.--31. 1. "DATA335,Data 335" hexmask.long.byte 0x30C 16.--23. 1. "DATA334,Data 334" newline hexmask.long.byte 0x30C 8.--15. 1. "DATA333,Data 333" hexmask.long.byte 0x30C 0.--7. 1. "DATA332,Data 332" line.long 0x310 "JPEG_DHTMEM0,JPEG DHT memory" hexmask.long.byte 0x310 24.--31. 1. "DATA3,Huffman table data 3" hexmask.long.byte 0x310 16.--23. 1. "DATA2,Huffman table data 2" newline hexmask.long.byte 0x310 8.--15. 1. "DATA1,Huffman table data 1" hexmask.long.byte 0x310 0.--7. 1. "DATA0,Huffman table data 0" line.long 0x314 "JPEG_DHTMEM1,JPEG DHT memory" hexmask.long.byte 0x314 24.--31. 1. "DATA7,Huffman table data 7" hexmask.long.byte 0x314 16.--23. 1. "DATA6,Huffman table data 6" newline hexmask.long.byte 0x314 8.--15. 1. "DATA5,Huffman table data 5" hexmask.long.byte 0x314 0.--7. 1. "DATA4,Huffman table data 4" line.long 0x318 "JPEG_DHTMEM2,JPEG DHT memory" hexmask.long.byte 0x318 24.--31. 1. "DATA11,Huffman table data 11" hexmask.long.byte 0x318 16.--23. 1. "DATA10,Huffman table data 10" newline hexmask.long.byte 0x318 8.--15. 1. "DATA9,Huffman table data 9" hexmask.long.byte 0x318 0.--7. 1. "DATA8,Huffman table data 8" line.long 0x31C "JPEG_DHTMEM3,JPEG DHT memory" hexmask.long.byte 0x31C 24.--31. 1. "DATA15,Huffman table data 15" hexmask.long.byte 0x31C 16.--23. 1. "DATA14,Huffman table data 14" newline hexmask.long.byte 0x31C 8.--15. 1. "DATA13,Huffman table data 13" hexmask.long.byte 0x31C 0.--7. 1. "DATA12,Huffman table data 12" line.long 0x320 "JPEG_DHTMEM4,JPEG DHT memory" hexmask.long.byte 0x320 24.--31. 1. "DATA19,Huffman table data 19" hexmask.long.byte 0x320 16.--23. 1. "DATA18,Huffman table data 18" newline hexmask.long.byte 0x320 8.--15. 1. "DATA17,Huffman table data 17" hexmask.long.byte 0x320 0.--7. 1. "DATA16,Huffman table data 16" line.long 0x324 "JPEG_DHTMEM5,JPEG DHT memory" hexmask.long.byte 0x324 24.--31. 1. "DATA23,Huffman table data 23" hexmask.long.byte 0x324 16.--23. 1. "DATA22,Huffman table data 22" newline hexmask.long.byte 0x324 8.--15. 1. "DATA21,Huffman table data 21" hexmask.long.byte 0x324 0.--7. 1. "DATA20,Huffman table data 20" line.long 0x328 "JPEG_DHTMEM6,JPEG DHT memory" hexmask.long.byte 0x328 24.--31. 1. "DATA27,Huffman table data 27" hexmask.long.byte 0x328 16.--23. 1. "DATA26,Huffman table data 26" newline hexmask.long.byte 0x328 8.--15. 1. "DATA25,Huffman table data 25" hexmask.long.byte 0x328 0.--7. 1. "DATA24,Huffman table data 24" line.long 0x32C "JPEG_DHTMEM7,JPEG DHT memory" hexmask.long.byte 0x32C 24.--31. 1. "DATA31,Huffman table data 31" hexmask.long.byte 0x32C 16.--23. 1. "DATA30,Huffman table data 30" newline hexmask.long.byte 0x32C 8.--15. 1. "DATA29,Huffman table data 29" hexmask.long.byte 0x32C 0.--7. 1. "DATA28,Huffman table data 28" line.long 0x330 "JPEG_DHTMEM8,JPEG DHT memory" hexmask.long.byte 0x330 24.--31. 1. "DATA35,Huffman table data 35" hexmask.long.byte 0x330 16.--23. 1. "DATA34,Huffman table data 34" newline hexmask.long.byte 0x330 8.--15. 1. "DATA33,Huffman table data 33" hexmask.long.byte 0x330 0.--7. 1. "DATA32,Huffman table data 32" line.long 0x334 "JPEG_DHTMEM9,JPEG DHT memory" hexmask.long.byte 0x334 24.--31. 1. "DATA39,Huffman table data 39" hexmask.long.byte 0x334 16.--23. 1. "DATA38,Huffman table data 38" newline hexmask.long.byte 0x334 8.--15. 1. "DATA37,Huffman table data 37" hexmask.long.byte 0x334 0.--7. 1. "DATA36,Huffman table data 36" line.long 0x338 "JPEG_DHTMEM10,JPEG DHT memory" hexmask.long.byte 0x338 24.--31. 1. "DATA43,Huffman table data 43" hexmask.long.byte 0x338 16.--23. 1. "DATA42,Huffman table data 42" newline hexmask.long.byte 0x338 8.--15. 1. "DATA41,Huffman table data 41" hexmask.long.byte 0x338 0.--7. 1. "DATA40,Huffman table data 40" line.long 0x33C "JPEG_DHTMEM11,JPEG DHT memory" hexmask.long.byte 0x33C 24.--31. 1. "DATA47,Huffman table data 47" hexmask.long.byte 0x33C 16.--23. 1. "DATA46,Huffman table data 46" newline hexmask.long.byte 0x33C 8.--15. 1. "DATA45,Huffman table data 45" hexmask.long.byte 0x33C 0.--7. 1. "DATA44,Huffman table data 44" line.long 0x340 "JPEG_DHTMEM12,JPEG DHT memory" hexmask.long.byte 0x340 24.--31. 1. "DATA51,Huffman table data 51" hexmask.long.byte 0x340 16.--23. 1. "DATA50,Huffman table data 50" newline hexmask.long.byte 0x340 8.--15. 1. "DATA49,Huffman table data 49" hexmask.long.byte 0x340 0.--7. 1. "DATA48,Huffman table data 48" line.long 0x344 "JPEG_DHTMEM13,JPEG DHT memory" hexmask.long.byte 0x344 24.--31. 1. "DATA55,Huffman table data 55" hexmask.long.byte 0x344 16.--23. 1. "DATA54,Huffman table data 54" newline hexmask.long.byte 0x344 8.--15. 1. "DATA53,Huffman table data 53" hexmask.long.byte 0x344 0.--7. 1. "DATA52,Huffman table data 52" line.long 0x348 "JPEG_DHTMEM14,JPEG DHT memory" hexmask.long.byte 0x348 24.--31. 1. "DATA59,Huffman table data 59" hexmask.long.byte 0x348 16.--23. 1. "DATA58,Huffman table data 58" newline hexmask.long.byte 0x348 8.--15. 1. "DATA57,Huffman table data 57" hexmask.long.byte 0x348 0.--7. 1. "DATA56,Huffman table data 56" line.long 0x34C "JPEG_DHTMEM15,JPEG DHT memory" hexmask.long.byte 0x34C 24.--31. 1. "DATA63,Huffman table data 63" hexmask.long.byte 0x34C 16.--23. 1. "DATA62,Huffman table data 62" newline hexmask.long.byte 0x34C 8.--15. 1. "DATA61,Huffman table data 61" hexmask.long.byte 0x34C 0.--7. 1. "DATA60,Huffman table data 60" line.long 0x350 "JPEG_DHTMEM16,JPEG DHT memory" hexmask.long.byte 0x350 24.--31. 1. "DATA67,Huffman table data 67" hexmask.long.byte 0x350 16.--23. 1. "DATA66,Huffman table data 66" newline hexmask.long.byte 0x350 8.--15. 1. "DATA65,Huffman table data 65" hexmask.long.byte 0x350 0.--7. 1. "DATA64,Huffman table data 64" line.long 0x354 "JPEG_DHTMEM17,JPEG DHT memory" hexmask.long.byte 0x354 24.--31. 1. "DATA71,Huffman table data 71" hexmask.long.byte 0x354 16.--23. 1. "DATA70,Huffman table data 70" newline hexmask.long.byte 0x354 8.--15. 1. "DATA69,Huffman table data 69" hexmask.long.byte 0x354 0.--7. 1. "DATA68,Huffman table data 68" line.long 0x358 "JPEG_DHTMEM18,JPEG DHT memory" hexmask.long.byte 0x358 24.--31. 1. "DATA75,Huffman table data 75" hexmask.long.byte 0x358 16.--23. 1. "DATA74,Huffman table data 74" newline hexmask.long.byte 0x358 8.--15. 1. "DATA73,Huffman table data 73" hexmask.long.byte 0x358 0.--7. 1. "DATA72,Huffman table data 72" line.long 0x35C "JPEG_DHTMEM19,JPEG DHT memory" hexmask.long.byte 0x35C 24.--31. 1. "DATA79,Huffman table data 79" hexmask.long.byte 0x35C 16.--23. 1. "DATA78,Huffman table data 78" newline hexmask.long.byte 0x35C 8.--15. 1. "DATA77,Huffman table data 77" hexmask.long.byte 0x35C 0.--7. 1. "DATA76,Huffman table data 76" line.long 0x360 "JPEG_DHTMEM20,JPEG DHT memory" hexmask.long.byte 0x360 24.--31. 1. "DATA83,Huffman table data 83" hexmask.long.byte 0x360 16.--23. 1. "DATA82,Huffman table data 82" newline hexmask.long.byte 0x360 8.--15. 1. "DATA81,Huffman table data 81" hexmask.long.byte 0x360 0.--7. 1. "DATA80,Huffman table data 80" line.long 0x364 "JPEG_DHTMEM21,JPEG DHT memory" hexmask.long.byte 0x364 24.--31. 1. "DATA87,Huffman table data 87" hexmask.long.byte 0x364 16.--23. 1. "DATA86,Huffman table data 86" newline hexmask.long.byte 0x364 8.--15. 1. "DATA85,Huffman table data 85" hexmask.long.byte 0x364 0.--7. 1. "DATA84,Huffman table data 84" line.long 0x368 "JPEG_DHTMEM22,JPEG DHT memory" hexmask.long.byte 0x368 24.--31. 1. "DATA91,Huffman table data 91" hexmask.long.byte 0x368 16.--23. 1. "DATA90,Huffman table data 90" newline hexmask.long.byte 0x368 8.--15. 1. "DATA89,Huffman table data 89" hexmask.long.byte 0x368 0.--7. 1. "DATA88,Huffman table data 88" line.long 0x36C "JPEG_DHTMEM23,JPEG DHT memory" hexmask.long.byte 0x36C 24.--31. 1. "DATA95,Huffman table data 95" hexmask.long.byte 0x36C 16.--23. 1. "DATA94,Huffman table data 94" newline hexmask.long.byte 0x36C 8.--15. 1. "DATA93,Huffman table data 93" hexmask.long.byte 0x36C 0.--7. 1. "DATA92,Huffman table data 92" line.long 0x370 "JPEG_DHTMEM24,JPEG DHT memory" hexmask.long.byte 0x370 24.--31. 1. "DATA99,Huffman table data 99" hexmask.long.byte 0x370 16.--23. 1. "DATA98,Huffman table data 98" newline hexmask.long.byte 0x370 8.--15. 1. "DATA97,Huffman table data 97" hexmask.long.byte 0x370 0.--7. 1. "DATA96,Huffman table data 96" line.long 0x374 "JPEG_DHTMEM25,JPEG DHT memory" hexmask.long.byte 0x374 24.--31. 1. "DATA103,Huffman table data 103" hexmask.long.byte 0x374 16.--23. 1. "DATA102,Huffman table data 102" newline hexmask.long.byte 0x374 8.--15. 1. "DATA101,Huffman table data 101" hexmask.long.byte 0x374 0.--7. 1. "DATA100,Huffman table data 100" line.long 0x378 "JPEG_DHTMEM26,JPEG DHT memory" hexmask.long.byte 0x378 24.--31. 1. "DATA107,Huffman table data 107" hexmask.long.byte 0x378 16.--23. 1. "DATA106,Huffman table data 106" newline hexmask.long.byte 0x378 8.--15. 1. "DATA105,Huffman table data 105" hexmask.long.byte 0x378 0.--7. 1. "DATA104,Huffman table data 104" line.long 0x37C "JPEG_DHTMEM27,JPEG DHT memory" hexmask.long.byte 0x37C 24.--31. 1. "DATA111,Huffman table data 111" hexmask.long.byte 0x37C 16.--23. 1. "DATA110,Huffman table data 110" newline hexmask.long.byte 0x37C 8.--15. 1. "DATA109,Huffman table data 109" hexmask.long.byte 0x37C 0.--7. 1. "DATA108,Huffman table data 108" line.long 0x380 "JPEG_DHTMEM28,JPEG DHT memory" hexmask.long.byte 0x380 24.--31. 1. "DATA115,Huffman table data 115" hexmask.long.byte 0x380 16.--23. 1. "DATA114,Huffman table data 114" newline hexmask.long.byte 0x380 8.--15. 1. "DATA113,Huffman table data 113" hexmask.long.byte 0x380 0.--7. 1. "DATA112,Huffman table data 112" line.long 0x384 "JPEG_DHTMEM29,JPEG DHT memory" hexmask.long.byte 0x384 24.--31. 1. "DATA119,Huffman table data 119" hexmask.long.byte 0x384 16.--23. 1. "DATA118,Huffman table data 118" newline hexmask.long.byte 0x384 8.--15. 1. "DATA117,Huffman table data 117" hexmask.long.byte 0x384 0.--7. 1. "DATA116,Huffman table data 116" line.long 0x388 "JPEG_DHTMEM30,JPEG DHT memory" hexmask.long.byte 0x388 24.--31. 1. "DATA123,Huffman table data 123" hexmask.long.byte 0x388 16.--23. 1. "DATA122,Huffman table data 122" newline hexmask.long.byte 0x388 8.--15. 1. "DATA121,Huffman table data 121" hexmask.long.byte 0x388 0.--7. 1. "DATA120,Huffman table data 120" line.long 0x38C "JPEG_DHTMEM31,JPEG DHT memory" hexmask.long.byte 0x38C 24.--31. 1. "DATA127,Huffman table data 127" hexmask.long.byte 0x38C 16.--23. 1. "DATA126,Huffman table data 126" newline hexmask.long.byte 0x38C 8.--15. 1. "DATA125,Huffman table data 125" hexmask.long.byte 0x38C 0.--7. 1. "DATA124,Huffman table data 124" line.long 0x390 "JPEG_DHTMEM32,JPEG DHT memory" hexmask.long.byte 0x390 24.--31. 1. "DATA131,Huffman table data 131" hexmask.long.byte 0x390 16.--23. 1. "DATA130,Huffman table data 130" newline hexmask.long.byte 0x390 8.--15. 1. "DATA129,Huffman table data 129" hexmask.long.byte 0x390 0.--7. 1. "DATA128,Huffman table data 128" line.long 0x394 "JPEG_DHTMEM33,JPEG DHT memory" hexmask.long.byte 0x394 24.--31. 1. "DATA135,Huffman table data 135" hexmask.long.byte 0x394 16.--23. 1. "DATA134,Huffman table data 134" newline hexmask.long.byte 0x394 8.--15. 1. "DATA133,Huffman table data 133" hexmask.long.byte 0x394 0.--7. 1. "DATA132,Huffman table data 132" line.long 0x398 "JPEG_DHTMEM34,JPEG DHT memory" hexmask.long.byte 0x398 24.--31. 1. "DATA139,Huffman table data 139" hexmask.long.byte 0x398 16.--23. 1. "DATA138,Huffman table data 138" newline hexmask.long.byte 0x398 8.--15. 1. "DATA137,Huffman table data 137" hexmask.long.byte 0x398 0.--7. 1. "DATA136,Huffman table data 136" line.long 0x39C "JPEG_DHTMEM35,JPEG DHT memory" hexmask.long.byte 0x39C 24.--31. 1. "DATA143,Huffman table data 143" hexmask.long.byte 0x39C 16.--23. 1. "DATA142,Huffman table data 142" newline hexmask.long.byte 0x39C 8.--15. 1. "DATA141,Huffman table data 141" hexmask.long.byte 0x39C 0.--7. 1. "DATA140,Huffman table data 140" line.long 0x3A0 "JPEG_DHTMEM36,JPEG DHT memory" hexmask.long.byte 0x3A0 24.--31. 1. "DATA147,Huffman table data 147" hexmask.long.byte 0x3A0 16.--23. 1. "DATA146,Huffman table data 146" newline hexmask.long.byte 0x3A0 8.--15. 1. "DATA145,Huffman table data 145" hexmask.long.byte 0x3A0 0.--7. 1. "DATA144,Huffman table data 144" line.long 0x3A4 "JPEG_DHTMEM37,JPEG DHT memory" hexmask.long.byte 0x3A4 24.--31. 1. "DATA151,Huffman table data 151" hexmask.long.byte 0x3A4 16.--23. 1. "DATA150,Huffman table data 150" newline hexmask.long.byte 0x3A4 8.--15. 1. "DATA149,Huffman table data 149" hexmask.long.byte 0x3A4 0.--7. 1. "DATA148,Huffman table data 148" line.long 0x3A8 "JPEG_DHTMEM38,JPEG DHT memory" hexmask.long.byte 0x3A8 24.--31. 1. "DATA155,Huffman table data 155" hexmask.long.byte 0x3A8 16.--23. 1. "DATA154,Huffman table data 154" newline hexmask.long.byte 0x3A8 8.--15. 1. "DATA153,Huffman table data 153" hexmask.long.byte 0x3A8 0.--7. 1. "DATA152,Huffman table data 152" line.long 0x3AC "JPEG_DHTMEM39,JPEG DHT memory" hexmask.long.byte 0x3AC 24.--31. 1. "DATA159,Huffman table data 159" hexmask.long.byte 0x3AC 16.--23. 1. "DATA158,Huffman table data 158" newline hexmask.long.byte 0x3AC 8.--15. 1. "DATA157,Huffman table data 157" hexmask.long.byte 0x3AC 0.--7. 1. "DATA156,Huffman table data 156" line.long 0x3B0 "JPEG_DHTMEM40,JPEG DHT memory" hexmask.long.byte 0x3B0 24.--31. 1. "DATA163,Huffman table data 163" hexmask.long.byte 0x3B0 16.--23. 1. "DATA162,Huffman table data 162" newline hexmask.long.byte 0x3B0 8.--15. 1. "DATA161,Huffman table data 161" hexmask.long.byte 0x3B0 0.--7. 1. "DATA160,Huffman table data 160" line.long 0x3B4 "JPEG_DHTMEM41,JPEG DHT memory" hexmask.long.byte 0x3B4 24.--31. 1. "DATA167,Huffman table data 167" hexmask.long.byte 0x3B4 16.--23. 1. "DATA166,Huffman table data 166" newline hexmask.long.byte 0x3B4 8.--15. 1. "DATA165,Huffman table data 165" hexmask.long.byte 0x3B4 0.--7. 1. "DATA164,Huffman table data 164" line.long 0x3B8 "JPEG_DHTMEM42,JPEG DHT memory" hexmask.long.byte 0x3B8 24.--31. 1. "DATA171,Huffman table data 171" hexmask.long.byte 0x3B8 16.--23. 1. "DATA170,Huffman table data 170" newline hexmask.long.byte 0x3B8 8.--15. 1. "DATA169,Huffman table data 169" hexmask.long.byte 0x3B8 0.--7. 1. "DATA168,Huffman table data 168" line.long 0x3BC "JPEG_DHTMEM43,JPEG DHT memory" hexmask.long.byte 0x3BC 24.--31. 1. "DATA175,Huffman table data 175" hexmask.long.byte 0x3BC 16.--23. 1. "DATA174,Huffman table data 174" newline hexmask.long.byte 0x3BC 8.--15. 1. "DATA173,Huffman table data 173" hexmask.long.byte 0x3BC 0.--7. 1. "DATA172,Huffman table data 172" line.long 0x3C0 "JPEG_DHTMEM44,JPEG DHT memory" hexmask.long.byte 0x3C0 24.--31. 1. "DATA179,Huffman table data 179" hexmask.long.byte 0x3C0 16.--23. 1. "DATA178,Huffman table data 178" newline hexmask.long.byte 0x3C0 8.--15. 1. "DATA177,Huffman table data 177" hexmask.long.byte 0x3C0 0.--7. 1. "DATA176,Huffman table data 176" line.long 0x3C4 "JPEG_DHTMEM45,JPEG DHT memory" hexmask.long.byte 0x3C4 24.--31. 1. "DATA183,Huffman table data 183" hexmask.long.byte 0x3C4 16.--23. 1. "DATA182,Huffman table data 182" newline hexmask.long.byte 0x3C4 8.--15. 1. "DATA181,Huffman table data 181" hexmask.long.byte 0x3C4 0.--7. 1. "DATA180,Huffman table data 180" line.long 0x3C8 "JPEG_DHTMEM46,JPEG DHT memory" hexmask.long.byte 0x3C8 24.--31. 1. "DATA187,Huffman table data 187" hexmask.long.byte 0x3C8 16.--23. 1. "DATA186,Huffman table data 186" newline hexmask.long.byte 0x3C8 8.--15. 1. "DATA185,Huffman table data 185" hexmask.long.byte 0x3C8 0.--7. 1. "DATA184,Huffman table data 184" line.long 0x3CC "JPEG_DHTMEM47,JPEG DHT memory" hexmask.long.byte 0x3CC 24.--31. 1. "DATA191,Huffman table data 191" hexmask.long.byte 0x3CC 16.--23. 1. "DATA190,Huffman table data 190" newline hexmask.long.byte 0x3CC 8.--15. 1. "DATA189,Huffman table data 189" hexmask.long.byte 0x3CC 0.--7. 1. "DATA188,Huffman table data 188" line.long 0x3D0 "JPEG_DHTMEM48,JPEG DHT memory" hexmask.long.byte 0x3D0 24.--31. 1. "DATA195,Huffman table data 195" hexmask.long.byte 0x3D0 16.--23. 1. "DATA194,Huffman table data 194" newline hexmask.long.byte 0x3D0 8.--15. 1. "DATA193,Huffman table data 193" hexmask.long.byte 0x3D0 0.--7. 1. "DATA192,Huffman table data 192" line.long 0x3D4 "JPEG_DHTMEM49,JPEG DHT memory" hexmask.long.byte 0x3D4 24.--31. 1. "DATA199,Huffman table data 199" hexmask.long.byte 0x3D4 16.--23. 1. "DATA198,Huffman table data 198" newline hexmask.long.byte 0x3D4 8.--15. 1. "DATA197,Huffman table data 197" hexmask.long.byte 0x3D4 0.--7. 1. "DATA196,Huffman table data 196" line.long 0x3D8 "JPEG_DHTMEM50,JPEG DHT memory" hexmask.long.byte 0x3D8 24.--31. 1. "DATA203,Huffman table data 203" hexmask.long.byte 0x3D8 16.--23. 1. "DATA202,Huffman table data 202" newline hexmask.long.byte 0x3D8 8.--15. 1. "DATA201,Huffman table data 201" hexmask.long.byte 0x3D8 0.--7. 1. "DATA200,Huffman table data 200" line.long 0x3DC "JPEG_DHTMEM51,JPEG DHT memory" hexmask.long.byte 0x3DC 24.--31. 1. "DATA207,Huffman table data 207" hexmask.long.byte 0x3DC 16.--23. 1. "DATA206,Huffman table data 206" newline hexmask.long.byte 0x3DC 8.--15. 1. "DATA205,Huffman table data 205" hexmask.long.byte 0x3DC 0.--7. 1. "DATA204,Huffman table data 204" line.long 0x3E0 "JPEG_DHTMEM52,JPEG DHT memory" hexmask.long.byte 0x3E0 24.--31. 1. "DATA211,Huffman table data 211" hexmask.long.byte 0x3E0 16.--23. 1. "DATA210,Huffman table data 210" newline hexmask.long.byte 0x3E0 8.--15. 1. "DATA209,Huffman table data 209" hexmask.long.byte 0x3E0 0.--7. 1. "DATA208,Huffman table data 208" line.long 0x3E4 "JPEG_DHTMEM53,JPEG DHT memory" hexmask.long.byte 0x3E4 24.--31. 1. "DATA215,Huffman table data 215" hexmask.long.byte 0x3E4 16.--23. 1. "DATA214,Huffman table data 214" newline hexmask.long.byte 0x3E4 8.--15. 1. "DATA213,Huffman table data 213" hexmask.long.byte 0x3E4 0.--7. 1. "DATA212,Huffman table data 212" line.long 0x3E8 "JPEG_DHTMEM54,JPEG DHT memory" hexmask.long.byte 0x3E8 24.--31. 1. "DATA219,Huffman table data 219" hexmask.long.byte 0x3E8 16.--23. 1. "DATA218,Huffman table data 218" newline hexmask.long.byte 0x3E8 8.--15. 1. "DATA217,Huffman table data 217" hexmask.long.byte 0x3E8 0.--7. 1. "DATA216,Huffman table data 216" line.long 0x3EC "JPEG_DHTMEM55,JPEG DHT memory" hexmask.long.byte 0x3EC 24.--31. 1. "DATA223,Huffman table data 223" hexmask.long.byte 0x3EC 16.--23. 1. "DATA222,Huffman table data 222" newline hexmask.long.byte 0x3EC 8.--15. 1. "DATA221,Huffman table data 221" hexmask.long.byte 0x3EC 0.--7. 1. "DATA220,Huffman table data 220" line.long 0x3F0 "JPEG_DHTMEM56,JPEG DHT memory" hexmask.long.byte 0x3F0 24.--31. 1. "DATA227,Huffman table data 227" hexmask.long.byte 0x3F0 16.--23. 1. "DATA226,Huffman table data 226" newline hexmask.long.byte 0x3F0 8.--15. 1. "DATA225,Huffman table data 225" hexmask.long.byte 0x3F0 0.--7. 1. "DATA224,Huffman table data 224" line.long 0x3F4 "JPEG_DHTMEM57,JPEG DHT memory" hexmask.long.byte 0x3F4 24.--31. 1. "DATA231,Huffman table data 231" hexmask.long.byte 0x3F4 16.--23. 1. "DATA230,Huffman table data 230" newline hexmask.long.byte 0x3F4 8.--15. 1. "DATA229,Huffman table data 229" hexmask.long.byte 0x3F4 0.--7. 1. "DATA228,Huffman table data 228" line.long 0x3F8 "JPEG_DHTMEM58,JPEG DHT memory" hexmask.long.byte 0x3F8 24.--31. 1. "DATA235,Huffman table data 235" hexmask.long.byte 0x3F8 16.--23. 1. "DATA234,Huffman table data 234" newline hexmask.long.byte 0x3F8 8.--15. 1. "DATA233,Huffman table data 233" hexmask.long.byte 0x3F8 0.--7. 1. "DATA232,Huffman table data 232" line.long 0x3FC "JPEG_DHTMEM59,JPEG DHT memory" hexmask.long.byte 0x3FC 24.--31. 1. "DATA239,Huffman table data 239" hexmask.long.byte 0x3FC 16.--23. 1. "DATA238,Huffman table data 238" newline hexmask.long.byte 0x3FC 8.--15. 1. "DATA237,Huffman table data 237" hexmask.long.byte 0x3FC 0.--7. 1. "DATA236,Huffman table data 236" line.long 0x400 "JPEG_DHTMEM60,JPEG DHT memory" hexmask.long.byte 0x400 24.--31. 1. "DATA243,Huffman table data 243" hexmask.long.byte 0x400 16.--23. 1. "DATA242,Huffman table data 242" newline hexmask.long.byte 0x400 8.--15. 1. "DATA241,Huffman table data 241" hexmask.long.byte 0x400 0.--7. 1. "DATA240,Huffman table data 240" line.long 0x404 "JPEG_DHTMEM61,JPEG DHT memory" hexmask.long.byte 0x404 24.--31. 1. "DATA247,Huffman table data 247" hexmask.long.byte 0x404 16.--23. 1. "DATA246,Huffman table data 246" newline hexmask.long.byte 0x404 8.--15. 1. "DATA245,Huffman table data 245" hexmask.long.byte 0x404 0.--7. 1. "DATA244,Huffman table data 244" line.long 0x408 "JPEG_DHTMEM62,JPEG DHT memory" hexmask.long.byte 0x408 24.--31. 1. "DATA251,Huffman table data 251" hexmask.long.byte 0x408 16.--23. 1. "DATA250,Huffman table data 250" newline hexmask.long.byte 0x408 8.--15. 1. "DATA249,Huffman table data 249" hexmask.long.byte 0x408 0.--7. 1. "DATA248,Huffman table data 248" line.long 0x40C "JPEG_DHTMEM63,JPEG DHT memory" hexmask.long.byte 0x40C 24.--31. 1. "DATA255,Huffman table data 255" hexmask.long.byte 0x40C 16.--23. 1. "DATA254,Huffman table data 254" newline hexmask.long.byte 0x40C 8.--15. 1. "DATA253,Huffman table data 253" hexmask.long.byte 0x40C 0.--7. 1. "DATA252,Huffman table data 252" line.long 0x410 "JPEG_DHTMEM64,JPEG DHT memory" hexmask.long.byte 0x410 24.--31. 1. "DATA259,Huffman table data 259" hexmask.long.byte 0x410 16.--23. 1. "DATA258,Huffman table data 258" newline hexmask.long.byte 0x410 8.--15. 1. "DATA257,Huffman table data 257" hexmask.long.byte 0x410 0.--7. 1. "DATA256,Huffman table data 256" line.long 0x414 "JPEG_DHTMEM65,JPEG DHT memory" hexmask.long.byte 0x414 24.--31. 1. "DATA263,Huffman table data 263" hexmask.long.byte 0x414 16.--23. 1. "DATA262,Huffman table data 262" newline hexmask.long.byte 0x414 8.--15. 1. "DATA261,Huffman table data 261" hexmask.long.byte 0x414 0.--7. 1. "DATA260,Huffman table data 260" line.long 0x418 "JPEG_DHTMEM66,JPEG DHT memory" hexmask.long.byte 0x418 24.--31. 1. "DATA267,Huffman table data 267" hexmask.long.byte 0x418 16.--23. 1. "DATA266,Huffman table data 266" newline hexmask.long.byte 0x418 8.--15. 1. "DATA265,Huffman table data 265" hexmask.long.byte 0x418 0.--7. 1. "DATA264,Huffman table data 264" line.long 0x41C "JPEG_DHTMEM67,JPEG DHT memory" hexmask.long.byte 0x41C 24.--31. 1. "DATA271,Huffman table data 271" hexmask.long.byte 0x41C 16.--23. 1. "DATA270,Huffman table data 270" newline hexmask.long.byte 0x41C 8.--15. 1. "DATA269,Huffman table data 269" hexmask.long.byte 0x41C 0.--7. 1. "DATA268,Huffman table data 268" line.long 0x420 "JPEG_DHTMEM68,JPEG DHT memory" hexmask.long.byte 0x420 24.--31. 1. "DATA275,Huffman table data 275" hexmask.long.byte 0x420 16.--23. 1. "DATA274,Huffman table data 274" newline hexmask.long.byte 0x420 8.--15. 1. "DATA273,Huffman table data 273" hexmask.long.byte 0x420 0.--7. 1. "DATA272,Huffman table data 272" line.long 0x424 "JPEG_DHTMEM69,JPEG DHT memory" hexmask.long.byte 0x424 24.--31. 1. "DATA279,Huffman table data 279" hexmask.long.byte 0x424 16.--23. 1. "DATA278,Huffman table data 278" newline hexmask.long.byte 0x424 8.--15. 1. "DATA277,Huffman table data 277" hexmask.long.byte 0x424 0.--7. 1. "DATA276,Huffman table data 276" line.long 0x428 "JPEG_DHTMEM70,JPEG DHT memory" hexmask.long.byte 0x428 24.--31. 1. "DATA283,Huffman table data 283" hexmask.long.byte 0x428 16.--23. 1. "DATA282,Huffman table data 282" newline hexmask.long.byte 0x428 8.--15. 1. "DATA281,Huffman table data 281" hexmask.long.byte 0x428 0.--7. 1. "DATA280,Huffman table data 280" line.long 0x42C "JPEG_DHTMEM71,JPEG DHT memory" hexmask.long.byte 0x42C 24.--31. 1. "DATA287,Huffman table data 287" hexmask.long.byte 0x42C 16.--23. 1. "DATA286,Huffman table data 286" newline hexmask.long.byte 0x42C 8.--15. 1. "DATA285,Huffman table data 285" hexmask.long.byte 0x42C 0.--7. 1. "DATA284,Huffman table data 284" line.long 0x430 "JPEG_DHTMEM72,JPEG DHT memory" hexmask.long.byte 0x430 24.--31. 1. "DATA291,Huffman table data 291" hexmask.long.byte 0x430 16.--23. 1. "DATA290,Huffman table data 290" newline hexmask.long.byte 0x430 8.--15. 1. "DATA289,Huffman table data 289" hexmask.long.byte 0x430 0.--7. 1. "DATA288,Huffman table data 288" line.long 0x434 "JPEG_DHTMEM73,JPEG DHT memory" hexmask.long.byte 0x434 24.--31. 1. "DATA295,Huffman table data 295" hexmask.long.byte 0x434 16.--23. 1. "DATA294,Huffman table data 294" newline hexmask.long.byte 0x434 8.--15. 1. "DATA293,Huffman table data 293" hexmask.long.byte 0x434 0.--7. 1. "DATA292,Huffman table data 292" line.long 0x438 "JPEG_DHTMEM74,JPEG DHT memory" hexmask.long.byte 0x438 24.--31. 1. "DATA299,Huffman table data 299" hexmask.long.byte 0x438 16.--23. 1. "DATA298,Huffman table data 298" newline hexmask.long.byte 0x438 8.--15. 1. "DATA297,Huffman table data 297" hexmask.long.byte 0x438 0.--7. 1. "DATA296,Huffman table data 296" line.long 0x43C "JPEG_DHTMEM75,JPEG DHT memory" hexmask.long.byte 0x43C 24.--31. 1. "DATA303,Huffman table data 303" hexmask.long.byte 0x43C 16.--23. 1. "DATA302,Huffman table data 302" newline hexmask.long.byte 0x43C 8.--15. 1. "DATA301,Huffman table data 301" hexmask.long.byte 0x43C 0.--7. 1. "DATA300,Huffman table data 300" line.long 0x440 "JPEG_DHTMEM76,JPEG DHT memory" hexmask.long.byte 0x440 24.--31. 1. "DATA307,Huffman table data 307" hexmask.long.byte 0x440 16.--23. 1. "DATA306,Huffman table data 306" newline hexmask.long.byte 0x440 8.--15. 1. "DATA305,Huffman table data 305" hexmask.long.byte 0x440 0.--7. 1. "DATA304,Huffman table data 304" line.long 0x444 "JPEG_DHTMEM77,JPEG DHT memory" hexmask.long.byte 0x444 24.--31. 1. "DATA311,Huffman table data 311" hexmask.long.byte 0x444 16.--23. 1. "DATA310,Huffman table data 310" newline hexmask.long.byte 0x444 8.--15. 1. "DATA309,Huffman table data 309" hexmask.long.byte 0x444 0.--7. 1. "DATA308,Huffman table data 308" line.long 0x448 "JPEG_DHTMEM78,JPEG DHT memory" hexmask.long.byte 0x448 24.--31. 1. "DATA315,Huffman table data 315" hexmask.long.byte 0x448 16.--23. 1. "DATA314,Huffman table data 314" newline hexmask.long.byte 0x448 8.--15. 1. "DATA313,Huffman table data 313" hexmask.long.byte 0x448 0.--7. 1. "DATA312,Huffman table data 312" line.long 0x44C "JPEG_DHTMEM79,JPEG DHT memory" hexmask.long.byte 0x44C 24.--31. 1. "DATA319,Huffman table data 319" hexmask.long.byte 0x44C 16.--23. 1. "DATA318,Huffman table data 318" newline hexmask.long.byte 0x44C 8.--15. 1. "DATA317,Huffman table data 317" hexmask.long.byte 0x44C 0.--7. 1. "DATA316,Huffman table data 316" line.long 0x450 "JPEG_DHTMEM80,JPEG DHT memory" hexmask.long.byte 0x450 24.--31. 1. "DATA323,Huffman table data 323" hexmask.long.byte 0x450 16.--23. 1. "DATA322,Huffman table data 322" newline hexmask.long.byte 0x450 8.--15. 1. "DATA321,Huffman table data 321" hexmask.long.byte 0x450 0.--7. 1. "DATA320,Huffman table data 320" line.long 0x454 "JPEG_DHTMEM81,JPEG DHT memory" hexmask.long.byte 0x454 24.--31. 1. "DATA327,Huffman table data 327" hexmask.long.byte 0x454 16.--23. 1. "DATA326,Huffman table data 326" newline hexmask.long.byte 0x454 8.--15. 1. "DATA325,Huffman table data 325" hexmask.long.byte 0x454 0.--7. 1. "DATA324,Huffman table data 324" line.long 0x458 "JPEG_DHTMEM82,JPEG DHT memory" hexmask.long.byte 0x458 24.--31. 1. "DATA331,Huffman table data 331" hexmask.long.byte 0x458 16.--23. 1. "DATA330,Huffman table data 330" newline hexmask.long.byte 0x458 8.--15. 1. "DATA329,Huffman table data 329" hexmask.long.byte 0x458 0.--7. 1. "DATA328,Huffman table data 328" line.long 0x45C "JPEG_DHTMEM83,JPEG DHT memory" hexmask.long.byte 0x45C 24.--31. 1. "DATA335,Huffman table data 335" hexmask.long.byte 0x45C 16.--23. 1. "DATA334,Huffman table data 334" newline hexmask.long.byte 0x45C 8.--15. 1. "DATA333,Huffman table data 333" hexmask.long.byte 0x45C 0.--7. 1. "DATA332,Huffman table data 332" line.long 0x460 "JPEG_DHTMEM84,JPEG DHT memory" hexmask.long.byte 0x460 24.--31. 1. "DATA339,Huffman table data 339" hexmask.long.byte 0x460 16.--23. 1. "DATA338,Huffman table data 338" newline hexmask.long.byte 0x460 8.--15. 1. "DATA337,Huffman table data 337" hexmask.long.byte 0x460 0.--7. 1. "DATA336,Huffman table data 336" line.long 0x464 "JPEG_DHTMEM85,JPEG DHT memory" hexmask.long.byte 0x464 24.--31. 1. "DATA343,Huffman table data 343" hexmask.long.byte 0x464 16.--23. 1. "DATA342,Huffman table data 342" newline hexmask.long.byte 0x464 8.--15. 1. "DATA341,Huffman table data 341" hexmask.long.byte 0x464 0.--7. 1. "DATA340,Huffman table data 340" line.long 0x468 "JPEG_DHTMEM86,JPEG DHT memory" hexmask.long.byte 0x468 24.--31. 1. "DATA347,Huffman table data 347" hexmask.long.byte 0x468 16.--23. 1. "DATA346,Huffman table data 346" newline hexmask.long.byte 0x468 8.--15. 1. "DATA345,Huffman table data 345" hexmask.long.byte 0x468 0.--7. 1. "DATA344,Huffman table data 344" line.long 0x46C "JPEG_DHTMEM87,JPEG DHT memory" hexmask.long.byte 0x46C 24.--31. 1. "DATA351,Huffman table data 351" hexmask.long.byte 0x46C 16.--23. 1. "DATA350,Huffman table data 350" newline hexmask.long.byte 0x46C 8.--15. 1. "DATA349,Huffman table data 349" hexmask.long.byte 0x46C 0.--7. 1. "DATA348,Huffman table data 348" line.long 0x470 "JPEG_DHTMEM88,JPEG DHT memory" hexmask.long.byte 0x470 24.--31. 1. "DATA355,Huffman table data 355" hexmask.long.byte 0x470 16.--23. 1. "DATA354,Huffman table data 354" newline hexmask.long.byte 0x470 8.--15. 1. "DATA353,Huffman table data 353" hexmask.long.byte 0x470 0.--7. 1. "DATA352,Huffman table data 352" line.long 0x474 "JPEG_DHTMEM89,JPEG DHT memory" hexmask.long.byte 0x474 24.--31. 1. "DATA359,Huffman table data 359" hexmask.long.byte 0x474 16.--23. 1. "DATA358,Huffman table data 358" newline hexmask.long.byte 0x474 8.--15. 1. "DATA357,Huffman table data 357" hexmask.long.byte 0x474 0.--7. 1. "DATA356,Huffman table data 356" line.long 0x478 "JPEG_DHTMEM90,JPEG DHT memory" hexmask.long.byte 0x478 24.--31. 1. "DATA363,Huffman table data 363" hexmask.long.byte 0x478 16.--23. 1. "DATA362,Huffman table data 362" newline hexmask.long.byte 0x478 8.--15. 1. "DATA361,Huffman table data 361" hexmask.long.byte 0x478 0.--7. 1. "DATA360,Huffman table data 360" line.long 0x47C "JPEG_DHTMEM91,JPEG DHT memory" hexmask.long.byte 0x47C 24.--31. 1. "DATA367,Huffman table data 367" hexmask.long.byte 0x47C 16.--23. 1. "DATA366,Huffman table data 366" newline hexmask.long.byte 0x47C 8.--15. 1. "DATA365,Huffman table data 365" hexmask.long.byte 0x47C 0.--7. 1. "DATA364,Huffman table data 364" line.long 0x480 "JPEG_DHTMEM92,JPEG DHT memory" hexmask.long.byte 0x480 24.--31. 1. "DATA371,Huffman table data 371" hexmask.long.byte 0x480 16.--23. 1. "DATA370,Huffman table data 370" newline hexmask.long.byte 0x480 8.--15. 1. "DATA369,Huffman table data 369" hexmask.long.byte 0x480 0.--7. 1. "DATA368,Huffman table data 368" line.long 0x484 "JPEG_DHTMEM93,JPEG DHT memory" hexmask.long.byte 0x484 24.--31. 1. "DATA375,Huffman table data 375" hexmask.long.byte 0x484 16.--23. 1. "DATA374,Huffman table data 374" newline hexmask.long.byte 0x484 8.--15. 1. "DATA373,Huffman table data 373" hexmask.long.byte 0x484 0.--7. 1. "DATA372,Huffman table data 372" line.long 0x488 "JPEG_DHTMEM94,JPEG DHT memory" hexmask.long.byte 0x488 24.--31. 1. "DATA379,Huffman table data 379" hexmask.long.byte 0x488 16.--23. 1. "DATA378,Huffman table data 378" newline hexmask.long.byte 0x488 8.--15. 1. "DATA377,Huffman table data 377" hexmask.long.byte 0x488 0.--7. 1. "DATA376,Huffman table data 376" line.long 0x48C "JPEG_DHTMEM95,JPEG DHT memory" hexmask.long.byte 0x48C 24.--31. 1. "DATA383,Huffman table data 383" hexmask.long.byte 0x48C 16.--23. 1. "DATA382,Huffman table data 382" newline hexmask.long.byte 0x48C 8.--15. 1. "DATA381,Huffman table data 381" hexmask.long.byte 0x48C 0.--7. 1. "DATA380,Huffman table data 380" line.long 0x490 "JPEG_DHTMEM96,JPEG DHT memory" hexmask.long.byte 0x490 24.--31. 1. "DATA387,Huffman table data 387" hexmask.long.byte 0x490 16.--23. 1. "DATA386,Huffman table data 386" newline hexmask.long.byte 0x490 8.--15. 1. "DATA385,Huffman table data 385" hexmask.long.byte 0x490 0.--7. 1. "DATA384,Huffman table data 384" line.long 0x494 "JPEG_DHTMEM97,JPEG DHT memory" hexmask.long.byte 0x494 24.--31. 1. "DATA391,Huffman table data 391" hexmask.long.byte 0x494 16.--23. 1. "DATA390,Huffman table data 390" newline hexmask.long.byte 0x494 8.--15. 1. "DATA389,Huffman table data 389" hexmask.long.byte 0x494 0.--7. 1. "DATA388,Huffman table data 388" line.long 0x498 "JPEG_DHTMEM98,JPEG DHT memory" hexmask.long.byte 0x498 24.--31. 1. "DATA395,Huffman table data 395" hexmask.long.byte 0x498 16.--23. 1. "DATA394,Huffman table data 394" newline hexmask.long.byte 0x498 8.--15. 1. "DATA393,Huffman table data 393" hexmask.long.byte 0x498 0.--7. 1. "DATA392,Huffman table data 392" line.long 0x49C "JPEG_DHTMEM99,JPEG DHT memory" hexmask.long.byte 0x49C 24.--31. 1. "DATA399,Huffman table data 399" hexmask.long.byte 0x49C 16.--23. 1. "DATA398,Huffman table data 398" newline hexmask.long.byte 0x49C 8.--15. 1. "DATA397,Huffman table data 397" hexmask.long.byte 0x49C 0.--7. 1. "DATA396,Huffman table data 396" line.long 0x4A0 "JPEG_DHTMEM100,JPEG DHT memory" hexmask.long.byte 0x4A0 24.--31. 1. "DATA403,Huffman table data 403" hexmask.long.byte 0x4A0 16.--23. 1. "DATA402,Huffman table data 402" newline hexmask.long.byte 0x4A0 8.--15. 1. "DATA401,Huffman table data 401" hexmask.long.byte 0x4A0 0.--7. 1. "DATA400,Huffman table data 400" line.long 0x4A4 "JPEG_DHTMEM101,JPEG DHT memory" hexmask.long.byte 0x4A4 24.--31. 1. "DATA407,Huffman table data 407" hexmask.long.byte 0x4A4 16.--23. 1. "DATA406,Huffman table data 406" newline hexmask.long.byte 0x4A4 8.--15. 1. "DATA405,Huffman table data 405" hexmask.long.byte 0x4A4 0.--7. 1. "DATA404,Huffman table data 404" line.long 0x4A8 "JPEG_DHTMEM102,JPEG DHT memory" hexmask.long.byte 0x4A8 24.--31. 1. "DATA411,Huffman table data 411" hexmask.long.byte 0x4A8 16.--23. 1. "DATA410,Huffman table data 410" newline hexmask.long.byte 0x4A8 8.--15. 1. "DATA409,Huffman table data 409" hexmask.long.byte 0x4A8 0.--7. 1. "DATA408,Huffman table data 408" group.long 0x500++0x2FF line.long 0x0 "JPEG_HUFFENC_AC0_0,JPEG Huffman encoder AC0" hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x4 "JPEG_HUFFENC_AC0_1,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x8 "JPEG_HUFFENC_AC0_2,JPEG Huffman encoder AC0" hexmask.long.byte 0x8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0xC "JPEG_HUFFENC_AC0_3,JPEG Huffman encoder AC0" hexmask.long.byte 0xC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0xC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0xC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0xC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x10 "JPEG_HUFFENC_AC0_4,JPEG Huffman encoder AC0" hexmask.long.byte 0x10 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x10 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x10 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x10 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x14 "JPEG_HUFFENC_AC0_5,JPEG Huffman encoder AC0" hexmask.long.byte 0x14 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x14 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x14 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x14 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x18 "JPEG_HUFFENC_AC0_6,JPEG Huffman encoder AC0" hexmask.long.byte 0x18 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x18 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x18 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x18 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x1C "JPEG_HUFFENC_AC0_7,JPEG Huffman encoder AC0" hexmask.long.byte 0x1C 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x1C 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x1C 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x1C 0.--7. 1. "HCODE14,Huffman code 14" line.long 0x20 "JPEG_HUFFENC_AC0_8,JPEG Huffman encoder AC0" hexmask.long.byte 0x20 24.--27. 1. "HLEN17,Huffman length 17" hexmask.long.byte 0x20 16.--23. 1. "HCODE17,Huffman code 17" newline hexmask.long.byte 0x20 8.--11. 1. "HLEN16,Huffman length 16" hexmask.long.byte 0x20 0.--7. 1. "HCODE16,Huffman code 16" line.long 0x24 "JPEG_HUFFENC_AC0_9,JPEG Huffman encoder AC0" hexmask.long.byte 0x24 24.--27. 1. "HLEN19,Huffman length 19" hexmask.long.byte 0x24 16.--23. 1. "HCODE19,Huffman code 19" newline hexmask.long.byte 0x24 8.--11. 1. "HLEN18,Huffman length 18" hexmask.long.byte 0x24 0.--7. 1. "HCODE18,Huffman code 18" line.long 0x28 "JPEG_HUFFENC_AC0_10,JPEG Huffman encoder AC0" hexmask.long.byte 0x28 24.--27. 1. "HLEN21,Huffman length 21" hexmask.long.byte 0x28 16.--23. 1. "HCODE21,Huffman code 21" newline hexmask.long.byte 0x28 8.--11. 1. "HLEN20,Huffman length 20" hexmask.long.byte 0x28 0.--7. 1. "HCODE20,Huffman code 20" line.long 0x2C "JPEG_HUFFENC_AC0_11,JPEG Huffman encoder AC0" hexmask.long.byte 0x2C 24.--27. 1. "HLEN23,Huffman length 23" hexmask.long.byte 0x2C 16.--23. 1. "HCODE23,Huffman code 23" newline hexmask.long.byte 0x2C 8.--11. 1. "HLEN22,Huffman length 22" hexmask.long.byte 0x2C 0.--7. 1. "HCODE22,Huffman code 22" line.long 0x30 "JPEG_HUFFENC_AC0_12,JPEG Huffman encoder AC0" hexmask.long.byte 0x30 24.--27. 1. "HLEN25,Huffman length 25" hexmask.long.byte 0x30 16.--23. 1. "HCODE25,Huffman code 25" newline hexmask.long.byte 0x30 8.--11. 1. "HLEN24,Huffman length 24" hexmask.long.byte 0x30 0.--7. 1. "HCODE24,Huffman code 24" line.long 0x34 "JPEG_HUFFENC_AC0_13,JPEG Huffman encoder AC0" hexmask.long.byte 0x34 24.--27. 1. "HLEN27,Huffman length 27" hexmask.long.byte 0x34 16.--23. 1. "HCODE27,Huffman code 27" newline hexmask.long.byte 0x34 8.--11. 1. "HLEN26,Huffman length 26" hexmask.long.byte 0x34 0.--7. 1. "HCODE26,Huffman code 26" line.long 0x38 "JPEG_HUFFENC_AC0_14,JPEG Huffman encoder AC0" hexmask.long.byte 0x38 24.--27. 1. "HLEN29,Huffman length 29" hexmask.long.byte 0x38 16.--23. 1. "HCODE29,Huffman code 29" newline hexmask.long.byte 0x38 8.--11. 1. "HLEN28,Huffman length 28" hexmask.long.byte 0x38 0.--7. 1. "HCODE28,Huffman code 28" line.long 0x3C "JPEG_HUFFENC_AC0_15,JPEG Huffman encoder AC0" hexmask.long.byte 0x3C 24.--27. 1. "HLEN31,Huffman length 31" hexmask.long.byte 0x3C 16.--23. 1. "HCODE31,Huffman code 31" newline hexmask.long.byte 0x3C 8.--11. 1. "HLEN30,Huffman length 30" hexmask.long.byte 0x3C 0.--7. 1. "HCODE30,Huffman code 30" line.long 0x40 "JPEG_HUFFENC_AC0_16,JPEG Huffman encoder AC0" hexmask.long.byte 0x40 24.--27. 1. "HLEN33,Huffman length 33" hexmask.long.byte 0x40 16.--23. 1. "HCODE33,Huffman code 33" newline hexmask.long.byte 0x40 8.--11. 1. "HLEN32,Huffman length 32" hexmask.long.byte 0x40 0.--7. 1. "HCODE32,Huffman code 32" line.long 0x44 "JPEG_HUFFENC_AC0_17,JPEG Huffman encoder AC0" hexmask.long.byte 0x44 24.--27. 1. "HLEN35,Huffman length 35" hexmask.long.byte 0x44 16.--23. 1. "HCODE35,Huffman code 35" newline hexmask.long.byte 0x44 8.--11. 1. "HLEN34,Huffman length 34" hexmask.long.byte 0x44 0.--7. 1. "HCODE34,Huffman code 34" line.long 0x48 "JPEG_HUFFENC_AC0_18,JPEG Huffman encoder AC0" hexmask.long.byte 0x48 24.--27. 1. "HLEN37,Huffman length 37" hexmask.long.byte 0x48 16.--23. 1. "HCODE37,Huffman code 37" newline hexmask.long.byte 0x48 8.--11. 1. "HLEN36,Huffman length 36" hexmask.long.byte 0x48 0.--7. 1. "HCODE36,Huffman code 36" line.long 0x4C "JPEG_HUFFENC_AC0_19,JPEG Huffman encoder AC0" hexmask.long.byte 0x4C 24.--27. 1. "HLEN39,Huffman length 39" hexmask.long.byte 0x4C 16.--23. 1. "HCODE39,Huffman code 39" newline hexmask.long.byte 0x4C 8.--11. 1. "HLEN38,Huffman length 38" hexmask.long.byte 0x4C 0.--7. 1. "HCODE38,Huffman code 38" line.long 0x50 "JPEG_HUFFENC_AC0_20,JPEG Huffman encoder AC0" hexmask.long.byte 0x50 24.--27. 1. "HLEN41,Huffman length 41" hexmask.long.byte 0x50 16.--23. 1. "HCODE41,Huffman code 41" newline hexmask.long.byte 0x50 8.--11. 1. "HLEN40,Huffman length 40" hexmask.long.byte 0x50 0.--7. 1. "HCODE40,Huffman code 40" line.long 0x54 "JPEG_HUFFENC_AC0_21,JPEG Huffman encoder AC0" hexmask.long.byte 0x54 24.--27. 1. "HLEN43,Huffman length 43" hexmask.long.byte 0x54 16.--23. 1. "HCODE43,Huffman code 43" newline hexmask.long.byte 0x54 8.--11. 1. "HLEN42,Huffman length 42" hexmask.long.byte 0x54 0.--7. 1. "HCODE42,Huffman code 42" line.long 0x58 "JPEG_HUFFENC_AC0_22,JPEG Huffman encoder AC0" hexmask.long.byte 0x58 24.--27. 1. "HLEN45,Huffman length 45" hexmask.long.byte 0x58 16.--23. 1. "HCODE45,Huffman code 45" newline hexmask.long.byte 0x58 8.--11. 1. "HLEN44,Huffman length 44" hexmask.long.byte 0x58 0.--7. 1. "HCODE44,Huffman code 44" line.long 0x5C "JPEG_HUFFENC_AC0_23,JPEG Huffman encoder AC0" hexmask.long.byte 0x5C 24.--27. 1. "HLEN47,Huffman length 47" hexmask.long.byte 0x5C 16.--23. 1. "HCODE47,Huffman code 47" newline hexmask.long.byte 0x5C 8.--11. 1. "HLEN46,Huffman length 46" hexmask.long.byte 0x5C 0.--7. 1. "HCODE46,Huffman code 46" line.long 0x60 "JPEG_HUFFENC_AC0_24,JPEG Huffman encoder AC0" hexmask.long.byte 0x60 24.--27. 1. "HLEN49,Huffman length 49" hexmask.long.byte 0x60 16.--23. 1. "HCODE49,Huffman code 49" newline hexmask.long.byte 0x60 8.--11. 1. "HLEN48,Huffman length 48" hexmask.long.byte 0x60 0.--7. 1. "HCODE48,Huffman code 48" line.long 0x64 "JPEG_HUFFENC_AC0_25,JPEG Huffman encoder AC0" hexmask.long.byte 0x64 24.--27. 1. "HLEN51,Huffman length 51" hexmask.long.byte 0x64 16.--23. 1. "HCODE51,Huffman code 51" newline hexmask.long.byte 0x64 8.--11. 1. "HLEN50,Huffman length 50" hexmask.long.byte 0x64 0.--7. 1. "HCODE50,Huffman code 50" line.long 0x68 "JPEG_HUFFENC_AC0_26,JPEG Huffman encoder AC0" hexmask.long.byte 0x68 24.--27. 1. "HLEN53,Huffman length 53" hexmask.long.byte 0x68 16.--23. 1. "HCODE53,Huffman code 53" newline hexmask.long.byte 0x68 8.--11. 1. "HLEN52,Huffman length 52" hexmask.long.byte 0x68 0.--7. 1. "HCODE52,Huffman code 52" line.long 0x6C "JPEG_HUFFENC_AC0_27,JPEG Huffman encoder AC0" hexmask.long.byte 0x6C 24.--27. 1. "HLEN55,Huffman length 55" hexmask.long.byte 0x6C 16.--23. 1. "HCODE55,Huffman code 55" newline hexmask.long.byte 0x6C 8.--11. 1. "HLEN54,Huffman length 54" hexmask.long.byte 0x6C 0.--7. 1. "HCODE54,Huffman code 54" line.long 0x70 "JPEG_HUFFENC_AC0_28,JPEG Huffman encoder AC0" hexmask.long.byte 0x70 24.--27. 1. "HLEN57,Huffman length 57" hexmask.long.byte 0x70 16.--23. 1. "HCODE57,Huffman code 57" newline hexmask.long.byte 0x70 8.--11. 1. "HLEN56,Huffman length 56" hexmask.long.byte 0x70 0.--7. 1. "HCODE56,Huffman code 56" line.long 0x74 "JPEG_HUFFENC_AC0_29,JPEG Huffman encoder AC0" hexmask.long.byte 0x74 24.--27. 1. "HLEN59,Huffman length 59" hexmask.long.byte 0x74 16.--23. 1. "HCODE59,Huffman code 59" newline hexmask.long.byte 0x74 8.--11. 1. "HLEN58,Huffman length 58" hexmask.long.byte 0x74 0.--7. 1. "HCODE58,Huffman code 58" line.long 0x78 "JPEG_HUFFENC_AC0_30,JPEG Huffman encoder AC0" hexmask.long.byte 0x78 24.--27. 1. "HLEN61,Huffman length 61" hexmask.long.byte 0x78 16.--23. 1. "HCODE61,Huffman code 61" newline hexmask.long.byte 0x78 8.--11. 1. "HLEN60,Huffman length 60" hexmask.long.byte 0x78 0.--7. 1. "HCODE60,Huffman code 60" line.long 0x7C "JPEG_HUFFENC_AC0_31,JPEG Huffman encoder AC0" hexmask.long.byte 0x7C 24.--27. 1. "HLEN63,Huffman length 63" hexmask.long.byte 0x7C 16.--23. 1. "HCODE63,Huffman code 63" newline hexmask.long.byte 0x7C 8.--11. 1. "HLEN62,Huffman length 62" hexmask.long.byte 0x7C 0.--7. 1. "HCODE62,Huffman code 62" line.long 0x80 "JPEG_HUFFENC_AC0_32,JPEG Huffman encoder AC0" hexmask.long.byte 0x80 24.--27. 1. "HLEN65,Huffman length 65" hexmask.long.byte 0x80 16.--23. 1. "HCODE65,Huffman code 65" newline hexmask.long.byte 0x80 8.--11. 1. "HLEN64,Huffman length 64" hexmask.long.byte 0x80 0.--7. 1. "HCODE64,Huffman code 64" line.long 0x84 "JPEG_HUFFENC_AC0_33,JPEG Huffman encoder AC0" hexmask.long.byte 0x84 24.--27. 1. "HLEN67,Huffman length 67" hexmask.long.byte 0x84 16.--23. 1. "HCODE67,Huffman code 67" newline hexmask.long.byte 0x84 8.--11. 1. "HLEN66,Huffman length 66" hexmask.long.byte 0x84 0.--7. 1. "HCODE66,Huffman code 66" line.long 0x88 "JPEG_HUFFENC_AC0_34,JPEG Huffman encoder AC0" hexmask.long.byte 0x88 24.--27. 1. "HLEN69,Huffman length 69" hexmask.long.byte 0x88 16.--23. 1. "HCODE69,Huffman code 69" newline hexmask.long.byte 0x88 8.--11. 1. "HLEN68,Huffman length 68" hexmask.long.byte 0x88 0.--7. 1. "HCODE68,Huffman code 68" line.long 0x8C "JPEG_HUFFENC_AC0_35,JPEG Huffman encoder AC0" hexmask.long.byte 0x8C 24.--27. 1. "HLEN71,Huffman length 71" hexmask.long.byte 0x8C 16.--23. 1. "HCODE71,Huffman code 71" newline hexmask.long.byte 0x8C 8.--11. 1. "HLEN70,Huffman length 70" hexmask.long.byte 0x8C 0.--7. 1. "HCODE70,Huffman code 70" line.long 0x90 "JPEG_HUFFENC_AC0_36,JPEG Huffman encoder AC0" hexmask.long.byte 0x90 24.--27. 1. "HLEN73,Huffman length 73" hexmask.long.byte 0x90 16.--23. 1. "HCODE73,Huffman code 73" newline hexmask.long.byte 0x90 8.--11. 1. "HLEN72,Huffman length 72" hexmask.long.byte 0x90 0.--7. 1. "HCODE72,Huffman code 72" line.long 0x94 "JPEG_HUFFENC_AC0_37,JPEG Huffman encoder AC0" hexmask.long.byte 0x94 24.--27. 1. "HLEN75,Huffman length 75" hexmask.long.byte 0x94 16.--23. 1. "HCODE75,Huffman code 75" newline hexmask.long.byte 0x94 8.--11. 1. "HLEN74,Huffman length 74" hexmask.long.byte 0x94 0.--7. 1. "HCODE74,Huffman code 74" line.long 0x98 "JPEG_HUFFENC_AC0_38,JPEG Huffman encoder AC0" hexmask.long.byte 0x98 24.--27. 1. "HLEN77,Huffman length 77" hexmask.long.byte 0x98 16.--23. 1. "HCODE77,Huffman code 77" newline hexmask.long.byte 0x98 8.--11. 1. "HLEN76,Huffman length 76" hexmask.long.byte 0x98 0.--7. 1. "HCODE76,Huffman code 76" line.long 0x9C "JPEG_HUFFENC_AC0_39,JPEG Huffman encoder AC0" hexmask.long.byte 0x9C 24.--27. 1. "HLEN79,Huffman length 79" hexmask.long.byte 0x9C 16.--23. 1. "HCODE79,Huffman code 79" newline hexmask.long.byte 0x9C 8.--11. 1. "HLEN78,Huffman length 78" hexmask.long.byte 0x9C 0.--7. 1. "HCODE78,Huffman code 78" line.long 0xA0 "JPEG_HUFFENC_AC0_40,JPEG Huffman encoder AC0" hexmask.long.byte 0xA0 24.--27. 1. "HLEN81,Huffman length 81" hexmask.long.byte 0xA0 16.--23. 1. "HCODE81,Huffman code 81" newline hexmask.long.byte 0xA0 8.--11. 1. "HLEN80,Huffman length 80" hexmask.long.byte 0xA0 0.--7. 1. "HCODE80,Huffman code 80" line.long 0xA4 "JPEG_HUFFENC_AC0_41,JPEG Huffman encoder AC0" hexmask.long.byte 0xA4 24.--27. 1. "HLEN83,Huffman length 83" hexmask.long.byte 0xA4 16.--23. 1. "HCODE83,Huffman code 83" newline hexmask.long.byte 0xA4 8.--11. 1. "HLEN82,Huffman length 82" hexmask.long.byte 0xA4 0.--7. 1. "HCODE82,Huffman code 82" line.long 0xA8 "JPEG_HUFFENC_AC0_42,JPEG Huffman encoder AC0" hexmask.long.byte 0xA8 24.--27. 1. "HLEN85,Huffman length 85" hexmask.long.byte 0xA8 16.--23. 1. "HCODE85,Huffman code 85" newline hexmask.long.byte 0xA8 8.--11. 1. "HLEN84,Huffman length 84" hexmask.long.byte 0xA8 0.--7. 1. "HCODE84,Huffman code 84" line.long 0xAC "JPEG_HUFFENC_AC0_43,JPEG Huffman encoder AC0" hexmask.long.byte 0xAC 24.--27. 1. "HLEN87,Huffman length 87" hexmask.long.byte 0xAC 16.--23. 1. "HCODE87,Huffman code 87" newline hexmask.long.byte 0xAC 8.--11. 1. "HLEN86,Huffman length 86" hexmask.long.byte 0xAC 0.--7. 1. "HCODE86,Huffman code 86" line.long 0xB0 "JPEG_HUFFENC_AC0_44,JPEG Huffman encoder AC0" hexmask.long.byte 0xB0 24.--27. 1. "HLEN89,Huffman length 89" hexmask.long.byte 0xB0 16.--23. 1. "HCODE89,Huffman code 89" newline hexmask.long.byte 0xB0 8.--11. 1. "HLEN88,Huffman length 88" hexmask.long.byte 0xB0 0.--7. 1. "HCODE88,Huffman code 88" line.long 0xB4 "JPEG_HUFFENC_AC0_45,JPEG Huffman encoder AC0" hexmask.long.byte 0xB4 24.--27. 1. "HLEN91,Huffman length 91" hexmask.long.byte 0xB4 16.--23. 1. "HCODE91,Huffman code 91" newline hexmask.long.byte 0xB4 8.--11. 1. "HLEN90,Huffman length 90" hexmask.long.byte 0xB4 0.--7. 1. "HCODE90,Huffman code 90" line.long 0xB8 "JPEG_HUFFENC_AC0_46,JPEG Huffman encoder AC0" hexmask.long.byte 0xB8 24.--27. 1. "HLEN93,Huffman length 93" hexmask.long.byte 0xB8 16.--23. 1. "HCODE93,Huffman code 93" newline hexmask.long.byte 0xB8 8.--11. 1. "HLEN92,Huffman length 92" hexmask.long.byte 0xB8 0.--7. 1. "HCODE92,Huffman code 92" line.long 0xBC "JPEG_HUFFENC_AC0_47,JPEG Huffman encoder AC0" hexmask.long.byte 0xBC 24.--27. 1. "HLEN95,Huffman length 95" hexmask.long.byte 0xBC 16.--23. 1. "HCODE95,Huffman code 95" newline hexmask.long.byte 0xBC 8.--11. 1. "HLEN94,Huffman length 94" hexmask.long.byte 0xBC 0.--7. 1. "HCODE94,Huffman code 94" line.long 0xC0 "JPEG_HUFFENC_AC0_48,JPEG Huffman encoder AC0" hexmask.long.byte 0xC0 24.--27. 1. "HLEN97,Huffman length 97" hexmask.long.byte 0xC0 16.--23. 1. "HCODE97,Huffman code 97" newline hexmask.long.byte 0xC0 8.--11. 1. "HLEN96,Huffman length 96" hexmask.long.byte 0xC0 0.--7. 1. "HCODE96,Huffman code 96" line.long 0xC4 "JPEG_HUFFENC_AC0_49,JPEG Huffman encoder AC0" hexmask.long.byte 0xC4 24.--27. 1. "HLEN99,Huffman length 99" hexmask.long.byte 0xC4 16.--23. 1. "HCODE99,Huffman code 99" newline hexmask.long.byte 0xC4 8.--11. 1. "HLEN98,Huffman length 98" hexmask.long.byte 0xC4 0.--7. 1. "HCODE98,Huffman code 98" line.long 0xC8 "JPEG_HUFFENC_AC0_50,JPEG Huffman encoder AC0" hexmask.long.byte 0xC8 24.--27. 1. "HLEN101,Huffman length 101" hexmask.long.byte 0xC8 16.--23. 1. "HCODE101,Huffman code 101" newline hexmask.long.byte 0xC8 8.--11. 1. "HLEN100,Huffman length 100" hexmask.long.byte 0xC8 0.--7. 1. "HCODE100,Huffman code 100" line.long 0xCC "JPEG_HUFFENC_AC0_51,JPEG Huffman encoder AC0" hexmask.long.byte 0xCC 24.--27. 1. "HLEN103,Huffman length 103" hexmask.long.byte 0xCC 16.--23. 1. "HCODE103,Huffman code 103" newline hexmask.long.byte 0xCC 8.--11. 1. "HLEN102,Huffman length 102" hexmask.long.byte 0xCC 0.--7. 1. "HCODE102,Huffman code 102" line.long 0xD0 "JPEG_HUFFENC_AC0_52,JPEG Huffman encoder AC0" hexmask.long.byte 0xD0 24.--27. 1. "HLEN105,Huffman length 105" hexmask.long.byte 0xD0 16.--23. 1. "HCODE105,Huffman code 105" newline hexmask.long.byte 0xD0 8.--11. 1. "HLEN104,Huffman length 104" hexmask.long.byte 0xD0 0.--7. 1. "HCODE104,Huffman code 104" line.long 0xD4 "JPEG_HUFFENC_AC0_53,JPEG Huffman encoder AC0" hexmask.long.byte 0xD4 24.--27. 1. "HLEN107,Huffman length 107" hexmask.long.byte 0xD4 16.--23. 1. "HCODE107,Huffman code 107" newline hexmask.long.byte 0xD4 8.--11. 1. "HLEN106,Huffman length 106" hexmask.long.byte 0xD4 0.--7. 1. "HCODE106,Huffman code 106" line.long 0xD8 "JPEG_HUFFENC_AC0_54,JPEG Huffman encoder AC0" hexmask.long.byte 0xD8 24.--27. 1. "HLEN109,Huffman length 109" hexmask.long.byte 0xD8 16.--23. 1. "HCODE109,Huffman code 109" newline hexmask.long.byte 0xD8 8.--11. 1. "HLEN108,Huffman length 108" hexmask.long.byte 0xD8 0.--7. 1. "HCODE108,Huffman code 108" line.long 0xDC "JPEG_HUFFENC_AC0_55,JPEG Huffman encoder AC0" hexmask.long.byte 0xDC 24.--27. 1. "HLEN111,Huffman length 111" hexmask.long.byte 0xDC 16.--23. 1. "HCODE111,Huffman code 111" newline hexmask.long.byte 0xDC 8.--11. 1. "HLEN110,Huffman length 110" hexmask.long.byte 0xDC 0.--7. 1. "HCODE110,Huffman code 110" line.long 0xE0 "JPEG_HUFFENC_AC0_56,JPEG Huffman encoder AC0" hexmask.long.byte 0xE0 24.--27. 1. "HLEN113,Huffman length 113" hexmask.long.byte 0xE0 16.--23. 1. "HCODE113,Huffman code 113" newline hexmask.long.byte 0xE0 8.--11. 1. "HLEN112,Huffman length 112" hexmask.long.byte 0xE0 0.--7. 1. "HCODE112,Huffman code 112" line.long 0xE4 "JPEG_HUFFENC_AC0_57,JPEG Huffman encoder AC0" hexmask.long.byte 0xE4 24.--27. 1. "HLEN115,Huffman length 115" hexmask.long.byte 0xE4 16.--23. 1. "HCODE115,Huffman code 115" newline hexmask.long.byte 0xE4 8.--11. 1. "HLEN114,Huffman length 114" hexmask.long.byte 0xE4 0.--7. 1. "HCODE114,Huffman code 114" line.long 0xE8 "JPEG_HUFFENC_AC0_58,JPEG Huffman encoder AC0" hexmask.long.byte 0xE8 24.--27. 1. "HLEN117,Huffman length 117" hexmask.long.byte 0xE8 16.--23. 1. "HCODE117,Huffman code 117" newline hexmask.long.byte 0xE8 8.--11. 1. "HLEN116,Huffman length 116" hexmask.long.byte 0xE8 0.--7. 1. "HCODE116,Huffman code 116" line.long 0xEC "JPEG_HUFFENC_AC0_59,JPEG Huffman encoder AC0" hexmask.long.byte 0xEC 24.--27. 1. "HLEN119,Huffman length 119" hexmask.long.byte 0xEC 16.--23. 1. "HCODE119,Huffman code 119" newline hexmask.long.byte 0xEC 8.--11. 1. "HLEN118,Huffman length 118" hexmask.long.byte 0xEC 0.--7. 1. "HCODE118,Huffman code 118" line.long 0xF0 "JPEG_HUFFENC_AC0_60,JPEG Huffman encoder AC0" hexmask.long.byte 0xF0 24.--27. 1. "HLEN121,Huffman length 121" hexmask.long.byte 0xF0 16.--23. 1. "HCODE121,Huffman code 121" newline hexmask.long.byte 0xF0 8.--11. 1. "HLEN120,Huffman length 120" hexmask.long.byte 0xF0 0.--7. 1. "HCODE120,Huffman code 120" line.long 0xF4 "JPEG_HUFFENC_AC0_61,JPEG Huffman encoder AC0" hexmask.long.byte 0xF4 24.--27. 1. "HLEN123,Huffman length 123" hexmask.long.byte 0xF4 16.--23. 1. "HCODE123,Huffman code 123" newline hexmask.long.byte 0xF4 8.--11. 1. "HLEN122,Huffman length 122" hexmask.long.byte 0xF4 0.--7. 1. "HCODE122,Huffman code 122" line.long 0xF8 "JPEG_HUFFENC_AC0_62,JPEG Huffman encoder AC0" hexmask.long.byte 0xF8 24.--27. 1. "HLEN125,Huffman length 125" hexmask.long.byte 0xF8 16.--23. 1. "HCODE125,Huffman code 125" newline hexmask.long.byte 0xF8 8.--11. 1. "HLEN124,Huffman length 124" hexmask.long.byte 0xF8 0.--7. 1. "HCODE124,Huffman code 124" line.long 0xFC "JPEG_HUFFENC_AC0_63,JPEG Huffman encoder AC0" hexmask.long.byte 0xFC 24.--27. 1. "HLEN127,Huffman length 127" hexmask.long.byte 0xFC 16.--23. 1. "HCODE127,Huffman code 127" newline hexmask.long.byte 0xFC 8.--11. 1. "HLEN126,Huffman length 126" hexmask.long.byte 0xFC 0.--7. 1. "HCODE126,Huffman code 126" line.long 0x100 "JPEG_HUFFENC_AC0_64,JPEG Huffman encoder AC0" hexmask.long.byte 0x100 24.--27. 1. "HLEN129,Huffman length 129" hexmask.long.byte 0x100 16.--23. 1. "HCODE129,Huffman code 129" newline hexmask.long.byte 0x100 8.--11. 1. "HLEN128,Huffman length 128" hexmask.long.byte 0x100 0.--7. 1. "HCODE128,Huffman code 128" line.long 0x104 "JPEG_HUFFENC_AC0_65,JPEG Huffman encoder AC0" hexmask.long.byte 0x104 24.--27. 1. "HLEN131,Huffman length 131" hexmask.long.byte 0x104 16.--23. 1. "HCODE131,Huffman code 131" newline hexmask.long.byte 0x104 8.--11. 1. "HLEN130,Huffman length 130" hexmask.long.byte 0x104 0.--7. 1. "HCODE130,Huffman code 130" line.long 0x108 "JPEG_HUFFENC_AC0_66,JPEG Huffman encoder AC0" hexmask.long.byte 0x108 24.--27. 1. "HLEN133,Huffman length 133" hexmask.long.byte 0x108 16.--23. 1. "HCODE133,Huffman code 133" newline hexmask.long.byte 0x108 8.--11. 1. "HLEN132,Huffman length 132" hexmask.long.byte 0x108 0.--7. 1. "HCODE132,Huffman code 132" line.long 0x10C "JPEG_HUFFENC_AC0_67,JPEG Huffman encoder AC0" hexmask.long.byte 0x10C 24.--27. 1. "HLEN135,Huffman length 135" hexmask.long.byte 0x10C 16.--23. 1. "HCODE135,Huffman code 135" newline hexmask.long.byte 0x10C 8.--11. 1. "HLEN134,Huffman length 134" hexmask.long.byte 0x10C 0.--7. 1. "HCODE134,Huffman code 134" line.long 0x110 "JPEG_HUFFENC_AC0_68,JPEG Huffman encoder AC0" hexmask.long.byte 0x110 24.--27. 1. "HLEN137,Huffman length 137" hexmask.long.byte 0x110 16.--23. 1. "HCODE137,Huffman code 137" newline hexmask.long.byte 0x110 8.--11. 1. "HLEN136,Huffman length 136" hexmask.long.byte 0x110 0.--7. 1. "HCODE136,Huffman code 136" line.long 0x114 "JPEG_HUFFENC_AC0_69,JPEG Huffman encoder AC0" hexmask.long.byte 0x114 24.--27. 1. "HLEN139,Huffman length 139" hexmask.long.byte 0x114 16.--23. 1. "HCODE139,Huffman code 139" newline hexmask.long.byte 0x114 8.--11. 1. "HLEN138,Huffman length 138" hexmask.long.byte 0x114 0.--7. 1. "HCODE138,Huffman code 138" line.long 0x118 "JPEG_HUFFENC_AC0_70,JPEG Huffman encoder AC0" hexmask.long.byte 0x118 24.--27. 1. "HLEN141,Huffman length 141" hexmask.long.byte 0x118 16.--23. 1. "HCODE141,Huffman code 141" newline hexmask.long.byte 0x118 8.--11. 1. "HLEN140,Huffman length 140" hexmask.long.byte 0x118 0.--7. 1. "HCODE140,Huffman code 140" line.long 0x11C "JPEG_HUFFENC_AC0_71,JPEG Huffman encoder AC0" hexmask.long.byte 0x11C 24.--27. 1. "HLEN143,Huffman length 143" hexmask.long.byte 0x11C 16.--23. 1. "HCODE143,Huffman code 143" newline hexmask.long.byte 0x11C 8.--11. 1. "HLEN142,Huffman length 142" hexmask.long.byte 0x11C 0.--7. 1. "HCODE142,Huffman code 142" line.long 0x120 "JPEG_HUFFENC_AC0_72,JPEG Huffman encoder AC0" hexmask.long.byte 0x120 24.--27. 1. "HLEN145,Huffman length 145" hexmask.long.byte 0x120 16.--23. 1. "HCODE145,Huffman code 145" newline hexmask.long.byte 0x120 8.--11. 1. "HLEN144,Huffman length 144" hexmask.long.byte 0x120 0.--7. 1. "HCODE144,Huffman code 144" line.long 0x124 "JPEG_HUFFENC_AC0_73,JPEG Huffman encoder AC0" hexmask.long.byte 0x124 24.--27. 1. "HLEN147,Huffman length 147" hexmask.long.byte 0x124 16.--23. 1. "HCODE147,Huffman code 147" newline hexmask.long.byte 0x124 8.--11. 1. "HLEN146,Huffman length 146" hexmask.long.byte 0x124 0.--7. 1. "HCODE146,Huffman code 146" line.long 0x128 "JPEG_HUFFENC_AC0_74,JPEG Huffman encoder AC0" hexmask.long.byte 0x128 24.--27. 1. "HLEN149,Huffman length 149" hexmask.long.byte 0x128 16.--23. 1. "HCODE149,Huffman code 149" newline hexmask.long.byte 0x128 8.--11. 1. "HLEN148,Huffman length 148" hexmask.long.byte 0x128 0.--7. 1. "HCODE148,Huffman code 148" line.long 0x12C "JPEG_HUFFENC_AC0_75,JPEG Huffman encoder AC0" hexmask.long.byte 0x12C 24.--27. 1. "HLEN151,Huffman length 151" hexmask.long.byte 0x12C 16.--23. 1. "HCODE151,Huffman code 151" newline hexmask.long.byte 0x12C 8.--11. 1. "HLEN150,Huffman length 150" hexmask.long.byte 0x12C 0.--7. 1. "HCODE150,Huffman code 150" line.long 0x130 "JPEG_HUFFENC_AC0_76,JPEG Huffman encoder AC0" hexmask.long.byte 0x130 24.--27. 1. "HLEN153,Huffman length 153" hexmask.long.byte 0x130 16.--23. 1. "HCODE153,Huffman code 153" newline hexmask.long.byte 0x130 8.--11. 1. "HLEN152,Huffman length 152" hexmask.long.byte 0x130 0.--7. 1. "HCODE152,Huffman code 152" line.long 0x134 "JPEG_HUFFENC_AC0_77,JPEG Huffman encoder AC0" hexmask.long.byte 0x134 24.--27. 1. "HLEN155,Huffman length 155" hexmask.long.byte 0x134 16.--23. 1. "HCODE155,Huffman code 155" newline hexmask.long.byte 0x134 8.--11. 1. "HLEN154,Huffman length 154" hexmask.long.byte 0x134 0.--7. 1. "HCODE154,Huffman code 154" line.long 0x138 "JPEG_HUFFENC_AC0_78,JPEG Huffman encoder AC0" hexmask.long.byte 0x138 24.--27. 1. "HLEN157,Huffman length 157" hexmask.long.byte 0x138 16.--23. 1. "HCODE157,Huffman code 157" newline hexmask.long.byte 0x138 8.--11. 1. "HLEN156,Huffman length 156" hexmask.long.byte 0x138 0.--7. 1. "HCODE156,Huffman code 156" line.long 0x13C "JPEG_HUFFENC_AC0_79,JPEG Huffman encoder AC0" hexmask.long.byte 0x13C 24.--27. 1. "HLEN159,Huffman length 159" hexmask.long.byte 0x13C 16.--23. 1. "HCODE159,Huffman code 159" newline hexmask.long.byte 0x13C 8.--11. 1. "HLEN158,Huffman length 158" hexmask.long.byte 0x13C 0.--7. 1. "HCODE158,Huffman code 158" line.long 0x140 "JPEG_HUFFENC_AC0_80,JPEG Huffman encoder AC0" hexmask.long.byte 0x140 24.--27. 1. "HLEN161,Huffman length 161" hexmask.long.byte 0x140 16.--23. 1. "HCODE161,Huffman code 161" newline hexmask.long.byte 0x140 8.--11. 1. "HLEN160,Huffman length 160" hexmask.long.byte 0x140 0.--7. 1. "HCODE160,Huffman code 160" line.long 0x144 "JPEG_HUFFENC_AC0_81,JPEG Huffman encoder AC0" hexmask.long.byte 0x144 24.--27. 1. "HLEN163,Huffman length 163" hexmask.long.byte 0x144 16.--23. 1. "HCODE163,Huffman code 163" newline hexmask.long.byte 0x144 8.--11. 1. "HLEN162,Huffman length 162" hexmask.long.byte 0x144 0.--7. 1. "HCODE162,Huffman code 162" line.long 0x148 "JPEG_HUFFENC_AC0_82,JPEG Huffman encoder AC0" hexmask.long.byte 0x148 24.--27. 1. "HLEN165,Huffman length 165" hexmask.long.byte 0x148 16.--23. 1. "HCODE165,Huffman code 165" newline hexmask.long.byte 0x148 8.--11. 1. "HLEN164,Huffman length 164" hexmask.long.byte 0x148 0.--7. 1. "HCODE164,Huffman code 164" line.long 0x14C "JPEG_HUFFENC_AC0_83,JPEG Huffman encoder AC0" hexmask.long.byte 0x14C 24.--27. 1. "HLEN167,Huffman length 167" hexmask.long.byte 0x14C 16.--23. 1. "HCODE167,Huffman code 167" newline hexmask.long.byte 0x14C 8.--11. 1. "HLEN166,Huffman length 166" hexmask.long.byte 0x14C 0.--7. 1. "HCODE166,Huffman code 166" line.long 0x150 "JPEG_HUFFENC_AC0_84,JPEG Huffman encoder AC0" hexmask.long.byte 0x150 24.--27. 1. "HLEN169,Huffman length 169" hexmask.long.byte 0x150 16.--23. 1. "HCODE169,Huffman code 169" newline hexmask.long.byte 0x150 8.--11. 1. "HLEN168,Huffman length 168" hexmask.long.byte 0x150 0.--7. 1. "HCODE168,Huffman code 168" line.long 0x154 "JPEG_HUFFENC_AC0_85,JPEG Huffman encoder AC0" hexmask.long.byte 0x154 24.--27. 1. "HLEN171,Huffman length 171" hexmask.long.byte 0x154 16.--23. 1. "HCODE171,Huffman code 171" newline hexmask.long.byte 0x154 8.--11. 1. "HLEN170,Huffman length 170" hexmask.long.byte 0x154 0.--7. 1. "HCODE170,Huffman code 170" line.long 0x158 "JPEG_HUFFENC_AC0_86,JPEG Huffman encoder AC0" hexmask.long.byte 0x158 24.--27. 1. "HLEN173,Huffman length 173" hexmask.long.byte 0x158 16.--23. 1. "HCODE173,Huffman code 173" newline hexmask.long.byte 0x158 8.--11. 1. "HLEN172,Huffman length 172" hexmask.long.byte 0x158 0.--7. 1. "HCODE172,Huffman code 172" line.long 0x15C "JPEG_HUFFENC_AC0_87,JPEG Huffman encoder AC0" hexmask.long.byte 0x15C 24.--27. 1. "HLEN175,Huffman length 175" hexmask.long.byte 0x15C 16.--23. 1. "HCODE175,Huffman code 175" newline hexmask.long.byte 0x15C 8.--11. 1. "HLEN174,Huffman length 174" hexmask.long.byte 0x15C 0.--7. 1. "HCODE174,Huffman code 174" line.long 0x160 "JPEG_HUFFENC_AC1_0,JPEG Huffman encoder AC1" hexmask.long.byte 0x160 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x160 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x160 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x160 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x164 "JPEG_HUFFENC_AC1_1,JPEG Huffman encoder AC1" hexmask.long.byte 0x164 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x164 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x164 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x164 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x168 "JPEG_HUFFENC_AC1_2,JPEG Huffman encoder AC1" hexmask.long.byte 0x168 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x168 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x168 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x168 0.--7. 1. "HCODE4,Huffman code 4" line.long 0x16C "JPEG_HUFFENC_AC1_3,JPEG Huffman encoder AC1" hexmask.long.byte 0x16C 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0x16C 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0x16C 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0x16C 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x170 "JPEG_HUFFENC_AC1_4,JPEG Huffman encoder AC1" hexmask.long.byte 0x170 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x170 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x170 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x170 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x174 "JPEG_HUFFENC_AC1_5,JPEG Huffman encoder AC1" hexmask.long.byte 0x174 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x174 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x174 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x174 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x178 "JPEG_HUFFENC_AC1_6,JPEG Huffman encoder AC1" hexmask.long.byte 0x178 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x178 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x178 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x178 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x17C "JPEG_HUFFENC_AC1_7,JPEG Huffman encoder AC1" hexmask.long.byte 0x17C 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x17C 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x17C 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x17C 0.--7. 1. "HCODE14,Huffman code 14" line.long 0x180 "JPEG_HUFFENC_AC1_8,JPEG Huffman encoder AC1" hexmask.long.byte 0x180 24.--27. 1. "HLEN17,Huffman length 17" hexmask.long.byte 0x180 16.--23. 1. "HCODE17,Huffman code 17" newline hexmask.long.byte 0x180 8.--11. 1. "HLEN16,Huffman length 16" hexmask.long.byte 0x180 0.--7. 1. "HCODE16,Huffman code 16" line.long 0x184 "JPEG_HUFFENC_AC1_9,JPEG Huffman encoder AC1" hexmask.long.byte 0x184 24.--27. 1. "HLEN19,Huffman length 19" hexmask.long.byte 0x184 16.--23. 1. "HCODE19,Huffman code 19" newline hexmask.long.byte 0x184 8.--11. 1. "HLEN18,Huffman length 18" hexmask.long.byte 0x184 0.--7. 1. "HCODE18,Huffman code 18" line.long 0x188 "JPEG_HUFFENC_AC1_10,JPEG Huffman encoder AC1" hexmask.long.byte 0x188 24.--27. 1. "HLEN21,Huffman length 21" hexmask.long.byte 0x188 16.--23. 1. "HCODE21,Huffman code 21" newline hexmask.long.byte 0x188 8.--11. 1. "HLEN20,Huffman length 20" hexmask.long.byte 0x188 0.--7. 1. "HCODE20,Huffman code 20" line.long 0x18C "JPEG_HUFFENC_AC1_11,JPEG Huffman encoder AC1" hexmask.long.byte 0x18C 24.--27. 1. "HLEN23,Huffman length 23" hexmask.long.byte 0x18C 16.--23. 1. "HCODE23,Huffman code 23" newline hexmask.long.byte 0x18C 8.--11. 1. "HLEN22,Huffman length 22" hexmask.long.byte 0x18C 0.--7. 1. "HCODE22,Huffman code 22" line.long 0x190 "JPEG_HUFFENC_AC1_12,JPEG Huffman encoder AC1" hexmask.long.byte 0x190 24.--27. 1. "HLEN25,Huffman length 25" hexmask.long.byte 0x190 16.--23. 1. "HCODE25,Huffman code 25" newline hexmask.long.byte 0x190 8.--11. 1. "HLEN24,Huffman length 24" hexmask.long.byte 0x190 0.--7. 1. "HCODE24,Huffman code 24" line.long 0x194 "JPEG_HUFFENC_AC1_13,JPEG Huffman encoder AC1" hexmask.long.byte 0x194 24.--27. 1. "HLEN27,Huffman length 27" hexmask.long.byte 0x194 16.--23. 1. "HCODE27,Huffman code 27" newline hexmask.long.byte 0x194 8.--11. 1. "HLEN26,Huffman length 26" hexmask.long.byte 0x194 0.--7. 1. "HCODE26,Huffman code 26" line.long 0x198 "JPEG_HUFFENC_AC1_14,JPEG Huffman encoder AC1" hexmask.long.byte 0x198 24.--27. 1. "HLEN29,Huffman length 29" hexmask.long.byte 0x198 16.--23. 1. "HCODE29,Huffman code 29" newline hexmask.long.byte 0x198 8.--11. 1. "HLEN28,Huffman length 28" hexmask.long.byte 0x198 0.--7. 1. "HCODE28,Huffman code 28" line.long 0x19C "JPEG_HUFFENC_AC1_15,JPEG Huffman encoder AC1" hexmask.long.byte 0x19C 24.--27. 1. "HLEN31,Huffman length 31" hexmask.long.byte 0x19C 16.--23. 1. "HCODE31,Huffman code 31" newline hexmask.long.byte 0x19C 8.--11. 1. "HLEN30,Huffman length 30" hexmask.long.byte 0x19C 0.--7. 1. "HCODE30,Huffman code 30" line.long 0x1A0 "JPEG_HUFFENC_AC1_16,JPEG Huffman encoder AC1" hexmask.long.byte 0x1A0 24.--27. 1. "HLEN33,Huffman length 33" hexmask.long.byte 0x1A0 16.--23. 1. "HCODE33,Huffman code 33" newline hexmask.long.byte 0x1A0 8.--11. 1. "HLEN32,Huffman length 32" hexmask.long.byte 0x1A0 0.--7. 1. "HCODE32,Huffman code 32" line.long 0x1A4 "JPEG_HUFFENC_AC1_17,JPEG Huffman encoder AC1" hexmask.long.byte 0x1A4 24.--27. 1. "HLEN35,Huffman length 35" hexmask.long.byte 0x1A4 16.--23. 1. "HCODE35,Huffman code 35" newline hexmask.long.byte 0x1A4 8.--11. 1. "HLEN34,Huffman length 34" hexmask.long.byte 0x1A4 0.--7. 1. "HCODE34,Huffman code 34" line.long 0x1A8 "JPEG_HUFFENC_AC1_18,JPEG Huffman encoder AC1" hexmask.long.byte 0x1A8 24.--27. 1. "HLEN37,Huffman length 37" hexmask.long.byte 0x1A8 16.--23. 1. "HCODE37,Huffman code 37" newline hexmask.long.byte 0x1A8 8.--11. 1. "HLEN36,Huffman length 36" hexmask.long.byte 0x1A8 0.--7. 1. "HCODE36,Huffman code 36" line.long 0x1AC "JPEG_HUFFENC_AC1_19,JPEG Huffman encoder AC1" hexmask.long.byte 0x1AC 24.--27. 1. "HLEN39,Huffman length 39" hexmask.long.byte 0x1AC 16.--23. 1. "HCODE39,Huffman code 39" newline hexmask.long.byte 0x1AC 8.--11. 1. "HLEN38,Huffman length 38" hexmask.long.byte 0x1AC 0.--7. 1. "HCODE38,Huffman code 38" line.long 0x1B0 "JPEG_HUFFENC_AC1_20,JPEG Huffman encoder AC1" hexmask.long.byte 0x1B0 24.--27. 1. "HLEN41,Huffman length 41" hexmask.long.byte 0x1B0 16.--23. 1. "HCODE41,Huffman code 41" newline hexmask.long.byte 0x1B0 8.--11. 1. "HLEN40,Huffman length 40" hexmask.long.byte 0x1B0 0.--7. 1. "HCODE40,Huffman code 40" line.long 0x1B4 "JPEG_HUFFENC_AC1_21,JPEG Huffman encoder AC1" hexmask.long.byte 0x1B4 24.--27. 1. "HLEN43,Huffman length 43" hexmask.long.byte 0x1B4 16.--23. 1. "HCODE43,Huffman code 43" newline hexmask.long.byte 0x1B4 8.--11. 1. "HLEN42,Huffman length 42" hexmask.long.byte 0x1B4 0.--7. 1. "HCODE42,Huffman code 42" line.long 0x1B8 "JPEG_HUFFENC_AC1_22,JPEG Huffman encoder AC1" hexmask.long.byte 0x1B8 24.--27. 1. "HLEN45,Huffman length 45" hexmask.long.byte 0x1B8 16.--23. 1. "HCODE45,Huffman code 45" newline hexmask.long.byte 0x1B8 8.--11. 1. "HLEN44,Huffman length 44" hexmask.long.byte 0x1B8 0.--7. 1. "HCODE44,Huffman code 44" line.long 0x1BC "JPEG_HUFFENC_AC1_23,JPEG Huffman encoder AC1" hexmask.long.byte 0x1BC 24.--27. 1. "HLEN47,Huffman length 47" hexmask.long.byte 0x1BC 16.--23. 1. "HCODE47,Huffman code 47" newline hexmask.long.byte 0x1BC 8.--11. 1. "HLEN46,Huffman length 46" hexmask.long.byte 0x1BC 0.--7. 1. "HCODE46,Huffman code 46" line.long 0x1C0 "JPEG_HUFFENC_AC1_24,JPEG Huffman encoder AC1" hexmask.long.byte 0x1C0 24.--27. 1. "HLEN49,Huffman length 49" hexmask.long.byte 0x1C0 16.--23. 1. "HCODE49,Huffman code 49" newline hexmask.long.byte 0x1C0 8.--11. 1. "HLEN48,Huffman length 48" hexmask.long.byte 0x1C0 0.--7. 1. "HCODE48,Huffman code 48" line.long 0x1C4 "JPEG_HUFFENC_AC1_25,JPEG Huffman encoder AC1" hexmask.long.byte 0x1C4 24.--27. 1. "HLEN51,Huffman length 51" hexmask.long.byte 0x1C4 16.--23. 1. "HCODE51,Huffman code 51" newline hexmask.long.byte 0x1C4 8.--11. 1. "HLEN50,Huffman length 50" hexmask.long.byte 0x1C4 0.--7. 1. "HCODE50,Huffman code 50" line.long 0x1C8 "JPEG_HUFFENC_AC1_26,JPEG Huffman encoder AC1" hexmask.long.byte 0x1C8 24.--27. 1. "HLEN53,Huffman length 53" hexmask.long.byte 0x1C8 16.--23. 1. "HCODE53,Huffman code 53" newline hexmask.long.byte 0x1C8 8.--11. 1. "HLEN52,Huffman length 52" hexmask.long.byte 0x1C8 0.--7. 1. "HCODE52,Huffman code 52" line.long 0x1CC "JPEG_HUFFENC_AC1_27,JPEG Huffman encoder AC1" hexmask.long.byte 0x1CC 24.--27. 1. "HLEN55,Huffman length 55" hexmask.long.byte 0x1CC 16.--23. 1. "HCODE55,Huffman code 55" newline hexmask.long.byte 0x1CC 8.--11. 1. "HLEN54,Huffman length 54" hexmask.long.byte 0x1CC 0.--7. 1. "HCODE54,Huffman code 54" line.long 0x1D0 "JPEG_HUFFENC_AC1_28,JPEG Huffman encoder AC1" hexmask.long.byte 0x1D0 24.--27. 1. "HLEN57,Huffman length 57" hexmask.long.byte 0x1D0 16.--23. 1. "HCODE57,Huffman code 57" newline hexmask.long.byte 0x1D0 8.--11. 1. "HLEN56,Huffman length 56" hexmask.long.byte 0x1D0 0.--7. 1. "HCODE56,Huffman code 56" line.long 0x1D4 "JPEG_HUFFENC_AC1_29,JPEG Huffman encoder AC1" hexmask.long.byte 0x1D4 24.--27. 1. "HLEN59,Huffman length 59" hexmask.long.byte 0x1D4 16.--23. 1. "HCODE59,Huffman code 59" newline hexmask.long.byte 0x1D4 8.--11. 1. "HLEN58,Huffman length 58" hexmask.long.byte 0x1D4 0.--7. 1. "HCODE58,Huffman code 58" line.long 0x1D8 "JPEG_HUFFENC_AC1_30,JPEG Huffman encoder AC1" hexmask.long.byte 0x1D8 24.--27. 1. "HLEN61,Huffman length 61" hexmask.long.byte 0x1D8 16.--23. 1. "HCODE61,Huffman code 61" newline hexmask.long.byte 0x1D8 8.--11. 1. "HLEN60,Huffman length 60" hexmask.long.byte 0x1D8 0.--7. 1. "HCODE60,Huffman code 60" line.long 0x1DC "JPEG_HUFFENC_AC1_31,JPEG Huffman encoder AC1" hexmask.long.byte 0x1DC 24.--27. 1. "HLEN63,Huffman length 63" hexmask.long.byte 0x1DC 16.--23. 1. "HCODE63,Huffman code 63" newline hexmask.long.byte 0x1DC 8.--11. 1. "HLEN62,Huffman length 62" hexmask.long.byte 0x1DC 0.--7. 1. "HCODE62,Huffman code 62" line.long 0x1E0 "JPEG_HUFFENC_AC1_32,JPEG Huffman encoder AC1" hexmask.long.byte 0x1E0 24.--27. 1. "HLEN65,Huffman length 65" hexmask.long.byte 0x1E0 16.--23. 1. "HCODE65,Huffman code 65" newline hexmask.long.byte 0x1E0 8.--11. 1. "HLEN64,Huffman length 64" hexmask.long.byte 0x1E0 0.--7. 1. "HCODE64,Huffman code 64" line.long 0x1E4 "JPEG_HUFFENC_AC1_33,JPEG Huffman encoder AC1" hexmask.long.byte 0x1E4 24.--27. 1. "HLEN67,Huffman length 67" hexmask.long.byte 0x1E4 16.--23. 1. "HCODE67,Huffman code 67" newline hexmask.long.byte 0x1E4 8.--11. 1. "HLEN66,Huffman length 66" hexmask.long.byte 0x1E4 0.--7. 1. "HCODE66,Huffman code 66" line.long 0x1E8 "JPEG_HUFFENC_AC1_34,JPEG Huffman encoder AC1" hexmask.long.byte 0x1E8 24.--27. 1. "HLEN69,Huffman length 69" hexmask.long.byte 0x1E8 16.--23. 1. "HCODE69,Huffman code 69" newline hexmask.long.byte 0x1E8 8.--11. 1. "HLEN68,Huffman length 68" hexmask.long.byte 0x1E8 0.--7. 1. "HCODE68,Huffman code 68" line.long 0x1EC "JPEG_HUFFENC_AC1_35,JPEG Huffman encoder AC1" hexmask.long.byte 0x1EC 24.--27. 1. "HLEN71,Huffman length 71" hexmask.long.byte 0x1EC 16.--23. 1. "HCODE71,Huffman code 71" newline hexmask.long.byte 0x1EC 8.--11. 1. "HLEN70,Huffman length 70" hexmask.long.byte 0x1EC 0.--7. 1. "HCODE70,Huffman code 70" line.long 0x1F0 "JPEG_HUFFENC_AC1_36,JPEG Huffman encoder AC1" hexmask.long.byte 0x1F0 24.--27. 1. "HLEN73,Huffman length 73" hexmask.long.byte 0x1F0 16.--23. 1. "HCODE73,Huffman code 73" newline hexmask.long.byte 0x1F0 8.--11. 1. "HLEN72,Huffman length 72" hexmask.long.byte 0x1F0 0.--7. 1. "HCODE72,Huffman code 72" line.long 0x1F4 "JPEG_HUFFENC_AC1_37,JPEG Huffman encoder AC1" hexmask.long.byte 0x1F4 24.--27. 1. "HLEN75,Huffman length 75" hexmask.long.byte 0x1F4 16.--23. 1. "HCODE75,Huffman code 75" newline hexmask.long.byte 0x1F4 8.--11. 1. "HLEN74,Huffman length 74" hexmask.long.byte 0x1F4 0.--7. 1. "HCODE74,Huffman code 74" line.long 0x1F8 "JPEG_HUFFENC_AC1_38,JPEG Huffman encoder AC1" hexmask.long.byte 0x1F8 24.--27. 1. "HLEN77,Huffman length 77" hexmask.long.byte 0x1F8 16.--23. 1. "HCODE77,Huffman code 77" newline hexmask.long.byte 0x1F8 8.--11. 1. "HLEN76,Huffman length 76" hexmask.long.byte 0x1F8 0.--7. 1. "HCODE76,Huffman code 76" line.long 0x1FC "JPEG_HUFFENC_AC1_39,JPEG Huffman encoder AC1" hexmask.long.byte 0x1FC 24.--27. 1. "HLEN79,Huffman length 79" hexmask.long.byte 0x1FC 16.--23. 1. "HCODE79,Huffman code 79" newline hexmask.long.byte 0x1FC 8.--11. 1. "HLEN78,Huffman length 78" hexmask.long.byte 0x1FC 0.--7. 1. "HCODE78,Huffman code 78" line.long 0x200 "JPEG_HUFFENC_AC1_40,JPEG Huffman encoder AC1" hexmask.long.byte 0x200 24.--27. 1. "HLEN81,Huffman length 81" hexmask.long.byte 0x200 16.--23. 1. "HCODE81,Huffman code 81" newline hexmask.long.byte 0x200 8.--11. 1. "HLEN80,Huffman length 80" hexmask.long.byte 0x200 0.--7. 1. "HCODE80,Huffman code 80" line.long 0x204 "JPEG_HUFFENC_AC1_41,JPEG Huffman encoder AC1" hexmask.long.byte 0x204 24.--27. 1. "HLEN83,Huffman length 83" hexmask.long.byte 0x204 16.--23. 1. "HCODE83,Huffman code 83" newline hexmask.long.byte 0x204 8.--11. 1. "HLEN82,Huffman length 82" hexmask.long.byte 0x204 0.--7. 1. "HCODE82,Huffman code 82" line.long 0x208 "JPEG_HUFFENC_AC1_42,JPEG Huffman encoder AC1" hexmask.long.byte 0x208 24.--27. 1. "HLEN85,Huffman length 85" hexmask.long.byte 0x208 16.--23. 1. "HCODE85,Huffman code 85" newline hexmask.long.byte 0x208 8.--11. 1. "HLEN84,Huffman length 84" hexmask.long.byte 0x208 0.--7. 1. "HCODE84,Huffman code 84" line.long 0x20C "JPEG_HUFFENC_AC1_43,JPEG Huffman encoder AC1" hexmask.long.byte 0x20C 24.--27. 1. "HLEN87,Huffman length 87" hexmask.long.byte 0x20C 16.--23. 1. "HCODE87,Huffman code 87" newline hexmask.long.byte 0x20C 8.--11. 1. "HLEN86,Huffman length 86" hexmask.long.byte 0x20C 0.--7. 1. "HCODE86,Huffman code 86" line.long 0x210 "JPEG_HUFFENC_AC1_44,JPEG Huffman encoder AC1" hexmask.long.byte 0x210 24.--27. 1. "HLEN89,Huffman length 89" hexmask.long.byte 0x210 16.--23. 1. "HCODE89,Huffman code 89" newline hexmask.long.byte 0x210 8.--11. 1. "HLEN88,Huffman length 88" hexmask.long.byte 0x210 0.--7. 1. "HCODE88,Huffman code 88" line.long 0x214 "JPEG_HUFFENC_AC1_45,JPEG Huffman encoder AC1" hexmask.long.byte 0x214 24.--27. 1. "HLEN91,Huffman length 91" hexmask.long.byte 0x214 16.--23. 1. "HCODE91,Huffman code 91" newline hexmask.long.byte 0x214 8.--11. 1. "HLEN90,Huffman length 90" hexmask.long.byte 0x214 0.--7. 1. "HCODE90,Huffman code 90" line.long 0x218 "JPEG_HUFFENC_AC1_46,JPEG Huffman encoder AC1" hexmask.long.byte 0x218 24.--27. 1. "HLEN93,Huffman length 93" hexmask.long.byte 0x218 16.--23. 1. "HCODE93,Huffman code 93" newline hexmask.long.byte 0x218 8.--11. 1. "HLEN92,Huffman length 92" hexmask.long.byte 0x218 0.--7. 1. "HCODE92,Huffman code 92" line.long 0x21C "JPEG_HUFFENC_AC1_47,JPEG Huffman encoder AC1" hexmask.long.byte 0x21C 24.--27. 1. "HLEN95,Huffman length 95" hexmask.long.byte 0x21C 16.--23. 1. "HCODE95,Huffman code 95" newline hexmask.long.byte 0x21C 8.--11. 1. "HLEN94,Huffman length 94" hexmask.long.byte 0x21C 0.--7. 1. "HCODE94,Huffman code 94" line.long 0x220 "JPEG_HUFFENC_AC1_48,JPEG Huffman encoder AC1" hexmask.long.byte 0x220 24.--27. 1. "HLEN97,Huffman length 97" hexmask.long.byte 0x220 16.--23. 1. "HCODE97,Huffman code 97" newline hexmask.long.byte 0x220 8.--11. 1. "HLEN96,Huffman length 96" hexmask.long.byte 0x220 0.--7. 1. "HCODE96,Huffman code 96" line.long 0x224 "JPEG_HUFFENC_AC1_49,JPEG Huffman encoder AC1" hexmask.long.byte 0x224 24.--27. 1. "HLEN99,Huffman length 99" hexmask.long.byte 0x224 16.--23. 1. "HCODE99,Huffman code 99" newline hexmask.long.byte 0x224 8.--11. 1. "HLEN98,Huffman length 98" hexmask.long.byte 0x224 0.--7. 1. "HCODE98,Huffman code 98" line.long 0x228 "JPEG_HUFFENC_AC1_50,JPEG Huffman encoder AC1" hexmask.long.byte 0x228 24.--27. 1. "HLEN101,Huffman length 101" hexmask.long.byte 0x228 16.--23. 1. "HCODE101,Huffman code 101" newline hexmask.long.byte 0x228 8.--11. 1. "HLEN100,Huffman length 100" hexmask.long.byte 0x228 0.--7. 1. "HCODE100,Huffman code 100" line.long 0x22C "JPEG_HUFFENC_AC1_51,JPEG Huffman encoder AC1" hexmask.long.byte 0x22C 24.--27. 1. "HLEN103,Huffman length 103" hexmask.long.byte 0x22C 16.--23. 1. "HCODE103,Huffman code 103" newline hexmask.long.byte 0x22C 8.--11. 1. "HLEN102,Huffman length 102" hexmask.long.byte 0x22C 0.--7. 1. "HCODE102,Huffman code 102" line.long 0x230 "JPEG_HUFFENC_AC1_52,JPEG Huffman encoder AC1" hexmask.long.byte 0x230 24.--27. 1. "HLEN105,Huffman length 105" hexmask.long.byte 0x230 16.--23. 1. "HCODE105,Huffman code 105" newline hexmask.long.byte 0x230 8.--11. 1. "HLEN104,Huffman length 104" hexmask.long.byte 0x230 0.--7. 1. "HCODE104,Huffman code 104" line.long 0x234 "JPEG_HUFFENC_AC1_53,JPEG Huffman encoder AC1" hexmask.long.byte 0x234 24.--27. 1. "HLEN107,Huffman length 107" hexmask.long.byte 0x234 16.--23. 1. "HCODE107,Huffman code 107" newline hexmask.long.byte 0x234 8.--11. 1. "HLEN106,Huffman length 106" hexmask.long.byte 0x234 0.--7. 1. "HCODE106,Huffman code 106" line.long 0x238 "JPEG_HUFFENC_AC1_54,JPEG Huffman encoder AC1" hexmask.long.byte 0x238 24.--27. 1. "HLEN109,Huffman length 109" hexmask.long.byte 0x238 16.--23. 1. "HCODE109,Huffman code 109" newline hexmask.long.byte 0x238 8.--11. 1. "HLEN108,Huffman length 108" hexmask.long.byte 0x238 0.--7. 1. "HCODE108,Huffman code 108" line.long 0x23C "JPEG_HUFFENC_AC1_55,JPEG Huffman encoder AC1" hexmask.long.byte 0x23C 24.--27. 1. "HLEN111,Huffman length 111" hexmask.long.byte 0x23C 16.--23. 1. "HCODE111,Huffman code 111" newline hexmask.long.byte 0x23C 8.--11. 1. "HLEN110,Huffman length 110" hexmask.long.byte 0x23C 0.--7. 1. "HCODE110,Huffman code 110" line.long 0x240 "JPEG_HUFFENC_AC1_56,JPEG Huffman encoder AC1" hexmask.long.byte 0x240 24.--27. 1. "HLEN113,Huffman length 113" hexmask.long.byte 0x240 16.--23. 1. "HCODE113,Huffman code 113" newline hexmask.long.byte 0x240 8.--11. 1. "HLEN112,Huffman length 112" hexmask.long.byte 0x240 0.--7. 1. "HCODE112,Huffman code 112" line.long 0x244 "JPEG_HUFFENC_AC1_57,JPEG Huffman encoder AC1" hexmask.long.byte 0x244 24.--27. 1. "HLEN115,Huffman length 115" hexmask.long.byte 0x244 16.--23. 1. "HCODE115,Huffman code 115" newline hexmask.long.byte 0x244 8.--11. 1. "HLEN114,Huffman length 114" hexmask.long.byte 0x244 0.--7. 1. "HCODE114,Huffman code 114" line.long 0x248 "JPEG_HUFFENC_AC1_58,JPEG Huffman encoder AC1" hexmask.long.byte 0x248 24.--27. 1. "HLEN117,Huffman length 117" hexmask.long.byte 0x248 16.--23. 1. "HCODE117,Huffman code 117" newline hexmask.long.byte 0x248 8.--11. 1. "HLEN116,Huffman length 116" hexmask.long.byte 0x248 0.--7. 1. "HCODE116,Huffman code 116" line.long 0x24C "JPEG_HUFFENC_AC1_59,JPEG Huffman encoder AC1" hexmask.long.byte 0x24C 24.--27. 1. "HLEN119,Huffman length 119" hexmask.long.byte 0x24C 16.--23. 1. "HCODE119,Huffman code 119" newline hexmask.long.byte 0x24C 8.--11. 1. "HLEN118,Huffman length 118" hexmask.long.byte 0x24C 0.--7. 1. "HCODE118,Huffman code 118" line.long 0x250 "JPEG_HUFFENC_AC1_60,JPEG Huffman encoder AC1" hexmask.long.byte 0x250 24.--27. 1. "HLEN121,Huffman length 121" hexmask.long.byte 0x250 16.--23. 1. "HCODE121,Huffman code 121" newline hexmask.long.byte 0x250 8.--11. 1. "HLEN120,Huffman length 120" hexmask.long.byte 0x250 0.--7. 1. "HCODE120,Huffman code 120" line.long 0x254 "JPEG_HUFFENC_AC1_61,JPEG Huffman encoder AC1" hexmask.long.byte 0x254 24.--27. 1. "HLEN123,Huffman length 123" hexmask.long.byte 0x254 16.--23. 1. "HCODE123,Huffman code 123" newline hexmask.long.byte 0x254 8.--11. 1. "HLEN122,Huffman length 122" hexmask.long.byte 0x254 0.--7. 1. "HCODE122,Huffman code 122" line.long 0x258 "JPEG_HUFFENC_AC1_62,JPEG Huffman encoder AC1" hexmask.long.byte 0x258 24.--27. 1. "HLEN125,Huffman length 125" hexmask.long.byte 0x258 16.--23. 1. "HCODE125,Huffman code 125" newline hexmask.long.byte 0x258 8.--11. 1. "HLEN124,Huffman length 124" hexmask.long.byte 0x258 0.--7. 1. "HCODE124,Huffman code 124" line.long 0x25C "JPEG_HUFFENC_AC1_63,JPEG Huffman encoder AC1" hexmask.long.byte 0x25C 24.--27. 1. "HLEN127,Huffman length 127" hexmask.long.byte 0x25C 16.--23. 1. "HCODE127,Huffman code 127" newline hexmask.long.byte 0x25C 8.--11. 1. "HLEN126,Huffman length 126" hexmask.long.byte 0x25C 0.--7. 1. "HCODE126,Huffman code 126" line.long 0x260 "JPEG_HUFFENC_AC1_64,JPEG Huffman encoder AC1" hexmask.long.byte 0x260 24.--27. 1. "HLEN129,Huffman length 129" hexmask.long.byte 0x260 16.--23. 1. "HCODE129,Huffman code 129" newline hexmask.long.byte 0x260 8.--11. 1. "HLEN128,Huffman length 128" hexmask.long.byte 0x260 0.--7. 1. "HCODE128,Huffman code 128" line.long 0x264 "JPEG_HUFFENC_AC1_65,JPEG Huffman encoder AC1" hexmask.long.byte 0x264 24.--27. 1. "HLEN131,Huffman length 131" hexmask.long.byte 0x264 16.--23. 1. "HCODE131,Huffman code 131" newline hexmask.long.byte 0x264 8.--11. 1. "HLEN130,Huffman length 130" hexmask.long.byte 0x264 0.--7. 1. "HCODE130,Huffman code 130" line.long 0x268 "JPEG_HUFFENC_AC1_66,JPEG Huffman encoder AC1" hexmask.long.byte 0x268 24.--27. 1. "HLEN133,Huffman length 133" hexmask.long.byte 0x268 16.--23. 1. "HCODE133,Huffman code 133" newline hexmask.long.byte 0x268 8.--11. 1. "HLEN132,Huffman length 132" hexmask.long.byte 0x268 0.--7. 1. "HCODE132,Huffman code 132" line.long 0x26C "JPEG_HUFFENC_AC1_67,JPEG Huffman encoder AC1" hexmask.long.byte 0x26C 24.--27. 1. "HLEN135,Huffman length 135" hexmask.long.byte 0x26C 16.--23. 1. "HCODE135,Huffman code 135" newline hexmask.long.byte 0x26C 8.--11. 1. "HLEN134,Huffman length 134" hexmask.long.byte 0x26C 0.--7. 1. "HCODE134,Huffman code 134" line.long 0x270 "JPEG_HUFFENC_AC1_68,JPEG Huffman encoder AC1" hexmask.long.byte 0x270 24.--27. 1. "HLEN137,Huffman length 137" hexmask.long.byte 0x270 16.--23. 1. "HCODE137,Huffman code 137" newline hexmask.long.byte 0x270 8.--11. 1. "HLEN136,Huffman length 136" hexmask.long.byte 0x270 0.--7. 1. "HCODE136,Huffman code 136" line.long 0x274 "JPEG_HUFFENC_AC1_69,JPEG Huffman encoder AC1" hexmask.long.byte 0x274 24.--27. 1. "HLEN139,Huffman length 139" hexmask.long.byte 0x274 16.--23. 1. "HCODE139,Huffman code 139" newline hexmask.long.byte 0x274 8.--11. 1. "HLEN138,Huffman length 138" hexmask.long.byte 0x274 0.--7. 1. "HCODE138,Huffman code 138" line.long 0x278 "JPEG_HUFFENC_AC1_70,JPEG Huffman encoder AC1" hexmask.long.byte 0x278 24.--27. 1. "HLEN141,Huffman length 141" hexmask.long.byte 0x278 16.--23. 1. "HCODE141,Huffman code 141" newline hexmask.long.byte 0x278 8.--11. 1. "HLEN140,Huffman length 140" hexmask.long.byte 0x278 0.--7. 1. "HCODE140,Huffman code 140" line.long 0x27C "JPEG_HUFFENC_AC1_71,JPEG Huffman encoder AC1" hexmask.long.byte 0x27C 24.--27. 1. "HLEN143,Huffman length 143" hexmask.long.byte 0x27C 16.--23. 1. "HCODE143,Huffman code 143" newline hexmask.long.byte 0x27C 8.--11. 1. "HLEN142,Huffman length 142" hexmask.long.byte 0x27C 0.--7. 1. "HCODE142,Huffman code 142" line.long 0x280 "JPEG_HUFFENC_AC1_72,JPEG Huffman encoder AC1" hexmask.long.byte 0x280 24.--27. 1. "HLEN145,Huffman length 145" hexmask.long.byte 0x280 16.--23. 1. "HCODE145,Huffman code 145" newline hexmask.long.byte 0x280 8.--11. 1. "HLEN144,Huffman length 144" hexmask.long.byte 0x280 0.--7. 1. "HCODE144,Huffman code 144" line.long 0x284 "JPEG_HUFFENC_AC1_73,JPEG Huffman encoder AC1" hexmask.long.byte 0x284 24.--27. 1. "HLEN147,Huffman length 147" hexmask.long.byte 0x284 16.--23. 1. "HCODE147,Huffman code 147" newline hexmask.long.byte 0x284 8.--11. 1. "HLEN146,Huffman length 146" hexmask.long.byte 0x284 0.--7. 1. "HCODE146,Huffman code 146" line.long 0x288 "JPEG_HUFFENC_AC1_74,JPEG Huffman encoder AC1" hexmask.long.byte 0x288 24.--27. 1. "HLEN149,Huffman length 149" hexmask.long.byte 0x288 16.--23. 1. "HCODE149,Huffman code 149" newline hexmask.long.byte 0x288 8.--11. 1. "HLEN148,Huffman length 148" hexmask.long.byte 0x288 0.--7. 1. "HCODE148,Huffman code 148" line.long 0x28C "JPEG_HUFFENC_AC1_75,JPEG Huffman encoder AC1" hexmask.long.byte 0x28C 24.--27. 1. "HLEN151,Huffman length 151" hexmask.long.byte 0x28C 16.--23. 1. "HCODE151,Huffman code 151" newline hexmask.long.byte 0x28C 8.--11. 1. "HLEN150,Huffman length 150" hexmask.long.byte 0x28C 0.--7. 1. "HCODE150,Huffman code 150" line.long 0x290 "JPEG_HUFFENC_AC1_76,JPEG Huffman encoder AC1" hexmask.long.byte 0x290 24.--27. 1. "HLEN153,Huffman length 153" hexmask.long.byte 0x290 16.--23. 1. "HCODE153,Huffman code 153" newline hexmask.long.byte 0x290 8.--11. 1. "HLEN152,Huffman length 152" hexmask.long.byte 0x290 0.--7. 1. "HCODE152,Huffman code 152" line.long 0x294 "JPEG_HUFFENC_AC1_77,JPEG Huffman encoder AC1" hexmask.long.byte 0x294 24.--27. 1. "HLEN155,Huffman length 155" hexmask.long.byte 0x294 16.--23. 1. "HCODE155,Huffman code 155" newline hexmask.long.byte 0x294 8.--11. 1. "HLEN154,Huffman length 154" hexmask.long.byte 0x294 0.--7. 1. "HCODE154,Huffman code 154" line.long 0x298 "JPEG_HUFFENC_AC1_78,JPEG Huffman encoder AC1" hexmask.long.byte 0x298 24.--27. 1. "HLEN157,Huffman length 157" hexmask.long.byte 0x298 16.--23. 1. "HCODE157,Huffman code 157" newline hexmask.long.byte 0x298 8.--11. 1. "HLEN156,Huffman length 156" hexmask.long.byte 0x298 0.--7. 1. "HCODE156,Huffman code 156" line.long 0x29C "JPEG_HUFFENC_AC1_79,JPEG Huffman encoder AC1" hexmask.long.byte 0x29C 24.--27. 1. "HLEN159,Huffman length 159" hexmask.long.byte 0x29C 16.--23. 1. "HCODE159,Huffman code 159" newline hexmask.long.byte 0x29C 8.--11. 1. "HLEN158,Huffman length 158" hexmask.long.byte 0x29C 0.--7. 1. "HCODE158,Huffman code 158" line.long 0x2A0 "JPEG_HUFFENC_AC1_80,JPEG Huffman encoder AC1" hexmask.long.byte 0x2A0 24.--27. 1. "HLEN161,Huffman length 161" hexmask.long.byte 0x2A0 16.--23. 1. "HCODE161,Huffman code 161" newline hexmask.long.byte 0x2A0 8.--11. 1. "HLEN160,Huffman length 160" hexmask.long.byte 0x2A0 0.--7. 1. "HCODE160,Huffman code 160" line.long 0x2A4 "JPEG_HUFFENC_AC1_81,JPEG Huffman encoder AC1" hexmask.long.byte 0x2A4 24.--27. 1. "HLEN163,Huffman length 163" hexmask.long.byte 0x2A4 16.--23. 1. "HCODE163,Huffman code 163" newline hexmask.long.byte 0x2A4 8.--11. 1. "HLEN162,Huffman length 162" hexmask.long.byte 0x2A4 0.--7. 1. "HCODE162,Huffman code 162" line.long 0x2A8 "JPEG_HUFFENC_AC1_82,JPEG Huffman encoder AC1" hexmask.long.byte 0x2A8 24.--27. 1. "HLEN165,Huffman length 165" hexmask.long.byte 0x2A8 16.--23. 1. "HCODE165,Huffman code 165" newline hexmask.long.byte 0x2A8 8.--11. 1. "HLEN164,Huffman length 164" hexmask.long.byte 0x2A8 0.--7. 1. "HCODE164,Huffman code 164" line.long 0x2AC "JPEG_HUFFENC_AC1_83,JPEG Huffman encoder AC1" hexmask.long.byte 0x2AC 24.--27. 1. "HLEN167,Huffman length 167" hexmask.long.byte 0x2AC 16.--23. 1. "HCODE167,Huffman code 167" newline hexmask.long.byte 0x2AC 8.--11. 1. "HLEN166,Huffman length 166" hexmask.long.byte 0x2AC 0.--7. 1. "HCODE166,Huffman code 166" line.long 0x2B0 "JPEG_HUFFENC_AC1_84,JPEG Huffman encoder AC1" hexmask.long.byte 0x2B0 24.--27. 1. "HLEN169,Huffman length 169" hexmask.long.byte 0x2B0 16.--23. 1. "HCODE169,Huffman code 169" newline hexmask.long.byte 0x2B0 8.--11. 1. "HLEN168,Huffman length 168" hexmask.long.byte 0x2B0 0.--7. 1. "HCODE168,Huffman code 168" line.long 0x2B4 "JPEG_HUFFENC_AC1_85,JPEG Huffman encoder AC1" hexmask.long.byte 0x2B4 24.--27. 1. "HLEN171,Huffman length 171" hexmask.long.byte 0x2B4 16.--23. 1. "HCODE171,Huffman code 171" newline hexmask.long.byte 0x2B4 8.--11. 1. "HLEN170,Huffman length 170" hexmask.long.byte 0x2B4 0.--7. 1. "HCODE170,Huffman code 170" line.long 0x2B8 "JPEG_HUFFENC_AC1_86,JPEG Huffman encoder AC1" hexmask.long.byte 0x2B8 24.--27. 1. "HLEN173,Huffman length 173" hexmask.long.byte 0x2B8 16.--23. 1. "HCODE173,Huffman code 173" newline hexmask.long.byte 0x2B8 8.--11. 1. "HLEN172,Huffman length 172" hexmask.long.byte 0x2B8 0.--7. 1. "HCODE172,Huffman code 172" line.long 0x2BC "JPEG_HUFFENC_AC1_87,JPEG Huffman encoder AC1" hexmask.long.byte 0x2BC 24.--27. 1. "HLEN175,Huffman length 175" hexmask.long.byte 0x2BC 16.--23. 1. "HCODE175,Huffman code 175" newline hexmask.long.byte 0x2BC 8.--11. 1. "HLEN174,Huffman length 174" hexmask.long.byte 0x2BC 0.--7. 1. "HCODE174,Huffman code 174" line.long 0x2C0 "JPEG_HUFFENC_DC0_0,JPEG Huffman encoder DC0" hexmask.long.byte 0x2C0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x2C0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x2C0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x2C0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x2C4 "JPEG_HUFFENC_DC0_1,JPEG Huffman encoder DC0" hexmask.long.byte 0x2C4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x2C4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x2C4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x2C4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x2C8 "JPEG_HUFFENC_DC0_2,JPEG Huffman encoder DC0" hexmask.long.byte 0x2C8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x2C8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x2C8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x2C8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0x2CC "JPEG_HUFFENC_DC0_3,JPEG Huffman encoder DC0" hexmask.long.byte 0x2CC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0x2CC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0x2CC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0x2CC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x2D0 "JPEG_HUFFENC_DC0_4,JPEG Huffman encoder DC0" hexmask.long.byte 0x2D0 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x2D0 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x2D0 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x2D0 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x2D4 "JPEG_HUFFENC_DC0_5,JPEG Huffman encoder DC0" hexmask.long.byte 0x2D4 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x2D4 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x2D4 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x2D4 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x2D8 "JPEG_HUFFENC_DC0_6,JPEG Huffman encoder DC0" hexmask.long.byte 0x2D8 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x2D8 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x2D8 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x2D8 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x2DC "JPEG_HUFFENC_DC0_7,JPEG Huffman encoder DC0" hexmask.long.byte 0x2DC 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x2DC 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x2DC 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x2DC 0.--7. 1. "HCODE14,Huffman code 14" line.long 0x2E0 "JPEG_HUFFENC_DC1_0,JPEG Huffman encoder DC1" hexmask.long.byte 0x2E0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x2E0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x2E0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x2E0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x2E4 "JPEG_HUFFENC_DC1_1,JPEG Huffman encoder DC1" hexmask.long.byte 0x2E4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x2E4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x2E4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x2E4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x2E8 "JPEG_HUFFENC_DC1_2,JPEG Huffman encoder DC1" hexmask.long.byte 0x2E8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x2E8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x2E8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x2E8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0x2EC "JPEG_HUFFENC_DC1_3,JPEG Huffman encoder DC1" hexmask.long.byte 0x2EC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0x2EC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0x2EC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0x2EC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x2F0 "JPEG_HUFFENC_DC1_4,JPEG Huffman encoder DC1" hexmask.long.byte 0x2F0 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x2F0 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x2F0 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x2F0 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x2F4 "JPEG_HUFFENC_DC1_5,JPEG Huffman encoder DC1" hexmask.long.byte 0x2F4 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x2F4 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x2F4 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x2F4 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x2F8 "JPEG_HUFFENC_DC1_6,JPEG Huffman encoder DC1" hexmask.long.byte 0x2F8 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x2F8 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x2F8 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x2F8 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x2FC "JPEG_HUFFENC_DC1_7,JPEG Huffman encoder DC1" hexmask.long.byte 0x2FC 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x2FC 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x2FC 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x2FC 0.--7. 1. "HCODE14,Huffman code 14" tree.end tree "JPEG_S" base ad:0x58023000 wgroup.long 0x0++0x3 line.long 0x0 "JPEG_CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start" "0: Stop/abort,1: Start" group.long 0x4++0x1B line.long 0x0 "JPEG_CONFR1,JPEG codec configuration register 1" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size" bitfld.long 0x0 8. "HDR,Header processing" "0: Disable,1: Enable" newline bitfld.long 0x0 6.--7. "NS,Number of components for scan" "0,1,2,3" bitfld.long 0x0 4.--5. "COLSPACE,Color space" "0: Grayscale (1 quantization table),1: YUV (2 quantization tables),2: RGB (3 quantization tables),3: CMYK (4 quantization tables)" newline bitfld.long 0x0 3. "DE,Codec operation as coder or decoder" "0: Code,1: Decode" bitfld.long 0x0 0.--1. "NF,Number of color components" "0: Grayscale (1 color component),1: - (2 color components),2: YUV or RGB (3 color components),3: CMYK (4 color components)" line.long 0x4 "JPEG_CONFR2,JPEG codec configuration register 2" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCUs" line.long 0x8 "JPEG_CONFR3,JPEG codec configuration register 3" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size" line.long 0xC "JPEG_CONFR4,JPEG codec configuration register 4" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of blocks" bitfld.long 0xC 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0xC 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0xC 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x10 "JPEG_CONFR5,JPEG codec configuration register 5" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of blocks" bitfld.long 0x10 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x10 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x10 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x14 "JPEG_CONFR6,JPEG codec configuration register 6" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of blocks" bitfld.long 0x14 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x14 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x14 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" line.long 0x18 "JPEG_CONFR7,JPEG codec configuration register 7" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal sampling factor" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical sampling factor" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of blocks" bitfld.long 0x18 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3" newline bitfld.long 0x18 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1" bitfld.long 0x18 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1" group.long 0x30++0x3 line.long 0x0 "JPEG_CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO flush" "0: No effect,1: Output FIFO is flushed" bitfld.long 0x0 13. "IFF,Input FIFO flush" "0: No effect,1: Input FIFO is flushed" newline bitfld.long 0x0 12. "ODMAEN,Output DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "IDMAEN,Input DMA enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "HPDIE,Header parsing done interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 5. "EOCIE,End of conversion interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO not empty interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 3. "OFTIE,Output FIFO threshold interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO not full interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 1. "IFTIE,Input FIFO threshold interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "JCEN,JPEG core enable" "0: Disabled (internal registers are reset).,1: Enabled (internal registers are accessible)." rgroup.long 0x34++0x3 line.long 0x0 "JPEG_SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec operation flag" "0: Not in progress,1: In progress" bitfld.long 0x0 6. "HPDF,Header parsing done flag" "0: Not completed,1: Completed" newline bitfld.long 0x0 5. "EOCF,End of conversion flag" "0: Not completed,1: Completed" bitfld.long 0x0 4. "OFNEF,Output FIFO not empty flag" "0: Empty (data not available),1: Not empty (data available)" newline bitfld.long 0x0 3. "OFTF,Output FIFO threshold flag" "0: Below threshold,1: At or above threshold" bitfld.long 0x0 2. "IFNFF,Input FIFO not full flag" "0: Full,1: Not full" newline bitfld.long 0x0 1. "IFTF,Input FIFO threshold flag" "0: At or above threshold,1: Below threshold." group.long 0x38++0x3 line.long 0x0 "JPEG_CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear header parsing done flag" "0: No effect,1: Clear" bitfld.long 0x0 5. "CEOCF,Clear end of conversion flag" "0: No effect,1: Clear" wgroup.long 0x40++0x3 line.long 0x0 "JPEG_DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input FIFO" rgroup.long 0x44++0x3 line.long 0x0 "JPEG_DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data output FIFO" group.long 0x50++0x4AB line.long 0x0 "JPEG_QMEM0_0,JPEG quantization memory 0" hexmask.long.byte 0x0 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x0 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x0 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x0 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x4 "JPEG_QMEM0_1,JPEG quantization memory 0" hexmask.long.byte 0x4 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x4 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x4 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x4 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x8 "JPEG_QMEM0_2,JPEG quantization memory 0" hexmask.long.byte 0x8 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x8 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x8 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x8 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0xC "JPEG_QMEM0_3,JPEG quantization memory 0" hexmask.long.byte 0xC 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0xC 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0xC 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0xC 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x10 "JPEG_QMEM0_4,JPEG quantization memory 0" hexmask.long.byte 0x10 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x10 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x10 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x10 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x14 "JPEG_QMEM0_5,JPEG quantization memory 0" hexmask.long.byte 0x14 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x14 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x14 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x14 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x18 "JPEG_QMEM0_6,JPEG quantization memory 0" hexmask.long.byte 0x18 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x18 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x18 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x18 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x1C "JPEG_QMEM0_7,JPEG quantization memory 0" hexmask.long.byte 0x1C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x1C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x1C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x1C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0x20 "JPEG_QMEM0_8,JPEG quantization memory 0" hexmask.long.byte 0x20 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0x20 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0x20 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0x20 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0x24 "JPEG_QMEM0_9,JPEG quantization memory 0" hexmask.long.byte 0x24 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0x24 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0x24 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0x24 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0x28 "JPEG_QMEM0_10,JPEG quantization memory 0" hexmask.long.byte 0x28 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0x28 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0x28 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0x28 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0x2C "JPEG_QMEM0_11,JPEG quantization memory 0" hexmask.long.byte 0x2C 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0x2C 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0x2C 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0x2C 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0x30 "JPEG_QMEM0_12,JPEG quantization memory 0" hexmask.long.byte 0x30 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0x30 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0x30 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0x30 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0x34 "JPEG_QMEM0_13,JPEG quantization memory 0" hexmask.long.byte 0x34 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0x34 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0x34 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0x34 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0x38 "JPEG_QMEM0_14,JPEG quantization memory 0" hexmask.long.byte 0x38 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0x38 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0x38 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0x38 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0x3C "JPEG_QMEM0_15,JPEG quantization memory 0" hexmask.long.byte 0x3C 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0x3C 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0x3C 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0x3C 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x40 "JPEG_QMEM1_0,JPEG quantization memory 1" hexmask.long.byte 0x40 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x40 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x40 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x40 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x44 "JPEG_QMEM1_1,JPEG quantization memory 1" hexmask.long.byte 0x44 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x44 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x44 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x44 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x48 "JPEG_QMEM1_2,JPEG quantization memory 1" hexmask.long.byte 0x48 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x48 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x48 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x48 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0x4C "JPEG_QMEM1_3,JPEG quantization memory 1" hexmask.long.byte 0x4C 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0x4C 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0x4C 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0x4C 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x50 "JPEG_QMEM1_4,JPEG quantization memory 1" hexmask.long.byte 0x50 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x50 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x50 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x50 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x54 "JPEG_QMEM1_5,JPEG quantization memory 1" hexmask.long.byte 0x54 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x54 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x54 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x54 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x58 "JPEG_QMEM1_6,JPEG quantization memory 1" hexmask.long.byte 0x58 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x58 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x58 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x58 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x5C "JPEG_QMEM1_7,JPEG quantization memory 1" hexmask.long.byte 0x5C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x5C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x5C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x5C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0x60 "JPEG_QMEM1_8,JPEG quantization memory 1" hexmask.long.byte 0x60 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0x60 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0x60 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0x60 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0x64 "JPEG_QMEM1_9,JPEG quantization memory 1" hexmask.long.byte 0x64 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0x64 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0x64 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0x64 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0x68 "JPEG_QMEM1_10,JPEG quantization memory 1" hexmask.long.byte 0x68 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0x68 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0x68 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0x68 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0x6C "JPEG_QMEM1_11,JPEG quantization memory 1" hexmask.long.byte 0x6C 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0x6C 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0x6C 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0x6C 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0x70 "JPEG_QMEM1_12,JPEG quantization memory 1" hexmask.long.byte 0x70 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0x70 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0x70 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0x70 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0x74 "JPEG_QMEM1_13,JPEG quantization memory 1" hexmask.long.byte 0x74 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0x74 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0x74 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0x74 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0x78 "JPEG_QMEM1_14,JPEG quantization memory 1" hexmask.long.byte 0x78 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0x78 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0x78 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0x78 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0x7C "JPEG_QMEM1_15,JPEG quantization memory 1" hexmask.long.byte 0x7C 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0x7C 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0x7C 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0x7C 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x80 "JPEG_QMEM2_0,JPEG quantization memory 2" hexmask.long.byte 0x80 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0x80 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0x80 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0x80 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0x84 "JPEG_QMEM2_1,JPEG quantization memory 2" hexmask.long.byte 0x84 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0x84 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0x84 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0x84 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0x88 "JPEG_QMEM2_2,JPEG quantization memory 2" hexmask.long.byte 0x88 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0x88 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0x88 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0x88 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0x8C "JPEG_QMEM2_3,JPEG quantization memory 2" hexmask.long.byte 0x8C 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0x8C 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0x8C 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0x8C 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0x90 "JPEG_QMEM2_4,JPEG quantization memory 2" hexmask.long.byte 0x90 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0x90 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0x90 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0x90 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0x94 "JPEG_QMEM2_5,JPEG quantization memory 2" hexmask.long.byte 0x94 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0x94 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0x94 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0x94 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0x98 "JPEG_QMEM2_6,JPEG quantization memory 2" hexmask.long.byte 0x98 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0x98 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0x98 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0x98 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0x9C "JPEG_QMEM2_7,JPEG quantization memory 2" hexmask.long.byte 0x9C 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0x9C 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0x9C 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0x9C 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0xA0 "JPEG_QMEM2_8,JPEG quantization memory 2" hexmask.long.byte 0xA0 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0xA0 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0xA0 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0xA0 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0xA4 "JPEG_QMEM2_9,JPEG quantization memory 2" hexmask.long.byte 0xA4 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0xA4 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0xA4 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0xA4 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0xA8 "JPEG_QMEM2_10,JPEG quantization memory 2" hexmask.long.byte 0xA8 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0xA8 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0xA8 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0xA8 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0xAC "JPEG_QMEM2_11,JPEG quantization memory 2" hexmask.long.byte 0xAC 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0xAC 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0xAC 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0xAC 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0xB0 "JPEG_QMEM2_12,JPEG quantization memory 2" hexmask.long.byte 0xB0 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0xB0 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0xB0 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0xB0 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0xB4 "JPEG_QMEM2_13,JPEG quantization memory 2" hexmask.long.byte 0xB4 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0xB4 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0xB4 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0xB4 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0xB8 "JPEG_QMEM2_14,JPEG quantization memory 2" hexmask.long.byte 0xB8 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0xB8 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0xB8 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0xB8 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0xBC "JPEG_QMEM2_15,JPEG quantization memory 2" hexmask.long.byte 0xBC 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0xBC 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0xBC 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0xBC 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0xC0 "JPEG_QMEM3_0,JPEG quantization memory 3" hexmask.long.byte 0xC0 24.--31. 1. "QCOEF3,Quantization coefficient 3" hexmask.long.byte 0xC0 16.--23. 1. "QCOEF2,Quantization coefficient 2" newline hexmask.long.byte 0xC0 8.--15. 1. "QCOEF1,Quantization coefficient 1" hexmask.long.byte 0xC0 0.--7. 1. "QCOEF0,Quantization coefficient 0" line.long 0xC4 "JPEG_QMEM3_1,JPEG quantization memory 3" hexmask.long.byte 0xC4 24.--31. 1. "QCOEF7,Quantization coefficient 7" hexmask.long.byte 0xC4 16.--23. 1. "QCOEF6,Quantization coefficient 6" newline hexmask.long.byte 0xC4 8.--15. 1. "QCOEF5,Quantization coefficient 5" hexmask.long.byte 0xC4 0.--7. 1. "QCOEF4,Quantization coefficient 4" line.long 0xC8 "JPEG_QMEM3_2,JPEG quantization memory 3" hexmask.long.byte 0xC8 24.--31. 1. "QCOEF11,Quantization coefficient 11" hexmask.long.byte 0xC8 16.--23. 1. "QCOEF10,Quantization coefficient 10" newline hexmask.long.byte 0xC8 8.--15. 1. "QCOEF9,Quantization coefficient 9" hexmask.long.byte 0xC8 0.--7. 1. "QCOEF8,Quantization coefficient 8" line.long 0xCC "JPEG_QMEM3_3,JPEG quantization memory 3" hexmask.long.byte 0xCC 24.--31. 1. "QCOEF15,Quantization coefficient 15" hexmask.long.byte 0xCC 16.--23. 1. "QCOEF14,Quantization coefficient 14" newline hexmask.long.byte 0xCC 8.--15. 1. "QCOEF13,Quantization coefficient 13" hexmask.long.byte 0xCC 0.--7. 1. "QCOEF12,Quantization coefficient 12" line.long 0xD0 "JPEG_QMEM3_4,JPEG quantization memory 3" hexmask.long.byte 0xD0 24.--31. 1. "QCOEF19,Quantization coefficient 19" hexmask.long.byte 0xD0 16.--23. 1. "QCOEF18,Quantization coefficient 18" newline hexmask.long.byte 0xD0 8.--15. 1. "QCOEF17,Quantization coefficient 17" hexmask.long.byte 0xD0 0.--7. 1. "QCOEF16,Quantization coefficient 16" line.long 0xD4 "JPEG_QMEM3_5,JPEG quantization memory 3" hexmask.long.byte 0xD4 24.--31. 1. "QCOEF23,Quantization coefficient 23" hexmask.long.byte 0xD4 16.--23. 1. "QCOEF22,Quantization coefficient 22" newline hexmask.long.byte 0xD4 8.--15. 1. "QCOEF21,Quantization coefficient 21" hexmask.long.byte 0xD4 0.--7. 1. "QCOEF20,Quantization coefficient 20" line.long 0xD8 "JPEG_QMEM3_6,JPEG quantization memory 3" hexmask.long.byte 0xD8 24.--31. 1. "QCOEF27,Quantization coefficient 27" hexmask.long.byte 0xD8 16.--23. 1. "QCOEF26,Quantization coefficient 26" newline hexmask.long.byte 0xD8 8.--15. 1. "QCOEF25,Quantization coefficient 25" hexmask.long.byte 0xD8 0.--7. 1. "QCOEF24,Quantization coefficient 24" line.long 0xDC "JPEG_QMEM3_7,JPEG quantization memory 3" hexmask.long.byte 0xDC 24.--31. 1. "QCOEF31,Quantization coefficient 31" hexmask.long.byte 0xDC 16.--23. 1. "QCOEF30,Quantization coefficient 30" newline hexmask.long.byte 0xDC 8.--15. 1. "QCOEF29,Quantization coefficient 29" hexmask.long.byte 0xDC 0.--7. 1. "QCOEF28,Quantization coefficient 28" line.long 0xE0 "JPEG_QMEM3_8,JPEG quantization memory 3" hexmask.long.byte 0xE0 24.--31. 1. "QCOEF35,Quantization coefficient 35" hexmask.long.byte 0xE0 16.--23. 1. "QCOEF34,Quantization coefficient 34" newline hexmask.long.byte 0xE0 8.--15. 1. "QCOEF33,Quantization coefficient 33" hexmask.long.byte 0xE0 0.--7. 1. "QCOEF32,Quantization coefficient 32" line.long 0xE4 "JPEG_QMEM3_9,JPEG quantization memory 3" hexmask.long.byte 0xE4 24.--31. 1. "QCOEF39,Quantization coefficient 39" hexmask.long.byte 0xE4 16.--23. 1. "QCOEF38,Quantization coefficient 38" newline hexmask.long.byte 0xE4 8.--15. 1. "QCOEF37,Quantization coefficient 37" hexmask.long.byte 0xE4 0.--7. 1. "QCOEF36,Quantization coefficient 36" line.long 0xE8 "JPEG_QMEM3_10,JPEG quantization memory 3" hexmask.long.byte 0xE8 24.--31. 1. "QCOEF43,Quantization coefficient 43" hexmask.long.byte 0xE8 16.--23. 1. "QCOEF42,Quantization coefficient 42" newline hexmask.long.byte 0xE8 8.--15. 1. "QCOEF41,Quantization coefficient 41" hexmask.long.byte 0xE8 0.--7. 1. "QCOEF40,Quantization coefficient 40" line.long 0xEC "JPEG_QMEM3_11,JPEG quantization memory 3" hexmask.long.byte 0xEC 24.--31. 1. "QCOEF47,Quantization coefficient 47" hexmask.long.byte 0xEC 16.--23. 1. "QCOEF46,Quantization coefficient 46" newline hexmask.long.byte 0xEC 8.--15. 1. "QCOEF45,Quantization coefficient 45" hexmask.long.byte 0xEC 0.--7. 1. "QCOEF44,Quantization coefficient 44" line.long 0xF0 "JPEG_QMEM3_12,JPEG quantization memory 3" hexmask.long.byte 0xF0 24.--31. 1. "QCOEF51,Quantization coefficient 51" hexmask.long.byte 0xF0 16.--23. 1. "QCOEF50,Quantization coefficient 50" newline hexmask.long.byte 0xF0 8.--15. 1. "QCOEF49,Quantization coefficient 49" hexmask.long.byte 0xF0 0.--7. 1. "QCOEF48,Quantization coefficient 48" line.long 0xF4 "JPEG_QMEM3_13,JPEG quantization memory 3" hexmask.long.byte 0xF4 24.--31. 1. "QCOEF55,Quantization coefficient 55" hexmask.long.byte 0xF4 16.--23. 1. "QCOEF54,Quantization coefficient 54" newline hexmask.long.byte 0xF4 8.--15. 1. "QCOEF53,Quantization coefficient 53" hexmask.long.byte 0xF4 0.--7. 1. "QCOEF52,Quantization coefficient 52" line.long 0xF8 "JPEG_QMEM3_14,JPEG quantization memory 3" hexmask.long.byte 0xF8 24.--31. 1. "QCOEF59,Quantization coefficient 59" hexmask.long.byte 0xF8 16.--23. 1. "QCOEF58,Quantization coefficient 58" newline hexmask.long.byte 0xF8 8.--15. 1. "QCOEF57,Quantization coefficient 57" hexmask.long.byte 0xF8 0.--7. 1. "QCOEF56,Quantization coefficient 56" line.long 0xFC "JPEG_QMEM3_15,JPEG quantization memory 3" hexmask.long.byte 0xFC 24.--31. 1. "QCOEF63,Quantization coefficient 63" hexmask.long.byte 0xFC 16.--23. 1. "QCOEF62,Quantization coefficient 62" newline hexmask.long.byte 0xFC 8.--15. 1. "QCOEF61,Quantization coefficient 61" hexmask.long.byte 0xFC 0.--7. 1. "QCOEF60,Quantization coefficient 60" line.long 0x100 "JPEG_HUFFMIN0_0,JPEG Huffman min" hexmask.long 0x100 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x104 "JPEG_HUFFMIN0_1,JPEG Huffman min" hexmask.long 0x104 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x108 "JPEG_HUFFMIN0_2,JPEG Huffman min" hexmask.long 0x108 0.--31. 1. "DATA0,Minimum Huffman value" line.long 0x10C "JPEG_HUFFMIN0_3,JPEG Huffman min 0" hexmask.long.byte 0x10C 0.--3. 1. "DATA0,Minimum Huffman value" line.long 0x110 "JPEG_HUFFMIN1_0,JPEG Huffman min" hexmask.long 0x110 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x114 "JPEG_HUFFMIN1_1,JPEG Huffman min" hexmask.long 0x114 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x118 "JPEG_HUFFMIN1_2,JPEG Huffman min" hexmask.long 0x118 0.--31. 1. "DATA1,Minimum Huffman value" line.long 0x11C "JPEG_HUFFMIN1_3,JPEG Huffman min 1" hexmask.long.byte 0x11C 0.--3. 1. "DATA1,Minimum Huffman value" line.long 0x120 "JPEG_HUFFMIN2_0,JPEG Huffman min" hexmask.long 0x120 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x124 "JPEG_HUFFMIN2_1,JPEG Huffman min" hexmask.long 0x124 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x128 "JPEG_HUFFMIN2_2,JPEG Huffman min" hexmask.long 0x128 0.--31. 1. "DATA2,Minimum Huffman value" line.long 0x12C "JPEG_HUFFMIN2_3,JPEG Huffman min 2" hexmask.long.byte 0x12C 0.--3. 1. "DATA2,Minimum Huffman value" line.long 0x130 "JPEG_HUFFMIN3_0,JPEG Huffman min" hexmask.long 0x130 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x134 "JPEG_HUFFMIN3_1,JPEG Huffman min" hexmask.long 0x134 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x138 "JPEG_HUFFMIN3_2,JPEG Huffman min" hexmask.long 0x138 0.--31. 1. "DATA3,Minimum Huffman value" line.long 0x13C "JPEG_HUFFMIN3_3,JPEG Huffman min 3" hexmask.long.byte 0x13C 0.--3. 1. "DATA3,Minimum Huffman value" line.long 0x140 "JPEG_HUFFBASE0,JPEG Huffman base" hexmask.long.word 0x140 16.--24. 1. "DATA1,Data 1" hexmask.long.word 0x140 0.--8. 1. "DATA0,Data 0" line.long 0x144 "JPEG_HUFFBASE1,JPEG Huffman base" hexmask.long.word 0x144 16.--24. 1. "DATA3,Data 3" hexmask.long.word 0x144 0.--8. 1. "DATA2,Data 2" line.long 0x148 "JPEG_HUFFBASE2,JPEG Huffman base" hexmask.long.word 0x148 16.--24. 1. "DATA5,Data 5" hexmask.long.word 0x148 0.--8. 1. "DATA4,Data 4" line.long 0x14C "JPEG_HUFFBASE3,JPEG Huffman base" hexmask.long.word 0x14C 16.--24. 1. "DATA7,Data 7" hexmask.long.word 0x14C 0.--8. 1. "DATA6,Data 6" line.long 0x150 "JPEG_HUFFBASE4,JPEG Huffman base" hexmask.long.word 0x150 16.--24. 1. "DATA9,Data 9" hexmask.long.word 0x150 0.--8. 1. "DATA8,Data 8" line.long 0x154 "JPEG_HUFFBASE5,JPEG Huffman base" hexmask.long.word 0x154 16.--24. 1. "DATA11,Data 11" hexmask.long.word 0x154 0.--8. 1. "DATA10,Data 10" line.long 0x158 "JPEG_HUFFBASE6,JPEG Huffman base" hexmask.long.word 0x158 16.--24. 1. "DATA13,Data 13" hexmask.long.word 0x158 0.--8. 1. "DATA12,Data 12" line.long 0x15C "JPEG_HUFFBASE7,JPEG Huffman base" hexmask.long.word 0x15C 16.--24. 1. "DATA15,Data 15" hexmask.long.word 0x15C 0.--8. 1. "DATA14,Data 14" line.long 0x160 "JPEG_HUFFBASE8,JPEG Huffman base" hexmask.long.word 0x160 16.--24. 1. "DATA17,Data 17" hexmask.long.word 0x160 0.--8. 1. "DATA16,Data 16" line.long 0x164 "JPEG_HUFFBASE9,JPEG Huffman base" hexmask.long.word 0x164 16.--24. 1. "DATA19,Data 19" hexmask.long.word 0x164 0.--8. 1. "DATA18,Data 18" line.long 0x168 "JPEG_HUFFBASE10,JPEG Huffman base" hexmask.long.word 0x168 16.--24. 1. "DATA21,Data 21" hexmask.long.word 0x168 0.--8. 1. "DATA20,Data 20" line.long 0x16C "JPEG_HUFFBASE11,JPEG Huffman base" hexmask.long.word 0x16C 16.--24. 1. "DATA23,Data 23" hexmask.long.word 0x16C 0.--8. 1. "DATA22,Data 22" line.long 0x170 "JPEG_HUFFBASE12,JPEG Huffman base" hexmask.long.word 0x170 16.--24. 1. "DATA25,Data 25" hexmask.long.word 0x170 0.--8. 1. "DATA24,Data 24" line.long 0x174 "JPEG_HUFFBASE13,JPEG Huffman base" hexmask.long.word 0x174 16.--24. 1. "DATA27,Data 27" hexmask.long.word 0x174 0.--8. 1. "DATA26,Data 26" line.long 0x178 "JPEG_HUFFBASE14,JPEG Huffman base" hexmask.long.word 0x178 16.--24. 1. "DATA29,Data 29" hexmask.long.word 0x178 0.--8. 1. "DATA28,Data 28" line.long 0x17C "JPEG_HUFFBASE15,JPEG Huffman base" hexmask.long.word 0x17C 16.--24. 1. "DATA31,Data 31" hexmask.long.word 0x17C 0.--8. 1. "DATA30,Data 30" line.long 0x180 "JPEG_HUFFBASE16,JPEG Huffman base" hexmask.long.word 0x180 16.--24. 1. "DATA33,Data 33" hexmask.long.word 0x180 0.--8. 1. "DATA32,Data 32" line.long 0x184 "JPEG_HUFFBASE17,JPEG Huffman base" hexmask.long.word 0x184 16.--24. 1. "DATA35,Data 35" hexmask.long.word 0x184 0.--8. 1. "DATA34,Data 34" line.long 0x188 "JPEG_HUFFBASE18,JPEG Huffman base" hexmask.long.word 0x188 16.--24. 1. "DATA37,Data 37" hexmask.long.word 0x188 0.--8. 1. "DATA36,Data 36" line.long 0x18C "JPEG_HUFFBASE19,JPEG Huffman base" hexmask.long.word 0x18C 16.--24. 1. "DATA39,Data 39" hexmask.long.word 0x18C 0.--8. 1. "DATA38,Data 38" line.long 0x190 "JPEG_HUFFBASE20,JPEG Huffman base" hexmask.long.word 0x190 16.--24. 1. "DATA41,Data 41" hexmask.long.word 0x190 0.--8. 1. "DATA40,Data 40" line.long 0x194 "JPEG_HUFFBASE21,JPEG Huffman base" hexmask.long.word 0x194 16.--24. 1. "DATA43,Data 43" hexmask.long.word 0x194 0.--8. 1. "DATA42,Data 42" line.long 0x198 "JPEG_HUFFBASE22,JPEG Huffman base" hexmask.long.word 0x198 16.--24. 1. "DATA45,Data 45" hexmask.long.word 0x198 0.--8. 1. "DATA44,Data 44" line.long 0x19C "JPEG_HUFFBASE23,JPEG Huffman base" hexmask.long.word 0x19C 16.--24. 1. "DATA47,Data 47" hexmask.long.word 0x19C 0.--8. 1. "DATA46,Data 46" line.long 0x1A0 "JPEG_HUFFBASE24,JPEG Huffman base" hexmask.long.word 0x1A0 16.--24. 1. "DATA49,Data 49" hexmask.long.word 0x1A0 0.--8. 1. "DATA48,Data 48" line.long 0x1A4 "JPEG_HUFFBASE25,JPEG Huffman base" hexmask.long.word 0x1A4 16.--24. 1. "DATA51,Data 51" hexmask.long.word 0x1A4 0.--8. 1. "DATA50,Data 50" line.long 0x1A8 "JPEG_HUFFBASE26,JPEG Huffman base" hexmask.long.word 0x1A8 16.--24. 1. "DATA53,Data 53" hexmask.long.word 0x1A8 0.--8. 1. "DATA52,Data 52" line.long 0x1AC "JPEG_HUFFBASE27,JPEG Huffman base" hexmask.long.word 0x1AC 16.--24. 1. "DATA55,Data 55" hexmask.long.word 0x1AC 0.--8. 1. "DATA54,Data 54" line.long 0x1B0 "JPEG_HUFFBASE28,JPEG Huffman base" hexmask.long.word 0x1B0 16.--24. 1. "DATA57,Data 57" hexmask.long.word 0x1B0 0.--8. 1. "DATA56,Data 56" line.long 0x1B4 "JPEG_HUFFBASE29,JPEG Huffman base" hexmask.long.word 0x1B4 16.--24. 1. "DATA59,Data 59" hexmask.long.word 0x1B4 0.--8. 1. "DATA58,Data 58" line.long 0x1B8 "JPEG_HUFFBASE30,JPEG Huffman base" hexmask.long.word 0x1B8 16.--24. 1. "DATA61,Data 61" hexmask.long.word 0x1B8 0.--8. 1. "DATA60,Data 60" line.long 0x1BC "JPEG_HUFFBASE31,JPEG Huffman base" hexmask.long.word 0x1BC 16.--24. 1. "DATA63,Data 63" hexmask.long.word 0x1BC 0.--8. 1. "DATA62,Data 62" line.long 0x1C0 "JPEG_HUFFSYMB0,JPEG Huffman symbol" hexmask.long.byte 0x1C0 24.--31. 1. "DATA3,Data 3" hexmask.long.byte 0x1C0 16.--23. 1. "DATA2,Data 2" newline hexmask.long.byte 0x1C0 8.--15. 1. "DATA1,Data 1" hexmask.long.byte 0x1C0 0.--7. 1. "DATA0,Data 0" line.long 0x1C4 "JPEG_HUFFSYMB1,JPEG Huffman symbol" hexmask.long.byte 0x1C4 24.--31. 1. "DATA7,Data 7" hexmask.long.byte 0x1C4 16.--23. 1. "DATA6,Data 6" newline hexmask.long.byte 0x1C4 8.--15. 1. "DATA5,Data 5" hexmask.long.byte 0x1C4 0.--7. 1. "DATA4,Data 4" line.long 0x1C8 "JPEG_HUFFSYMB2,JPEG Huffman symbol" hexmask.long.byte 0x1C8 24.--31. 1. "DATA11,Data 11" hexmask.long.byte 0x1C8 16.--23. 1. "DATA10,Data 10" newline hexmask.long.byte 0x1C8 8.--15. 1. "DATA9,Data 9" hexmask.long.byte 0x1C8 0.--7. 1. "DATA8,Data 8" line.long 0x1CC "JPEG_HUFFSYMB3,JPEG Huffman symbol" hexmask.long.byte 0x1CC 24.--31. 1. "DATA15,Data 15" hexmask.long.byte 0x1CC 16.--23. 1. "DATA14,Data 14" newline hexmask.long.byte 0x1CC 8.--15. 1. "DATA13,Data 13" hexmask.long.byte 0x1CC 0.--7. 1. "DATA12,Data 12" line.long 0x1D0 "JPEG_HUFFSYMB4,JPEG Huffman symbol" hexmask.long.byte 0x1D0 24.--31. 1. "DATA19,Data 19" hexmask.long.byte 0x1D0 16.--23. 1. "DATA18,Data 18" newline hexmask.long.byte 0x1D0 8.--15. 1. "DATA17,Data 17" hexmask.long.byte 0x1D0 0.--7. 1. "DATA16,Data 16" line.long 0x1D4 "JPEG_HUFFSYMB5,JPEG Huffman symbol" hexmask.long.byte 0x1D4 24.--31. 1. "DATA23,Data 23" hexmask.long.byte 0x1D4 16.--23. 1. "DATA22,Data 22" newline hexmask.long.byte 0x1D4 8.--15. 1. "DATA21,Data 21" hexmask.long.byte 0x1D4 0.--7. 1. "DATA20,Data 20" line.long 0x1D8 "JPEG_HUFFSYMB6,JPEG Huffman symbol" hexmask.long.byte 0x1D8 24.--31. 1. "DATA27,Data 27" hexmask.long.byte 0x1D8 16.--23. 1. "DATA26,Data 26" newline hexmask.long.byte 0x1D8 8.--15. 1. "DATA25,Data 25" hexmask.long.byte 0x1D8 0.--7. 1. "DATA24,Data 24" line.long 0x1DC "JPEG_HUFFSYMB7,JPEG Huffman symbol" hexmask.long.byte 0x1DC 24.--31. 1. "DATA31,Data 31" hexmask.long.byte 0x1DC 16.--23. 1. "DATA30,Data 30" newline hexmask.long.byte 0x1DC 8.--15. 1. "DATA29,Data 29" hexmask.long.byte 0x1DC 0.--7. 1. "DATA28,Data 28" line.long 0x1E0 "JPEG_HUFFSYMB8,JPEG Huffman symbol" hexmask.long.byte 0x1E0 24.--31. 1. "DATA35,Data 35" hexmask.long.byte 0x1E0 16.--23. 1. "DATA34,Data 34" newline hexmask.long.byte 0x1E0 8.--15. 1. "DATA33,Data 33" hexmask.long.byte 0x1E0 0.--7. 1. "DATA32,Data 32" line.long 0x1E4 "JPEG_HUFFSYMB9,JPEG Huffman symbol" hexmask.long.byte 0x1E4 24.--31. 1. "DATA39,Data 39" hexmask.long.byte 0x1E4 16.--23. 1. "DATA38,Data 38" newline hexmask.long.byte 0x1E4 8.--15. 1. "DATA37,Data 37" hexmask.long.byte 0x1E4 0.--7. 1. "DATA36,Data 36" line.long 0x1E8 "JPEG_HUFFSYMB10,JPEG Huffman symbol" hexmask.long.byte 0x1E8 24.--31. 1. "DATA43,Data 43" hexmask.long.byte 0x1E8 16.--23. 1. "DATA42,Data 42" newline hexmask.long.byte 0x1E8 8.--15. 1. "DATA41,Data 41" hexmask.long.byte 0x1E8 0.--7. 1. "DATA40,Data 40" line.long 0x1EC "JPEG_HUFFSYMB11,JPEG Huffman symbol" hexmask.long.byte 0x1EC 24.--31. 1. "DATA47,Data 47" hexmask.long.byte 0x1EC 16.--23. 1. "DATA46,Data 46" newline hexmask.long.byte 0x1EC 8.--15. 1. "DATA45,Data 45" hexmask.long.byte 0x1EC 0.--7. 1. "DATA44,Data 44" line.long 0x1F0 "JPEG_HUFFSYMB12,JPEG Huffman symbol" hexmask.long.byte 0x1F0 24.--31. 1. "DATA51,Data 51" hexmask.long.byte 0x1F0 16.--23. 1. "DATA50,Data 50" newline hexmask.long.byte 0x1F0 8.--15. 1. "DATA49,Data 49" hexmask.long.byte 0x1F0 0.--7. 1. "DATA48,Data 48" line.long 0x1F4 "JPEG_HUFFSYMB13,JPEG Huffman symbol" hexmask.long.byte 0x1F4 24.--31. 1. "DATA55,Data 55" hexmask.long.byte 0x1F4 16.--23. 1. "DATA54,Data 54" newline hexmask.long.byte 0x1F4 8.--15. 1. "DATA53,Data 53" hexmask.long.byte 0x1F4 0.--7. 1. "DATA52,Data 52" line.long 0x1F8 "JPEG_HUFFSYMB14,JPEG Huffman symbol" hexmask.long.byte 0x1F8 24.--31. 1. "DATA59,Data 59" hexmask.long.byte 0x1F8 16.--23. 1. "DATA58,Data 58" newline hexmask.long.byte 0x1F8 8.--15. 1. "DATA57,Data 57" hexmask.long.byte 0x1F8 0.--7. 1. "DATA56,Data 56" line.long 0x1FC "JPEG_HUFFSYMB15,JPEG Huffman symbol" hexmask.long.byte 0x1FC 24.--31. 1. "DATA63,Data 63" hexmask.long.byte 0x1FC 16.--23. 1. "DATA62,Data 62" newline hexmask.long.byte 0x1FC 8.--15. 1. "DATA61,Data 61" hexmask.long.byte 0x1FC 0.--7. 1. "DATA60,Data 60" line.long 0x200 "JPEG_HUFFSYMB16,JPEG Huffman symbol" hexmask.long.byte 0x200 24.--31. 1. "DATA67,Data 67" hexmask.long.byte 0x200 16.--23. 1. "DATA66,Data 66" newline hexmask.long.byte 0x200 8.--15. 1. "DATA65,Data 65" hexmask.long.byte 0x200 0.--7. 1. "DATA64,Data 64" line.long 0x204 "JPEG_HUFFSYMB17,JPEG Huffman symbol" hexmask.long.byte 0x204 24.--31. 1. "DATA71,Data 71" hexmask.long.byte 0x204 16.--23. 1. "DATA70,Data 70" newline hexmask.long.byte 0x204 8.--15. 1. "DATA69,Data 69" hexmask.long.byte 0x204 0.--7. 1. "DATA68,Data 68" line.long 0x208 "JPEG_HUFFSYMB18,JPEG Huffman symbol" hexmask.long.byte 0x208 24.--31. 1. "DATA75,Data 75" hexmask.long.byte 0x208 16.--23. 1. "DATA74,Data 74" newline hexmask.long.byte 0x208 8.--15. 1. "DATA73,Data 73" hexmask.long.byte 0x208 0.--7. 1. "DATA72,Data 72" line.long 0x20C "JPEG_HUFFSYMB19,JPEG Huffman symbol" hexmask.long.byte 0x20C 24.--31. 1. "DATA79,Data 79" hexmask.long.byte 0x20C 16.--23. 1. "DATA78,Data 78" newline hexmask.long.byte 0x20C 8.--15. 1. "DATA77,Data 77" hexmask.long.byte 0x20C 0.--7. 1. "DATA76,Data 76" line.long 0x210 "JPEG_HUFFSYMB20,JPEG Huffman symbol" hexmask.long.byte 0x210 24.--31. 1. "DATA83,Data 83" hexmask.long.byte 0x210 16.--23. 1. "DATA82,Data 82" newline hexmask.long.byte 0x210 8.--15. 1. "DATA81,Data 81" hexmask.long.byte 0x210 0.--7. 1. "DATA80,Data 80" line.long 0x214 "JPEG_HUFFSYMB21,JPEG Huffman symbol" hexmask.long.byte 0x214 24.--31. 1. "DATA87,Data 87" hexmask.long.byte 0x214 16.--23. 1. "DATA86,Data 86" newline hexmask.long.byte 0x214 8.--15. 1. "DATA85,Data 85" hexmask.long.byte 0x214 0.--7. 1. "DATA84,Data 84" line.long 0x218 "JPEG_HUFFSYMB22,JPEG Huffman symbol" hexmask.long.byte 0x218 24.--31. 1. "DATA91,Data 91" hexmask.long.byte 0x218 16.--23. 1. "DATA90,Data 90" newline hexmask.long.byte 0x218 8.--15. 1. "DATA89,Data 89" hexmask.long.byte 0x218 0.--7. 1. "DATA88,Data 88" line.long 0x21C "JPEG_HUFFSYMB23,JPEG Huffman symbol" hexmask.long.byte 0x21C 24.--31. 1. "DATA95,Data 95" hexmask.long.byte 0x21C 16.--23. 1. "DATA94,Data 94" newline hexmask.long.byte 0x21C 8.--15. 1. "DATA93,Data 93" hexmask.long.byte 0x21C 0.--7. 1. "DATA92,Data 92" line.long 0x220 "JPEG_HUFFSYMB24,JPEG Huffman symbol" hexmask.long.byte 0x220 24.--31. 1. "DATA99,Data 99" hexmask.long.byte 0x220 16.--23. 1. "DATA98,Data 98" newline hexmask.long.byte 0x220 8.--15. 1. "DATA97,Data 97" hexmask.long.byte 0x220 0.--7. 1. "DATA96,Data 96" line.long 0x224 "JPEG_HUFFSYMB25,JPEG Huffman symbol" hexmask.long.byte 0x224 24.--31. 1. "DATA103,Data 103" hexmask.long.byte 0x224 16.--23. 1. "DATA102,Data 102" newline hexmask.long.byte 0x224 8.--15. 1. "DATA101,Data 101" hexmask.long.byte 0x224 0.--7. 1. "DATA100,Data 100" line.long 0x228 "JPEG_HUFFSYMB26,JPEG Huffman symbol" hexmask.long.byte 0x228 24.--31. 1. "DATA107,Data 107" hexmask.long.byte 0x228 16.--23. 1. "DATA106,Data 106" newline hexmask.long.byte 0x228 8.--15. 1. "DATA105,Data 105" hexmask.long.byte 0x228 0.--7. 1. "DATA104,Data 104" line.long 0x22C "JPEG_HUFFSYMB27,JPEG Huffman symbol" hexmask.long.byte 0x22C 24.--31. 1. "DATA111,Data 111" hexmask.long.byte 0x22C 16.--23. 1. "DATA110,Data 110" newline hexmask.long.byte 0x22C 8.--15. 1. "DATA109,Data 109" hexmask.long.byte 0x22C 0.--7. 1. "DATA108,Data 108" line.long 0x230 "JPEG_HUFFSYMB28,JPEG Huffman symbol" hexmask.long.byte 0x230 24.--31. 1. "DATA115,Data 115" hexmask.long.byte 0x230 16.--23. 1. "DATA114,Data 114" newline hexmask.long.byte 0x230 8.--15. 1. "DATA113,Data 113" hexmask.long.byte 0x230 0.--7. 1. "DATA112,Data 112" line.long 0x234 "JPEG_HUFFSYMB29,JPEG Huffman symbol" hexmask.long.byte 0x234 24.--31. 1. "DATA119,Data 119" hexmask.long.byte 0x234 16.--23. 1. "DATA118,Data 118" newline hexmask.long.byte 0x234 8.--15. 1. "DATA117,Data 117" hexmask.long.byte 0x234 0.--7. 1. "DATA116,Data 116" line.long 0x238 "JPEG_HUFFSYMB30,JPEG Huffman symbol" hexmask.long.byte 0x238 24.--31. 1. "DATA123,Data 123" hexmask.long.byte 0x238 16.--23. 1. "DATA122,Data 122" newline hexmask.long.byte 0x238 8.--15. 1. "DATA121,Data 121" hexmask.long.byte 0x238 0.--7. 1. "DATA120,Data 120" line.long 0x23C "JPEG_HUFFSYMB31,JPEG Huffman symbol" hexmask.long.byte 0x23C 24.--31. 1. "DATA127,Data 127" hexmask.long.byte 0x23C 16.--23. 1. "DATA126,Data 126" newline hexmask.long.byte 0x23C 8.--15. 1. "DATA125,Data 125" hexmask.long.byte 0x23C 0.--7. 1. "DATA124,Data 124" line.long 0x240 "JPEG_HUFFSYMB32,JPEG Huffman symbol" hexmask.long.byte 0x240 24.--31. 1. "DATA131,Data 131" hexmask.long.byte 0x240 16.--23. 1. "DATA130,Data 130" newline hexmask.long.byte 0x240 8.--15. 1. "DATA129,Data 129" hexmask.long.byte 0x240 0.--7. 1. "DATA128,Data 128" line.long 0x244 "JPEG_HUFFSYMB33,JPEG Huffman symbol" hexmask.long.byte 0x244 24.--31. 1. "DATA135,Data 135" hexmask.long.byte 0x244 16.--23. 1. "DATA134,Data 134" newline hexmask.long.byte 0x244 8.--15. 1. "DATA133,Data 133" hexmask.long.byte 0x244 0.--7. 1. "DATA132,Data 132" line.long 0x248 "JPEG_HUFFSYMB34,JPEG Huffman symbol" hexmask.long.byte 0x248 24.--31. 1. "DATA139,Data 139" hexmask.long.byte 0x248 16.--23. 1. "DATA138,Data 138" newline hexmask.long.byte 0x248 8.--15. 1. "DATA137,Data 137" hexmask.long.byte 0x248 0.--7. 1. "DATA136,Data 136" line.long 0x24C "JPEG_HUFFSYMB35,JPEG Huffman symbol" hexmask.long.byte 0x24C 24.--31. 1. "DATA143,Data 143" hexmask.long.byte 0x24C 16.--23. 1. "DATA142,Data 142" newline hexmask.long.byte 0x24C 8.--15. 1. "DATA141,Data 141" hexmask.long.byte 0x24C 0.--7. 1. "DATA140,Data 140" line.long 0x250 "JPEG_HUFFSYMB36,JPEG Huffman symbol" hexmask.long.byte 0x250 24.--31. 1. "DATA147,Data 147" hexmask.long.byte 0x250 16.--23. 1. "DATA146,Data 146" newline hexmask.long.byte 0x250 8.--15. 1. "DATA145,Data 145" hexmask.long.byte 0x250 0.--7. 1. "DATA144,Data 144" line.long 0x254 "JPEG_HUFFSYMB37,JPEG Huffman symbol" hexmask.long.byte 0x254 24.--31. 1. "DATA151,Data 151" hexmask.long.byte 0x254 16.--23. 1. "DATA150,Data 150" newline hexmask.long.byte 0x254 8.--15. 1. "DATA149,Data 149" hexmask.long.byte 0x254 0.--7. 1. "DATA148,Data 148" line.long 0x258 "JPEG_HUFFSYMB38,JPEG Huffman symbol" hexmask.long.byte 0x258 24.--31. 1. "DATA155,Data 155" hexmask.long.byte 0x258 16.--23. 1. "DATA154,Data 154" newline hexmask.long.byte 0x258 8.--15. 1. "DATA153,Data 153" hexmask.long.byte 0x258 0.--7. 1. "DATA152,Data 152" line.long 0x25C "JPEG_HUFFSYMB39,JPEG Huffman symbol" hexmask.long.byte 0x25C 24.--31. 1. "DATA159,Data 159" hexmask.long.byte 0x25C 16.--23. 1. "DATA158,Data 158" newline hexmask.long.byte 0x25C 8.--15. 1. "DATA157,Data 157" hexmask.long.byte 0x25C 0.--7. 1. "DATA156,Data 156" line.long 0x260 "JPEG_HUFFSYMB40,JPEG Huffman symbol" hexmask.long.byte 0x260 24.--31. 1. "DATA163,Data 163" hexmask.long.byte 0x260 16.--23. 1. "DATA162,Data 162" newline hexmask.long.byte 0x260 8.--15. 1. "DATA161,Data 161" hexmask.long.byte 0x260 0.--7. 1. "DATA160,Data 160" line.long 0x264 "JPEG_HUFFSYMB41,JPEG Huffman symbol" hexmask.long.byte 0x264 24.--31. 1. "DATA167,Data 167" hexmask.long.byte 0x264 16.--23. 1. "DATA166,Data 166" newline hexmask.long.byte 0x264 8.--15. 1. "DATA165,Data 165" hexmask.long.byte 0x264 0.--7. 1. "DATA164,Data 164" line.long 0x268 "JPEG_HUFFSYMB42,JPEG Huffman symbol" hexmask.long.byte 0x268 24.--31. 1. "DATA171,Data 171" hexmask.long.byte 0x268 16.--23. 1. "DATA170,Data 170" newline hexmask.long.byte 0x268 8.--15. 1. "DATA169,Data 169" hexmask.long.byte 0x268 0.--7. 1. "DATA168,Data 168" line.long 0x26C "JPEG_HUFFSYMB43,JPEG Huffman symbol" hexmask.long.byte 0x26C 24.--31. 1. "DATA175,Data 175" hexmask.long.byte 0x26C 16.--23. 1. "DATA174,Data 174" newline hexmask.long.byte 0x26C 8.--15. 1. "DATA173,Data 173" hexmask.long.byte 0x26C 0.--7. 1. "DATA172,Data 172" line.long 0x270 "JPEG_HUFFSYMB44,JPEG Huffman symbol" hexmask.long.byte 0x270 24.--31. 1. "DATA179,Data 179" hexmask.long.byte 0x270 16.--23. 1. "DATA178,Data 178" newline hexmask.long.byte 0x270 8.--15. 1. "DATA177,Data 177" hexmask.long.byte 0x270 0.--7. 1. "DATA176,Data 176" line.long 0x274 "JPEG_HUFFSYMB45,JPEG Huffman symbol" hexmask.long.byte 0x274 24.--31. 1. "DATA183,Data 183" hexmask.long.byte 0x274 16.--23. 1. "DATA182,Data 182" newline hexmask.long.byte 0x274 8.--15. 1. "DATA181,Data 181" hexmask.long.byte 0x274 0.--7. 1. "DATA180,Data 180" line.long 0x278 "JPEG_HUFFSYMB46,JPEG Huffman symbol" hexmask.long.byte 0x278 24.--31. 1. "DATA187,Data 187" hexmask.long.byte 0x278 16.--23. 1. "DATA186,Data 186" newline hexmask.long.byte 0x278 8.--15. 1. "DATA185,Data 185" hexmask.long.byte 0x278 0.--7. 1. "DATA184,Data 184" line.long 0x27C "JPEG_HUFFSYMB47,JPEG Huffman symbol" hexmask.long.byte 0x27C 24.--31. 1. "DATA191,Data 191" hexmask.long.byte 0x27C 16.--23. 1. "DATA190,Data 190" newline hexmask.long.byte 0x27C 8.--15. 1. "DATA189,Data 189" hexmask.long.byte 0x27C 0.--7. 1. "DATA188,Data 188" line.long 0x280 "JPEG_HUFFSYMB48,JPEG Huffman symbol" hexmask.long.byte 0x280 24.--31. 1. "DATA195,Data 195" hexmask.long.byte 0x280 16.--23. 1. "DATA194,Data 194" newline hexmask.long.byte 0x280 8.--15. 1. "DATA193,Data 193" hexmask.long.byte 0x280 0.--7. 1. "DATA192,Data 192" line.long 0x284 "JPEG_HUFFSYMB49,JPEG Huffman symbol" hexmask.long.byte 0x284 24.--31. 1. "DATA199,Data 199" hexmask.long.byte 0x284 16.--23. 1. "DATA198,Data 198" newline hexmask.long.byte 0x284 8.--15. 1. "DATA197,Data 197" hexmask.long.byte 0x284 0.--7. 1. "DATA196,Data 196" line.long 0x288 "JPEG_HUFFSYMB50,JPEG Huffman symbol" hexmask.long.byte 0x288 24.--31. 1. "DATA203,Data 203" hexmask.long.byte 0x288 16.--23. 1. "DATA202,Data 202" newline hexmask.long.byte 0x288 8.--15. 1. "DATA201,Data 201" hexmask.long.byte 0x288 0.--7. 1. "DATA200,Data 200" line.long 0x28C "JPEG_HUFFSYMB51,JPEG Huffman symbol" hexmask.long.byte 0x28C 24.--31. 1. "DATA207,Data 207" hexmask.long.byte 0x28C 16.--23. 1. "DATA206,Data 206" newline hexmask.long.byte 0x28C 8.--15. 1. "DATA205,Data 205" hexmask.long.byte 0x28C 0.--7. 1. "DATA204,Data 204" line.long 0x290 "JPEG_HUFFSYMB52,JPEG Huffman symbol" hexmask.long.byte 0x290 24.--31. 1. "DATA211,Data 211" hexmask.long.byte 0x290 16.--23. 1. "DATA210,Data 210" newline hexmask.long.byte 0x290 8.--15. 1. "DATA209,Data 209" hexmask.long.byte 0x290 0.--7. 1. "DATA208,Data 208" line.long 0x294 "JPEG_HUFFSYMB53,JPEG Huffman symbol" hexmask.long.byte 0x294 24.--31. 1. "DATA215,Data 215" hexmask.long.byte 0x294 16.--23. 1. "DATA214,Data 214" newline hexmask.long.byte 0x294 8.--15. 1. "DATA213,Data 213" hexmask.long.byte 0x294 0.--7. 1. "DATA212,Data 212" line.long 0x298 "JPEG_HUFFSYMB54,JPEG Huffman symbol" hexmask.long.byte 0x298 24.--31. 1. "DATA219,Data 219" hexmask.long.byte 0x298 16.--23. 1. "DATA218,Data 218" newline hexmask.long.byte 0x298 8.--15. 1. "DATA217,Data 217" hexmask.long.byte 0x298 0.--7. 1. "DATA216,Data 216" line.long 0x29C "JPEG_HUFFSYMB55,JPEG Huffman symbol" hexmask.long.byte 0x29C 24.--31. 1. "DATA223,Data 223" hexmask.long.byte 0x29C 16.--23. 1. "DATA222,Data 222" newline hexmask.long.byte 0x29C 8.--15. 1. "DATA221,Data 221" hexmask.long.byte 0x29C 0.--7. 1. "DATA220,Data 220" line.long 0x2A0 "JPEG_HUFFSYMB56,JPEG Huffman symbol" hexmask.long.byte 0x2A0 24.--31. 1. "DATA227,Data 227" hexmask.long.byte 0x2A0 16.--23. 1. "DATA226,Data 226" newline hexmask.long.byte 0x2A0 8.--15. 1. "DATA225,Data 225" hexmask.long.byte 0x2A0 0.--7. 1. "DATA224,Data 224" line.long 0x2A4 "JPEG_HUFFSYMB57,JPEG Huffman symbol" hexmask.long.byte 0x2A4 24.--31. 1. "DATA231,Data 231" hexmask.long.byte 0x2A4 16.--23. 1. "DATA230,Data 230" newline hexmask.long.byte 0x2A4 8.--15. 1. "DATA229,Data 229" hexmask.long.byte 0x2A4 0.--7. 1. "DATA228,Data 228" line.long 0x2A8 "JPEG_HUFFSYMB58,JPEG Huffman symbol" hexmask.long.byte 0x2A8 24.--31. 1. "DATA235,Data 235" hexmask.long.byte 0x2A8 16.--23. 1. "DATA234,Data 234" newline hexmask.long.byte 0x2A8 8.--15. 1. "DATA233,Data 233" hexmask.long.byte 0x2A8 0.--7. 1. "DATA232,Data 232" line.long 0x2AC "JPEG_HUFFSYMB59,JPEG Huffman symbol" hexmask.long.byte 0x2AC 24.--31. 1. "DATA239,Data 239" hexmask.long.byte 0x2AC 16.--23. 1. "DATA238,Data 238" newline hexmask.long.byte 0x2AC 8.--15. 1. "DATA237,Data 237" hexmask.long.byte 0x2AC 0.--7. 1. "DATA236,Data 236" line.long 0x2B0 "JPEG_HUFFSYMB60,JPEG Huffman symbol" hexmask.long.byte 0x2B0 24.--31. 1. "DATA243,Data 243" hexmask.long.byte 0x2B0 16.--23. 1. "DATA242,Data 242" newline hexmask.long.byte 0x2B0 8.--15. 1. "DATA241,Data 241" hexmask.long.byte 0x2B0 0.--7. 1. "DATA240,Data 240" line.long 0x2B4 "JPEG_HUFFSYMB61,JPEG Huffman symbol" hexmask.long.byte 0x2B4 24.--31. 1. "DATA247,Data 247" hexmask.long.byte 0x2B4 16.--23. 1. "DATA246,Data 246" newline hexmask.long.byte 0x2B4 8.--15. 1. "DATA245,Data 245" hexmask.long.byte 0x2B4 0.--7. 1. "DATA244,Data 244" line.long 0x2B8 "JPEG_HUFFSYMB62,JPEG Huffman symbol" hexmask.long.byte 0x2B8 24.--31. 1. "DATA251,Data 251" hexmask.long.byte 0x2B8 16.--23. 1. "DATA250,Data 250" newline hexmask.long.byte 0x2B8 8.--15. 1. "DATA249,Data 249" hexmask.long.byte 0x2B8 0.--7. 1. "DATA248,Data 248" line.long 0x2BC "JPEG_HUFFSYMB63,JPEG Huffman symbol" hexmask.long.byte 0x2BC 24.--31. 1. "DATA255,Data 255" hexmask.long.byte 0x2BC 16.--23. 1. "DATA254,Data 254" newline hexmask.long.byte 0x2BC 8.--15. 1. "DATA253,Data 253" hexmask.long.byte 0x2BC 0.--7. 1. "DATA252,Data 252" line.long 0x2C0 "JPEG_HUFFSYMB64,JPEG Huffman symbol" hexmask.long.byte 0x2C0 24.--31. 1. "DATA259,Data 259" hexmask.long.byte 0x2C0 16.--23. 1. "DATA258,Data 258" newline hexmask.long.byte 0x2C0 8.--15. 1. "DATA257,Data 257" hexmask.long.byte 0x2C0 0.--7. 1. "DATA256,Data 256" line.long 0x2C4 "JPEG_HUFFSYMB65,JPEG Huffman symbol" hexmask.long.byte 0x2C4 24.--31. 1. "DATA263,Data 263" hexmask.long.byte 0x2C4 16.--23. 1. "DATA262,Data 262" newline hexmask.long.byte 0x2C4 8.--15. 1. "DATA261,Data 261" hexmask.long.byte 0x2C4 0.--7. 1. "DATA260,Data 260" line.long 0x2C8 "JPEG_HUFFSYMB66,JPEG Huffman symbol" hexmask.long.byte 0x2C8 24.--31. 1. "DATA267,Data 267" hexmask.long.byte 0x2C8 16.--23. 1. "DATA266,Data 266" newline hexmask.long.byte 0x2C8 8.--15. 1. "DATA265,Data 265" hexmask.long.byte 0x2C8 0.--7. 1. "DATA264,Data 264" line.long 0x2CC "JPEG_HUFFSYMB67,JPEG Huffman symbol" hexmask.long.byte 0x2CC 24.--31. 1. "DATA271,Data 271" hexmask.long.byte 0x2CC 16.--23. 1. "DATA270,Data 270" newline hexmask.long.byte 0x2CC 8.--15. 1. "DATA269,Data 269" hexmask.long.byte 0x2CC 0.--7. 1. "DATA268,Data 268" line.long 0x2D0 "JPEG_HUFFSYMB68,JPEG Huffman symbol" hexmask.long.byte 0x2D0 24.--31. 1. "DATA275,Data 275" hexmask.long.byte 0x2D0 16.--23. 1. "DATA274,Data 274" newline hexmask.long.byte 0x2D0 8.--15. 1. "DATA273,Data 273" hexmask.long.byte 0x2D0 0.--7. 1. "DATA272,Data 272" line.long 0x2D4 "JPEG_HUFFSYMB69,JPEG Huffman symbol" hexmask.long.byte 0x2D4 24.--31. 1. "DATA279,Data 279" hexmask.long.byte 0x2D4 16.--23. 1. "DATA278,Data 278" newline hexmask.long.byte 0x2D4 8.--15. 1. "DATA277,Data 277" hexmask.long.byte 0x2D4 0.--7. 1. "DATA276,Data 276" line.long 0x2D8 "JPEG_HUFFSYMB70,JPEG Huffman symbol" hexmask.long.byte 0x2D8 24.--31. 1. "DATA283,Data 283" hexmask.long.byte 0x2D8 16.--23. 1. "DATA282,Data 282" newline hexmask.long.byte 0x2D8 8.--15. 1. "DATA281,Data 281" hexmask.long.byte 0x2D8 0.--7. 1. "DATA280,Data 280" line.long 0x2DC "JPEG_HUFFSYMB71,JPEG Huffman symbol" hexmask.long.byte 0x2DC 24.--31. 1. "DATA287,Data 287" hexmask.long.byte 0x2DC 16.--23. 1. "DATA286,Data 286" newline hexmask.long.byte 0x2DC 8.--15. 1. "DATA285,Data 285" hexmask.long.byte 0x2DC 0.--7. 1. "DATA284,Data 284" line.long 0x2E0 "JPEG_HUFFSYMB72,JPEG Huffman symbol" hexmask.long.byte 0x2E0 24.--31. 1. "DATA291,Data 291" hexmask.long.byte 0x2E0 16.--23. 1. "DATA290,Data 290" newline hexmask.long.byte 0x2E0 8.--15. 1. "DATA289,Data 289" hexmask.long.byte 0x2E0 0.--7. 1. "DATA288,Data 288" line.long 0x2E4 "JPEG_HUFFSYMB73,JPEG Huffman symbol" hexmask.long.byte 0x2E4 24.--31. 1. "DATA295,Data 295" hexmask.long.byte 0x2E4 16.--23. 1. "DATA294,Data 294" newline hexmask.long.byte 0x2E4 8.--15. 1. "DATA293,Data 293" hexmask.long.byte 0x2E4 0.--7. 1. "DATA292,Data 292" line.long 0x2E8 "JPEG_HUFFSYMB74,JPEG Huffman symbol" hexmask.long.byte 0x2E8 24.--31. 1. "DATA299,Data 299" hexmask.long.byte 0x2E8 16.--23. 1. "DATA298,Data 298" newline hexmask.long.byte 0x2E8 8.--15. 1. "DATA297,Data 297" hexmask.long.byte 0x2E8 0.--7. 1. "DATA296,Data 296" line.long 0x2EC "JPEG_HUFFSYMB75,JPEG Huffman symbol" hexmask.long.byte 0x2EC 24.--31. 1. "DATA303,Data 303" hexmask.long.byte 0x2EC 16.--23. 1. "DATA302,Data 302" newline hexmask.long.byte 0x2EC 8.--15. 1. "DATA301,Data 301" hexmask.long.byte 0x2EC 0.--7. 1. "DATA300,Data 300" line.long 0x2F0 "JPEG_HUFFSYMB76,JPEG Huffman symbol" hexmask.long.byte 0x2F0 24.--31. 1. "DATA307,Data 307" hexmask.long.byte 0x2F0 16.--23. 1. "DATA306,Data 306" newline hexmask.long.byte 0x2F0 8.--15. 1. "DATA305,Data 305" hexmask.long.byte 0x2F0 0.--7. 1. "DATA304,Data 304" line.long 0x2F4 "JPEG_HUFFSYMB77,JPEG Huffman symbol" hexmask.long.byte 0x2F4 24.--31. 1. "DATA311,Data 311" hexmask.long.byte 0x2F4 16.--23. 1. "DATA310,Data 310" newline hexmask.long.byte 0x2F4 8.--15. 1. "DATA309,Data 309" hexmask.long.byte 0x2F4 0.--7. 1. "DATA308,Data 308" line.long 0x2F8 "JPEG_HUFFSYMB78,JPEG Huffman symbol" hexmask.long.byte 0x2F8 24.--31. 1. "DATA315,Data 315" hexmask.long.byte 0x2F8 16.--23. 1. "DATA314,Data 314" newline hexmask.long.byte 0x2F8 8.--15. 1. "DATA313,Data 313" hexmask.long.byte 0x2F8 0.--7. 1. "DATA312,Data 312" line.long 0x2FC "JPEG_HUFFSYMB79,JPEG Huffman symbol" hexmask.long.byte 0x2FC 24.--31. 1. "DATA319,Data 319" hexmask.long.byte 0x2FC 16.--23. 1. "DATA318,Data 318" newline hexmask.long.byte 0x2FC 8.--15. 1. "DATA317,Data 317" hexmask.long.byte 0x2FC 0.--7. 1. "DATA316,Data 316" line.long 0x300 "JPEG_HUFFSYMB80,JPEG Huffman symbol" hexmask.long.byte 0x300 24.--31. 1. "DATA323,Data 323" hexmask.long.byte 0x300 16.--23. 1. "DATA322,Data 322" newline hexmask.long.byte 0x300 8.--15. 1. "DATA321,Data 321" hexmask.long.byte 0x300 0.--7. 1. "DATA320,Data 320" line.long 0x304 "JPEG_HUFFSYMB81,JPEG Huffman symbol" hexmask.long.byte 0x304 24.--31. 1. "DATA327,Data 327" hexmask.long.byte 0x304 16.--23. 1. "DATA326,Data 326" newline hexmask.long.byte 0x304 8.--15. 1. "DATA325,Data 325" hexmask.long.byte 0x304 0.--7. 1. "DATA324,Data 324" line.long 0x308 "JPEG_HUFFSYMB82,JPEG Huffman symbol" hexmask.long.byte 0x308 24.--31. 1. "DATA331,Data 331" hexmask.long.byte 0x308 16.--23. 1. "DATA330,Data 330" newline hexmask.long.byte 0x308 8.--15. 1. "DATA329,Data 329" hexmask.long.byte 0x308 0.--7. 1. "DATA328,Data 328" line.long 0x30C "JPEG_HUFFSYMB83,JPEG Huffman symbol" hexmask.long.byte 0x30C 24.--31. 1. "DATA335,Data 335" hexmask.long.byte 0x30C 16.--23. 1. "DATA334,Data 334" newline hexmask.long.byte 0x30C 8.--15. 1. "DATA333,Data 333" hexmask.long.byte 0x30C 0.--7. 1. "DATA332,Data 332" line.long 0x310 "JPEG_DHTMEM0,JPEG DHT memory" hexmask.long.byte 0x310 24.--31. 1. "DATA3,Huffman table data 3" hexmask.long.byte 0x310 16.--23. 1. "DATA2,Huffman table data 2" newline hexmask.long.byte 0x310 8.--15. 1. "DATA1,Huffman table data 1" hexmask.long.byte 0x310 0.--7. 1. "DATA0,Huffman table data 0" line.long 0x314 "JPEG_DHTMEM1,JPEG DHT memory" hexmask.long.byte 0x314 24.--31. 1. "DATA7,Huffman table data 7" hexmask.long.byte 0x314 16.--23. 1. "DATA6,Huffman table data 6" newline hexmask.long.byte 0x314 8.--15. 1. "DATA5,Huffman table data 5" hexmask.long.byte 0x314 0.--7. 1. "DATA4,Huffman table data 4" line.long 0x318 "JPEG_DHTMEM2,JPEG DHT memory" hexmask.long.byte 0x318 24.--31. 1. "DATA11,Huffman table data 11" hexmask.long.byte 0x318 16.--23. 1. "DATA10,Huffman table data 10" newline hexmask.long.byte 0x318 8.--15. 1. "DATA9,Huffman table data 9" hexmask.long.byte 0x318 0.--7. 1. "DATA8,Huffman table data 8" line.long 0x31C "JPEG_DHTMEM3,JPEG DHT memory" hexmask.long.byte 0x31C 24.--31. 1. "DATA15,Huffman table data 15" hexmask.long.byte 0x31C 16.--23. 1. "DATA14,Huffman table data 14" newline hexmask.long.byte 0x31C 8.--15. 1. "DATA13,Huffman table data 13" hexmask.long.byte 0x31C 0.--7. 1. "DATA12,Huffman table data 12" line.long 0x320 "JPEG_DHTMEM4,JPEG DHT memory" hexmask.long.byte 0x320 24.--31. 1. "DATA19,Huffman table data 19" hexmask.long.byte 0x320 16.--23. 1. "DATA18,Huffman table data 18" newline hexmask.long.byte 0x320 8.--15. 1. "DATA17,Huffman table data 17" hexmask.long.byte 0x320 0.--7. 1. "DATA16,Huffman table data 16" line.long 0x324 "JPEG_DHTMEM5,JPEG DHT memory" hexmask.long.byte 0x324 24.--31. 1. "DATA23,Huffman table data 23" hexmask.long.byte 0x324 16.--23. 1. "DATA22,Huffman table data 22" newline hexmask.long.byte 0x324 8.--15. 1. "DATA21,Huffman table data 21" hexmask.long.byte 0x324 0.--7. 1. "DATA20,Huffman table data 20" line.long 0x328 "JPEG_DHTMEM6,JPEG DHT memory" hexmask.long.byte 0x328 24.--31. 1. "DATA27,Huffman table data 27" hexmask.long.byte 0x328 16.--23. 1. "DATA26,Huffman table data 26" newline hexmask.long.byte 0x328 8.--15. 1. "DATA25,Huffman table data 25" hexmask.long.byte 0x328 0.--7. 1. "DATA24,Huffman table data 24" line.long 0x32C "JPEG_DHTMEM7,JPEG DHT memory" hexmask.long.byte 0x32C 24.--31. 1. "DATA31,Huffman table data 31" hexmask.long.byte 0x32C 16.--23. 1. "DATA30,Huffman table data 30" newline hexmask.long.byte 0x32C 8.--15. 1. "DATA29,Huffman table data 29" hexmask.long.byte 0x32C 0.--7. 1. "DATA28,Huffman table data 28" line.long 0x330 "JPEG_DHTMEM8,JPEG DHT memory" hexmask.long.byte 0x330 24.--31. 1. "DATA35,Huffman table data 35" hexmask.long.byte 0x330 16.--23. 1. "DATA34,Huffman table data 34" newline hexmask.long.byte 0x330 8.--15. 1. "DATA33,Huffman table data 33" hexmask.long.byte 0x330 0.--7. 1. "DATA32,Huffman table data 32" line.long 0x334 "JPEG_DHTMEM9,JPEG DHT memory" hexmask.long.byte 0x334 24.--31. 1. "DATA39,Huffman table data 39" hexmask.long.byte 0x334 16.--23. 1. "DATA38,Huffman table data 38" newline hexmask.long.byte 0x334 8.--15. 1. "DATA37,Huffman table data 37" hexmask.long.byte 0x334 0.--7. 1. "DATA36,Huffman table data 36" line.long 0x338 "JPEG_DHTMEM10,JPEG DHT memory" hexmask.long.byte 0x338 24.--31. 1. "DATA43,Huffman table data 43" hexmask.long.byte 0x338 16.--23. 1. "DATA42,Huffman table data 42" newline hexmask.long.byte 0x338 8.--15. 1. "DATA41,Huffman table data 41" hexmask.long.byte 0x338 0.--7. 1. "DATA40,Huffman table data 40" line.long 0x33C "JPEG_DHTMEM11,JPEG DHT memory" hexmask.long.byte 0x33C 24.--31. 1. "DATA47,Huffman table data 47" hexmask.long.byte 0x33C 16.--23. 1. "DATA46,Huffman table data 46" newline hexmask.long.byte 0x33C 8.--15. 1. "DATA45,Huffman table data 45" hexmask.long.byte 0x33C 0.--7. 1. "DATA44,Huffman table data 44" line.long 0x340 "JPEG_DHTMEM12,JPEG DHT memory" hexmask.long.byte 0x340 24.--31. 1. "DATA51,Huffman table data 51" hexmask.long.byte 0x340 16.--23. 1. "DATA50,Huffman table data 50" newline hexmask.long.byte 0x340 8.--15. 1. "DATA49,Huffman table data 49" hexmask.long.byte 0x340 0.--7. 1. "DATA48,Huffman table data 48" line.long 0x344 "JPEG_DHTMEM13,JPEG DHT memory" hexmask.long.byte 0x344 24.--31. 1. "DATA55,Huffman table data 55" hexmask.long.byte 0x344 16.--23. 1. "DATA54,Huffman table data 54" newline hexmask.long.byte 0x344 8.--15. 1. "DATA53,Huffman table data 53" hexmask.long.byte 0x344 0.--7. 1. "DATA52,Huffman table data 52" line.long 0x348 "JPEG_DHTMEM14,JPEG DHT memory" hexmask.long.byte 0x348 24.--31. 1. "DATA59,Huffman table data 59" hexmask.long.byte 0x348 16.--23. 1. "DATA58,Huffman table data 58" newline hexmask.long.byte 0x348 8.--15. 1. "DATA57,Huffman table data 57" hexmask.long.byte 0x348 0.--7. 1. "DATA56,Huffman table data 56" line.long 0x34C "JPEG_DHTMEM15,JPEG DHT memory" hexmask.long.byte 0x34C 24.--31. 1. "DATA63,Huffman table data 63" hexmask.long.byte 0x34C 16.--23. 1. "DATA62,Huffman table data 62" newline hexmask.long.byte 0x34C 8.--15. 1. "DATA61,Huffman table data 61" hexmask.long.byte 0x34C 0.--7. 1. "DATA60,Huffman table data 60" line.long 0x350 "JPEG_DHTMEM16,JPEG DHT memory" hexmask.long.byte 0x350 24.--31. 1. "DATA67,Huffman table data 67" hexmask.long.byte 0x350 16.--23. 1. "DATA66,Huffman table data 66" newline hexmask.long.byte 0x350 8.--15. 1. "DATA65,Huffman table data 65" hexmask.long.byte 0x350 0.--7. 1. "DATA64,Huffman table data 64" line.long 0x354 "JPEG_DHTMEM17,JPEG DHT memory" hexmask.long.byte 0x354 24.--31. 1. "DATA71,Huffman table data 71" hexmask.long.byte 0x354 16.--23. 1. "DATA70,Huffman table data 70" newline hexmask.long.byte 0x354 8.--15. 1. "DATA69,Huffman table data 69" hexmask.long.byte 0x354 0.--7. 1. "DATA68,Huffman table data 68" line.long 0x358 "JPEG_DHTMEM18,JPEG DHT memory" hexmask.long.byte 0x358 24.--31. 1. "DATA75,Huffman table data 75" hexmask.long.byte 0x358 16.--23. 1. "DATA74,Huffman table data 74" newline hexmask.long.byte 0x358 8.--15. 1. "DATA73,Huffman table data 73" hexmask.long.byte 0x358 0.--7. 1. "DATA72,Huffman table data 72" line.long 0x35C "JPEG_DHTMEM19,JPEG DHT memory" hexmask.long.byte 0x35C 24.--31. 1. "DATA79,Huffman table data 79" hexmask.long.byte 0x35C 16.--23. 1. "DATA78,Huffman table data 78" newline hexmask.long.byte 0x35C 8.--15. 1. "DATA77,Huffman table data 77" hexmask.long.byte 0x35C 0.--7. 1. "DATA76,Huffman table data 76" line.long 0x360 "JPEG_DHTMEM20,JPEG DHT memory" hexmask.long.byte 0x360 24.--31. 1. "DATA83,Huffman table data 83" hexmask.long.byte 0x360 16.--23. 1. "DATA82,Huffman table data 82" newline hexmask.long.byte 0x360 8.--15. 1. "DATA81,Huffman table data 81" hexmask.long.byte 0x360 0.--7. 1. "DATA80,Huffman table data 80" line.long 0x364 "JPEG_DHTMEM21,JPEG DHT memory" hexmask.long.byte 0x364 24.--31. 1. "DATA87,Huffman table data 87" hexmask.long.byte 0x364 16.--23. 1. "DATA86,Huffman table data 86" newline hexmask.long.byte 0x364 8.--15. 1. "DATA85,Huffman table data 85" hexmask.long.byte 0x364 0.--7. 1. "DATA84,Huffman table data 84" line.long 0x368 "JPEG_DHTMEM22,JPEG DHT memory" hexmask.long.byte 0x368 24.--31. 1. "DATA91,Huffman table data 91" hexmask.long.byte 0x368 16.--23. 1. "DATA90,Huffman table data 90" newline hexmask.long.byte 0x368 8.--15. 1. "DATA89,Huffman table data 89" hexmask.long.byte 0x368 0.--7. 1. "DATA88,Huffman table data 88" line.long 0x36C "JPEG_DHTMEM23,JPEG DHT memory" hexmask.long.byte 0x36C 24.--31. 1. "DATA95,Huffman table data 95" hexmask.long.byte 0x36C 16.--23. 1. "DATA94,Huffman table data 94" newline hexmask.long.byte 0x36C 8.--15. 1. "DATA93,Huffman table data 93" hexmask.long.byte 0x36C 0.--7. 1. "DATA92,Huffman table data 92" line.long 0x370 "JPEG_DHTMEM24,JPEG DHT memory" hexmask.long.byte 0x370 24.--31. 1. "DATA99,Huffman table data 99" hexmask.long.byte 0x370 16.--23. 1. "DATA98,Huffman table data 98" newline hexmask.long.byte 0x370 8.--15. 1. "DATA97,Huffman table data 97" hexmask.long.byte 0x370 0.--7. 1. "DATA96,Huffman table data 96" line.long 0x374 "JPEG_DHTMEM25,JPEG DHT memory" hexmask.long.byte 0x374 24.--31. 1. "DATA103,Huffman table data 103" hexmask.long.byte 0x374 16.--23. 1. "DATA102,Huffman table data 102" newline hexmask.long.byte 0x374 8.--15. 1. "DATA101,Huffman table data 101" hexmask.long.byte 0x374 0.--7. 1. "DATA100,Huffman table data 100" line.long 0x378 "JPEG_DHTMEM26,JPEG DHT memory" hexmask.long.byte 0x378 24.--31. 1. "DATA107,Huffman table data 107" hexmask.long.byte 0x378 16.--23. 1. "DATA106,Huffman table data 106" newline hexmask.long.byte 0x378 8.--15. 1. "DATA105,Huffman table data 105" hexmask.long.byte 0x378 0.--7. 1. "DATA104,Huffman table data 104" line.long 0x37C "JPEG_DHTMEM27,JPEG DHT memory" hexmask.long.byte 0x37C 24.--31. 1. "DATA111,Huffman table data 111" hexmask.long.byte 0x37C 16.--23. 1. "DATA110,Huffman table data 110" newline hexmask.long.byte 0x37C 8.--15. 1. "DATA109,Huffman table data 109" hexmask.long.byte 0x37C 0.--7. 1. "DATA108,Huffman table data 108" line.long 0x380 "JPEG_DHTMEM28,JPEG DHT memory" hexmask.long.byte 0x380 24.--31. 1. "DATA115,Huffman table data 115" hexmask.long.byte 0x380 16.--23. 1. "DATA114,Huffman table data 114" newline hexmask.long.byte 0x380 8.--15. 1. "DATA113,Huffman table data 113" hexmask.long.byte 0x380 0.--7. 1. "DATA112,Huffman table data 112" line.long 0x384 "JPEG_DHTMEM29,JPEG DHT memory" hexmask.long.byte 0x384 24.--31. 1. "DATA119,Huffman table data 119" hexmask.long.byte 0x384 16.--23. 1. "DATA118,Huffman table data 118" newline hexmask.long.byte 0x384 8.--15. 1. "DATA117,Huffman table data 117" hexmask.long.byte 0x384 0.--7. 1. "DATA116,Huffman table data 116" line.long 0x388 "JPEG_DHTMEM30,JPEG DHT memory" hexmask.long.byte 0x388 24.--31. 1. "DATA123,Huffman table data 123" hexmask.long.byte 0x388 16.--23. 1. "DATA122,Huffman table data 122" newline hexmask.long.byte 0x388 8.--15. 1. "DATA121,Huffman table data 121" hexmask.long.byte 0x388 0.--7. 1. "DATA120,Huffman table data 120" line.long 0x38C "JPEG_DHTMEM31,JPEG DHT memory" hexmask.long.byte 0x38C 24.--31. 1. "DATA127,Huffman table data 127" hexmask.long.byte 0x38C 16.--23. 1. "DATA126,Huffman table data 126" newline hexmask.long.byte 0x38C 8.--15. 1. "DATA125,Huffman table data 125" hexmask.long.byte 0x38C 0.--7. 1. "DATA124,Huffman table data 124" line.long 0x390 "JPEG_DHTMEM32,JPEG DHT memory" hexmask.long.byte 0x390 24.--31. 1. "DATA131,Huffman table data 131" hexmask.long.byte 0x390 16.--23. 1. "DATA130,Huffman table data 130" newline hexmask.long.byte 0x390 8.--15. 1. "DATA129,Huffman table data 129" hexmask.long.byte 0x390 0.--7. 1. "DATA128,Huffman table data 128" line.long 0x394 "JPEG_DHTMEM33,JPEG DHT memory" hexmask.long.byte 0x394 24.--31. 1. "DATA135,Huffman table data 135" hexmask.long.byte 0x394 16.--23. 1. "DATA134,Huffman table data 134" newline hexmask.long.byte 0x394 8.--15. 1. "DATA133,Huffman table data 133" hexmask.long.byte 0x394 0.--7. 1. "DATA132,Huffman table data 132" line.long 0x398 "JPEG_DHTMEM34,JPEG DHT memory" hexmask.long.byte 0x398 24.--31. 1. "DATA139,Huffman table data 139" hexmask.long.byte 0x398 16.--23. 1. "DATA138,Huffman table data 138" newline hexmask.long.byte 0x398 8.--15. 1. "DATA137,Huffman table data 137" hexmask.long.byte 0x398 0.--7. 1. "DATA136,Huffman table data 136" line.long 0x39C "JPEG_DHTMEM35,JPEG DHT memory" hexmask.long.byte 0x39C 24.--31. 1. "DATA143,Huffman table data 143" hexmask.long.byte 0x39C 16.--23. 1. "DATA142,Huffman table data 142" newline hexmask.long.byte 0x39C 8.--15. 1. "DATA141,Huffman table data 141" hexmask.long.byte 0x39C 0.--7. 1. "DATA140,Huffman table data 140" line.long 0x3A0 "JPEG_DHTMEM36,JPEG DHT memory" hexmask.long.byte 0x3A0 24.--31. 1. "DATA147,Huffman table data 147" hexmask.long.byte 0x3A0 16.--23. 1. "DATA146,Huffman table data 146" newline hexmask.long.byte 0x3A0 8.--15. 1. "DATA145,Huffman table data 145" hexmask.long.byte 0x3A0 0.--7. 1. "DATA144,Huffman table data 144" line.long 0x3A4 "JPEG_DHTMEM37,JPEG DHT memory" hexmask.long.byte 0x3A4 24.--31. 1. "DATA151,Huffman table data 151" hexmask.long.byte 0x3A4 16.--23. 1. "DATA150,Huffman table data 150" newline hexmask.long.byte 0x3A4 8.--15. 1. "DATA149,Huffman table data 149" hexmask.long.byte 0x3A4 0.--7. 1. "DATA148,Huffman table data 148" line.long 0x3A8 "JPEG_DHTMEM38,JPEG DHT memory" hexmask.long.byte 0x3A8 24.--31. 1. "DATA155,Huffman table data 155" hexmask.long.byte 0x3A8 16.--23. 1. "DATA154,Huffman table data 154" newline hexmask.long.byte 0x3A8 8.--15. 1. "DATA153,Huffman table data 153" hexmask.long.byte 0x3A8 0.--7. 1. "DATA152,Huffman table data 152" line.long 0x3AC "JPEG_DHTMEM39,JPEG DHT memory" hexmask.long.byte 0x3AC 24.--31. 1. "DATA159,Huffman table data 159" hexmask.long.byte 0x3AC 16.--23. 1. "DATA158,Huffman table data 158" newline hexmask.long.byte 0x3AC 8.--15. 1. "DATA157,Huffman table data 157" hexmask.long.byte 0x3AC 0.--7. 1. "DATA156,Huffman table data 156" line.long 0x3B0 "JPEG_DHTMEM40,JPEG DHT memory" hexmask.long.byte 0x3B0 24.--31. 1. "DATA163,Huffman table data 163" hexmask.long.byte 0x3B0 16.--23. 1. "DATA162,Huffman table data 162" newline hexmask.long.byte 0x3B0 8.--15. 1. "DATA161,Huffman table data 161" hexmask.long.byte 0x3B0 0.--7. 1. "DATA160,Huffman table data 160" line.long 0x3B4 "JPEG_DHTMEM41,JPEG DHT memory" hexmask.long.byte 0x3B4 24.--31. 1. "DATA167,Huffman table data 167" hexmask.long.byte 0x3B4 16.--23. 1. "DATA166,Huffman table data 166" newline hexmask.long.byte 0x3B4 8.--15. 1. "DATA165,Huffman table data 165" hexmask.long.byte 0x3B4 0.--7. 1. "DATA164,Huffman table data 164" line.long 0x3B8 "JPEG_DHTMEM42,JPEG DHT memory" hexmask.long.byte 0x3B8 24.--31. 1. "DATA171,Huffman table data 171" hexmask.long.byte 0x3B8 16.--23. 1. "DATA170,Huffman table data 170" newline hexmask.long.byte 0x3B8 8.--15. 1. "DATA169,Huffman table data 169" hexmask.long.byte 0x3B8 0.--7. 1. "DATA168,Huffman table data 168" line.long 0x3BC "JPEG_DHTMEM43,JPEG DHT memory" hexmask.long.byte 0x3BC 24.--31. 1. "DATA175,Huffman table data 175" hexmask.long.byte 0x3BC 16.--23. 1. "DATA174,Huffman table data 174" newline hexmask.long.byte 0x3BC 8.--15. 1. "DATA173,Huffman table data 173" hexmask.long.byte 0x3BC 0.--7. 1. "DATA172,Huffman table data 172" line.long 0x3C0 "JPEG_DHTMEM44,JPEG DHT memory" hexmask.long.byte 0x3C0 24.--31. 1. "DATA179,Huffman table data 179" hexmask.long.byte 0x3C0 16.--23. 1. "DATA178,Huffman table data 178" newline hexmask.long.byte 0x3C0 8.--15. 1. "DATA177,Huffman table data 177" hexmask.long.byte 0x3C0 0.--7. 1. "DATA176,Huffman table data 176" line.long 0x3C4 "JPEG_DHTMEM45,JPEG DHT memory" hexmask.long.byte 0x3C4 24.--31. 1. "DATA183,Huffman table data 183" hexmask.long.byte 0x3C4 16.--23. 1. "DATA182,Huffman table data 182" newline hexmask.long.byte 0x3C4 8.--15. 1. "DATA181,Huffman table data 181" hexmask.long.byte 0x3C4 0.--7. 1. "DATA180,Huffman table data 180" line.long 0x3C8 "JPEG_DHTMEM46,JPEG DHT memory" hexmask.long.byte 0x3C8 24.--31. 1. "DATA187,Huffman table data 187" hexmask.long.byte 0x3C8 16.--23. 1. "DATA186,Huffman table data 186" newline hexmask.long.byte 0x3C8 8.--15. 1. "DATA185,Huffman table data 185" hexmask.long.byte 0x3C8 0.--7. 1. "DATA184,Huffman table data 184" line.long 0x3CC "JPEG_DHTMEM47,JPEG DHT memory" hexmask.long.byte 0x3CC 24.--31. 1. "DATA191,Huffman table data 191" hexmask.long.byte 0x3CC 16.--23. 1. "DATA190,Huffman table data 190" newline hexmask.long.byte 0x3CC 8.--15. 1. "DATA189,Huffman table data 189" hexmask.long.byte 0x3CC 0.--7. 1. "DATA188,Huffman table data 188" line.long 0x3D0 "JPEG_DHTMEM48,JPEG DHT memory" hexmask.long.byte 0x3D0 24.--31. 1. "DATA195,Huffman table data 195" hexmask.long.byte 0x3D0 16.--23. 1. "DATA194,Huffman table data 194" newline hexmask.long.byte 0x3D0 8.--15. 1. "DATA193,Huffman table data 193" hexmask.long.byte 0x3D0 0.--7. 1. "DATA192,Huffman table data 192" line.long 0x3D4 "JPEG_DHTMEM49,JPEG DHT memory" hexmask.long.byte 0x3D4 24.--31. 1. "DATA199,Huffman table data 199" hexmask.long.byte 0x3D4 16.--23. 1. "DATA198,Huffman table data 198" newline hexmask.long.byte 0x3D4 8.--15. 1. "DATA197,Huffman table data 197" hexmask.long.byte 0x3D4 0.--7. 1. "DATA196,Huffman table data 196" line.long 0x3D8 "JPEG_DHTMEM50,JPEG DHT memory" hexmask.long.byte 0x3D8 24.--31. 1. "DATA203,Huffman table data 203" hexmask.long.byte 0x3D8 16.--23. 1. "DATA202,Huffman table data 202" newline hexmask.long.byte 0x3D8 8.--15. 1. "DATA201,Huffman table data 201" hexmask.long.byte 0x3D8 0.--7. 1. "DATA200,Huffman table data 200" line.long 0x3DC "JPEG_DHTMEM51,JPEG DHT memory" hexmask.long.byte 0x3DC 24.--31. 1. "DATA207,Huffman table data 207" hexmask.long.byte 0x3DC 16.--23. 1. "DATA206,Huffman table data 206" newline hexmask.long.byte 0x3DC 8.--15. 1. "DATA205,Huffman table data 205" hexmask.long.byte 0x3DC 0.--7. 1. "DATA204,Huffman table data 204" line.long 0x3E0 "JPEG_DHTMEM52,JPEG DHT memory" hexmask.long.byte 0x3E0 24.--31. 1. "DATA211,Huffman table data 211" hexmask.long.byte 0x3E0 16.--23. 1. "DATA210,Huffman table data 210" newline hexmask.long.byte 0x3E0 8.--15. 1. "DATA209,Huffman table data 209" hexmask.long.byte 0x3E0 0.--7. 1. "DATA208,Huffman table data 208" line.long 0x3E4 "JPEG_DHTMEM53,JPEG DHT memory" hexmask.long.byte 0x3E4 24.--31. 1. "DATA215,Huffman table data 215" hexmask.long.byte 0x3E4 16.--23. 1. "DATA214,Huffman table data 214" newline hexmask.long.byte 0x3E4 8.--15. 1. "DATA213,Huffman table data 213" hexmask.long.byte 0x3E4 0.--7. 1. "DATA212,Huffman table data 212" line.long 0x3E8 "JPEG_DHTMEM54,JPEG DHT memory" hexmask.long.byte 0x3E8 24.--31. 1. "DATA219,Huffman table data 219" hexmask.long.byte 0x3E8 16.--23. 1. "DATA218,Huffman table data 218" newline hexmask.long.byte 0x3E8 8.--15. 1. "DATA217,Huffman table data 217" hexmask.long.byte 0x3E8 0.--7. 1. "DATA216,Huffman table data 216" line.long 0x3EC "JPEG_DHTMEM55,JPEG DHT memory" hexmask.long.byte 0x3EC 24.--31. 1. "DATA223,Huffman table data 223" hexmask.long.byte 0x3EC 16.--23. 1. "DATA222,Huffman table data 222" newline hexmask.long.byte 0x3EC 8.--15. 1. "DATA221,Huffman table data 221" hexmask.long.byte 0x3EC 0.--7. 1. "DATA220,Huffman table data 220" line.long 0x3F0 "JPEG_DHTMEM56,JPEG DHT memory" hexmask.long.byte 0x3F0 24.--31. 1. "DATA227,Huffman table data 227" hexmask.long.byte 0x3F0 16.--23. 1. "DATA226,Huffman table data 226" newline hexmask.long.byte 0x3F0 8.--15. 1. "DATA225,Huffman table data 225" hexmask.long.byte 0x3F0 0.--7. 1. "DATA224,Huffman table data 224" line.long 0x3F4 "JPEG_DHTMEM57,JPEG DHT memory" hexmask.long.byte 0x3F4 24.--31. 1. "DATA231,Huffman table data 231" hexmask.long.byte 0x3F4 16.--23. 1. "DATA230,Huffman table data 230" newline hexmask.long.byte 0x3F4 8.--15. 1. "DATA229,Huffman table data 229" hexmask.long.byte 0x3F4 0.--7. 1. "DATA228,Huffman table data 228" line.long 0x3F8 "JPEG_DHTMEM58,JPEG DHT memory" hexmask.long.byte 0x3F8 24.--31. 1. "DATA235,Huffman table data 235" hexmask.long.byte 0x3F8 16.--23. 1. "DATA234,Huffman table data 234" newline hexmask.long.byte 0x3F8 8.--15. 1. "DATA233,Huffman table data 233" hexmask.long.byte 0x3F8 0.--7. 1. "DATA232,Huffman table data 232" line.long 0x3FC "JPEG_DHTMEM59,JPEG DHT memory" hexmask.long.byte 0x3FC 24.--31. 1. "DATA239,Huffman table data 239" hexmask.long.byte 0x3FC 16.--23. 1. "DATA238,Huffman table data 238" newline hexmask.long.byte 0x3FC 8.--15. 1. "DATA237,Huffman table data 237" hexmask.long.byte 0x3FC 0.--7. 1. "DATA236,Huffman table data 236" line.long 0x400 "JPEG_DHTMEM60,JPEG DHT memory" hexmask.long.byte 0x400 24.--31. 1. "DATA243,Huffman table data 243" hexmask.long.byte 0x400 16.--23. 1. "DATA242,Huffman table data 242" newline hexmask.long.byte 0x400 8.--15. 1. "DATA241,Huffman table data 241" hexmask.long.byte 0x400 0.--7. 1. "DATA240,Huffman table data 240" line.long 0x404 "JPEG_DHTMEM61,JPEG DHT memory" hexmask.long.byte 0x404 24.--31. 1. "DATA247,Huffman table data 247" hexmask.long.byte 0x404 16.--23. 1. "DATA246,Huffman table data 246" newline hexmask.long.byte 0x404 8.--15. 1. "DATA245,Huffman table data 245" hexmask.long.byte 0x404 0.--7. 1. "DATA244,Huffman table data 244" line.long 0x408 "JPEG_DHTMEM62,JPEG DHT memory" hexmask.long.byte 0x408 24.--31. 1. "DATA251,Huffman table data 251" hexmask.long.byte 0x408 16.--23. 1. "DATA250,Huffman table data 250" newline hexmask.long.byte 0x408 8.--15. 1. "DATA249,Huffman table data 249" hexmask.long.byte 0x408 0.--7. 1. "DATA248,Huffman table data 248" line.long 0x40C "JPEG_DHTMEM63,JPEG DHT memory" hexmask.long.byte 0x40C 24.--31. 1. "DATA255,Huffman table data 255" hexmask.long.byte 0x40C 16.--23. 1. "DATA254,Huffman table data 254" newline hexmask.long.byte 0x40C 8.--15. 1. "DATA253,Huffman table data 253" hexmask.long.byte 0x40C 0.--7. 1. "DATA252,Huffman table data 252" line.long 0x410 "JPEG_DHTMEM64,JPEG DHT memory" hexmask.long.byte 0x410 24.--31. 1. "DATA259,Huffman table data 259" hexmask.long.byte 0x410 16.--23. 1. "DATA258,Huffman table data 258" newline hexmask.long.byte 0x410 8.--15. 1. "DATA257,Huffman table data 257" hexmask.long.byte 0x410 0.--7. 1. "DATA256,Huffman table data 256" line.long 0x414 "JPEG_DHTMEM65,JPEG DHT memory" hexmask.long.byte 0x414 24.--31. 1. "DATA263,Huffman table data 263" hexmask.long.byte 0x414 16.--23. 1. "DATA262,Huffman table data 262" newline hexmask.long.byte 0x414 8.--15. 1. "DATA261,Huffman table data 261" hexmask.long.byte 0x414 0.--7. 1. "DATA260,Huffman table data 260" line.long 0x418 "JPEG_DHTMEM66,JPEG DHT memory" hexmask.long.byte 0x418 24.--31. 1. "DATA267,Huffman table data 267" hexmask.long.byte 0x418 16.--23. 1. "DATA266,Huffman table data 266" newline hexmask.long.byte 0x418 8.--15. 1. "DATA265,Huffman table data 265" hexmask.long.byte 0x418 0.--7. 1. "DATA264,Huffman table data 264" line.long 0x41C "JPEG_DHTMEM67,JPEG DHT memory" hexmask.long.byte 0x41C 24.--31. 1. "DATA271,Huffman table data 271" hexmask.long.byte 0x41C 16.--23. 1. "DATA270,Huffman table data 270" newline hexmask.long.byte 0x41C 8.--15. 1. "DATA269,Huffman table data 269" hexmask.long.byte 0x41C 0.--7. 1. "DATA268,Huffman table data 268" line.long 0x420 "JPEG_DHTMEM68,JPEG DHT memory" hexmask.long.byte 0x420 24.--31. 1. "DATA275,Huffman table data 275" hexmask.long.byte 0x420 16.--23. 1. "DATA274,Huffman table data 274" newline hexmask.long.byte 0x420 8.--15. 1. "DATA273,Huffman table data 273" hexmask.long.byte 0x420 0.--7. 1. "DATA272,Huffman table data 272" line.long 0x424 "JPEG_DHTMEM69,JPEG DHT memory" hexmask.long.byte 0x424 24.--31. 1. "DATA279,Huffman table data 279" hexmask.long.byte 0x424 16.--23. 1. "DATA278,Huffman table data 278" newline hexmask.long.byte 0x424 8.--15. 1. "DATA277,Huffman table data 277" hexmask.long.byte 0x424 0.--7. 1. "DATA276,Huffman table data 276" line.long 0x428 "JPEG_DHTMEM70,JPEG DHT memory" hexmask.long.byte 0x428 24.--31. 1. "DATA283,Huffman table data 283" hexmask.long.byte 0x428 16.--23. 1. "DATA282,Huffman table data 282" newline hexmask.long.byte 0x428 8.--15. 1. "DATA281,Huffman table data 281" hexmask.long.byte 0x428 0.--7. 1. "DATA280,Huffman table data 280" line.long 0x42C "JPEG_DHTMEM71,JPEG DHT memory" hexmask.long.byte 0x42C 24.--31. 1. "DATA287,Huffman table data 287" hexmask.long.byte 0x42C 16.--23. 1. "DATA286,Huffman table data 286" newline hexmask.long.byte 0x42C 8.--15. 1. "DATA285,Huffman table data 285" hexmask.long.byte 0x42C 0.--7. 1. "DATA284,Huffman table data 284" line.long 0x430 "JPEG_DHTMEM72,JPEG DHT memory" hexmask.long.byte 0x430 24.--31. 1. "DATA291,Huffman table data 291" hexmask.long.byte 0x430 16.--23. 1. "DATA290,Huffman table data 290" newline hexmask.long.byte 0x430 8.--15. 1. "DATA289,Huffman table data 289" hexmask.long.byte 0x430 0.--7. 1. "DATA288,Huffman table data 288" line.long 0x434 "JPEG_DHTMEM73,JPEG DHT memory" hexmask.long.byte 0x434 24.--31. 1. "DATA295,Huffman table data 295" hexmask.long.byte 0x434 16.--23. 1. "DATA294,Huffman table data 294" newline hexmask.long.byte 0x434 8.--15. 1. "DATA293,Huffman table data 293" hexmask.long.byte 0x434 0.--7. 1. "DATA292,Huffman table data 292" line.long 0x438 "JPEG_DHTMEM74,JPEG DHT memory" hexmask.long.byte 0x438 24.--31. 1. "DATA299,Huffman table data 299" hexmask.long.byte 0x438 16.--23. 1. "DATA298,Huffman table data 298" newline hexmask.long.byte 0x438 8.--15. 1. "DATA297,Huffman table data 297" hexmask.long.byte 0x438 0.--7. 1. "DATA296,Huffman table data 296" line.long 0x43C "JPEG_DHTMEM75,JPEG DHT memory" hexmask.long.byte 0x43C 24.--31. 1. "DATA303,Huffman table data 303" hexmask.long.byte 0x43C 16.--23. 1. "DATA302,Huffman table data 302" newline hexmask.long.byte 0x43C 8.--15. 1. "DATA301,Huffman table data 301" hexmask.long.byte 0x43C 0.--7. 1. "DATA300,Huffman table data 300" line.long 0x440 "JPEG_DHTMEM76,JPEG DHT memory" hexmask.long.byte 0x440 24.--31. 1. "DATA307,Huffman table data 307" hexmask.long.byte 0x440 16.--23. 1. "DATA306,Huffman table data 306" newline hexmask.long.byte 0x440 8.--15. 1. "DATA305,Huffman table data 305" hexmask.long.byte 0x440 0.--7. 1. "DATA304,Huffman table data 304" line.long 0x444 "JPEG_DHTMEM77,JPEG DHT memory" hexmask.long.byte 0x444 24.--31. 1. "DATA311,Huffman table data 311" hexmask.long.byte 0x444 16.--23. 1. "DATA310,Huffman table data 310" newline hexmask.long.byte 0x444 8.--15. 1. "DATA309,Huffman table data 309" hexmask.long.byte 0x444 0.--7. 1. "DATA308,Huffman table data 308" line.long 0x448 "JPEG_DHTMEM78,JPEG DHT memory" hexmask.long.byte 0x448 24.--31. 1. "DATA315,Huffman table data 315" hexmask.long.byte 0x448 16.--23. 1. "DATA314,Huffman table data 314" newline hexmask.long.byte 0x448 8.--15. 1. "DATA313,Huffman table data 313" hexmask.long.byte 0x448 0.--7. 1. "DATA312,Huffman table data 312" line.long 0x44C "JPEG_DHTMEM79,JPEG DHT memory" hexmask.long.byte 0x44C 24.--31. 1. "DATA319,Huffman table data 319" hexmask.long.byte 0x44C 16.--23. 1. "DATA318,Huffman table data 318" newline hexmask.long.byte 0x44C 8.--15. 1. "DATA317,Huffman table data 317" hexmask.long.byte 0x44C 0.--7. 1. "DATA316,Huffman table data 316" line.long 0x450 "JPEG_DHTMEM80,JPEG DHT memory" hexmask.long.byte 0x450 24.--31. 1. "DATA323,Huffman table data 323" hexmask.long.byte 0x450 16.--23. 1. "DATA322,Huffman table data 322" newline hexmask.long.byte 0x450 8.--15. 1. "DATA321,Huffman table data 321" hexmask.long.byte 0x450 0.--7. 1. "DATA320,Huffman table data 320" line.long 0x454 "JPEG_DHTMEM81,JPEG DHT memory" hexmask.long.byte 0x454 24.--31. 1. "DATA327,Huffman table data 327" hexmask.long.byte 0x454 16.--23. 1. "DATA326,Huffman table data 326" newline hexmask.long.byte 0x454 8.--15. 1. "DATA325,Huffman table data 325" hexmask.long.byte 0x454 0.--7. 1. "DATA324,Huffman table data 324" line.long 0x458 "JPEG_DHTMEM82,JPEG DHT memory" hexmask.long.byte 0x458 24.--31. 1. "DATA331,Huffman table data 331" hexmask.long.byte 0x458 16.--23. 1. "DATA330,Huffman table data 330" newline hexmask.long.byte 0x458 8.--15. 1. "DATA329,Huffman table data 329" hexmask.long.byte 0x458 0.--7. 1. "DATA328,Huffman table data 328" line.long 0x45C "JPEG_DHTMEM83,JPEG DHT memory" hexmask.long.byte 0x45C 24.--31. 1. "DATA335,Huffman table data 335" hexmask.long.byte 0x45C 16.--23. 1. "DATA334,Huffman table data 334" newline hexmask.long.byte 0x45C 8.--15. 1. "DATA333,Huffman table data 333" hexmask.long.byte 0x45C 0.--7. 1. "DATA332,Huffman table data 332" line.long 0x460 "JPEG_DHTMEM84,JPEG DHT memory" hexmask.long.byte 0x460 24.--31. 1. "DATA339,Huffman table data 339" hexmask.long.byte 0x460 16.--23. 1. "DATA338,Huffman table data 338" newline hexmask.long.byte 0x460 8.--15. 1. "DATA337,Huffman table data 337" hexmask.long.byte 0x460 0.--7. 1. "DATA336,Huffman table data 336" line.long 0x464 "JPEG_DHTMEM85,JPEG DHT memory" hexmask.long.byte 0x464 24.--31. 1. "DATA343,Huffman table data 343" hexmask.long.byte 0x464 16.--23. 1. "DATA342,Huffman table data 342" newline hexmask.long.byte 0x464 8.--15. 1. "DATA341,Huffman table data 341" hexmask.long.byte 0x464 0.--7. 1. "DATA340,Huffman table data 340" line.long 0x468 "JPEG_DHTMEM86,JPEG DHT memory" hexmask.long.byte 0x468 24.--31. 1. "DATA347,Huffman table data 347" hexmask.long.byte 0x468 16.--23. 1. "DATA346,Huffman table data 346" newline hexmask.long.byte 0x468 8.--15. 1. "DATA345,Huffman table data 345" hexmask.long.byte 0x468 0.--7. 1. "DATA344,Huffman table data 344" line.long 0x46C "JPEG_DHTMEM87,JPEG DHT memory" hexmask.long.byte 0x46C 24.--31. 1. "DATA351,Huffman table data 351" hexmask.long.byte 0x46C 16.--23. 1. "DATA350,Huffman table data 350" newline hexmask.long.byte 0x46C 8.--15. 1. "DATA349,Huffman table data 349" hexmask.long.byte 0x46C 0.--7. 1. "DATA348,Huffman table data 348" line.long 0x470 "JPEG_DHTMEM88,JPEG DHT memory" hexmask.long.byte 0x470 24.--31. 1. "DATA355,Huffman table data 355" hexmask.long.byte 0x470 16.--23. 1. "DATA354,Huffman table data 354" newline hexmask.long.byte 0x470 8.--15. 1. "DATA353,Huffman table data 353" hexmask.long.byte 0x470 0.--7. 1. "DATA352,Huffman table data 352" line.long 0x474 "JPEG_DHTMEM89,JPEG DHT memory" hexmask.long.byte 0x474 24.--31. 1. "DATA359,Huffman table data 359" hexmask.long.byte 0x474 16.--23. 1. "DATA358,Huffman table data 358" newline hexmask.long.byte 0x474 8.--15. 1. "DATA357,Huffman table data 357" hexmask.long.byte 0x474 0.--7. 1. "DATA356,Huffman table data 356" line.long 0x478 "JPEG_DHTMEM90,JPEG DHT memory" hexmask.long.byte 0x478 24.--31. 1. "DATA363,Huffman table data 363" hexmask.long.byte 0x478 16.--23. 1. "DATA362,Huffman table data 362" newline hexmask.long.byte 0x478 8.--15. 1. "DATA361,Huffman table data 361" hexmask.long.byte 0x478 0.--7. 1. "DATA360,Huffman table data 360" line.long 0x47C "JPEG_DHTMEM91,JPEG DHT memory" hexmask.long.byte 0x47C 24.--31. 1. "DATA367,Huffman table data 367" hexmask.long.byte 0x47C 16.--23. 1. "DATA366,Huffman table data 366" newline hexmask.long.byte 0x47C 8.--15. 1. "DATA365,Huffman table data 365" hexmask.long.byte 0x47C 0.--7. 1. "DATA364,Huffman table data 364" line.long 0x480 "JPEG_DHTMEM92,JPEG DHT memory" hexmask.long.byte 0x480 24.--31. 1. "DATA371,Huffman table data 371" hexmask.long.byte 0x480 16.--23. 1. "DATA370,Huffman table data 370" newline hexmask.long.byte 0x480 8.--15. 1. "DATA369,Huffman table data 369" hexmask.long.byte 0x480 0.--7. 1. "DATA368,Huffman table data 368" line.long 0x484 "JPEG_DHTMEM93,JPEG DHT memory" hexmask.long.byte 0x484 24.--31. 1. "DATA375,Huffman table data 375" hexmask.long.byte 0x484 16.--23. 1. "DATA374,Huffman table data 374" newline hexmask.long.byte 0x484 8.--15. 1. "DATA373,Huffman table data 373" hexmask.long.byte 0x484 0.--7. 1. "DATA372,Huffman table data 372" line.long 0x488 "JPEG_DHTMEM94,JPEG DHT memory" hexmask.long.byte 0x488 24.--31. 1. "DATA379,Huffman table data 379" hexmask.long.byte 0x488 16.--23. 1. "DATA378,Huffman table data 378" newline hexmask.long.byte 0x488 8.--15. 1. "DATA377,Huffman table data 377" hexmask.long.byte 0x488 0.--7. 1. "DATA376,Huffman table data 376" line.long 0x48C "JPEG_DHTMEM95,JPEG DHT memory" hexmask.long.byte 0x48C 24.--31. 1. "DATA383,Huffman table data 383" hexmask.long.byte 0x48C 16.--23. 1. "DATA382,Huffman table data 382" newline hexmask.long.byte 0x48C 8.--15. 1. "DATA381,Huffman table data 381" hexmask.long.byte 0x48C 0.--7. 1. "DATA380,Huffman table data 380" line.long 0x490 "JPEG_DHTMEM96,JPEG DHT memory" hexmask.long.byte 0x490 24.--31. 1. "DATA387,Huffman table data 387" hexmask.long.byte 0x490 16.--23. 1. "DATA386,Huffman table data 386" newline hexmask.long.byte 0x490 8.--15. 1. "DATA385,Huffman table data 385" hexmask.long.byte 0x490 0.--7. 1. "DATA384,Huffman table data 384" line.long 0x494 "JPEG_DHTMEM97,JPEG DHT memory" hexmask.long.byte 0x494 24.--31. 1. "DATA391,Huffman table data 391" hexmask.long.byte 0x494 16.--23. 1. "DATA390,Huffman table data 390" newline hexmask.long.byte 0x494 8.--15. 1. "DATA389,Huffman table data 389" hexmask.long.byte 0x494 0.--7. 1. "DATA388,Huffman table data 388" line.long 0x498 "JPEG_DHTMEM98,JPEG DHT memory" hexmask.long.byte 0x498 24.--31. 1. "DATA395,Huffman table data 395" hexmask.long.byte 0x498 16.--23. 1. "DATA394,Huffman table data 394" newline hexmask.long.byte 0x498 8.--15. 1. "DATA393,Huffman table data 393" hexmask.long.byte 0x498 0.--7. 1. "DATA392,Huffman table data 392" line.long 0x49C "JPEG_DHTMEM99,JPEG DHT memory" hexmask.long.byte 0x49C 24.--31. 1. "DATA399,Huffman table data 399" hexmask.long.byte 0x49C 16.--23. 1. "DATA398,Huffman table data 398" newline hexmask.long.byte 0x49C 8.--15. 1. "DATA397,Huffman table data 397" hexmask.long.byte 0x49C 0.--7. 1. "DATA396,Huffman table data 396" line.long 0x4A0 "JPEG_DHTMEM100,JPEG DHT memory" hexmask.long.byte 0x4A0 24.--31. 1. "DATA403,Huffman table data 403" hexmask.long.byte 0x4A0 16.--23. 1. "DATA402,Huffman table data 402" newline hexmask.long.byte 0x4A0 8.--15. 1. "DATA401,Huffman table data 401" hexmask.long.byte 0x4A0 0.--7. 1. "DATA400,Huffman table data 400" line.long 0x4A4 "JPEG_DHTMEM101,JPEG DHT memory" hexmask.long.byte 0x4A4 24.--31. 1. "DATA407,Huffman table data 407" hexmask.long.byte 0x4A4 16.--23. 1. "DATA406,Huffman table data 406" newline hexmask.long.byte 0x4A4 8.--15. 1. "DATA405,Huffman table data 405" hexmask.long.byte 0x4A4 0.--7. 1. "DATA404,Huffman table data 404" line.long 0x4A8 "JPEG_DHTMEM102,JPEG DHT memory" hexmask.long.byte 0x4A8 24.--31. 1. "DATA411,Huffman table data 411" hexmask.long.byte 0x4A8 16.--23. 1. "DATA410,Huffman table data 410" newline hexmask.long.byte 0x4A8 8.--15. 1. "DATA409,Huffman table data 409" hexmask.long.byte 0x4A8 0.--7. 1. "DATA408,Huffman table data 408" group.long 0x500++0x2FF line.long 0x0 "JPEG_HUFFENC_AC0_0,JPEG Huffman encoder AC0" hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x4 "JPEG_HUFFENC_AC0_1,JPEG Huffman encoder AC0" hexmask.long.byte 0x4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x8 "JPEG_HUFFENC_AC0_2,JPEG Huffman encoder AC0" hexmask.long.byte 0x8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0xC "JPEG_HUFFENC_AC0_3,JPEG Huffman encoder AC0" hexmask.long.byte 0xC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0xC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0xC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0xC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x10 "JPEG_HUFFENC_AC0_4,JPEG Huffman encoder AC0" hexmask.long.byte 0x10 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x10 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x10 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x10 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x14 "JPEG_HUFFENC_AC0_5,JPEG Huffman encoder AC0" hexmask.long.byte 0x14 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x14 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x14 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x14 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x18 "JPEG_HUFFENC_AC0_6,JPEG Huffman encoder AC0" hexmask.long.byte 0x18 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x18 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x18 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x18 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x1C "JPEG_HUFFENC_AC0_7,JPEG Huffman encoder AC0" hexmask.long.byte 0x1C 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x1C 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x1C 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x1C 0.--7. 1. "HCODE14,Huffman code 14" line.long 0x20 "JPEG_HUFFENC_AC0_8,JPEG Huffman encoder AC0" hexmask.long.byte 0x20 24.--27. 1. "HLEN17,Huffman length 17" hexmask.long.byte 0x20 16.--23. 1. "HCODE17,Huffman code 17" newline hexmask.long.byte 0x20 8.--11. 1. "HLEN16,Huffman length 16" hexmask.long.byte 0x20 0.--7. 1. "HCODE16,Huffman code 16" line.long 0x24 "JPEG_HUFFENC_AC0_9,JPEG Huffman encoder AC0" hexmask.long.byte 0x24 24.--27. 1. "HLEN19,Huffman length 19" hexmask.long.byte 0x24 16.--23. 1. "HCODE19,Huffman code 19" newline hexmask.long.byte 0x24 8.--11. 1. "HLEN18,Huffman length 18" hexmask.long.byte 0x24 0.--7. 1. "HCODE18,Huffman code 18" line.long 0x28 "JPEG_HUFFENC_AC0_10,JPEG Huffman encoder AC0" hexmask.long.byte 0x28 24.--27. 1. "HLEN21,Huffman length 21" hexmask.long.byte 0x28 16.--23. 1. "HCODE21,Huffman code 21" newline hexmask.long.byte 0x28 8.--11. 1. "HLEN20,Huffman length 20" hexmask.long.byte 0x28 0.--7. 1. "HCODE20,Huffman code 20" line.long 0x2C "JPEG_HUFFENC_AC0_11,JPEG Huffman encoder AC0" hexmask.long.byte 0x2C 24.--27. 1. "HLEN23,Huffman length 23" hexmask.long.byte 0x2C 16.--23. 1. "HCODE23,Huffman code 23" newline hexmask.long.byte 0x2C 8.--11. 1. "HLEN22,Huffman length 22" hexmask.long.byte 0x2C 0.--7. 1. "HCODE22,Huffman code 22" line.long 0x30 "JPEG_HUFFENC_AC0_12,JPEG Huffman encoder AC0" hexmask.long.byte 0x30 24.--27. 1. "HLEN25,Huffman length 25" hexmask.long.byte 0x30 16.--23. 1. "HCODE25,Huffman code 25" newline hexmask.long.byte 0x30 8.--11. 1. "HLEN24,Huffman length 24" hexmask.long.byte 0x30 0.--7. 1. "HCODE24,Huffman code 24" line.long 0x34 "JPEG_HUFFENC_AC0_13,JPEG Huffman encoder AC0" hexmask.long.byte 0x34 24.--27. 1. "HLEN27,Huffman length 27" hexmask.long.byte 0x34 16.--23. 1. "HCODE27,Huffman code 27" newline hexmask.long.byte 0x34 8.--11. 1. "HLEN26,Huffman length 26" hexmask.long.byte 0x34 0.--7. 1. "HCODE26,Huffman code 26" line.long 0x38 "JPEG_HUFFENC_AC0_14,JPEG Huffman encoder AC0" hexmask.long.byte 0x38 24.--27. 1. "HLEN29,Huffman length 29" hexmask.long.byte 0x38 16.--23. 1. "HCODE29,Huffman code 29" newline hexmask.long.byte 0x38 8.--11. 1. "HLEN28,Huffman length 28" hexmask.long.byte 0x38 0.--7. 1. "HCODE28,Huffman code 28" line.long 0x3C "JPEG_HUFFENC_AC0_15,JPEG Huffman encoder AC0" hexmask.long.byte 0x3C 24.--27. 1. "HLEN31,Huffman length 31" hexmask.long.byte 0x3C 16.--23. 1. "HCODE31,Huffman code 31" newline hexmask.long.byte 0x3C 8.--11. 1. "HLEN30,Huffman length 30" hexmask.long.byte 0x3C 0.--7. 1. "HCODE30,Huffman code 30" line.long 0x40 "JPEG_HUFFENC_AC0_16,JPEG Huffman encoder AC0" hexmask.long.byte 0x40 24.--27. 1. "HLEN33,Huffman length 33" hexmask.long.byte 0x40 16.--23. 1. "HCODE33,Huffman code 33" newline hexmask.long.byte 0x40 8.--11. 1. "HLEN32,Huffman length 32" hexmask.long.byte 0x40 0.--7. 1. "HCODE32,Huffman code 32" line.long 0x44 "JPEG_HUFFENC_AC0_17,JPEG Huffman encoder AC0" hexmask.long.byte 0x44 24.--27. 1. "HLEN35,Huffman length 35" hexmask.long.byte 0x44 16.--23. 1. "HCODE35,Huffman code 35" newline hexmask.long.byte 0x44 8.--11. 1. "HLEN34,Huffman length 34" hexmask.long.byte 0x44 0.--7. 1. "HCODE34,Huffman code 34" line.long 0x48 "JPEG_HUFFENC_AC0_18,JPEG Huffman encoder AC0" hexmask.long.byte 0x48 24.--27. 1. "HLEN37,Huffman length 37" hexmask.long.byte 0x48 16.--23. 1. "HCODE37,Huffman code 37" newline hexmask.long.byte 0x48 8.--11. 1. "HLEN36,Huffman length 36" hexmask.long.byte 0x48 0.--7. 1. "HCODE36,Huffman code 36" line.long 0x4C "JPEG_HUFFENC_AC0_19,JPEG Huffman encoder AC0" hexmask.long.byte 0x4C 24.--27. 1. "HLEN39,Huffman length 39" hexmask.long.byte 0x4C 16.--23. 1. "HCODE39,Huffman code 39" newline hexmask.long.byte 0x4C 8.--11. 1. "HLEN38,Huffman length 38" hexmask.long.byte 0x4C 0.--7. 1. "HCODE38,Huffman code 38" line.long 0x50 "JPEG_HUFFENC_AC0_20,JPEG Huffman encoder AC0" hexmask.long.byte 0x50 24.--27. 1. "HLEN41,Huffman length 41" hexmask.long.byte 0x50 16.--23. 1. "HCODE41,Huffman code 41" newline hexmask.long.byte 0x50 8.--11. 1. "HLEN40,Huffman length 40" hexmask.long.byte 0x50 0.--7. 1. "HCODE40,Huffman code 40" line.long 0x54 "JPEG_HUFFENC_AC0_21,JPEG Huffman encoder AC0" hexmask.long.byte 0x54 24.--27. 1. "HLEN43,Huffman length 43" hexmask.long.byte 0x54 16.--23. 1. "HCODE43,Huffman code 43" newline hexmask.long.byte 0x54 8.--11. 1. "HLEN42,Huffman length 42" hexmask.long.byte 0x54 0.--7. 1. "HCODE42,Huffman code 42" line.long 0x58 "JPEG_HUFFENC_AC0_22,JPEG Huffman encoder AC0" hexmask.long.byte 0x58 24.--27. 1. "HLEN45,Huffman length 45" hexmask.long.byte 0x58 16.--23. 1. "HCODE45,Huffman code 45" newline hexmask.long.byte 0x58 8.--11. 1. "HLEN44,Huffman length 44" hexmask.long.byte 0x58 0.--7. 1. "HCODE44,Huffman code 44" line.long 0x5C "JPEG_HUFFENC_AC0_23,JPEG Huffman encoder AC0" hexmask.long.byte 0x5C 24.--27. 1. "HLEN47,Huffman length 47" hexmask.long.byte 0x5C 16.--23. 1. "HCODE47,Huffman code 47" newline hexmask.long.byte 0x5C 8.--11. 1. "HLEN46,Huffman length 46" hexmask.long.byte 0x5C 0.--7. 1. "HCODE46,Huffman code 46" line.long 0x60 "JPEG_HUFFENC_AC0_24,JPEG Huffman encoder AC0" hexmask.long.byte 0x60 24.--27. 1. "HLEN49,Huffman length 49" hexmask.long.byte 0x60 16.--23. 1. "HCODE49,Huffman code 49" newline hexmask.long.byte 0x60 8.--11. 1. "HLEN48,Huffman length 48" hexmask.long.byte 0x60 0.--7. 1. "HCODE48,Huffman code 48" line.long 0x64 "JPEG_HUFFENC_AC0_25,JPEG Huffman encoder AC0" hexmask.long.byte 0x64 24.--27. 1. "HLEN51,Huffman length 51" hexmask.long.byte 0x64 16.--23. 1. "HCODE51,Huffman code 51" newline hexmask.long.byte 0x64 8.--11. 1. "HLEN50,Huffman length 50" hexmask.long.byte 0x64 0.--7. 1. "HCODE50,Huffman code 50" line.long 0x68 "JPEG_HUFFENC_AC0_26,JPEG Huffman encoder AC0" hexmask.long.byte 0x68 24.--27. 1. "HLEN53,Huffman length 53" hexmask.long.byte 0x68 16.--23. 1. "HCODE53,Huffman code 53" newline hexmask.long.byte 0x68 8.--11. 1. "HLEN52,Huffman length 52" hexmask.long.byte 0x68 0.--7. 1. "HCODE52,Huffman code 52" line.long 0x6C "JPEG_HUFFENC_AC0_27,JPEG Huffman encoder AC0" hexmask.long.byte 0x6C 24.--27. 1. "HLEN55,Huffman length 55" hexmask.long.byte 0x6C 16.--23. 1. "HCODE55,Huffman code 55" newline hexmask.long.byte 0x6C 8.--11. 1. "HLEN54,Huffman length 54" hexmask.long.byte 0x6C 0.--7. 1. "HCODE54,Huffman code 54" line.long 0x70 "JPEG_HUFFENC_AC0_28,JPEG Huffman encoder AC0" hexmask.long.byte 0x70 24.--27. 1. "HLEN57,Huffman length 57" hexmask.long.byte 0x70 16.--23. 1. "HCODE57,Huffman code 57" newline hexmask.long.byte 0x70 8.--11. 1. "HLEN56,Huffman length 56" hexmask.long.byte 0x70 0.--7. 1. "HCODE56,Huffman code 56" line.long 0x74 "JPEG_HUFFENC_AC0_29,JPEG Huffman encoder AC0" hexmask.long.byte 0x74 24.--27. 1. "HLEN59,Huffman length 59" hexmask.long.byte 0x74 16.--23. 1. "HCODE59,Huffman code 59" newline hexmask.long.byte 0x74 8.--11. 1. "HLEN58,Huffman length 58" hexmask.long.byte 0x74 0.--7. 1. "HCODE58,Huffman code 58" line.long 0x78 "JPEG_HUFFENC_AC0_30,JPEG Huffman encoder AC0" hexmask.long.byte 0x78 24.--27. 1. "HLEN61,Huffman length 61" hexmask.long.byte 0x78 16.--23. 1. "HCODE61,Huffman code 61" newline hexmask.long.byte 0x78 8.--11. 1. "HLEN60,Huffman length 60" hexmask.long.byte 0x78 0.--7. 1. "HCODE60,Huffman code 60" line.long 0x7C "JPEG_HUFFENC_AC0_31,JPEG Huffman encoder AC0" hexmask.long.byte 0x7C 24.--27. 1. "HLEN63,Huffman length 63" hexmask.long.byte 0x7C 16.--23. 1. "HCODE63,Huffman code 63" newline hexmask.long.byte 0x7C 8.--11. 1. "HLEN62,Huffman length 62" hexmask.long.byte 0x7C 0.--7. 1. "HCODE62,Huffman code 62" line.long 0x80 "JPEG_HUFFENC_AC0_32,JPEG Huffman encoder AC0" hexmask.long.byte 0x80 24.--27. 1. "HLEN65,Huffman length 65" hexmask.long.byte 0x80 16.--23. 1. "HCODE65,Huffman code 65" newline hexmask.long.byte 0x80 8.--11. 1. "HLEN64,Huffman length 64" hexmask.long.byte 0x80 0.--7. 1. "HCODE64,Huffman code 64" line.long 0x84 "JPEG_HUFFENC_AC0_33,JPEG Huffman encoder AC0" hexmask.long.byte 0x84 24.--27. 1. "HLEN67,Huffman length 67" hexmask.long.byte 0x84 16.--23. 1. "HCODE67,Huffman code 67" newline hexmask.long.byte 0x84 8.--11. 1. "HLEN66,Huffman length 66" hexmask.long.byte 0x84 0.--7. 1. "HCODE66,Huffman code 66" line.long 0x88 "JPEG_HUFFENC_AC0_34,JPEG Huffman encoder AC0" hexmask.long.byte 0x88 24.--27. 1. "HLEN69,Huffman length 69" hexmask.long.byte 0x88 16.--23. 1. "HCODE69,Huffman code 69" newline hexmask.long.byte 0x88 8.--11. 1. "HLEN68,Huffman length 68" hexmask.long.byte 0x88 0.--7. 1. "HCODE68,Huffman code 68" line.long 0x8C "JPEG_HUFFENC_AC0_35,JPEG Huffman encoder AC0" hexmask.long.byte 0x8C 24.--27. 1. "HLEN71,Huffman length 71" hexmask.long.byte 0x8C 16.--23. 1. "HCODE71,Huffman code 71" newline hexmask.long.byte 0x8C 8.--11. 1. "HLEN70,Huffman length 70" hexmask.long.byte 0x8C 0.--7. 1. "HCODE70,Huffman code 70" line.long 0x90 "JPEG_HUFFENC_AC0_36,JPEG Huffman encoder AC0" hexmask.long.byte 0x90 24.--27. 1. "HLEN73,Huffman length 73" hexmask.long.byte 0x90 16.--23. 1. "HCODE73,Huffman code 73" newline hexmask.long.byte 0x90 8.--11. 1. "HLEN72,Huffman length 72" hexmask.long.byte 0x90 0.--7. 1. "HCODE72,Huffman code 72" line.long 0x94 "JPEG_HUFFENC_AC0_37,JPEG Huffman encoder AC0" hexmask.long.byte 0x94 24.--27. 1. "HLEN75,Huffman length 75" hexmask.long.byte 0x94 16.--23. 1. "HCODE75,Huffman code 75" newline hexmask.long.byte 0x94 8.--11. 1. "HLEN74,Huffman length 74" hexmask.long.byte 0x94 0.--7. 1. "HCODE74,Huffman code 74" line.long 0x98 "JPEG_HUFFENC_AC0_38,JPEG Huffman encoder AC0" hexmask.long.byte 0x98 24.--27. 1. "HLEN77,Huffman length 77" hexmask.long.byte 0x98 16.--23. 1. "HCODE77,Huffman code 77" newline hexmask.long.byte 0x98 8.--11. 1. "HLEN76,Huffman length 76" hexmask.long.byte 0x98 0.--7. 1. "HCODE76,Huffman code 76" line.long 0x9C "JPEG_HUFFENC_AC0_39,JPEG Huffman encoder AC0" hexmask.long.byte 0x9C 24.--27. 1. "HLEN79,Huffman length 79" hexmask.long.byte 0x9C 16.--23. 1. "HCODE79,Huffman code 79" newline hexmask.long.byte 0x9C 8.--11. 1. "HLEN78,Huffman length 78" hexmask.long.byte 0x9C 0.--7. 1. "HCODE78,Huffman code 78" line.long 0xA0 "JPEG_HUFFENC_AC0_40,JPEG Huffman encoder AC0" hexmask.long.byte 0xA0 24.--27. 1. "HLEN81,Huffman length 81" hexmask.long.byte 0xA0 16.--23. 1. "HCODE81,Huffman code 81" newline hexmask.long.byte 0xA0 8.--11. 1. "HLEN80,Huffman length 80" hexmask.long.byte 0xA0 0.--7. 1. "HCODE80,Huffman code 80" line.long 0xA4 "JPEG_HUFFENC_AC0_41,JPEG Huffman encoder AC0" hexmask.long.byte 0xA4 24.--27. 1. "HLEN83,Huffman length 83" hexmask.long.byte 0xA4 16.--23. 1. "HCODE83,Huffman code 83" newline hexmask.long.byte 0xA4 8.--11. 1. "HLEN82,Huffman length 82" hexmask.long.byte 0xA4 0.--7. 1. "HCODE82,Huffman code 82" line.long 0xA8 "JPEG_HUFFENC_AC0_42,JPEG Huffman encoder AC0" hexmask.long.byte 0xA8 24.--27. 1. "HLEN85,Huffman length 85" hexmask.long.byte 0xA8 16.--23. 1. "HCODE85,Huffman code 85" newline hexmask.long.byte 0xA8 8.--11. 1. "HLEN84,Huffman length 84" hexmask.long.byte 0xA8 0.--7. 1. "HCODE84,Huffman code 84" line.long 0xAC "JPEG_HUFFENC_AC0_43,JPEG Huffman encoder AC0" hexmask.long.byte 0xAC 24.--27. 1. "HLEN87,Huffman length 87" hexmask.long.byte 0xAC 16.--23. 1. "HCODE87,Huffman code 87" newline hexmask.long.byte 0xAC 8.--11. 1. "HLEN86,Huffman length 86" hexmask.long.byte 0xAC 0.--7. 1. "HCODE86,Huffman code 86" line.long 0xB0 "JPEG_HUFFENC_AC0_44,JPEG Huffman encoder AC0" hexmask.long.byte 0xB0 24.--27. 1. "HLEN89,Huffman length 89" hexmask.long.byte 0xB0 16.--23. 1. "HCODE89,Huffman code 89" newline hexmask.long.byte 0xB0 8.--11. 1. "HLEN88,Huffman length 88" hexmask.long.byte 0xB0 0.--7. 1. "HCODE88,Huffman code 88" line.long 0xB4 "JPEG_HUFFENC_AC0_45,JPEG Huffman encoder AC0" hexmask.long.byte 0xB4 24.--27. 1. "HLEN91,Huffman length 91" hexmask.long.byte 0xB4 16.--23. 1. "HCODE91,Huffman code 91" newline hexmask.long.byte 0xB4 8.--11. 1. "HLEN90,Huffman length 90" hexmask.long.byte 0xB4 0.--7. 1. "HCODE90,Huffman code 90" line.long 0xB8 "JPEG_HUFFENC_AC0_46,JPEG Huffman encoder AC0" hexmask.long.byte 0xB8 24.--27. 1. "HLEN93,Huffman length 93" hexmask.long.byte 0xB8 16.--23. 1. "HCODE93,Huffman code 93" newline hexmask.long.byte 0xB8 8.--11. 1. "HLEN92,Huffman length 92" hexmask.long.byte 0xB8 0.--7. 1. "HCODE92,Huffman code 92" line.long 0xBC "JPEG_HUFFENC_AC0_47,JPEG Huffman encoder AC0" hexmask.long.byte 0xBC 24.--27. 1. "HLEN95,Huffman length 95" hexmask.long.byte 0xBC 16.--23. 1. "HCODE95,Huffman code 95" newline hexmask.long.byte 0xBC 8.--11. 1. "HLEN94,Huffman length 94" hexmask.long.byte 0xBC 0.--7. 1. "HCODE94,Huffman code 94" line.long 0xC0 "JPEG_HUFFENC_AC0_48,JPEG Huffman encoder AC0" hexmask.long.byte 0xC0 24.--27. 1. "HLEN97,Huffman length 97" hexmask.long.byte 0xC0 16.--23. 1. "HCODE97,Huffman code 97" newline hexmask.long.byte 0xC0 8.--11. 1. "HLEN96,Huffman length 96" hexmask.long.byte 0xC0 0.--7. 1. "HCODE96,Huffman code 96" line.long 0xC4 "JPEG_HUFFENC_AC0_49,JPEG Huffman encoder AC0" hexmask.long.byte 0xC4 24.--27. 1. "HLEN99,Huffman length 99" hexmask.long.byte 0xC4 16.--23. 1. "HCODE99,Huffman code 99" newline hexmask.long.byte 0xC4 8.--11. 1. "HLEN98,Huffman length 98" hexmask.long.byte 0xC4 0.--7. 1. "HCODE98,Huffman code 98" line.long 0xC8 "JPEG_HUFFENC_AC0_50,JPEG Huffman encoder AC0" hexmask.long.byte 0xC8 24.--27. 1. "HLEN101,Huffman length 101" hexmask.long.byte 0xC8 16.--23. 1. "HCODE101,Huffman code 101" newline hexmask.long.byte 0xC8 8.--11. 1. "HLEN100,Huffman length 100" hexmask.long.byte 0xC8 0.--7. 1. "HCODE100,Huffman code 100" line.long 0xCC "JPEG_HUFFENC_AC0_51,JPEG Huffman encoder AC0" hexmask.long.byte 0xCC 24.--27. 1. "HLEN103,Huffman length 103" hexmask.long.byte 0xCC 16.--23. 1. "HCODE103,Huffman code 103" newline hexmask.long.byte 0xCC 8.--11. 1. "HLEN102,Huffman length 102" hexmask.long.byte 0xCC 0.--7. 1. "HCODE102,Huffman code 102" line.long 0xD0 "JPEG_HUFFENC_AC0_52,JPEG Huffman encoder AC0" hexmask.long.byte 0xD0 24.--27. 1. "HLEN105,Huffman length 105" hexmask.long.byte 0xD0 16.--23. 1. "HCODE105,Huffman code 105" newline hexmask.long.byte 0xD0 8.--11. 1. "HLEN104,Huffman length 104" hexmask.long.byte 0xD0 0.--7. 1. "HCODE104,Huffman code 104" line.long 0xD4 "JPEG_HUFFENC_AC0_53,JPEG Huffman encoder AC0" hexmask.long.byte 0xD4 24.--27. 1. "HLEN107,Huffman length 107" hexmask.long.byte 0xD4 16.--23. 1. "HCODE107,Huffman code 107" newline hexmask.long.byte 0xD4 8.--11. 1. "HLEN106,Huffman length 106" hexmask.long.byte 0xD4 0.--7. 1. "HCODE106,Huffman code 106" line.long 0xD8 "JPEG_HUFFENC_AC0_54,JPEG Huffman encoder AC0" hexmask.long.byte 0xD8 24.--27. 1. "HLEN109,Huffman length 109" hexmask.long.byte 0xD8 16.--23. 1. "HCODE109,Huffman code 109" newline hexmask.long.byte 0xD8 8.--11. 1. "HLEN108,Huffman length 108" hexmask.long.byte 0xD8 0.--7. 1. "HCODE108,Huffman code 108" line.long 0xDC "JPEG_HUFFENC_AC0_55,JPEG Huffman encoder AC0" hexmask.long.byte 0xDC 24.--27. 1. "HLEN111,Huffman length 111" hexmask.long.byte 0xDC 16.--23. 1. "HCODE111,Huffman code 111" newline hexmask.long.byte 0xDC 8.--11. 1. "HLEN110,Huffman length 110" hexmask.long.byte 0xDC 0.--7. 1. "HCODE110,Huffman code 110" line.long 0xE0 "JPEG_HUFFENC_AC0_56,JPEG Huffman encoder AC0" hexmask.long.byte 0xE0 24.--27. 1. "HLEN113,Huffman length 113" hexmask.long.byte 0xE0 16.--23. 1. "HCODE113,Huffman code 113" newline hexmask.long.byte 0xE0 8.--11. 1. "HLEN112,Huffman length 112" hexmask.long.byte 0xE0 0.--7. 1. "HCODE112,Huffman code 112" line.long 0xE4 "JPEG_HUFFENC_AC0_57,JPEG Huffman encoder AC0" hexmask.long.byte 0xE4 24.--27. 1. "HLEN115,Huffman length 115" hexmask.long.byte 0xE4 16.--23. 1. "HCODE115,Huffman code 115" newline hexmask.long.byte 0xE4 8.--11. 1. "HLEN114,Huffman length 114" hexmask.long.byte 0xE4 0.--7. 1. "HCODE114,Huffman code 114" line.long 0xE8 "JPEG_HUFFENC_AC0_58,JPEG Huffman encoder AC0" hexmask.long.byte 0xE8 24.--27. 1. "HLEN117,Huffman length 117" hexmask.long.byte 0xE8 16.--23. 1. "HCODE117,Huffman code 117" newline hexmask.long.byte 0xE8 8.--11. 1. "HLEN116,Huffman length 116" hexmask.long.byte 0xE8 0.--7. 1. "HCODE116,Huffman code 116" line.long 0xEC "JPEG_HUFFENC_AC0_59,JPEG Huffman encoder AC0" hexmask.long.byte 0xEC 24.--27. 1. "HLEN119,Huffman length 119" hexmask.long.byte 0xEC 16.--23. 1. "HCODE119,Huffman code 119" newline hexmask.long.byte 0xEC 8.--11. 1. "HLEN118,Huffman length 118" hexmask.long.byte 0xEC 0.--7. 1. "HCODE118,Huffman code 118" line.long 0xF0 "JPEG_HUFFENC_AC0_60,JPEG Huffman encoder AC0" hexmask.long.byte 0xF0 24.--27. 1. "HLEN121,Huffman length 121" hexmask.long.byte 0xF0 16.--23. 1. "HCODE121,Huffman code 121" newline hexmask.long.byte 0xF0 8.--11. 1. "HLEN120,Huffman length 120" hexmask.long.byte 0xF0 0.--7. 1. "HCODE120,Huffman code 120" line.long 0xF4 "JPEG_HUFFENC_AC0_61,JPEG Huffman encoder AC0" hexmask.long.byte 0xF4 24.--27. 1. "HLEN123,Huffman length 123" hexmask.long.byte 0xF4 16.--23. 1. "HCODE123,Huffman code 123" newline hexmask.long.byte 0xF4 8.--11. 1. "HLEN122,Huffman length 122" hexmask.long.byte 0xF4 0.--7. 1. "HCODE122,Huffman code 122" line.long 0xF8 "JPEG_HUFFENC_AC0_62,JPEG Huffman encoder AC0" hexmask.long.byte 0xF8 24.--27. 1. "HLEN125,Huffman length 125" hexmask.long.byte 0xF8 16.--23. 1. "HCODE125,Huffman code 125" newline hexmask.long.byte 0xF8 8.--11. 1. "HLEN124,Huffman length 124" hexmask.long.byte 0xF8 0.--7. 1. "HCODE124,Huffman code 124" line.long 0xFC "JPEG_HUFFENC_AC0_63,JPEG Huffman encoder AC0" hexmask.long.byte 0xFC 24.--27. 1. "HLEN127,Huffman length 127" hexmask.long.byte 0xFC 16.--23. 1. "HCODE127,Huffman code 127" newline hexmask.long.byte 0xFC 8.--11. 1. "HLEN126,Huffman length 126" hexmask.long.byte 0xFC 0.--7. 1. "HCODE126,Huffman code 126" line.long 0x100 "JPEG_HUFFENC_AC0_64,JPEG Huffman encoder AC0" hexmask.long.byte 0x100 24.--27. 1. "HLEN129,Huffman length 129" hexmask.long.byte 0x100 16.--23. 1. "HCODE129,Huffman code 129" newline hexmask.long.byte 0x100 8.--11. 1. "HLEN128,Huffman length 128" hexmask.long.byte 0x100 0.--7. 1. "HCODE128,Huffman code 128" line.long 0x104 "JPEG_HUFFENC_AC0_65,JPEG Huffman encoder AC0" hexmask.long.byte 0x104 24.--27. 1. "HLEN131,Huffman length 131" hexmask.long.byte 0x104 16.--23. 1. "HCODE131,Huffman code 131" newline hexmask.long.byte 0x104 8.--11. 1. "HLEN130,Huffman length 130" hexmask.long.byte 0x104 0.--7. 1. "HCODE130,Huffman code 130" line.long 0x108 "JPEG_HUFFENC_AC0_66,JPEG Huffman encoder AC0" hexmask.long.byte 0x108 24.--27. 1. "HLEN133,Huffman length 133" hexmask.long.byte 0x108 16.--23. 1. "HCODE133,Huffman code 133" newline hexmask.long.byte 0x108 8.--11. 1. "HLEN132,Huffman length 132" hexmask.long.byte 0x108 0.--7. 1. "HCODE132,Huffman code 132" line.long 0x10C "JPEG_HUFFENC_AC0_67,JPEG Huffman encoder AC0" hexmask.long.byte 0x10C 24.--27. 1. "HLEN135,Huffman length 135" hexmask.long.byte 0x10C 16.--23. 1. "HCODE135,Huffman code 135" newline hexmask.long.byte 0x10C 8.--11. 1. "HLEN134,Huffman length 134" hexmask.long.byte 0x10C 0.--7. 1. "HCODE134,Huffman code 134" line.long 0x110 "JPEG_HUFFENC_AC0_68,JPEG Huffman encoder AC0" hexmask.long.byte 0x110 24.--27. 1. "HLEN137,Huffman length 137" hexmask.long.byte 0x110 16.--23. 1. "HCODE137,Huffman code 137" newline hexmask.long.byte 0x110 8.--11. 1. "HLEN136,Huffman length 136" hexmask.long.byte 0x110 0.--7. 1. "HCODE136,Huffman code 136" line.long 0x114 "JPEG_HUFFENC_AC0_69,JPEG Huffman encoder AC0" hexmask.long.byte 0x114 24.--27. 1. "HLEN139,Huffman length 139" hexmask.long.byte 0x114 16.--23. 1. "HCODE139,Huffman code 139" newline hexmask.long.byte 0x114 8.--11. 1. "HLEN138,Huffman length 138" hexmask.long.byte 0x114 0.--7. 1. "HCODE138,Huffman code 138" line.long 0x118 "JPEG_HUFFENC_AC0_70,JPEG Huffman encoder AC0" hexmask.long.byte 0x118 24.--27. 1. "HLEN141,Huffman length 141" hexmask.long.byte 0x118 16.--23. 1. "HCODE141,Huffman code 141" newline hexmask.long.byte 0x118 8.--11. 1. "HLEN140,Huffman length 140" hexmask.long.byte 0x118 0.--7. 1. "HCODE140,Huffman code 140" line.long 0x11C "JPEG_HUFFENC_AC0_71,JPEG Huffman encoder AC0" hexmask.long.byte 0x11C 24.--27. 1. "HLEN143,Huffman length 143" hexmask.long.byte 0x11C 16.--23. 1. "HCODE143,Huffman code 143" newline hexmask.long.byte 0x11C 8.--11. 1. "HLEN142,Huffman length 142" hexmask.long.byte 0x11C 0.--7. 1. "HCODE142,Huffman code 142" line.long 0x120 "JPEG_HUFFENC_AC0_72,JPEG Huffman encoder AC0" hexmask.long.byte 0x120 24.--27. 1. "HLEN145,Huffman length 145" hexmask.long.byte 0x120 16.--23. 1. "HCODE145,Huffman code 145" newline hexmask.long.byte 0x120 8.--11. 1. "HLEN144,Huffman length 144" hexmask.long.byte 0x120 0.--7. 1. "HCODE144,Huffman code 144" line.long 0x124 "JPEG_HUFFENC_AC0_73,JPEG Huffman encoder AC0" hexmask.long.byte 0x124 24.--27. 1. "HLEN147,Huffman length 147" hexmask.long.byte 0x124 16.--23. 1. "HCODE147,Huffman code 147" newline hexmask.long.byte 0x124 8.--11. 1. "HLEN146,Huffman length 146" hexmask.long.byte 0x124 0.--7. 1. "HCODE146,Huffman code 146" line.long 0x128 "JPEG_HUFFENC_AC0_74,JPEG Huffman encoder AC0" hexmask.long.byte 0x128 24.--27. 1. "HLEN149,Huffman length 149" hexmask.long.byte 0x128 16.--23. 1. "HCODE149,Huffman code 149" newline hexmask.long.byte 0x128 8.--11. 1. "HLEN148,Huffman length 148" hexmask.long.byte 0x128 0.--7. 1. "HCODE148,Huffman code 148" line.long 0x12C "JPEG_HUFFENC_AC0_75,JPEG Huffman encoder AC0" hexmask.long.byte 0x12C 24.--27. 1. "HLEN151,Huffman length 151" hexmask.long.byte 0x12C 16.--23. 1. "HCODE151,Huffman code 151" newline hexmask.long.byte 0x12C 8.--11. 1. "HLEN150,Huffman length 150" hexmask.long.byte 0x12C 0.--7. 1. "HCODE150,Huffman code 150" line.long 0x130 "JPEG_HUFFENC_AC0_76,JPEG Huffman encoder AC0" hexmask.long.byte 0x130 24.--27. 1. "HLEN153,Huffman length 153" hexmask.long.byte 0x130 16.--23. 1. "HCODE153,Huffman code 153" newline hexmask.long.byte 0x130 8.--11. 1. "HLEN152,Huffman length 152" hexmask.long.byte 0x130 0.--7. 1. "HCODE152,Huffman code 152" line.long 0x134 "JPEG_HUFFENC_AC0_77,JPEG Huffman encoder AC0" hexmask.long.byte 0x134 24.--27. 1. "HLEN155,Huffman length 155" hexmask.long.byte 0x134 16.--23. 1. "HCODE155,Huffman code 155" newline hexmask.long.byte 0x134 8.--11. 1. "HLEN154,Huffman length 154" hexmask.long.byte 0x134 0.--7. 1. "HCODE154,Huffman code 154" line.long 0x138 "JPEG_HUFFENC_AC0_78,JPEG Huffman encoder AC0" hexmask.long.byte 0x138 24.--27. 1. "HLEN157,Huffman length 157" hexmask.long.byte 0x138 16.--23. 1. "HCODE157,Huffman code 157" newline hexmask.long.byte 0x138 8.--11. 1. "HLEN156,Huffman length 156" hexmask.long.byte 0x138 0.--7. 1. "HCODE156,Huffman code 156" line.long 0x13C "JPEG_HUFFENC_AC0_79,JPEG Huffman encoder AC0" hexmask.long.byte 0x13C 24.--27. 1. "HLEN159,Huffman length 159" hexmask.long.byte 0x13C 16.--23. 1. "HCODE159,Huffman code 159" newline hexmask.long.byte 0x13C 8.--11. 1. "HLEN158,Huffman length 158" hexmask.long.byte 0x13C 0.--7. 1. "HCODE158,Huffman code 158" line.long 0x140 "JPEG_HUFFENC_AC0_80,JPEG Huffman encoder AC0" hexmask.long.byte 0x140 24.--27. 1. "HLEN161,Huffman length 161" hexmask.long.byte 0x140 16.--23. 1. "HCODE161,Huffman code 161" newline hexmask.long.byte 0x140 8.--11. 1. "HLEN160,Huffman length 160" hexmask.long.byte 0x140 0.--7. 1. "HCODE160,Huffman code 160" line.long 0x144 "JPEG_HUFFENC_AC0_81,JPEG Huffman encoder AC0" hexmask.long.byte 0x144 24.--27. 1. "HLEN163,Huffman length 163" hexmask.long.byte 0x144 16.--23. 1. "HCODE163,Huffman code 163" newline hexmask.long.byte 0x144 8.--11. 1. "HLEN162,Huffman length 162" hexmask.long.byte 0x144 0.--7. 1. "HCODE162,Huffman code 162" line.long 0x148 "JPEG_HUFFENC_AC0_82,JPEG Huffman encoder AC0" hexmask.long.byte 0x148 24.--27. 1. "HLEN165,Huffman length 165" hexmask.long.byte 0x148 16.--23. 1. "HCODE165,Huffman code 165" newline hexmask.long.byte 0x148 8.--11. 1. "HLEN164,Huffman length 164" hexmask.long.byte 0x148 0.--7. 1. "HCODE164,Huffman code 164" line.long 0x14C "JPEG_HUFFENC_AC0_83,JPEG Huffman encoder AC0" hexmask.long.byte 0x14C 24.--27. 1. "HLEN167,Huffman length 167" hexmask.long.byte 0x14C 16.--23. 1. "HCODE167,Huffman code 167" newline hexmask.long.byte 0x14C 8.--11. 1. "HLEN166,Huffman length 166" hexmask.long.byte 0x14C 0.--7. 1. "HCODE166,Huffman code 166" line.long 0x150 "JPEG_HUFFENC_AC0_84,JPEG Huffman encoder AC0" hexmask.long.byte 0x150 24.--27. 1. "HLEN169,Huffman length 169" hexmask.long.byte 0x150 16.--23. 1. "HCODE169,Huffman code 169" newline hexmask.long.byte 0x150 8.--11. 1. "HLEN168,Huffman length 168" hexmask.long.byte 0x150 0.--7. 1. "HCODE168,Huffman code 168" line.long 0x154 "JPEG_HUFFENC_AC0_85,JPEG Huffman encoder AC0" hexmask.long.byte 0x154 24.--27. 1. "HLEN171,Huffman length 171" hexmask.long.byte 0x154 16.--23. 1. "HCODE171,Huffman code 171" newline hexmask.long.byte 0x154 8.--11. 1. "HLEN170,Huffman length 170" hexmask.long.byte 0x154 0.--7. 1. "HCODE170,Huffman code 170" line.long 0x158 "JPEG_HUFFENC_AC0_86,JPEG Huffman encoder AC0" hexmask.long.byte 0x158 24.--27. 1. "HLEN173,Huffman length 173" hexmask.long.byte 0x158 16.--23. 1. "HCODE173,Huffman code 173" newline hexmask.long.byte 0x158 8.--11. 1. "HLEN172,Huffman length 172" hexmask.long.byte 0x158 0.--7. 1. "HCODE172,Huffman code 172" line.long 0x15C "JPEG_HUFFENC_AC0_87,JPEG Huffman encoder AC0" hexmask.long.byte 0x15C 24.--27. 1. "HLEN175,Huffman length 175" hexmask.long.byte 0x15C 16.--23. 1. "HCODE175,Huffman code 175" newline hexmask.long.byte 0x15C 8.--11. 1. "HLEN174,Huffman length 174" hexmask.long.byte 0x15C 0.--7. 1. "HCODE174,Huffman code 174" line.long 0x160 "JPEG_HUFFENC_AC1_0,JPEG Huffman encoder AC1" hexmask.long.byte 0x160 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x160 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x160 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x160 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x164 "JPEG_HUFFENC_AC1_1,JPEG Huffman encoder AC1" hexmask.long.byte 0x164 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x164 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x164 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x164 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x168 "JPEG_HUFFENC_AC1_2,JPEG Huffman encoder AC1" hexmask.long.byte 0x168 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x168 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x168 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x168 0.--7. 1. "HCODE4,Huffman code 4" line.long 0x16C "JPEG_HUFFENC_AC1_3,JPEG Huffman encoder AC1" hexmask.long.byte 0x16C 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0x16C 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0x16C 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0x16C 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x170 "JPEG_HUFFENC_AC1_4,JPEG Huffman encoder AC1" hexmask.long.byte 0x170 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x170 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x170 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x170 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x174 "JPEG_HUFFENC_AC1_5,JPEG Huffman encoder AC1" hexmask.long.byte 0x174 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x174 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x174 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x174 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x178 "JPEG_HUFFENC_AC1_6,JPEG Huffman encoder AC1" hexmask.long.byte 0x178 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x178 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x178 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x178 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x17C "JPEG_HUFFENC_AC1_7,JPEG Huffman encoder AC1" hexmask.long.byte 0x17C 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x17C 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x17C 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x17C 0.--7. 1. "HCODE14,Huffman code 14" line.long 0x180 "JPEG_HUFFENC_AC1_8,JPEG Huffman encoder AC1" hexmask.long.byte 0x180 24.--27. 1. "HLEN17,Huffman length 17" hexmask.long.byte 0x180 16.--23. 1. "HCODE17,Huffman code 17" newline hexmask.long.byte 0x180 8.--11. 1. "HLEN16,Huffman length 16" hexmask.long.byte 0x180 0.--7. 1. "HCODE16,Huffman code 16" line.long 0x184 "JPEG_HUFFENC_AC1_9,JPEG Huffman encoder AC1" hexmask.long.byte 0x184 24.--27. 1. "HLEN19,Huffman length 19" hexmask.long.byte 0x184 16.--23. 1. "HCODE19,Huffman code 19" newline hexmask.long.byte 0x184 8.--11. 1. "HLEN18,Huffman length 18" hexmask.long.byte 0x184 0.--7. 1. "HCODE18,Huffman code 18" line.long 0x188 "JPEG_HUFFENC_AC1_10,JPEG Huffman encoder AC1" hexmask.long.byte 0x188 24.--27. 1. "HLEN21,Huffman length 21" hexmask.long.byte 0x188 16.--23. 1. "HCODE21,Huffman code 21" newline hexmask.long.byte 0x188 8.--11. 1. "HLEN20,Huffman length 20" hexmask.long.byte 0x188 0.--7. 1. "HCODE20,Huffman code 20" line.long 0x18C "JPEG_HUFFENC_AC1_11,JPEG Huffman encoder AC1" hexmask.long.byte 0x18C 24.--27. 1. "HLEN23,Huffman length 23" hexmask.long.byte 0x18C 16.--23. 1. "HCODE23,Huffman code 23" newline hexmask.long.byte 0x18C 8.--11. 1. "HLEN22,Huffman length 22" hexmask.long.byte 0x18C 0.--7. 1. "HCODE22,Huffman code 22" line.long 0x190 "JPEG_HUFFENC_AC1_12,JPEG Huffman encoder AC1" hexmask.long.byte 0x190 24.--27. 1. "HLEN25,Huffman length 25" hexmask.long.byte 0x190 16.--23. 1. "HCODE25,Huffman code 25" newline hexmask.long.byte 0x190 8.--11. 1. "HLEN24,Huffman length 24" hexmask.long.byte 0x190 0.--7. 1. "HCODE24,Huffman code 24" line.long 0x194 "JPEG_HUFFENC_AC1_13,JPEG Huffman encoder AC1" hexmask.long.byte 0x194 24.--27. 1. "HLEN27,Huffman length 27" hexmask.long.byte 0x194 16.--23. 1. "HCODE27,Huffman code 27" newline hexmask.long.byte 0x194 8.--11. 1. "HLEN26,Huffman length 26" hexmask.long.byte 0x194 0.--7. 1. "HCODE26,Huffman code 26" line.long 0x198 "JPEG_HUFFENC_AC1_14,JPEG Huffman encoder AC1" hexmask.long.byte 0x198 24.--27. 1. "HLEN29,Huffman length 29" hexmask.long.byte 0x198 16.--23. 1. "HCODE29,Huffman code 29" newline hexmask.long.byte 0x198 8.--11. 1. "HLEN28,Huffman length 28" hexmask.long.byte 0x198 0.--7. 1. "HCODE28,Huffman code 28" line.long 0x19C "JPEG_HUFFENC_AC1_15,JPEG Huffman encoder AC1" hexmask.long.byte 0x19C 24.--27. 1. "HLEN31,Huffman length 31" hexmask.long.byte 0x19C 16.--23. 1. "HCODE31,Huffman code 31" newline hexmask.long.byte 0x19C 8.--11. 1. "HLEN30,Huffman length 30" hexmask.long.byte 0x19C 0.--7. 1. "HCODE30,Huffman code 30" line.long 0x1A0 "JPEG_HUFFENC_AC1_16,JPEG Huffman encoder AC1" hexmask.long.byte 0x1A0 24.--27. 1. "HLEN33,Huffman length 33" hexmask.long.byte 0x1A0 16.--23. 1. "HCODE33,Huffman code 33" newline hexmask.long.byte 0x1A0 8.--11. 1. "HLEN32,Huffman length 32" hexmask.long.byte 0x1A0 0.--7. 1. "HCODE32,Huffman code 32" line.long 0x1A4 "JPEG_HUFFENC_AC1_17,JPEG Huffman encoder AC1" hexmask.long.byte 0x1A4 24.--27. 1. "HLEN35,Huffman length 35" hexmask.long.byte 0x1A4 16.--23. 1. "HCODE35,Huffman code 35" newline hexmask.long.byte 0x1A4 8.--11. 1. "HLEN34,Huffman length 34" hexmask.long.byte 0x1A4 0.--7. 1. "HCODE34,Huffman code 34" line.long 0x1A8 "JPEG_HUFFENC_AC1_18,JPEG Huffman encoder AC1" hexmask.long.byte 0x1A8 24.--27. 1. "HLEN37,Huffman length 37" hexmask.long.byte 0x1A8 16.--23. 1. "HCODE37,Huffman code 37" newline hexmask.long.byte 0x1A8 8.--11. 1. "HLEN36,Huffman length 36" hexmask.long.byte 0x1A8 0.--7. 1. "HCODE36,Huffman code 36" line.long 0x1AC "JPEG_HUFFENC_AC1_19,JPEG Huffman encoder AC1" hexmask.long.byte 0x1AC 24.--27. 1. "HLEN39,Huffman length 39" hexmask.long.byte 0x1AC 16.--23. 1. "HCODE39,Huffman code 39" newline hexmask.long.byte 0x1AC 8.--11. 1. "HLEN38,Huffman length 38" hexmask.long.byte 0x1AC 0.--7. 1. "HCODE38,Huffman code 38" line.long 0x1B0 "JPEG_HUFFENC_AC1_20,JPEG Huffman encoder AC1" hexmask.long.byte 0x1B0 24.--27. 1. "HLEN41,Huffman length 41" hexmask.long.byte 0x1B0 16.--23. 1. "HCODE41,Huffman code 41" newline hexmask.long.byte 0x1B0 8.--11. 1. "HLEN40,Huffman length 40" hexmask.long.byte 0x1B0 0.--7. 1. "HCODE40,Huffman code 40" line.long 0x1B4 "JPEG_HUFFENC_AC1_21,JPEG Huffman encoder AC1" hexmask.long.byte 0x1B4 24.--27. 1. "HLEN43,Huffman length 43" hexmask.long.byte 0x1B4 16.--23. 1. "HCODE43,Huffman code 43" newline hexmask.long.byte 0x1B4 8.--11. 1. "HLEN42,Huffman length 42" hexmask.long.byte 0x1B4 0.--7. 1. "HCODE42,Huffman code 42" line.long 0x1B8 "JPEG_HUFFENC_AC1_22,JPEG Huffman encoder AC1" hexmask.long.byte 0x1B8 24.--27. 1. "HLEN45,Huffman length 45" hexmask.long.byte 0x1B8 16.--23. 1. "HCODE45,Huffman code 45" newline hexmask.long.byte 0x1B8 8.--11. 1. "HLEN44,Huffman length 44" hexmask.long.byte 0x1B8 0.--7. 1. "HCODE44,Huffman code 44" line.long 0x1BC "JPEG_HUFFENC_AC1_23,JPEG Huffman encoder AC1" hexmask.long.byte 0x1BC 24.--27. 1. "HLEN47,Huffman length 47" hexmask.long.byte 0x1BC 16.--23. 1. "HCODE47,Huffman code 47" newline hexmask.long.byte 0x1BC 8.--11. 1. "HLEN46,Huffman length 46" hexmask.long.byte 0x1BC 0.--7. 1. "HCODE46,Huffman code 46" line.long 0x1C0 "JPEG_HUFFENC_AC1_24,JPEG Huffman encoder AC1" hexmask.long.byte 0x1C0 24.--27. 1. "HLEN49,Huffman length 49" hexmask.long.byte 0x1C0 16.--23. 1. "HCODE49,Huffman code 49" newline hexmask.long.byte 0x1C0 8.--11. 1. "HLEN48,Huffman length 48" hexmask.long.byte 0x1C0 0.--7. 1. "HCODE48,Huffman code 48" line.long 0x1C4 "JPEG_HUFFENC_AC1_25,JPEG Huffman encoder AC1" hexmask.long.byte 0x1C4 24.--27. 1. "HLEN51,Huffman length 51" hexmask.long.byte 0x1C4 16.--23. 1. "HCODE51,Huffman code 51" newline hexmask.long.byte 0x1C4 8.--11. 1. "HLEN50,Huffman length 50" hexmask.long.byte 0x1C4 0.--7. 1. "HCODE50,Huffman code 50" line.long 0x1C8 "JPEG_HUFFENC_AC1_26,JPEG Huffman encoder AC1" hexmask.long.byte 0x1C8 24.--27. 1. "HLEN53,Huffman length 53" hexmask.long.byte 0x1C8 16.--23. 1. "HCODE53,Huffman code 53" newline hexmask.long.byte 0x1C8 8.--11. 1. "HLEN52,Huffman length 52" hexmask.long.byte 0x1C8 0.--7. 1. "HCODE52,Huffman code 52" line.long 0x1CC "JPEG_HUFFENC_AC1_27,JPEG Huffman encoder AC1" hexmask.long.byte 0x1CC 24.--27. 1. "HLEN55,Huffman length 55" hexmask.long.byte 0x1CC 16.--23. 1. "HCODE55,Huffman code 55" newline hexmask.long.byte 0x1CC 8.--11. 1. "HLEN54,Huffman length 54" hexmask.long.byte 0x1CC 0.--7. 1. "HCODE54,Huffman code 54" line.long 0x1D0 "JPEG_HUFFENC_AC1_28,JPEG Huffman encoder AC1" hexmask.long.byte 0x1D0 24.--27. 1. "HLEN57,Huffman length 57" hexmask.long.byte 0x1D0 16.--23. 1. "HCODE57,Huffman code 57" newline hexmask.long.byte 0x1D0 8.--11. 1. "HLEN56,Huffman length 56" hexmask.long.byte 0x1D0 0.--7. 1. "HCODE56,Huffman code 56" line.long 0x1D4 "JPEG_HUFFENC_AC1_29,JPEG Huffman encoder AC1" hexmask.long.byte 0x1D4 24.--27. 1. "HLEN59,Huffman length 59" hexmask.long.byte 0x1D4 16.--23. 1. "HCODE59,Huffman code 59" newline hexmask.long.byte 0x1D4 8.--11. 1. "HLEN58,Huffman length 58" hexmask.long.byte 0x1D4 0.--7. 1. "HCODE58,Huffman code 58" line.long 0x1D8 "JPEG_HUFFENC_AC1_30,JPEG Huffman encoder AC1" hexmask.long.byte 0x1D8 24.--27. 1. "HLEN61,Huffman length 61" hexmask.long.byte 0x1D8 16.--23. 1. "HCODE61,Huffman code 61" newline hexmask.long.byte 0x1D8 8.--11. 1. "HLEN60,Huffman length 60" hexmask.long.byte 0x1D8 0.--7. 1. "HCODE60,Huffman code 60" line.long 0x1DC "JPEG_HUFFENC_AC1_31,JPEG Huffman encoder AC1" hexmask.long.byte 0x1DC 24.--27. 1. "HLEN63,Huffman length 63" hexmask.long.byte 0x1DC 16.--23. 1. "HCODE63,Huffman code 63" newline hexmask.long.byte 0x1DC 8.--11. 1. "HLEN62,Huffman length 62" hexmask.long.byte 0x1DC 0.--7. 1. "HCODE62,Huffman code 62" line.long 0x1E0 "JPEG_HUFFENC_AC1_32,JPEG Huffman encoder AC1" hexmask.long.byte 0x1E0 24.--27. 1. "HLEN65,Huffman length 65" hexmask.long.byte 0x1E0 16.--23. 1. "HCODE65,Huffman code 65" newline hexmask.long.byte 0x1E0 8.--11. 1. "HLEN64,Huffman length 64" hexmask.long.byte 0x1E0 0.--7. 1. "HCODE64,Huffman code 64" line.long 0x1E4 "JPEG_HUFFENC_AC1_33,JPEG Huffman encoder AC1" hexmask.long.byte 0x1E4 24.--27. 1. "HLEN67,Huffman length 67" hexmask.long.byte 0x1E4 16.--23. 1. "HCODE67,Huffman code 67" newline hexmask.long.byte 0x1E4 8.--11. 1. "HLEN66,Huffman length 66" hexmask.long.byte 0x1E4 0.--7. 1. "HCODE66,Huffman code 66" line.long 0x1E8 "JPEG_HUFFENC_AC1_34,JPEG Huffman encoder AC1" hexmask.long.byte 0x1E8 24.--27. 1. "HLEN69,Huffman length 69" hexmask.long.byte 0x1E8 16.--23. 1. "HCODE69,Huffman code 69" newline hexmask.long.byte 0x1E8 8.--11. 1. "HLEN68,Huffman length 68" hexmask.long.byte 0x1E8 0.--7. 1. "HCODE68,Huffman code 68" line.long 0x1EC "JPEG_HUFFENC_AC1_35,JPEG Huffman encoder AC1" hexmask.long.byte 0x1EC 24.--27. 1. "HLEN71,Huffman length 71" hexmask.long.byte 0x1EC 16.--23. 1. "HCODE71,Huffman code 71" newline hexmask.long.byte 0x1EC 8.--11. 1. "HLEN70,Huffman length 70" hexmask.long.byte 0x1EC 0.--7. 1. "HCODE70,Huffman code 70" line.long 0x1F0 "JPEG_HUFFENC_AC1_36,JPEG Huffman encoder AC1" hexmask.long.byte 0x1F0 24.--27. 1. "HLEN73,Huffman length 73" hexmask.long.byte 0x1F0 16.--23. 1. "HCODE73,Huffman code 73" newline hexmask.long.byte 0x1F0 8.--11. 1. "HLEN72,Huffman length 72" hexmask.long.byte 0x1F0 0.--7. 1. "HCODE72,Huffman code 72" line.long 0x1F4 "JPEG_HUFFENC_AC1_37,JPEG Huffman encoder AC1" hexmask.long.byte 0x1F4 24.--27. 1. "HLEN75,Huffman length 75" hexmask.long.byte 0x1F4 16.--23. 1. "HCODE75,Huffman code 75" newline hexmask.long.byte 0x1F4 8.--11. 1. "HLEN74,Huffman length 74" hexmask.long.byte 0x1F4 0.--7. 1. "HCODE74,Huffman code 74" line.long 0x1F8 "JPEG_HUFFENC_AC1_38,JPEG Huffman encoder AC1" hexmask.long.byte 0x1F8 24.--27. 1. "HLEN77,Huffman length 77" hexmask.long.byte 0x1F8 16.--23. 1. "HCODE77,Huffman code 77" newline hexmask.long.byte 0x1F8 8.--11. 1. "HLEN76,Huffman length 76" hexmask.long.byte 0x1F8 0.--7. 1. "HCODE76,Huffman code 76" line.long 0x1FC "JPEG_HUFFENC_AC1_39,JPEG Huffman encoder AC1" hexmask.long.byte 0x1FC 24.--27. 1. "HLEN79,Huffman length 79" hexmask.long.byte 0x1FC 16.--23. 1. "HCODE79,Huffman code 79" newline hexmask.long.byte 0x1FC 8.--11. 1. "HLEN78,Huffman length 78" hexmask.long.byte 0x1FC 0.--7. 1. "HCODE78,Huffman code 78" line.long 0x200 "JPEG_HUFFENC_AC1_40,JPEG Huffman encoder AC1" hexmask.long.byte 0x200 24.--27. 1. "HLEN81,Huffman length 81" hexmask.long.byte 0x200 16.--23. 1. "HCODE81,Huffman code 81" newline hexmask.long.byte 0x200 8.--11. 1. "HLEN80,Huffman length 80" hexmask.long.byte 0x200 0.--7. 1. "HCODE80,Huffman code 80" line.long 0x204 "JPEG_HUFFENC_AC1_41,JPEG Huffman encoder AC1" hexmask.long.byte 0x204 24.--27. 1. "HLEN83,Huffman length 83" hexmask.long.byte 0x204 16.--23. 1. "HCODE83,Huffman code 83" newline hexmask.long.byte 0x204 8.--11. 1. "HLEN82,Huffman length 82" hexmask.long.byte 0x204 0.--7. 1. "HCODE82,Huffman code 82" line.long 0x208 "JPEG_HUFFENC_AC1_42,JPEG Huffman encoder AC1" hexmask.long.byte 0x208 24.--27. 1. "HLEN85,Huffman length 85" hexmask.long.byte 0x208 16.--23. 1. "HCODE85,Huffman code 85" newline hexmask.long.byte 0x208 8.--11. 1. "HLEN84,Huffman length 84" hexmask.long.byte 0x208 0.--7. 1. "HCODE84,Huffman code 84" line.long 0x20C "JPEG_HUFFENC_AC1_43,JPEG Huffman encoder AC1" hexmask.long.byte 0x20C 24.--27. 1. "HLEN87,Huffman length 87" hexmask.long.byte 0x20C 16.--23. 1. "HCODE87,Huffman code 87" newline hexmask.long.byte 0x20C 8.--11. 1. "HLEN86,Huffman length 86" hexmask.long.byte 0x20C 0.--7. 1. "HCODE86,Huffman code 86" line.long 0x210 "JPEG_HUFFENC_AC1_44,JPEG Huffman encoder AC1" hexmask.long.byte 0x210 24.--27. 1. "HLEN89,Huffman length 89" hexmask.long.byte 0x210 16.--23. 1. "HCODE89,Huffman code 89" newline hexmask.long.byte 0x210 8.--11. 1. "HLEN88,Huffman length 88" hexmask.long.byte 0x210 0.--7. 1. "HCODE88,Huffman code 88" line.long 0x214 "JPEG_HUFFENC_AC1_45,JPEG Huffman encoder AC1" hexmask.long.byte 0x214 24.--27. 1. "HLEN91,Huffman length 91" hexmask.long.byte 0x214 16.--23. 1. "HCODE91,Huffman code 91" newline hexmask.long.byte 0x214 8.--11. 1. "HLEN90,Huffman length 90" hexmask.long.byte 0x214 0.--7. 1. "HCODE90,Huffman code 90" line.long 0x218 "JPEG_HUFFENC_AC1_46,JPEG Huffman encoder AC1" hexmask.long.byte 0x218 24.--27. 1. "HLEN93,Huffman length 93" hexmask.long.byte 0x218 16.--23. 1. "HCODE93,Huffman code 93" newline hexmask.long.byte 0x218 8.--11. 1. "HLEN92,Huffman length 92" hexmask.long.byte 0x218 0.--7. 1. "HCODE92,Huffman code 92" line.long 0x21C "JPEG_HUFFENC_AC1_47,JPEG Huffman encoder AC1" hexmask.long.byte 0x21C 24.--27. 1. "HLEN95,Huffman length 95" hexmask.long.byte 0x21C 16.--23. 1. "HCODE95,Huffman code 95" newline hexmask.long.byte 0x21C 8.--11. 1. "HLEN94,Huffman length 94" hexmask.long.byte 0x21C 0.--7. 1. "HCODE94,Huffman code 94" line.long 0x220 "JPEG_HUFFENC_AC1_48,JPEG Huffman encoder AC1" hexmask.long.byte 0x220 24.--27. 1. "HLEN97,Huffman length 97" hexmask.long.byte 0x220 16.--23. 1. "HCODE97,Huffman code 97" newline hexmask.long.byte 0x220 8.--11. 1. "HLEN96,Huffman length 96" hexmask.long.byte 0x220 0.--7. 1. "HCODE96,Huffman code 96" line.long 0x224 "JPEG_HUFFENC_AC1_49,JPEG Huffman encoder AC1" hexmask.long.byte 0x224 24.--27. 1. "HLEN99,Huffman length 99" hexmask.long.byte 0x224 16.--23. 1. "HCODE99,Huffman code 99" newline hexmask.long.byte 0x224 8.--11. 1. "HLEN98,Huffman length 98" hexmask.long.byte 0x224 0.--7. 1. "HCODE98,Huffman code 98" line.long 0x228 "JPEG_HUFFENC_AC1_50,JPEG Huffman encoder AC1" hexmask.long.byte 0x228 24.--27. 1. "HLEN101,Huffman length 101" hexmask.long.byte 0x228 16.--23. 1. "HCODE101,Huffman code 101" newline hexmask.long.byte 0x228 8.--11. 1. "HLEN100,Huffman length 100" hexmask.long.byte 0x228 0.--7. 1. "HCODE100,Huffman code 100" line.long 0x22C "JPEG_HUFFENC_AC1_51,JPEG Huffman encoder AC1" hexmask.long.byte 0x22C 24.--27. 1. "HLEN103,Huffman length 103" hexmask.long.byte 0x22C 16.--23. 1. "HCODE103,Huffman code 103" newline hexmask.long.byte 0x22C 8.--11. 1. "HLEN102,Huffman length 102" hexmask.long.byte 0x22C 0.--7. 1. "HCODE102,Huffman code 102" line.long 0x230 "JPEG_HUFFENC_AC1_52,JPEG Huffman encoder AC1" hexmask.long.byte 0x230 24.--27. 1. "HLEN105,Huffman length 105" hexmask.long.byte 0x230 16.--23. 1. "HCODE105,Huffman code 105" newline hexmask.long.byte 0x230 8.--11. 1. "HLEN104,Huffman length 104" hexmask.long.byte 0x230 0.--7. 1. "HCODE104,Huffman code 104" line.long 0x234 "JPEG_HUFFENC_AC1_53,JPEG Huffman encoder AC1" hexmask.long.byte 0x234 24.--27. 1. "HLEN107,Huffman length 107" hexmask.long.byte 0x234 16.--23. 1. "HCODE107,Huffman code 107" newline hexmask.long.byte 0x234 8.--11. 1. "HLEN106,Huffman length 106" hexmask.long.byte 0x234 0.--7. 1. "HCODE106,Huffman code 106" line.long 0x238 "JPEG_HUFFENC_AC1_54,JPEG Huffman encoder AC1" hexmask.long.byte 0x238 24.--27. 1. "HLEN109,Huffman length 109" hexmask.long.byte 0x238 16.--23. 1. "HCODE109,Huffman code 109" newline hexmask.long.byte 0x238 8.--11. 1. "HLEN108,Huffman length 108" hexmask.long.byte 0x238 0.--7. 1. "HCODE108,Huffman code 108" line.long 0x23C "JPEG_HUFFENC_AC1_55,JPEG Huffman encoder AC1" hexmask.long.byte 0x23C 24.--27. 1. "HLEN111,Huffman length 111" hexmask.long.byte 0x23C 16.--23. 1. "HCODE111,Huffman code 111" newline hexmask.long.byte 0x23C 8.--11. 1. "HLEN110,Huffman length 110" hexmask.long.byte 0x23C 0.--7. 1. "HCODE110,Huffman code 110" line.long 0x240 "JPEG_HUFFENC_AC1_56,JPEG Huffman encoder AC1" hexmask.long.byte 0x240 24.--27. 1. "HLEN113,Huffman length 113" hexmask.long.byte 0x240 16.--23. 1. "HCODE113,Huffman code 113" newline hexmask.long.byte 0x240 8.--11. 1. "HLEN112,Huffman length 112" hexmask.long.byte 0x240 0.--7. 1. "HCODE112,Huffman code 112" line.long 0x244 "JPEG_HUFFENC_AC1_57,JPEG Huffman encoder AC1" hexmask.long.byte 0x244 24.--27. 1. "HLEN115,Huffman length 115" hexmask.long.byte 0x244 16.--23. 1. "HCODE115,Huffman code 115" newline hexmask.long.byte 0x244 8.--11. 1. "HLEN114,Huffman length 114" hexmask.long.byte 0x244 0.--7. 1. "HCODE114,Huffman code 114" line.long 0x248 "JPEG_HUFFENC_AC1_58,JPEG Huffman encoder AC1" hexmask.long.byte 0x248 24.--27. 1. "HLEN117,Huffman length 117" hexmask.long.byte 0x248 16.--23. 1. "HCODE117,Huffman code 117" newline hexmask.long.byte 0x248 8.--11. 1. "HLEN116,Huffman length 116" hexmask.long.byte 0x248 0.--7. 1. "HCODE116,Huffman code 116" line.long 0x24C "JPEG_HUFFENC_AC1_59,JPEG Huffman encoder AC1" hexmask.long.byte 0x24C 24.--27. 1. "HLEN119,Huffman length 119" hexmask.long.byte 0x24C 16.--23. 1. "HCODE119,Huffman code 119" newline hexmask.long.byte 0x24C 8.--11. 1. "HLEN118,Huffman length 118" hexmask.long.byte 0x24C 0.--7. 1. "HCODE118,Huffman code 118" line.long 0x250 "JPEG_HUFFENC_AC1_60,JPEG Huffman encoder AC1" hexmask.long.byte 0x250 24.--27. 1. "HLEN121,Huffman length 121" hexmask.long.byte 0x250 16.--23. 1. "HCODE121,Huffman code 121" newline hexmask.long.byte 0x250 8.--11. 1. "HLEN120,Huffman length 120" hexmask.long.byte 0x250 0.--7. 1. "HCODE120,Huffman code 120" line.long 0x254 "JPEG_HUFFENC_AC1_61,JPEG Huffman encoder AC1" hexmask.long.byte 0x254 24.--27. 1. "HLEN123,Huffman length 123" hexmask.long.byte 0x254 16.--23. 1. "HCODE123,Huffman code 123" newline hexmask.long.byte 0x254 8.--11. 1. "HLEN122,Huffman length 122" hexmask.long.byte 0x254 0.--7. 1. "HCODE122,Huffman code 122" line.long 0x258 "JPEG_HUFFENC_AC1_62,JPEG Huffman encoder AC1" hexmask.long.byte 0x258 24.--27. 1. "HLEN125,Huffman length 125" hexmask.long.byte 0x258 16.--23. 1. "HCODE125,Huffman code 125" newline hexmask.long.byte 0x258 8.--11. 1. "HLEN124,Huffman length 124" hexmask.long.byte 0x258 0.--7. 1. "HCODE124,Huffman code 124" line.long 0x25C "JPEG_HUFFENC_AC1_63,JPEG Huffman encoder AC1" hexmask.long.byte 0x25C 24.--27. 1. "HLEN127,Huffman length 127" hexmask.long.byte 0x25C 16.--23. 1. "HCODE127,Huffman code 127" newline hexmask.long.byte 0x25C 8.--11. 1. "HLEN126,Huffman length 126" hexmask.long.byte 0x25C 0.--7. 1. "HCODE126,Huffman code 126" line.long 0x260 "JPEG_HUFFENC_AC1_64,JPEG Huffman encoder AC1" hexmask.long.byte 0x260 24.--27. 1. "HLEN129,Huffman length 129" hexmask.long.byte 0x260 16.--23. 1. "HCODE129,Huffman code 129" newline hexmask.long.byte 0x260 8.--11. 1. "HLEN128,Huffman length 128" hexmask.long.byte 0x260 0.--7. 1. "HCODE128,Huffman code 128" line.long 0x264 "JPEG_HUFFENC_AC1_65,JPEG Huffman encoder AC1" hexmask.long.byte 0x264 24.--27. 1. "HLEN131,Huffman length 131" hexmask.long.byte 0x264 16.--23. 1. "HCODE131,Huffman code 131" newline hexmask.long.byte 0x264 8.--11. 1. "HLEN130,Huffman length 130" hexmask.long.byte 0x264 0.--7. 1. "HCODE130,Huffman code 130" line.long 0x268 "JPEG_HUFFENC_AC1_66,JPEG Huffman encoder AC1" hexmask.long.byte 0x268 24.--27. 1. "HLEN133,Huffman length 133" hexmask.long.byte 0x268 16.--23. 1. "HCODE133,Huffman code 133" newline hexmask.long.byte 0x268 8.--11. 1. "HLEN132,Huffman length 132" hexmask.long.byte 0x268 0.--7. 1. "HCODE132,Huffman code 132" line.long 0x26C "JPEG_HUFFENC_AC1_67,JPEG Huffman encoder AC1" hexmask.long.byte 0x26C 24.--27. 1. "HLEN135,Huffman length 135" hexmask.long.byte 0x26C 16.--23. 1. "HCODE135,Huffman code 135" newline hexmask.long.byte 0x26C 8.--11. 1. "HLEN134,Huffman length 134" hexmask.long.byte 0x26C 0.--7. 1. "HCODE134,Huffman code 134" line.long 0x270 "JPEG_HUFFENC_AC1_68,JPEG Huffman encoder AC1" hexmask.long.byte 0x270 24.--27. 1. "HLEN137,Huffman length 137" hexmask.long.byte 0x270 16.--23. 1. "HCODE137,Huffman code 137" newline hexmask.long.byte 0x270 8.--11. 1. "HLEN136,Huffman length 136" hexmask.long.byte 0x270 0.--7. 1. "HCODE136,Huffman code 136" line.long 0x274 "JPEG_HUFFENC_AC1_69,JPEG Huffman encoder AC1" hexmask.long.byte 0x274 24.--27. 1. "HLEN139,Huffman length 139" hexmask.long.byte 0x274 16.--23. 1. "HCODE139,Huffman code 139" newline hexmask.long.byte 0x274 8.--11. 1. "HLEN138,Huffman length 138" hexmask.long.byte 0x274 0.--7. 1. "HCODE138,Huffman code 138" line.long 0x278 "JPEG_HUFFENC_AC1_70,JPEG Huffman encoder AC1" hexmask.long.byte 0x278 24.--27. 1. "HLEN141,Huffman length 141" hexmask.long.byte 0x278 16.--23. 1. "HCODE141,Huffman code 141" newline hexmask.long.byte 0x278 8.--11. 1. "HLEN140,Huffman length 140" hexmask.long.byte 0x278 0.--7. 1. "HCODE140,Huffman code 140" line.long 0x27C "JPEG_HUFFENC_AC1_71,JPEG Huffman encoder AC1" hexmask.long.byte 0x27C 24.--27. 1. "HLEN143,Huffman length 143" hexmask.long.byte 0x27C 16.--23. 1. "HCODE143,Huffman code 143" newline hexmask.long.byte 0x27C 8.--11. 1. "HLEN142,Huffman length 142" hexmask.long.byte 0x27C 0.--7. 1. "HCODE142,Huffman code 142" line.long 0x280 "JPEG_HUFFENC_AC1_72,JPEG Huffman encoder AC1" hexmask.long.byte 0x280 24.--27. 1. "HLEN145,Huffman length 145" hexmask.long.byte 0x280 16.--23. 1. "HCODE145,Huffman code 145" newline hexmask.long.byte 0x280 8.--11. 1. "HLEN144,Huffman length 144" hexmask.long.byte 0x280 0.--7. 1. "HCODE144,Huffman code 144" line.long 0x284 "JPEG_HUFFENC_AC1_73,JPEG Huffman encoder AC1" hexmask.long.byte 0x284 24.--27. 1. "HLEN147,Huffman length 147" hexmask.long.byte 0x284 16.--23. 1. "HCODE147,Huffman code 147" newline hexmask.long.byte 0x284 8.--11. 1. "HLEN146,Huffman length 146" hexmask.long.byte 0x284 0.--7. 1. "HCODE146,Huffman code 146" line.long 0x288 "JPEG_HUFFENC_AC1_74,JPEG Huffman encoder AC1" hexmask.long.byte 0x288 24.--27. 1. "HLEN149,Huffman length 149" hexmask.long.byte 0x288 16.--23. 1. "HCODE149,Huffman code 149" newline hexmask.long.byte 0x288 8.--11. 1. "HLEN148,Huffman length 148" hexmask.long.byte 0x288 0.--7. 1. "HCODE148,Huffman code 148" line.long 0x28C "JPEG_HUFFENC_AC1_75,JPEG Huffman encoder AC1" hexmask.long.byte 0x28C 24.--27. 1. "HLEN151,Huffman length 151" hexmask.long.byte 0x28C 16.--23. 1. "HCODE151,Huffman code 151" newline hexmask.long.byte 0x28C 8.--11. 1. "HLEN150,Huffman length 150" hexmask.long.byte 0x28C 0.--7. 1. "HCODE150,Huffman code 150" line.long 0x290 "JPEG_HUFFENC_AC1_76,JPEG Huffman encoder AC1" hexmask.long.byte 0x290 24.--27. 1. "HLEN153,Huffman length 153" hexmask.long.byte 0x290 16.--23. 1. "HCODE153,Huffman code 153" newline hexmask.long.byte 0x290 8.--11. 1. "HLEN152,Huffman length 152" hexmask.long.byte 0x290 0.--7. 1. "HCODE152,Huffman code 152" line.long 0x294 "JPEG_HUFFENC_AC1_77,JPEG Huffman encoder AC1" hexmask.long.byte 0x294 24.--27. 1. "HLEN155,Huffman length 155" hexmask.long.byte 0x294 16.--23. 1. "HCODE155,Huffman code 155" newline hexmask.long.byte 0x294 8.--11. 1. "HLEN154,Huffman length 154" hexmask.long.byte 0x294 0.--7. 1. "HCODE154,Huffman code 154" line.long 0x298 "JPEG_HUFFENC_AC1_78,JPEG Huffman encoder AC1" hexmask.long.byte 0x298 24.--27. 1. "HLEN157,Huffman length 157" hexmask.long.byte 0x298 16.--23. 1. "HCODE157,Huffman code 157" newline hexmask.long.byte 0x298 8.--11. 1. "HLEN156,Huffman length 156" hexmask.long.byte 0x298 0.--7. 1. "HCODE156,Huffman code 156" line.long 0x29C "JPEG_HUFFENC_AC1_79,JPEG Huffman encoder AC1" hexmask.long.byte 0x29C 24.--27. 1. "HLEN159,Huffman length 159" hexmask.long.byte 0x29C 16.--23. 1. "HCODE159,Huffman code 159" newline hexmask.long.byte 0x29C 8.--11. 1. "HLEN158,Huffman length 158" hexmask.long.byte 0x29C 0.--7. 1. "HCODE158,Huffman code 158" line.long 0x2A0 "JPEG_HUFFENC_AC1_80,JPEG Huffman encoder AC1" hexmask.long.byte 0x2A0 24.--27. 1. "HLEN161,Huffman length 161" hexmask.long.byte 0x2A0 16.--23. 1. "HCODE161,Huffman code 161" newline hexmask.long.byte 0x2A0 8.--11. 1. "HLEN160,Huffman length 160" hexmask.long.byte 0x2A0 0.--7. 1. "HCODE160,Huffman code 160" line.long 0x2A4 "JPEG_HUFFENC_AC1_81,JPEG Huffman encoder AC1" hexmask.long.byte 0x2A4 24.--27. 1. "HLEN163,Huffman length 163" hexmask.long.byte 0x2A4 16.--23. 1. "HCODE163,Huffman code 163" newline hexmask.long.byte 0x2A4 8.--11. 1. "HLEN162,Huffman length 162" hexmask.long.byte 0x2A4 0.--7. 1. "HCODE162,Huffman code 162" line.long 0x2A8 "JPEG_HUFFENC_AC1_82,JPEG Huffman encoder AC1" hexmask.long.byte 0x2A8 24.--27. 1. "HLEN165,Huffman length 165" hexmask.long.byte 0x2A8 16.--23. 1. "HCODE165,Huffman code 165" newline hexmask.long.byte 0x2A8 8.--11. 1. "HLEN164,Huffman length 164" hexmask.long.byte 0x2A8 0.--7. 1. "HCODE164,Huffman code 164" line.long 0x2AC "JPEG_HUFFENC_AC1_83,JPEG Huffman encoder AC1" hexmask.long.byte 0x2AC 24.--27. 1. "HLEN167,Huffman length 167" hexmask.long.byte 0x2AC 16.--23. 1. "HCODE167,Huffman code 167" newline hexmask.long.byte 0x2AC 8.--11. 1. "HLEN166,Huffman length 166" hexmask.long.byte 0x2AC 0.--7. 1. "HCODE166,Huffman code 166" line.long 0x2B0 "JPEG_HUFFENC_AC1_84,JPEG Huffman encoder AC1" hexmask.long.byte 0x2B0 24.--27. 1. "HLEN169,Huffman length 169" hexmask.long.byte 0x2B0 16.--23. 1. "HCODE169,Huffman code 169" newline hexmask.long.byte 0x2B0 8.--11. 1. "HLEN168,Huffman length 168" hexmask.long.byte 0x2B0 0.--7. 1. "HCODE168,Huffman code 168" line.long 0x2B4 "JPEG_HUFFENC_AC1_85,JPEG Huffman encoder AC1" hexmask.long.byte 0x2B4 24.--27. 1. "HLEN171,Huffman length 171" hexmask.long.byte 0x2B4 16.--23. 1. "HCODE171,Huffman code 171" newline hexmask.long.byte 0x2B4 8.--11. 1. "HLEN170,Huffman length 170" hexmask.long.byte 0x2B4 0.--7. 1. "HCODE170,Huffman code 170" line.long 0x2B8 "JPEG_HUFFENC_AC1_86,JPEG Huffman encoder AC1" hexmask.long.byte 0x2B8 24.--27. 1. "HLEN173,Huffman length 173" hexmask.long.byte 0x2B8 16.--23. 1. "HCODE173,Huffman code 173" newline hexmask.long.byte 0x2B8 8.--11. 1. "HLEN172,Huffman length 172" hexmask.long.byte 0x2B8 0.--7. 1. "HCODE172,Huffman code 172" line.long 0x2BC "JPEG_HUFFENC_AC1_87,JPEG Huffman encoder AC1" hexmask.long.byte 0x2BC 24.--27. 1. "HLEN175,Huffman length 175" hexmask.long.byte 0x2BC 16.--23. 1. "HCODE175,Huffman code 175" newline hexmask.long.byte 0x2BC 8.--11. 1. "HLEN174,Huffman length 174" hexmask.long.byte 0x2BC 0.--7. 1. "HCODE174,Huffman code 174" line.long 0x2C0 "JPEG_HUFFENC_DC0_0,JPEG Huffman encoder DC0" hexmask.long.byte 0x2C0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x2C0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x2C0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x2C0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x2C4 "JPEG_HUFFENC_DC0_1,JPEG Huffman encoder DC0" hexmask.long.byte 0x2C4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x2C4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x2C4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x2C4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x2C8 "JPEG_HUFFENC_DC0_2,JPEG Huffman encoder DC0" hexmask.long.byte 0x2C8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x2C8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x2C8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x2C8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0x2CC "JPEG_HUFFENC_DC0_3,JPEG Huffman encoder DC0" hexmask.long.byte 0x2CC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0x2CC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0x2CC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0x2CC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x2D0 "JPEG_HUFFENC_DC0_4,JPEG Huffman encoder DC0" hexmask.long.byte 0x2D0 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x2D0 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x2D0 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x2D0 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x2D4 "JPEG_HUFFENC_DC0_5,JPEG Huffman encoder DC0" hexmask.long.byte 0x2D4 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x2D4 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x2D4 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x2D4 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x2D8 "JPEG_HUFFENC_DC0_6,JPEG Huffman encoder DC0" hexmask.long.byte 0x2D8 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x2D8 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x2D8 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x2D8 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x2DC "JPEG_HUFFENC_DC0_7,JPEG Huffman encoder DC0" hexmask.long.byte 0x2DC 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x2DC 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x2DC 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x2DC 0.--7. 1. "HCODE14,Huffman code 14" line.long 0x2E0 "JPEG_HUFFENC_DC1_0,JPEG Huffman encoder DC1" hexmask.long.byte 0x2E0 24.--27. 1. "HLEN1,Huffman length 1" hexmask.long.byte 0x2E0 16.--23. 1. "HCODE1,Huffman code 1" newline hexmask.long.byte 0x2E0 8.--11. 1. "HLEN0,Huffman length 0" hexmask.long.byte 0x2E0 0.--7. 1. "HCODE0,Huffman code 0" line.long 0x2E4 "JPEG_HUFFENC_DC1_1,JPEG Huffman encoder DC1" hexmask.long.byte 0x2E4 24.--27. 1. "HLEN3,Huffman length 3" hexmask.long.byte 0x2E4 16.--23. 1. "HCODE3,Huffman code 3" newline hexmask.long.byte 0x2E4 8.--11. 1. "HLEN2,Huffman length 2" hexmask.long.byte 0x2E4 0.--7. 1. "HCODE2,Huffman code 2" line.long 0x2E8 "JPEG_HUFFENC_DC1_2,JPEG Huffman encoder DC1" hexmask.long.byte 0x2E8 24.--27. 1. "HLEN5,Huffman length 5" hexmask.long.byte 0x2E8 16.--23. 1. "HCODE5,Huffman code 5" newline hexmask.long.byte 0x2E8 8.--11. 1. "HLEN4,Huffman length 4" hexmask.long.byte 0x2E8 0.--7. 1. "HCODE4,Huffman code 4" line.long 0x2EC "JPEG_HUFFENC_DC1_3,JPEG Huffman encoder DC1" hexmask.long.byte 0x2EC 24.--27. 1. "HLEN7,Huffman length 7" hexmask.long.byte 0x2EC 16.--23. 1. "HCODE7,Huffman code 7" newline hexmask.long.byte 0x2EC 8.--11. 1. "HLEN6,Huffman length 6" hexmask.long.byte 0x2EC 0.--7. 1. "HCODE6,Huffman code 6" line.long 0x2F0 "JPEG_HUFFENC_DC1_4,JPEG Huffman encoder DC1" hexmask.long.byte 0x2F0 24.--27. 1. "HLEN9,Huffman length 9" hexmask.long.byte 0x2F0 16.--23. 1. "HCODE9,Huffman code 9" newline hexmask.long.byte 0x2F0 8.--11. 1. "HLEN8,Huffman length 8" hexmask.long.byte 0x2F0 0.--7. 1. "HCODE8,Huffman code 8" line.long 0x2F4 "JPEG_HUFFENC_DC1_5,JPEG Huffman encoder DC1" hexmask.long.byte 0x2F4 24.--27. 1. "HLEN11,Huffman length 11" hexmask.long.byte 0x2F4 16.--23. 1. "HCODE11,Huffman code 11" newline hexmask.long.byte 0x2F4 8.--11. 1. "HLEN10,Huffman length 10" hexmask.long.byte 0x2F4 0.--7. 1. "HCODE10,Huffman code 10" line.long 0x2F8 "JPEG_HUFFENC_DC1_6,JPEG Huffman encoder DC1" hexmask.long.byte 0x2F8 24.--27. 1. "HLEN13,Huffman length 13" hexmask.long.byte 0x2F8 16.--23. 1. "HCODE13,Huffman code 13" newline hexmask.long.byte 0x2F8 8.--11. 1. "HLEN12,Huffman length 12" hexmask.long.byte 0x2F8 0.--7. 1. "HCODE12,Huffman code 12" line.long 0x2FC "JPEG_HUFFENC_DC1_7,JPEG Huffman encoder DC1" hexmask.long.byte 0x2FC 24.--27. 1. "HLEN15,Huffman length 15" hexmask.long.byte 0x2FC 16.--23. 1. "HCODE15,Huffman code 15" newline hexmask.long.byte 0x2FC 8.--11. 1. "HLEN14,Huffman length 14" hexmask.long.byte 0x2FC 0.--7. 1. "HCODE14,Huffman code 14" tree.end tree.end tree "LPTIM (Low Power Timer)" base ad:0x0 sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_OUTPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_INPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_OUTPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_INPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM1_DIER_OUTPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM1_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM1_CFGR,LPTIM1 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM1_CR,LPTIM1 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM1_CCR1,LPTIM1 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM1_ARR,LPTIM1 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM1_CNT,LPTIM1 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM1_CFGR2,LPTIM1 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM1_RCR,LPTIM1 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM1_CCMR1,LPTIM1 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline sif (cpuis("STM32N645*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: rising edge circuit is sensitive to IC2 rising..,1: falling edge circuit is sensitive to IC2 falling..,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: rising edge circuit is sensitive to IC1 rising..,1: falling edge circuit is sensitive to IC1 falling..,?,3: both edges circuit is sensitive to both IC1.." newline endif sif (cpuis("STM32N647*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." endif bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" sif (cpuis("STM32N647*")) bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline endif bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM1_CCR2,LPTIM1 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32N655*")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_OUTPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_INPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_OUTPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_INPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM1_DIER_OUTPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM1_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM1_CFGR,LPTIM1 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM1_CR,LPTIM1 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM1_CCR1,LPTIM1 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM1_ARR,LPTIM1 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM1_CNT,LPTIM1 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM1_CFGR2,LPTIM1 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM1_RCR,LPTIM1 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM1_CCMR1,LPTIM1 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM1_CCR2,LPTIM1 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "LPTIM1_S" base ad:0x50002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_OUTPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_INPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_OUTPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_INPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM1_DIER_OUTPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM1_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM1_CFGR,LPTIM1 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM1_CR,LPTIM1 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM1_CCR1,LPTIM1 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM1_ARR,LPTIM1 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM1_CNT,LPTIM1 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM1_CFGR2,LPTIM1 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM1_RCR,LPTIM1 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM1_CCMR1,LPTIM1 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM1_CCR2,LPTIM1 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "LPTIM2_S" base ad:0x56002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_OUTPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_INPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_OUTPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_INPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM2_DIER_OUTPUT,LPTIM2 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM2_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM2_CFGR,LPTIM2 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM2_CR,LPTIM2 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM2_CCR1,LPTIM2 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM2_ARR,LPTIM2 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM2_CNT,LPTIM2 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM2_CFGR2,LPTIM2 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM2_RCR,LPTIM2 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM2_CCMR1,LPTIM2 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM2_CCR2,LPTIM2 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "LPTIM3_S" base ad:0x56002800 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_OUTPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_INPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_OUTPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_INPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM3_DIER_OUTPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM3_DIER_INPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM3_CFGR,LPTIM3 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM3_CR,LPTIM3 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM3_CCR1,LPTIM3 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM3_ARR,LPTIM3 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM3_CNT,LPTIM3 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM3_CFGR2,LPTIM3 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM3_RCR,LPTIM3 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM3_CCMR1,LPTIM3 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM3_CCR2,LPTIM3 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32N657*")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_OUTPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_INPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_OUTPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_INPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM1_DIER_OUTPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM1_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM1_CFGR,LPTIM1 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM1_CR,LPTIM1 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM1_CCR1,LPTIM1 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM1_ARR,LPTIM1 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM1_CNT,LPTIM1 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM1_CFGR2,LPTIM1 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM1_RCR,LPTIM1 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM1_CCMR1,LPTIM1 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM1_CCR2,LPTIM1 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "LPTIM1_S" base ad:0x50002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_OUTPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_INPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_OUTPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_INPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM1_DIER_OUTPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM1_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM1_CFGR,LPTIM1 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM1_CR,LPTIM1 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM1_CCR1,LPTIM1 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM1_ARR,LPTIM1 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM1_CNT,LPTIM1 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM1_CFGR2,LPTIM1 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM1_RCR,LPTIM1 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM1_CCMR1,LPTIM1 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM1_CCR2,LPTIM1 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "LPTIM2_S" base ad:0x56002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_OUTPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_INPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_OUTPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_INPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM2_DIER_OUTPUT,LPTIM2 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM2_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM2_CFGR,LPTIM2 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM2_CR,LPTIM2 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM2_CCR1,LPTIM2 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM2_ARR,LPTIM2 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM2_CNT,LPTIM2 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM2_CFGR2,LPTIM2 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM2_RCR,LPTIM2 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM2_CCMR1,LPTIM2 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM2_CCR2,LPTIM2 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "LPTIM3_S" base ad:0x56002800 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_OUTPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_INPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_OUTPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_INPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM3_DIER_OUTPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM3_DIER_INPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM3_CFGR,LPTIM3 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM3_CR,LPTIM3 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM3_CCR1,LPTIM3 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM3_ARR,LPTIM3 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM3_CNT,LPTIM3 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM3_CFGR2,LPTIM3 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM3_RCR,LPTIM3 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM3_CCMR1,LPTIM3 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM3_CCR2,LPTIM3 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32N655*")) tree "LPTIM2" base ad:0x46002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_OUTPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_INPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_OUTPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_INPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM2_DIER_OUTPUT,LPTIM2 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM2_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM2_CFGR,LPTIM2 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM2_CR,LPTIM2 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM2_CCR1,LPTIM2 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM2_ARR,LPTIM2 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM2_CNT,LPTIM2 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM2_CFGR2,LPTIM2 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM2_RCR,LPTIM2 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM2_CCMR1,LPTIM2 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM2_CCR2,LPTIM2 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "LPTIM3" base ad:0x46002800 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_OUTPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_INPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_OUTPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_INPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM3_DIER_OUTPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM3_DIER_INPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM3_CFGR,LPTIM3 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM3_CR,LPTIM3 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM3_CCR1,LPTIM3 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM3_ARR,LPTIM3 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM3_CNT,LPTIM3 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM3_CFGR2,LPTIM3 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM3_RCR,LPTIM3 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM3_CCMR1,LPTIM3 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM3_CCR2,LPTIM3 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32N657*")) tree "LPTIM2" base ad:0x46002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_OUTPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_INPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_OUTPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_INPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM2_DIER_OUTPUT,LPTIM2 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM2_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM2_CFGR,LPTIM2 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM2_CR,LPTIM2 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM2_CCR1,LPTIM2 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM2_ARR,LPTIM2 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM2_CNT,LPTIM2 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM2_CFGR2,LPTIM2 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM2_RCR,LPTIM2 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM2_CCMR1,LPTIM2 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM2_CCR2,LPTIM2 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "LPTIM3" base ad:0x46002800 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_OUTPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_INPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_OUTPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_INPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM3_DIER_OUTPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM3_DIER_INPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM3_CFGR,LPTIM3 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM3_CR,LPTIM3 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM3_CCR1,LPTIM3 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM3_ARR,LPTIM3 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM3_CNT,LPTIM3 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM3_CFGR2,LPTIM3 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM3_RCR,LPTIM3 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM3_CCMR1,LPTIM3 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM3_CCR2,LPTIM3 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "LPTIM1_S" base ad:0x50002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_OUTPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM1_ISR_INPUT,LPTIM1 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_OUTPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM1_ICR_INPUT,LPTIM1 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM1_DIER_OUTPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM1_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM1_CFGR,LPTIM1 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM1_CR,LPTIM1 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM1_CCR1,LPTIM1 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM1_ARR,LPTIM1 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM1_CNT,LPTIM1 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM1_CFGR2,LPTIM1 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM1_RCR,LPTIM1 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM1_CCMR1,LPTIM1 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline sif (cpuis("STM32N645*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: rising edge circuit is sensitive to IC2 rising..,1: falling edge circuit is sensitive to IC2 falling..,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: rising edge circuit is sensitive to IC1 rising..,1: falling edge circuit is sensitive to IC1 falling..,?,3: both edges circuit is sensitive to both IC1.." newline endif sif (cpuis("STM32N647*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." endif bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" sif (cpuis("STM32N647*")) bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline endif bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM1_CCR2,LPTIM1 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "LPTIM2" base ad:0x46002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_OUTPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_INPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_OUTPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_INPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM2_DIER_OUTPUT,LPTIM2 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM2_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM2_CFGR,LPTIM2 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM2_CR,LPTIM2 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM2_CCR1,LPTIM2 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM2_ARR,LPTIM2 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM2_CNT,LPTIM2 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM2_CFGR2,LPTIM2 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM2_RCR,LPTIM2 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM2_CCMR1,LPTIM2 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline sif (cpuis("STM32N645*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: rising edge circuit is sensitive to IC2 rising..,1: falling edge circuit is sensitive to IC2 falling..,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: rising edge circuit is sensitive to IC1 rising..,1: falling edge circuit is sensitive to IC1 falling..,?,3: both edges circuit is sensitive to both IC1.." newline endif sif (cpuis("STM32N647*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." endif bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" sif (cpuis("STM32N647*")) bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline endif bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM2_CCR2,LPTIM2 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "LPTIM2_S" base ad:0x56002400 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_OUTPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM2_ISR_INPUT,LPTIM2 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_OUTPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM2_ICR_INPUT,LPTIM2 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM2_DIER_OUTPUT,LPTIM2 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM2_DIER_INPUT,LPTIM1 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM2_CFGR,LPTIM2 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM2_CR,LPTIM2 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM2_CCR1,LPTIM2 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM2_ARR,LPTIM2 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM2_CNT,LPTIM2 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM2_CFGR2,LPTIM2 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM2_RCR,LPTIM2 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM2_CCMR1,LPTIM2 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline sif (cpuis("STM32N645*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: rising edge circuit is sensitive to IC2 rising..,1: falling edge circuit is sensitive to IC2 falling..,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: rising edge circuit is sensitive to IC1 rising..,1: falling edge circuit is sensitive to IC1 falling..,?,3: both edges circuit is sensitive to both IC1.." newline endif sif (cpuis("STM32N647*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." endif bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" sif (cpuis("STM32N647*")) bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline endif bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM2_CCR2,LPTIM2 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "LPTIM3" base ad:0x46002800 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_OUTPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_INPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_OUTPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_INPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM3_DIER_OUTPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM3_DIER_INPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM3_CFGR,LPTIM3 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM3_CR,LPTIM3 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM3_CCR1,LPTIM3 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM3_ARR,LPTIM3 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM3_CNT,LPTIM3 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM3_CFGR2,LPTIM3 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM3_RCR,LPTIM3 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM3_CCMR1,LPTIM3 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline sif (cpuis("STM32N645*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: rising edge circuit is sensitive to IC2 rising..,1: falling edge circuit is sensitive to IC2 falling..,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: rising edge circuit is sensitive to IC1 rising..,1: falling edge circuit is sensitive to IC1 falling..,?,3: both edges circuit is sensitive to both IC1.." newline endif sif (cpuis("STM32N647*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." endif bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" sif (cpuis("STM32N647*")) bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline endif bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM3_CCR2,LPTIM3 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "LPTIM3_S" base ad:0x56002800 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_OUTPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1" newline bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." rgroup.long 0x0++0x3 line.long 0x0 "LPTIM3_ISR_INPUT,LPTIM3 interrupt and status register [alternate]" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." newline bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.." bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." newline bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" newline bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_OUTPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1" newline bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM3_ICR_INPUT,LPTIM3 interrupt clear register [alternate]" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1" newline bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1" bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1" newline bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" newline bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x3 line.long 0x0 "LPTIM3_DIER_OUTPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled" newline bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" newline bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" newline bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" newline bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" group.long 0x8++0x13 line.long 0x0 "LPTIM3_DIER_INPUT,LPTIM3 interrupt enable register [alternate]" bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled" bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled" newline bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled" bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled" newline bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled" bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled" newline bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" newline bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM3_CFGR,LPTIM3 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM3_CR,LPTIM3 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM3_CCR1,LPTIM3 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM3_ARR,LPTIM3 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM3_CNT,LPTIM3 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM3_CFGR2,LPTIM3 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM3_RCR,LPTIM3 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM3_CCMR1,LPTIM3 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline sif (cpuis("STM32N645*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: rising edge circuit is sensitive to IC2 rising..,1: falling edge circuit is sensitive to IC2 falling..,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: rising edge circuit is sensitive to IC1 rising..,1: falling edge circuit is sensitive to IC1 falling..,?,3: both edges circuit is sensitive to both IC1.." newline endif sif (cpuis("STM32N647*")) bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." endif bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" sif (cpuis("STM32N647*")) bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline endif bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM3_CCR2,LPTIM3 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end endif tree "LPTIM4" base ad:0x46002C00 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM4_ISR,LPTIM4 interrupt and status register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM4_ICR,LPTIM4 interrupt clear register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM4_DIER,LPTIM4 interrupt enable register" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" newline bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM4_CFGR,LPTIM4 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM4_CR,LPTIM4 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM4_CCR1,LPTIM4 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM4_ARR,LPTIM4 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM4_CNT,LPTIM4 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM4_CFGR2,LPTIM4 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM4_RCR,LPTIM4 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM4_CCMR1,LPTIM4 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM4_CCR2,LPTIM4 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "LPTIM4_S" base ad:0x56002C00 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM4_ISR,LPTIM4 interrupt and status register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM4_ICR,LPTIM4 interrupt clear register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM4_DIER,LPTIM4 interrupt enable register" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" newline bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM4_CFGR,LPTIM4 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM4_CR,LPTIM4 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM4_CCR1,LPTIM4 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM4_ARR,LPTIM4 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM4_CNT,LPTIM4 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM4_CFGR2,LPTIM4 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM4_RCR,LPTIM4 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM4_CCMR1,LPTIM4 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM4_CCR2,LPTIM4 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "LPTIM5" base ad:0x46003000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM5_ISR,LPTIM5 interrupt and status register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM5_ICR,LPTIM5 interrupt clear register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM5_DIER,LPTIM5 interrupt enable register" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" newline bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM5_CFGR,LPTIM5 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM5_CR,LPTIM5 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM5_CCR1,LPTIM5 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM5_ARR,LPTIM5 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM5_CNT,LPTIM5 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM5_CFGR2,LPTIM5 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM5_RCR,LPTIM5 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM5_CCMR1,LPTIM5 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM5_CCR2,LPTIM5 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree "LPTIM5_S" base ad:0x56003000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM5_ISR,LPTIM5 interrupt and status register" bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1" bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1" newline bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" newline bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" newline bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" newline bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.." wgroup.long 0x4++0x3 line.long 0x0 "LPTIM5_ICR,LPTIM5 interrupt clear register" bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1" bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1" newline bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" newline bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" newline bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" newline bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM5_DIER,LPTIM5 interrupt enable register" bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled" bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled" newline bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" newline bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled" line.long 0x4 "LPTIM5_CFGR,LPTIM5 configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM5_CR,LPTIM5 control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled" line.long 0xC "LPTIM5_CCR1,LPTIM5 compare register 1" hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value" line.long 0x10 "LPTIM5_ARR,LPTIM5 autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM5_CNT,LPTIM5 counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0xB line.long 0x0 "LPTIM5_CFGR2,LPTIM5 configuration register 2" bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: lptim_ic2_mux0,1: lptim_ic2_mux1,2: lptim_ic2_mux2,3: lptim_ic2_mux3" bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: lptim_ic1_mux0,1: lptim_ic1_mux1,2: lptim_ic1_mux2,3: lptim_ic1_mux3" newline bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" line.long 0x4 "LPTIM5_RCR,LPTIM5 repetition register" hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value" line.long 0x8 "LPTIM5_CCMR1,LPTIM5 capture/compare mode register 1" bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0: OC2 active high,1: OC2 active low,?,3: both edges circuit is sensitive to both IC2.." bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0: Off - OC2 is not active. Writing '0' to the CC2E..,1: On - OC2 signal is output on the corresponding.." newline bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode" bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.." newline bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0: OC1 active high the LPTIM output reflects the..,1: OC1 active low the LPTIM output reflects the..,?,3: both edges circuit is sensitive to both IC1.." newline bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0: Off - OC1 is not active. Writing '0' to the CC1E..,1: On - OC1 signal is output on the corresponding.." bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode" group.long 0x34++0x3 line.long 0x0 "LPTIM5_CCR2,LPTIM5 compare register 2" hexmask.long.word 0x0 0.--15. 1. "CCR2,Capture/compare 2 value" tree.end tree.end tree "LPUART (Low Power Universal Synchronous Asynchronous Receiver)" base ad:0x0 tree "LPUART1" base ad:0x46000C00 group.long 0x0++0x3 line.long 0x0 "LPUART_CR1_ENABLED,LPUART control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when RXFF=1 in.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when TXFE=1 in.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.." bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." newline bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark" newline bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" newline bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.." bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXFNF.." newline bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.." bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.." newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.." bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" newline bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." newline bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled" group.long 0x0++0xF line.long 0x0 "LPUART_CR1_DISABLED,LPUART control register 1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.." bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." newline bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark" newline bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" newline bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.." bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXE =1.." newline bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.." bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.." newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.." bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" newline bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." newline bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled" line.long 0x4 "LPUART_CR2,LPUART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." newline bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." newline bitfld.long 0x4 12.--13. "STOP,STOP bits" "0: 1 stop bit,?,2: 2 stop bits,?" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" line.long 0x8 "LPUART_CR3,LPUART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth.,1: TXFIFO reaches 1/4 of its depth.,?,3: TXFIFO reaches 3/4 of its depth.,4: TXFIFO reaches 7/8 of its depth.,5: TXFIFO becomes empty.,6: TXFIFO reaches 1/2 of its depth.,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when Receive.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth.,1: Receive FIFO reaches 1/4 of its depth.,?,3: Receive FIFO reaches 3/4 of its depth.,4: Receive FIFO reaches 7/8 of its depth.,5: Receive FIFO becomes full.,6: Receive FIFO reaches 1/2 of its depth.,?" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when TXFIFO.." newline bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated when FE=1 or ORE=1 or.." line.long 0xC "LPUART_BRR,LPUART baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,LPUART baud rate division (LPUARTDIV)" wgroup.long 0x18++0x3 line.long 0x0 "LPUART_RQR,LPUART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "LPUART_ISR_ENABLED,LPUART interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO is not Full.,1: RXFIFO is Full." bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO is not empty.,1: TXFIFO is empty." newline bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" newline bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1" bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" newline bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" newline bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full." newline bitfld.long 0x0 6. "TC,Transmission complete" "0,1" bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." newline bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" newline bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected" bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" newline bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "LPUART_ISR_DISABLED,LPUART interrupt and status register" bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" newline bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1" bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" newline bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" newline bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full." newline bitfld.long 0x0 6. "TC,Transmission complete" "0,1" bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." newline bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" newline bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected" bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" newline bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "LPUART_ICR,LPUART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "LPUART_RDR,LPUART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "LPUART_TDR,LPUART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "LPUART_PRESC,LPUART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "LPUART1_S" base ad:0x56000C00 group.long 0x0++0x3 line.long 0x0 "LPUART_CR1_ENABLED,LPUART control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when RXFF=1 in.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when TXFE=1 in.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.." bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." newline bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark" newline bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" newline bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.." bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXFNF.." newline bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.." bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.." newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.." bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" newline bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." newline bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled" group.long 0x0++0xF line.long 0x0 "LPUART_CR1_DISABLED,LPUART control register 1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.." bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." newline bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark" newline bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" newline bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.." bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXE =1.." newline bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.." bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.." newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.." bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" newline bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." newline bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled" line.long 0x4 "LPUART_CR2,LPUART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." newline bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." newline bitfld.long 0x4 12.--13. "STOP,STOP bits" "0: 1 stop bit,?,2: 2 stop bits,?" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" line.long 0x8 "LPUART_CR3,LPUART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth.,1: TXFIFO reaches 1/4 of its depth.,?,3: TXFIFO reaches 3/4 of its depth.,4: TXFIFO reaches 7/8 of its depth.,5: TXFIFO becomes empty.,6: TXFIFO reaches 1/2 of its depth.,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when Receive.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth.,1: Receive FIFO reaches 1/4 of its depth.,?,3: Receive FIFO reaches 3/4 of its depth.,4: Receive FIFO reaches 7/8 of its depth.,5: Receive FIFO becomes full.,6: Receive FIFO reaches 1/2 of its depth.,?" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when TXFIFO.." newline bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated when FE=1 or ORE=1 or.." line.long 0xC "LPUART_BRR,LPUART baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,LPUART baud rate division (LPUARTDIV)" wgroup.long 0x18++0x3 line.long 0x0 "LPUART_RQR,LPUART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "LPUART_ISR_ENABLED,LPUART interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO is not Full.,1: RXFIFO is Full." bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO is not empty.,1: TXFIFO is empty." newline bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" newline bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1" bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" newline bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" newline bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full." newline bitfld.long 0x0 6. "TC,Transmission complete" "0,1" bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." newline bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" newline bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected" bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" newline bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "LPUART_ISR_DISABLED,LPUART interrupt and status register" bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" newline bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1" bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" newline bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" newline bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full." newline bitfld.long 0x0 6. "TC,Transmission complete" "0,1" bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." newline bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" newline bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected" bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" newline bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "LPUART_ICR,LPUART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "LPUART_RDR,LPUART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "LPUART_TDR,LPUART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "LPUART_PRESC,LPUART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree.end tree "LTDC (LCD-TFT Display Controller)" base ad:0x0 tree "LTDC" base ad:0x48001000 group.long 0x8++0x13 line.long 0x0 "LTDC_SSCR,LTDC synchronization size configuration register" hexmask.long.word 0x0 16.--31. 1. "HSW,horizontal synchronization width (in units of pixel clock period)" hexmask.long.word 0x0 0.--15. 1. "VSH,vertical synchronization height (in units of horizontal scan line)" line.long 0x4 "LTDC_BPCR,LTDC back porch configuration register" hexmask.long.word 0x4 16.--31. 1. "AHBP,accumulated horizontal back porch (in units of pixel clock period)" hexmask.long.word 0x4 0.--15. 1. "AVBP,accumulated Vertical back porch (in units of horizontal scan line)" line.long 0x8 "LTDC_AWCR,LTDC active width configuration register" hexmask.long.word 0x8 16.--31. 1. "AAW,accumulated active width (in units of pixel clock period)" hexmask.long.word 0x8 0.--15. 1. "AAH,accumulated active height (in units of horizontal scan line)" line.long 0xC "LTDC_TWCR,LTDC total width configuration register" hexmask.long.word 0xC 16.--31. 1. "TOTALW,total width (in units of pixel clock period)" hexmask.long.word 0xC 0.--15. 1. "TOTALH,total height (in units of horizontal scan line)" line.long 0x10 "LTDC_GCR,LTDC global control register" bitfld.long 0x10 31. "HSPOL,horizontal synchronization polarity" "0: horizontal synchronization polarity is active low.,1: horizontal synchronization polarity is active.." bitfld.long 0x10 30. "VSPOL,vertical synchronization polarity" "0: vertical synchronization is active low.,1: vertical synchronization is active high." newline bitfld.long 0x10 29. "DEPOL,blanking (no data/pixel) polarity" "0: blanking (no data/pixel) polarity is active low.,1: blanking (no data/pixel) polarity is active high." bitfld.long 0x10 28. "PCPOL,pixel clock polarity" "0: the pixel and sync data are generated at the..,1: the pixel and sync data are generated at the.." newline bitfld.long 0x10 25. "SFSWTR,single-frame mode: software trigger" "0: no action,1: triggers one frame" bitfld.long 0x10 24. "SFEN,single-frame mode: mode enable" "0: single-frame disabled: a trigger (on SFSWTR)..,1: single-frame enabled: a trigger (on SFSWTR).." newline bitfld.long 0x10 19. "CRCEN,CRC enable" "0: CRC disabled,1: CRC enabled" bitfld.long 0x10 16. "DEN,dither enable" "0: dither disabled,1: dither enabled" newline rbitfld.long 0x10 12.--14. "DRW,dither red width" "0,1,2,3,4,5,6,7" rbitfld.long 0x10 8.--10. "DGW,dither green width" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 4.--6. "DBW,dither blue width" "0,1,2,3,4,5,6,7" bitfld.long 0x10 1. "GAMEN,Gamma correction enable" "0: Gamma correction disabled (pixels bypass the..,1: Gamma correction enabled" newline bitfld.long 0x10 0. "LTDCEN,LTDC global enable" "0: LTDC disabled,1: LTDC enabled" rgroup.long 0x1C++0x7 line.long 0x0 "LTDC_GC1R,LTDC global configuration 1 register" bitfld.long 0x0 31. "BMA,blind mode ability" "0,1" bitfld.long 0x0 30. "CRMA,configuration reading mode ability" "0,1" newline bitfld.long 0x0 29. "STRA,status register ability" "0,1" bitfld.long 0x0 28. "DWP,dither width programmability" "0,1" newline bitfld.long 0x0 27. "SPP,sync polarity programmability" "0,1" bitfld.long 0x0 25. "TP,timing programmability" "0,1" newline bitfld.long 0x0 24. "LNIP,line-IRQ: line position programmability" "0,1" bitfld.long 0x0 23. "BBA,background blending ability" "0,1" newline bitfld.long 0x0 22. "BCP,background color programmability (unique color blended as background)" "0,1" bitfld.long 0x0 21. "SHRA,shadow registers ability" "0,1" newline bitfld.long 0x0 17.--19. "GCT,gamma correction technique implemented" "0: no gamma,1: gamma with 256 samples,2: gamma with 8 interpolated segments,?,?,?,?,?" bitfld.long 0x0 14.--15. "DT,dithering technique implemented" "0: no dithering,1: ordered 4x4 Bayer,?,3: pseudo-random LFSR" newline bitfld.long 0x0 12. "PRBA,precise blending ability" "0,1" hexmask.long.byte 0x0 8.--11. 1. "WRCH,width of red channel output" newline hexmask.long.byte 0x0 4.--7. 1. "WGCH,width of green channel output" hexmask.long.byte 0x0 0.--3. 1. "WBCH,width of blue channel output" line.long 0x4 "LTDC_GC2R,LTDC global configuration 2 register" bitfld.long 0x4 15. "BOA,blending order ability" "0: blending order fixed,1: blending order configurable" bitfld.long 0x4 13. "CRCA,CRC ability" "0: CRC no computation available,1: CRC computation available" newline bitfld.long 0x4 12. "SFA,single frame mode ability" "0: single frame not available,1: single frame available" bitfld.long 0x4 11. "SISA,second interrupt set ability" "0: second interrupt set not available,1: second interrupt set available" newline bitfld.long 0x4 10. "ROTA,rotation support ability" "0,1" bitfld.long 0x4 9. "AXIIDA,AXIID ability" "0,1" newline bitfld.long 0x4 8. "OCA,output conversion ability (RGB to YCbCr)" "0,1" bitfld.long 0x4 7. "EDCA,external display control ability" "0,1" newline bitfld.long 0x4 4.--6. "BW,bus width (log2 of number of bytes)" "?,?,2: 32-bit bus,3: 64-bit bus,4: 128-bit bus,?,?,?" bitfld.long 0x4 3. "DPA,secondary RGB output port ability" "0,1" newline bitfld.long 0x4 2. "DVA,dual-view ability" "0,1" bitfld.long 0x4 1. "STSA,slave timings synchronization ability" "0,1" newline bitfld.long 0x4 0. "BLA,background layer ability (pixels of background layer are read from memory)" "0,1" group.long 0x24++0x3 line.long 0x0 "LTDC_SRCR,LTDC shadow reload configuration register" bitfld.long 0x0 1. "VBR,vertical blanking reload request" "0: no effect,1: The shadow registers are reloaded during the.." bitfld.long 0x0 0. "IMR,immediate reload trigger" "0: no effect,1: The shadow registers are reloaded immediately." wgroup.long 0x28++0x3 line.long 0x0 "LTDC_GCCR,LTDC gamma correction configuration register" bitfld.long 0x0 18. "REN,write trigger to the red table" "0: no action done,1: COMP is written at ADDR in the red table." bitfld.long 0x0 17. "GEN,write trigger to the green table" "0: no action done,1: COMP is written at ADDR in the green table." newline bitfld.long 0x0 16. "BEN,write trigger to the blue table" "0: no action done,1: COMP is written at ADDR in the blue table." hexmask.long.byte 0x0 8.--15. 1. "COMP,color component to be written in either (or all) the R G B tables" newline hexmask.long.byte 0x0 0.--7. 1. "ADDR,address of the R G B table where the COMP component is written" group.long 0x2C++0x3 line.long 0x0 "LTDC_BCCR,LTDC background color configuration register" hexmask.long.byte 0x0 16.--23. 1. "BCRED,background color red value" hexmask.long.byte 0x0 8.--15. 1. "BCGREEN,background color green value" newline hexmask.long.byte 0x0 0.--7. 1. "BCBLUE,background color blue value" group.long 0x34++0x3 line.long 0x0 "LTDC_IER,LTDC interrupt enable register" bitfld.long 0x0 7. "CRCIE,CRC error interrupt enable" "0: CRC error disabled,1: CRC error interrupt enabled" bitfld.long 0x0 6. "FUIE,FIFO underrun interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" newline bitfld.long 0x0 3. "RRIE,Register reload interrupt enable" "0: register reload interrupt disabled,1: register reload interrupt enabled" bitfld.long 0x0 2. "TERRIE,Transfer Error interrupt enable" "0: transfer error interrupt disabled,1: transfer error interrupt enabled" newline bitfld.long 0x0 1. "FUWIE,FIFO underrun warning interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" bitfld.long 0x0 0. "LIE,Line interrupt enable" "0: line interrupt disabled,1: line interrupt enabled" rgroup.long 0x38++0x3 line.long 0x0 "LTDC_ISR,LTDC interrupt status register" bitfld.long 0x0 7. "CRCIF,CRC error interrupt flag" "0: no CRC error interrupt generated,1: CRC error interrupt generated when a bus error.." bitfld.long 0x0 6. "FUIF,FIFO underrun interrupt flag" "0: no FIFO underrun interrupt generated,1: FIFO underrun interrupt generated if one of the.." newline bitfld.long 0x0 3. "RRIF,Register reload interrupt flag" "0: no register reload interrupt generated,1: register reload interrupt generated when a.." bitfld.long 0x0 2. "TERRIF,Transfer error interrupt flag" "0: no transfer error interrupt generated,1: transfer error interrupt generated when a bus.." newline bitfld.long 0x0 1. "FUWIF,FIFO underrun warning interrupt flag" "0: no FIFO underrun warning interrupt generated,1: FIFO underrun warning interrupt generated if one.." bitfld.long 0x0 0. "LIF,Line interrupt flag" "0: no line interrupt generated,1: line interrupt generated when a programmed line.." wgroup.long 0x3C++0x3 line.long 0x0 "LTDC_ICR,LTDC interrupt clear register" bitfld.long 0x0 7. "CCRCIF,clears the CRC error interrupt flag" "0: no effect,1: clears the CRCIF flag in LTDC_ISR." bitfld.long 0x0 6. "CFUIF,clears the FIFO underrun interrupt flag" "0: no effect,1: clears the FUIF flag in LTDC_ISR." newline bitfld.long 0x0 3. "CRRIF,clears register reload interrupt flag" "0: no effect,1: clears the RRIF flag in LTDC_ISR." bitfld.long 0x0 2. "CTERRIF,clears the transfer error interrupt flag" "0: no effect,1: clears the TERRIF flag in LTDC_ISR." newline bitfld.long 0x0 1. "CFUWIF,clears the FIFO underrun warning interrupt flag" "0: no effect,1: clears the FUWIF flag in LTDC_ISR." bitfld.long 0x0 0. "CLIF,clears the line interrupt flag" "0: no effect,1: clears the LIF flag in LTDC_ISR." group.long 0x40++0x3 line.long 0x0 "LTDC_LIPCR,LTDC line interrupt position configuration register" hexmask.long.word 0x0 0.--15. 1. "LIPOS,line interrupt position" rgroup.long 0x44++0x7 line.long 0x0 "LTDC_CPSR,LTDC current position status register" hexmask.long.word 0x0 16.--31. 1. "CXPOS,current X position" hexmask.long.word 0x0 0.--15. 1. "CYPOS,current Y position" line.long 0x4 "LTDC_CDSR,LTDC current display status register" bitfld.long 0x4 3. "HSYNCS,horizontal synchronization display status" "0: active low,1: active high" bitfld.long 0x4 2. "VSYNCS,vertical synchronization display status" "0: active low,1: active high" newline bitfld.long 0x4 1. "HDES,horizontal data enable display status" "0: active low,1: active high" bitfld.long 0x4 0. "VDES,vertical data enable display status" "0: active low,1: active high" group.long 0x60++0x7 line.long 0x0 "LTDC_EDCR,LTDC external display control register" bitfld.long 0x0 27. "OCYCO,output conversion to YCbCr 422" "0: Cb is output first (Y0Cb then Y1Cr Y2Cb and so..,1: Cr is output first (Y0Cr then Y1Cb Y2Cr and so.." bitfld.long 0x0 26. "OCYSEL,output conversion to YCbCr 422" "0: use ITU-R BT.601 set (for typically SDTV..,1: use ITU-R BT.709 set (for typically HDTV.." newline bitfld.long 0x0 25. "OCYEN,output conversion to YCbCr 422 enable" "0: conversion disabled,1: conversion enabled" line.long 0x4 "LTDC_IER2,LTDC interrupt enable register 2" bitfld.long 0x4 7. "CRCIE,CRC error interrupt enable" "0: CRC error disabled,1: CRC error interrupt enabled" bitfld.long 0x4 6. "FUIE,FIFO underrun interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" newline bitfld.long 0x4 3. "RRIE,Register reload interrupt enable" "0: register reload interrupt disabled,1: register reload interrupt enabled" bitfld.long 0x4 2. "TERRIE,Transfer error interrupt enable" "0: transfer error interrupt disabled,1: transfer error interrupt enabled" newline bitfld.long 0x4 1. "FUWIE,FIFO underrun warning interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" bitfld.long 0x4 0. "LIE,Line interrupt enable" "0: line interrupt disabled,1: line interrupt enabled" rgroup.long 0x68++0x3 line.long 0x0 "LTDC_ISR2,LTDC interrupt status register 2" bitfld.long 0x0 7. "CRCIF,CRC Error interrupt flag" "0: no CRC error interrupt generated,1: CRC error interrupt generated when a bus error.." bitfld.long 0x0 6. "FUIF,FIFO underrun interrupt flag" "0: no FIFO underrun interrupt generated.,1: FIFO underrun interrupt generated if one of the.." newline bitfld.long 0x0 3. "RRIF,Register reload interrupt flag" "0: no register reload interrupt generated,1: register reload interrupt generated when a.." bitfld.long 0x0 2. "TERRIF,Transfer error interrupt flag" "0: no transfer error interrupt generated,1: transfer error interrupt generated when a bus.." newline bitfld.long 0x0 1. "FUWIF,FIFO underrun warning interrupt flag" "0: no FIFO underrun warning interrupt generated.,1: FIFO underrun warning interrupt generated if one.." bitfld.long 0x0 0. "LIF,Line interrupt flag" "0: no line interrupt generated,1: line interrupt generated when a programmed line.." wgroup.long 0x6C++0x3 line.long 0x0 "LTDC_ICR2,LTDC interrupt clear register 2" bitfld.long 0x0 7. "CCRCIF,clears the CRC error interrupt flag" "0: no effect,1: clears the CRCIF flag in LTDC_ISR2." bitfld.long 0x0 6. "CFUIF,clears the FIFO underrun interrupt flag" "0: no effect,1: clears the FUIF flag in LTDC_ISR2." newline bitfld.long 0x0 3. "CRRIF,clears register reload interrupt flag" "0: no effect,1: clears the RRIF flag in LTDC_ISR2." bitfld.long 0x0 2. "CTERRIF,clears the Transfer Error interrupt flag" "0: no effect,1: clears the TERRIF flag in LTDC_ISR2." newline bitfld.long 0x0 1. "CFUWIF,clears the FIFO underrun warning interrupt flag" "0: no effect,1: clears the FUWIF flag in LTDC_ISR2." bitfld.long 0x0 0. "CLIF,clears the Line interrupt flag" "0: no effect,1: clears the LIF flag in LTDC_ISR2." group.long 0x70++0x3 line.long 0x0 "LTDC_LIPCR2,LTDC line interrupt position configuration register 2" hexmask.long.word 0x0 0.--15. 1. "LIPOS,line interrupt position" group.long 0x78++0x3 line.long 0x0 "LTDC_ECRCR,LTDC expected CRC register" hexmask.long.word 0x0 0.--15. 1. "ECRC,expected CRC of frame" rgroup.long 0x7C++0x3 line.long 0x0 "LTDC_CCRCR,LTDC computed CRC register" hexmask.long.word 0x0 0.--15. 1. "CCRC,computed CRC of frame" group.long 0x90++0x3 line.long 0x0 "LTDC_FUTR,LTDC FIFO underrun threshold register" hexmask.long.word 0x0 0.--15. 1. "THRE,threshold to trigger a FIFO underrun interrupt (per FIFO word 64 bits)" rgroup.long 0x100++0x3 line.long 0x0 "LTDC_L1C0R,LTDC layerx configuration 0 register" bitfld.long 0x0 31. "ARGB8888,pixel format ability for argb8888" "0,1" bitfld.long 0x0 30. "ABGR8888,pixel format ability for abgr8888" "0,1" newline bitfld.long 0x0 29. "RGBA8888,pixel format ability for rgba8888" "0,1" bitfld.long 0x0 28. "BGRA888,pixel format ability for bgra8888" "0,1" newline bitfld.long 0x0 27. "RGB565,pixel format ability for rgb565" "0,1" bitfld.long 0x0 26. "BGR565,pixel format ability for bgr565" "0,1" newline bitfld.long 0x0 25. "RGB888,pixel format ability for rgb888" "0,1" bitfld.long 0x0 24. "FF,flexible pixel format ability" "0,1" newline bitfld.long 0x0 23. "F11PC,blending factor 1 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 22. "F1PC,blending factor 1 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 21. "F11C,blending factor 1 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 20. "F1C,blending factor 1 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 19. "F11P,blending factor 1 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 18. "F1P,blending factor 1 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 17. "F10,blending factor 1 ability for: 0.0" "0,1" bitfld.long 0x0 16. "F11,blending factor 1 ability for: 1.0" "0,1" newline bitfld.long 0x0 15. "F21PC,blending factor 2 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 14. "F2PC,blending factor 2 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 13. "F21C,blending factor 2 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 12. "F2C,blending factor 2 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 11. "F21P,blending factor 2 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 10. "F2P,blending factor 2 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 9. "F20,blending factor 2 ability for: 0.0" "0,1" bitfld.long 0x0 8. "F21,blending factor 2 ability for: 1.0" "0,1" newline bitfld.long 0x0 7. "CKRA,color key replace ability" "0,1" bitfld.long 0x0 6. "CLUTA,CLUT ability" "0,1" newline bitfld.long 0x0 5. "WINA,windowing ability" "0,1" bitfld.long 0x0 4. "DCP,default color programmability" "0,1" newline bitfld.long 0x0 3. "APA,alpha plane ability" "0,1" bitfld.long 0x0 2. "CFBPA,color frame buffer pitch ability" "0,1" newline bitfld.long 0x0 1. "CFBDA,color frame buffer duplication ability" "0,1" bitfld.long 0x0 0. "CKTA,color key transparency ability" "0,1" group.long 0x104++0x4B line.long 0x0 "LTDC_L1C1R,LTDC layerx configuration 1 register" bitfld.long 0x0 31. "SCA,scaling ability for that layer" "0: scaling not available,1: scaling available" bitfld.long 0x0 2. "YFPA,YCbCr 420 full-planar ability for that layer" "0: full planar not available,1: full planar available" newline bitfld.long 0x0 1. "YSPA,YCbCr 420 semi-planar ability for that layer" "0: semi-planar not available,1: semi-planar available" bitfld.long 0x0 0. "YIA,YCbCr 422 interleaved ability for that layer" "0: interleaved not available,1: interleaved available" line.long 0x4 "LTDC_L1RCR,LTDC layerx reload control register" bitfld.long 0x4 2. "GRMSK,shadow reload control global (centralized) reload masked" "0: global reload active for this layer (control..,1: global reload masked for this layer (control.." bitfld.long 0x4 1. "VBR,vertical blanking reload request" "0: no effect,1: The shadow registers are reloaded during the.." newline bitfld.long 0x4 0. "IMR,immediate reload trigger" "0: no effect,1: The shadow registers are reloaded immediately." line.long 0x8 "LTDC_L1CR,LTDC layerx control register" bitfld.long 0x8 9. "DCBEN,default color blending enable" "0: blending disabled,1: blending enabled" bitfld.long 0x8 8. "HMEN,horizontal mirroring enable" "0: mirror disabled,1: mirror enabled (if so the color frame buffer.." newline bitfld.long 0x8 4. "CLUTEN,color look-up table enable" "0: color look-up table disabled,1: color look-up table enabled" bitfld.long 0x8 1. "CKEN,color keying enable" "0: color keying disabled,1: color keying enabled: if RGB matches then the.." newline bitfld.long 0x8 0. "LEN,layer enable" "0: layer disabled,1: layer enabled" line.long 0xC "LTDC_L1WHPCR,LTDC layerx window horizontal position configuration register" hexmask.long.word 0xC 16.--31. 1. "WHSPPOS,window horizontal stop position" hexmask.long.word 0xC 0.--15. 1. "WHSTPOS,window horizontal start position" line.long 0x10 "LTDC_L1WVPCR,LTDC layerx window vertical position configuration register" hexmask.long.word 0x10 16.--31. 1. "WVSPPOS,window vertical stop position" hexmask.long.word 0x10 0.--15. 1. "WVSTPOS,window vertical start position" line.long 0x14 "LTDC_L1CKCR,LTDC layerx color keying configuration register" hexmask.long.byte 0x14 16.--23. 1. "CKRED,color key red value" hexmask.long.byte 0x14 8.--15. 1. "CKGREEN,color key green value" newline hexmask.long.byte 0x14 0.--7. 1. "CKBLUE,color key blue value" line.long 0x18 "LTDC_L1PFCR,LTDC layerx pixel format configuration register" bitfld.long 0x18 0.--2. "PF,pixel format" "0: ARGB8888 (32 bpp),1: ABGR888 (32 bpp),2: RGBA888 (32 bpp),3: BGRA8888 (32 bpp),4: RGB565 (16 bpp A = 255),5: BGR565 (16 bpp A = 255),6: RGB888 (24 bpp packed A = 255),7: Flexible pixel format selected (see Section.." line.long 0x1C "LTDC_L1CACR,LTDC layerx constant alpha configuration register" hexmask.long.byte 0x1C 0.--7. 1. "CONSTA,constant alpha" line.long 0x20 "LTDC_L1DCCR,LTDC layerx default color configuration register" hexmask.long.byte 0x20 24.--31. 1. "DCALPHA,default color alpha" hexmask.long.byte 0x20 16.--23. 1. "DCRED,default color red" newline hexmask.long.byte 0x20 8.--15. 1. "DCGREEN,default color green" hexmask.long.byte 0x20 0.--7. 1. "DCBLUE,default color blue" line.long 0x24 "LTDC_L1BFCR,LTDC layerx blending factors configuration register" bitfld.long 0x24 16. "BOR,blending order" "0: layer set in background,1: layer set in foreground" bitfld.long 0x24 8.--10. "BF1,blending factor 1" "?,?,?,?,4: constant alpha,?,6: pixel alpha x constant alpha,?" newline bitfld.long 0x24 0.--2. "BF2,blending factor 2" "?,?,?,?,?,5: 1 - constant alpha,?,7: 1 - (pixel alpha x constant alpha)" line.long 0x28 "LTDC_L1BLCR,LTDC layerx burst length configuration register" hexmask.long.byte 0x28 0.--7. 1. "BL,burst length" line.long 0x2C "LTDC_L1PCR,LTDC layerx planar configuration register" bitfld.long 0x2C 9. "YREN,Y rescale enable for the color dynamic range" "0: rescaling disabled (input component thus assumed..,1: rescaling enabled (input component thus assumed.." bitfld.long 0x2C 8. "OF,Odd pixel first" "0: odd pixel disabled (thus even pixel on byte 0),1: odd pixel enabled (thus odd pixel on byte 0)" newline bitfld.long 0x2C 7. "CBF,Cb component first" "0: Cb disabled (thus Cr component is on byte 0 and 1),1: Cb enabled (thus Cb component is on byte 0 and 1)" bitfld.long 0x2C 6. "YF,Y component first" "0: Y component disabled (thus Cr or Cb component is..,1: Y component enabled (thus Y component is on byte.." newline bitfld.long 0x2C 4.--5. "YCM,YCbCr conversion mode" "0: interleaved 422 (Cb and Cr component are..,1: semi-Planar 420: (Cb and Cr component are..,2: full-Planar 420: (Cb and Cr component are..,?" bitfld.long 0x2C 3. "YCEN,YCbCr-to-RGB conversion enable" "0: conversion disabled,1: YCbCr conversion enabled using the YCM setting.." line.long 0x30 "LTDC_L1CFBAR,LTDC layerx color frame buffer address register" hexmask.long 0x30 0.--31. 1. "CFBADD,color frame buffer start address" line.long 0x34 "LTDC_L1CFBLR,LTDC layerx color frame buffer length register" hexmask.long.word 0x34 16.--31. 1. "CFBP,color frame buffer pitch in bytes" hexmask.long.word 0x34 0.--15. 1. "CFBLL,color frame buffer line length" line.long 0x38 "LTDC_L1CFBLNR,LTDC layerx color frame buffer line number register" hexmask.long.word 0x38 0.--15. 1. "CFBLNBR,frame buffer line number" line.long 0x3C "LTDC_L1AFBA0R,LTDC layer1 auxiliary frame buffer address 0 register" hexmask.long 0x3C 0.--31. 1. "AFBADD0,frame buffer start address" line.long 0x40 "LTDC_L1AFBA1R,LTDC layer1 auxiliary frame buffer address 1 register" hexmask.long 0x40 0.--31. 1. "AFBADD1,auxiliary frame buffer start address" line.long 0x44 "LTDC_L1AFBLR,LTDC layer1 auxiliary frame buffer length register" hexmask.long.word 0x44 16.--31. 1. "AFBP,auxiliary frame buffer pitch in bytes" hexmask.long.word 0x44 0.--15. 1. "AFBLL,auxiliary frame buffer line length" line.long 0x48 "LTDC_L1AFBLNR,LTDC layer1 auxiliary frame buffer line number register" hexmask.long.word 0x48 0.--15. 1. "AFBLNBR,auxiliary frame buffer line number" wgroup.long 0x150++0x3 line.long 0x0 "LTDC_L1CLUTWR,LTDC layerx CLUT write register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address" hexmask.long.byte 0x0 16.--23. 1. "RED,red value" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value" group.long 0x16C++0xF line.long 0x0 "LTDC_L1CYR0R,LTDC layerx conversion YCbCr RGB 0 register" hexmask.long.word 0x0 16.--25. 1. "CB2B,Cb-to-Blue coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x0 0.--9. 1. "CR2R,Cr-to-Red coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x4 "LTDC_L1CYR1R,LTDC layerx conversion YCbCr RGB 1 register" hexmask.long.word 0x4 16.--25. 1. "CB2G,Cb-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x4 0.--9. 1. "CR2G,Cr-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x8 "LTDC_L1FPF0R,LTDC layerx flexible pixel format 0 register" hexmask.long.byte 0x8 14.--17. 1. "RLEN,Width of the Red component (in bits)" hexmask.long.byte 0x8 9.--13. 1. "RPOS,Location of the Red component inside the pixel memory word (in bits)" newline hexmask.long.byte 0x8 5.--8. 1. "ALEN,Width of the Alpha component (in bits)" hexmask.long.byte 0x8 0.--4. 1. "APOS,Location of the Alpha component inside the pixel memory word (in bits)" line.long 0xC "LTDC_L1FPF1R,LTDC layerx flexible pixel format 1 register" bitfld.long 0xC 18.--20. "PSIZE,Pixel size (in bytes)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 14.--17. 1. "BLEN,Width of the Blue component (in bits)" newline hexmask.long.byte 0xC 9.--13. 1. "BPOS,Location of the Blue component inside the pixel memory word (in bits)" hexmask.long.byte 0xC 5.--8. 1. "GLEN,Width of the Green component (in bits)" newline hexmask.long.byte 0xC 0.--4. 1. "GPOS,Location of the Green component inside the pixel memory word (in bits)" rgroup.long 0x200++0x3 line.long 0x0 "LTDC_L2C0R,LTDC layerx configuration 0 register" bitfld.long 0x0 31. "ARGB8888,pixel format ability for argb8888" "0,1" bitfld.long 0x0 30. "ABGR8888,pixel format ability for abgr8888" "0,1" newline bitfld.long 0x0 29. "RGBA8888,pixel format ability for rgba8888" "0,1" bitfld.long 0x0 28. "BGRA888,pixel format ability for bgra8888" "0,1" newline bitfld.long 0x0 27. "RGB565,pixel format ability for rgb565" "0,1" bitfld.long 0x0 26. "BGR565,pixel format ability for bgr565" "0,1" newline bitfld.long 0x0 25. "RGB888,pixel format ability for rgb888" "0,1" bitfld.long 0x0 24. "FF,flexible pixel format ability" "0,1" newline bitfld.long 0x0 23. "F11PC,blending factor 1 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 22. "F1PC,blending factor 1 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 21. "F11C,blending factor 1 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 20. "F1C,blending factor 1 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 19. "F11P,blending factor 1 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 18. "F1P,blending factor 1 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 17. "F10,blending factor 1 ability for: 0.0" "0,1" bitfld.long 0x0 16. "F11,blending factor 1 ability for: 1.0" "0,1" newline bitfld.long 0x0 15. "F21PC,blending factor 2 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 14. "F2PC,blending factor 2 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 13. "F21C,blending factor 2 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 12. "F2C,blending factor 2 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 11. "F21P,blending factor 2 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 10. "F2P,blending factor 2 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 9. "F20,blending factor 2 ability for: 0.0" "0,1" bitfld.long 0x0 8. "F21,blending factor 2 ability for: 1.0" "0,1" newline bitfld.long 0x0 7. "CKRA,color key replace ability" "0,1" bitfld.long 0x0 6. "CLUTA,CLUT ability" "0,1" newline bitfld.long 0x0 5. "WINA,windowing ability" "0,1" bitfld.long 0x0 4. "DCP,default color programmability" "0,1" newline bitfld.long 0x0 3. "APA,alpha plane ability" "0,1" bitfld.long 0x0 2. "CFBPA,color frame buffer pitch ability" "0,1" newline bitfld.long 0x0 1. "CFBDA,color frame buffer duplication ability" "0,1" bitfld.long 0x0 0. "CKTA,color key transparency ability" "0,1" group.long 0x204++0x3B line.long 0x0 "LTDC_L2C1R,LTDC layerx configuration 1 register" bitfld.long 0x0 31. "SCA,scaling ability for that layer" "0: scaling not available,1: scaling available" bitfld.long 0x0 2. "YFPA,YCbCr 420 full-planar ability for that layer" "0: full planar not available,1: full planar available" newline bitfld.long 0x0 1. "YSPA,YCbCr 420 semi-planar ability for that layer" "0: semi-planar not available,1: semi-planar available" bitfld.long 0x0 0. "YIA,YCbCr 422 interleaved ability for that layer" "0: interleaved not available,1: interleaved available" line.long 0x4 "LTDC_L2RCR,LTDC layerx reload control register" bitfld.long 0x4 2. "GRMSK,shadow reload control global (centralized) reload masked" "0: global reload active for this layer (control..,1: global reload masked for this layer (control.." bitfld.long 0x4 1. "VBR,vertical blanking reload request" "0: no effect,1: The shadow registers are reloaded during the.." newline bitfld.long 0x4 0. "IMR,immediate reload trigger" "0: no effect,1: The shadow registers are reloaded immediately." line.long 0x8 "LTDC_L2CR,LTDC layerx control register" bitfld.long 0x8 9. "DCBEN,default color blending enable" "0: blending disabled,1: blending enabled" bitfld.long 0x8 8. "HMEN,horizontal mirroring enable" "0: mirror disabled,1: mirror enabled (if so the color frame buffer.." newline bitfld.long 0x8 4. "CLUTEN,color look-up table enable" "0: color look-up table disabled,1: color look-up table enabled" bitfld.long 0x8 1. "CKEN,color keying enable" "0: color keying disabled,1: color keying enabled: if RGB matches then the.." newline bitfld.long 0x8 0. "LEN,layer enable" "0: layer disabled,1: layer enabled" line.long 0xC "LTDC_L2WHPCR,LTDC layerx window horizontal position configuration register" hexmask.long.word 0xC 16.--31. 1. "WHSPPOS,window horizontal stop position" hexmask.long.word 0xC 0.--15. 1. "WHSTPOS,window horizontal start position" line.long 0x10 "LTDC_L2WVPCR,LTDC layerx window vertical position configuration register" hexmask.long.word 0x10 16.--31. 1. "WVSPPOS,window vertical stop position" hexmask.long.word 0x10 0.--15. 1. "WVSTPOS,window vertical start position" line.long 0x14 "LTDC_L2CKCR,LTDC layerx color keying configuration register" hexmask.long.byte 0x14 16.--23. 1. "CKRED,color key red value" hexmask.long.byte 0x14 8.--15. 1. "CKGREEN,color key green value" newline hexmask.long.byte 0x14 0.--7. 1. "CKBLUE,color key blue value" line.long 0x18 "LTDC_L2PFCR,LTDC layerx pixel format configuration register" bitfld.long 0x18 0.--2. "PF,pixel format" "0: ARGB8888 (32 bpp),1: ABGR888 (32 bpp),2: RGBA888 (32 bpp),3: BGRA8888 (32 bpp),4: RGB565 (16 bpp A = 255),5: BGR565 (16 bpp A = 255),6: RGB888 (24 bpp packed A = 255),7: Flexible pixel format selected (see Section.." line.long 0x1C "LTDC_L2CACR,LTDC layerx constant alpha configuration register" hexmask.long.byte 0x1C 0.--7. 1. "CONSTA,constant alpha" line.long 0x20 "LTDC_L2DCCR,LTDC layerx default color configuration register" hexmask.long.byte 0x20 24.--31. 1. "DCALPHA,default color alpha" hexmask.long.byte 0x20 16.--23. 1. "DCRED,default color red" newline hexmask.long.byte 0x20 8.--15. 1. "DCGREEN,default color green" hexmask.long.byte 0x20 0.--7. 1. "DCBLUE,default color blue" line.long 0x24 "LTDC_L2BFCR,LTDC layerx blending factors configuration register" bitfld.long 0x24 16. "BOR,blending order" "0: layer set in background,1: layer set in foreground" bitfld.long 0x24 8.--10. "BF1,blending factor 1" "?,?,?,?,4: constant alpha,?,6: pixel alpha x constant alpha,?" newline bitfld.long 0x24 0.--2. "BF2,blending factor 2" "?,?,?,?,?,5: 1 - constant alpha,?,7: 1 - (pixel alpha x constant alpha)" line.long 0x28 "LTDC_L2BLCR,LTDC layerx burst length configuration register" hexmask.long.byte 0x28 0.--7. 1. "BL,burst length" line.long 0x2C "LTDC_L2PCR,LTDC layerx planar configuration register" bitfld.long 0x2C 9. "YREN,Y rescale enable for the color dynamic range" "0: rescaling disabled (input component thus assumed..,1: rescaling enabled (input component thus assumed.." bitfld.long 0x2C 8. "OF,Odd pixel first" "0: odd pixel disabled (thus even pixel on byte 0),1: odd pixel enabled (thus odd pixel on byte 0)" newline bitfld.long 0x2C 7. "CBF,Cb component first" "0: Cb disabled (thus Cr component is on byte 0 and 1),1: Cb enabled (thus Cb component is on byte 0 and 1)" bitfld.long 0x2C 6. "YF,Y component first" "0: Y component disabled (thus Cr or Cb component is..,1: Y component enabled (thus Y component is on byte.." newline bitfld.long 0x2C 4.--5. "YCM,YCbCr conversion mode" "0: interleaved 422 (Cb and Cr component are..,1: semi-Planar 420: (Cb and Cr component are..,2: full-Planar 420: (Cb and Cr component are..,?" bitfld.long 0x2C 3. "YCEN,YCbCr-to-RGB conversion enable" "0: conversion disabled,1: YCbCr conversion enabled using the YCM setting.." line.long 0x30 "LTDC_L2CFBAR,LTDC layerx color frame buffer address register" hexmask.long 0x30 0.--31. 1. "CFBADD,color frame buffer start address" line.long 0x34 "LTDC_L2CFBLR,LTDC layerx color frame buffer length register" hexmask.long.word 0x34 16.--31. 1. "CFBP,color frame buffer pitch in bytes" hexmask.long.word 0x34 0.--15. 1. "CFBLL,color frame buffer line length" line.long 0x38 "LTDC_L2CFBLNR,LTDC layerx color frame buffer line number register" hexmask.long.word 0x38 0.--15. 1. "CFBLNBR,frame buffer line number" wgroup.long 0x250++0x3 line.long 0x0 "LTDC_L2CLUTWR,LTDC layerx CLUT write register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address" hexmask.long.byte 0x0 16.--23. 1. "RED,red value" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value" group.long 0x26C++0xF line.long 0x0 "LTDC_L2CYR0R,LTDC layerx conversion YCbCr RGB 0 register" hexmask.long.word 0x0 16.--25. 1. "CB2B,Cb-to-Blue coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x0 0.--9. 1. "CR2R,Cr-to-Red coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x4 "LTDC_L2CYR1R,LTDC layerx conversion YCbCr RGB 1 register" hexmask.long.word 0x4 16.--25. 1. "CB2G,Cb-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x4 0.--9. 1. "CR2G,Cr-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x8 "LTDC_L2FPF0R,LTDC layerx flexible pixel format 0 register" hexmask.long.byte 0x8 14.--17. 1. "RLEN,Width of the Red component (in bits)" hexmask.long.byte 0x8 9.--13. 1. "RPOS,Location of the Red component inside the pixel memory word (in bits)" newline hexmask.long.byte 0x8 5.--8. 1. "ALEN,Width of the Alpha component (in bits)" hexmask.long.byte 0x8 0.--4. 1. "APOS,Location of the Alpha component inside the pixel memory word (in bits)" line.long 0xC "LTDC_L2FPF1R,LTDC layerx flexible pixel format 1 register" bitfld.long 0xC 18.--20. "PSIZE,Pixel size (in bytes)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 14.--17. 1. "BLEN,Width of the Blue component (in bits)" newline hexmask.long.byte 0xC 9.--13. 1. "BPOS,Location of the Blue component inside the pixel memory word (in bits)" hexmask.long.byte 0xC 5.--8. 1. "GLEN,Width of the Green component (in bits)" newline hexmask.long.byte 0xC 0.--4. 1. "GPOS,Location of the Green component inside the pixel memory word (in bits)" tree.end tree "LTDC_S" base ad:0x58001000 group.long 0x8++0x13 line.long 0x0 "LTDC_SSCR,LTDC synchronization size configuration register" hexmask.long.word 0x0 16.--31. 1. "HSW,horizontal synchronization width (in units of pixel clock period)" hexmask.long.word 0x0 0.--15. 1. "VSH,vertical synchronization height (in units of horizontal scan line)" line.long 0x4 "LTDC_BPCR,LTDC back porch configuration register" hexmask.long.word 0x4 16.--31. 1. "AHBP,accumulated horizontal back porch (in units of pixel clock period)" hexmask.long.word 0x4 0.--15. 1. "AVBP,accumulated Vertical back porch (in units of horizontal scan line)" line.long 0x8 "LTDC_AWCR,LTDC active width configuration register" hexmask.long.word 0x8 16.--31. 1. "AAW,accumulated active width (in units of pixel clock period)" hexmask.long.word 0x8 0.--15. 1. "AAH,accumulated active height (in units of horizontal scan line)" line.long 0xC "LTDC_TWCR,LTDC total width configuration register" hexmask.long.word 0xC 16.--31. 1. "TOTALW,total width (in units of pixel clock period)" hexmask.long.word 0xC 0.--15. 1. "TOTALH,total height (in units of horizontal scan line)" line.long 0x10 "LTDC_GCR,LTDC global control register" bitfld.long 0x10 31. "HSPOL,horizontal synchronization polarity" "0: horizontal synchronization polarity is active low.,1: horizontal synchronization polarity is active.." bitfld.long 0x10 30. "VSPOL,vertical synchronization polarity" "0: vertical synchronization is active low.,1: vertical synchronization is active high." newline bitfld.long 0x10 29. "DEPOL,blanking (no data/pixel) polarity" "0: blanking (no data/pixel) polarity is active low.,1: blanking (no data/pixel) polarity is active high." bitfld.long 0x10 28. "PCPOL,pixel clock polarity" "0: the pixel and sync data are generated at the..,1: the pixel and sync data are generated at the.." newline bitfld.long 0x10 25. "SFSWTR,single-frame mode: software trigger" "0: no action,1: triggers one frame" bitfld.long 0x10 24. "SFEN,single-frame mode: mode enable" "0: single-frame disabled: a trigger (on SFSWTR)..,1: single-frame enabled: a trigger (on SFSWTR).." newline bitfld.long 0x10 19. "CRCEN,CRC enable" "0: CRC disabled,1: CRC enabled" bitfld.long 0x10 16. "DEN,dither enable" "0: dither disabled,1: dither enabled" newline rbitfld.long 0x10 12.--14. "DRW,dither red width" "0,1,2,3,4,5,6,7" rbitfld.long 0x10 8.--10. "DGW,dither green width" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 4.--6. "DBW,dither blue width" "0,1,2,3,4,5,6,7" bitfld.long 0x10 1. "GAMEN,Gamma correction enable" "0: Gamma correction disabled (pixels bypass the..,1: Gamma correction enabled" newline bitfld.long 0x10 0. "LTDCEN,LTDC global enable" "0: LTDC disabled,1: LTDC enabled" rgroup.long 0x1C++0x7 line.long 0x0 "LTDC_GC1R,LTDC global configuration 1 register" bitfld.long 0x0 31. "BMA,blind mode ability" "0,1" bitfld.long 0x0 30. "CRMA,configuration reading mode ability" "0,1" newline bitfld.long 0x0 29. "STRA,status register ability" "0,1" bitfld.long 0x0 28. "DWP,dither width programmability" "0,1" newline bitfld.long 0x0 27. "SPP,sync polarity programmability" "0,1" bitfld.long 0x0 25. "TP,timing programmability" "0,1" newline bitfld.long 0x0 24. "LNIP,line-IRQ: line position programmability" "0,1" bitfld.long 0x0 23. "BBA,background blending ability" "0,1" newline bitfld.long 0x0 22. "BCP,background color programmability (unique color blended as background)" "0,1" bitfld.long 0x0 21. "SHRA,shadow registers ability" "0,1" newline bitfld.long 0x0 17.--19. "GCT,gamma correction technique implemented" "0: no gamma,1: gamma with 256 samples,2: gamma with 8 interpolated segments,?,?,?,?,?" bitfld.long 0x0 14.--15. "DT,dithering technique implemented" "0: no dithering,1: ordered 4x4 Bayer,?,3: pseudo-random LFSR" newline bitfld.long 0x0 12. "PRBA,precise blending ability" "0,1" hexmask.long.byte 0x0 8.--11. 1. "WRCH,width of red channel output" newline hexmask.long.byte 0x0 4.--7. 1. "WGCH,width of green channel output" hexmask.long.byte 0x0 0.--3. 1. "WBCH,width of blue channel output" line.long 0x4 "LTDC_GC2R,LTDC global configuration 2 register" bitfld.long 0x4 15. "BOA,blending order ability" "0: blending order fixed,1: blending order configurable" bitfld.long 0x4 13. "CRCA,CRC ability" "0: CRC no computation available,1: CRC computation available" newline bitfld.long 0x4 12. "SFA,single frame mode ability" "0: single frame not available,1: single frame available" bitfld.long 0x4 11. "SISA,second interrupt set ability" "0: second interrupt set not available,1: second interrupt set available" newline bitfld.long 0x4 10. "ROTA,rotation support ability" "0,1" bitfld.long 0x4 9. "AXIIDA,AXIID ability" "0,1" newline bitfld.long 0x4 8. "OCA,output conversion ability (RGB to YCbCr)" "0,1" bitfld.long 0x4 7. "EDCA,external display control ability" "0,1" newline bitfld.long 0x4 4.--6. "BW,bus width (log2 of number of bytes)" "?,?,2: 32-bit bus,3: 64-bit bus,4: 128-bit bus,?,?,?" bitfld.long 0x4 3. "DPA,secondary RGB output port ability" "0,1" newline bitfld.long 0x4 2. "DVA,dual-view ability" "0,1" bitfld.long 0x4 1. "STSA,slave timings synchronization ability" "0,1" newline bitfld.long 0x4 0. "BLA,background layer ability (pixels of background layer are read from memory)" "0,1" group.long 0x24++0x3 line.long 0x0 "LTDC_SRCR,LTDC shadow reload configuration register" bitfld.long 0x0 1. "VBR,vertical blanking reload request" "0: no effect,1: The shadow registers are reloaded during the.." bitfld.long 0x0 0. "IMR,immediate reload trigger" "0: no effect,1: The shadow registers are reloaded immediately." wgroup.long 0x28++0x3 line.long 0x0 "LTDC_GCCR,LTDC gamma correction configuration register" bitfld.long 0x0 18. "REN,write trigger to the red table" "0: no action done,1: COMP is written at ADDR in the red table." bitfld.long 0x0 17. "GEN,write trigger to the green table" "0: no action done,1: COMP is written at ADDR in the green table." newline bitfld.long 0x0 16. "BEN,write trigger to the blue table" "0: no action done,1: COMP is written at ADDR in the blue table." hexmask.long.byte 0x0 8.--15. 1. "COMP,color component to be written in either (or all) the R G B tables" newline hexmask.long.byte 0x0 0.--7. 1. "ADDR,address of the R G B table where the COMP component is written" group.long 0x2C++0x3 line.long 0x0 "LTDC_BCCR,LTDC background color configuration register" hexmask.long.byte 0x0 16.--23. 1. "BCRED,background color red value" hexmask.long.byte 0x0 8.--15. 1. "BCGREEN,background color green value" newline hexmask.long.byte 0x0 0.--7. 1. "BCBLUE,background color blue value" group.long 0x34++0x3 line.long 0x0 "LTDC_IER,LTDC interrupt enable register" bitfld.long 0x0 7. "CRCIE,CRC error interrupt enable" "0: CRC error disabled,1: CRC error interrupt enabled" bitfld.long 0x0 6. "FUIE,FIFO underrun interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" newline bitfld.long 0x0 3. "RRIE,Register reload interrupt enable" "0: register reload interrupt disabled,1: register reload interrupt enabled" bitfld.long 0x0 2. "TERRIE,Transfer Error interrupt enable" "0: transfer error interrupt disabled,1: transfer error interrupt enabled" newline bitfld.long 0x0 1. "FUWIE,FIFO underrun warning interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" bitfld.long 0x0 0. "LIE,Line interrupt enable" "0: line interrupt disabled,1: line interrupt enabled" rgroup.long 0x38++0x3 line.long 0x0 "LTDC_ISR,LTDC interrupt status register" bitfld.long 0x0 7. "CRCIF,CRC error interrupt flag" "0: no CRC error interrupt generated,1: CRC error interrupt generated when a bus error.." bitfld.long 0x0 6. "FUIF,FIFO underrun interrupt flag" "0: no FIFO underrun interrupt generated,1: FIFO underrun interrupt generated if one of the.." newline bitfld.long 0x0 3. "RRIF,Register reload interrupt flag" "0: no register reload interrupt generated,1: register reload interrupt generated when a.." bitfld.long 0x0 2. "TERRIF,Transfer error interrupt flag" "0: no transfer error interrupt generated,1: transfer error interrupt generated when a bus.." newline bitfld.long 0x0 1. "FUWIF,FIFO underrun warning interrupt flag" "0: no FIFO underrun warning interrupt generated,1: FIFO underrun warning interrupt generated if one.." bitfld.long 0x0 0. "LIF,Line interrupt flag" "0: no line interrupt generated,1: line interrupt generated when a programmed line.." wgroup.long 0x3C++0x3 line.long 0x0 "LTDC_ICR,LTDC interrupt clear register" bitfld.long 0x0 7. "CCRCIF,clears the CRC error interrupt flag" "0: no effect,1: clears the CRCIF flag in LTDC_ISR." bitfld.long 0x0 6. "CFUIF,clears the FIFO underrun interrupt flag" "0: no effect,1: clears the FUIF flag in LTDC_ISR." newline bitfld.long 0x0 3. "CRRIF,clears register reload interrupt flag" "0: no effect,1: clears the RRIF flag in LTDC_ISR." bitfld.long 0x0 2. "CTERRIF,clears the transfer error interrupt flag" "0: no effect,1: clears the TERRIF flag in LTDC_ISR." newline bitfld.long 0x0 1. "CFUWIF,clears the FIFO underrun warning interrupt flag" "0: no effect,1: clears the FUWIF flag in LTDC_ISR." bitfld.long 0x0 0. "CLIF,clears the line interrupt flag" "0: no effect,1: clears the LIF flag in LTDC_ISR." group.long 0x40++0x3 line.long 0x0 "LTDC_LIPCR,LTDC line interrupt position configuration register" hexmask.long.word 0x0 0.--15. 1. "LIPOS,line interrupt position" rgroup.long 0x44++0x7 line.long 0x0 "LTDC_CPSR,LTDC current position status register" hexmask.long.word 0x0 16.--31. 1. "CXPOS,current X position" hexmask.long.word 0x0 0.--15. 1. "CYPOS,current Y position" line.long 0x4 "LTDC_CDSR,LTDC current display status register" bitfld.long 0x4 3. "HSYNCS,horizontal synchronization display status" "0: active low,1: active high" bitfld.long 0x4 2. "VSYNCS,vertical synchronization display status" "0: active low,1: active high" newline bitfld.long 0x4 1. "HDES,horizontal data enable display status" "0: active low,1: active high" bitfld.long 0x4 0. "VDES,vertical data enable display status" "0: active low,1: active high" group.long 0x60++0x7 line.long 0x0 "LTDC_EDCR,LTDC external display control register" bitfld.long 0x0 27. "OCYCO,output conversion to YCbCr 422" "0: Cb is output first (Y0Cb then Y1Cr Y2Cb and so..,1: Cr is output first (Y0Cr then Y1Cb Y2Cr and so.." bitfld.long 0x0 26. "OCYSEL,output conversion to YCbCr 422" "0: use ITU-R BT.601 set (for typically SDTV..,1: use ITU-R BT.709 set (for typically HDTV.." newline bitfld.long 0x0 25. "OCYEN,output conversion to YCbCr 422 enable" "0: conversion disabled,1: conversion enabled" line.long 0x4 "LTDC_IER2,LTDC interrupt enable register 2" bitfld.long 0x4 7. "CRCIE,CRC error interrupt enable" "0: CRC error disabled,1: CRC error interrupt enabled" bitfld.long 0x4 6. "FUIE,FIFO underrun interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" newline bitfld.long 0x4 3. "RRIE,Register reload interrupt enable" "0: register reload interrupt disabled,1: register reload interrupt enabled" bitfld.long 0x4 2. "TERRIE,Transfer error interrupt enable" "0: transfer error interrupt disabled,1: transfer error interrupt enabled" newline bitfld.long 0x4 1. "FUWIE,FIFO underrun warning interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" bitfld.long 0x4 0. "LIE,Line interrupt enable" "0: line interrupt disabled,1: line interrupt enabled" rgroup.long 0x68++0x3 line.long 0x0 "LTDC_ISR2,LTDC interrupt status register 2" bitfld.long 0x0 7. "CRCIF,CRC Error interrupt flag" "0: no CRC error interrupt generated,1: CRC error interrupt generated when a bus error.." bitfld.long 0x0 6. "FUIF,FIFO underrun interrupt flag" "0: no FIFO underrun interrupt generated.,1: FIFO underrun interrupt generated if one of the.." newline bitfld.long 0x0 3. "RRIF,Register reload interrupt flag" "0: no register reload interrupt generated,1: register reload interrupt generated when a.." bitfld.long 0x0 2. "TERRIF,Transfer error interrupt flag" "0: no transfer error interrupt generated,1: transfer error interrupt generated when a bus.." newline bitfld.long 0x0 1. "FUWIF,FIFO underrun warning interrupt flag" "0: no FIFO underrun warning interrupt generated.,1: FIFO underrun warning interrupt generated if one.." bitfld.long 0x0 0. "LIF,Line interrupt flag" "0: no line interrupt generated,1: line interrupt generated when a programmed line.." wgroup.long 0x6C++0x3 line.long 0x0 "LTDC_ICR2,LTDC interrupt clear register 2" bitfld.long 0x0 7. "CCRCIF,clears the CRC error interrupt flag" "0: no effect,1: clears the CRCIF flag in LTDC_ISR2." bitfld.long 0x0 6. "CFUIF,clears the FIFO underrun interrupt flag" "0: no effect,1: clears the FUIF flag in LTDC_ISR2." newline bitfld.long 0x0 3. "CRRIF,clears register reload interrupt flag" "0: no effect,1: clears the RRIF flag in LTDC_ISR2." bitfld.long 0x0 2. "CTERRIF,clears the Transfer Error interrupt flag" "0: no effect,1: clears the TERRIF flag in LTDC_ISR2." newline bitfld.long 0x0 1. "CFUWIF,clears the FIFO underrun warning interrupt flag" "0: no effect,1: clears the FUWIF flag in LTDC_ISR2." bitfld.long 0x0 0. "CLIF,clears the Line interrupt flag" "0: no effect,1: clears the LIF flag in LTDC_ISR2." group.long 0x70++0x3 line.long 0x0 "LTDC_LIPCR2,LTDC line interrupt position configuration register 2" hexmask.long.word 0x0 0.--15. 1. "LIPOS,line interrupt position" group.long 0x78++0x3 line.long 0x0 "LTDC_ECRCR,LTDC expected CRC register" hexmask.long.word 0x0 0.--15. 1. "ECRC,expected CRC of frame" rgroup.long 0x7C++0x3 line.long 0x0 "LTDC_CCRCR,LTDC computed CRC register" hexmask.long.word 0x0 0.--15. 1. "CCRC,computed CRC of frame" group.long 0x90++0x3 line.long 0x0 "LTDC_FUTR,LTDC FIFO underrun threshold register" hexmask.long.word 0x0 0.--15. 1. "THRE,threshold to trigger a FIFO underrun interrupt (per FIFO word 64 bits)" rgroup.long 0x100++0x3 line.long 0x0 "LTDC_L1C0R,LTDC layerx configuration 0 register" bitfld.long 0x0 31. "ARGB8888,pixel format ability for argb8888" "0,1" bitfld.long 0x0 30. "ABGR8888,pixel format ability for abgr8888" "0,1" newline bitfld.long 0x0 29. "RGBA8888,pixel format ability for rgba8888" "0,1" bitfld.long 0x0 28. "BGRA888,pixel format ability for bgra8888" "0,1" newline bitfld.long 0x0 27. "RGB565,pixel format ability for rgb565" "0,1" bitfld.long 0x0 26. "BGR565,pixel format ability for bgr565" "0,1" newline bitfld.long 0x0 25. "RGB888,pixel format ability for rgb888" "0,1" bitfld.long 0x0 24. "FF,flexible pixel format ability" "0,1" newline bitfld.long 0x0 23. "F11PC,blending factor 1 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 22. "F1PC,blending factor 1 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 21. "F11C,blending factor 1 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 20. "F1C,blending factor 1 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 19. "F11P,blending factor 1 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 18. "F1P,blending factor 1 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 17. "F10,blending factor 1 ability for: 0.0" "0,1" bitfld.long 0x0 16. "F11,blending factor 1 ability for: 1.0" "0,1" newline bitfld.long 0x0 15. "F21PC,blending factor 2 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 14. "F2PC,blending factor 2 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 13. "F21C,blending factor 2 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 12. "F2C,blending factor 2 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 11. "F21P,blending factor 2 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 10. "F2P,blending factor 2 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 9. "F20,blending factor 2 ability for: 0.0" "0,1" bitfld.long 0x0 8. "F21,blending factor 2 ability for: 1.0" "0,1" newline bitfld.long 0x0 7. "CKRA,color key replace ability" "0,1" bitfld.long 0x0 6. "CLUTA,CLUT ability" "0,1" newline bitfld.long 0x0 5. "WINA,windowing ability" "0,1" bitfld.long 0x0 4. "DCP,default color programmability" "0,1" newline bitfld.long 0x0 3. "APA,alpha plane ability" "0,1" bitfld.long 0x0 2. "CFBPA,color frame buffer pitch ability" "0,1" newline bitfld.long 0x0 1. "CFBDA,color frame buffer duplication ability" "0,1" bitfld.long 0x0 0. "CKTA,color key transparency ability" "0,1" group.long 0x104++0x4B line.long 0x0 "LTDC_L1C1R,LTDC layerx configuration 1 register" bitfld.long 0x0 31. "SCA,scaling ability for that layer" "0: scaling not available,1: scaling available" bitfld.long 0x0 2. "YFPA,YCbCr 420 full-planar ability for that layer" "0: full planar not available,1: full planar available" newline bitfld.long 0x0 1. "YSPA,YCbCr 420 semi-planar ability for that layer" "0: semi-planar not available,1: semi-planar available" bitfld.long 0x0 0. "YIA,YCbCr 422 interleaved ability for that layer" "0: interleaved not available,1: interleaved available" line.long 0x4 "LTDC_L1RCR,LTDC layerx reload control register" bitfld.long 0x4 2. "GRMSK,shadow reload control global (centralized) reload masked" "0: global reload active for this layer (control..,1: global reload masked for this layer (control.." bitfld.long 0x4 1. "VBR,vertical blanking reload request" "0: no effect,1: The shadow registers are reloaded during the.." newline bitfld.long 0x4 0. "IMR,immediate reload trigger" "0: no effect,1: The shadow registers are reloaded immediately." line.long 0x8 "LTDC_L1CR,LTDC layerx control register" bitfld.long 0x8 9. "DCBEN,default color blending enable" "0: blending disabled,1: blending enabled" bitfld.long 0x8 8. "HMEN,horizontal mirroring enable" "0: mirror disabled,1: mirror enabled (if so the color frame buffer.." newline bitfld.long 0x8 4. "CLUTEN,color look-up table enable" "0: color look-up table disabled,1: color look-up table enabled" bitfld.long 0x8 1. "CKEN,color keying enable" "0: color keying disabled,1: color keying enabled: if RGB matches then the.." newline bitfld.long 0x8 0. "LEN,layer enable" "0: layer disabled,1: layer enabled" line.long 0xC "LTDC_L1WHPCR,LTDC layerx window horizontal position configuration register" hexmask.long.word 0xC 16.--31. 1. "WHSPPOS,window horizontal stop position" hexmask.long.word 0xC 0.--15. 1. "WHSTPOS,window horizontal start position" line.long 0x10 "LTDC_L1WVPCR,LTDC layerx window vertical position configuration register" hexmask.long.word 0x10 16.--31. 1. "WVSPPOS,window vertical stop position" hexmask.long.word 0x10 0.--15. 1. "WVSTPOS,window vertical start position" line.long 0x14 "LTDC_L1CKCR,LTDC layerx color keying configuration register" hexmask.long.byte 0x14 16.--23. 1. "CKRED,color key red value" hexmask.long.byte 0x14 8.--15. 1. "CKGREEN,color key green value" newline hexmask.long.byte 0x14 0.--7. 1. "CKBLUE,color key blue value" line.long 0x18 "LTDC_L1PFCR,LTDC layerx pixel format configuration register" bitfld.long 0x18 0.--2. "PF,pixel format" "0: ARGB8888 (32 bpp),1: ABGR888 (32 bpp),2: RGBA888 (32 bpp),3: BGRA8888 (32 bpp),4: RGB565 (16 bpp A = 255),5: BGR565 (16 bpp A = 255),6: RGB888 (24 bpp packed A = 255),7: Flexible pixel format selected (see Section.." line.long 0x1C "LTDC_L1CACR,LTDC layerx constant alpha configuration register" hexmask.long.byte 0x1C 0.--7. 1. "CONSTA,constant alpha" line.long 0x20 "LTDC_L1DCCR,LTDC layerx default color configuration register" hexmask.long.byte 0x20 24.--31. 1. "DCALPHA,default color alpha" hexmask.long.byte 0x20 16.--23. 1. "DCRED,default color red" newline hexmask.long.byte 0x20 8.--15. 1. "DCGREEN,default color green" hexmask.long.byte 0x20 0.--7. 1. "DCBLUE,default color blue" line.long 0x24 "LTDC_L1BFCR,LTDC layerx blending factors configuration register" bitfld.long 0x24 16. "BOR,blending order" "0: layer set in background,1: layer set in foreground" bitfld.long 0x24 8.--10. "BF1,blending factor 1" "?,?,?,?,4: constant alpha,?,6: pixel alpha x constant alpha,?" newline bitfld.long 0x24 0.--2. "BF2,blending factor 2" "?,?,?,?,?,5: 1 - constant alpha,?,7: 1 - (pixel alpha x constant alpha)" line.long 0x28 "LTDC_L1BLCR,LTDC layerx burst length configuration register" hexmask.long.byte 0x28 0.--7. 1. "BL,burst length" line.long 0x2C "LTDC_L1PCR,LTDC layerx planar configuration register" bitfld.long 0x2C 9. "YREN,Y rescale enable for the color dynamic range" "0: rescaling disabled (input component thus assumed..,1: rescaling enabled (input component thus assumed.." bitfld.long 0x2C 8. "OF,Odd pixel first" "0: odd pixel disabled (thus even pixel on byte 0),1: odd pixel enabled (thus odd pixel on byte 0)" newline bitfld.long 0x2C 7. "CBF,Cb component first" "0: Cb disabled (thus Cr component is on byte 0 and 1),1: Cb enabled (thus Cb component is on byte 0 and 1)" bitfld.long 0x2C 6. "YF,Y component first" "0: Y component disabled (thus Cr or Cb component is..,1: Y component enabled (thus Y component is on byte.." newline bitfld.long 0x2C 4.--5. "YCM,YCbCr conversion mode" "0: interleaved 422 (Cb and Cr component are..,1: semi-Planar 420: (Cb and Cr component are..,2: full-Planar 420: (Cb and Cr component are..,?" bitfld.long 0x2C 3. "YCEN,YCbCr-to-RGB conversion enable" "0: conversion disabled,1: YCbCr conversion enabled using the YCM setting.." line.long 0x30 "LTDC_L1CFBAR,LTDC layerx color frame buffer address register" hexmask.long 0x30 0.--31. 1. "CFBADD,color frame buffer start address" line.long 0x34 "LTDC_L1CFBLR,LTDC layerx color frame buffer length register" hexmask.long.word 0x34 16.--31. 1. "CFBP,color frame buffer pitch in bytes" hexmask.long.word 0x34 0.--15. 1. "CFBLL,color frame buffer line length" line.long 0x38 "LTDC_L1CFBLNR,LTDC layerx color frame buffer line number register" hexmask.long.word 0x38 0.--15. 1. "CFBLNBR,frame buffer line number" line.long 0x3C "LTDC_L1AFBA0R,LTDC layer1 auxiliary frame buffer address 0 register" hexmask.long 0x3C 0.--31. 1. "AFBADD0,frame buffer start address" line.long 0x40 "LTDC_L1AFBA1R,LTDC layer1 auxiliary frame buffer address 1 register" hexmask.long 0x40 0.--31. 1. "AFBADD1,auxiliary frame buffer start address" line.long 0x44 "LTDC_L1AFBLR,LTDC layer1 auxiliary frame buffer length register" hexmask.long.word 0x44 16.--31. 1. "AFBP,auxiliary frame buffer pitch in bytes" hexmask.long.word 0x44 0.--15. 1. "AFBLL,auxiliary frame buffer line length" line.long 0x48 "LTDC_L1AFBLNR,LTDC layer1 auxiliary frame buffer line number register" hexmask.long.word 0x48 0.--15. 1. "AFBLNBR,auxiliary frame buffer line number" wgroup.long 0x150++0x3 line.long 0x0 "LTDC_L1CLUTWR,LTDC layerx CLUT write register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address" hexmask.long.byte 0x0 16.--23. 1. "RED,red value" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value" group.long 0x16C++0xF line.long 0x0 "LTDC_L1CYR0R,LTDC layerx conversion YCbCr RGB 0 register" hexmask.long.word 0x0 16.--25. 1. "CB2B,Cb-to-Blue coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x0 0.--9. 1. "CR2R,Cr-to-Red coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x4 "LTDC_L1CYR1R,LTDC layerx conversion YCbCr RGB 1 register" hexmask.long.word 0x4 16.--25. 1. "CB2G,Cb-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x4 0.--9. 1. "CR2G,Cr-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x8 "LTDC_L1FPF0R,LTDC layerx flexible pixel format 0 register" hexmask.long.byte 0x8 14.--17. 1. "RLEN,Width of the Red component (in bits)" hexmask.long.byte 0x8 9.--13. 1. "RPOS,Location of the Red component inside the pixel memory word (in bits)" newline hexmask.long.byte 0x8 5.--8. 1. "ALEN,Width of the Alpha component (in bits)" hexmask.long.byte 0x8 0.--4. 1. "APOS,Location of the Alpha component inside the pixel memory word (in bits)" line.long 0xC "LTDC_L1FPF1R,LTDC layerx flexible pixel format 1 register" bitfld.long 0xC 18.--20. "PSIZE,Pixel size (in bytes)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 14.--17. 1. "BLEN,Width of the Blue component (in bits)" newline hexmask.long.byte 0xC 9.--13. 1. "BPOS,Location of the Blue component inside the pixel memory word (in bits)" hexmask.long.byte 0xC 5.--8. 1. "GLEN,Width of the Green component (in bits)" newline hexmask.long.byte 0xC 0.--4. 1. "GPOS,Location of the Green component inside the pixel memory word (in bits)" rgroup.long 0x200++0x3 line.long 0x0 "LTDC_L2C0R,LTDC layerx configuration 0 register" bitfld.long 0x0 31. "ARGB8888,pixel format ability for argb8888" "0,1" bitfld.long 0x0 30. "ABGR8888,pixel format ability for abgr8888" "0,1" newline bitfld.long 0x0 29. "RGBA8888,pixel format ability for rgba8888" "0,1" bitfld.long 0x0 28. "BGRA888,pixel format ability for bgra8888" "0,1" newline bitfld.long 0x0 27. "RGB565,pixel format ability for rgb565" "0,1" bitfld.long 0x0 26. "BGR565,pixel format ability for bgr565" "0,1" newline bitfld.long 0x0 25. "RGB888,pixel format ability for rgb888" "0,1" bitfld.long 0x0 24. "FF,flexible pixel format ability" "0,1" newline bitfld.long 0x0 23. "F11PC,blending factor 1 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 22. "F1PC,blending factor 1 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 21. "F11C,blending factor 1 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 20. "F1C,blending factor 1 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 19. "F11P,blending factor 1 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 18. "F1P,blending factor 1 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 17. "F10,blending factor 1 ability for: 0.0" "0,1" bitfld.long 0x0 16. "F11,blending factor 1 ability for: 1.0" "0,1" newline bitfld.long 0x0 15. "F21PC,blending factor 2 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 14. "F2PC,blending factor 2 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 13. "F21C,blending factor 2 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 12. "F2C,blending factor 2 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 11. "F21P,blending factor 2 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 10. "F2P,blending factor 2 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 9. "F20,blending factor 2 ability for: 0.0" "0,1" bitfld.long 0x0 8. "F21,blending factor 2 ability for: 1.0" "0,1" newline bitfld.long 0x0 7. "CKRA,color key replace ability" "0,1" bitfld.long 0x0 6. "CLUTA,CLUT ability" "0,1" newline bitfld.long 0x0 5. "WINA,windowing ability" "0,1" bitfld.long 0x0 4. "DCP,default color programmability" "0,1" newline bitfld.long 0x0 3. "APA,alpha plane ability" "0,1" bitfld.long 0x0 2. "CFBPA,color frame buffer pitch ability" "0,1" newline bitfld.long 0x0 1. "CFBDA,color frame buffer duplication ability" "0,1" bitfld.long 0x0 0. "CKTA,color key transparency ability" "0,1" group.long 0x204++0x3B line.long 0x0 "LTDC_L2C1R,LTDC layerx configuration 1 register" bitfld.long 0x0 31. "SCA,scaling ability for that layer" "0: scaling not available,1: scaling available" bitfld.long 0x0 2. "YFPA,YCbCr 420 full-planar ability for that layer" "0: full planar not available,1: full planar available" newline bitfld.long 0x0 1. "YSPA,YCbCr 420 semi-planar ability for that layer" "0: semi-planar not available,1: semi-planar available" bitfld.long 0x0 0. "YIA,YCbCr 422 interleaved ability for that layer" "0: interleaved not available,1: interleaved available" line.long 0x4 "LTDC_L2RCR,LTDC layerx reload control register" bitfld.long 0x4 2. "GRMSK,shadow reload control global (centralized) reload masked" "0: global reload active for this layer (control..,1: global reload masked for this layer (control.." bitfld.long 0x4 1. "VBR,vertical blanking reload request" "0: no effect,1: The shadow registers are reloaded during the.." newline bitfld.long 0x4 0. "IMR,immediate reload trigger" "0: no effect,1: The shadow registers are reloaded immediately." line.long 0x8 "LTDC_L2CR,LTDC layerx control register" bitfld.long 0x8 9. "DCBEN,default color blending enable" "0: blending disabled,1: blending enabled" bitfld.long 0x8 8. "HMEN,horizontal mirroring enable" "0: mirror disabled,1: mirror enabled (if so the color frame buffer.." newline bitfld.long 0x8 4. "CLUTEN,color look-up table enable" "0: color look-up table disabled,1: color look-up table enabled" bitfld.long 0x8 1. "CKEN,color keying enable" "0: color keying disabled,1: color keying enabled: if RGB matches then the.." newline bitfld.long 0x8 0. "LEN,layer enable" "0: layer disabled,1: layer enabled" line.long 0xC "LTDC_L2WHPCR,LTDC layerx window horizontal position configuration register" hexmask.long.word 0xC 16.--31. 1. "WHSPPOS,window horizontal stop position" hexmask.long.word 0xC 0.--15. 1. "WHSTPOS,window horizontal start position" line.long 0x10 "LTDC_L2WVPCR,LTDC layerx window vertical position configuration register" hexmask.long.word 0x10 16.--31. 1. "WVSPPOS,window vertical stop position" hexmask.long.word 0x10 0.--15. 1. "WVSTPOS,window vertical start position" line.long 0x14 "LTDC_L2CKCR,LTDC layerx color keying configuration register" hexmask.long.byte 0x14 16.--23. 1. "CKRED,color key red value" hexmask.long.byte 0x14 8.--15. 1. "CKGREEN,color key green value" newline hexmask.long.byte 0x14 0.--7. 1. "CKBLUE,color key blue value" line.long 0x18 "LTDC_L2PFCR,LTDC layerx pixel format configuration register" bitfld.long 0x18 0.--2. "PF,pixel format" "0: ARGB8888 (32 bpp),1: ABGR888 (32 bpp),2: RGBA888 (32 bpp),3: BGRA8888 (32 bpp),4: RGB565 (16 bpp A = 255),5: BGR565 (16 bpp A = 255),6: RGB888 (24 bpp packed A = 255),7: Flexible pixel format selected (see Section.." line.long 0x1C "LTDC_L2CACR,LTDC layerx constant alpha configuration register" hexmask.long.byte 0x1C 0.--7. 1. "CONSTA,constant alpha" line.long 0x20 "LTDC_L2DCCR,LTDC layerx default color configuration register" hexmask.long.byte 0x20 24.--31. 1. "DCALPHA,default color alpha" hexmask.long.byte 0x20 16.--23. 1. "DCRED,default color red" newline hexmask.long.byte 0x20 8.--15. 1. "DCGREEN,default color green" hexmask.long.byte 0x20 0.--7. 1. "DCBLUE,default color blue" line.long 0x24 "LTDC_L2BFCR,LTDC layerx blending factors configuration register" bitfld.long 0x24 16. "BOR,blending order" "0: layer set in background,1: layer set in foreground" bitfld.long 0x24 8.--10. "BF1,blending factor 1" "?,?,?,?,4: constant alpha,?,6: pixel alpha x constant alpha,?" newline bitfld.long 0x24 0.--2. "BF2,blending factor 2" "?,?,?,?,?,5: 1 - constant alpha,?,7: 1 - (pixel alpha x constant alpha)" line.long 0x28 "LTDC_L2BLCR,LTDC layerx burst length configuration register" hexmask.long.byte 0x28 0.--7. 1. "BL,burst length" line.long 0x2C "LTDC_L2PCR,LTDC layerx planar configuration register" bitfld.long 0x2C 9. "YREN,Y rescale enable for the color dynamic range" "0: rescaling disabled (input component thus assumed..,1: rescaling enabled (input component thus assumed.." bitfld.long 0x2C 8. "OF,Odd pixel first" "0: odd pixel disabled (thus even pixel on byte 0),1: odd pixel enabled (thus odd pixel on byte 0)" newline bitfld.long 0x2C 7. "CBF,Cb component first" "0: Cb disabled (thus Cr component is on byte 0 and 1),1: Cb enabled (thus Cb component is on byte 0 and 1)" bitfld.long 0x2C 6. "YF,Y component first" "0: Y component disabled (thus Cr or Cb component is..,1: Y component enabled (thus Y component is on byte.." newline bitfld.long 0x2C 4.--5. "YCM,YCbCr conversion mode" "0: interleaved 422 (Cb and Cr component are..,1: semi-Planar 420: (Cb and Cr component are..,2: full-Planar 420: (Cb and Cr component are..,?" bitfld.long 0x2C 3. "YCEN,YCbCr-to-RGB conversion enable" "0: conversion disabled,1: YCbCr conversion enabled using the YCM setting.." line.long 0x30 "LTDC_L2CFBAR,LTDC layerx color frame buffer address register" hexmask.long 0x30 0.--31. 1. "CFBADD,color frame buffer start address" line.long 0x34 "LTDC_L2CFBLR,LTDC layerx color frame buffer length register" hexmask.long.word 0x34 16.--31. 1. "CFBP,color frame buffer pitch in bytes" hexmask.long.word 0x34 0.--15. 1. "CFBLL,color frame buffer line length" line.long 0x38 "LTDC_L2CFBLNR,LTDC layerx color frame buffer line number register" hexmask.long.word 0x38 0.--15. 1. "CFBLNBR,frame buffer line number" wgroup.long 0x250++0x3 line.long 0x0 "LTDC_L2CLUTWR,LTDC layerx CLUT write register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address" hexmask.long.byte 0x0 16.--23. 1. "RED,red value" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value" group.long 0x26C++0xF line.long 0x0 "LTDC_L2CYR0R,LTDC layerx conversion YCbCr RGB 0 register" hexmask.long.word 0x0 16.--25. 1. "CB2B,Cb-to-Blue coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x0 0.--9. 1. "CR2R,Cr-to-Red coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x4 "LTDC_L2CYR1R,LTDC layerx conversion YCbCr RGB 1 register" hexmask.long.word 0x4 16.--25. 1. "CB2G,Cb-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x4 0.--9. 1. "CR2G,Cr-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x8 "LTDC_L2FPF0R,LTDC layerx flexible pixel format 0 register" hexmask.long.byte 0x8 14.--17. 1. "RLEN,Width of the Red component (in bits)" hexmask.long.byte 0x8 9.--13. 1. "RPOS,Location of the Red component inside the pixel memory word (in bits)" newline hexmask.long.byte 0x8 5.--8. 1. "ALEN,Width of the Alpha component (in bits)" hexmask.long.byte 0x8 0.--4. 1. "APOS,Location of the Alpha component inside the pixel memory word (in bits)" line.long 0xC "LTDC_L2FPF1R,LTDC layerx flexible pixel format 1 register" bitfld.long 0xC 18.--20. "PSIZE,Pixel size (in bytes)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 14.--17. 1. "BLEN,Width of the Blue component (in bits)" newline hexmask.long.byte 0xC 9.--13. 1. "BPOS,Location of the Blue component inside the pixel memory word (in bits)" hexmask.long.byte 0xC 5.--8. 1. "GLEN,Width of the Green component (in bits)" newline hexmask.long.byte 0xC 0.--4. 1. "GPOS,Location of the Green component inside the pixel memory word (in bits)" tree.end tree.end sif (cpuis("STM32N655*")||cpuis("STM32N657*")) tree "MCE (Memory Cipher Engine)" base ad:0x0 tree "MCE1" base ad:0x4802B800 group.long 0x0++0x3 line.long 0x0 "MCE_CR,MCE configuration register" bitfld.long 0x0 4.--5. "CIPHERSEL,Cipher selection" "0: No cipher is selected. Any read (resp. write) to..,1: AES-128 cipher selected for all encrypted regions,2: Noekeon cipher selected for all encrypted regions,3: AES-256 cipher selected for all encrypted regions" bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx and MCE_FMKEYRx registers..,1: Writes to MCE_MKEYRx and MCE_FMKEYRx registers.." newline bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.." rgroup.long 0x4++0x7 line.long 0x0 "MCE_SR,MCE status register" bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCRx all..,1: When ENC bit and BREN are set in any MCE_REGCRx.." bitfld.long 0x0 2. "FMKVALID,Fast master key valid" "0: A valid key has not been written in MCE_FMKEYRx..,1: A valid key has been written in MCE_FMKEYRx.." newline bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.." line.long 0x4 "MCE_IASR,MCE illegal access status register" bitfld.long 0x4 1. "IAEF,Illegal access error flag" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "MCE_IACR,MCE illegal access clear register" bitfld.long 0x0 1. "IAEF,Illegal access error flag clear" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register" bitfld.long 0x0 1. "IAEIE,Illegal access error interrupt enable" "0: Interrupt generation on illegal access errors is..,1: Interrupt generation when an illegal access.." rgroup.long 0x24++0x3 line.long 0x0 "MCE_IADDR,MCE illegal address register" hexmask.long 0x0 0.--31. 1. "IADD,Illegal address" group.long 0x40++0xB line.long 0x0 "MCE_REGCR1,MCE region 1 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR1,MCE start address for region 1 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR1,MCE end address for region 1 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x50++0xB line.long 0x0 "MCE_REGCR2,MCE region 2 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR2,MCE start address for region 2 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR2,MCE end address for region 2 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x60++0xB line.long 0x0 "MCE_REGCR3,MCE region 3 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR3,MCE start address for region 3 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR3,MCE end address for region 3 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x70++0xB line.long 0x0 "MCE_REGCR4,MCE region 4 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR4,MCE start address for region 4 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR4,MCE end address for region 4 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" wgroup.long 0x200++0x3F line.long 0x0 "MCE_MKEYR0,.MCE master key 0" bitfld.long 0x0 31. "MKEY31,Master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x0 30. "MKEY30,Master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 29. "MKEY29,Master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x0 28. "MKEY28,Master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 27. "MKEY27,Master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x0 26. "MKEY26,Master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 25. "MKEY25,Master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x0 24. "MKEY24,Master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 23. "MKEY23,Master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x0 22. "MKEY22,Master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 21. "MKEY21,Master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x0 20. "MKEY20,Master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 19. "MKEY19,Master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x0 18. "MKEY18,Master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 17. "MKEY17,Master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x0 16. "MKEY16,Master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 15. "MKEY15,Master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x0 14. "MKEY14,Master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 13. "MKEY13,Master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x0 12. "MKEY12,Master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 11. "MKEY11,Master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x0 10. "MKEY10,Master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 9. "MKEY9,Master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x0 8. "MKEY8,Master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 7. "MKEY7,Master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x0 6. "MKEY6,Master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 5. "MKEY5,Master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x0 4. "MKEY4,Master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 3. "MKEY3,Master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x0 2. "MKEY2,Master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 1. "MKEY1,Master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x0 0. "MKEY0,Master key bit 0 (i = 31 to 0)" "0,1" line.long 0x4 "MCE_MKEYR1,.MCE master key 1" bitfld.long 0x4 31. "MKEY63,Master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x4 30. "MKEY62,Master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 29. "MKEY61,Master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x4 28. "MKEY60,Master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 27. "MKEY59,Master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x4 26. "MKEY58,Master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 25. "MKEY57,Master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x4 24. "MKEY56,Master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 23. "MKEY55,Master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x4 22. "MKEY54,Master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 21. "MKEY53,Master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x4 20. "MKEY52,Master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 19. "MKEY51,Master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x4 18. "MKEY50,Master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 17. "MKEY49,Master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x4 16. "MKEY48,Master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 15. "MKEY47,Master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x4 14. "MKEY46,Master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 13. "MKEY45,Master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x4 12. "MKEY44,Master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 11. "MKEY43,Master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x4 10. "MKEY42,Master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 9. "MKEY41,Master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x4 8. "MKEY40,Master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 7. "MKEY39,Master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x4 6. "MKEY38,Master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 5. "MKEY37,Master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x4 4. "MKEY36,Master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 3. "MKEY35,Master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x4 2. "MKEY34,Master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 1. "MKEY33,Master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x4 0. "MKEY32,Master key bit 32 (i = 31 to 0)" "0,1" line.long 0x8 "MCE_MKEYR2,.MCE master key 2" bitfld.long 0x8 31. "MKEY95,Master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x8 30. "MKEY94,Master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 29. "MKEY93,Master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x8 28. "MKEY92,Master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 27. "MKEY91,Master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x8 26. "MKEY90,Master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 25. "MKEY89,Master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x8 24. "MKEY88,Master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 23. "MKEY87,Master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x8 22. "MKEY86,Master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 21. "MKEY85,Master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x8 20. "MKEY84,Master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 19. "MKEY83,Master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x8 18. "MKEY82,Master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 17. "MKEY81,Master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x8 16. "MKEY80,Master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 15. "MKEY79,Master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x8 14. "MKEY78,Master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 13. "MKEY77,Master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x8 12. "MKEY76,Master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 11. "MKEY75,Master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x8 10. "MKEY74,Master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 9. "MKEY73,Master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x8 8. "MKEY72,Master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 7. "MKEY71,Master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x8 6. "MKEY70,Master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 5. "MKEY69,Master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x8 4. "MKEY68,Master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 3. "MKEY67,Master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x8 2. "MKEY66,Master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 1. "MKEY65,Master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x8 0. "MKEY64,Master key bit 64 (i = 31 to 0)" "0,1" line.long 0xC "MCE_MKEYR3,.MCE master key 3" bitfld.long 0xC 31. "MKEY127,Master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0xC 30. "MKEY126,Master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 29. "MKEY125,Master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0xC 28. "MKEY124,Master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 27. "MKEY123,Master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0xC 26. "MKEY122,Master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 25. "MKEY121,Master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0xC 24. "MKEY120,Master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 23. "MKEY119,Master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0xC 22. "MKEY118,Master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 21. "MKEY117,Master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0xC 20. "MKEY116,Master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 19. "MKEY115,Master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0xC 18. "MKEY114,Master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 17. "MKEY113,Master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0xC 16. "MKEY112,Master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 15. "MKEY111,Master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0xC 14. "MKEY110,Master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 13. "MKEY109,Master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0xC 12. "MKEY108,Master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 11. "MKEY107,Master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0xC 10. "MKEY106,Master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 9. "MKEY105,Master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0xC 8. "MKEY104,Master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 7. "MKEY103,Master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0xC 6. "MKEY102,Master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 5. "MKEY101,Master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0xC 4. "MKEY100,Master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 3. "MKEY99,Master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0xC 2. "MKEY98,Master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 1. "MKEY97,Master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0xC 0. "MKEY96,Master key bit 96 (i = 31 to 0)" "0,1" line.long 0x10 "MCE_MKEYR4,.MCE master key 4" bitfld.long 0x10 31. "MKEY159,Master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x10 30. "MKEY158,Master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 29. "MKEY157,Master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x10 28. "MKEY156,Master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 27. "MKEY155,Master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x10 26. "MKEY154,Master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 25. "MKEY153,Master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x10 24. "MKEY152,Master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 23. "MKEY151,Master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x10 22. "MKEY150,Master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 21. "MKEY149,Master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x10 20. "MKEY148,Master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 19. "MKEY147,Master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x10 18. "MKEY146,Master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 17. "MKEY145,Master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x10 16. "MKEY144,Master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 15. "MKEY143,Master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x10 14. "MKEY142,Master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 13. "MKEY141,Master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x10 12. "MKEY140,Master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 11. "MKEY139,Master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x10 10. "MKEY138,Master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 9. "MKEY137,Master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x10 8. "MKEY136,Master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 7. "MKEY135,Master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x10 6. "MKEY134,Master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 5. "MKEY133,Master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x10 4. "MKEY132,Master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 3. "MKEY131,Master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x10 2. "MKEY130,Master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 1. "MKEY129,Master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x10 0. "MKEY128,Master key bit 128 (i = 31 to 0)" "0,1" line.long 0x14 "MCE_MKEYR5,.MCE master key 5" bitfld.long 0x14 31. "MKEY191,Master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x14 30. "MKEY190,Master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 29. "MKEY189,Master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x14 28. "MKEY188,Master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 27. "MKEY187,Master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x14 26. "MKEY186,Master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 25. "MKEY185,Master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x14 24. "MKEY184,Master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 23. "MKEY183,Master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x14 22. "MKEY182,Master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 21. "MKEY181,Master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x14 20. "MKEY180,Master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 19. "MKEY179,Master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x14 18. "MKEY178,Master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 17. "MKEY177,Master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x14 16. "MKEY176,Master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 15. "MKEY175,Master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x14 14. "MKEY174,Master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 13. "MKEY173,Master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x14 12. "MKEY172,Master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 11. "MKEY171,Master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x14 10. "MKEY170,Master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 9. "MKEY169,Master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x14 8. "MKEY168,Master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 7. "MKEY167,Master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x14 6. "MKEY166,Master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 5. "MKEY165,Master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x14 4. "MKEY164,Master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 3. "MKEY163,Master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x14 2. "MKEY162,Master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 1. "MKEY161,Master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x14 0. "MKEY160,Master key bit 160 (i = 31 to 0)" "0,1" line.long 0x18 "MCE_MKEYR6,.MCE master key 6" bitfld.long 0x18 31. "MKEY223,Master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x18 30. "MKEY222,Master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 29. "MKEY221,Master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x18 28. "MKEY220,Master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 27. "MKEY219,Master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x18 26. "MKEY218,Master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 25. "MKEY217,Master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x18 24. "MKEY216,Master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 23. "MKEY215,Master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x18 22. "MKEY214,Master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 21. "MKEY213,Master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x18 20. "MKEY212,Master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 19. "MKEY211,Master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x18 18. "MKEY210,Master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 17. "MKEY209,Master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x18 16. "MKEY208,Master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 15. "MKEY207,Master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x18 14. "MKEY206,Master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 13. "MKEY205,Master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x18 12. "MKEY204,Master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 11. "MKEY203,Master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x18 10. "MKEY202,Master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 9. "MKEY201,Master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x18 8. "MKEY200,Master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 7. "MKEY199,Master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x18 6. "MKEY198,Master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 5. "MKEY197,Master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x18 4. "MKEY196,Master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 3. "MKEY195,Master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x18 2. "MKEY194,Master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 1. "MKEY193,Master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x18 0. "MKEY192,Master key bit 192 (i = 31 to 0)" "0,1" line.long 0x1C "MCE_MKEYR7,.MCE master key 7" bitfld.long 0x1C 31. "MKEY255,Master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x1C 30. "MKEY254,Master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 29. "MKEY253,Master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x1C 28. "MKEY252,Master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 27. "MKEY251,Master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x1C 26. "MKEY250,Master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 25. "MKEY249,Master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x1C 24. "MKEY248,Master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 23. "MKEY247,Master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x1C 22. "MKEY246,Master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 21. "MKEY245,Master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x1C 20. "MKEY244,Master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 19. "MKEY243,Master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x1C 18. "MKEY242,Master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 17. "MKEY241,Master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x1C 16. "MKEY240,Master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 15. "MKEY239,Master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x1C 14. "MKEY238,Master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 13. "MKEY237,Master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x1C 12. "MKEY236,Master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 11. "MKEY235,Master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x1C 10. "MKEY234,Master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 9. "MKEY233,Master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x1C 8. "MKEY232,Master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 7. "MKEY231,Master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x1C 6. "MKEY230,Master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 5. "MKEY229,Master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x1C 4. "MKEY228,Master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 3. "MKEY227,Master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x1C 2. "MKEY226,Master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 1. "MKEY225,Master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x1C 0. "MKEY224,Master key bit 224 (i = 31 to 0)" "0,1" line.long 0x20 "MCE_FMKEYR0,MCE fast master key 0" bitfld.long 0x20 31. "FMKEY31,Fast master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x20 30. "FMKEY30,Fast master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 29. "FMKEY29,Fast master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x20 28. "FMKEY28,Fast master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 27. "FMKEY27,Fast master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x20 26. "FMKEY26,Fast master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 25. "FMKEY25,Fast master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x20 24. "FMKEY24,Fast master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 23. "FMKEY23,Fast master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x20 22. "FMKEY22,Fast master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 21. "FMKEY21,Fast master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x20 20. "FMKEY20,Fast master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 19. "FMKEY19,Fast master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x20 18. "FMKEY18,Fast master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 17. "FMKEY17,Fast master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x20 16. "FMKEY16,Fast master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 15. "FMKEY15,Fast master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x20 14. "FMKEY14,Fast master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 13. "FMKEY13,Fast master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x20 12. "FMKEY12,Fast master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 11. "FMKEY11,Fast master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x20 10. "FMKEY10,Fast master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 9. "FMKEY9,Fast master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x20 8. "FMKEY8,Fast master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 7. "FMKEY7,Fast master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x20 6. "FMKEY6,Fast master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 5. "FMKEY5,Fast master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x20 4. "FMKEY4,Fast master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 3. "FMKEY3,Fast master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x20 2. "FMKEY2,Fast master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 1. "FMKEY1,Fast master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x20 0. "FMKEY0,Fast master key bit 0 (i = 31 to 0)" "0,1" line.long 0x24 "MCE_FMKEYR1,MCE fast master key 1" bitfld.long 0x24 31. "FMKEY63,Fast master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x24 30. "FMKEY62,Fast master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 29. "FMKEY61,Fast master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x24 28. "FMKEY60,Fast master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 27. "FMKEY59,Fast master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x24 26. "FMKEY58,Fast master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 25. "FMKEY57,Fast master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x24 24. "FMKEY56,Fast master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 23. "FMKEY55,Fast master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x24 22. "FMKEY54,Fast master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 21. "FMKEY53,Fast master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x24 20. "FMKEY52,Fast master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 19. "FMKEY51,Fast master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x24 18. "FMKEY50,Fast master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 17. "FMKEY49,Fast master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x24 16. "FMKEY48,Fast master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 15. "FMKEY47,Fast master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x24 14. "FMKEY46,Fast master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 13. "FMKEY45,Fast master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x24 12. "FMKEY44,Fast master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 11. "FMKEY43,Fast master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x24 10. "FMKEY42,Fast master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 9. "FMKEY41,Fast master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x24 8. "FMKEY40,Fast master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 7. "FMKEY39,Fast master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x24 6. "FMKEY38,Fast master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 5. "FMKEY37,Fast master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x24 4. "FMKEY36,Fast master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 3. "FMKEY35,Fast master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x24 2. "FMKEY34,Fast master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 1. "FMKEY33,Fast master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x24 0. "FMKEY32,Fast master key bit 32 (i = 31 to 0)" "0,1" line.long 0x28 "MCE_FMKEYR2,MCE fast master key 2" bitfld.long 0x28 31. "FMKEY95,Fast master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x28 30. "FMKEY94,Fast master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 29. "FMKEY93,Fast master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x28 28. "FMKEY92,Fast master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 27. "FMKEY91,Fast master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x28 26. "FMKEY90,Fast master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 25. "FMKEY89,Fast master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x28 24. "FMKEY88,Fast master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 23. "FMKEY87,Fast master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x28 22. "FMKEY86,Fast master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 21. "FMKEY85,Fast master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x28 20. "FMKEY84,Fast master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 19. "FMKEY83,Fast master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x28 18. "FMKEY82,Fast master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 17. "FMKEY81,Fast master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x28 16. "FMKEY80,Fast master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 15. "FMKEY79,Fast master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x28 14. "FMKEY78,Fast master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 13. "FMKEY77,Fast master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x28 12. "FMKEY76,Fast master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 11. "FMKEY75,Fast master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x28 10. "FMKEY74,Fast master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 9. "FMKEY73,Fast master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x28 8. "FMKEY72,Fast master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 7. "FMKEY71,Fast master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x28 6. "FMKEY70,Fast master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 5. "FMKEY69,Fast master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x28 4. "FMKEY68,Fast master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 3. "FMKEY67,Fast master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x28 2. "FMKEY66,Fast master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 1. "FMKEY65,Fast master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x28 0. "FMKEY64,Fast master key bit 64 (i = 31 to 0)" "0,1" line.long 0x2C "MCE_FMKEYR3,MCE fast master key 3" bitfld.long 0x2C 31. "FMKEY127,Fast master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0x2C 30. "FMKEY126,Fast master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 29. "FMKEY125,Fast master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0x2C 28. "FMKEY124,Fast master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 27. "FMKEY123,Fast master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0x2C 26. "FMKEY122,Fast master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 25. "FMKEY121,Fast master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0x2C 24. "FMKEY120,Fast master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 23. "FMKEY119,Fast master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0x2C 22. "FMKEY118,Fast master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 21. "FMKEY117,Fast master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0x2C 20. "FMKEY116,Fast master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 19. "FMKEY115,Fast master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0x2C 18. "FMKEY114,Fast master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 17. "FMKEY113,Fast master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0x2C 16. "FMKEY112,Fast master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 15. "FMKEY111,Fast master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0x2C 14. "FMKEY110,Fast master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 13. "FMKEY109,Fast master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0x2C 12. "FMKEY108,Fast master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 11. "FMKEY107,Fast master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0x2C 10. "FMKEY106,Fast master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 9. "FMKEY105,Fast master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0x2C 8. "FMKEY104,Fast master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 7. "FMKEY103,Fast master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0x2C 6. "FMKEY102,Fast master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 5. "FMKEY101,Fast master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0x2C 4. "FMKEY100,Fast master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 3. "FMKEY99,Fast master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0x2C 2. "FMKEY98,Fast master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 1. "FMKEY97,Fast master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0x2C 0. "FMKEY96,Fast master key bit 96 (i = 31 to 0)" "0,1" line.long 0x30 "MCE_FMKEYR4,MCE fast master key 4" bitfld.long 0x30 31. "FMKEY159,Fast master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x30 30. "FMKEY158,Fast master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 29. "FMKEY157,Fast master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x30 28. "FMKEY156,Fast master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 27. "FMKEY155,Fast master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x30 26. "FMKEY154,Fast master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 25. "FMKEY153,Fast master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x30 24. "FMKEY152,Fast master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 23. "FMKEY151,Fast master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x30 22. "FMKEY150,Fast master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 21. "FMKEY149,Fast master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x30 20. "FMKEY148,Fast master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 19. "FMKEY147,Fast master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x30 18. "FMKEY146,Fast master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 17. "FMKEY145,Fast master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x30 16. "FMKEY144,Fast master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 15. "FMKEY143,Fast master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x30 14. "FMKEY142,Fast master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 13. "FMKEY141,Fast master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x30 12. "FMKEY140,Fast master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 11. "FMKEY139,Fast master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x30 10. "FMKEY138,Fast master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 9. "FMKEY137,Fast master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x30 8. "FMKEY136,Fast master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 7. "FMKEY135,Fast master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x30 6. "FMKEY134,Fast master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 5. "FMKEY133,Fast master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x30 4. "FMKEY132,Fast master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 3. "FMKEY131,Fast master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x30 2. "FMKEY130,Fast master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 1. "FMKEY129,Fast master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x30 0. "FMKEY128,Fast master key bit 128 (i = 31 to 0)" "0,1" line.long 0x34 "MCE_FMKEYR5,MCE fast master key 5" bitfld.long 0x34 31. "FMKEY191,Fast master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x34 30. "FMKEY190,Fast master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 29. "FMKEY189,Fast master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x34 28. "FMKEY188,Fast master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 27. "FMKEY187,Fast master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x34 26. "FMKEY186,Fast master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 25. "FMKEY185,Fast master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x34 24. "FMKEY184,Fast master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 23. "FMKEY183,Fast master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x34 22. "FMKEY182,Fast master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 21. "FMKEY181,Fast master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x34 20. "FMKEY180,Fast master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 19. "FMKEY179,Fast master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x34 18. "FMKEY178,Fast master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 17. "FMKEY177,Fast master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x34 16. "FMKEY176,Fast master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 15. "FMKEY175,Fast master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x34 14. "FMKEY174,Fast master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 13. "FMKEY173,Fast master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x34 12. "FMKEY172,Fast master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 11. "FMKEY171,Fast master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x34 10. "FMKEY170,Fast master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 9. "FMKEY169,Fast master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x34 8. "FMKEY168,Fast master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 7. "FMKEY167,Fast master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x34 6. "FMKEY166,Fast master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 5. "FMKEY165,Fast master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x34 4. "FMKEY164,Fast master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 3. "FMKEY163,Fast master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x34 2. "FMKEY162,Fast master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 1. "FMKEY161,Fast master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x34 0. "FMKEY160,Fast master key bit 160 (i = 31 to 0)" "0,1" line.long 0x38 "MCE_FMKEYR6,MCE fast master key 6" bitfld.long 0x38 31. "FMKEY223,Fast master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x38 30. "FMKEY222,Fast master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 29. "FMKEY221,Fast master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x38 28. "FMKEY220,Fast master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 27. "FMKEY219,Fast master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x38 26. "FMKEY218,Fast master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 25. "FMKEY217,Fast master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x38 24. "FMKEY216,Fast master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 23. "FMKEY215,Fast master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x38 22. "FMKEY214,Fast master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 21. "FMKEY213,Fast master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x38 20. "FMKEY212,Fast master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 19. "FMKEY211,Fast master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x38 18. "FMKEY210,Fast master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 17. "FMKEY209,Fast master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x38 16. "FMKEY208,Fast master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 15. "FMKEY207,Fast master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x38 14. "FMKEY206,Fast master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 13. "FMKEY205,Fast master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x38 12. "FMKEY204,Fast master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 11. "FMKEY203,Fast master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x38 10. "FMKEY202,Fast master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 9. "FMKEY201,Fast master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x38 8. "FMKEY200,Fast master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 7. "FMKEY199,Fast master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x38 6. "FMKEY198,Fast master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 5. "FMKEY197,Fast master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x38 4. "FMKEY196,Fast master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 3. "FMKEY195,Fast master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x38 2. "FMKEY194,Fast master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 1. "FMKEY193,Fast master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x38 0. "FMKEY192,Fast master key bit 192 (i = 31 to 0)" "0,1" line.long 0x3C "MCE_FMKEYR7,MCE fast master key 7" bitfld.long 0x3C 31. "FMKEY255,Fast master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x3C 30. "FMKEY254,Fast master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 29. "FMKEY253,Fast master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x3C 28. "FMKEY252,Fast master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 27. "FMKEY251,Fast master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x3C 26. "FMKEY250,Fast master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 25. "FMKEY249,Fast master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x3C 24. "FMKEY248,Fast master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 23. "FMKEY247,Fast master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x3C 22. "FMKEY246,Fast master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 21. "FMKEY245,Fast master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x3C 20. "FMKEY244,Fast master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 19. "FMKEY243,Fast master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x3C 18. "FMKEY242,Fast master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 17. "FMKEY241,Fast master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x3C 16. "FMKEY240,Fast master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 15. "FMKEY239,Fast master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x3C 14. "FMKEY238,Fast master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 13. "FMKEY237,Fast master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x3C 12. "FMKEY236,Fast master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 11. "FMKEY235,Fast master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x3C 10. "FMKEY234,Fast master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 9. "FMKEY233,Fast master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x3C 8. "FMKEY232,Fast master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 7. "FMKEY231,Fast master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x3C 6. "FMKEY230,Fast master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 5. "FMKEY229,Fast master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x3C 4. "FMKEY228,Fast master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 3. "FMKEY227,Fast master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x3C 2. "FMKEY226,Fast master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 1. "FMKEY225,Fast master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x3C 0. "FMKEY224,Fast master key bit 224 (i = 31 to 0)" "0,1" group.long 0x240++0xB line.long 0x0 "MCE_CC1CFGR,MCE cipher context 1 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC1NR0,MCE cipher context 1 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC1NR1,MCE cipher context 1 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x24C++0xF line.long 0x0 "MCE_CC1KEYR0,MCE cipher context 1 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC1KEYR1,MCE cipher context 1 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC1KEYR2,MCE cipher context 1 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC1KEYR3,MCE cipher context 1 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" group.long 0x270++0xB line.long 0x0 "MCE_CC2CFGR,MCE cipher context 2 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC2NR0,MCE cipher context 2 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC2NR1,MCE cipher context 2 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x27C++0xF line.long 0x0 "MCE_CC2KEYR0,MCE cipher context 2 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC2KEYR1,MCE cipher context 2 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC2KEYR2,MCE cipher context 2 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC2KEYR3,MCE cipher context 2 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" tree.end tree "MCE1_S" base ad:0x5802B800 group.long 0x0++0x3 line.long 0x0 "MCE_CR,MCE configuration register" bitfld.long 0x0 4.--5. "CIPHERSEL,Cipher selection" "0: No cipher is selected. Any read (resp. write) to..,1: AES-128 cipher selected for all encrypted regions,2: Noekeon cipher selected for all encrypted regions,3: AES-256 cipher selected for all encrypted regions" bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx and MCE_FMKEYRx registers..,1: Writes to MCE_MKEYRx and MCE_FMKEYRx registers.." newline bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.." rgroup.long 0x4++0x7 line.long 0x0 "MCE_SR,MCE status register" bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCRx all..,1: When ENC bit and BREN are set in any MCE_REGCRx.." bitfld.long 0x0 2. "FMKVALID,Fast master key valid" "0: A valid key has not been written in MCE_FMKEYRx..,1: A valid key has been written in MCE_FMKEYRx.." newline bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.." line.long 0x4 "MCE_IASR,MCE illegal access status register" bitfld.long 0x4 1. "IAEF,Illegal access error flag" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "MCE_IACR,MCE illegal access clear register" bitfld.long 0x0 1. "IAEF,Illegal access error flag clear" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register" bitfld.long 0x0 1. "IAEIE,Illegal access error interrupt enable" "0: Interrupt generation on illegal access errors is..,1: Interrupt generation when an illegal access.." rgroup.long 0x24++0x3 line.long 0x0 "MCE_IADDR,MCE illegal address register" hexmask.long 0x0 0.--31. 1. "IADD,Illegal address" group.long 0x40++0xB line.long 0x0 "MCE_REGCR1,MCE region 1 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR1,MCE start address for region 1 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR1,MCE end address for region 1 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x50++0xB line.long 0x0 "MCE_REGCR2,MCE region 2 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR2,MCE start address for region 2 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR2,MCE end address for region 2 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x60++0xB line.long 0x0 "MCE_REGCR3,MCE region 3 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR3,MCE start address for region 3 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR3,MCE end address for region 3 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x70++0xB line.long 0x0 "MCE_REGCR4,MCE region 4 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR4,MCE start address for region 4 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR4,MCE end address for region 4 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" wgroup.long 0x200++0x3F line.long 0x0 "MCE_MKEYR0,.MCE master key 0" bitfld.long 0x0 31. "MKEY31,Master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x0 30. "MKEY30,Master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 29. "MKEY29,Master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x0 28. "MKEY28,Master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 27. "MKEY27,Master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x0 26. "MKEY26,Master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 25. "MKEY25,Master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x0 24. "MKEY24,Master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 23. "MKEY23,Master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x0 22. "MKEY22,Master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 21. "MKEY21,Master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x0 20. "MKEY20,Master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 19. "MKEY19,Master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x0 18. "MKEY18,Master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 17. "MKEY17,Master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x0 16. "MKEY16,Master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 15. "MKEY15,Master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x0 14. "MKEY14,Master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 13. "MKEY13,Master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x0 12. "MKEY12,Master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 11. "MKEY11,Master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x0 10. "MKEY10,Master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 9. "MKEY9,Master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x0 8. "MKEY8,Master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 7. "MKEY7,Master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x0 6. "MKEY6,Master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 5. "MKEY5,Master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x0 4. "MKEY4,Master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 3. "MKEY3,Master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x0 2. "MKEY2,Master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 1. "MKEY1,Master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x0 0. "MKEY0,Master key bit 0 (i = 31 to 0)" "0,1" line.long 0x4 "MCE_MKEYR1,.MCE master key 1" bitfld.long 0x4 31. "MKEY63,Master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x4 30. "MKEY62,Master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 29. "MKEY61,Master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x4 28. "MKEY60,Master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 27. "MKEY59,Master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x4 26. "MKEY58,Master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 25. "MKEY57,Master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x4 24. "MKEY56,Master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 23. "MKEY55,Master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x4 22. "MKEY54,Master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 21. "MKEY53,Master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x4 20. "MKEY52,Master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 19. "MKEY51,Master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x4 18. "MKEY50,Master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 17. "MKEY49,Master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x4 16. "MKEY48,Master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 15. "MKEY47,Master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x4 14. "MKEY46,Master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 13. "MKEY45,Master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x4 12. "MKEY44,Master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 11. "MKEY43,Master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x4 10. "MKEY42,Master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 9. "MKEY41,Master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x4 8. "MKEY40,Master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 7. "MKEY39,Master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x4 6. "MKEY38,Master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 5. "MKEY37,Master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x4 4. "MKEY36,Master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 3. "MKEY35,Master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x4 2. "MKEY34,Master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 1. "MKEY33,Master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x4 0. "MKEY32,Master key bit 32 (i = 31 to 0)" "0,1" line.long 0x8 "MCE_MKEYR2,.MCE master key 2" bitfld.long 0x8 31. "MKEY95,Master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x8 30. "MKEY94,Master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 29. "MKEY93,Master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x8 28. "MKEY92,Master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 27. "MKEY91,Master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x8 26. "MKEY90,Master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 25. "MKEY89,Master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x8 24. "MKEY88,Master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 23. "MKEY87,Master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x8 22. "MKEY86,Master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 21. "MKEY85,Master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x8 20. "MKEY84,Master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 19. "MKEY83,Master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x8 18. "MKEY82,Master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 17. "MKEY81,Master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x8 16. "MKEY80,Master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 15. "MKEY79,Master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x8 14. "MKEY78,Master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 13. "MKEY77,Master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x8 12. "MKEY76,Master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 11. "MKEY75,Master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x8 10. "MKEY74,Master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 9. "MKEY73,Master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x8 8. "MKEY72,Master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 7. "MKEY71,Master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x8 6. "MKEY70,Master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 5. "MKEY69,Master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x8 4. "MKEY68,Master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 3. "MKEY67,Master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x8 2. "MKEY66,Master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 1. "MKEY65,Master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x8 0. "MKEY64,Master key bit 64 (i = 31 to 0)" "0,1" line.long 0xC "MCE_MKEYR3,.MCE master key 3" bitfld.long 0xC 31. "MKEY127,Master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0xC 30. "MKEY126,Master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 29. "MKEY125,Master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0xC 28. "MKEY124,Master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 27. "MKEY123,Master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0xC 26. "MKEY122,Master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 25. "MKEY121,Master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0xC 24. "MKEY120,Master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 23. "MKEY119,Master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0xC 22. "MKEY118,Master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 21. "MKEY117,Master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0xC 20. "MKEY116,Master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 19. "MKEY115,Master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0xC 18. "MKEY114,Master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 17. "MKEY113,Master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0xC 16. "MKEY112,Master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 15. "MKEY111,Master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0xC 14. "MKEY110,Master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 13. "MKEY109,Master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0xC 12. "MKEY108,Master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 11. "MKEY107,Master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0xC 10. "MKEY106,Master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 9. "MKEY105,Master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0xC 8. "MKEY104,Master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 7. "MKEY103,Master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0xC 6. "MKEY102,Master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 5. "MKEY101,Master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0xC 4. "MKEY100,Master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 3. "MKEY99,Master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0xC 2. "MKEY98,Master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 1. "MKEY97,Master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0xC 0. "MKEY96,Master key bit 96 (i = 31 to 0)" "0,1" line.long 0x10 "MCE_MKEYR4,.MCE master key 4" bitfld.long 0x10 31. "MKEY159,Master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x10 30. "MKEY158,Master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 29. "MKEY157,Master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x10 28. "MKEY156,Master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 27. "MKEY155,Master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x10 26. "MKEY154,Master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 25. "MKEY153,Master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x10 24. "MKEY152,Master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 23. "MKEY151,Master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x10 22. "MKEY150,Master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 21. "MKEY149,Master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x10 20. "MKEY148,Master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 19. "MKEY147,Master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x10 18. "MKEY146,Master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 17. "MKEY145,Master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x10 16. "MKEY144,Master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 15. "MKEY143,Master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x10 14. "MKEY142,Master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 13. "MKEY141,Master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x10 12. "MKEY140,Master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 11. "MKEY139,Master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x10 10. "MKEY138,Master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 9. "MKEY137,Master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x10 8. "MKEY136,Master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 7. "MKEY135,Master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x10 6. "MKEY134,Master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 5. "MKEY133,Master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x10 4. "MKEY132,Master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 3. "MKEY131,Master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x10 2. "MKEY130,Master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 1. "MKEY129,Master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x10 0. "MKEY128,Master key bit 128 (i = 31 to 0)" "0,1" line.long 0x14 "MCE_MKEYR5,.MCE master key 5" bitfld.long 0x14 31. "MKEY191,Master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x14 30. "MKEY190,Master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 29. "MKEY189,Master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x14 28. "MKEY188,Master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 27. "MKEY187,Master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x14 26. "MKEY186,Master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 25. "MKEY185,Master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x14 24. "MKEY184,Master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 23. "MKEY183,Master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x14 22. "MKEY182,Master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 21. "MKEY181,Master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x14 20. "MKEY180,Master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 19. "MKEY179,Master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x14 18. "MKEY178,Master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 17. "MKEY177,Master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x14 16. "MKEY176,Master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 15. "MKEY175,Master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x14 14. "MKEY174,Master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 13. "MKEY173,Master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x14 12. "MKEY172,Master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 11. "MKEY171,Master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x14 10. "MKEY170,Master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 9. "MKEY169,Master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x14 8. "MKEY168,Master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 7. "MKEY167,Master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x14 6. "MKEY166,Master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 5. "MKEY165,Master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x14 4. "MKEY164,Master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 3. "MKEY163,Master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x14 2. "MKEY162,Master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 1. "MKEY161,Master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x14 0. "MKEY160,Master key bit 160 (i = 31 to 0)" "0,1" line.long 0x18 "MCE_MKEYR6,.MCE master key 6" bitfld.long 0x18 31. "MKEY223,Master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x18 30. "MKEY222,Master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 29. "MKEY221,Master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x18 28. "MKEY220,Master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 27. "MKEY219,Master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x18 26. "MKEY218,Master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 25. "MKEY217,Master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x18 24. "MKEY216,Master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 23. "MKEY215,Master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x18 22. "MKEY214,Master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 21. "MKEY213,Master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x18 20. "MKEY212,Master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 19. "MKEY211,Master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x18 18. "MKEY210,Master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 17. "MKEY209,Master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x18 16. "MKEY208,Master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 15. "MKEY207,Master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x18 14. "MKEY206,Master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 13. "MKEY205,Master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x18 12. "MKEY204,Master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 11. "MKEY203,Master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x18 10. "MKEY202,Master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 9. "MKEY201,Master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x18 8. "MKEY200,Master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 7. "MKEY199,Master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x18 6. "MKEY198,Master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 5. "MKEY197,Master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x18 4. "MKEY196,Master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 3. "MKEY195,Master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x18 2. "MKEY194,Master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 1. "MKEY193,Master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x18 0. "MKEY192,Master key bit 192 (i = 31 to 0)" "0,1" line.long 0x1C "MCE_MKEYR7,.MCE master key 7" bitfld.long 0x1C 31. "MKEY255,Master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x1C 30. "MKEY254,Master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 29. "MKEY253,Master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x1C 28. "MKEY252,Master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 27. "MKEY251,Master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x1C 26. "MKEY250,Master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 25. "MKEY249,Master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x1C 24. "MKEY248,Master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 23. "MKEY247,Master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x1C 22. "MKEY246,Master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 21. "MKEY245,Master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x1C 20. "MKEY244,Master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 19. "MKEY243,Master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x1C 18. "MKEY242,Master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 17. "MKEY241,Master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x1C 16. "MKEY240,Master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 15. "MKEY239,Master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x1C 14. "MKEY238,Master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 13. "MKEY237,Master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x1C 12. "MKEY236,Master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 11. "MKEY235,Master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x1C 10. "MKEY234,Master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 9. "MKEY233,Master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x1C 8. "MKEY232,Master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 7. "MKEY231,Master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x1C 6. "MKEY230,Master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 5. "MKEY229,Master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x1C 4. "MKEY228,Master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 3. "MKEY227,Master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x1C 2. "MKEY226,Master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 1. "MKEY225,Master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x1C 0. "MKEY224,Master key bit 224 (i = 31 to 0)" "0,1" line.long 0x20 "MCE_FMKEYR0,MCE fast master key 0" bitfld.long 0x20 31. "FMKEY31,Fast master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x20 30. "FMKEY30,Fast master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 29. "FMKEY29,Fast master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x20 28. "FMKEY28,Fast master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 27. "FMKEY27,Fast master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x20 26. "FMKEY26,Fast master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 25. "FMKEY25,Fast master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x20 24. "FMKEY24,Fast master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 23. "FMKEY23,Fast master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x20 22. "FMKEY22,Fast master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 21. "FMKEY21,Fast master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x20 20. "FMKEY20,Fast master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 19. "FMKEY19,Fast master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x20 18. "FMKEY18,Fast master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 17. "FMKEY17,Fast master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x20 16. "FMKEY16,Fast master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 15. "FMKEY15,Fast master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x20 14. "FMKEY14,Fast master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 13. "FMKEY13,Fast master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x20 12. "FMKEY12,Fast master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 11. "FMKEY11,Fast master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x20 10. "FMKEY10,Fast master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 9. "FMKEY9,Fast master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x20 8. "FMKEY8,Fast master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 7. "FMKEY7,Fast master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x20 6. "FMKEY6,Fast master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 5. "FMKEY5,Fast master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x20 4. "FMKEY4,Fast master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 3. "FMKEY3,Fast master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x20 2. "FMKEY2,Fast master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 1. "FMKEY1,Fast master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x20 0. "FMKEY0,Fast master key bit 0 (i = 31 to 0)" "0,1" line.long 0x24 "MCE_FMKEYR1,MCE fast master key 1" bitfld.long 0x24 31. "FMKEY63,Fast master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x24 30. "FMKEY62,Fast master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 29. "FMKEY61,Fast master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x24 28. "FMKEY60,Fast master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 27. "FMKEY59,Fast master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x24 26. "FMKEY58,Fast master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 25. "FMKEY57,Fast master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x24 24. "FMKEY56,Fast master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 23. "FMKEY55,Fast master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x24 22. "FMKEY54,Fast master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 21. "FMKEY53,Fast master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x24 20. "FMKEY52,Fast master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 19. "FMKEY51,Fast master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x24 18. "FMKEY50,Fast master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 17. "FMKEY49,Fast master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x24 16. "FMKEY48,Fast master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 15. "FMKEY47,Fast master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x24 14. "FMKEY46,Fast master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 13. "FMKEY45,Fast master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x24 12. "FMKEY44,Fast master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 11. "FMKEY43,Fast master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x24 10. "FMKEY42,Fast master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 9. "FMKEY41,Fast master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x24 8. "FMKEY40,Fast master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 7. "FMKEY39,Fast master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x24 6. "FMKEY38,Fast master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 5. "FMKEY37,Fast master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x24 4. "FMKEY36,Fast master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 3. "FMKEY35,Fast master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x24 2. "FMKEY34,Fast master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 1. "FMKEY33,Fast master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x24 0. "FMKEY32,Fast master key bit 32 (i = 31 to 0)" "0,1" line.long 0x28 "MCE_FMKEYR2,MCE fast master key 2" bitfld.long 0x28 31. "FMKEY95,Fast master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x28 30. "FMKEY94,Fast master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 29. "FMKEY93,Fast master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x28 28. "FMKEY92,Fast master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 27. "FMKEY91,Fast master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x28 26. "FMKEY90,Fast master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 25. "FMKEY89,Fast master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x28 24. "FMKEY88,Fast master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 23. "FMKEY87,Fast master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x28 22. "FMKEY86,Fast master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 21. "FMKEY85,Fast master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x28 20. "FMKEY84,Fast master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 19. "FMKEY83,Fast master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x28 18. "FMKEY82,Fast master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 17. "FMKEY81,Fast master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x28 16. "FMKEY80,Fast master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 15. "FMKEY79,Fast master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x28 14. "FMKEY78,Fast master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 13. "FMKEY77,Fast master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x28 12. "FMKEY76,Fast master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 11. "FMKEY75,Fast master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x28 10. "FMKEY74,Fast master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 9. "FMKEY73,Fast master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x28 8. "FMKEY72,Fast master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 7. "FMKEY71,Fast master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x28 6. "FMKEY70,Fast master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 5. "FMKEY69,Fast master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x28 4. "FMKEY68,Fast master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 3. "FMKEY67,Fast master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x28 2. "FMKEY66,Fast master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 1. "FMKEY65,Fast master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x28 0. "FMKEY64,Fast master key bit 64 (i = 31 to 0)" "0,1" line.long 0x2C "MCE_FMKEYR3,MCE fast master key 3" bitfld.long 0x2C 31. "FMKEY127,Fast master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0x2C 30. "FMKEY126,Fast master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 29. "FMKEY125,Fast master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0x2C 28. "FMKEY124,Fast master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 27. "FMKEY123,Fast master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0x2C 26. "FMKEY122,Fast master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 25. "FMKEY121,Fast master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0x2C 24. "FMKEY120,Fast master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 23. "FMKEY119,Fast master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0x2C 22. "FMKEY118,Fast master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 21. "FMKEY117,Fast master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0x2C 20. "FMKEY116,Fast master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 19. "FMKEY115,Fast master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0x2C 18. "FMKEY114,Fast master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 17. "FMKEY113,Fast master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0x2C 16. "FMKEY112,Fast master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 15. "FMKEY111,Fast master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0x2C 14. "FMKEY110,Fast master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 13. "FMKEY109,Fast master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0x2C 12. "FMKEY108,Fast master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 11. "FMKEY107,Fast master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0x2C 10. "FMKEY106,Fast master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 9. "FMKEY105,Fast master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0x2C 8. "FMKEY104,Fast master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 7. "FMKEY103,Fast master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0x2C 6. "FMKEY102,Fast master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 5. "FMKEY101,Fast master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0x2C 4. "FMKEY100,Fast master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 3. "FMKEY99,Fast master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0x2C 2. "FMKEY98,Fast master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 1. "FMKEY97,Fast master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0x2C 0. "FMKEY96,Fast master key bit 96 (i = 31 to 0)" "0,1" line.long 0x30 "MCE_FMKEYR4,MCE fast master key 4" bitfld.long 0x30 31. "FMKEY159,Fast master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x30 30. "FMKEY158,Fast master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 29. "FMKEY157,Fast master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x30 28. "FMKEY156,Fast master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 27. "FMKEY155,Fast master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x30 26. "FMKEY154,Fast master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 25. "FMKEY153,Fast master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x30 24. "FMKEY152,Fast master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 23. "FMKEY151,Fast master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x30 22. "FMKEY150,Fast master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 21. "FMKEY149,Fast master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x30 20. "FMKEY148,Fast master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 19. "FMKEY147,Fast master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x30 18. "FMKEY146,Fast master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 17. "FMKEY145,Fast master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x30 16. "FMKEY144,Fast master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 15. "FMKEY143,Fast master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x30 14. "FMKEY142,Fast master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 13. "FMKEY141,Fast master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x30 12. "FMKEY140,Fast master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 11. "FMKEY139,Fast master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x30 10. "FMKEY138,Fast master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 9. "FMKEY137,Fast master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x30 8. "FMKEY136,Fast master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 7. "FMKEY135,Fast master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x30 6. "FMKEY134,Fast master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 5. "FMKEY133,Fast master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x30 4. "FMKEY132,Fast master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 3. "FMKEY131,Fast master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x30 2. "FMKEY130,Fast master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 1. "FMKEY129,Fast master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x30 0. "FMKEY128,Fast master key bit 128 (i = 31 to 0)" "0,1" line.long 0x34 "MCE_FMKEYR5,MCE fast master key 5" bitfld.long 0x34 31. "FMKEY191,Fast master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x34 30. "FMKEY190,Fast master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 29. "FMKEY189,Fast master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x34 28. "FMKEY188,Fast master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 27. "FMKEY187,Fast master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x34 26. "FMKEY186,Fast master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 25. "FMKEY185,Fast master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x34 24. "FMKEY184,Fast master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 23. "FMKEY183,Fast master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x34 22. "FMKEY182,Fast master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 21. "FMKEY181,Fast master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x34 20. "FMKEY180,Fast master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 19. "FMKEY179,Fast master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x34 18. "FMKEY178,Fast master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 17. "FMKEY177,Fast master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x34 16. "FMKEY176,Fast master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 15. "FMKEY175,Fast master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x34 14. "FMKEY174,Fast master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 13. "FMKEY173,Fast master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x34 12. "FMKEY172,Fast master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 11. "FMKEY171,Fast master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x34 10. "FMKEY170,Fast master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 9. "FMKEY169,Fast master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x34 8. "FMKEY168,Fast master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 7. "FMKEY167,Fast master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x34 6. "FMKEY166,Fast master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 5. "FMKEY165,Fast master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x34 4. "FMKEY164,Fast master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 3. "FMKEY163,Fast master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x34 2. "FMKEY162,Fast master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 1. "FMKEY161,Fast master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x34 0. "FMKEY160,Fast master key bit 160 (i = 31 to 0)" "0,1" line.long 0x38 "MCE_FMKEYR6,MCE fast master key 6" bitfld.long 0x38 31. "FMKEY223,Fast master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x38 30. "FMKEY222,Fast master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 29. "FMKEY221,Fast master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x38 28. "FMKEY220,Fast master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 27. "FMKEY219,Fast master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x38 26. "FMKEY218,Fast master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 25. "FMKEY217,Fast master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x38 24. "FMKEY216,Fast master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 23. "FMKEY215,Fast master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x38 22. "FMKEY214,Fast master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 21. "FMKEY213,Fast master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x38 20. "FMKEY212,Fast master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 19. "FMKEY211,Fast master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x38 18. "FMKEY210,Fast master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 17. "FMKEY209,Fast master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x38 16. "FMKEY208,Fast master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 15. "FMKEY207,Fast master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x38 14. "FMKEY206,Fast master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 13. "FMKEY205,Fast master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x38 12. "FMKEY204,Fast master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 11. "FMKEY203,Fast master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x38 10. "FMKEY202,Fast master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 9. "FMKEY201,Fast master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x38 8. "FMKEY200,Fast master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 7. "FMKEY199,Fast master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x38 6. "FMKEY198,Fast master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 5. "FMKEY197,Fast master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x38 4. "FMKEY196,Fast master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 3. "FMKEY195,Fast master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x38 2. "FMKEY194,Fast master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 1. "FMKEY193,Fast master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x38 0. "FMKEY192,Fast master key bit 192 (i = 31 to 0)" "0,1" line.long 0x3C "MCE_FMKEYR7,MCE fast master key 7" bitfld.long 0x3C 31. "FMKEY255,Fast master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x3C 30. "FMKEY254,Fast master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 29. "FMKEY253,Fast master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x3C 28. "FMKEY252,Fast master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 27. "FMKEY251,Fast master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x3C 26. "FMKEY250,Fast master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 25. "FMKEY249,Fast master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x3C 24. "FMKEY248,Fast master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 23. "FMKEY247,Fast master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x3C 22. "FMKEY246,Fast master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 21. "FMKEY245,Fast master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x3C 20. "FMKEY244,Fast master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 19. "FMKEY243,Fast master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x3C 18. "FMKEY242,Fast master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 17. "FMKEY241,Fast master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x3C 16. "FMKEY240,Fast master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 15. "FMKEY239,Fast master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x3C 14. "FMKEY238,Fast master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 13. "FMKEY237,Fast master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x3C 12. "FMKEY236,Fast master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 11. "FMKEY235,Fast master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x3C 10. "FMKEY234,Fast master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 9. "FMKEY233,Fast master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x3C 8. "FMKEY232,Fast master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 7. "FMKEY231,Fast master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x3C 6. "FMKEY230,Fast master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 5. "FMKEY229,Fast master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x3C 4. "FMKEY228,Fast master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 3. "FMKEY227,Fast master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x3C 2. "FMKEY226,Fast master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 1. "FMKEY225,Fast master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x3C 0. "FMKEY224,Fast master key bit 224 (i = 31 to 0)" "0,1" group.long 0x240++0xB line.long 0x0 "MCE_CC1CFGR,MCE cipher context 1 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC1NR0,MCE cipher context 1 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC1NR1,MCE cipher context 1 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x24C++0xF line.long 0x0 "MCE_CC1KEYR0,MCE cipher context 1 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC1KEYR1,MCE cipher context 1 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC1KEYR2,MCE cipher context 1 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC1KEYR3,MCE cipher context 1 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" group.long 0x270++0xB line.long 0x0 "MCE_CC2CFGR,MCE cipher context 2 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC2NR0,MCE cipher context 2 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC2NR1,MCE cipher context 2 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x27C++0xF line.long 0x0 "MCE_CC2KEYR0,MCE cipher context 2 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC2KEYR1,MCE cipher context 2 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC2KEYR2,MCE cipher context 2 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC2KEYR3,MCE cipher context 2 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" tree.end tree "MCE2" base ad:0x4802BC00 group.long 0x0++0x3 line.long 0x0 "MCE_CR,MCE configuration register" bitfld.long 0x0 4.--5. "CIPHERSEL,Cipher selection" "0: No cipher is selected. Any read (resp. write) to..,1: AES-128 cipher selected for all encrypted regions,2: Noekeon cipher selected for all encrypted regions,3: AES-256 cipher selected for all encrypted regions" bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx and MCE_FMKEYRx registers..,1: Writes to MCE_MKEYRx and MCE_FMKEYRx registers.." newline bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.." rgroup.long 0x4++0x7 line.long 0x0 "MCE_SR,MCE status register" bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCRx all..,1: When ENC bit and BREN are set in any MCE_REGCRx.." bitfld.long 0x0 2. "FMKVALID,Fast master key valid" "0: A valid key has not been written in MCE_FMKEYRx..,1: A valid key has been written in MCE_FMKEYRx.." newline bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.." line.long 0x4 "MCE_IASR,MCE illegal access status register" bitfld.long 0x4 1. "IAEF,Illegal access error flag" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "MCE_IACR,MCE illegal access clear register" bitfld.long 0x0 1. "IAEF,Illegal access error flag clear" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register" bitfld.long 0x0 1. "IAEIE,Illegal access error interrupt enable" "0: Interrupt generation on illegal access errors is..,1: Interrupt generation when an illegal access.." rgroup.long 0x24++0x3 line.long 0x0 "MCE_IADDR,MCE illegal address register" hexmask.long 0x0 0.--31. 1. "IADD,Illegal address" group.long 0x40++0xB line.long 0x0 "MCE_REGCR1,MCE region 1 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR1,MCE start address for region 1 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR1,MCE end address for region 1 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x50++0xB line.long 0x0 "MCE_REGCR2,MCE region 2 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR2,MCE start address for region 2 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR2,MCE end address for region 2 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x60++0xB line.long 0x0 "MCE_REGCR3,MCE region 3 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR3,MCE start address for region 3 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR3,MCE end address for region 3 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x70++0xB line.long 0x0 "MCE_REGCR4,MCE region 4 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR4,MCE start address for region 4 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR4,MCE end address for region 4 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" wgroup.long 0x200++0x3F line.long 0x0 "MCE_MKEYR0,.MCE master key 0" bitfld.long 0x0 31. "MKEY31,Master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x0 30. "MKEY30,Master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 29. "MKEY29,Master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x0 28. "MKEY28,Master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 27. "MKEY27,Master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x0 26. "MKEY26,Master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 25. "MKEY25,Master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x0 24. "MKEY24,Master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 23. "MKEY23,Master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x0 22. "MKEY22,Master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 21. "MKEY21,Master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x0 20. "MKEY20,Master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 19. "MKEY19,Master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x0 18. "MKEY18,Master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 17. "MKEY17,Master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x0 16. "MKEY16,Master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 15. "MKEY15,Master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x0 14. "MKEY14,Master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 13. "MKEY13,Master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x0 12. "MKEY12,Master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 11. "MKEY11,Master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x0 10. "MKEY10,Master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 9. "MKEY9,Master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x0 8. "MKEY8,Master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 7. "MKEY7,Master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x0 6. "MKEY6,Master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 5. "MKEY5,Master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x0 4. "MKEY4,Master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 3. "MKEY3,Master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x0 2. "MKEY2,Master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 1. "MKEY1,Master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x0 0. "MKEY0,Master key bit 0 (i = 31 to 0)" "0,1" line.long 0x4 "MCE_MKEYR1,.MCE master key 1" bitfld.long 0x4 31. "MKEY63,Master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x4 30. "MKEY62,Master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 29. "MKEY61,Master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x4 28. "MKEY60,Master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 27. "MKEY59,Master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x4 26. "MKEY58,Master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 25. "MKEY57,Master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x4 24. "MKEY56,Master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 23. "MKEY55,Master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x4 22. "MKEY54,Master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 21. "MKEY53,Master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x4 20. "MKEY52,Master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 19. "MKEY51,Master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x4 18. "MKEY50,Master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 17. "MKEY49,Master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x4 16. "MKEY48,Master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 15. "MKEY47,Master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x4 14. "MKEY46,Master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 13. "MKEY45,Master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x4 12. "MKEY44,Master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 11. "MKEY43,Master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x4 10. "MKEY42,Master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 9. "MKEY41,Master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x4 8. "MKEY40,Master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 7. "MKEY39,Master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x4 6. "MKEY38,Master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 5. "MKEY37,Master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x4 4. "MKEY36,Master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 3. "MKEY35,Master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x4 2. "MKEY34,Master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 1. "MKEY33,Master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x4 0. "MKEY32,Master key bit 32 (i = 31 to 0)" "0,1" line.long 0x8 "MCE_MKEYR2,.MCE master key 2" bitfld.long 0x8 31. "MKEY95,Master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x8 30. "MKEY94,Master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 29. "MKEY93,Master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x8 28. "MKEY92,Master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 27. "MKEY91,Master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x8 26. "MKEY90,Master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 25. "MKEY89,Master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x8 24. "MKEY88,Master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 23. "MKEY87,Master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x8 22. "MKEY86,Master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 21. "MKEY85,Master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x8 20. "MKEY84,Master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 19. "MKEY83,Master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x8 18. "MKEY82,Master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 17. "MKEY81,Master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x8 16. "MKEY80,Master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 15. "MKEY79,Master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x8 14. "MKEY78,Master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 13. "MKEY77,Master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x8 12. "MKEY76,Master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 11. "MKEY75,Master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x8 10. "MKEY74,Master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 9. "MKEY73,Master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x8 8. "MKEY72,Master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 7. "MKEY71,Master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x8 6. "MKEY70,Master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 5. "MKEY69,Master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x8 4. "MKEY68,Master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 3. "MKEY67,Master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x8 2. "MKEY66,Master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 1. "MKEY65,Master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x8 0. "MKEY64,Master key bit 64 (i = 31 to 0)" "0,1" line.long 0xC "MCE_MKEYR3,.MCE master key 3" bitfld.long 0xC 31. "MKEY127,Master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0xC 30. "MKEY126,Master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 29. "MKEY125,Master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0xC 28. "MKEY124,Master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 27. "MKEY123,Master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0xC 26. "MKEY122,Master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 25. "MKEY121,Master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0xC 24. "MKEY120,Master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 23. "MKEY119,Master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0xC 22. "MKEY118,Master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 21. "MKEY117,Master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0xC 20. "MKEY116,Master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 19. "MKEY115,Master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0xC 18. "MKEY114,Master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 17. "MKEY113,Master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0xC 16. "MKEY112,Master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 15. "MKEY111,Master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0xC 14. "MKEY110,Master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 13. "MKEY109,Master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0xC 12. "MKEY108,Master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 11. "MKEY107,Master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0xC 10. "MKEY106,Master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 9. "MKEY105,Master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0xC 8. "MKEY104,Master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 7. "MKEY103,Master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0xC 6. "MKEY102,Master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 5. "MKEY101,Master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0xC 4. "MKEY100,Master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 3. "MKEY99,Master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0xC 2. "MKEY98,Master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 1. "MKEY97,Master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0xC 0. "MKEY96,Master key bit 96 (i = 31 to 0)" "0,1" line.long 0x10 "MCE_MKEYR4,.MCE master key 4" bitfld.long 0x10 31. "MKEY159,Master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x10 30. "MKEY158,Master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 29. "MKEY157,Master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x10 28. "MKEY156,Master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 27. "MKEY155,Master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x10 26. "MKEY154,Master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 25. "MKEY153,Master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x10 24. "MKEY152,Master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 23. "MKEY151,Master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x10 22. "MKEY150,Master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 21. "MKEY149,Master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x10 20. "MKEY148,Master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 19. "MKEY147,Master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x10 18. "MKEY146,Master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 17. "MKEY145,Master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x10 16. "MKEY144,Master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 15. "MKEY143,Master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x10 14. "MKEY142,Master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 13. "MKEY141,Master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x10 12. "MKEY140,Master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 11. "MKEY139,Master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x10 10. "MKEY138,Master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 9. "MKEY137,Master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x10 8. "MKEY136,Master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 7. "MKEY135,Master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x10 6. "MKEY134,Master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 5. "MKEY133,Master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x10 4. "MKEY132,Master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 3. "MKEY131,Master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x10 2. "MKEY130,Master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 1. "MKEY129,Master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x10 0. "MKEY128,Master key bit 128 (i = 31 to 0)" "0,1" line.long 0x14 "MCE_MKEYR5,.MCE master key 5" bitfld.long 0x14 31. "MKEY191,Master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x14 30. "MKEY190,Master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 29. "MKEY189,Master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x14 28. "MKEY188,Master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 27. "MKEY187,Master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x14 26. "MKEY186,Master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 25. "MKEY185,Master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x14 24. "MKEY184,Master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 23. "MKEY183,Master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x14 22. "MKEY182,Master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 21. "MKEY181,Master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x14 20. "MKEY180,Master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 19. "MKEY179,Master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x14 18. "MKEY178,Master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 17. "MKEY177,Master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x14 16. "MKEY176,Master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 15. "MKEY175,Master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x14 14. "MKEY174,Master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 13. "MKEY173,Master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x14 12. "MKEY172,Master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 11. "MKEY171,Master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x14 10. "MKEY170,Master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 9. "MKEY169,Master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x14 8. "MKEY168,Master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 7. "MKEY167,Master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x14 6. "MKEY166,Master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 5. "MKEY165,Master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x14 4. "MKEY164,Master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 3. "MKEY163,Master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x14 2. "MKEY162,Master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 1. "MKEY161,Master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x14 0. "MKEY160,Master key bit 160 (i = 31 to 0)" "0,1" line.long 0x18 "MCE_MKEYR6,.MCE master key 6" bitfld.long 0x18 31. "MKEY223,Master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x18 30. "MKEY222,Master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 29. "MKEY221,Master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x18 28. "MKEY220,Master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 27. "MKEY219,Master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x18 26. "MKEY218,Master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 25. "MKEY217,Master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x18 24. "MKEY216,Master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 23. "MKEY215,Master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x18 22. "MKEY214,Master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 21. "MKEY213,Master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x18 20. "MKEY212,Master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 19. "MKEY211,Master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x18 18. "MKEY210,Master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 17. "MKEY209,Master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x18 16. "MKEY208,Master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 15. "MKEY207,Master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x18 14. "MKEY206,Master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 13. "MKEY205,Master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x18 12. "MKEY204,Master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 11. "MKEY203,Master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x18 10. "MKEY202,Master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 9. "MKEY201,Master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x18 8. "MKEY200,Master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 7. "MKEY199,Master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x18 6. "MKEY198,Master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 5. "MKEY197,Master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x18 4. "MKEY196,Master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 3. "MKEY195,Master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x18 2. "MKEY194,Master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 1. "MKEY193,Master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x18 0. "MKEY192,Master key bit 192 (i = 31 to 0)" "0,1" line.long 0x1C "MCE_MKEYR7,.MCE master key 7" bitfld.long 0x1C 31. "MKEY255,Master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x1C 30. "MKEY254,Master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 29. "MKEY253,Master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x1C 28. "MKEY252,Master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 27. "MKEY251,Master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x1C 26. "MKEY250,Master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 25. "MKEY249,Master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x1C 24. "MKEY248,Master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 23. "MKEY247,Master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x1C 22. "MKEY246,Master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 21. "MKEY245,Master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x1C 20. "MKEY244,Master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 19. "MKEY243,Master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x1C 18. "MKEY242,Master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 17. "MKEY241,Master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x1C 16. "MKEY240,Master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 15. "MKEY239,Master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x1C 14. "MKEY238,Master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 13. "MKEY237,Master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x1C 12. "MKEY236,Master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 11. "MKEY235,Master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x1C 10. "MKEY234,Master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 9. "MKEY233,Master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x1C 8. "MKEY232,Master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 7. "MKEY231,Master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x1C 6. "MKEY230,Master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 5. "MKEY229,Master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x1C 4. "MKEY228,Master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 3. "MKEY227,Master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x1C 2. "MKEY226,Master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 1. "MKEY225,Master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x1C 0. "MKEY224,Master key bit 224 (i = 31 to 0)" "0,1" line.long 0x20 "MCE_FMKEYR0,MCE fast master key 0" bitfld.long 0x20 31. "FMKEY31,Fast master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x20 30. "FMKEY30,Fast master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 29. "FMKEY29,Fast master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x20 28. "FMKEY28,Fast master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 27. "FMKEY27,Fast master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x20 26. "FMKEY26,Fast master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 25. "FMKEY25,Fast master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x20 24. "FMKEY24,Fast master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 23. "FMKEY23,Fast master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x20 22. "FMKEY22,Fast master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 21. "FMKEY21,Fast master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x20 20. "FMKEY20,Fast master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 19. "FMKEY19,Fast master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x20 18. "FMKEY18,Fast master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 17. "FMKEY17,Fast master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x20 16. "FMKEY16,Fast master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 15. "FMKEY15,Fast master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x20 14. "FMKEY14,Fast master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 13. "FMKEY13,Fast master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x20 12. "FMKEY12,Fast master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 11. "FMKEY11,Fast master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x20 10. "FMKEY10,Fast master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 9. "FMKEY9,Fast master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x20 8. "FMKEY8,Fast master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 7. "FMKEY7,Fast master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x20 6. "FMKEY6,Fast master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 5. "FMKEY5,Fast master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x20 4. "FMKEY4,Fast master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 3. "FMKEY3,Fast master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x20 2. "FMKEY2,Fast master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 1. "FMKEY1,Fast master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x20 0. "FMKEY0,Fast master key bit 0 (i = 31 to 0)" "0,1" line.long 0x24 "MCE_FMKEYR1,MCE fast master key 1" bitfld.long 0x24 31. "FMKEY63,Fast master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x24 30. "FMKEY62,Fast master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 29. "FMKEY61,Fast master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x24 28. "FMKEY60,Fast master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 27. "FMKEY59,Fast master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x24 26. "FMKEY58,Fast master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 25. "FMKEY57,Fast master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x24 24. "FMKEY56,Fast master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 23. "FMKEY55,Fast master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x24 22. "FMKEY54,Fast master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 21. "FMKEY53,Fast master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x24 20. "FMKEY52,Fast master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 19. "FMKEY51,Fast master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x24 18. "FMKEY50,Fast master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 17. "FMKEY49,Fast master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x24 16. "FMKEY48,Fast master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 15. "FMKEY47,Fast master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x24 14. "FMKEY46,Fast master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 13. "FMKEY45,Fast master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x24 12. "FMKEY44,Fast master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 11. "FMKEY43,Fast master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x24 10. "FMKEY42,Fast master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 9. "FMKEY41,Fast master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x24 8. "FMKEY40,Fast master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 7. "FMKEY39,Fast master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x24 6. "FMKEY38,Fast master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 5. "FMKEY37,Fast master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x24 4. "FMKEY36,Fast master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 3. "FMKEY35,Fast master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x24 2. "FMKEY34,Fast master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 1. "FMKEY33,Fast master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x24 0. "FMKEY32,Fast master key bit 32 (i = 31 to 0)" "0,1" line.long 0x28 "MCE_FMKEYR2,MCE fast master key 2" bitfld.long 0x28 31. "FMKEY95,Fast master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x28 30. "FMKEY94,Fast master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 29. "FMKEY93,Fast master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x28 28. "FMKEY92,Fast master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 27. "FMKEY91,Fast master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x28 26. "FMKEY90,Fast master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 25. "FMKEY89,Fast master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x28 24. "FMKEY88,Fast master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 23. "FMKEY87,Fast master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x28 22. "FMKEY86,Fast master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 21. "FMKEY85,Fast master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x28 20. "FMKEY84,Fast master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 19. "FMKEY83,Fast master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x28 18. "FMKEY82,Fast master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 17. "FMKEY81,Fast master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x28 16. "FMKEY80,Fast master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 15. "FMKEY79,Fast master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x28 14. "FMKEY78,Fast master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 13. "FMKEY77,Fast master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x28 12. "FMKEY76,Fast master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 11. "FMKEY75,Fast master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x28 10. "FMKEY74,Fast master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 9. "FMKEY73,Fast master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x28 8. "FMKEY72,Fast master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 7. "FMKEY71,Fast master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x28 6. "FMKEY70,Fast master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 5. "FMKEY69,Fast master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x28 4. "FMKEY68,Fast master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 3. "FMKEY67,Fast master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x28 2. "FMKEY66,Fast master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 1. "FMKEY65,Fast master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x28 0. "FMKEY64,Fast master key bit 64 (i = 31 to 0)" "0,1" line.long 0x2C "MCE_FMKEYR3,MCE fast master key 3" bitfld.long 0x2C 31. "FMKEY127,Fast master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0x2C 30. "FMKEY126,Fast master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 29. "FMKEY125,Fast master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0x2C 28. "FMKEY124,Fast master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 27. "FMKEY123,Fast master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0x2C 26. "FMKEY122,Fast master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 25. "FMKEY121,Fast master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0x2C 24. "FMKEY120,Fast master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 23. "FMKEY119,Fast master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0x2C 22. "FMKEY118,Fast master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 21. "FMKEY117,Fast master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0x2C 20. "FMKEY116,Fast master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 19. "FMKEY115,Fast master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0x2C 18. "FMKEY114,Fast master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 17. "FMKEY113,Fast master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0x2C 16. "FMKEY112,Fast master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 15. "FMKEY111,Fast master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0x2C 14. "FMKEY110,Fast master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 13. "FMKEY109,Fast master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0x2C 12. "FMKEY108,Fast master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 11. "FMKEY107,Fast master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0x2C 10. "FMKEY106,Fast master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 9. "FMKEY105,Fast master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0x2C 8. "FMKEY104,Fast master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 7. "FMKEY103,Fast master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0x2C 6. "FMKEY102,Fast master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 5. "FMKEY101,Fast master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0x2C 4. "FMKEY100,Fast master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 3. "FMKEY99,Fast master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0x2C 2. "FMKEY98,Fast master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 1. "FMKEY97,Fast master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0x2C 0. "FMKEY96,Fast master key bit 96 (i = 31 to 0)" "0,1" line.long 0x30 "MCE_FMKEYR4,MCE fast master key 4" bitfld.long 0x30 31. "FMKEY159,Fast master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x30 30. "FMKEY158,Fast master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 29. "FMKEY157,Fast master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x30 28. "FMKEY156,Fast master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 27. "FMKEY155,Fast master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x30 26. "FMKEY154,Fast master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 25. "FMKEY153,Fast master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x30 24. "FMKEY152,Fast master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 23. "FMKEY151,Fast master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x30 22. "FMKEY150,Fast master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 21. "FMKEY149,Fast master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x30 20. "FMKEY148,Fast master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 19. "FMKEY147,Fast master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x30 18. "FMKEY146,Fast master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 17. "FMKEY145,Fast master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x30 16. "FMKEY144,Fast master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 15. "FMKEY143,Fast master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x30 14. "FMKEY142,Fast master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 13. "FMKEY141,Fast master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x30 12. "FMKEY140,Fast master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 11. "FMKEY139,Fast master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x30 10. "FMKEY138,Fast master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 9. "FMKEY137,Fast master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x30 8. "FMKEY136,Fast master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 7. "FMKEY135,Fast master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x30 6. "FMKEY134,Fast master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 5. "FMKEY133,Fast master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x30 4. "FMKEY132,Fast master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 3. "FMKEY131,Fast master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x30 2. "FMKEY130,Fast master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 1. "FMKEY129,Fast master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x30 0. "FMKEY128,Fast master key bit 128 (i = 31 to 0)" "0,1" line.long 0x34 "MCE_FMKEYR5,MCE fast master key 5" bitfld.long 0x34 31. "FMKEY191,Fast master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x34 30. "FMKEY190,Fast master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 29. "FMKEY189,Fast master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x34 28. "FMKEY188,Fast master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 27. "FMKEY187,Fast master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x34 26. "FMKEY186,Fast master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 25. "FMKEY185,Fast master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x34 24. "FMKEY184,Fast master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 23. "FMKEY183,Fast master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x34 22. "FMKEY182,Fast master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 21. "FMKEY181,Fast master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x34 20. "FMKEY180,Fast master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 19. "FMKEY179,Fast master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x34 18. "FMKEY178,Fast master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 17. "FMKEY177,Fast master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x34 16. "FMKEY176,Fast master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 15. "FMKEY175,Fast master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x34 14. "FMKEY174,Fast master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 13. "FMKEY173,Fast master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x34 12. "FMKEY172,Fast master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 11. "FMKEY171,Fast master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x34 10. "FMKEY170,Fast master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 9. "FMKEY169,Fast master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x34 8. "FMKEY168,Fast master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 7. "FMKEY167,Fast master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x34 6. "FMKEY166,Fast master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 5. "FMKEY165,Fast master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x34 4. "FMKEY164,Fast master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 3. "FMKEY163,Fast master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x34 2. "FMKEY162,Fast master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 1. "FMKEY161,Fast master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x34 0. "FMKEY160,Fast master key bit 160 (i = 31 to 0)" "0,1" line.long 0x38 "MCE_FMKEYR6,MCE fast master key 6" bitfld.long 0x38 31. "FMKEY223,Fast master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x38 30. "FMKEY222,Fast master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 29. "FMKEY221,Fast master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x38 28. "FMKEY220,Fast master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 27. "FMKEY219,Fast master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x38 26. "FMKEY218,Fast master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 25. "FMKEY217,Fast master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x38 24. "FMKEY216,Fast master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 23. "FMKEY215,Fast master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x38 22. "FMKEY214,Fast master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 21. "FMKEY213,Fast master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x38 20. "FMKEY212,Fast master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 19. "FMKEY211,Fast master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x38 18. "FMKEY210,Fast master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 17. "FMKEY209,Fast master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x38 16. "FMKEY208,Fast master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 15. "FMKEY207,Fast master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x38 14. "FMKEY206,Fast master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 13. "FMKEY205,Fast master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x38 12. "FMKEY204,Fast master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 11. "FMKEY203,Fast master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x38 10. "FMKEY202,Fast master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 9. "FMKEY201,Fast master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x38 8. "FMKEY200,Fast master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 7. "FMKEY199,Fast master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x38 6. "FMKEY198,Fast master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 5. "FMKEY197,Fast master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x38 4. "FMKEY196,Fast master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 3. "FMKEY195,Fast master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x38 2. "FMKEY194,Fast master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 1. "FMKEY193,Fast master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x38 0. "FMKEY192,Fast master key bit 192 (i = 31 to 0)" "0,1" line.long 0x3C "MCE_FMKEYR7,MCE fast master key 7" bitfld.long 0x3C 31. "FMKEY255,Fast master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x3C 30. "FMKEY254,Fast master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 29. "FMKEY253,Fast master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x3C 28. "FMKEY252,Fast master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 27. "FMKEY251,Fast master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x3C 26. "FMKEY250,Fast master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 25. "FMKEY249,Fast master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x3C 24. "FMKEY248,Fast master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 23. "FMKEY247,Fast master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x3C 22. "FMKEY246,Fast master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 21. "FMKEY245,Fast master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x3C 20. "FMKEY244,Fast master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 19. "FMKEY243,Fast master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x3C 18. "FMKEY242,Fast master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 17. "FMKEY241,Fast master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x3C 16. "FMKEY240,Fast master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 15. "FMKEY239,Fast master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x3C 14. "FMKEY238,Fast master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 13. "FMKEY237,Fast master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x3C 12. "FMKEY236,Fast master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 11. "FMKEY235,Fast master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x3C 10. "FMKEY234,Fast master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 9. "FMKEY233,Fast master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x3C 8. "FMKEY232,Fast master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 7. "FMKEY231,Fast master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x3C 6. "FMKEY230,Fast master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 5. "FMKEY229,Fast master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x3C 4. "FMKEY228,Fast master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 3. "FMKEY227,Fast master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x3C 2. "FMKEY226,Fast master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 1. "FMKEY225,Fast master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x3C 0. "FMKEY224,Fast master key bit 224 (i = 31 to 0)" "0,1" group.long 0x240++0xB line.long 0x0 "MCE_CC1CFGR,MCE cipher context 1 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC1NR0,MCE cipher context 1 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC1NR1,MCE cipher context 1 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x24C++0xF line.long 0x0 "MCE_CC1KEYR0,MCE cipher context 1 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC1KEYR1,MCE cipher context 1 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC1KEYR2,MCE cipher context 1 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC1KEYR3,MCE cipher context 1 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" group.long 0x270++0xB line.long 0x0 "MCE_CC2CFGR,MCE cipher context 2 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC2NR0,MCE cipher context 2 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC2NR1,MCE cipher context 2 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x27C++0xF line.long 0x0 "MCE_CC2KEYR0,MCE cipher context 2 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC2KEYR1,MCE cipher context 2 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC2KEYR2,MCE cipher context 2 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC2KEYR3,MCE cipher context 2 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" tree.end tree "MCE2_S" base ad:0x5802BC00 group.long 0x0++0x3 line.long 0x0 "MCE_CR,MCE configuration register" bitfld.long 0x0 4.--5. "CIPHERSEL,Cipher selection" "0: No cipher is selected. Any read (resp. write) to..,1: AES-128 cipher selected for all encrypted regions,2: Noekeon cipher selected for all encrypted regions,3: AES-256 cipher selected for all encrypted regions" bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx and MCE_FMKEYRx registers..,1: Writes to MCE_MKEYRx and MCE_FMKEYRx registers.." newline bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.." rgroup.long 0x4++0x7 line.long 0x0 "MCE_SR,MCE status register" bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCRx all..,1: When ENC bit and BREN are set in any MCE_REGCRx.." bitfld.long 0x0 2. "FMKVALID,Fast master key valid" "0: A valid key has not been written in MCE_FMKEYRx..,1: A valid key has been written in MCE_FMKEYRx.." newline bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.." line.long 0x4 "MCE_IASR,MCE illegal access status register" bitfld.long 0x4 1. "IAEF,Illegal access error flag" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "MCE_IACR,MCE illegal access clear register" bitfld.long 0x0 1. "IAEF,Illegal access error flag clear" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register" bitfld.long 0x0 1. "IAEIE,Illegal access error interrupt enable" "0: Interrupt generation on illegal access errors is..,1: Interrupt generation when an illegal access.." rgroup.long 0x24++0x3 line.long 0x0 "MCE_IADDR,MCE illegal address register" hexmask.long 0x0 0.--31. 1. "IADD,Illegal address" group.long 0x40++0xB line.long 0x0 "MCE_REGCR1,MCE region 1 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR1,MCE start address for region 1 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR1,MCE end address for region 1 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x50++0xB line.long 0x0 "MCE_REGCR2,MCE region 2 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR2,MCE start address for region 2 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR2,MCE end address for region 2 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x60++0xB line.long 0x0 "MCE_REGCR3,MCE region 3 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR3,MCE start address for region 3 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR3,MCE end address for region 3 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x70++0xB line.long 0x0 "MCE_REGCR4,MCE region 4 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR4,MCE start address for region 4 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR4,MCE end address for region 4 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" wgroup.long 0x200++0x3F line.long 0x0 "MCE_MKEYR0,.MCE master key 0" bitfld.long 0x0 31. "MKEY31,Master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x0 30. "MKEY30,Master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 29. "MKEY29,Master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x0 28. "MKEY28,Master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 27. "MKEY27,Master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x0 26. "MKEY26,Master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 25. "MKEY25,Master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x0 24. "MKEY24,Master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 23. "MKEY23,Master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x0 22. "MKEY22,Master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 21. "MKEY21,Master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x0 20. "MKEY20,Master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 19. "MKEY19,Master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x0 18. "MKEY18,Master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 17. "MKEY17,Master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x0 16. "MKEY16,Master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 15. "MKEY15,Master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x0 14. "MKEY14,Master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 13. "MKEY13,Master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x0 12. "MKEY12,Master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 11. "MKEY11,Master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x0 10. "MKEY10,Master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 9. "MKEY9,Master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x0 8. "MKEY8,Master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 7. "MKEY7,Master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x0 6. "MKEY6,Master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 5. "MKEY5,Master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x0 4. "MKEY4,Master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 3. "MKEY3,Master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x0 2. "MKEY2,Master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 1. "MKEY1,Master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x0 0. "MKEY0,Master key bit 0 (i = 31 to 0)" "0,1" line.long 0x4 "MCE_MKEYR1,.MCE master key 1" bitfld.long 0x4 31. "MKEY63,Master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x4 30. "MKEY62,Master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 29. "MKEY61,Master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x4 28. "MKEY60,Master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 27. "MKEY59,Master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x4 26. "MKEY58,Master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 25. "MKEY57,Master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x4 24. "MKEY56,Master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 23. "MKEY55,Master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x4 22. "MKEY54,Master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 21. "MKEY53,Master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x4 20. "MKEY52,Master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 19. "MKEY51,Master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x4 18. "MKEY50,Master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 17. "MKEY49,Master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x4 16. "MKEY48,Master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 15. "MKEY47,Master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x4 14. "MKEY46,Master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 13. "MKEY45,Master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x4 12. "MKEY44,Master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 11. "MKEY43,Master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x4 10. "MKEY42,Master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 9. "MKEY41,Master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x4 8. "MKEY40,Master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 7. "MKEY39,Master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x4 6. "MKEY38,Master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 5. "MKEY37,Master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x4 4. "MKEY36,Master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 3. "MKEY35,Master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x4 2. "MKEY34,Master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 1. "MKEY33,Master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x4 0. "MKEY32,Master key bit 32 (i = 31 to 0)" "0,1" line.long 0x8 "MCE_MKEYR2,.MCE master key 2" bitfld.long 0x8 31. "MKEY95,Master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x8 30. "MKEY94,Master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 29. "MKEY93,Master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x8 28. "MKEY92,Master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 27. "MKEY91,Master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x8 26. "MKEY90,Master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 25. "MKEY89,Master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x8 24. "MKEY88,Master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 23. "MKEY87,Master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x8 22. "MKEY86,Master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 21. "MKEY85,Master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x8 20. "MKEY84,Master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 19. "MKEY83,Master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x8 18. "MKEY82,Master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 17. "MKEY81,Master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x8 16. "MKEY80,Master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 15. "MKEY79,Master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x8 14. "MKEY78,Master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 13. "MKEY77,Master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x8 12. "MKEY76,Master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 11. "MKEY75,Master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x8 10. "MKEY74,Master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 9. "MKEY73,Master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x8 8. "MKEY72,Master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 7. "MKEY71,Master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x8 6. "MKEY70,Master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 5. "MKEY69,Master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x8 4. "MKEY68,Master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 3. "MKEY67,Master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x8 2. "MKEY66,Master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 1. "MKEY65,Master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x8 0. "MKEY64,Master key bit 64 (i = 31 to 0)" "0,1" line.long 0xC "MCE_MKEYR3,.MCE master key 3" bitfld.long 0xC 31. "MKEY127,Master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0xC 30. "MKEY126,Master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 29. "MKEY125,Master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0xC 28. "MKEY124,Master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 27. "MKEY123,Master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0xC 26. "MKEY122,Master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 25. "MKEY121,Master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0xC 24. "MKEY120,Master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 23. "MKEY119,Master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0xC 22. "MKEY118,Master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 21. "MKEY117,Master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0xC 20. "MKEY116,Master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 19. "MKEY115,Master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0xC 18. "MKEY114,Master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 17. "MKEY113,Master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0xC 16. "MKEY112,Master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 15. "MKEY111,Master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0xC 14. "MKEY110,Master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 13. "MKEY109,Master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0xC 12. "MKEY108,Master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 11. "MKEY107,Master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0xC 10. "MKEY106,Master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 9. "MKEY105,Master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0xC 8. "MKEY104,Master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 7. "MKEY103,Master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0xC 6. "MKEY102,Master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 5. "MKEY101,Master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0xC 4. "MKEY100,Master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 3. "MKEY99,Master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0xC 2. "MKEY98,Master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 1. "MKEY97,Master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0xC 0. "MKEY96,Master key bit 96 (i = 31 to 0)" "0,1" line.long 0x10 "MCE_MKEYR4,.MCE master key 4" bitfld.long 0x10 31. "MKEY159,Master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x10 30. "MKEY158,Master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 29. "MKEY157,Master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x10 28. "MKEY156,Master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 27. "MKEY155,Master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x10 26. "MKEY154,Master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 25. "MKEY153,Master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x10 24. "MKEY152,Master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 23. "MKEY151,Master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x10 22. "MKEY150,Master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 21. "MKEY149,Master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x10 20. "MKEY148,Master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 19. "MKEY147,Master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x10 18. "MKEY146,Master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 17. "MKEY145,Master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x10 16. "MKEY144,Master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 15. "MKEY143,Master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x10 14. "MKEY142,Master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 13. "MKEY141,Master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x10 12. "MKEY140,Master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 11. "MKEY139,Master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x10 10. "MKEY138,Master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 9. "MKEY137,Master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x10 8. "MKEY136,Master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 7. "MKEY135,Master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x10 6. "MKEY134,Master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 5. "MKEY133,Master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x10 4. "MKEY132,Master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 3. "MKEY131,Master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x10 2. "MKEY130,Master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 1. "MKEY129,Master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x10 0. "MKEY128,Master key bit 128 (i = 31 to 0)" "0,1" line.long 0x14 "MCE_MKEYR5,.MCE master key 5" bitfld.long 0x14 31. "MKEY191,Master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x14 30. "MKEY190,Master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 29. "MKEY189,Master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x14 28. "MKEY188,Master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 27. "MKEY187,Master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x14 26. "MKEY186,Master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 25. "MKEY185,Master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x14 24. "MKEY184,Master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 23. "MKEY183,Master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x14 22. "MKEY182,Master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 21. "MKEY181,Master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x14 20. "MKEY180,Master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 19. "MKEY179,Master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x14 18. "MKEY178,Master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 17. "MKEY177,Master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x14 16. "MKEY176,Master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 15. "MKEY175,Master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x14 14. "MKEY174,Master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 13. "MKEY173,Master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x14 12. "MKEY172,Master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 11. "MKEY171,Master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x14 10. "MKEY170,Master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 9. "MKEY169,Master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x14 8. "MKEY168,Master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 7. "MKEY167,Master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x14 6. "MKEY166,Master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 5. "MKEY165,Master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x14 4. "MKEY164,Master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 3. "MKEY163,Master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x14 2. "MKEY162,Master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 1. "MKEY161,Master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x14 0. "MKEY160,Master key bit 160 (i = 31 to 0)" "0,1" line.long 0x18 "MCE_MKEYR6,.MCE master key 6" bitfld.long 0x18 31. "MKEY223,Master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x18 30. "MKEY222,Master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 29. "MKEY221,Master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x18 28. "MKEY220,Master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 27. "MKEY219,Master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x18 26. "MKEY218,Master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 25. "MKEY217,Master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x18 24. "MKEY216,Master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 23. "MKEY215,Master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x18 22. "MKEY214,Master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 21. "MKEY213,Master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x18 20. "MKEY212,Master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 19. "MKEY211,Master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x18 18. "MKEY210,Master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 17. "MKEY209,Master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x18 16. "MKEY208,Master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 15. "MKEY207,Master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x18 14. "MKEY206,Master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 13. "MKEY205,Master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x18 12. "MKEY204,Master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 11. "MKEY203,Master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x18 10. "MKEY202,Master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 9. "MKEY201,Master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x18 8. "MKEY200,Master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 7. "MKEY199,Master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x18 6. "MKEY198,Master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 5. "MKEY197,Master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x18 4. "MKEY196,Master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 3. "MKEY195,Master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x18 2. "MKEY194,Master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 1. "MKEY193,Master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x18 0. "MKEY192,Master key bit 192 (i = 31 to 0)" "0,1" line.long 0x1C "MCE_MKEYR7,.MCE master key 7" bitfld.long 0x1C 31. "MKEY255,Master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x1C 30. "MKEY254,Master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 29. "MKEY253,Master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x1C 28. "MKEY252,Master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 27. "MKEY251,Master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x1C 26. "MKEY250,Master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 25. "MKEY249,Master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x1C 24. "MKEY248,Master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 23. "MKEY247,Master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x1C 22. "MKEY246,Master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 21. "MKEY245,Master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x1C 20. "MKEY244,Master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 19. "MKEY243,Master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x1C 18. "MKEY242,Master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 17. "MKEY241,Master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x1C 16. "MKEY240,Master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 15. "MKEY239,Master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x1C 14. "MKEY238,Master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 13. "MKEY237,Master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x1C 12. "MKEY236,Master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 11. "MKEY235,Master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x1C 10. "MKEY234,Master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 9. "MKEY233,Master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x1C 8. "MKEY232,Master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 7. "MKEY231,Master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x1C 6. "MKEY230,Master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 5. "MKEY229,Master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x1C 4. "MKEY228,Master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 3. "MKEY227,Master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x1C 2. "MKEY226,Master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 1. "MKEY225,Master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x1C 0. "MKEY224,Master key bit 224 (i = 31 to 0)" "0,1" line.long 0x20 "MCE_FMKEYR0,MCE fast master key 0" bitfld.long 0x20 31. "FMKEY31,Fast master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x20 30. "FMKEY30,Fast master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 29. "FMKEY29,Fast master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x20 28. "FMKEY28,Fast master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 27. "FMKEY27,Fast master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x20 26. "FMKEY26,Fast master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 25. "FMKEY25,Fast master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x20 24. "FMKEY24,Fast master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 23. "FMKEY23,Fast master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x20 22. "FMKEY22,Fast master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 21. "FMKEY21,Fast master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x20 20. "FMKEY20,Fast master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 19. "FMKEY19,Fast master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x20 18. "FMKEY18,Fast master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 17. "FMKEY17,Fast master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x20 16. "FMKEY16,Fast master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 15. "FMKEY15,Fast master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x20 14. "FMKEY14,Fast master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 13. "FMKEY13,Fast master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x20 12. "FMKEY12,Fast master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 11. "FMKEY11,Fast master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x20 10. "FMKEY10,Fast master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 9. "FMKEY9,Fast master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x20 8. "FMKEY8,Fast master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 7. "FMKEY7,Fast master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x20 6. "FMKEY6,Fast master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 5. "FMKEY5,Fast master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x20 4. "FMKEY4,Fast master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 3. "FMKEY3,Fast master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x20 2. "FMKEY2,Fast master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 1. "FMKEY1,Fast master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x20 0. "FMKEY0,Fast master key bit 0 (i = 31 to 0)" "0,1" line.long 0x24 "MCE_FMKEYR1,MCE fast master key 1" bitfld.long 0x24 31. "FMKEY63,Fast master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x24 30. "FMKEY62,Fast master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 29. "FMKEY61,Fast master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x24 28. "FMKEY60,Fast master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 27. "FMKEY59,Fast master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x24 26. "FMKEY58,Fast master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 25. "FMKEY57,Fast master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x24 24. "FMKEY56,Fast master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 23. "FMKEY55,Fast master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x24 22. "FMKEY54,Fast master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 21. "FMKEY53,Fast master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x24 20. "FMKEY52,Fast master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 19. "FMKEY51,Fast master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x24 18. "FMKEY50,Fast master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 17. "FMKEY49,Fast master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x24 16. "FMKEY48,Fast master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 15. "FMKEY47,Fast master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x24 14. "FMKEY46,Fast master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 13. "FMKEY45,Fast master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x24 12. "FMKEY44,Fast master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 11. "FMKEY43,Fast master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x24 10. "FMKEY42,Fast master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 9. "FMKEY41,Fast master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x24 8. "FMKEY40,Fast master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 7. "FMKEY39,Fast master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x24 6. "FMKEY38,Fast master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 5. "FMKEY37,Fast master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x24 4. "FMKEY36,Fast master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 3. "FMKEY35,Fast master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x24 2. "FMKEY34,Fast master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 1. "FMKEY33,Fast master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x24 0. "FMKEY32,Fast master key bit 32 (i = 31 to 0)" "0,1" line.long 0x28 "MCE_FMKEYR2,MCE fast master key 2" bitfld.long 0x28 31. "FMKEY95,Fast master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x28 30. "FMKEY94,Fast master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 29. "FMKEY93,Fast master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x28 28. "FMKEY92,Fast master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 27. "FMKEY91,Fast master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x28 26. "FMKEY90,Fast master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 25. "FMKEY89,Fast master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x28 24. "FMKEY88,Fast master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 23. "FMKEY87,Fast master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x28 22. "FMKEY86,Fast master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 21. "FMKEY85,Fast master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x28 20. "FMKEY84,Fast master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 19. "FMKEY83,Fast master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x28 18. "FMKEY82,Fast master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 17. "FMKEY81,Fast master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x28 16. "FMKEY80,Fast master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 15. "FMKEY79,Fast master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x28 14. "FMKEY78,Fast master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 13. "FMKEY77,Fast master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x28 12. "FMKEY76,Fast master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 11. "FMKEY75,Fast master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x28 10. "FMKEY74,Fast master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 9. "FMKEY73,Fast master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x28 8. "FMKEY72,Fast master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 7. "FMKEY71,Fast master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x28 6. "FMKEY70,Fast master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 5. "FMKEY69,Fast master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x28 4. "FMKEY68,Fast master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 3. "FMKEY67,Fast master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x28 2. "FMKEY66,Fast master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 1. "FMKEY65,Fast master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x28 0. "FMKEY64,Fast master key bit 64 (i = 31 to 0)" "0,1" line.long 0x2C "MCE_FMKEYR3,MCE fast master key 3" bitfld.long 0x2C 31. "FMKEY127,Fast master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0x2C 30. "FMKEY126,Fast master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 29. "FMKEY125,Fast master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0x2C 28. "FMKEY124,Fast master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 27. "FMKEY123,Fast master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0x2C 26. "FMKEY122,Fast master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 25. "FMKEY121,Fast master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0x2C 24. "FMKEY120,Fast master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 23. "FMKEY119,Fast master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0x2C 22. "FMKEY118,Fast master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 21. "FMKEY117,Fast master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0x2C 20. "FMKEY116,Fast master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 19. "FMKEY115,Fast master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0x2C 18. "FMKEY114,Fast master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 17. "FMKEY113,Fast master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0x2C 16. "FMKEY112,Fast master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 15. "FMKEY111,Fast master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0x2C 14. "FMKEY110,Fast master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 13. "FMKEY109,Fast master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0x2C 12. "FMKEY108,Fast master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 11. "FMKEY107,Fast master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0x2C 10. "FMKEY106,Fast master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 9. "FMKEY105,Fast master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0x2C 8. "FMKEY104,Fast master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 7. "FMKEY103,Fast master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0x2C 6. "FMKEY102,Fast master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 5. "FMKEY101,Fast master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0x2C 4. "FMKEY100,Fast master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 3. "FMKEY99,Fast master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0x2C 2. "FMKEY98,Fast master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 1. "FMKEY97,Fast master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0x2C 0. "FMKEY96,Fast master key bit 96 (i = 31 to 0)" "0,1" line.long 0x30 "MCE_FMKEYR4,MCE fast master key 4" bitfld.long 0x30 31. "FMKEY159,Fast master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x30 30. "FMKEY158,Fast master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 29. "FMKEY157,Fast master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x30 28. "FMKEY156,Fast master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 27. "FMKEY155,Fast master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x30 26. "FMKEY154,Fast master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 25. "FMKEY153,Fast master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x30 24. "FMKEY152,Fast master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 23. "FMKEY151,Fast master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x30 22. "FMKEY150,Fast master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 21. "FMKEY149,Fast master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x30 20. "FMKEY148,Fast master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 19. "FMKEY147,Fast master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x30 18. "FMKEY146,Fast master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 17. "FMKEY145,Fast master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x30 16. "FMKEY144,Fast master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 15. "FMKEY143,Fast master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x30 14. "FMKEY142,Fast master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 13. "FMKEY141,Fast master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x30 12. "FMKEY140,Fast master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 11. "FMKEY139,Fast master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x30 10. "FMKEY138,Fast master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 9. "FMKEY137,Fast master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x30 8. "FMKEY136,Fast master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 7. "FMKEY135,Fast master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x30 6. "FMKEY134,Fast master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 5. "FMKEY133,Fast master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x30 4. "FMKEY132,Fast master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 3. "FMKEY131,Fast master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x30 2. "FMKEY130,Fast master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 1. "FMKEY129,Fast master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x30 0. "FMKEY128,Fast master key bit 128 (i = 31 to 0)" "0,1" line.long 0x34 "MCE_FMKEYR5,MCE fast master key 5" bitfld.long 0x34 31. "FMKEY191,Fast master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x34 30. "FMKEY190,Fast master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 29. "FMKEY189,Fast master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x34 28. "FMKEY188,Fast master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 27. "FMKEY187,Fast master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x34 26. "FMKEY186,Fast master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 25. "FMKEY185,Fast master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x34 24. "FMKEY184,Fast master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 23. "FMKEY183,Fast master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x34 22. "FMKEY182,Fast master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 21. "FMKEY181,Fast master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x34 20. "FMKEY180,Fast master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 19. "FMKEY179,Fast master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x34 18. "FMKEY178,Fast master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 17. "FMKEY177,Fast master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x34 16. "FMKEY176,Fast master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 15. "FMKEY175,Fast master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x34 14. "FMKEY174,Fast master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 13. "FMKEY173,Fast master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x34 12. "FMKEY172,Fast master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 11. "FMKEY171,Fast master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x34 10. "FMKEY170,Fast master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 9. "FMKEY169,Fast master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x34 8. "FMKEY168,Fast master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 7. "FMKEY167,Fast master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x34 6. "FMKEY166,Fast master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 5. "FMKEY165,Fast master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x34 4. "FMKEY164,Fast master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 3. "FMKEY163,Fast master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x34 2. "FMKEY162,Fast master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 1. "FMKEY161,Fast master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x34 0. "FMKEY160,Fast master key bit 160 (i = 31 to 0)" "0,1" line.long 0x38 "MCE_FMKEYR6,MCE fast master key 6" bitfld.long 0x38 31. "FMKEY223,Fast master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x38 30. "FMKEY222,Fast master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 29. "FMKEY221,Fast master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x38 28. "FMKEY220,Fast master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 27. "FMKEY219,Fast master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x38 26. "FMKEY218,Fast master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 25. "FMKEY217,Fast master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x38 24. "FMKEY216,Fast master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 23. "FMKEY215,Fast master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x38 22. "FMKEY214,Fast master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 21. "FMKEY213,Fast master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x38 20. "FMKEY212,Fast master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 19. "FMKEY211,Fast master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x38 18. "FMKEY210,Fast master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 17. "FMKEY209,Fast master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x38 16. "FMKEY208,Fast master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 15. "FMKEY207,Fast master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x38 14. "FMKEY206,Fast master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 13. "FMKEY205,Fast master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x38 12. "FMKEY204,Fast master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 11. "FMKEY203,Fast master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x38 10. "FMKEY202,Fast master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 9. "FMKEY201,Fast master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x38 8. "FMKEY200,Fast master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 7. "FMKEY199,Fast master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x38 6. "FMKEY198,Fast master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 5. "FMKEY197,Fast master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x38 4. "FMKEY196,Fast master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 3. "FMKEY195,Fast master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x38 2. "FMKEY194,Fast master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 1. "FMKEY193,Fast master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x38 0. "FMKEY192,Fast master key bit 192 (i = 31 to 0)" "0,1" line.long 0x3C "MCE_FMKEYR7,MCE fast master key 7" bitfld.long 0x3C 31. "FMKEY255,Fast master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x3C 30. "FMKEY254,Fast master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 29. "FMKEY253,Fast master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x3C 28. "FMKEY252,Fast master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 27. "FMKEY251,Fast master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x3C 26. "FMKEY250,Fast master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 25. "FMKEY249,Fast master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x3C 24. "FMKEY248,Fast master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 23. "FMKEY247,Fast master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x3C 22. "FMKEY246,Fast master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 21. "FMKEY245,Fast master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x3C 20. "FMKEY244,Fast master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 19. "FMKEY243,Fast master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x3C 18. "FMKEY242,Fast master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 17. "FMKEY241,Fast master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x3C 16. "FMKEY240,Fast master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 15. "FMKEY239,Fast master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x3C 14. "FMKEY238,Fast master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 13. "FMKEY237,Fast master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x3C 12. "FMKEY236,Fast master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 11. "FMKEY235,Fast master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x3C 10. "FMKEY234,Fast master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 9. "FMKEY233,Fast master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x3C 8. "FMKEY232,Fast master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 7. "FMKEY231,Fast master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x3C 6. "FMKEY230,Fast master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 5. "FMKEY229,Fast master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x3C 4. "FMKEY228,Fast master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 3. "FMKEY227,Fast master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x3C 2. "FMKEY226,Fast master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 1. "FMKEY225,Fast master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x3C 0. "FMKEY224,Fast master key bit 224 (i = 31 to 0)" "0,1" group.long 0x240++0xB line.long 0x0 "MCE_CC1CFGR,MCE cipher context 1 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC1NR0,MCE cipher context 1 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC1NR1,MCE cipher context 1 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x24C++0xF line.long 0x0 "MCE_CC1KEYR0,MCE cipher context 1 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC1KEYR1,MCE cipher context 1 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC1KEYR2,MCE cipher context 1 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC1KEYR3,MCE cipher context 1 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" group.long 0x270++0xB line.long 0x0 "MCE_CC2CFGR,MCE cipher context 2 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC2NR0,MCE cipher context 2 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC2NR1,MCE cipher context 2 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x27C++0xF line.long 0x0 "MCE_CC2KEYR0,MCE cipher context 2 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC2KEYR1,MCE cipher context 2 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC2KEYR2,MCE cipher context 2 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC2KEYR3,MCE cipher context 2 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" tree.end tree "MCE3" base ad:0x4802C000 group.long 0x0++0x3 line.long 0x0 "MCE_CR,MCE configuration register" bitfld.long 0x0 4.--5. "CIPHERSEL,Cipher selection" "0: No cipher is selected. Any read (resp. write) to..,1: AES-128 cipher selected for all encrypted regions,2: Noekeon cipher selected for all encrypted regions,3: AES-256 cipher selected for all encrypted regions" bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx and MCE_FMKEYRx registers..,1: Writes to MCE_MKEYRx and MCE_FMKEYRx registers.." newline bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.." rgroup.long 0x4++0x7 line.long 0x0 "MCE_SR,MCE status register" bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCRx all..,1: When ENC bit and BREN are set in any MCE_REGCRx.." bitfld.long 0x0 2. "FMKVALID,Fast master key valid" "0: A valid key has not been written in MCE_FMKEYRx..,1: A valid key has been written in MCE_FMKEYRx.." newline bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.." line.long 0x4 "MCE_IASR,MCE illegal access status register" bitfld.long 0x4 1. "IAEF,Illegal access error flag" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "MCE_IACR,MCE illegal access clear register" bitfld.long 0x0 1. "IAEF,Illegal access error flag clear" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register" bitfld.long 0x0 1. "IAEIE,Illegal access error interrupt enable" "0: Interrupt generation on illegal access errors is..,1: Interrupt generation when an illegal access.." rgroup.long 0x24++0x3 line.long 0x0 "MCE_IADDR,MCE illegal address register" hexmask.long 0x0 0.--31. 1. "IADD,Illegal address" group.long 0x40++0xB line.long 0x0 "MCE_REGCR1,MCE region 1 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR1,MCE start address for region 1 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR1,MCE end address for region 1 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x50++0xB line.long 0x0 "MCE_REGCR2,MCE region 2 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR2,MCE start address for region 2 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR2,MCE end address for region 2 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x60++0xB line.long 0x0 "MCE_REGCR3,MCE region 3 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR3,MCE start address for region 3 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR3,MCE end address for region 3 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x70++0xB line.long 0x0 "MCE_REGCR4,MCE region 4 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR4,MCE start address for region 4 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR4,MCE end address for region 4 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" wgroup.long 0x200++0x3F line.long 0x0 "MCE_MKEYR0,.MCE master key 0" bitfld.long 0x0 31. "MKEY31,Master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x0 30. "MKEY30,Master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 29. "MKEY29,Master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x0 28. "MKEY28,Master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 27. "MKEY27,Master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x0 26. "MKEY26,Master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 25. "MKEY25,Master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x0 24. "MKEY24,Master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 23. "MKEY23,Master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x0 22. "MKEY22,Master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 21. "MKEY21,Master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x0 20. "MKEY20,Master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 19. "MKEY19,Master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x0 18. "MKEY18,Master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 17. "MKEY17,Master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x0 16. "MKEY16,Master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 15. "MKEY15,Master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x0 14. "MKEY14,Master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 13. "MKEY13,Master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x0 12. "MKEY12,Master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 11. "MKEY11,Master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x0 10. "MKEY10,Master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 9. "MKEY9,Master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x0 8. "MKEY8,Master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 7. "MKEY7,Master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x0 6. "MKEY6,Master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 5. "MKEY5,Master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x0 4. "MKEY4,Master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 3. "MKEY3,Master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x0 2. "MKEY2,Master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 1. "MKEY1,Master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x0 0. "MKEY0,Master key bit 0 (i = 31 to 0)" "0,1" line.long 0x4 "MCE_MKEYR1,.MCE master key 1" bitfld.long 0x4 31. "MKEY63,Master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x4 30. "MKEY62,Master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 29. "MKEY61,Master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x4 28. "MKEY60,Master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 27. "MKEY59,Master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x4 26. "MKEY58,Master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 25. "MKEY57,Master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x4 24. "MKEY56,Master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 23. "MKEY55,Master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x4 22. "MKEY54,Master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 21. "MKEY53,Master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x4 20. "MKEY52,Master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 19. "MKEY51,Master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x4 18. "MKEY50,Master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 17. "MKEY49,Master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x4 16. "MKEY48,Master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 15. "MKEY47,Master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x4 14. "MKEY46,Master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 13. "MKEY45,Master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x4 12. "MKEY44,Master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 11. "MKEY43,Master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x4 10. "MKEY42,Master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 9. "MKEY41,Master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x4 8. "MKEY40,Master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 7. "MKEY39,Master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x4 6. "MKEY38,Master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 5. "MKEY37,Master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x4 4. "MKEY36,Master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 3. "MKEY35,Master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x4 2. "MKEY34,Master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 1. "MKEY33,Master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x4 0. "MKEY32,Master key bit 32 (i = 31 to 0)" "0,1" line.long 0x8 "MCE_MKEYR2,.MCE master key 2" bitfld.long 0x8 31. "MKEY95,Master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x8 30. "MKEY94,Master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 29. "MKEY93,Master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x8 28. "MKEY92,Master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 27. "MKEY91,Master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x8 26. "MKEY90,Master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 25. "MKEY89,Master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x8 24. "MKEY88,Master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 23. "MKEY87,Master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x8 22. "MKEY86,Master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 21. "MKEY85,Master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x8 20. "MKEY84,Master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 19. "MKEY83,Master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x8 18. "MKEY82,Master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 17. "MKEY81,Master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x8 16. "MKEY80,Master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 15. "MKEY79,Master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x8 14. "MKEY78,Master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 13. "MKEY77,Master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x8 12. "MKEY76,Master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 11. "MKEY75,Master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x8 10. "MKEY74,Master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 9. "MKEY73,Master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x8 8. "MKEY72,Master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 7. "MKEY71,Master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x8 6. "MKEY70,Master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 5. "MKEY69,Master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x8 4. "MKEY68,Master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 3. "MKEY67,Master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x8 2. "MKEY66,Master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 1. "MKEY65,Master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x8 0. "MKEY64,Master key bit 64 (i = 31 to 0)" "0,1" line.long 0xC "MCE_MKEYR3,.MCE master key 3" bitfld.long 0xC 31. "MKEY127,Master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0xC 30. "MKEY126,Master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 29. "MKEY125,Master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0xC 28. "MKEY124,Master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 27. "MKEY123,Master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0xC 26. "MKEY122,Master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 25. "MKEY121,Master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0xC 24. "MKEY120,Master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 23. "MKEY119,Master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0xC 22. "MKEY118,Master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 21. "MKEY117,Master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0xC 20. "MKEY116,Master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 19. "MKEY115,Master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0xC 18. "MKEY114,Master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 17. "MKEY113,Master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0xC 16. "MKEY112,Master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 15. "MKEY111,Master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0xC 14. "MKEY110,Master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 13. "MKEY109,Master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0xC 12. "MKEY108,Master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 11. "MKEY107,Master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0xC 10. "MKEY106,Master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 9. "MKEY105,Master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0xC 8. "MKEY104,Master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 7. "MKEY103,Master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0xC 6. "MKEY102,Master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 5. "MKEY101,Master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0xC 4. "MKEY100,Master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 3. "MKEY99,Master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0xC 2. "MKEY98,Master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 1. "MKEY97,Master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0xC 0. "MKEY96,Master key bit 96 (i = 31 to 0)" "0,1" line.long 0x10 "MCE_MKEYR4,.MCE master key 4" bitfld.long 0x10 31. "MKEY159,Master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x10 30. "MKEY158,Master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 29. "MKEY157,Master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x10 28. "MKEY156,Master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 27. "MKEY155,Master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x10 26. "MKEY154,Master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 25. "MKEY153,Master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x10 24. "MKEY152,Master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 23. "MKEY151,Master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x10 22. "MKEY150,Master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 21. "MKEY149,Master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x10 20. "MKEY148,Master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 19. "MKEY147,Master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x10 18. "MKEY146,Master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 17. "MKEY145,Master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x10 16. "MKEY144,Master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 15. "MKEY143,Master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x10 14. "MKEY142,Master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 13. "MKEY141,Master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x10 12. "MKEY140,Master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 11. "MKEY139,Master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x10 10. "MKEY138,Master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 9. "MKEY137,Master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x10 8. "MKEY136,Master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 7. "MKEY135,Master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x10 6. "MKEY134,Master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 5. "MKEY133,Master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x10 4. "MKEY132,Master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 3. "MKEY131,Master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x10 2. "MKEY130,Master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 1. "MKEY129,Master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x10 0. "MKEY128,Master key bit 128 (i = 31 to 0)" "0,1" line.long 0x14 "MCE_MKEYR5,.MCE master key 5" bitfld.long 0x14 31. "MKEY191,Master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x14 30. "MKEY190,Master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 29. "MKEY189,Master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x14 28. "MKEY188,Master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 27. "MKEY187,Master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x14 26. "MKEY186,Master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 25. "MKEY185,Master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x14 24. "MKEY184,Master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 23. "MKEY183,Master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x14 22. "MKEY182,Master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 21. "MKEY181,Master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x14 20. "MKEY180,Master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 19. "MKEY179,Master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x14 18. "MKEY178,Master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 17. "MKEY177,Master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x14 16. "MKEY176,Master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 15. "MKEY175,Master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x14 14. "MKEY174,Master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 13. "MKEY173,Master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x14 12. "MKEY172,Master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 11. "MKEY171,Master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x14 10. "MKEY170,Master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 9. "MKEY169,Master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x14 8. "MKEY168,Master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 7. "MKEY167,Master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x14 6. "MKEY166,Master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 5. "MKEY165,Master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x14 4. "MKEY164,Master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 3. "MKEY163,Master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x14 2. "MKEY162,Master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 1. "MKEY161,Master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x14 0. "MKEY160,Master key bit 160 (i = 31 to 0)" "0,1" line.long 0x18 "MCE_MKEYR6,.MCE master key 6" bitfld.long 0x18 31. "MKEY223,Master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x18 30. "MKEY222,Master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 29. "MKEY221,Master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x18 28. "MKEY220,Master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 27. "MKEY219,Master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x18 26. "MKEY218,Master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 25. "MKEY217,Master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x18 24. "MKEY216,Master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 23. "MKEY215,Master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x18 22. "MKEY214,Master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 21. "MKEY213,Master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x18 20. "MKEY212,Master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 19. "MKEY211,Master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x18 18. "MKEY210,Master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 17. "MKEY209,Master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x18 16. "MKEY208,Master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 15. "MKEY207,Master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x18 14. "MKEY206,Master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 13. "MKEY205,Master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x18 12. "MKEY204,Master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 11. "MKEY203,Master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x18 10. "MKEY202,Master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 9. "MKEY201,Master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x18 8. "MKEY200,Master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 7. "MKEY199,Master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x18 6. "MKEY198,Master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 5. "MKEY197,Master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x18 4. "MKEY196,Master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 3. "MKEY195,Master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x18 2. "MKEY194,Master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 1. "MKEY193,Master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x18 0. "MKEY192,Master key bit 192 (i = 31 to 0)" "0,1" line.long 0x1C "MCE_MKEYR7,.MCE master key 7" bitfld.long 0x1C 31. "MKEY255,Master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x1C 30. "MKEY254,Master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 29. "MKEY253,Master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x1C 28. "MKEY252,Master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 27. "MKEY251,Master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x1C 26. "MKEY250,Master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 25. "MKEY249,Master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x1C 24. "MKEY248,Master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 23. "MKEY247,Master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x1C 22. "MKEY246,Master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 21. "MKEY245,Master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x1C 20. "MKEY244,Master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 19. "MKEY243,Master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x1C 18. "MKEY242,Master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 17. "MKEY241,Master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x1C 16. "MKEY240,Master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 15. "MKEY239,Master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x1C 14. "MKEY238,Master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 13. "MKEY237,Master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x1C 12. "MKEY236,Master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 11. "MKEY235,Master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x1C 10. "MKEY234,Master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 9. "MKEY233,Master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x1C 8. "MKEY232,Master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 7. "MKEY231,Master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x1C 6. "MKEY230,Master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 5. "MKEY229,Master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x1C 4. "MKEY228,Master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 3. "MKEY227,Master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x1C 2. "MKEY226,Master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 1. "MKEY225,Master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x1C 0. "MKEY224,Master key bit 224 (i = 31 to 0)" "0,1" line.long 0x20 "MCE_FMKEYR0,MCE fast master key 0" bitfld.long 0x20 31. "FMKEY31,Fast master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x20 30. "FMKEY30,Fast master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 29. "FMKEY29,Fast master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x20 28. "FMKEY28,Fast master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 27. "FMKEY27,Fast master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x20 26. "FMKEY26,Fast master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 25. "FMKEY25,Fast master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x20 24. "FMKEY24,Fast master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 23. "FMKEY23,Fast master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x20 22. "FMKEY22,Fast master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 21. "FMKEY21,Fast master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x20 20. "FMKEY20,Fast master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 19. "FMKEY19,Fast master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x20 18. "FMKEY18,Fast master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 17. "FMKEY17,Fast master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x20 16. "FMKEY16,Fast master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 15. "FMKEY15,Fast master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x20 14. "FMKEY14,Fast master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 13. "FMKEY13,Fast master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x20 12. "FMKEY12,Fast master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 11. "FMKEY11,Fast master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x20 10. "FMKEY10,Fast master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 9. "FMKEY9,Fast master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x20 8. "FMKEY8,Fast master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 7. "FMKEY7,Fast master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x20 6. "FMKEY6,Fast master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 5. "FMKEY5,Fast master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x20 4. "FMKEY4,Fast master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 3. "FMKEY3,Fast master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x20 2. "FMKEY2,Fast master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 1. "FMKEY1,Fast master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x20 0. "FMKEY0,Fast master key bit 0 (i = 31 to 0)" "0,1" line.long 0x24 "MCE_FMKEYR1,MCE fast master key 1" bitfld.long 0x24 31. "FMKEY63,Fast master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x24 30. "FMKEY62,Fast master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 29. "FMKEY61,Fast master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x24 28. "FMKEY60,Fast master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 27. "FMKEY59,Fast master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x24 26. "FMKEY58,Fast master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 25. "FMKEY57,Fast master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x24 24. "FMKEY56,Fast master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 23. "FMKEY55,Fast master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x24 22. "FMKEY54,Fast master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 21. "FMKEY53,Fast master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x24 20. "FMKEY52,Fast master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 19. "FMKEY51,Fast master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x24 18. "FMKEY50,Fast master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 17. "FMKEY49,Fast master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x24 16. "FMKEY48,Fast master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 15. "FMKEY47,Fast master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x24 14. "FMKEY46,Fast master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 13. "FMKEY45,Fast master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x24 12. "FMKEY44,Fast master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 11. "FMKEY43,Fast master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x24 10. "FMKEY42,Fast master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 9. "FMKEY41,Fast master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x24 8. "FMKEY40,Fast master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 7. "FMKEY39,Fast master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x24 6. "FMKEY38,Fast master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 5. "FMKEY37,Fast master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x24 4. "FMKEY36,Fast master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 3. "FMKEY35,Fast master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x24 2. "FMKEY34,Fast master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 1. "FMKEY33,Fast master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x24 0. "FMKEY32,Fast master key bit 32 (i = 31 to 0)" "0,1" line.long 0x28 "MCE_FMKEYR2,MCE fast master key 2" bitfld.long 0x28 31. "FMKEY95,Fast master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x28 30. "FMKEY94,Fast master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 29. "FMKEY93,Fast master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x28 28. "FMKEY92,Fast master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 27. "FMKEY91,Fast master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x28 26. "FMKEY90,Fast master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 25. "FMKEY89,Fast master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x28 24. "FMKEY88,Fast master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 23. "FMKEY87,Fast master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x28 22. "FMKEY86,Fast master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 21. "FMKEY85,Fast master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x28 20. "FMKEY84,Fast master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 19. "FMKEY83,Fast master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x28 18. "FMKEY82,Fast master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 17. "FMKEY81,Fast master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x28 16. "FMKEY80,Fast master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 15. "FMKEY79,Fast master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x28 14. "FMKEY78,Fast master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 13. "FMKEY77,Fast master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x28 12. "FMKEY76,Fast master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 11. "FMKEY75,Fast master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x28 10. "FMKEY74,Fast master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 9. "FMKEY73,Fast master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x28 8. "FMKEY72,Fast master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 7. "FMKEY71,Fast master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x28 6. "FMKEY70,Fast master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 5. "FMKEY69,Fast master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x28 4. "FMKEY68,Fast master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 3. "FMKEY67,Fast master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x28 2. "FMKEY66,Fast master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 1. "FMKEY65,Fast master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x28 0. "FMKEY64,Fast master key bit 64 (i = 31 to 0)" "0,1" line.long 0x2C "MCE_FMKEYR3,MCE fast master key 3" bitfld.long 0x2C 31. "FMKEY127,Fast master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0x2C 30. "FMKEY126,Fast master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 29. "FMKEY125,Fast master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0x2C 28. "FMKEY124,Fast master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 27. "FMKEY123,Fast master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0x2C 26. "FMKEY122,Fast master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 25. "FMKEY121,Fast master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0x2C 24. "FMKEY120,Fast master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 23. "FMKEY119,Fast master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0x2C 22. "FMKEY118,Fast master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 21. "FMKEY117,Fast master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0x2C 20. "FMKEY116,Fast master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 19. "FMKEY115,Fast master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0x2C 18. "FMKEY114,Fast master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 17. "FMKEY113,Fast master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0x2C 16. "FMKEY112,Fast master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 15. "FMKEY111,Fast master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0x2C 14. "FMKEY110,Fast master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 13. "FMKEY109,Fast master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0x2C 12. "FMKEY108,Fast master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 11. "FMKEY107,Fast master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0x2C 10. "FMKEY106,Fast master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 9. "FMKEY105,Fast master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0x2C 8. "FMKEY104,Fast master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 7. "FMKEY103,Fast master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0x2C 6. "FMKEY102,Fast master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 5. "FMKEY101,Fast master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0x2C 4. "FMKEY100,Fast master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 3. "FMKEY99,Fast master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0x2C 2. "FMKEY98,Fast master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 1. "FMKEY97,Fast master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0x2C 0. "FMKEY96,Fast master key bit 96 (i = 31 to 0)" "0,1" line.long 0x30 "MCE_FMKEYR4,MCE fast master key 4" bitfld.long 0x30 31. "FMKEY159,Fast master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x30 30. "FMKEY158,Fast master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 29. "FMKEY157,Fast master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x30 28. "FMKEY156,Fast master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 27. "FMKEY155,Fast master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x30 26. "FMKEY154,Fast master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 25. "FMKEY153,Fast master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x30 24. "FMKEY152,Fast master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 23. "FMKEY151,Fast master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x30 22. "FMKEY150,Fast master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 21. "FMKEY149,Fast master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x30 20. "FMKEY148,Fast master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 19. "FMKEY147,Fast master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x30 18. "FMKEY146,Fast master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 17. "FMKEY145,Fast master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x30 16. "FMKEY144,Fast master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 15. "FMKEY143,Fast master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x30 14. "FMKEY142,Fast master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 13. "FMKEY141,Fast master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x30 12. "FMKEY140,Fast master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 11. "FMKEY139,Fast master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x30 10. "FMKEY138,Fast master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 9. "FMKEY137,Fast master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x30 8. "FMKEY136,Fast master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 7. "FMKEY135,Fast master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x30 6. "FMKEY134,Fast master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 5. "FMKEY133,Fast master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x30 4. "FMKEY132,Fast master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 3. "FMKEY131,Fast master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x30 2. "FMKEY130,Fast master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 1. "FMKEY129,Fast master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x30 0. "FMKEY128,Fast master key bit 128 (i = 31 to 0)" "0,1" line.long 0x34 "MCE_FMKEYR5,MCE fast master key 5" bitfld.long 0x34 31. "FMKEY191,Fast master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x34 30. "FMKEY190,Fast master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 29. "FMKEY189,Fast master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x34 28. "FMKEY188,Fast master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 27. "FMKEY187,Fast master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x34 26. "FMKEY186,Fast master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 25. "FMKEY185,Fast master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x34 24. "FMKEY184,Fast master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 23. "FMKEY183,Fast master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x34 22. "FMKEY182,Fast master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 21. "FMKEY181,Fast master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x34 20. "FMKEY180,Fast master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 19. "FMKEY179,Fast master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x34 18. "FMKEY178,Fast master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 17. "FMKEY177,Fast master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x34 16. "FMKEY176,Fast master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 15. "FMKEY175,Fast master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x34 14. "FMKEY174,Fast master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 13. "FMKEY173,Fast master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x34 12. "FMKEY172,Fast master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 11. "FMKEY171,Fast master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x34 10. "FMKEY170,Fast master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 9. "FMKEY169,Fast master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x34 8. "FMKEY168,Fast master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 7. "FMKEY167,Fast master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x34 6. "FMKEY166,Fast master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 5. "FMKEY165,Fast master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x34 4. "FMKEY164,Fast master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 3. "FMKEY163,Fast master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x34 2. "FMKEY162,Fast master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 1. "FMKEY161,Fast master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x34 0. "FMKEY160,Fast master key bit 160 (i = 31 to 0)" "0,1" line.long 0x38 "MCE_FMKEYR6,MCE fast master key 6" bitfld.long 0x38 31. "FMKEY223,Fast master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x38 30. "FMKEY222,Fast master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 29. "FMKEY221,Fast master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x38 28. "FMKEY220,Fast master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 27. "FMKEY219,Fast master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x38 26. "FMKEY218,Fast master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 25. "FMKEY217,Fast master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x38 24. "FMKEY216,Fast master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 23. "FMKEY215,Fast master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x38 22. "FMKEY214,Fast master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 21. "FMKEY213,Fast master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x38 20. "FMKEY212,Fast master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 19. "FMKEY211,Fast master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x38 18. "FMKEY210,Fast master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 17. "FMKEY209,Fast master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x38 16. "FMKEY208,Fast master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 15. "FMKEY207,Fast master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x38 14. "FMKEY206,Fast master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 13. "FMKEY205,Fast master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x38 12. "FMKEY204,Fast master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 11. "FMKEY203,Fast master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x38 10. "FMKEY202,Fast master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 9. "FMKEY201,Fast master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x38 8. "FMKEY200,Fast master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 7. "FMKEY199,Fast master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x38 6. "FMKEY198,Fast master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 5. "FMKEY197,Fast master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x38 4. "FMKEY196,Fast master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 3. "FMKEY195,Fast master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x38 2. "FMKEY194,Fast master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 1. "FMKEY193,Fast master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x38 0. "FMKEY192,Fast master key bit 192 (i = 31 to 0)" "0,1" line.long 0x3C "MCE_FMKEYR7,MCE fast master key 7" bitfld.long 0x3C 31. "FMKEY255,Fast master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x3C 30. "FMKEY254,Fast master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 29. "FMKEY253,Fast master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x3C 28. "FMKEY252,Fast master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 27. "FMKEY251,Fast master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x3C 26. "FMKEY250,Fast master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 25. "FMKEY249,Fast master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x3C 24. "FMKEY248,Fast master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 23. "FMKEY247,Fast master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x3C 22. "FMKEY246,Fast master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 21. "FMKEY245,Fast master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x3C 20. "FMKEY244,Fast master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 19. "FMKEY243,Fast master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x3C 18. "FMKEY242,Fast master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 17. "FMKEY241,Fast master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x3C 16. "FMKEY240,Fast master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 15. "FMKEY239,Fast master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x3C 14. "FMKEY238,Fast master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 13. "FMKEY237,Fast master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x3C 12. "FMKEY236,Fast master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 11. "FMKEY235,Fast master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x3C 10. "FMKEY234,Fast master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 9. "FMKEY233,Fast master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x3C 8. "FMKEY232,Fast master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 7. "FMKEY231,Fast master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x3C 6. "FMKEY230,Fast master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 5. "FMKEY229,Fast master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x3C 4. "FMKEY228,Fast master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 3. "FMKEY227,Fast master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x3C 2. "FMKEY226,Fast master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 1. "FMKEY225,Fast master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x3C 0. "FMKEY224,Fast master key bit 224 (i = 31 to 0)" "0,1" group.long 0x240++0xB line.long 0x0 "MCE_CC1CFGR,MCE cipher context 1 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC1NR0,MCE cipher context 1 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC1NR1,MCE cipher context 1 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x24C++0xF line.long 0x0 "MCE_CC1KEYR0,MCE cipher context 1 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC1KEYR1,MCE cipher context 1 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC1KEYR2,MCE cipher context 1 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC1KEYR3,MCE cipher context 1 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" group.long 0x270++0xB line.long 0x0 "MCE_CC2CFGR,MCE cipher context 2 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC2NR0,MCE cipher context 2 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC2NR1,MCE cipher context 2 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x27C++0xF line.long 0x0 "MCE_CC2KEYR0,MCE cipher context 2 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC2KEYR1,MCE cipher context 2 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC2KEYR2,MCE cipher context 2 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC2KEYR3,MCE cipher context 2 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" tree.end tree "MCE3_S" base ad:0x5802C000 group.long 0x0++0x3 line.long 0x0 "MCE_CR,MCE configuration register" bitfld.long 0x0 4.--5. "CIPHERSEL,Cipher selection" "0: No cipher is selected. Any read (resp. write) to..,1: AES-128 cipher selected for all encrypted regions,2: Noekeon cipher selected for all encrypted regions,3: AES-256 cipher selected for all encrypted regions" bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx and MCE_FMKEYRx registers..,1: Writes to MCE_MKEYRx and MCE_FMKEYRx registers.." newline bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.." rgroup.long 0x4++0x7 line.long 0x0 "MCE_SR,MCE status register" bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCRx all..,1: When ENC bit and BREN are set in any MCE_REGCRx.." bitfld.long 0x0 2. "FMKVALID,Fast master key valid" "0: A valid key has not been written in MCE_FMKEYRx..,1: A valid key has been written in MCE_FMKEYRx.." newline bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.." line.long 0x4 "MCE_IASR,MCE illegal access status register" bitfld.long 0x4 1. "IAEF,Illegal access error flag" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "MCE_IACR,MCE illegal access clear register" bitfld.long 0x0 1. "IAEF,Illegal access error flag clear" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register" bitfld.long 0x0 1. "IAEIE,Illegal access error interrupt enable" "0: Interrupt generation on illegal access errors is..,1: Interrupt generation when an illegal access.." rgroup.long 0x24++0x3 line.long 0x0 "MCE_IADDR,MCE illegal address register" hexmask.long 0x0 0.--31. 1. "IADD,Illegal address" group.long 0x40++0xB line.long 0x0 "MCE_REGCR1,MCE region 1 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR1,MCE start address for region 1 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR1,MCE end address for region 1 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x50++0xB line.long 0x0 "MCE_REGCR2,MCE region 2 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR2,MCE start address for region 2 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR2,MCE end address for region 2 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x60++0xB line.long 0x0 "MCE_REGCR3,MCE region 3 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR3,MCE start address for region 3 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR3,MCE end address for region 3 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x70++0xB line.long 0x0 "MCE_REGCR4,MCE region 4 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR4,MCE start address for region 4 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR4,MCE end address for region 4 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" wgroup.long 0x200++0x3F line.long 0x0 "MCE_MKEYR0,.MCE master key 0" bitfld.long 0x0 31. "MKEY31,Master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x0 30. "MKEY30,Master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 29. "MKEY29,Master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x0 28. "MKEY28,Master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 27. "MKEY27,Master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x0 26. "MKEY26,Master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 25. "MKEY25,Master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x0 24. "MKEY24,Master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 23. "MKEY23,Master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x0 22. "MKEY22,Master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 21. "MKEY21,Master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x0 20. "MKEY20,Master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 19. "MKEY19,Master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x0 18. "MKEY18,Master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 17. "MKEY17,Master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x0 16. "MKEY16,Master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 15. "MKEY15,Master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x0 14. "MKEY14,Master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 13. "MKEY13,Master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x0 12. "MKEY12,Master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 11. "MKEY11,Master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x0 10. "MKEY10,Master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 9. "MKEY9,Master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x0 8. "MKEY8,Master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 7. "MKEY7,Master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x0 6. "MKEY6,Master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 5. "MKEY5,Master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x0 4. "MKEY4,Master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 3. "MKEY3,Master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x0 2. "MKEY2,Master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 1. "MKEY1,Master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x0 0. "MKEY0,Master key bit 0 (i = 31 to 0)" "0,1" line.long 0x4 "MCE_MKEYR1,.MCE master key 1" bitfld.long 0x4 31. "MKEY63,Master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x4 30. "MKEY62,Master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 29. "MKEY61,Master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x4 28. "MKEY60,Master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 27. "MKEY59,Master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x4 26. "MKEY58,Master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 25. "MKEY57,Master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x4 24. "MKEY56,Master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 23. "MKEY55,Master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x4 22. "MKEY54,Master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 21. "MKEY53,Master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x4 20. "MKEY52,Master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 19. "MKEY51,Master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x4 18. "MKEY50,Master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 17. "MKEY49,Master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x4 16. "MKEY48,Master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 15. "MKEY47,Master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x4 14. "MKEY46,Master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 13. "MKEY45,Master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x4 12. "MKEY44,Master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 11. "MKEY43,Master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x4 10. "MKEY42,Master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 9. "MKEY41,Master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x4 8. "MKEY40,Master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 7. "MKEY39,Master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x4 6. "MKEY38,Master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 5. "MKEY37,Master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x4 4. "MKEY36,Master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 3. "MKEY35,Master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x4 2. "MKEY34,Master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 1. "MKEY33,Master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x4 0. "MKEY32,Master key bit 32 (i = 31 to 0)" "0,1" line.long 0x8 "MCE_MKEYR2,.MCE master key 2" bitfld.long 0x8 31. "MKEY95,Master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x8 30. "MKEY94,Master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 29. "MKEY93,Master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x8 28. "MKEY92,Master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 27. "MKEY91,Master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x8 26. "MKEY90,Master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 25. "MKEY89,Master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x8 24. "MKEY88,Master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 23. "MKEY87,Master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x8 22. "MKEY86,Master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 21. "MKEY85,Master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x8 20. "MKEY84,Master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 19. "MKEY83,Master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x8 18. "MKEY82,Master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 17. "MKEY81,Master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x8 16. "MKEY80,Master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 15. "MKEY79,Master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x8 14. "MKEY78,Master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 13. "MKEY77,Master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x8 12. "MKEY76,Master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 11. "MKEY75,Master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x8 10. "MKEY74,Master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 9. "MKEY73,Master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x8 8. "MKEY72,Master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 7. "MKEY71,Master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x8 6. "MKEY70,Master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 5. "MKEY69,Master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x8 4. "MKEY68,Master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 3. "MKEY67,Master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x8 2. "MKEY66,Master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 1. "MKEY65,Master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x8 0. "MKEY64,Master key bit 64 (i = 31 to 0)" "0,1" line.long 0xC "MCE_MKEYR3,.MCE master key 3" bitfld.long 0xC 31. "MKEY127,Master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0xC 30. "MKEY126,Master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 29. "MKEY125,Master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0xC 28. "MKEY124,Master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 27. "MKEY123,Master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0xC 26. "MKEY122,Master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 25. "MKEY121,Master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0xC 24. "MKEY120,Master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 23. "MKEY119,Master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0xC 22. "MKEY118,Master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 21. "MKEY117,Master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0xC 20. "MKEY116,Master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 19. "MKEY115,Master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0xC 18. "MKEY114,Master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 17. "MKEY113,Master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0xC 16. "MKEY112,Master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 15. "MKEY111,Master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0xC 14. "MKEY110,Master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 13. "MKEY109,Master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0xC 12. "MKEY108,Master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 11. "MKEY107,Master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0xC 10. "MKEY106,Master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 9. "MKEY105,Master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0xC 8. "MKEY104,Master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 7. "MKEY103,Master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0xC 6. "MKEY102,Master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 5. "MKEY101,Master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0xC 4. "MKEY100,Master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 3. "MKEY99,Master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0xC 2. "MKEY98,Master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 1. "MKEY97,Master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0xC 0. "MKEY96,Master key bit 96 (i = 31 to 0)" "0,1" line.long 0x10 "MCE_MKEYR4,.MCE master key 4" bitfld.long 0x10 31. "MKEY159,Master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x10 30. "MKEY158,Master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 29. "MKEY157,Master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x10 28. "MKEY156,Master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 27. "MKEY155,Master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x10 26. "MKEY154,Master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 25. "MKEY153,Master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x10 24. "MKEY152,Master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 23. "MKEY151,Master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x10 22. "MKEY150,Master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 21. "MKEY149,Master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x10 20. "MKEY148,Master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 19. "MKEY147,Master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x10 18. "MKEY146,Master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 17. "MKEY145,Master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x10 16. "MKEY144,Master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 15. "MKEY143,Master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x10 14. "MKEY142,Master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 13. "MKEY141,Master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x10 12. "MKEY140,Master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 11. "MKEY139,Master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x10 10. "MKEY138,Master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 9. "MKEY137,Master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x10 8. "MKEY136,Master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 7. "MKEY135,Master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x10 6. "MKEY134,Master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 5. "MKEY133,Master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x10 4. "MKEY132,Master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 3. "MKEY131,Master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x10 2. "MKEY130,Master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 1. "MKEY129,Master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x10 0. "MKEY128,Master key bit 128 (i = 31 to 0)" "0,1" line.long 0x14 "MCE_MKEYR5,.MCE master key 5" bitfld.long 0x14 31. "MKEY191,Master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x14 30. "MKEY190,Master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 29. "MKEY189,Master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x14 28. "MKEY188,Master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 27. "MKEY187,Master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x14 26. "MKEY186,Master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 25. "MKEY185,Master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x14 24. "MKEY184,Master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 23. "MKEY183,Master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x14 22. "MKEY182,Master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 21. "MKEY181,Master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x14 20. "MKEY180,Master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 19. "MKEY179,Master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x14 18. "MKEY178,Master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 17. "MKEY177,Master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x14 16. "MKEY176,Master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 15. "MKEY175,Master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x14 14. "MKEY174,Master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 13. "MKEY173,Master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x14 12. "MKEY172,Master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 11. "MKEY171,Master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x14 10. "MKEY170,Master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 9. "MKEY169,Master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x14 8. "MKEY168,Master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 7. "MKEY167,Master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x14 6. "MKEY166,Master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 5. "MKEY165,Master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x14 4. "MKEY164,Master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 3. "MKEY163,Master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x14 2. "MKEY162,Master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 1. "MKEY161,Master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x14 0. "MKEY160,Master key bit 160 (i = 31 to 0)" "0,1" line.long 0x18 "MCE_MKEYR6,.MCE master key 6" bitfld.long 0x18 31. "MKEY223,Master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x18 30. "MKEY222,Master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 29. "MKEY221,Master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x18 28. "MKEY220,Master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 27. "MKEY219,Master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x18 26. "MKEY218,Master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 25. "MKEY217,Master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x18 24. "MKEY216,Master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 23. "MKEY215,Master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x18 22. "MKEY214,Master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 21. "MKEY213,Master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x18 20. "MKEY212,Master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 19. "MKEY211,Master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x18 18. "MKEY210,Master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 17. "MKEY209,Master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x18 16. "MKEY208,Master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 15. "MKEY207,Master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x18 14. "MKEY206,Master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 13. "MKEY205,Master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x18 12. "MKEY204,Master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 11. "MKEY203,Master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x18 10. "MKEY202,Master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 9. "MKEY201,Master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x18 8. "MKEY200,Master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 7. "MKEY199,Master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x18 6. "MKEY198,Master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 5. "MKEY197,Master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x18 4. "MKEY196,Master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 3. "MKEY195,Master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x18 2. "MKEY194,Master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 1. "MKEY193,Master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x18 0. "MKEY192,Master key bit 192 (i = 31 to 0)" "0,1" line.long 0x1C "MCE_MKEYR7,.MCE master key 7" bitfld.long 0x1C 31. "MKEY255,Master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x1C 30. "MKEY254,Master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 29. "MKEY253,Master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x1C 28. "MKEY252,Master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 27. "MKEY251,Master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x1C 26. "MKEY250,Master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 25. "MKEY249,Master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x1C 24. "MKEY248,Master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 23. "MKEY247,Master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x1C 22. "MKEY246,Master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 21. "MKEY245,Master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x1C 20. "MKEY244,Master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 19. "MKEY243,Master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x1C 18. "MKEY242,Master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 17. "MKEY241,Master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x1C 16. "MKEY240,Master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 15. "MKEY239,Master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x1C 14. "MKEY238,Master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 13. "MKEY237,Master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x1C 12. "MKEY236,Master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 11. "MKEY235,Master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x1C 10. "MKEY234,Master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 9. "MKEY233,Master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x1C 8. "MKEY232,Master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 7. "MKEY231,Master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x1C 6. "MKEY230,Master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 5. "MKEY229,Master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x1C 4. "MKEY228,Master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 3. "MKEY227,Master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x1C 2. "MKEY226,Master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 1. "MKEY225,Master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x1C 0. "MKEY224,Master key bit 224 (i = 31 to 0)" "0,1" line.long 0x20 "MCE_FMKEYR0,MCE fast master key 0" bitfld.long 0x20 31. "FMKEY31,Fast master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x20 30. "FMKEY30,Fast master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 29. "FMKEY29,Fast master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x20 28. "FMKEY28,Fast master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 27. "FMKEY27,Fast master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x20 26. "FMKEY26,Fast master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 25. "FMKEY25,Fast master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x20 24. "FMKEY24,Fast master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 23. "FMKEY23,Fast master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x20 22. "FMKEY22,Fast master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 21. "FMKEY21,Fast master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x20 20. "FMKEY20,Fast master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 19. "FMKEY19,Fast master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x20 18. "FMKEY18,Fast master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 17. "FMKEY17,Fast master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x20 16. "FMKEY16,Fast master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 15. "FMKEY15,Fast master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x20 14. "FMKEY14,Fast master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 13. "FMKEY13,Fast master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x20 12. "FMKEY12,Fast master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 11. "FMKEY11,Fast master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x20 10. "FMKEY10,Fast master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 9. "FMKEY9,Fast master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x20 8. "FMKEY8,Fast master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 7. "FMKEY7,Fast master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x20 6. "FMKEY6,Fast master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 5. "FMKEY5,Fast master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x20 4. "FMKEY4,Fast master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 3. "FMKEY3,Fast master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x20 2. "FMKEY2,Fast master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 1. "FMKEY1,Fast master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x20 0. "FMKEY0,Fast master key bit 0 (i = 31 to 0)" "0,1" line.long 0x24 "MCE_FMKEYR1,MCE fast master key 1" bitfld.long 0x24 31. "FMKEY63,Fast master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x24 30. "FMKEY62,Fast master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 29. "FMKEY61,Fast master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x24 28. "FMKEY60,Fast master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 27. "FMKEY59,Fast master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x24 26. "FMKEY58,Fast master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 25. "FMKEY57,Fast master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x24 24. "FMKEY56,Fast master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 23. "FMKEY55,Fast master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x24 22. "FMKEY54,Fast master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 21. "FMKEY53,Fast master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x24 20. "FMKEY52,Fast master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 19. "FMKEY51,Fast master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x24 18. "FMKEY50,Fast master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 17. "FMKEY49,Fast master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x24 16. "FMKEY48,Fast master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 15. "FMKEY47,Fast master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x24 14. "FMKEY46,Fast master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 13. "FMKEY45,Fast master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x24 12. "FMKEY44,Fast master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 11. "FMKEY43,Fast master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x24 10. "FMKEY42,Fast master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 9. "FMKEY41,Fast master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x24 8. "FMKEY40,Fast master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 7. "FMKEY39,Fast master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x24 6. "FMKEY38,Fast master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 5. "FMKEY37,Fast master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x24 4. "FMKEY36,Fast master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 3. "FMKEY35,Fast master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x24 2. "FMKEY34,Fast master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 1. "FMKEY33,Fast master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x24 0. "FMKEY32,Fast master key bit 32 (i = 31 to 0)" "0,1" line.long 0x28 "MCE_FMKEYR2,MCE fast master key 2" bitfld.long 0x28 31. "FMKEY95,Fast master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x28 30. "FMKEY94,Fast master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 29. "FMKEY93,Fast master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x28 28. "FMKEY92,Fast master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 27. "FMKEY91,Fast master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x28 26. "FMKEY90,Fast master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 25. "FMKEY89,Fast master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x28 24. "FMKEY88,Fast master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 23. "FMKEY87,Fast master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x28 22. "FMKEY86,Fast master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 21. "FMKEY85,Fast master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x28 20. "FMKEY84,Fast master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 19. "FMKEY83,Fast master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x28 18. "FMKEY82,Fast master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 17. "FMKEY81,Fast master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x28 16. "FMKEY80,Fast master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 15. "FMKEY79,Fast master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x28 14. "FMKEY78,Fast master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 13. "FMKEY77,Fast master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x28 12. "FMKEY76,Fast master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 11. "FMKEY75,Fast master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x28 10. "FMKEY74,Fast master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 9. "FMKEY73,Fast master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x28 8. "FMKEY72,Fast master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 7. "FMKEY71,Fast master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x28 6. "FMKEY70,Fast master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 5. "FMKEY69,Fast master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x28 4. "FMKEY68,Fast master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 3. "FMKEY67,Fast master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x28 2. "FMKEY66,Fast master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 1. "FMKEY65,Fast master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x28 0. "FMKEY64,Fast master key bit 64 (i = 31 to 0)" "0,1" line.long 0x2C "MCE_FMKEYR3,MCE fast master key 3" bitfld.long 0x2C 31. "FMKEY127,Fast master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0x2C 30. "FMKEY126,Fast master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 29. "FMKEY125,Fast master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0x2C 28. "FMKEY124,Fast master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 27. "FMKEY123,Fast master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0x2C 26. "FMKEY122,Fast master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 25. "FMKEY121,Fast master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0x2C 24. "FMKEY120,Fast master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 23. "FMKEY119,Fast master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0x2C 22. "FMKEY118,Fast master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 21. "FMKEY117,Fast master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0x2C 20. "FMKEY116,Fast master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 19. "FMKEY115,Fast master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0x2C 18. "FMKEY114,Fast master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 17. "FMKEY113,Fast master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0x2C 16. "FMKEY112,Fast master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 15. "FMKEY111,Fast master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0x2C 14. "FMKEY110,Fast master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 13. "FMKEY109,Fast master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0x2C 12. "FMKEY108,Fast master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 11. "FMKEY107,Fast master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0x2C 10. "FMKEY106,Fast master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 9. "FMKEY105,Fast master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0x2C 8. "FMKEY104,Fast master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 7. "FMKEY103,Fast master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0x2C 6. "FMKEY102,Fast master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 5. "FMKEY101,Fast master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0x2C 4. "FMKEY100,Fast master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 3. "FMKEY99,Fast master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0x2C 2. "FMKEY98,Fast master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 1. "FMKEY97,Fast master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0x2C 0. "FMKEY96,Fast master key bit 96 (i = 31 to 0)" "0,1" line.long 0x30 "MCE_FMKEYR4,MCE fast master key 4" bitfld.long 0x30 31. "FMKEY159,Fast master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x30 30. "FMKEY158,Fast master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 29. "FMKEY157,Fast master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x30 28. "FMKEY156,Fast master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 27. "FMKEY155,Fast master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x30 26. "FMKEY154,Fast master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 25. "FMKEY153,Fast master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x30 24. "FMKEY152,Fast master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 23. "FMKEY151,Fast master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x30 22. "FMKEY150,Fast master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 21. "FMKEY149,Fast master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x30 20. "FMKEY148,Fast master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 19. "FMKEY147,Fast master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x30 18. "FMKEY146,Fast master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 17. "FMKEY145,Fast master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x30 16. "FMKEY144,Fast master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 15. "FMKEY143,Fast master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x30 14. "FMKEY142,Fast master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 13. "FMKEY141,Fast master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x30 12. "FMKEY140,Fast master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 11. "FMKEY139,Fast master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x30 10. "FMKEY138,Fast master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 9. "FMKEY137,Fast master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x30 8. "FMKEY136,Fast master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 7. "FMKEY135,Fast master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x30 6. "FMKEY134,Fast master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 5. "FMKEY133,Fast master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x30 4. "FMKEY132,Fast master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 3. "FMKEY131,Fast master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x30 2. "FMKEY130,Fast master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 1. "FMKEY129,Fast master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x30 0. "FMKEY128,Fast master key bit 128 (i = 31 to 0)" "0,1" line.long 0x34 "MCE_FMKEYR5,MCE fast master key 5" bitfld.long 0x34 31. "FMKEY191,Fast master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x34 30. "FMKEY190,Fast master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 29. "FMKEY189,Fast master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x34 28. "FMKEY188,Fast master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 27. "FMKEY187,Fast master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x34 26. "FMKEY186,Fast master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 25. "FMKEY185,Fast master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x34 24. "FMKEY184,Fast master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 23. "FMKEY183,Fast master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x34 22. "FMKEY182,Fast master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 21. "FMKEY181,Fast master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x34 20. "FMKEY180,Fast master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 19. "FMKEY179,Fast master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x34 18. "FMKEY178,Fast master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 17. "FMKEY177,Fast master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x34 16. "FMKEY176,Fast master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 15. "FMKEY175,Fast master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x34 14. "FMKEY174,Fast master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 13. "FMKEY173,Fast master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x34 12. "FMKEY172,Fast master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 11. "FMKEY171,Fast master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x34 10. "FMKEY170,Fast master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 9. "FMKEY169,Fast master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x34 8. "FMKEY168,Fast master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 7. "FMKEY167,Fast master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x34 6. "FMKEY166,Fast master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 5. "FMKEY165,Fast master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x34 4. "FMKEY164,Fast master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 3. "FMKEY163,Fast master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x34 2. "FMKEY162,Fast master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 1. "FMKEY161,Fast master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x34 0. "FMKEY160,Fast master key bit 160 (i = 31 to 0)" "0,1" line.long 0x38 "MCE_FMKEYR6,MCE fast master key 6" bitfld.long 0x38 31. "FMKEY223,Fast master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x38 30. "FMKEY222,Fast master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 29. "FMKEY221,Fast master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x38 28. "FMKEY220,Fast master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 27. "FMKEY219,Fast master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x38 26. "FMKEY218,Fast master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 25. "FMKEY217,Fast master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x38 24. "FMKEY216,Fast master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 23. "FMKEY215,Fast master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x38 22. "FMKEY214,Fast master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 21. "FMKEY213,Fast master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x38 20. "FMKEY212,Fast master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 19. "FMKEY211,Fast master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x38 18. "FMKEY210,Fast master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 17. "FMKEY209,Fast master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x38 16. "FMKEY208,Fast master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 15. "FMKEY207,Fast master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x38 14. "FMKEY206,Fast master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 13. "FMKEY205,Fast master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x38 12. "FMKEY204,Fast master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 11. "FMKEY203,Fast master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x38 10. "FMKEY202,Fast master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 9. "FMKEY201,Fast master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x38 8. "FMKEY200,Fast master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 7. "FMKEY199,Fast master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x38 6. "FMKEY198,Fast master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 5. "FMKEY197,Fast master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x38 4. "FMKEY196,Fast master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 3. "FMKEY195,Fast master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x38 2. "FMKEY194,Fast master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 1. "FMKEY193,Fast master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x38 0. "FMKEY192,Fast master key bit 192 (i = 31 to 0)" "0,1" line.long 0x3C "MCE_FMKEYR7,MCE fast master key 7" bitfld.long 0x3C 31. "FMKEY255,Fast master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x3C 30. "FMKEY254,Fast master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 29. "FMKEY253,Fast master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x3C 28. "FMKEY252,Fast master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 27. "FMKEY251,Fast master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x3C 26. "FMKEY250,Fast master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 25. "FMKEY249,Fast master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x3C 24. "FMKEY248,Fast master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 23. "FMKEY247,Fast master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x3C 22. "FMKEY246,Fast master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 21. "FMKEY245,Fast master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x3C 20. "FMKEY244,Fast master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 19. "FMKEY243,Fast master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x3C 18. "FMKEY242,Fast master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 17. "FMKEY241,Fast master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x3C 16. "FMKEY240,Fast master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 15. "FMKEY239,Fast master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x3C 14. "FMKEY238,Fast master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 13. "FMKEY237,Fast master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x3C 12. "FMKEY236,Fast master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 11. "FMKEY235,Fast master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x3C 10. "FMKEY234,Fast master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 9. "FMKEY233,Fast master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x3C 8. "FMKEY232,Fast master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 7. "FMKEY231,Fast master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x3C 6. "FMKEY230,Fast master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 5. "FMKEY229,Fast master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x3C 4. "FMKEY228,Fast master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 3. "FMKEY227,Fast master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x3C 2. "FMKEY226,Fast master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 1. "FMKEY225,Fast master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x3C 0. "FMKEY224,Fast master key bit 224 (i = 31 to 0)" "0,1" group.long 0x240++0xB line.long 0x0 "MCE_CC1CFGR,MCE cipher context 1 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC1NR0,MCE cipher context 1 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC1NR1,MCE cipher context 1 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x24C++0xF line.long 0x0 "MCE_CC1KEYR0,MCE cipher context 1 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC1KEYR1,MCE cipher context 1 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC1KEYR2,MCE cipher context 1 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC1KEYR3,MCE cipher context 1 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" group.long 0x270++0xB line.long 0x0 "MCE_CC2CFGR,MCE cipher context 2 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC2NR0,MCE cipher context 2 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC2NR1,MCE cipher context 2 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x27C++0xF line.long 0x0 "MCE_CC2KEYR0,MCE cipher context 2 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC2KEYR1,MCE cipher context 2 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC2KEYR2,MCE cipher context 2 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC2KEYR3,MCE cipher context 2 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" tree.end tree "MCE4" base ad:0x4802E000 group.long 0x0++0x3 line.long 0x0 "MCE_CR,MCE configuration register" bitfld.long 0x0 4.--5. "CIPHERSEL,Cipher selection" "0: No cipher is selected. Any read (resp. write) to..,1: AES-128 cipher selected for all encrypted regions,2: Noekeon cipher selected for all encrypted regions,3: AES-256 cipher selected for all encrypted regions" bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx and MCE_FMKEYRx registers..,1: Writes to MCE_MKEYRx and MCE_FMKEYRx registers.." newline bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.." rgroup.long 0x4++0x7 line.long 0x0 "MCE_SR,MCE status register" bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCRx all..,1: When ENC bit and BREN are set in any MCE_REGCRx.." bitfld.long 0x0 2. "FMKVALID,Fast master key valid" "0: A valid key has not been written in MCE_FMKEYRx..,1: A valid key has been written in MCE_FMKEYRx.." newline bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.." line.long 0x4 "MCE_IASR,MCE illegal access status register" bitfld.long 0x4 1. "IAEF,Illegal access error flag" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "MCE_IACR,MCE illegal access clear register" bitfld.long 0x0 1. "IAEF,Illegal access error flag clear" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register" bitfld.long 0x0 1. "IAEIE,Illegal access error interrupt enable" "0: Interrupt generation on illegal access errors is..,1: Interrupt generation when an illegal access.." rgroup.long 0x24++0x3 line.long 0x0 "MCE_IADDR,MCE illegal address register" hexmask.long 0x0 0.--31. 1. "IADD,Illegal address" group.long 0x40++0xB line.long 0x0 "MCE_REGCR1,MCE region 1 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR1,MCE start address for region 1 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR1,MCE end address for region 1 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x50++0xB line.long 0x0 "MCE_REGCR2,MCE region 2 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR2,MCE start address for region 2 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR2,MCE end address for region 2 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x60++0xB line.long 0x0 "MCE_REGCR3,MCE region 3 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR3,MCE start address for region 3 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR3,MCE end address for region 3 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x70++0xB line.long 0x0 "MCE_REGCR4,MCE region 4 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR4,MCE start address for region 4 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR4,MCE end address for region 4 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" wgroup.long 0x200++0x3F line.long 0x0 "MCE_MKEYR0,.MCE master key 0" bitfld.long 0x0 31. "MKEY31,Master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x0 30. "MKEY30,Master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 29. "MKEY29,Master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x0 28. "MKEY28,Master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 27. "MKEY27,Master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x0 26. "MKEY26,Master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 25. "MKEY25,Master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x0 24. "MKEY24,Master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 23. "MKEY23,Master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x0 22. "MKEY22,Master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 21. "MKEY21,Master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x0 20. "MKEY20,Master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 19. "MKEY19,Master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x0 18. "MKEY18,Master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 17. "MKEY17,Master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x0 16. "MKEY16,Master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 15. "MKEY15,Master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x0 14. "MKEY14,Master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 13. "MKEY13,Master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x0 12. "MKEY12,Master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 11. "MKEY11,Master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x0 10. "MKEY10,Master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 9. "MKEY9,Master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x0 8. "MKEY8,Master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 7. "MKEY7,Master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x0 6. "MKEY6,Master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 5. "MKEY5,Master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x0 4. "MKEY4,Master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 3. "MKEY3,Master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x0 2. "MKEY2,Master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 1. "MKEY1,Master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x0 0. "MKEY0,Master key bit 0 (i = 31 to 0)" "0,1" line.long 0x4 "MCE_MKEYR1,.MCE master key 1" bitfld.long 0x4 31. "MKEY63,Master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x4 30. "MKEY62,Master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 29. "MKEY61,Master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x4 28. "MKEY60,Master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 27. "MKEY59,Master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x4 26. "MKEY58,Master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 25. "MKEY57,Master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x4 24. "MKEY56,Master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 23. "MKEY55,Master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x4 22. "MKEY54,Master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 21. "MKEY53,Master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x4 20. "MKEY52,Master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 19. "MKEY51,Master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x4 18. "MKEY50,Master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 17. "MKEY49,Master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x4 16. "MKEY48,Master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 15. "MKEY47,Master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x4 14. "MKEY46,Master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 13. "MKEY45,Master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x4 12. "MKEY44,Master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 11. "MKEY43,Master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x4 10. "MKEY42,Master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 9. "MKEY41,Master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x4 8. "MKEY40,Master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 7. "MKEY39,Master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x4 6. "MKEY38,Master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 5. "MKEY37,Master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x4 4. "MKEY36,Master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 3. "MKEY35,Master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x4 2. "MKEY34,Master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 1. "MKEY33,Master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x4 0. "MKEY32,Master key bit 32 (i = 31 to 0)" "0,1" line.long 0x8 "MCE_MKEYR2,.MCE master key 2" bitfld.long 0x8 31. "MKEY95,Master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x8 30. "MKEY94,Master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 29. "MKEY93,Master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x8 28. "MKEY92,Master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 27. "MKEY91,Master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x8 26. "MKEY90,Master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 25. "MKEY89,Master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x8 24. "MKEY88,Master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 23. "MKEY87,Master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x8 22. "MKEY86,Master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 21. "MKEY85,Master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x8 20. "MKEY84,Master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 19. "MKEY83,Master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x8 18. "MKEY82,Master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 17. "MKEY81,Master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x8 16. "MKEY80,Master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 15. "MKEY79,Master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x8 14. "MKEY78,Master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 13. "MKEY77,Master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x8 12. "MKEY76,Master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 11. "MKEY75,Master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x8 10. "MKEY74,Master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 9. "MKEY73,Master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x8 8. "MKEY72,Master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 7. "MKEY71,Master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x8 6. "MKEY70,Master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 5. "MKEY69,Master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x8 4. "MKEY68,Master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 3. "MKEY67,Master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x8 2. "MKEY66,Master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 1. "MKEY65,Master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x8 0. "MKEY64,Master key bit 64 (i = 31 to 0)" "0,1" line.long 0xC "MCE_MKEYR3,.MCE master key 3" bitfld.long 0xC 31. "MKEY127,Master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0xC 30. "MKEY126,Master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 29. "MKEY125,Master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0xC 28. "MKEY124,Master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 27. "MKEY123,Master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0xC 26. "MKEY122,Master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 25. "MKEY121,Master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0xC 24. "MKEY120,Master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 23. "MKEY119,Master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0xC 22. "MKEY118,Master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 21. "MKEY117,Master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0xC 20. "MKEY116,Master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 19. "MKEY115,Master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0xC 18. "MKEY114,Master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 17. "MKEY113,Master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0xC 16. "MKEY112,Master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 15. "MKEY111,Master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0xC 14. "MKEY110,Master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 13. "MKEY109,Master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0xC 12. "MKEY108,Master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 11. "MKEY107,Master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0xC 10. "MKEY106,Master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 9. "MKEY105,Master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0xC 8. "MKEY104,Master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 7. "MKEY103,Master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0xC 6. "MKEY102,Master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 5. "MKEY101,Master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0xC 4. "MKEY100,Master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 3. "MKEY99,Master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0xC 2. "MKEY98,Master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 1. "MKEY97,Master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0xC 0. "MKEY96,Master key bit 96 (i = 31 to 0)" "0,1" line.long 0x10 "MCE_MKEYR4,.MCE master key 4" bitfld.long 0x10 31. "MKEY159,Master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x10 30. "MKEY158,Master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 29. "MKEY157,Master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x10 28. "MKEY156,Master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 27. "MKEY155,Master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x10 26. "MKEY154,Master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 25. "MKEY153,Master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x10 24. "MKEY152,Master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 23. "MKEY151,Master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x10 22. "MKEY150,Master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 21. "MKEY149,Master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x10 20. "MKEY148,Master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 19. "MKEY147,Master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x10 18. "MKEY146,Master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 17. "MKEY145,Master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x10 16. "MKEY144,Master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 15. "MKEY143,Master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x10 14. "MKEY142,Master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 13. "MKEY141,Master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x10 12. "MKEY140,Master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 11. "MKEY139,Master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x10 10. "MKEY138,Master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 9. "MKEY137,Master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x10 8. "MKEY136,Master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 7. "MKEY135,Master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x10 6. "MKEY134,Master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 5. "MKEY133,Master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x10 4. "MKEY132,Master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 3. "MKEY131,Master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x10 2. "MKEY130,Master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 1. "MKEY129,Master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x10 0. "MKEY128,Master key bit 128 (i = 31 to 0)" "0,1" line.long 0x14 "MCE_MKEYR5,.MCE master key 5" bitfld.long 0x14 31. "MKEY191,Master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x14 30. "MKEY190,Master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 29. "MKEY189,Master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x14 28. "MKEY188,Master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 27. "MKEY187,Master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x14 26. "MKEY186,Master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 25. "MKEY185,Master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x14 24. "MKEY184,Master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 23. "MKEY183,Master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x14 22. "MKEY182,Master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 21. "MKEY181,Master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x14 20. "MKEY180,Master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 19. "MKEY179,Master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x14 18. "MKEY178,Master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 17. "MKEY177,Master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x14 16. "MKEY176,Master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 15. "MKEY175,Master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x14 14. "MKEY174,Master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 13. "MKEY173,Master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x14 12. "MKEY172,Master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 11. "MKEY171,Master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x14 10. "MKEY170,Master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 9. "MKEY169,Master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x14 8. "MKEY168,Master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 7. "MKEY167,Master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x14 6. "MKEY166,Master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 5. "MKEY165,Master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x14 4. "MKEY164,Master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 3. "MKEY163,Master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x14 2. "MKEY162,Master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 1. "MKEY161,Master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x14 0. "MKEY160,Master key bit 160 (i = 31 to 0)" "0,1" line.long 0x18 "MCE_MKEYR6,.MCE master key 6" bitfld.long 0x18 31. "MKEY223,Master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x18 30. "MKEY222,Master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 29. "MKEY221,Master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x18 28. "MKEY220,Master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 27. "MKEY219,Master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x18 26. "MKEY218,Master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 25. "MKEY217,Master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x18 24. "MKEY216,Master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 23. "MKEY215,Master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x18 22. "MKEY214,Master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 21. "MKEY213,Master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x18 20. "MKEY212,Master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 19. "MKEY211,Master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x18 18. "MKEY210,Master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 17. "MKEY209,Master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x18 16. "MKEY208,Master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 15. "MKEY207,Master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x18 14. "MKEY206,Master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 13. "MKEY205,Master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x18 12. "MKEY204,Master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 11. "MKEY203,Master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x18 10. "MKEY202,Master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 9. "MKEY201,Master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x18 8. "MKEY200,Master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 7. "MKEY199,Master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x18 6. "MKEY198,Master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 5. "MKEY197,Master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x18 4. "MKEY196,Master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 3. "MKEY195,Master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x18 2. "MKEY194,Master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 1. "MKEY193,Master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x18 0. "MKEY192,Master key bit 192 (i = 31 to 0)" "0,1" line.long 0x1C "MCE_MKEYR7,.MCE master key 7" bitfld.long 0x1C 31. "MKEY255,Master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x1C 30. "MKEY254,Master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 29. "MKEY253,Master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x1C 28. "MKEY252,Master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 27. "MKEY251,Master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x1C 26. "MKEY250,Master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 25. "MKEY249,Master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x1C 24. "MKEY248,Master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 23. "MKEY247,Master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x1C 22. "MKEY246,Master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 21. "MKEY245,Master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x1C 20. "MKEY244,Master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 19. "MKEY243,Master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x1C 18. "MKEY242,Master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 17. "MKEY241,Master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x1C 16. "MKEY240,Master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 15. "MKEY239,Master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x1C 14. "MKEY238,Master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 13. "MKEY237,Master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x1C 12. "MKEY236,Master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 11. "MKEY235,Master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x1C 10. "MKEY234,Master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 9. "MKEY233,Master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x1C 8. "MKEY232,Master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 7. "MKEY231,Master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x1C 6. "MKEY230,Master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 5. "MKEY229,Master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x1C 4. "MKEY228,Master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 3. "MKEY227,Master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x1C 2. "MKEY226,Master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 1. "MKEY225,Master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x1C 0. "MKEY224,Master key bit 224 (i = 31 to 0)" "0,1" line.long 0x20 "MCE_FMKEYR0,MCE fast master key 0" bitfld.long 0x20 31. "FMKEY31,Fast master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x20 30. "FMKEY30,Fast master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 29. "FMKEY29,Fast master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x20 28. "FMKEY28,Fast master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 27. "FMKEY27,Fast master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x20 26. "FMKEY26,Fast master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 25. "FMKEY25,Fast master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x20 24. "FMKEY24,Fast master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 23. "FMKEY23,Fast master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x20 22. "FMKEY22,Fast master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 21. "FMKEY21,Fast master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x20 20. "FMKEY20,Fast master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 19. "FMKEY19,Fast master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x20 18. "FMKEY18,Fast master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 17. "FMKEY17,Fast master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x20 16. "FMKEY16,Fast master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 15. "FMKEY15,Fast master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x20 14. "FMKEY14,Fast master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 13. "FMKEY13,Fast master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x20 12. "FMKEY12,Fast master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 11. "FMKEY11,Fast master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x20 10. "FMKEY10,Fast master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 9. "FMKEY9,Fast master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x20 8. "FMKEY8,Fast master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 7. "FMKEY7,Fast master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x20 6. "FMKEY6,Fast master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 5. "FMKEY5,Fast master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x20 4. "FMKEY4,Fast master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 3. "FMKEY3,Fast master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x20 2. "FMKEY2,Fast master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 1. "FMKEY1,Fast master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x20 0. "FMKEY0,Fast master key bit 0 (i = 31 to 0)" "0,1" line.long 0x24 "MCE_FMKEYR1,MCE fast master key 1" bitfld.long 0x24 31. "FMKEY63,Fast master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x24 30. "FMKEY62,Fast master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 29. "FMKEY61,Fast master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x24 28. "FMKEY60,Fast master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 27. "FMKEY59,Fast master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x24 26. "FMKEY58,Fast master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 25. "FMKEY57,Fast master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x24 24. "FMKEY56,Fast master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 23. "FMKEY55,Fast master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x24 22. "FMKEY54,Fast master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 21. "FMKEY53,Fast master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x24 20. "FMKEY52,Fast master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 19. "FMKEY51,Fast master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x24 18. "FMKEY50,Fast master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 17. "FMKEY49,Fast master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x24 16. "FMKEY48,Fast master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 15. "FMKEY47,Fast master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x24 14. "FMKEY46,Fast master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 13. "FMKEY45,Fast master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x24 12. "FMKEY44,Fast master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 11. "FMKEY43,Fast master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x24 10. "FMKEY42,Fast master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 9. "FMKEY41,Fast master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x24 8. "FMKEY40,Fast master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 7. "FMKEY39,Fast master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x24 6. "FMKEY38,Fast master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 5. "FMKEY37,Fast master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x24 4. "FMKEY36,Fast master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 3. "FMKEY35,Fast master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x24 2. "FMKEY34,Fast master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 1. "FMKEY33,Fast master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x24 0. "FMKEY32,Fast master key bit 32 (i = 31 to 0)" "0,1" line.long 0x28 "MCE_FMKEYR2,MCE fast master key 2" bitfld.long 0x28 31. "FMKEY95,Fast master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x28 30. "FMKEY94,Fast master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 29. "FMKEY93,Fast master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x28 28. "FMKEY92,Fast master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 27. "FMKEY91,Fast master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x28 26. "FMKEY90,Fast master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 25. "FMKEY89,Fast master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x28 24. "FMKEY88,Fast master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 23. "FMKEY87,Fast master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x28 22. "FMKEY86,Fast master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 21. "FMKEY85,Fast master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x28 20. "FMKEY84,Fast master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 19. "FMKEY83,Fast master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x28 18. "FMKEY82,Fast master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 17. "FMKEY81,Fast master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x28 16. "FMKEY80,Fast master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 15. "FMKEY79,Fast master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x28 14. "FMKEY78,Fast master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 13. "FMKEY77,Fast master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x28 12. "FMKEY76,Fast master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 11. "FMKEY75,Fast master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x28 10. "FMKEY74,Fast master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 9. "FMKEY73,Fast master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x28 8. "FMKEY72,Fast master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 7. "FMKEY71,Fast master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x28 6. "FMKEY70,Fast master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 5. "FMKEY69,Fast master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x28 4. "FMKEY68,Fast master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 3. "FMKEY67,Fast master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x28 2. "FMKEY66,Fast master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 1. "FMKEY65,Fast master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x28 0. "FMKEY64,Fast master key bit 64 (i = 31 to 0)" "0,1" line.long 0x2C "MCE_FMKEYR3,MCE fast master key 3" bitfld.long 0x2C 31. "FMKEY127,Fast master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0x2C 30. "FMKEY126,Fast master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 29. "FMKEY125,Fast master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0x2C 28. "FMKEY124,Fast master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 27. "FMKEY123,Fast master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0x2C 26. "FMKEY122,Fast master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 25. "FMKEY121,Fast master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0x2C 24. "FMKEY120,Fast master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 23. "FMKEY119,Fast master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0x2C 22. "FMKEY118,Fast master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 21. "FMKEY117,Fast master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0x2C 20. "FMKEY116,Fast master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 19. "FMKEY115,Fast master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0x2C 18. "FMKEY114,Fast master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 17. "FMKEY113,Fast master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0x2C 16. "FMKEY112,Fast master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 15. "FMKEY111,Fast master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0x2C 14. "FMKEY110,Fast master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 13. "FMKEY109,Fast master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0x2C 12. "FMKEY108,Fast master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 11. "FMKEY107,Fast master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0x2C 10. "FMKEY106,Fast master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 9. "FMKEY105,Fast master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0x2C 8. "FMKEY104,Fast master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 7. "FMKEY103,Fast master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0x2C 6. "FMKEY102,Fast master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 5. "FMKEY101,Fast master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0x2C 4. "FMKEY100,Fast master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 3. "FMKEY99,Fast master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0x2C 2. "FMKEY98,Fast master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 1. "FMKEY97,Fast master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0x2C 0. "FMKEY96,Fast master key bit 96 (i = 31 to 0)" "0,1" line.long 0x30 "MCE_FMKEYR4,MCE fast master key 4" bitfld.long 0x30 31. "FMKEY159,Fast master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x30 30. "FMKEY158,Fast master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 29. "FMKEY157,Fast master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x30 28. "FMKEY156,Fast master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 27. "FMKEY155,Fast master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x30 26. "FMKEY154,Fast master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 25. "FMKEY153,Fast master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x30 24. "FMKEY152,Fast master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 23. "FMKEY151,Fast master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x30 22. "FMKEY150,Fast master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 21. "FMKEY149,Fast master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x30 20. "FMKEY148,Fast master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 19. "FMKEY147,Fast master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x30 18. "FMKEY146,Fast master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 17. "FMKEY145,Fast master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x30 16. "FMKEY144,Fast master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 15. "FMKEY143,Fast master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x30 14. "FMKEY142,Fast master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 13. "FMKEY141,Fast master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x30 12. "FMKEY140,Fast master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 11. "FMKEY139,Fast master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x30 10. "FMKEY138,Fast master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 9. "FMKEY137,Fast master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x30 8. "FMKEY136,Fast master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 7. "FMKEY135,Fast master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x30 6. "FMKEY134,Fast master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 5. "FMKEY133,Fast master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x30 4. "FMKEY132,Fast master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 3. "FMKEY131,Fast master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x30 2. "FMKEY130,Fast master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 1. "FMKEY129,Fast master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x30 0. "FMKEY128,Fast master key bit 128 (i = 31 to 0)" "0,1" line.long 0x34 "MCE_FMKEYR5,MCE fast master key 5" bitfld.long 0x34 31. "FMKEY191,Fast master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x34 30. "FMKEY190,Fast master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 29. "FMKEY189,Fast master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x34 28. "FMKEY188,Fast master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 27. "FMKEY187,Fast master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x34 26. "FMKEY186,Fast master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 25. "FMKEY185,Fast master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x34 24. "FMKEY184,Fast master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 23. "FMKEY183,Fast master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x34 22. "FMKEY182,Fast master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 21. "FMKEY181,Fast master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x34 20. "FMKEY180,Fast master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 19. "FMKEY179,Fast master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x34 18. "FMKEY178,Fast master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 17. "FMKEY177,Fast master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x34 16. "FMKEY176,Fast master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 15. "FMKEY175,Fast master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x34 14. "FMKEY174,Fast master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 13. "FMKEY173,Fast master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x34 12. "FMKEY172,Fast master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 11. "FMKEY171,Fast master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x34 10. "FMKEY170,Fast master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 9. "FMKEY169,Fast master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x34 8. "FMKEY168,Fast master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 7. "FMKEY167,Fast master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x34 6. "FMKEY166,Fast master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 5. "FMKEY165,Fast master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x34 4. "FMKEY164,Fast master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 3. "FMKEY163,Fast master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x34 2. "FMKEY162,Fast master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 1. "FMKEY161,Fast master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x34 0. "FMKEY160,Fast master key bit 160 (i = 31 to 0)" "0,1" line.long 0x38 "MCE_FMKEYR6,MCE fast master key 6" bitfld.long 0x38 31. "FMKEY223,Fast master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x38 30. "FMKEY222,Fast master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 29. "FMKEY221,Fast master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x38 28. "FMKEY220,Fast master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 27. "FMKEY219,Fast master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x38 26. "FMKEY218,Fast master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 25. "FMKEY217,Fast master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x38 24. "FMKEY216,Fast master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 23. "FMKEY215,Fast master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x38 22. "FMKEY214,Fast master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 21. "FMKEY213,Fast master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x38 20. "FMKEY212,Fast master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 19. "FMKEY211,Fast master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x38 18. "FMKEY210,Fast master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 17. "FMKEY209,Fast master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x38 16. "FMKEY208,Fast master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 15. "FMKEY207,Fast master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x38 14. "FMKEY206,Fast master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 13. "FMKEY205,Fast master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x38 12. "FMKEY204,Fast master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 11. "FMKEY203,Fast master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x38 10. "FMKEY202,Fast master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 9. "FMKEY201,Fast master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x38 8. "FMKEY200,Fast master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 7. "FMKEY199,Fast master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x38 6. "FMKEY198,Fast master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 5. "FMKEY197,Fast master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x38 4. "FMKEY196,Fast master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 3. "FMKEY195,Fast master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x38 2. "FMKEY194,Fast master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 1. "FMKEY193,Fast master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x38 0. "FMKEY192,Fast master key bit 192 (i = 31 to 0)" "0,1" line.long 0x3C "MCE_FMKEYR7,MCE fast master key 7" bitfld.long 0x3C 31. "FMKEY255,Fast master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x3C 30. "FMKEY254,Fast master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 29. "FMKEY253,Fast master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x3C 28. "FMKEY252,Fast master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 27. "FMKEY251,Fast master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x3C 26. "FMKEY250,Fast master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 25. "FMKEY249,Fast master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x3C 24. "FMKEY248,Fast master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 23. "FMKEY247,Fast master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x3C 22. "FMKEY246,Fast master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 21. "FMKEY245,Fast master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x3C 20. "FMKEY244,Fast master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 19. "FMKEY243,Fast master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x3C 18. "FMKEY242,Fast master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 17. "FMKEY241,Fast master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x3C 16. "FMKEY240,Fast master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 15. "FMKEY239,Fast master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x3C 14. "FMKEY238,Fast master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 13. "FMKEY237,Fast master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x3C 12. "FMKEY236,Fast master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 11. "FMKEY235,Fast master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x3C 10. "FMKEY234,Fast master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 9. "FMKEY233,Fast master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x3C 8. "FMKEY232,Fast master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 7. "FMKEY231,Fast master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x3C 6. "FMKEY230,Fast master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 5. "FMKEY229,Fast master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x3C 4. "FMKEY228,Fast master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 3. "FMKEY227,Fast master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x3C 2. "FMKEY226,Fast master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 1. "FMKEY225,Fast master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x3C 0. "FMKEY224,Fast master key bit 224 (i = 31 to 0)" "0,1" group.long 0x240++0xB line.long 0x0 "MCE_CC1CFGR,MCE cipher context 1 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC1NR0,MCE cipher context 1 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC1NR1,MCE cipher context 1 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x24C++0xF line.long 0x0 "MCE_CC1KEYR0,MCE cipher context 1 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC1KEYR1,MCE cipher context 1 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC1KEYR2,MCE cipher context 1 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC1KEYR3,MCE cipher context 1 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" group.long 0x270++0xB line.long 0x0 "MCE_CC2CFGR,MCE cipher context 2 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC2NR0,MCE cipher context 2 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC2NR1,MCE cipher context 2 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x27C++0xF line.long 0x0 "MCE_CC2KEYR0,MCE cipher context 2 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC2KEYR1,MCE cipher context 2 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC2KEYR2,MCE cipher context 2 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC2KEYR3,MCE cipher context 2 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" tree.end tree "MCE4_S" base ad:0x5802E000 group.long 0x0++0x3 line.long 0x0 "MCE_CR,MCE configuration register" bitfld.long 0x0 4.--5. "CIPHERSEL,Cipher selection" "0: No cipher is selected. Any read (resp. write) to..,1: AES-128 cipher selected for all encrypted regions,2: Noekeon cipher selected for all encrypted regions,3: AES-256 cipher selected for all encrypted regions" bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx and MCE_FMKEYRx registers..,1: Writes to MCE_MKEYRx and MCE_FMKEYRx registers.." newline bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.." rgroup.long 0x4++0x7 line.long 0x0 "MCE_SR,MCE status register" bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCRx all..,1: When ENC bit and BREN are set in any MCE_REGCRx.." bitfld.long 0x0 2. "FMKVALID,Fast master key valid" "0: A valid key has not been written in MCE_FMKEYRx..,1: A valid key has been written in MCE_FMKEYRx.." newline bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.." line.long 0x4 "MCE_IASR,MCE illegal access status register" bitfld.long 0x4 1. "IAEF,Illegal access error flag" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "MCE_IACR,MCE illegal access clear register" bitfld.long 0x0 1. "IAEF,Illegal access error flag clear" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register" bitfld.long 0x0 1. "IAEIE,Illegal access error interrupt enable" "0: Interrupt generation on illegal access errors is..,1: Interrupt generation when an illegal access.." rgroup.long 0x24++0x3 line.long 0x0 "MCE_IADDR,MCE illegal address register" hexmask.long 0x0 0.--31. 1. "IADD,Illegal address" group.long 0x40++0xB line.long 0x0 "MCE_REGCR1,MCE region 1 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR1,MCE start address for region 1 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR1,MCE end address for region 1 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x50++0xB line.long 0x0 "MCE_REGCR2,MCE region 2 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR2,MCE start address for region 2 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR2,MCE end address for region 2 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x60++0xB line.long 0x0 "MCE_REGCR3,MCE region 3 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR3,MCE start address for region 3 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR3,MCE end address for region 3 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" group.long 0x70++0xB line.long 0x0 "MCE_REGCR4,MCE region 4 configuration register" bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: Fast block cipher - All allowed read (resp." bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,?" newline bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.." line.long 0x4 "MCE_SADDR4,MCE start address for region 4 register" hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR4,MCE end address for region 4 register" hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end" wgroup.long 0x200++0x3F line.long 0x0 "MCE_MKEYR0,.MCE master key 0" bitfld.long 0x0 31. "MKEY31,Master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x0 30. "MKEY30,Master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 29. "MKEY29,Master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x0 28. "MKEY28,Master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 27. "MKEY27,Master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x0 26. "MKEY26,Master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 25. "MKEY25,Master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x0 24. "MKEY24,Master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 23. "MKEY23,Master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x0 22. "MKEY22,Master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 21. "MKEY21,Master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x0 20. "MKEY20,Master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 19. "MKEY19,Master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x0 18. "MKEY18,Master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 17. "MKEY17,Master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x0 16. "MKEY16,Master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 15. "MKEY15,Master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x0 14. "MKEY14,Master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 13. "MKEY13,Master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x0 12. "MKEY12,Master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 11. "MKEY11,Master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x0 10. "MKEY10,Master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 9. "MKEY9,Master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x0 8. "MKEY8,Master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 7. "MKEY7,Master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x0 6. "MKEY6,Master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 5. "MKEY5,Master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x0 4. "MKEY4,Master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 3. "MKEY3,Master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x0 2. "MKEY2,Master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x0 1. "MKEY1,Master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x0 0. "MKEY0,Master key bit 0 (i = 31 to 0)" "0,1" line.long 0x4 "MCE_MKEYR1,.MCE master key 1" bitfld.long 0x4 31. "MKEY63,Master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x4 30. "MKEY62,Master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 29. "MKEY61,Master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x4 28. "MKEY60,Master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 27. "MKEY59,Master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x4 26. "MKEY58,Master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 25. "MKEY57,Master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x4 24. "MKEY56,Master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 23. "MKEY55,Master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x4 22. "MKEY54,Master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 21. "MKEY53,Master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x4 20. "MKEY52,Master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 19. "MKEY51,Master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x4 18. "MKEY50,Master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 17. "MKEY49,Master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x4 16. "MKEY48,Master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 15. "MKEY47,Master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x4 14. "MKEY46,Master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 13. "MKEY45,Master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x4 12. "MKEY44,Master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 11. "MKEY43,Master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x4 10. "MKEY42,Master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 9. "MKEY41,Master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x4 8. "MKEY40,Master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 7. "MKEY39,Master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x4 6. "MKEY38,Master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 5. "MKEY37,Master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x4 4. "MKEY36,Master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 3. "MKEY35,Master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x4 2. "MKEY34,Master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x4 1. "MKEY33,Master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x4 0. "MKEY32,Master key bit 32 (i = 31 to 0)" "0,1" line.long 0x8 "MCE_MKEYR2,.MCE master key 2" bitfld.long 0x8 31. "MKEY95,Master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x8 30. "MKEY94,Master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 29. "MKEY93,Master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x8 28. "MKEY92,Master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 27. "MKEY91,Master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x8 26. "MKEY90,Master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 25. "MKEY89,Master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x8 24. "MKEY88,Master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 23. "MKEY87,Master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x8 22. "MKEY86,Master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 21. "MKEY85,Master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x8 20. "MKEY84,Master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 19. "MKEY83,Master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x8 18. "MKEY82,Master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 17. "MKEY81,Master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x8 16. "MKEY80,Master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 15. "MKEY79,Master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x8 14. "MKEY78,Master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 13. "MKEY77,Master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x8 12. "MKEY76,Master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 11. "MKEY75,Master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x8 10. "MKEY74,Master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 9. "MKEY73,Master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x8 8. "MKEY72,Master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 7. "MKEY71,Master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x8 6. "MKEY70,Master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 5. "MKEY69,Master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x8 4. "MKEY68,Master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 3. "MKEY67,Master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x8 2. "MKEY66,Master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x8 1. "MKEY65,Master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x8 0. "MKEY64,Master key bit 64 (i = 31 to 0)" "0,1" line.long 0xC "MCE_MKEYR3,.MCE master key 3" bitfld.long 0xC 31. "MKEY127,Master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0xC 30. "MKEY126,Master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 29. "MKEY125,Master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0xC 28. "MKEY124,Master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 27. "MKEY123,Master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0xC 26. "MKEY122,Master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 25. "MKEY121,Master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0xC 24. "MKEY120,Master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 23. "MKEY119,Master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0xC 22. "MKEY118,Master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 21. "MKEY117,Master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0xC 20. "MKEY116,Master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 19. "MKEY115,Master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0xC 18. "MKEY114,Master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 17. "MKEY113,Master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0xC 16. "MKEY112,Master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 15. "MKEY111,Master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0xC 14. "MKEY110,Master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 13. "MKEY109,Master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0xC 12. "MKEY108,Master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 11. "MKEY107,Master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0xC 10. "MKEY106,Master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 9. "MKEY105,Master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0xC 8. "MKEY104,Master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 7. "MKEY103,Master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0xC 6. "MKEY102,Master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 5. "MKEY101,Master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0xC 4. "MKEY100,Master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 3. "MKEY99,Master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0xC 2. "MKEY98,Master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0xC 1. "MKEY97,Master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0xC 0. "MKEY96,Master key bit 96 (i = 31 to 0)" "0,1" line.long 0x10 "MCE_MKEYR4,.MCE master key 4" bitfld.long 0x10 31. "MKEY159,Master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x10 30. "MKEY158,Master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 29. "MKEY157,Master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x10 28. "MKEY156,Master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 27. "MKEY155,Master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x10 26. "MKEY154,Master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 25. "MKEY153,Master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x10 24. "MKEY152,Master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 23. "MKEY151,Master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x10 22. "MKEY150,Master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 21. "MKEY149,Master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x10 20. "MKEY148,Master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 19. "MKEY147,Master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x10 18. "MKEY146,Master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 17. "MKEY145,Master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x10 16. "MKEY144,Master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 15. "MKEY143,Master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x10 14. "MKEY142,Master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 13. "MKEY141,Master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x10 12. "MKEY140,Master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 11. "MKEY139,Master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x10 10. "MKEY138,Master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 9. "MKEY137,Master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x10 8. "MKEY136,Master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 7. "MKEY135,Master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x10 6. "MKEY134,Master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 5. "MKEY133,Master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x10 4. "MKEY132,Master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 3. "MKEY131,Master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x10 2. "MKEY130,Master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x10 1. "MKEY129,Master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x10 0. "MKEY128,Master key bit 128 (i = 31 to 0)" "0,1" line.long 0x14 "MCE_MKEYR5,.MCE master key 5" bitfld.long 0x14 31. "MKEY191,Master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x14 30. "MKEY190,Master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 29. "MKEY189,Master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x14 28. "MKEY188,Master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 27. "MKEY187,Master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x14 26. "MKEY186,Master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 25. "MKEY185,Master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x14 24. "MKEY184,Master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 23. "MKEY183,Master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x14 22. "MKEY182,Master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 21. "MKEY181,Master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x14 20. "MKEY180,Master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 19. "MKEY179,Master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x14 18. "MKEY178,Master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 17. "MKEY177,Master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x14 16. "MKEY176,Master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 15. "MKEY175,Master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x14 14. "MKEY174,Master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 13. "MKEY173,Master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x14 12. "MKEY172,Master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 11. "MKEY171,Master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x14 10. "MKEY170,Master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 9. "MKEY169,Master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x14 8. "MKEY168,Master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 7. "MKEY167,Master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x14 6. "MKEY166,Master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 5. "MKEY165,Master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x14 4. "MKEY164,Master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 3. "MKEY163,Master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x14 2. "MKEY162,Master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x14 1. "MKEY161,Master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x14 0. "MKEY160,Master key bit 160 (i = 31 to 0)" "0,1" line.long 0x18 "MCE_MKEYR6,.MCE master key 6" bitfld.long 0x18 31. "MKEY223,Master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x18 30. "MKEY222,Master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 29. "MKEY221,Master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x18 28. "MKEY220,Master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 27. "MKEY219,Master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x18 26. "MKEY218,Master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 25. "MKEY217,Master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x18 24. "MKEY216,Master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 23. "MKEY215,Master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x18 22. "MKEY214,Master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 21. "MKEY213,Master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x18 20. "MKEY212,Master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 19. "MKEY211,Master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x18 18. "MKEY210,Master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 17. "MKEY209,Master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x18 16. "MKEY208,Master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 15. "MKEY207,Master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x18 14. "MKEY206,Master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 13. "MKEY205,Master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x18 12. "MKEY204,Master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 11. "MKEY203,Master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x18 10. "MKEY202,Master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 9. "MKEY201,Master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x18 8. "MKEY200,Master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 7. "MKEY199,Master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x18 6. "MKEY198,Master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 5. "MKEY197,Master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x18 4. "MKEY196,Master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 3. "MKEY195,Master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x18 2. "MKEY194,Master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x18 1. "MKEY193,Master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x18 0. "MKEY192,Master key bit 192 (i = 31 to 0)" "0,1" line.long 0x1C "MCE_MKEYR7,.MCE master key 7" bitfld.long 0x1C 31. "MKEY255,Master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x1C 30. "MKEY254,Master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 29. "MKEY253,Master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x1C 28. "MKEY252,Master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 27. "MKEY251,Master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x1C 26. "MKEY250,Master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 25. "MKEY249,Master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x1C 24. "MKEY248,Master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 23. "MKEY247,Master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x1C 22. "MKEY246,Master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 21. "MKEY245,Master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x1C 20. "MKEY244,Master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 19. "MKEY243,Master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x1C 18. "MKEY242,Master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 17. "MKEY241,Master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x1C 16. "MKEY240,Master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 15. "MKEY239,Master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x1C 14. "MKEY238,Master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 13. "MKEY237,Master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x1C 12. "MKEY236,Master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 11. "MKEY235,Master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x1C 10. "MKEY234,Master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 9. "MKEY233,Master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x1C 8. "MKEY232,Master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 7. "MKEY231,Master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x1C 6. "MKEY230,Master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 5. "MKEY229,Master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x1C 4. "MKEY228,Master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 3. "MKEY227,Master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x1C 2. "MKEY226,Master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x1C 1. "MKEY225,Master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x1C 0. "MKEY224,Master key bit 224 (i = 31 to 0)" "0,1" line.long 0x20 "MCE_FMKEYR0,MCE fast master key 0" bitfld.long 0x20 31. "FMKEY31,Fast master key bit 31 (i = 31 to 0)" "0,1" bitfld.long 0x20 30. "FMKEY30,Fast master key bit 30 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 29. "FMKEY29,Fast master key bit 29 (i = 31 to 0)" "0,1" bitfld.long 0x20 28. "FMKEY28,Fast master key bit 28 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 27. "FMKEY27,Fast master key bit 27 (i = 31 to 0)" "0,1" bitfld.long 0x20 26. "FMKEY26,Fast master key bit 26 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 25. "FMKEY25,Fast master key bit 25 (i = 31 to 0)" "0,1" bitfld.long 0x20 24. "FMKEY24,Fast master key bit 24 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 23. "FMKEY23,Fast master key bit 23 (i = 31 to 0)" "0,1" bitfld.long 0x20 22. "FMKEY22,Fast master key bit 22 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 21. "FMKEY21,Fast master key bit 21 (i = 31 to 0)" "0,1" bitfld.long 0x20 20. "FMKEY20,Fast master key bit 20 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 19. "FMKEY19,Fast master key bit 19 (i = 31 to 0)" "0,1" bitfld.long 0x20 18. "FMKEY18,Fast master key bit 18 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 17. "FMKEY17,Fast master key bit 17 (i = 31 to 0)" "0,1" bitfld.long 0x20 16. "FMKEY16,Fast master key bit 16 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 15. "FMKEY15,Fast master key bit 15 (i = 31 to 0)" "0,1" bitfld.long 0x20 14. "FMKEY14,Fast master key bit 14 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 13. "FMKEY13,Fast master key bit 13 (i = 31 to 0)" "0,1" bitfld.long 0x20 12. "FMKEY12,Fast master key bit 12 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 11. "FMKEY11,Fast master key bit 11 (i = 31 to 0)" "0,1" bitfld.long 0x20 10. "FMKEY10,Fast master key bit 10 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 9. "FMKEY9,Fast master key bit 9 (i = 31 to 0)" "0,1" bitfld.long 0x20 8. "FMKEY8,Fast master key bit 8 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 7. "FMKEY7,Fast master key bit 7 (i = 31 to 0)" "0,1" bitfld.long 0x20 6. "FMKEY6,Fast master key bit 6 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 5. "FMKEY5,Fast master key bit 5 (i = 31 to 0)" "0,1" bitfld.long 0x20 4. "FMKEY4,Fast master key bit 4 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 3. "FMKEY3,Fast master key bit 3 (i = 31 to 0)" "0,1" bitfld.long 0x20 2. "FMKEY2,Fast master key bit 2 (i = 31 to 0)" "0,1" newline bitfld.long 0x20 1. "FMKEY1,Fast master key bit 1 (i = 31 to 0)" "0,1" bitfld.long 0x20 0. "FMKEY0,Fast master key bit 0 (i = 31 to 0)" "0,1" line.long 0x24 "MCE_FMKEYR1,MCE fast master key 1" bitfld.long 0x24 31. "FMKEY63,Fast master key bit 63 (i = 31 to 0)" "0,1" bitfld.long 0x24 30. "FMKEY62,Fast master key bit 62 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 29. "FMKEY61,Fast master key bit 61 (i = 31 to 0)" "0,1" bitfld.long 0x24 28. "FMKEY60,Fast master key bit 60 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 27. "FMKEY59,Fast master key bit 59 (i = 31 to 0)" "0,1" bitfld.long 0x24 26. "FMKEY58,Fast master key bit 58 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 25. "FMKEY57,Fast master key bit 57 (i = 31 to 0)" "0,1" bitfld.long 0x24 24. "FMKEY56,Fast master key bit 56 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 23. "FMKEY55,Fast master key bit 55 (i = 31 to 0)" "0,1" bitfld.long 0x24 22. "FMKEY54,Fast master key bit 54 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 21. "FMKEY53,Fast master key bit 53 (i = 31 to 0)" "0,1" bitfld.long 0x24 20. "FMKEY52,Fast master key bit 52 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 19. "FMKEY51,Fast master key bit 51 (i = 31 to 0)" "0,1" bitfld.long 0x24 18. "FMKEY50,Fast master key bit 50 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 17. "FMKEY49,Fast master key bit 49 (i = 31 to 0)" "0,1" bitfld.long 0x24 16. "FMKEY48,Fast master key bit 48 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 15. "FMKEY47,Fast master key bit 47 (i = 31 to 0)" "0,1" bitfld.long 0x24 14. "FMKEY46,Fast master key bit 46 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 13. "FMKEY45,Fast master key bit 45 (i = 31 to 0)" "0,1" bitfld.long 0x24 12. "FMKEY44,Fast master key bit 44 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 11. "FMKEY43,Fast master key bit 43 (i = 31 to 0)" "0,1" bitfld.long 0x24 10. "FMKEY42,Fast master key bit 42 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 9. "FMKEY41,Fast master key bit 41 (i = 31 to 0)" "0,1" bitfld.long 0x24 8. "FMKEY40,Fast master key bit 40 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 7. "FMKEY39,Fast master key bit 39 (i = 31 to 0)" "0,1" bitfld.long 0x24 6. "FMKEY38,Fast master key bit 38 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 5. "FMKEY37,Fast master key bit 37 (i = 31 to 0)" "0,1" bitfld.long 0x24 4. "FMKEY36,Fast master key bit 36 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 3. "FMKEY35,Fast master key bit 35 (i = 31 to 0)" "0,1" bitfld.long 0x24 2. "FMKEY34,Fast master key bit 34 (i = 31 to 0)" "0,1" newline bitfld.long 0x24 1. "FMKEY33,Fast master key bit 33 (i = 31 to 0)" "0,1" bitfld.long 0x24 0. "FMKEY32,Fast master key bit 32 (i = 31 to 0)" "0,1" line.long 0x28 "MCE_FMKEYR2,MCE fast master key 2" bitfld.long 0x28 31. "FMKEY95,Fast master key bit 95 (i = 31 to 0)" "0,1" bitfld.long 0x28 30. "FMKEY94,Fast master key bit 94 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 29. "FMKEY93,Fast master key bit 93 (i = 31 to 0)" "0,1" bitfld.long 0x28 28. "FMKEY92,Fast master key bit 92 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 27. "FMKEY91,Fast master key bit 91 (i = 31 to 0)" "0,1" bitfld.long 0x28 26. "FMKEY90,Fast master key bit 90 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 25. "FMKEY89,Fast master key bit 89 (i = 31 to 0)" "0,1" bitfld.long 0x28 24. "FMKEY88,Fast master key bit 88 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 23. "FMKEY87,Fast master key bit 87 (i = 31 to 0)" "0,1" bitfld.long 0x28 22. "FMKEY86,Fast master key bit 86 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 21. "FMKEY85,Fast master key bit 85 (i = 31 to 0)" "0,1" bitfld.long 0x28 20. "FMKEY84,Fast master key bit 84 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 19. "FMKEY83,Fast master key bit 83 (i = 31 to 0)" "0,1" bitfld.long 0x28 18. "FMKEY82,Fast master key bit 82 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 17. "FMKEY81,Fast master key bit 81 (i = 31 to 0)" "0,1" bitfld.long 0x28 16. "FMKEY80,Fast master key bit 80 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 15. "FMKEY79,Fast master key bit 79 (i = 31 to 0)" "0,1" bitfld.long 0x28 14. "FMKEY78,Fast master key bit 78 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 13. "FMKEY77,Fast master key bit 77 (i = 31 to 0)" "0,1" bitfld.long 0x28 12. "FMKEY76,Fast master key bit 76 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 11. "FMKEY75,Fast master key bit 75 (i = 31 to 0)" "0,1" bitfld.long 0x28 10. "FMKEY74,Fast master key bit 74 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 9. "FMKEY73,Fast master key bit 73 (i = 31 to 0)" "0,1" bitfld.long 0x28 8. "FMKEY72,Fast master key bit 72 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 7. "FMKEY71,Fast master key bit 71 (i = 31 to 0)" "0,1" bitfld.long 0x28 6. "FMKEY70,Fast master key bit 70 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 5. "FMKEY69,Fast master key bit 69 (i = 31 to 0)" "0,1" bitfld.long 0x28 4. "FMKEY68,Fast master key bit 68 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 3. "FMKEY67,Fast master key bit 67 (i = 31 to 0)" "0,1" bitfld.long 0x28 2. "FMKEY66,Fast master key bit 66 (i = 31 to 0)" "0,1" newline bitfld.long 0x28 1. "FMKEY65,Fast master key bit 65 (i = 31 to 0)" "0,1" bitfld.long 0x28 0. "FMKEY64,Fast master key bit 64 (i = 31 to 0)" "0,1" line.long 0x2C "MCE_FMKEYR3,MCE fast master key 3" bitfld.long 0x2C 31. "FMKEY127,Fast master key bit 127 (i = 31 to 0)" "0,1" bitfld.long 0x2C 30. "FMKEY126,Fast master key bit 126 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 29. "FMKEY125,Fast master key bit 125 (i = 31 to 0)" "0,1" bitfld.long 0x2C 28. "FMKEY124,Fast master key bit 124 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 27. "FMKEY123,Fast master key bit 123 (i = 31 to 0)" "0,1" bitfld.long 0x2C 26. "FMKEY122,Fast master key bit 122 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 25. "FMKEY121,Fast master key bit 121 (i = 31 to 0)" "0,1" bitfld.long 0x2C 24. "FMKEY120,Fast master key bit 120 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 23. "FMKEY119,Fast master key bit 119 (i = 31 to 0)" "0,1" bitfld.long 0x2C 22. "FMKEY118,Fast master key bit 118 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 21. "FMKEY117,Fast master key bit 117 (i = 31 to 0)" "0,1" bitfld.long 0x2C 20. "FMKEY116,Fast master key bit 116 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 19. "FMKEY115,Fast master key bit 115 (i = 31 to 0)" "0,1" bitfld.long 0x2C 18. "FMKEY114,Fast master key bit 114 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 17. "FMKEY113,Fast master key bit 113 (i = 31 to 0)" "0,1" bitfld.long 0x2C 16. "FMKEY112,Fast master key bit 112 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 15. "FMKEY111,Fast master key bit 111 (i = 31 to 0)" "0,1" bitfld.long 0x2C 14. "FMKEY110,Fast master key bit 110 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 13. "FMKEY109,Fast master key bit 109 (i = 31 to 0)" "0,1" bitfld.long 0x2C 12. "FMKEY108,Fast master key bit 108 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 11. "FMKEY107,Fast master key bit 107 (i = 31 to 0)" "0,1" bitfld.long 0x2C 10. "FMKEY106,Fast master key bit 106 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 9. "FMKEY105,Fast master key bit 105 (i = 31 to 0)" "0,1" bitfld.long 0x2C 8. "FMKEY104,Fast master key bit 104 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 7. "FMKEY103,Fast master key bit 103 (i = 31 to 0)" "0,1" bitfld.long 0x2C 6. "FMKEY102,Fast master key bit 102 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 5. "FMKEY101,Fast master key bit 101 (i = 31 to 0)" "0,1" bitfld.long 0x2C 4. "FMKEY100,Fast master key bit 100 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 3. "FMKEY99,Fast master key bit 99 (i = 31 to 0)" "0,1" bitfld.long 0x2C 2. "FMKEY98,Fast master key bit 98 (i = 31 to 0)" "0,1" newline bitfld.long 0x2C 1. "FMKEY97,Fast master key bit 97 (i = 31 to 0)" "0,1" bitfld.long 0x2C 0. "FMKEY96,Fast master key bit 96 (i = 31 to 0)" "0,1" line.long 0x30 "MCE_FMKEYR4,MCE fast master key 4" bitfld.long 0x30 31. "FMKEY159,Fast master key bit 159 (i = 31 to 0)" "0,1" bitfld.long 0x30 30. "FMKEY158,Fast master key bit 158 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 29. "FMKEY157,Fast master key bit 157 (i = 31 to 0)" "0,1" bitfld.long 0x30 28. "FMKEY156,Fast master key bit 156 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 27. "FMKEY155,Fast master key bit 155 (i = 31 to 0)" "0,1" bitfld.long 0x30 26. "FMKEY154,Fast master key bit 154 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 25. "FMKEY153,Fast master key bit 153 (i = 31 to 0)" "0,1" bitfld.long 0x30 24. "FMKEY152,Fast master key bit 152 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 23. "FMKEY151,Fast master key bit 151 (i = 31 to 0)" "0,1" bitfld.long 0x30 22. "FMKEY150,Fast master key bit 150 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 21. "FMKEY149,Fast master key bit 149 (i = 31 to 0)" "0,1" bitfld.long 0x30 20. "FMKEY148,Fast master key bit 148 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 19. "FMKEY147,Fast master key bit 147 (i = 31 to 0)" "0,1" bitfld.long 0x30 18. "FMKEY146,Fast master key bit 146 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 17. "FMKEY145,Fast master key bit 145 (i = 31 to 0)" "0,1" bitfld.long 0x30 16. "FMKEY144,Fast master key bit 144 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 15. "FMKEY143,Fast master key bit 143 (i = 31 to 0)" "0,1" bitfld.long 0x30 14. "FMKEY142,Fast master key bit 142 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 13. "FMKEY141,Fast master key bit 141 (i = 31 to 0)" "0,1" bitfld.long 0x30 12. "FMKEY140,Fast master key bit 140 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 11. "FMKEY139,Fast master key bit 139 (i = 31 to 0)" "0,1" bitfld.long 0x30 10. "FMKEY138,Fast master key bit 138 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 9. "FMKEY137,Fast master key bit 137 (i = 31 to 0)" "0,1" bitfld.long 0x30 8. "FMKEY136,Fast master key bit 136 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 7. "FMKEY135,Fast master key bit 135 (i = 31 to 0)" "0,1" bitfld.long 0x30 6. "FMKEY134,Fast master key bit 134 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 5. "FMKEY133,Fast master key bit 133 (i = 31 to 0)" "0,1" bitfld.long 0x30 4. "FMKEY132,Fast master key bit 132 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 3. "FMKEY131,Fast master key bit 131 (i = 31 to 0)" "0,1" bitfld.long 0x30 2. "FMKEY130,Fast master key bit 130 (i = 31 to 0)" "0,1" newline bitfld.long 0x30 1. "FMKEY129,Fast master key bit 129 (i = 31 to 0)" "0,1" bitfld.long 0x30 0. "FMKEY128,Fast master key bit 128 (i = 31 to 0)" "0,1" line.long 0x34 "MCE_FMKEYR5,MCE fast master key 5" bitfld.long 0x34 31. "FMKEY191,Fast master key bit 191 (i = 31 to 0)" "0,1" bitfld.long 0x34 30. "FMKEY190,Fast master key bit 190 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 29. "FMKEY189,Fast master key bit 189 (i = 31 to 0)" "0,1" bitfld.long 0x34 28. "FMKEY188,Fast master key bit 188 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 27. "FMKEY187,Fast master key bit 187 (i = 31 to 0)" "0,1" bitfld.long 0x34 26. "FMKEY186,Fast master key bit 186 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 25. "FMKEY185,Fast master key bit 185 (i = 31 to 0)" "0,1" bitfld.long 0x34 24. "FMKEY184,Fast master key bit 184 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 23. "FMKEY183,Fast master key bit 183 (i = 31 to 0)" "0,1" bitfld.long 0x34 22. "FMKEY182,Fast master key bit 182 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 21. "FMKEY181,Fast master key bit 181 (i = 31 to 0)" "0,1" bitfld.long 0x34 20. "FMKEY180,Fast master key bit 180 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 19. "FMKEY179,Fast master key bit 179 (i = 31 to 0)" "0,1" bitfld.long 0x34 18. "FMKEY178,Fast master key bit 178 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 17. "FMKEY177,Fast master key bit 177 (i = 31 to 0)" "0,1" bitfld.long 0x34 16. "FMKEY176,Fast master key bit 176 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 15. "FMKEY175,Fast master key bit 175 (i = 31 to 0)" "0,1" bitfld.long 0x34 14. "FMKEY174,Fast master key bit 174 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 13. "FMKEY173,Fast master key bit 173 (i = 31 to 0)" "0,1" bitfld.long 0x34 12. "FMKEY172,Fast master key bit 172 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 11. "FMKEY171,Fast master key bit 171 (i = 31 to 0)" "0,1" bitfld.long 0x34 10. "FMKEY170,Fast master key bit 170 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 9. "FMKEY169,Fast master key bit 169 (i = 31 to 0)" "0,1" bitfld.long 0x34 8. "FMKEY168,Fast master key bit 168 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 7. "FMKEY167,Fast master key bit 167 (i = 31 to 0)" "0,1" bitfld.long 0x34 6. "FMKEY166,Fast master key bit 166 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 5. "FMKEY165,Fast master key bit 165 (i = 31 to 0)" "0,1" bitfld.long 0x34 4. "FMKEY164,Fast master key bit 164 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 3. "FMKEY163,Fast master key bit 163 (i = 31 to 0)" "0,1" bitfld.long 0x34 2. "FMKEY162,Fast master key bit 162 (i = 31 to 0)" "0,1" newline bitfld.long 0x34 1. "FMKEY161,Fast master key bit 161 (i = 31 to 0)" "0,1" bitfld.long 0x34 0. "FMKEY160,Fast master key bit 160 (i = 31 to 0)" "0,1" line.long 0x38 "MCE_FMKEYR6,MCE fast master key 6" bitfld.long 0x38 31. "FMKEY223,Fast master key bit 223 (i = 31 to 0)" "0,1" bitfld.long 0x38 30. "FMKEY222,Fast master key bit 222 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 29. "FMKEY221,Fast master key bit 221 (i = 31 to 0)" "0,1" bitfld.long 0x38 28. "FMKEY220,Fast master key bit 220 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 27. "FMKEY219,Fast master key bit 219 (i = 31 to 0)" "0,1" bitfld.long 0x38 26. "FMKEY218,Fast master key bit 218 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 25. "FMKEY217,Fast master key bit 217 (i = 31 to 0)" "0,1" bitfld.long 0x38 24. "FMKEY216,Fast master key bit 216 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 23. "FMKEY215,Fast master key bit 215 (i = 31 to 0)" "0,1" bitfld.long 0x38 22. "FMKEY214,Fast master key bit 214 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 21. "FMKEY213,Fast master key bit 213 (i = 31 to 0)" "0,1" bitfld.long 0x38 20. "FMKEY212,Fast master key bit 212 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 19. "FMKEY211,Fast master key bit 211 (i = 31 to 0)" "0,1" bitfld.long 0x38 18. "FMKEY210,Fast master key bit 210 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 17. "FMKEY209,Fast master key bit 209 (i = 31 to 0)" "0,1" bitfld.long 0x38 16. "FMKEY208,Fast master key bit 208 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 15. "FMKEY207,Fast master key bit 207 (i = 31 to 0)" "0,1" bitfld.long 0x38 14. "FMKEY206,Fast master key bit 206 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 13. "FMKEY205,Fast master key bit 205 (i = 31 to 0)" "0,1" bitfld.long 0x38 12. "FMKEY204,Fast master key bit 204 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 11. "FMKEY203,Fast master key bit 203 (i = 31 to 0)" "0,1" bitfld.long 0x38 10. "FMKEY202,Fast master key bit 202 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 9. "FMKEY201,Fast master key bit 201 (i = 31 to 0)" "0,1" bitfld.long 0x38 8. "FMKEY200,Fast master key bit 200 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 7. "FMKEY199,Fast master key bit 199 (i = 31 to 0)" "0,1" bitfld.long 0x38 6. "FMKEY198,Fast master key bit 198 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 5. "FMKEY197,Fast master key bit 197 (i = 31 to 0)" "0,1" bitfld.long 0x38 4. "FMKEY196,Fast master key bit 196 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 3. "FMKEY195,Fast master key bit 195 (i = 31 to 0)" "0,1" bitfld.long 0x38 2. "FMKEY194,Fast master key bit 194 (i = 31 to 0)" "0,1" newline bitfld.long 0x38 1. "FMKEY193,Fast master key bit 193 (i = 31 to 0)" "0,1" bitfld.long 0x38 0. "FMKEY192,Fast master key bit 192 (i = 31 to 0)" "0,1" line.long 0x3C "MCE_FMKEYR7,MCE fast master key 7" bitfld.long 0x3C 31. "FMKEY255,Fast master key bit 255 (i = 31 to 0)" "0,1" bitfld.long 0x3C 30. "FMKEY254,Fast master key bit 254 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 29. "FMKEY253,Fast master key bit 253 (i = 31 to 0)" "0,1" bitfld.long 0x3C 28. "FMKEY252,Fast master key bit 252 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 27. "FMKEY251,Fast master key bit 251 (i = 31 to 0)" "0,1" bitfld.long 0x3C 26. "FMKEY250,Fast master key bit 250 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 25. "FMKEY249,Fast master key bit 249 (i = 31 to 0)" "0,1" bitfld.long 0x3C 24. "FMKEY248,Fast master key bit 248 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 23. "FMKEY247,Fast master key bit 247 (i = 31 to 0)" "0,1" bitfld.long 0x3C 22. "FMKEY246,Fast master key bit 246 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 21. "FMKEY245,Fast master key bit 245 (i = 31 to 0)" "0,1" bitfld.long 0x3C 20. "FMKEY244,Fast master key bit 244 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 19. "FMKEY243,Fast master key bit 243 (i = 31 to 0)" "0,1" bitfld.long 0x3C 18. "FMKEY242,Fast master key bit 242 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 17. "FMKEY241,Fast master key bit 241 (i = 31 to 0)" "0,1" bitfld.long 0x3C 16. "FMKEY240,Fast master key bit 240 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 15. "FMKEY239,Fast master key bit 239 (i = 31 to 0)" "0,1" bitfld.long 0x3C 14. "FMKEY238,Fast master key bit 238 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 13. "FMKEY237,Fast master key bit 237 (i = 31 to 0)" "0,1" bitfld.long 0x3C 12. "FMKEY236,Fast master key bit 236 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 11. "FMKEY235,Fast master key bit 235 (i = 31 to 0)" "0,1" bitfld.long 0x3C 10. "FMKEY234,Fast master key bit 234 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 9. "FMKEY233,Fast master key bit 233 (i = 31 to 0)" "0,1" bitfld.long 0x3C 8. "FMKEY232,Fast master key bit 232 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 7. "FMKEY231,Fast master key bit 231 (i = 31 to 0)" "0,1" bitfld.long 0x3C 6. "FMKEY230,Fast master key bit 230 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 5. "FMKEY229,Fast master key bit 229 (i = 31 to 0)" "0,1" bitfld.long 0x3C 4. "FMKEY228,Fast master key bit 228 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 3. "FMKEY227,Fast master key bit 227 (i = 31 to 0)" "0,1" bitfld.long 0x3C 2. "FMKEY226,Fast master key bit 226 (i = 31 to 0)" "0,1" newline bitfld.long 0x3C 1. "FMKEY225,Fast master key bit 225 (i = 31 to 0)" "0,1" bitfld.long 0x3C 0. "FMKEY224,Fast master key bit 224 (i = 31 to 0)" "0,1" group.long 0x240++0xB line.long 0x0 "MCE_CC1CFGR,MCE cipher context 1 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC1NR0,MCE cipher context 1 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC1NR1,MCE cipher context 1 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x24C++0xF line.long 0x0 "MCE_CC1KEYR0,MCE cipher context 1 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC1KEYR1,MCE cipher context 1 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC1KEYR2,MCE cipher context 1 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC1KEYR3,MCE cipher context 1 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" group.long 0x270++0xB line.long 0x0 "MCE_CC2CFGR,MCE cipher context 2 configuration register" hexmask.long.word 0x0 16.--31. 1. "VERSION,Version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC" newline bitfld.long 0x0 4.--5. "MODE,Authorized cipher mode" "?,?,2: Block cipher is allowed with this cipher context,3: Fast block cipher is allowed with this cipher.." bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.." newline bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.." bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.." line.long 0x4 "MCE_CC2NR0,MCE cipher context 2 nonce register 0" hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]" line.long 0x8 "MCE_CC2NR1,MCE cipher context 2 nonce register 1" hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]" wgroup.long 0x27C++0xF line.long 0x0 "MCE_CC2KEYR0,MCE cipher context 2 key register 0" hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]" line.long 0x4 "MCE_CC2KEYR1,MCE cipher context 2 key register 1" hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]" line.long 0x8 "MCE_CC2KEYR2,MCE cipher context 2 key register 2" hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]" line.long 0xC "MCE_CC2KEYR3,MCE cipher context 2 key register 3" hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]" tree.end tree.end endif tree "MDF (Multi-function Digital Filter)" base ad:0x0 tree "MDF1" base ad:0x42025000 group.long 0x0++0x7 line.long 0x0 "MDF_GCR,MDF global control register" hexmask.long.byte 0x0 4.--7. 1. "ILVNB,Interleaved number" bitfld.long 0x0 0. "TRGO,Trigger output control" "0: Write 0 has no effect. Read 0 means that the..,1: Write 1 generates a positive pulse on mdf_trgo.." line.long 0x4 "MDF_CKGCR,MDF clock generator control register" rbitfld.long 0x4 31. "CKGACTIVE,Clock generator active flag" "0: The clock generator is not active and can be..,1: The clock generator is active and protected.." hexmask.long.byte 0x4 24.--30. 1. "PROCDIV,Divider to control the serial interface clock" newline hexmask.long.byte 0x4 16.--19. 1. "CCKDIV,Divider to control the MDF_CCK clock" hexmask.long.byte 0x4 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" newline bitfld.long 0x4 8. "TRGSENS,CKGEN trigger sensitivity selection" "0: A rising edge event triggers the activation of..,1: A falling edge even triggers the activation of.." bitfld.long 0x4 6. "CCK1DIR,MDF_CCK1 direction" "0: MDF_CCK1 pin direction is in input.,1: MDF_CCK1 pin direction is in output." newline bitfld.long 0x4 5. "CCK0DIR,MDF_CCK0 direction" "0: MDF_CCK0 pin direction is in input.,1: MDF_CCK0 pin direction is in output." bitfld.long 0x4 4. "CKGMOD,Clock generator mode" "0: The kernel clock is provided to the dividers as..,1: The kernel clock is provided to the dividers.." newline bitfld.long 0x4 2. "CCK1EN,MDF_CCK1 clock enable" "0: Bitstream clock not generated,1: Bitstream clock generated on the MDF_CCK1 pad" bitfld.long 0x4 1. "CCK0EN,MDF_CCK0 clock enable" "0: Bitstream clock not generated,1: Bitstream clock generated on the MDF_CCK0 pad" newline bitfld.long 0x4 0. "CKGDEN,CKGEN dividers enable" "0: CKGEN dividers disabled,1: CKGEN dividers enabled" group.long 0x80++0x37 line.long 0x0 "MDF_SITF0CR,MDF serial interface control register 0" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX0CR,MDF bitstream matrix control register 0" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT0CR,MDF digital filter control register 0" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT0CICR,MDF digital filter configuration register 0" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT0RSFR,MDF reshape filter configuration register 0" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT0INTR,MDF integrator configuration register 0" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD0CR,MDF out-of limit detector control register 0" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD0THLR,MDF OLD0 low threshold register 0" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD0THHR,MDF OLD0 high threshold register 0" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY0CR,MDF delay control register 0" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD0CR,MDF short circuit detector control register 0" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT0IER,MDF DFLT0 interrupt enable register 0" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCD0 interrupt enable" "0: SCD0 interrupt disabled,1: SCD0 interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLD0 interrupt enable" "0: OLD0 event interrupt disabled,1: OLD0 event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT0ISR,MDF DFLT0 interrupt status register 0" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD0 event is detected.,1: Read 1 means that a SCD0 event is detected." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLD0 flag" "0: Read 0 means that no OLD0 event is detected.,1: Read 1 means that an OLD0 event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC0CR,MDF offset error compensation control register 0" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0xEC++0x7 line.long 0x0 "MDF_SNPS0DR,MDF snapshot data register 0" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT0DR,MDF digital filter data register 0" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" group.long 0x100++0x37 line.long 0x0 "MDF_SITF1CR,MDF serial interface control register 1" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX1CR,MDF bitstream matrix control register 1" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT1CR,MDF digital filter control register 1" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT1CICR,MDF digital filter configuration register 1" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT1RSFR,MDF reshape filter configuration register 1" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT1INTR,MDF integrator configuration register 1" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD1CR,MDF out-of limit detector control register 1" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD1THLR,MDF OLD1 low threshold register 1" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD1THHR,MDF OLD1 high threshold register 1" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY1CR,MDF delay control register 1" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD1CR,MDF short circuit detector control register 1" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT1IER,MDF DFLT1 interrupt enable register 1" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCDx interrupt enable" "0: SCDx interrupt disabled,1: SCDx interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLDx interrupt enable" "0: OLDx event interrupt disabled,1: OLDx event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT1ISR,MDF DFLT1 interrupt status register 1" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD event is detected.,1: Read 1 means that a SCD event is detected. Write.." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLDx flag" "0: Read 0 means that no OLDx event is detected.,1: Read 1 means that an OLDx event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC1CR,MDF offset error compensation control register 1" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0x16C++0x7 line.long 0x0 "MDF_SNPS1DR,MDF snapshot data register 1" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT1DR,MDF digital filter data register 1" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" group.long 0x180++0x37 line.long 0x0 "MDF_SITF2CR,MDF serial interface control register 2" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX2CR,MDF bitstream matrix control register 2" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT2CR,MDF digital filter control register 2" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT2CICR,MDF digital filter configuration register 2" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT2RSFR,MDF reshape filter configuration register 2" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT2INTR,MDF integrator configuration register 2" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD2CR,MDF out-of limit detector control register 2" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD2THLR,MDF OLD2 low threshold register 2" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD2THHR,MDF OLD2 high threshold register 2" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY2CR,MDF delay control register 2" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD2CR,MDF short circuit detector control register 2" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT2IER,MDF DFLT2 interrupt enable register 2" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCDx interrupt enable" "0: SCDx interrupt disabled,1: SCDx interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLDx interrupt enable" "0: OLDx event interrupt disabled,1: OLDx event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT2ISR,MDF DFLT2 interrupt status register 2" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD event is detected.,1: Read 1 means that a SCD event is detected. Write.." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLDx flag" "0: Read 0 means that no OLDx event is detected.,1: Read 1 means that an OLDx event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC2CR,MDF offset error compensation control register 2" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0x1EC++0x7 line.long 0x0 "MDF_SNPS2DR,MDF snapshot data register 2" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT2DR,MDF digital filter data register 2" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" group.long 0x200++0x37 line.long 0x0 "MDF_SITF3CR,MDF serial interface control register 3" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX3CR,MDF bitstream matrix control register 3" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT3CR,MDF digital filter control register 3" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT3CICR,MDF digital filter configuration register 3" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT3RSFR,MDF reshape filter configuration register 3" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT3INTR,MDF integrator configuration register 3" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD3CR,MDF out-of limit detector control register 3" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD3THLR,MDF OLD3 low threshold register 3" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD3THHR,MDF OLD3 high threshold register 3" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY3CR,MDF delay control register 3" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD3CR,MDF short circuit detector control register 3" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT3IER,MDF DFLT3 interrupt enable register 3" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCDx interrupt enable" "0: SCDx interrupt disabled,1: SCDx interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLDx interrupt enable" "0: OLDx event interrupt disabled,1: OLDx event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT3ISR,MDF DFLT3 interrupt status register 3" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD event is detected.,1: Read 1 means that a SCD event is detected. Write.." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLDx flag" "0: Read 0 means that no OLDx event is detected.,1: Read 1 means that an OLDx event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC3CR,MDF offset error compensation control register 3" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0x26C++0x7 line.long 0x0 "MDF_SNPS3DR,MDF snapshot data register 3" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT3DR,MDF digital filter data register 3" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" group.long 0x280++0x37 line.long 0x0 "MDF_SITF4CR,MDF serial interface control register 4" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX4CR,MDF bitstream matrix control register 4" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT4CR,MDF digital filter control register 4" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT4CICR,MDF digital filter configuration register 4" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT4RSFR,MDF reshape filter configuration register 4" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT4INTR,MDF integrator configuration register 4" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD4CR,MDF out-of limit detector control register 4" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD4THLR,MDF OLD4 low threshold register 4" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD4THHR,MDF OLD4 high threshold register 4" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY4CR,MDF delay control register 4" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD4CR,MDF short circuit detector control register 4" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT4IER,MDF DFLT4 interrupt enable register 4" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCDx interrupt enable" "0: SCDx interrupt disabled,1: SCDx interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLDx interrupt enable" "0: OLDx event interrupt disabled,1: OLDx event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT4ISR,MDF DFLT4 interrupt status register 4" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD event is detected.,1: Read 1 means that a SCD event is detected. Write.." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLDx flag" "0: Read 0 means that no OLDx event is detected.,1: Read 1 means that an OLDx event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC4CR,MDF offset error compensation control register 4" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0x2EC++0x7 line.long 0x0 "MDF_SNPS4DR,MDF snapshot data register 4" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT4DR,MDF digital filter data register 4" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" group.long 0x300++0x37 line.long 0x0 "MDF_SITF5CR,MDF serial interface control register 5" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX5CR,MDF bitstream matrix control register 5" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT5CR,MDF digital filter control register 5" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT5CICR,MDF digital filter configuration register 5" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT5RSFR,MDF reshape filter configuration register 5" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT5INTR,MDF integrator configuration register 5" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD5CR,MDF out-of limit detector control register 5" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD5THLR,MDF OLD5 low threshold register 5" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD5THHR,MDF OLD5 high threshold register 5" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY5CR,MDF delay control register 5" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD5CR,MDF short circuit detector control register 5" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT5IER,MDF DFLT5 interrupt enable register 5" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCDx interrupt enable" "0: SCDx interrupt disabled,1: SCDx interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLDx interrupt enable" "0: OLDx event interrupt disabled,1: OLDx event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT5ISR,MDF DFLT5 interrupt status register 5" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD event is detected.,1: Read 1 means that a SCD event is detected. Write.." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLDx flag" "0: Read 0 means that no OLDx event is detected.,1: Read 1 means that an OLDx event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC5CR,MDF offset error compensation control register 5" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0x36C++0x7 line.long 0x0 "MDF_SNPS5DR,MDF snapshot data register 5" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT5DR,MDF digital filter data register 5" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" tree.end tree "MDF1_S" base ad:0x52025000 group.long 0x0++0x7 line.long 0x0 "MDF_GCR,MDF global control register" hexmask.long.byte 0x0 4.--7. 1. "ILVNB,Interleaved number" bitfld.long 0x0 0. "TRGO,Trigger output control" "0: Write 0 has no effect. Read 0 means that the..,1: Write 1 generates a positive pulse on mdf_trgo.." line.long 0x4 "MDF_CKGCR,MDF clock generator control register" rbitfld.long 0x4 31. "CKGACTIVE,Clock generator active flag" "0: The clock generator is not active and can be..,1: The clock generator is active and protected.." hexmask.long.byte 0x4 24.--30. 1. "PROCDIV,Divider to control the serial interface clock" newline hexmask.long.byte 0x4 16.--19. 1. "CCKDIV,Divider to control the MDF_CCK clock" hexmask.long.byte 0x4 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" newline bitfld.long 0x4 8. "TRGSENS,CKGEN trigger sensitivity selection" "0: A rising edge event triggers the activation of..,1: A falling edge even triggers the activation of.." bitfld.long 0x4 6. "CCK1DIR,MDF_CCK1 direction" "0: MDF_CCK1 pin direction is in input.,1: MDF_CCK1 pin direction is in output." newline bitfld.long 0x4 5. "CCK0DIR,MDF_CCK0 direction" "0: MDF_CCK0 pin direction is in input.,1: MDF_CCK0 pin direction is in output." bitfld.long 0x4 4. "CKGMOD,Clock generator mode" "0: The kernel clock is provided to the dividers as..,1: The kernel clock is provided to the dividers.." newline bitfld.long 0x4 2. "CCK1EN,MDF_CCK1 clock enable" "0: Bitstream clock not generated,1: Bitstream clock generated on the MDF_CCK1 pad" bitfld.long 0x4 1. "CCK0EN,MDF_CCK0 clock enable" "0: Bitstream clock not generated,1: Bitstream clock generated on the MDF_CCK0 pad" newline bitfld.long 0x4 0. "CKGDEN,CKGEN dividers enable" "0: CKGEN dividers disabled,1: CKGEN dividers enabled" group.long 0x80++0x37 line.long 0x0 "MDF_SITF0CR,MDF serial interface control register 0" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX0CR,MDF bitstream matrix control register 0" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT0CR,MDF digital filter control register 0" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT0CICR,MDF digital filter configuration register 0" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT0RSFR,MDF reshape filter configuration register 0" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT0INTR,MDF integrator configuration register 0" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD0CR,MDF out-of limit detector control register 0" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD0THLR,MDF OLD0 low threshold register 0" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD0THHR,MDF OLD0 high threshold register 0" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY0CR,MDF delay control register 0" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD0CR,MDF short circuit detector control register 0" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT0IER,MDF DFLT0 interrupt enable register 0" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCD0 interrupt enable" "0: SCD0 interrupt disabled,1: SCD0 interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLD0 interrupt enable" "0: OLD0 event interrupt disabled,1: OLD0 event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT0ISR,MDF DFLT0 interrupt status register 0" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD0 event is detected.,1: Read 1 means that a SCD0 event is detected." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLD0 flag" "0: Read 0 means that no OLD0 event is detected.,1: Read 1 means that an OLD0 event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC0CR,MDF offset error compensation control register 0" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0xEC++0x7 line.long 0x0 "MDF_SNPS0DR,MDF snapshot data register 0" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT0DR,MDF digital filter data register 0" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" group.long 0x100++0x37 line.long 0x0 "MDF_SITF1CR,MDF serial interface control register 1" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX1CR,MDF bitstream matrix control register 1" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT1CR,MDF digital filter control register 1" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT1CICR,MDF digital filter configuration register 1" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT1RSFR,MDF reshape filter configuration register 1" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT1INTR,MDF integrator configuration register 1" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD1CR,MDF out-of limit detector control register 1" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD1THLR,MDF OLD1 low threshold register 1" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD1THHR,MDF OLD1 high threshold register 1" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY1CR,MDF delay control register 1" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD1CR,MDF short circuit detector control register 1" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT1IER,MDF DFLT1 interrupt enable register 1" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCDx interrupt enable" "0: SCDx interrupt disabled,1: SCDx interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLDx interrupt enable" "0: OLDx event interrupt disabled,1: OLDx event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT1ISR,MDF DFLT1 interrupt status register 1" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD event is detected.,1: Read 1 means that a SCD event is detected. Write.." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLDx flag" "0: Read 0 means that no OLDx event is detected.,1: Read 1 means that an OLDx event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC1CR,MDF offset error compensation control register 1" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0x16C++0x7 line.long 0x0 "MDF_SNPS1DR,MDF snapshot data register 1" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT1DR,MDF digital filter data register 1" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" group.long 0x180++0x37 line.long 0x0 "MDF_SITF2CR,MDF serial interface control register 2" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX2CR,MDF bitstream matrix control register 2" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT2CR,MDF digital filter control register 2" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT2CICR,MDF digital filter configuration register 2" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT2RSFR,MDF reshape filter configuration register 2" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT2INTR,MDF integrator configuration register 2" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD2CR,MDF out-of limit detector control register 2" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD2THLR,MDF OLD2 low threshold register 2" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD2THHR,MDF OLD2 high threshold register 2" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY2CR,MDF delay control register 2" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD2CR,MDF short circuit detector control register 2" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT2IER,MDF DFLT2 interrupt enable register 2" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCDx interrupt enable" "0: SCDx interrupt disabled,1: SCDx interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLDx interrupt enable" "0: OLDx event interrupt disabled,1: OLDx event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT2ISR,MDF DFLT2 interrupt status register 2" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD event is detected.,1: Read 1 means that a SCD event is detected. Write.." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLDx flag" "0: Read 0 means that no OLDx event is detected.,1: Read 1 means that an OLDx event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC2CR,MDF offset error compensation control register 2" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0x1EC++0x7 line.long 0x0 "MDF_SNPS2DR,MDF snapshot data register 2" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT2DR,MDF digital filter data register 2" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" group.long 0x200++0x37 line.long 0x0 "MDF_SITF3CR,MDF serial interface control register 3" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX3CR,MDF bitstream matrix control register 3" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT3CR,MDF digital filter control register 3" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT3CICR,MDF digital filter configuration register 3" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT3RSFR,MDF reshape filter configuration register 3" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT3INTR,MDF integrator configuration register 3" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD3CR,MDF out-of limit detector control register 3" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD3THLR,MDF OLD3 low threshold register 3" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD3THHR,MDF OLD3 high threshold register 3" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY3CR,MDF delay control register 3" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD3CR,MDF short circuit detector control register 3" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT3IER,MDF DFLT3 interrupt enable register 3" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCDx interrupt enable" "0: SCDx interrupt disabled,1: SCDx interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLDx interrupt enable" "0: OLDx event interrupt disabled,1: OLDx event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT3ISR,MDF DFLT3 interrupt status register 3" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD event is detected.,1: Read 1 means that a SCD event is detected. Write.." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLDx flag" "0: Read 0 means that no OLDx event is detected.,1: Read 1 means that an OLDx event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC3CR,MDF offset error compensation control register 3" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0x26C++0x7 line.long 0x0 "MDF_SNPS3DR,MDF snapshot data register 3" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT3DR,MDF digital filter data register 3" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" group.long 0x280++0x37 line.long 0x0 "MDF_SITF4CR,MDF serial interface control register 4" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX4CR,MDF bitstream matrix control register 4" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT4CR,MDF digital filter control register 4" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT4CICR,MDF digital filter configuration register 4" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT4RSFR,MDF reshape filter configuration register 4" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT4INTR,MDF integrator configuration register 4" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD4CR,MDF out-of limit detector control register 4" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD4THLR,MDF OLD4 low threshold register 4" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD4THHR,MDF OLD4 high threshold register 4" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY4CR,MDF delay control register 4" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD4CR,MDF short circuit detector control register 4" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT4IER,MDF DFLT4 interrupt enable register 4" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCDx interrupt enable" "0: SCDx interrupt disabled,1: SCDx interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLDx interrupt enable" "0: OLDx event interrupt disabled,1: OLDx event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT4ISR,MDF DFLT4 interrupt status register 4" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD event is detected.,1: Read 1 means that a SCD event is detected. Write.." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLDx flag" "0: Read 0 means that no OLDx event is detected.,1: Read 1 means that an OLDx event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC4CR,MDF offset error compensation control register 4" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0x2EC++0x7 line.long 0x0 "MDF_SNPS4DR,MDF snapshot data register 4" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT4DR,MDF digital filter data register 4" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" group.long 0x300++0x37 line.long 0x0 "MDF_SITF5CR,MDF serial interface control register 5" rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.." hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold" newline bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.." bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is MDF_CCK0.,1: Serial clock source is MDF_CCK1.,?,?" newline bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled" line.long 0x4 "MDF_BSMX5CR,MDF bitstream matrix control register 5" rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.." hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream Selection" line.long 0x8 "MDF_DFLT5CR,MDF digital filter control register 5" rbitfld.long 0x8 31. "DFLTACTIVE,Digital filter active flag" "0: Digital filter not active (can be re-enabled..,1: Digital filter active" rbitfld.long 0x8 30. "DFLTRUN,Digital filter run status flag" "0: Digital filter not running and ready to accept a..,1: Digital filter running" newline hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded" bitfld.long 0x8 16. "SNPSFMT,Snapshot data format" "0: Integrator counter (INT_CNT) not inserted into..,1: Integrator counter (INT_CNT) inserted at.." newline hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,Digital filter trigger signal selection" bitfld.long 0x8 8. "TRGSENS,Digital filter trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition." newline bitfld.long 0x8 4.--6. "ACQMOD,Digital filter trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,5: Synchronous snapshot mode,?,?" bitfld.long 0x8 2. "FTH,RXFIFO Threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.." newline bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.." bitfld.long 0x8 0. "DFLTEN,Digital filter enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.." line.long 0xC "MDF_DFLT5CICR,MDF digital filter configuration register 5" hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection" bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2." newline hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection" bitfld.long 0xC 4.--6. "CICMOD,Select the CIC mode" "0: CIC split in two filters and MCIC configured in..,1: CIC split in two filters and MCIC configured in..,2: CIC split in two filters and MCIC configured in..,3: CIC split in two filters and MCIC configured in..,4: CIC configured in single Sinc less than sup>4..,?,?,?" newline bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected" line.long 0x10 "MDF_DFLT5RSFR,MDF reshape filter configuration register 5" bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x F less than..,1: Cut-off frequency = 0.00125 x F less than..,2: Cut-off frequency = 0.00250 x F less than..,3: Cut-off frequency = 0.00950 x F less than.." bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed" newline bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1." bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed" line.long 0x14 "MDF_DFLT5INTR,MDF integrator configuration register 5" hexmask.long.byte 0x14 4.--10. 1. "INTVAL,Integration value selection" bitfld.long 0x14 0.--1. "INTDIV,Integrator output division" "0: The integrator data outputs are divided by 128..,1: The integrator data outputs are divided by 32.,2: The integrator data outputs are divided by 4.,3: The integrator data outputs are not divided." line.long 0x18 "MDF_OLD5CR,MDF out-of limit detector control register 5" rbitfld.long 0x18 31. "OLDACTIVE,OLDx active flag" "0: OLDx not active and can be configured if needed,1: OLDx active and protected fields cannot be.." hexmask.long.byte 0x18 17.--21. 1. "ACICD,OLDx CIC decimation ratio selection" newline bitfld.long 0x18 12.--13. "ACICN,OLDx CIC order selection" "0: FastSinc filter type,1: Sinc less than sup>1 less than /sup> filter type,2: Sinc less than sup>2 less than /sup> filter type,3: Sinc less than sup>3 less than /sup> filter type" hexmask.long.byte 0x18 4.--7. 1. "BKOLD,Break signal assignment for out-of limit detector" newline bitfld.long 0x18 1. "THINB,Threshold In band" "0: The OLDx generates an event if the signal is..,1: The OLDx generates an event if the signal is.." bitfld.long 0x18 0. "OLDEN,OLDx enable" "0: OLDx disabled (default value),1: OLDx enabled including the ACIC filter working.." line.long 0x1C "MDF_OLD5THLR,MDF OLD5 low threshold register 5" hexmask.long 0x1C 0.--25. 1. "OLDTHL,OLD low threshold value" line.long 0x20 "MDF_OLD5THHR,MDF OLD5 high threshold register 5" hexmask.long 0x20 0.--25. 1. "OLDTHH,OLDx high threshold value" line.long 0x24 "MDF_DLY5CR,MDF delay control register 5" rbitfld.long 0x24 31. "SKPBF,Skip busy flag" "0: MDF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under processing" hexmask.long.byte 0x24 0.--6. 1. "SKPDLY,Delay to apply to a bitstream" line.long 0x28 "MDF_SCD5CR,MDF short circuit detector control register 5" rbitfld.long 0x28 31. "SCDACTIVE,SCDx active flag" "0: SCDx not active and can be configured if needed,1: SCDx active and protected fields cannot be.." hexmask.long.byte 0x28 12.--19. 1. "SCDT,SCDx threshold" newline hexmask.long.byte 0x28 4.--7. 1. "BKSCD,Break signal assignment for short circuit detector" bitfld.long 0x28 0. "SCDEN,SCDx enable" "0: SCDx disabled,1: SSCDx enabled" line.long 0x2C "MDF_DFLT5IER,MDF DFLT5 interrupt enable register 5" bitfld.long 0x2C 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled" bitfld.long 0x2C 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled" newline bitfld.long 0x2C 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled" bitfld.long 0x2C 8. "SCDIE,SCDx interrupt enable" "0: SCDx interrupt disabled,1: SCDx interrupt enabled" newline bitfld.long 0x2C 7. "SSOVRIE,Snapshot overrun interrupt enable" "0: Snapshot overrun interrupt disabled,1: Snapshot overrun interrupt enabled" bitfld.long 0x2C 4. "OLDIE,OLDx interrupt enable" "0: OLDx event interrupt disabled,1: OLDx event interrupt enabled" newline bitfld.long 0x2C 2. "SSDRIE,Snapshot data ready interrupt enable" "0: Snapshot data ready interrupt disabled,1: Snapshot data ready interrupt enabled" bitfld.long 0x2C 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled" newline bitfld.long 0x2C 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled" line.long 0x30 "MDF_DFLT5ISR,MDF DFLT5 interrupt status register 5" bitfld.long 0x30 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.." bitfld.long 0x30 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected." newline bitfld.long 0x30 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected." bitfld.long 0x30 8. "SCDF,Short-circuit detector flag" "0: Read 0 means that no SCD event is detected.,1: Read 1 means that a SCD event is detected. Write.." newline bitfld.long 0x30 7. "SSOVRF,Snapshot overrun flag" "0: Read 0 means that no snapshot overrun event is..,1: Read 1 means that a snapshot overrun event is.." rbitfld.long 0x30 6. "THHF,High-threshold status flag" "0: The signal was lower than OLDTHH when the last..,1: The signal was higher than OLDTHH when the last.." newline rbitfld.long 0x30 5. "THLF,Low-threshold status flag" "0: The signal was higher than OLDTHL when the last..,1: The signal was lower than OLDTHL when the last.." bitfld.long 0x30 4. "OLDF,OLDx flag" "0: Read 0 means that no OLDx event is detected.,1: Read 1 means that an OLDx event is detected.." newline rbitfld.long 0x30 3. "RXNEF,RXFIFO not-empty flag" "0: RXFIFO empty,1: RXFIFO not empty" bitfld.long 0x30 2. "SSDRF,Snapshot data ready flag" "0: Read 0 means that no data is available. Write 0..,1: Read 1 means that a new data is available. Write.." newline bitfld.long 0x30 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.." rbitfld.long 0x30 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached" line.long 0x34 "MDF_OEC5CR,MDF offset error compensation control register 5" hexmask.long 0x34 0.--25. 1. "OFFSET,Offset error compensation" rgroup.long 0x36C++0x7 line.long 0x0 "MDF_SNPS5DR,MDF snapshot data register 5" hexmask.long.word 0x0 16.--31. 1. "SDR,Contains the 16 MSB of the last valid data processed by the digital filter." hexmask.long.byte 0x0 9.--15. 1. "EXTSDR,Extended data size" newline hexmask.long.word 0x0 0.--8. 1. "MCICDC,Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" line.long 0x4 "MDF_DFLT5DR,MDF digital filter data register 5" hexmask.long.tbyte 0x4 8.--31. 1. "DR,Data processed by digital filter" tree.end tree.end tree "MDIOS (Management Data Input/Output)" base ad:0x0 tree "MDIOS" base ad:0x40009400 group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,slave address" bitfld.long 0x0 7. "DPC,disable preamble check" "0: MDIO master must give preamble before each frame.,1: MDIO master can send each frame without a.." newline bitfld.long 0x0 3. "EIE,error interrupt enable" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x0 2. "RDIE,register read interrupt enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x0 1. "WRIE,register write interrupt enable" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x0 0. "EN,peripheral enable" "0: MDIOS is disabled.,1: MDIOS is enabled and monitoring the MDIO bus.." rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,write flags for MDIOS registers 0 to 31." group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag register" hexmask.long 0x0 0.--31. 1. "CWRF,clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,read flags for MDIOS registers 0 to 31." group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,turnaround error flag" "0: No turnaround error has occurred.,1: A turnaround error has occurred." bitfld.long 0x0 1. "SERF,start error flag" "0: No start error has occurred.,1: A start error has occurred." newline bitfld.long 0x0 0. "PERF,preamble error flag" "0: No preamble error has occurred.,1: A preamble error has occurred." group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,clear the turnaround error flag" "0,1" bitfld.long 0x0 1. "CSERF,clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,clear the preamble error flag" "0,1" rgroup.long 0x100++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN,input data received from MDIO master during write frames" group.long 0x180++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" tree.end tree "MDIOS_S" base ad:0x50009400 group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,slave address" bitfld.long 0x0 7. "DPC,disable preamble check" "0: MDIO master must give preamble before each frame.,1: MDIO master can send each frame without a.." newline bitfld.long 0x0 3. "EIE,error interrupt enable" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x0 2. "RDIE,register read interrupt enable" "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x0 1. "WRIE,register write interrupt enable" "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x0 0. "EN,peripheral enable" "0: MDIOS is disabled.,1: MDIOS is enabled and monitoring the MDIO bus.." rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,write flags for MDIOS registers 0 to 31." group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag register" hexmask.long 0x0 0.--31. 1. "CWRF,clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,read flags for MDIOS registers 0 to 31." group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,turnaround error flag" "0: No turnaround error has occurred.,1: A turnaround error has occurred." bitfld.long 0x0 1. "SERF,start error flag" "0: No start error has occurred.,1: A start error has occurred." newline bitfld.long 0x0 0. "PERF,preamble error flag" "0: No preamble error has occurred.,1: A preamble error has occurred." group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,clear the turnaround error flag" "0,1" bitfld.long 0x0 1. "CSERF,clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,clear the preamble error flag" "0,1" rgroup.long 0x100++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN,input data received from MDIO master during write frames" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN,input data received from MDIO master during write frames" group.long 0x180++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames" tree.end tree.end tree "OTG (USB On-the-Go High-Speed)" base ad:0x0 tree "OTG1" base ad:0x48040000 group.long 0x0++0x17 line.long 0x0 "OTG_GOTGCTL,OTG control and status register" rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0: Device mode,1: Host mode" newline bitfld.long 0x0 20. "OTGVER,OTG version" "0: OTG Version 1.3. OTG1.3 is obsolete for new..,1: OTG Version 2.0. In this version the core.." newline rbitfld.long 0x0 19. "BSVLD,B-session valid" "0: B-session is not valid.,1: B-session is valid." newline rbitfld.long 0x0 18. "ASVLD,A-session valid" "0: A-session is not valid,1: A-session is valid" newline rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0: Long debounce time used for physical connections..,1: Short debounce time used for soft connections.." newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0: The OTG controller is in A-device mode,1: The OTG controller is in B-device mode" newline bitfld.long 0x0 12. "EHEN,Embedded host enable" "0: OTG A device state machine is selected,1: Embedded host state machine is selected" newline bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value." "0: Bvalid value is '0' when BVALOEN = 1,1: Bvalid value is '1' when BVALOEN = 1" newline bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0: Override is disabled and Bvalid signal from the..,?" newline bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value." "0: Avalid value is '0' when AVALOEN = 1,1: Avalid value is '1' when AVALOEN = 1" newline bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable." "0: Override is disabled and Avalid signal from the..,1: Internally Avalid received from the PHY is.." newline bitfld.long 0x0 3. "VBVALOVAL,V less than sub>BUS less than /sub> valid override value." "0: vbusvalid value is '0' when VBVALOEN = 1,1: vbusvalid value is '1' when VBVALOEN = 1" newline bitfld.long 0x0 2. "VBVALOEN,V less than sub>BUS less than /sub> valid override enable." "0: Override is disabled and vbusvalid signal from..,1: Internally vbusvalid received from the PHY is.." line.long 0x4 "OTG_GOTGINT,OTG interrupt register" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" newline bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_GAHBCFG,OTG AHB configuration register" bitfld.long 0x8 8. "PTXFELVL,Periodic Tx FIFO empty level" "0: PTXFE (in OTG_GINTSTS) interrupt indicates that..,1: PTXFE (in OTG_GINTSTS) interrupt indicates that.." newline bitfld.long 0x8 7. "TXFELVL,Tx FIFO empty level" "0: The TXFE (in OTG_DIEPINTx) interrupt indicates..,1: The TXFE (in OTG_DIEPINTx) interrupt indicates.." newline bitfld.long 0x8 5. "DMAEN,DMA enabled" "0: The core operates in slave mode,1: The core operates in DMA mode" newline hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" newline bitfld.long 0x8 0. "GINTMSK,Global interrupt mask" "0: Mask the interrupt assertion to the application.,1: Unmask the interrupt assertion to the application." line.long 0xC "OTG_GUSBCFG,OTG USB configuration register" bitfld.long 0xC 30. "FDMOD,Force device mode" "0: Normal mode,1: Force device mode" newline bitfld.long 0xC 29. "FHMOD,Force host mode" "0: Normal mode,1: Force host mode" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing selection" "0: Data line pulsing using utmi_txvalid (default),1: Data line pulsing using utmi_termsel" newline bitfld.long 0xC 15. "PHYLPC,PHY Low-power clock select" "0: 480 MHz internal PLL clock,1: 48 MHz external clock" newline hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" newline bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_GRSTCTL,OTG reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" newline rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled" "0,1" newline hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x10 5. "TXFFLSH,Tx FIFO flush" "0,1" newline bitfld.long 0x10 4. "RXFFLSH,Rx FIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" newline bitfld.long 0x10 1. "PSRST,Partial soft reset" "0,1" newline bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_GINTSTS,OTG core interrupt register [alternate]" bitfld.long 0x14 31. "WKUPINT,Resume/remote wake-up detected interrupt" "0,1" newline bitfld.long 0x14 30. "SRQINT,Session request/new session detected interrupt" "0,1" newline bitfld.long 0x14 29. "DISCINT,Disconnect detected interrupt" "0,1" newline bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" newline bitfld.long 0x14 27. "LPMINT,LPM interrupt" "0,1" newline rbitfld.long 0x14 26. "PTXFE,Periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" newline rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" newline bitfld.long 0x14 23. "RSTDET,Reset detected interrupt" "0,1" newline bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" newline bitfld.long 0x14 21. "IPXFR,Incomplete periodic transfer" "0,1" newline bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" newline rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" newline bitfld.long 0x14 15. "EOPF,End of periodic frame interrupt" "0,1" newline bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1" newline bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" newline bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" newline bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" newline rbitfld.long 0x14 7. "GONAKEFF,Global OUT NAK effective" "0,1" newline rbitfld.long 0x14 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 4. "RXFLVL,Rx FIFO non-empty" "0,1" newline bitfld.long 0x14 3. "SOF,Start of frame" "0,1" newline rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" newline bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode" group.long 0x14++0x7 line.long 0x0 "OTG_GINTSTS_ALTERNATE,OTG core interrupt register [alternate]" bitfld.long 0x0 31. "WKUPINT,Resume/remote wake-up detected interrupt" "0,1" newline bitfld.long 0x0 30. "SRQINT,Session request/new session detected interrupt" "0,1" newline bitfld.long 0x0 29. "DISCINT,Disconnect detected interrupt" "0,1" newline bitfld.long 0x0 28. "CIDSCHG,Connector ID status change" "0,1" newline bitfld.long 0x0 27. "LPMINT,LPM interrupt" "0,1" newline rbitfld.long 0x0 26. "PTXFE,Periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x0 25. "HCINT,Host channels interrupt" "0,1" newline rbitfld.long 0x0 24. "HPRTINT,Host port interrupt" "0,1" newline bitfld.long 0x0 23. "RSTDET,Reset detected interrupt" "0,1" newline bitfld.long 0x0 22. "DATAFSUSP,Data fetch suspended" "0,1" newline bitfld.long 0x0 21. "INCOMPISOOUT,Incomplete isochronous OUT transfer" "0,1" newline bitfld.long 0x0 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1" newline rbitfld.long 0x0 19. "OEPINT,OUT endpoint interrupt" "0,1" newline rbitfld.long 0x0 18. "IEPINT,IN endpoint interrupt" "0,1" newline bitfld.long 0x0 15. "EOPF,End of periodic frame interrupt" "0,1" newline bitfld.long 0x0 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1" newline bitfld.long 0x0 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x0 12. "USBRST,USB reset" "0,1" newline bitfld.long 0x0 11. "USBSUSP,USB suspend" "0,1" newline bitfld.long 0x0 10. "ESUSP,Early suspend" "0,1" newline rbitfld.long 0x0 7. "GONAKEFF,Global OUT NAK effective" "0,1" newline rbitfld.long 0x0 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1" newline rbitfld.long 0x0 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x0 4. "RXFLVL,Rx FIFO non-empty" "0,1" newline bitfld.long 0x0 3. "SOF,Start of frame" "0,1" newline rbitfld.long 0x0 2. "OTGINT,OTG interrupt" "0,1" newline bitfld.long 0x0 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x0 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode" line.long 0x4 "OTG_GINTMSK,OTG interrupt mask register [alternate]" bitfld.long 0x4 31. "WUIM,Resume/remote wake-up detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 29. "DISCINT,Disconnect detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 26. "PTXFEM,Periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 25. "HCIM,Host channels interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline rbitfld.long 0x4 24. "PRTIM,Host port interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 21. "IPXFRM,Incomplete periodic transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 5. "NPTXFEM,Non-periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" group.long 0x18++0x3 line.long 0x0 "OTG_GINTMSK_ALTERNATE,OTG interrupt mask register [alternate]" bitfld.long 0x0 31. "WUIM,Resume/remote wake-up detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 23. "RSTDETM,Reset detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 22. "FSUSPM,Data fetch suspended mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 21. "IISOOXFRM,Incomplete isochronous OUT transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 20. "IISOIXFRM,Incomplete isochronous IN transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 19. "OEPINT,OUT endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 18. "IEPINT,IN endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 15. "EOPFM,End of periodic frame interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 14. "ISOODRPM,Isochronous OUT packet dropped interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 13. "ENUMDNEM,Enumeration done mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 12. "USBRST,USB reset mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 11. "USBSUSPM,USB suspend mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 10. "ESUSPM,Early suspend mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 7. "GONAKEFFM,Global OUT NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 6. "GINAKEFFM,Global non-periodic IN NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" rgroup.long 0x1C++0x3 line.long 0x0 "OTG_GRXSTSR,OTG receive status debug read register [alternate]" bitfld.long 0x0 27. "STSPHST,Status phase start" "0,1" newline hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_GRXSTSR_ALTERNATE,OTG receive status debug read register [alternate]" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_GRXSTSP,OTG status read and pop registers" bitfld.long 0x4 27. "STSPHST,Status phase start" "0,1" newline hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x4 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" rgroup.long 0x20++0x3 line.long 0x0 "OTG_GRXSTSP_ALTERNATE,OTG status read and pop registers" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_GRXFSIZ,OTG receive FIFO size register" hexmask.long.word 0x0 0.--15. 1. "RXFD,Rx FIFO depth" line.long 0x4 "OTG_HNPTXFSIZ,OTG host non-periodic transmit FIFO size register [alternate]" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Non-periodic Tx FIFO depth" newline hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Non-periodic transmit RAM start address" group.long 0x28++0x3 line.long 0x0 "OTG_HNPTXFSIZ_ALTERNATE,OTG host non-periodic transmit FIFO size register [alternate]" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 Tx FIFO depth" newline hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start address" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HNPTXSTS,OTG non-periodic transmit FIFO/queue status register" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the non-periodic transmit request queue" newline hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Non-periodic transmit request queue space available" newline hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Non-periodic Tx FIFO space available" group.long 0x38++0x7 line.long 0x0 "OTG_GCCFG,OTG general core configuration register" bitfld.long 0x0 28. "IDPULLUPDIS,Disable ID pin pull-up" "0: Enables ID pin pull-up,1: Disable ID pin pull-up" newline bitfld.long 0x0 26. "BCDEN,Force Battery charging (BC) mode" "0: Normal USB mode,1: Battery Charging mode" newline bitfld.long 0x0 25. "FORCEHOSTPD,Force host mode pull-downs" "0: Do not force host mode pull-downs,1: Force host mode pull-downs" newline bitfld.long 0x0 23. "VBVALOVAL,Software override value of the VBUS B-session detection" "0: B-session inactive,1: B-session active" newline bitfld.long 0x0 22. "SDEN,Secondary detection enable" "0: Secondary detection disabled,1: Secondary detection enabled" newline bitfld.long 0x0 20. "PDEN,Primary detection enable" "0: Primary detection disabled,1: Primary detection enabled" newline bitfld.long 0x0 19. "DCDEN,Data Contact Detection enable" "0: Data Contact Detection disabled,1: Data Contact Detection enabled" newline bitfld.long 0x0 18. "HVDMSRCEN,Host CDP port Voltage source enable on DM" "0: DM voltage source disabled,1: DM Voltage source enabled" newline bitfld.long 0x0 17. "HCDPDETEN,Host CDP port voltage detector enable on DP" "0: DP voltage detection disabled,1: DP voltage detection enabled" newline bitfld.long 0x0 16. "HCDPEN,Host CDP behavior enable" "0: Disable CDP behavior,1: Enable CDP behavior" newline rbitfld.long 0x0 4. "VBUSVLD,VBUS valid indicator" "0: VBUS is below VBUS valid threshold,1: VBUS is above VBUS valid threshold" newline rbitfld.long 0x0 3. "SESSVLD,VBUS session indicator" "0: VBUS is below VBUS session threshold,1: VBUS is above VBUS session threshold" newline rbitfld.long 0x0 2. "FSVMINUS,Single-Ended DM indicator" "0: DM voltage at low level,1: DM voltage at high level" newline rbitfld.long 0x0 1. "FSVPLUS,Single-Ended DP indicator" "0: DM voltage at low level,1: DM voltage at high level" newline rbitfld.long 0x0 0. "CHGDET,Charger detection result of the current mode (primary or secondary)." "0: Low value on pin,1: High value on pin" line.long 0x4 "OTG_CID,OTG core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x54++0x3 line.long 0x0 "OTG_GLPMCFG,OTG core LPM configuration register" bitfld.long 0x0 28. "ENBESL,Enable best effort service latency" "0: The core works as described in the following..,1: The core works as described in the LPM Errata:" newline rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" newline bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep state resume OK" "0: The application or host cannot start resume from..,1: The application or host can start resume from.." newline rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0: Core not in L1,1: Core in L1" newline rbitfld.long 0x0 13.--14. "LPMRSP,LPM response" "0: ERROR (No handshake response),1: STALL,2: NYET,3: ACK" newline bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" newline bitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service latency" newline bitfld.long 0x0 1. "LPMACK,LPM token acknowledge enable" "0: NYET,1: ACK" newline bitfld.long 0x0 0. "LPMEN,LPM support enable" "0: LPM capability is not enabled,1: LPM capability is enabled" group.long 0x100++0x23 line.long 0x0 "OTG_HPTXFSIZ,OTG host periodic transmit FIFO size register" hexmask.long.word 0x0 16.--31. 1. "PTXFSIZ,Host periodic Tx FIFO depth" newline hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic Tx FIFO start address" line.long 0x4 "OTG_DIEPTXF1,OTG device IN endpoint transmit FIFO 1 size register" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x8 "OTG_DIEPTXF2,OTG device IN endpoint transmit FIFO 2 size register" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0xC "OTG_DIEPTXF3,OTG device IN endpoint transmit FIFO 3 size register" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x10 "OTG_DIEPTXF4,OTG device IN endpoint transmit FIFO 4 size register" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x14 "OTG_DIEPTXF5,OTG device IN endpoint transmit FIFO 5 size register" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x18 "OTG_DIEPTXF6,OTG device IN endpoint transmit FIFO 6 size register" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x1C "OTG_DIEPTXF7,OTG device IN endpoint transmit FIFO 7 size register" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x20 "OTG_DIEPTXF8,OTG device IN endpoint transmit FIFO 8 size register" hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" group.long 0x400++0x7 line.long 0x0 "OTG_HCFG,OTG host configuration register" rbitfld.long 0x0 2. "FSLSS,FS- and LS-only support" "0,1" newline bitfld.long 0x0 0.--1. "FSLSPCS,FS/LS PHY clock select" "?,1: PHY clock is running at 48 MHz,2: Select 6 MHz PHY clock frequency,?" line.long 0x4 "OTG_HFIR,OTG host frame interval register" bitfld.long 0x4 16. "RLDCTRL,Reload control" "0: The HFIR cannot be reloaded dynamically,1: The HFIR can be dynamically reloaded during run.." newline hexmask.long.word 0x4 0.--15. 1. "FRIVL,Frame interval" rgroup.long 0x408++0x3 line.long 0x0 "OTG_HFNUM,OTG host frame number/frame time remaining register" hexmask.long.word 0x0 16.--31. 1. "FTREM,Frame time remaining" newline hexmask.long.word 0x0 0.--15. 1. "FRNUM,Frame number" rgroup.long 0x410++0x7 line.long 0x0 "OTG_HPTXSTS,OTG_Host periodic transmit FIFO/queue status register" hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,Top of the periodic transmit request queue" newline hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,Periodic transmit request queue space available" newline hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,Periodic transmit data FIFO space available" line.long 0x4 "OTG_HAINT,OTG host all channels interrupt register" hexmask.long.word 0x4 0.--15. 1. "HAINT,Channel interrupts" group.long 0x418++0x3 line.long 0x0 "OTG_HAINTMSK,OTG host all channels interrupt mask register" hexmask.long.word 0x0 0.--15. 1. "HAINTM,Channel interrupt mask" group.long 0x440++0x3 line.long 0x0 "OTG_HPRT,OTG host port control and status register" rbitfld.long 0x0 17.--18. "PSPD,Port speed" "0: High speed,1: Full speed,2: Low speed,?" newline hexmask.long.byte 0x0 13.--16. 1. "PTCTL,Port test control" newline bitfld.long 0x0 12. "PPWR,Port power" "0: Power off,1: Power on" newline rbitfld.long 0x0 10.--11. "PLSTS,Port line status" "0,1,2,3" newline bitfld.long 0x0 8. "PRST,Port reset" "0: Port not in reset,1: Port in reset" newline bitfld.long 0x0 7. "PSUSP,Port suspend" "0: Port not in suspend mode,1: Port in suspend mode" newline bitfld.long 0x0 6. "PRES,Port resume" "0: No resume driven,1: Resume driven" newline bitfld.long 0x0 5. "POCCHNG,Port overcurrent change" "0,1" newline rbitfld.long 0x0 4. "POCA,Port overcurrent active" "0: No overcurrent condition,1: Overcurrent condition" newline bitfld.long 0x0 3. "PENCHNG,Port enable/disable change" "0,1" newline bitfld.long 0x0 2. "PENA,Port enable" "0: Port disabled,1: Port enabled" newline bitfld.long 0x0 1. "PCDET,Port connect detected" "0,1" newline rbitfld.long 0x0 0. "PCSTS,Port connect status" "0: No device is attached to the port,1: A device is attached to the port" group.long 0x500++0x17 line.long 0x0 "OTG_HCCHAR0,OTG host channel 0 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT0,OTG host channel 0 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT0,OTG host channel 0 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK0,OTG host channel 0 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ0,OTG host channel 0 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA0,OTG host channel 0 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x520++0x17 line.long 0x0 "OTG_HCCHAR1,OTG host channel 1 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT1,OTG host channel 1 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT1,OTG host channel 1 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK1,OTG host channel 1 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ1,OTG host channel 1 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA1,OTG host channel 1 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x540++0x17 line.long 0x0 "OTG_HCCHAR2,OTG host channel 2 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT2,OTG host channel 2 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT2,OTG host channel 2 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK2,OTG host channel 2 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ2,OTG host channel 2 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA2,OTG host channel 2 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x560++0x17 line.long 0x0 "OTG_HCCHAR3,OTG host channel 3 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT3,OTG host channel 3 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT3,OTG host channel 3 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK3,OTG host channel 3 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ3,OTG host channel 3 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA3,OTG host channel 3 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x580++0x17 line.long 0x0 "OTG_HCCHAR4,OTG host channel 4 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT4,OTG host channel 4 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT4,OTG host channel 4 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK4,OTG host channel 4 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ4,OTG host channel 4 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA4,OTG host channel 4 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5A0++0x17 line.long 0x0 "OTG_HCCHAR5,OTG host channel 5 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT5,OTG host channel 5 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT5,OTG host channel 5 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK5,OTG host channel 5 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ5,OTG host channel 5 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA5,OTG host channel 5 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5C0++0x17 line.long 0x0 "OTG_HCCHAR6,OTG host channel 6 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT6,OTG host channel 6 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT6,OTG host channel 6 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK6,OTG host channel 6 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ6,OTG host channel 6 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA6,OTG host channel 6 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5E0++0x17 line.long 0x0 "OTG_HCCHAR7,OTG host channel 7 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT7,OTG host channel 7 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT7,OTG host channel 7 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK7,OTG host channel 7 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ7,OTG host channel 7 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA7,OTG host channel 7 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x600++0x17 line.long 0x0 "OTG_HCCHAR8,OTG host channel 8 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT8,OTG host channel 8 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT8,OTG host channel 8 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK8,OTG host channel 8 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ8,OTG host channel 8 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA8,OTG host channel 8 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x620++0x17 line.long 0x0 "OTG_HCCHAR9,OTG host channel 9 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT9,OTG host channel 9 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT9,OTG host channel 9 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK9,OTG host channel 9 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ9,OTG host channel 9 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA9,OTG host channel 9 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x640++0x17 line.long 0x0 "OTG_HCCHAR10,OTG host channel 10 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT10,OTG host channel 10 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT10,OTG host channel 10 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK10,OTG host channel 10 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ10,OTG host channel 10 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA10,OTG host channel 10 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x660++0x17 line.long 0x0 "OTG_HCCHAR11,OTG host channel 11 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT11,OTG host channel 11 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT11,OTG host channel 11 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK11,OTG host channel 11 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ11,OTG host channel 11 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA11,OTG host channel 11 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x680++0x17 line.long 0x0 "OTG_HCCHAR12,OTG host channel 12 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT12,OTG host channel 12 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT12,OTG host channel 12 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK12,OTG host channel 12 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ12,OTG host channel 12 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA12,OTG host channel 12 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6A0++0x17 line.long 0x0 "OTG_HCCHAR13,OTG host channel 13 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT13,OTG host channel 13 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT13,OTG host channel 13 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK13,OTG host channel 13 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ13,OTG host channel 13 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA13,OTG host channel 13 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6C0++0x17 line.long 0x0 "OTG_HCCHAR14,OTG host channel 14 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT14,OTG host channel 14 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT14,OTG host channel 14 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK14,OTG host channel 14 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ14,OTG host channel 14 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA14,OTG host channel 14 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6E0++0x17 line.long 0x0 "OTG_HCCHAR15,OTG host channel 15 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT15,OTG host channel 15 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT15,OTG host channel 15 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK15,OTG host channel 15 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ15,OTG host channel 15 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA15,OTG host channel 15 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x800++0x7 line.long 0x0 "OTG_DCFG,OTG device configuration register" bitfld.long 0x0 24.--25. "PERSCHIVL,Periodic schedule interval" "0: 25% of (micro)frame,1: 50% of (micro)frame,2: 75% of (micro)frame,?" newline bitfld.long 0x0 15. "ERRATIM,Erratic error interrupt mask" "0: Early suspend interrupt is generated on erratic..,1: Mask early suspend interrupt on erratic error" newline bitfld.long 0x0 11.--12. "PFIVL,Periodic frame interval" "0: 80% of the frame interval,1: 85% of the frame interval,2: 90% of the frame interval,3: 95% of the frame interval" newline hexmask.long.byte 0x0 4.--10. 1. "DAD,Device address" newline bitfld.long 0x0 2. "NZLSOHSK,Non-zero-length status OUT handshake" "0: Send the received OUT packet to the application..,1: Send a STALL handshake on a nonzero-length.." newline bitfld.long 0x0 0.--1. "DSPD,Device speed" "0: High speed,1: Full speed,?,?" line.long 0x4 "OTG_DCTL,OTG device control register" bitfld.long 0x4 18. "DSBESLRJCT,Deep sleep BESL reject" "0,1" newline bitfld.long 0x4 11. "POPRGDNE,Power-on programming done" "0,1" newline bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1" newline bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1" newline bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1" newline bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1" newline bitfld.long 0x4 4.--6. "TCTL,Test control" "0: Test mode disabled,1: Test_J mode,2: Test_K mode,3: Test_SE0_NAK mode,4: Test_Packet mode,5: Test_Force_Enable,?,?" newline rbitfld.long 0x4 3. "GONSTS,Global OUT NAK status" "0: A handshake is sent based on the FIFO status and..,1: No data is written to the Rx FIFO irrespective.." newline rbitfld.long 0x4 2. "GINSTS,Global IN NAK status" "0: A handshake is sent out based on the data..,1: A NAK handshake is sent out on all non-periodic.." newline bitfld.long 0x4 1. "SDIS,Soft disconnect" "0: Normal operation. When this bit is cleared after..,1: The core generates a device disconnect event to.." newline bitfld.long 0x4 0. "RWUSIG,Remote wake-up signaling" "0,1" rgroup.long 0x808++0x3 line.long 0x0 "OTG_DSTS,OTG device status register" bitfld.long 0x0 22.--23. "DEVLNSTS,Device line status" "0,1,2,3" newline hexmask.long.word 0x0 8.--21. 1. "FNSOF,Frame number of the received SOF" newline bitfld.long 0x0 3. "EERR,Erratic error" "0,1" newline bitfld.long 0x0 1.--2. "ENUMSPD,Enumerated speed" "0: High Speed,1: Full Speed,?,?" newline bitfld.long 0x0 0. "SUSPSTS,Suspend status" "0,1" group.long 0x810++0x7 line.long 0x0 "OTG_DIEPMSK,OTG device IN endpoint common interrupt mask register" bitfld.long 0x0 13. "NAKM,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 8. "TXFURM,FIFO underrun mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 6. "INEPNEM,IN endpoint NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 5. "INEPNMM,IN token received with EP mismatch mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 4. "ITTXFEMSK,IN token received when Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 3. "TOM,Timeout condition mask (Non-isochronous endpoints)" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x4 "OTG_DOEPMSK,OTG device OUT endpoint common interrupt mask register" bitfld.long 0x4 14. "NYETMSK,NYET interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 13. "NAKMSK,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 12. "BERRM,Babble error interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 8. "OUTPKTERRM,Out packet error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 6. "B2BSTUPM,Back-to-back SETUP packets received mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 5. "STSPHSRXM,Status phase received for control write mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 4. "OTEPDM,OUT token received when endpoint disabled mask. Applies to control OUT endpoints only." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 3. "STUPM,STUPM: SETUP phase done mask. Applies to control endpoints only." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" rgroup.long 0x818++0x3 line.long 0x0 "OTG_DAINT,OTG device all endpoints interrupt register" hexmask.long.word 0x0 16.--31. 1. "OEPINT,OUT endpoint interrupt bits" newline hexmask.long.word 0x0 0.--15. 1. "IEPINT,IN endpoint interrupt bits" group.long 0x81C++0x3 line.long 0x0 "OTG_DAINTMSK,OTG all endpoints interrupt mask register" hexmask.long.word 0x0 16.--31. 1. "OEPM,OUT EP interrupt mask bits" newline hexmask.long.word 0x0 0.--15. 1. "IEPM,IN EP interrupt mask bits" group.long 0x830++0x7 line.long 0x0 "OTG_DTHRCTL,OTG device threshold control register" bitfld.long 0x0 27. "ARPEN,Arbiter parking enable" "0,1" newline hexmask.long.word 0x0 17.--25. 1. "RXTHRLEN,Receive threshold length" newline bitfld.long 0x0 16. "RXTHREN,Receive threshold enable" "0,1" newline hexmask.long.word 0x0 2.--10. 1. "TXTHRLEN,Transmit threshold length" newline bitfld.long 0x0 1. "ISOTHREN,ISO IN endpoint threshold enable" "0,1" newline bitfld.long 0x0 0. "NONISOTHREN,Nonisochronous IN endpoints threshold enable" "0,1" line.long 0x4 "OTG_DIEPEMPMSK,OTG device IN endpoint FIFO empty interrupt mask register" hexmask.long.word 0x4 0.--15. 1. "INEPTXFEM,IN EP Tx FIFO empty interrupt mask bits" group.long 0x900++0x3 line.long 0x0 "OTG_DIEPCTL0,OTG device IN endpoint 0 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x900++0x3 line.long 0x0 "OTG_DIEPCTL0_ALTERNATE,OTG device IN endpoint 0 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x908++0x3 line.long 0x0 "OTG_DIEPINT0,OTG device IN endpoint 0 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x910++0x7 line.long 0x0 "OTG_DIEPTSIZ0,OTG device IN endpoint 0 transfer size register" bitfld.long 0x0 19.--20. "PKTCNT,Packet count" "0,1,2,3" newline hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA0,OTG device IN endpoint 0 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x918++0x3 line.long 0x0 "OTG_DTXFSTS0,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x920++0x3 line.long 0x0 "OTG_DIEPCTL1,OTG device IN endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x920++0x3 line.long 0x0 "OTG_DIEPCTL1_ALTERNATE,OTG device IN endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x928++0x3 line.long 0x0 "OTG_DIEPINT1,OTG device IN endpoint 1 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x930++0x7 line.long 0x0 "OTG_DIEPTSIZ1,OTG device IN endpoint 1 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA1,OTG device IN endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x938++0x3 line.long 0x0 "OTG_DTXFSTS1,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x940++0x3 line.long 0x0 "OTG_DIEPCTL2,OTG device IN endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x940++0x3 line.long 0x0 "OTG_DIEPCTL2_ALTERNATE,OTG device IN endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x948++0x3 line.long 0x0 "OTG_DIEPINT2,OTG device IN endpoint 2 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x950++0x7 line.long 0x0 "OTG_DIEPTSIZ2,OTG device IN endpoint 2 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA2,OTG device IN endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x958++0x3 line.long 0x0 "OTG_DTXFSTS2,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x960++0x3 line.long 0x0 "OTG_DIEPCTL3,OTG device IN endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x960++0x3 line.long 0x0 "OTG_DIEPCTL3_ALTERNATE,OTG device IN endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x968++0x3 line.long 0x0 "OTG_DIEPINT3,OTG device IN endpoint 3 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x970++0x7 line.long 0x0 "OTG_DIEPTSIZ3,OTG device IN endpoint 3 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA3,OTG device IN endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x978++0x3 line.long 0x0 "OTG_DTXFSTS3,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x980++0x3 line.long 0x0 "OTG_DIEPCTL4,OTG device IN endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x980++0x3 line.long 0x0 "OTG_DIEPCTL4_ALTERNATE,OTG device IN endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x988++0x3 line.long 0x0 "OTG_DIEPINT4,OTG device IN endpoint 4 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x990++0x7 line.long 0x0 "OTG_DIEPTSIZ4,OTG device IN endpoint 4 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA4,OTG device IN endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x998++0x3 line.long 0x0 "OTG_DTXFSTS4,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9A0++0x3 line.long 0x0 "OTG_DIEPCTL5,OTG device IN endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9A0++0x3 line.long 0x0 "OTG_DIEPCTL5_ALTERNATE,OTG device IN endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9A8++0x3 line.long 0x0 "OTG_DIEPINT5,OTG device IN endpoint 5 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9B0++0x7 line.long 0x0 "OTG_DIEPTSIZ5,OTG device IN endpoint 5 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA5,OTG device IN endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9B8++0x3 line.long 0x0 "OTG_DTXFSTS5,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9C0++0x3 line.long 0x0 "OTG_DIEPCTL6,OTG device IN endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9C0++0x3 line.long 0x0 "OTG_DIEPCTL6_ALTERNATE,OTG device IN endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9C8++0x3 line.long 0x0 "OTG_DIEPINT6,OTG device IN endpoint 6 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9D0++0x7 line.long 0x0 "OTG_DIEPTSIZ6,OTG device IN endpoint 6 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA6,OTG device IN endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9D8++0x3 line.long 0x0 "OTG_DTXFSTS6,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9E0++0x3 line.long 0x0 "OTG_DIEPCTL7,OTG device IN endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9E0++0x3 line.long 0x0 "OTG_DIEPCTL7_ALTERNATE,OTG device IN endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9E8++0x3 line.long 0x0 "OTG_DIEPINT7,OTG device IN endpoint 7 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9F0++0x7 line.long 0x0 "OTG_DIEPTSIZ7,OTG device IN endpoint 7 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA7,OTG device IN endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9F8++0x3 line.long 0x0 "OTG_DTXFSTS7,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0xA00++0x3 line.long 0x0 "OTG_DIEPCTL8,OTG device IN endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xA00++0x3 line.long 0x0 "OTG_DIEPCTL8_ALTERNATE,OTG device IN endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xA08++0x3 line.long 0x0 "OTG_DIEPINT8,OTG device IN endpoint 8 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xA10++0x7 line.long 0x0 "OTG_DIEPTSIZ8,OTG device IN endpoint 8 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA8,OTG device IN endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0xA18++0x3 line.long 0x0 "OTG_DTXFSTS8,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0xB00++0x3 line.long 0x0 "OTG_DOEPCTL0,OTG device control OUT endpoint 0 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline rbitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline rbitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline rbitfld.long 0x0 0.--1. "MPSIZ,Maximum packet size" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes" group.long 0xB08++0x3 line.long 0x0 "OTG_DOEPINT0,OTG device OUT endpoint 0 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB10++0x7 line.long 0x0 "OTG_DOEPTSIZ0,OTG device OUT endpoint 0 transfer size register" bitfld.long 0x0 29.--30. "STUPCNT,SETUP packet count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline bitfld.long 0x0 19. "PKTCNT,Packet count" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA0,OTG device OUT endpoint 0 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB20++0x3 line.long 0x0 "OTG_DOEPCTL1,OTG device OUT endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB20++0x3 line.long 0x0 "OTG_DOEPCTL1_ALTERNATE,OTG device OUT endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB28++0x3 line.long 0x0 "OTG_DOEPINT1,OTG device OUT endpoint 1 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB30++0x7 line.long 0x0 "OTG_DOEPTSIZ1,OTG device OUT endpoint 1 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA1,OTG device OUT endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB40++0x3 line.long 0x0 "OTG_DOEPCTL2,OTG device OUT endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB40++0x3 line.long 0x0 "OTG_DOEPCTL2_ALTERNATE,OTG device OUT endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB48++0x3 line.long 0x0 "OTG_DOEPINT2,OTG device OUT endpoint 2 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB50++0x7 line.long 0x0 "OTG_DOEPTSIZ2,OTG device OUT endpoint 2 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA2,OTG device OUT endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB60++0x3 line.long 0x0 "OTG_DOEPCTL3,OTG device OUT endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB60++0x3 line.long 0x0 "OTG_DOEPCTL3_ALTERNATE,OTG device OUT endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB68++0x3 line.long 0x0 "OTG_DOEPINT3,OTG device OUT endpoint 3 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB70++0x7 line.long 0x0 "OTG_DOEPTSIZ3,OTG device OUT endpoint 3 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA3,OTG device OUT endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB80++0x3 line.long 0x0 "OTG_DOEPCTL4,OTG device OUT endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB80++0x3 line.long 0x0 "OTG_DOEPCTL4_ALTERNATE,OTG device OUT endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB88++0x3 line.long 0x0 "OTG_DOEPINT4,OTG device OUT endpoint 4 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB90++0x7 line.long 0x0 "OTG_DOEPTSIZ4,OTG device OUT endpoint 4 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA4,OTG device OUT endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBA0++0x3 line.long 0x0 "OTG_DOEPCTL5,OTG device OUT endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBA0++0x3 line.long 0x0 "OTG_DOEPCTL5_ALTERNATE,OTG device OUT endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBA8++0x3 line.long 0x0 "OTG_DOEPINT5,OTG device OUT endpoint 5 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBB0++0x7 line.long 0x0 "OTG_DOEPTSIZ5,OTG device OUT endpoint 5 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA5,OTG device OUT endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBC0++0x3 line.long 0x0 "OTG_DOEPCTL6,OTG device OUT endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBC0++0x3 line.long 0x0 "OTG_DOEPCTL6_ALTERNATE,OTG device OUT endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBC8++0x3 line.long 0x0 "OTG_DOEPINT6,OTG device OUT endpoint 6 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBD0++0x7 line.long 0x0 "OTG_DOEPTSIZ6,OTG device OUT endpoint 6 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA6,OTG device OUT endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBE0++0x3 line.long 0x0 "OTG_DOEPCTL7,OTG device OUT endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBE0++0x3 line.long 0x0 "OTG_DOEPCTL7_ALTERNATE,OTG device OUT endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBE8++0x3 line.long 0x0 "OTG_DOEPINT7,OTG device OUT endpoint 7 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBF0++0x7 line.long 0x0 "OTG_DOEPTSIZ7,OTG device OUT endpoint 7 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA7,OTG device OUT endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xC00++0x3 line.long 0x0 "OTG_DOEPCTL8,OTG device OUT endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xC00++0x3 line.long 0x0 "OTG_DOEPCTL8_ALTERNATE,OTG device OUT endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xC08++0x3 line.long 0x0 "OTG_DOEPINT8,OTG device OUT endpoint 8 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xC10++0x7 line.long 0x0 "OTG_DOEPTSIZ8,OTG device OUT endpoint 8 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA8,OTG device OUT endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xE00++0x7 line.long 0x0 "OTG_PCGCCTL,OTG power and clock gating control register" rbitfld.long 0x0 7. "SUSP,Deep Sleep" "0,1" newline rbitfld.long 0x0 6. "PHYSLEEP,PHY in Sleep" "0,1" newline bitfld.long 0x0 5. "ENL1GTG,Enable sleep clock gating" "0,1" newline rbitfld.long 0x0 4. "PHYSUSP,PHY suspended" "0,1" newline bitfld.long 0x0 1. "GATEHCLK,Gate HCLK" "0,1" newline bitfld.long 0x0 0. "STPPCLK,Stop PHY clock" "0,1" line.long 0x4 "OTG_PCGCCTL1,OTG power and clock gating control register 1" bitfld.long 0x4 3. "RAMGATEEN,Enable RAM clock gating" "0,1" newline bitfld.long 0x4 1.--2. "CNTGATECLK,Counter for clock gating" "0: 64 clocks,1: 128 clocks,?,?" newline bitfld.long 0x4 0. "GATEEN,Enable active clock gating" "0,1" tree.end tree "OTG1_S" base ad:0x58040000 group.long 0x0++0x17 line.long 0x0 "OTG_GOTGCTL,OTG control and status register" rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0: Device mode,1: Host mode" newline bitfld.long 0x0 20. "OTGVER,OTG version" "0: OTG Version 1.3. OTG1.3 is obsolete for new..,1: OTG Version 2.0. In this version the core.." newline rbitfld.long 0x0 19. "BSVLD,B-session valid" "0: B-session is not valid.,1: B-session is valid." newline rbitfld.long 0x0 18. "ASVLD,A-session valid" "0: A-session is not valid,1: A-session is valid" newline rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0: Long debounce time used for physical connections..,1: Short debounce time used for soft connections.." newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0: The OTG controller is in A-device mode,1: The OTG controller is in B-device mode" newline bitfld.long 0x0 12. "EHEN,Embedded host enable" "0: OTG A device state machine is selected,1: Embedded host state machine is selected" newline bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value." "0: Bvalid value is '0' when BVALOEN = 1,1: Bvalid value is '1' when BVALOEN = 1" newline bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0: Override is disabled and Bvalid signal from the..,?" newline bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value." "0: Avalid value is '0' when AVALOEN = 1,1: Avalid value is '1' when AVALOEN = 1" newline bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable." "0: Override is disabled and Avalid signal from the..,1: Internally Avalid received from the PHY is.." newline bitfld.long 0x0 3. "VBVALOVAL,V less than sub>BUS less than /sub> valid override value." "0: vbusvalid value is '0' when VBVALOEN = 1,1: vbusvalid value is '1' when VBVALOEN = 1" newline bitfld.long 0x0 2. "VBVALOEN,V less than sub>BUS less than /sub> valid override enable." "0: Override is disabled and vbusvalid signal from..,1: Internally vbusvalid received from the PHY is.." line.long 0x4 "OTG_GOTGINT,OTG interrupt register" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" newline bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_GAHBCFG,OTG AHB configuration register" bitfld.long 0x8 8. "PTXFELVL,Periodic Tx FIFO empty level" "0: PTXFE (in OTG_GINTSTS) interrupt indicates that..,1: PTXFE (in OTG_GINTSTS) interrupt indicates that.." newline bitfld.long 0x8 7. "TXFELVL,Tx FIFO empty level" "0: The TXFE (in OTG_DIEPINTx) interrupt indicates..,1: The TXFE (in OTG_DIEPINTx) interrupt indicates.." newline bitfld.long 0x8 5. "DMAEN,DMA enabled" "0: The core operates in slave mode,1: The core operates in DMA mode" newline hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" newline bitfld.long 0x8 0. "GINTMSK,Global interrupt mask" "0: Mask the interrupt assertion to the application.,1: Unmask the interrupt assertion to the application." line.long 0xC "OTG_GUSBCFG,OTG USB configuration register" bitfld.long 0xC 30. "FDMOD,Force device mode" "0: Normal mode,1: Force device mode" newline bitfld.long 0xC 29. "FHMOD,Force host mode" "0: Normal mode,1: Force host mode" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing selection" "0: Data line pulsing using utmi_txvalid (default),1: Data line pulsing using utmi_termsel" newline bitfld.long 0xC 15. "PHYLPC,PHY Low-power clock select" "0: 480 MHz internal PLL clock,1: 48 MHz external clock" newline hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" newline bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_GRSTCTL,OTG reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" newline rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled" "0,1" newline hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x10 5. "TXFFLSH,Tx FIFO flush" "0,1" newline bitfld.long 0x10 4. "RXFFLSH,Rx FIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" newline bitfld.long 0x10 1. "PSRST,Partial soft reset" "0,1" newline bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_GINTSTS,OTG core interrupt register [alternate]" bitfld.long 0x14 31. "WKUPINT,Resume/remote wake-up detected interrupt" "0,1" newline bitfld.long 0x14 30. "SRQINT,Session request/new session detected interrupt" "0,1" newline bitfld.long 0x14 29. "DISCINT,Disconnect detected interrupt" "0,1" newline bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" newline bitfld.long 0x14 27. "LPMINT,LPM interrupt" "0,1" newline rbitfld.long 0x14 26. "PTXFE,Periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" newline rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" newline bitfld.long 0x14 23. "RSTDET,Reset detected interrupt" "0,1" newline bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" newline bitfld.long 0x14 21. "IPXFR,Incomplete periodic transfer" "0,1" newline bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" newline rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" newline bitfld.long 0x14 15. "EOPF,End of periodic frame interrupt" "0,1" newline bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1" newline bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" newline bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" newline bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" newline rbitfld.long 0x14 7. "GONAKEFF,Global OUT NAK effective" "0,1" newline rbitfld.long 0x14 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 4. "RXFLVL,Rx FIFO non-empty" "0,1" newline bitfld.long 0x14 3. "SOF,Start of frame" "0,1" newline rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" newline bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode" group.long 0x14++0x7 line.long 0x0 "OTG_GINTSTS_ALTERNATE,OTG core interrupt register [alternate]" bitfld.long 0x0 31. "WKUPINT,Resume/remote wake-up detected interrupt" "0,1" newline bitfld.long 0x0 30. "SRQINT,Session request/new session detected interrupt" "0,1" newline bitfld.long 0x0 29. "DISCINT,Disconnect detected interrupt" "0,1" newline bitfld.long 0x0 28. "CIDSCHG,Connector ID status change" "0,1" newline bitfld.long 0x0 27. "LPMINT,LPM interrupt" "0,1" newline rbitfld.long 0x0 26. "PTXFE,Periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x0 25. "HCINT,Host channels interrupt" "0,1" newline rbitfld.long 0x0 24. "HPRTINT,Host port interrupt" "0,1" newline bitfld.long 0x0 23. "RSTDET,Reset detected interrupt" "0,1" newline bitfld.long 0x0 22. "DATAFSUSP,Data fetch suspended" "0,1" newline bitfld.long 0x0 21. "INCOMPISOOUT,Incomplete isochronous OUT transfer" "0,1" newline bitfld.long 0x0 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1" newline rbitfld.long 0x0 19. "OEPINT,OUT endpoint interrupt" "0,1" newline rbitfld.long 0x0 18. "IEPINT,IN endpoint interrupt" "0,1" newline bitfld.long 0x0 15. "EOPF,End of periodic frame interrupt" "0,1" newline bitfld.long 0x0 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1" newline bitfld.long 0x0 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x0 12. "USBRST,USB reset" "0,1" newline bitfld.long 0x0 11. "USBSUSP,USB suspend" "0,1" newline bitfld.long 0x0 10. "ESUSP,Early suspend" "0,1" newline rbitfld.long 0x0 7. "GONAKEFF,Global OUT NAK effective" "0,1" newline rbitfld.long 0x0 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1" newline rbitfld.long 0x0 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x0 4. "RXFLVL,Rx FIFO non-empty" "0,1" newline bitfld.long 0x0 3. "SOF,Start of frame" "0,1" newline rbitfld.long 0x0 2. "OTGINT,OTG interrupt" "0,1" newline bitfld.long 0x0 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x0 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode" line.long 0x4 "OTG_GINTMSK,OTG interrupt mask register [alternate]" bitfld.long 0x4 31. "WUIM,Resume/remote wake-up detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 29. "DISCINT,Disconnect detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 26. "PTXFEM,Periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 25. "HCIM,Host channels interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline rbitfld.long 0x4 24. "PRTIM,Host port interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 21. "IPXFRM,Incomplete periodic transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 5. "NPTXFEM,Non-periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" group.long 0x18++0x3 line.long 0x0 "OTG_GINTMSK_ALTERNATE,OTG interrupt mask register [alternate]" bitfld.long 0x0 31. "WUIM,Resume/remote wake-up detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 23. "RSTDETM,Reset detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 22. "FSUSPM,Data fetch suspended mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 21. "IISOOXFRM,Incomplete isochronous OUT transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 20. "IISOIXFRM,Incomplete isochronous IN transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 19. "OEPINT,OUT endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 18. "IEPINT,IN endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 15. "EOPFM,End of periodic frame interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 14. "ISOODRPM,Isochronous OUT packet dropped interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 13. "ENUMDNEM,Enumeration done mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 12. "USBRST,USB reset mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 11. "USBSUSPM,USB suspend mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 10. "ESUSPM,Early suspend mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 7. "GONAKEFFM,Global OUT NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 6. "GINAKEFFM,Global non-periodic IN NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" rgroup.long 0x1C++0x3 line.long 0x0 "OTG_GRXSTSR,OTG receive status debug read register [alternate]" bitfld.long 0x0 27. "STSPHST,Status phase start" "0,1" newline hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_GRXSTSR_ALTERNATE,OTG receive status debug read register [alternate]" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_GRXSTSP,OTG status read and pop registers" bitfld.long 0x4 27. "STSPHST,Status phase start" "0,1" newline hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x4 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" rgroup.long 0x20++0x3 line.long 0x0 "OTG_GRXSTSP_ALTERNATE,OTG status read and pop registers" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_GRXFSIZ,OTG receive FIFO size register" hexmask.long.word 0x0 0.--15. 1. "RXFD,Rx FIFO depth" line.long 0x4 "OTG_HNPTXFSIZ,OTG host non-periodic transmit FIFO size register [alternate]" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Non-periodic Tx FIFO depth" newline hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Non-periodic transmit RAM start address" group.long 0x28++0x3 line.long 0x0 "OTG_HNPTXFSIZ_ALTERNATE,OTG host non-periodic transmit FIFO size register [alternate]" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 Tx FIFO depth" newline hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start address" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HNPTXSTS,OTG non-periodic transmit FIFO/queue status register" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the non-periodic transmit request queue" newline hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Non-periodic transmit request queue space available" newline hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Non-periodic Tx FIFO space available" group.long 0x38++0x7 line.long 0x0 "OTG_GCCFG,OTG general core configuration register" bitfld.long 0x0 28. "IDPULLUPDIS,Disable ID pin pull-up" "0: Enables ID pin pull-up,1: Disable ID pin pull-up" newline bitfld.long 0x0 26. "BCDEN,Force Battery charging (BC) mode" "0: Normal USB mode,1: Battery Charging mode" newline bitfld.long 0x0 25. "FORCEHOSTPD,Force host mode pull-downs" "0: Do not force host mode pull-downs,1: Force host mode pull-downs" newline bitfld.long 0x0 23. "VBVALOVAL,Software override value of the VBUS B-session detection" "0: B-session inactive,1: B-session active" newline bitfld.long 0x0 22. "SDEN,Secondary detection enable" "0: Secondary detection disabled,1: Secondary detection enabled" newline bitfld.long 0x0 20. "PDEN,Primary detection enable" "0: Primary detection disabled,1: Primary detection enabled" newline bitfld.long 0x0 19. "DCDEN,Data Contact Detection enable" "0: Data Contact Detection disabled,1: Data Contact Detection enabled" newline bitfld.long 0x0 18. "HVDMSRCEN,Host CDP port Voltage source enable on DM" "0: DM voltage source disabled,1: DM Voltage source enabled" newline bitfld.long 0x0 17. "HCDPDETEN,Host CDP port voltage detector enable on DP" "0: DP voltage detection disabled,1: DP voltage detection enabled" newline bitfld.long 0x0 16. "HCDPEN,Host CDP behavior enable" "0: Disable CDP behavior,1: Enable CDP behavior" newline rbitfld.long 0x0 4. "VBUSVLD,VBUS valid indicator" "0: VBUS is below VBUS valid threshold,1: VBUS is above VBUS valid threshold" newline rbitfld.long 0x0 3. "SESSVLD,VBUS session indicator" "0: VBUS is below VBUS session threshold,1: VBUS is above VBUS session threshold" newline rbitfld.long 0x0 2. "FSVMINUS,Single-Ended DM indicator" "0: DM voltage at low level,1: DM voltage at high level" newline rbitfld.long 0x0 1. "FSVPLUS,Single-Ended DP indicator" "0: DM voltage at low level,1: DM voltage at high level" newline rbitfld.long 0x0 0. "CHGDET,Charger detection result of the current mode (primary or secondary)." "0: Low value on pin,1: High value on pin" line.long 0x4 "OTG_CID,OTG core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x54++0x3 line.long 0x0 "OTG_GLPMCFG,OTG core LPM configuration register" bitfld.long 0x0 28. "ENBESL,Enable best effort service latency" "0: The core works as described in the following..,1: The core works as described in the LPM Errata:" newline rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" newline bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep state resume OK" "0: The application or host cannot start resume from..,1: The application or host can start resume from.." newline rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0: Core not in L1,1: Core in L1" newline rbitfld.long 0x0 13.--14. "LPMRSP,LPM response" "0: ERROR (No handshake response),1: STALL,2: NYET,3: ACK" newline bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" newline bitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service latency" newline bitfld.long 0x0 1. "LPMACK,LPM token acknowledge enable" "0: NYET,1: ACK" newline bitfld.long 0x0 0. "LPMEN,LPM support enable" "0: LPM capability is not enabled,1: LPM capability is enabled" group.long 0x100++0x23 line.long 0x0 "OTG_HPTXFSIZ,OTG host periodic transmit FIFO size register" hexmask.long.word 0x0 16.--31. 1. "PTXFSIZ,Host periodic Tx FIFO depth" newline hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic Tx FIFO start address" line.long 0x4 "OTG_DIEPTXF1,OTG device IN endpoint transmit FIFO 1 size register" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x8 "OTG_DIEPTXF2,OTG device IN endpoint transmit FIFO 2 size register" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0xC "OTG_DIEPTXF3,OTG device IN endpoint transmit FIFO 3 size register" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x10 "OTG_DIEPTXF4,OTG device IN endpoint transmit FIFO 4 size register" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x14 "OTG_DIEPTXF5,OTG device IN endpoint transmit FIFO 5 size register" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x18 "OTG_DIEPTXF6,OTG device IN endpoint transmit FIFO 6 size register" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x1C "OTG_DIEPTXF7,OTG device IN endpoint transmit FIFO 7 size register" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x20 "OTG_DIEPTXF8,OTG device IN endpoint transmit FIFO 8 size register" hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" group.long 0x400++0x7 line.long 0x0 "OTG_HCFG,OTG host configuration register" rbitfld.long 0x0 2. "FSLSS,FS- and LS-only support" "0,1" newline bitfld.long 0x0 0.--1. "FSLSPCS,FS/LS PHY clock select" "?,1: PHY clock is running at 48 MHz,2: Select 6 MHz PHY clock frequency,?" line.long 0x4 "OTG_HFIR,OTG host frame interval register" bitfld.long 0x4 16. "RLDCTRL,Reload control" "0: The HFIR cannot be reloaded dynamically,1: The HFIR can be dynamically reloaded during run.." newline hexmask.long.word 0x4 0.--15. 1. "FRIVL,Frame interval" rgroup.long 0x408++0x3 line.long 0x0 "OTG_HFNUM,OTG host frame number/frame time remaining register" hexmask.long.word 0x0 16.--31. 1. "FTREM,Frame time remaining" newline hexmask.long.word 0x0 0.--15. 1. "FRNUM,Frame number" rgroup.long 0x410++0x7 line.long 0x0 "OTG_HPTXSTS,OTG_Host periodic transmit FIFO/queue status register" hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,Top of the periodic transmit request queue" newline hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,Periodic transmit request queue space available" newline hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,Periodic transmit data FIFO space available" line.long 0x4 "OTG_HAINT,OTG host all channels interrupt register" hexmask.long.word 0x4 0.--15. 1. "HAINT,Channel interrupts" group.long 0x418++0x3 line.long 0x0 "OTG_HAINTMSK,OTG host all channels interrupt mask register" hexmask.long.word 0x0 0.--15. 1. "HAINTM,Channel interrupt mask" group.long 0x440++0x3 line.long 0x0 "OTG_HPRT,OTG host port control and status register" rbitfld.long 0x0 17.--18. "PSPD,Port speed" "0: High speed,1: Full speed,2: Low speed,?" newline hexmask.long.byte 0x0 13.--16. 1. "PTCTL,Port test control" newline bitfld.long 0x0 12. "PPWR,Port power" "0: Power off,1: Power on" newline rbitfld.long 0x0 10.--11. "PLSTS,Port line status" "0,1,2,3" newline bitfld.long 0x0 8. "PRST,Port reset" "0: Port not in reset,1: Port in reset" newline bitfld.long 0x0 7. "PSUSP,Port suspend" "0: Port not in suspend mode,1: Port in suspend mode" newline bitfld.long 0x0 6. "PRES,Port resume" "0: No resume driven,1: Resume driven" newline bitfld.long 0x0 5. "POCCHNG,Port overcurrent change" "0,1" newline rbitfld.long 0x0 4. "POCA,Port overcurrent active" "0: No overcurrent condition,1: Overcurrent condition" newline bitfld.long 0x0 3. "PENCHNG,Port enable/disable change" "0,1" newline bitfld.long 0x0 2. "PENA,Port enable" "0: Port disabled,1: Port enabled" newline bitfld.long 0x0 1. "PCDET,Port connect detected" "0,1" newline rbitfld.long 0x0 0. "PCSTS,Port connect status" "0: No device is attached to the port,1: A device is attached to the port" group.long 0x500++0x17 line.long 0x0 "OTG_HCCHAR0,OTG host channel 0 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT0,OTG host channel 0 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT0,OTG host channel 0 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK0,OTG host channel 0 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ0,OTG host channel 0 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA0,OTG host channel 0 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x520++0x17 line.long 0x0 "OTG_HCCHAR1,OTG host channel 1 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT1,OTG host channel 1 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT1,OTG host channel 1 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK1,OTG host channel 1 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ1,OTG host channel 1 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA1,OTG host channel 1 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x540++0x17 line.long 0x0 "OTG_HCCHAR2,OTG host channel 2 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT2,OTG host channel 2 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT2,OTG host channel 2 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK2,OTG host channel 2 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ2,OTG host channel 2 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA2,OTG host channel 2 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x560++0x17 line.long 0x0 "OTG_HCCHAR3,OTG host channel 3 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT3,OTG host channel 3 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT3,OTG host channel 3 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK3,OTG host channel 3 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ3,OTG host channel 3 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA3,OTG host channel 3 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x580++0x17 line.long 0x0 "OTG_HCCHAR4,OTG host channel 4 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT4,OTG host channel 4 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT4,OTG host channel 4 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK4,OTG host channel 4 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ4,OTG host channel 4 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA4,OTG host channel 4 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5A0++0x17 line.long 0x0 "OTG_HCCHAR5,OTG host channel 5 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT5,OTG host channel 5 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT5,OTG host channel 5 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK5,OTG host channel 5 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ5,OTG host channel 5 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA5,OTG host channel 5 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5C0++0x17 line.long 0x0 "OTG_HCCHAR6,OTG host channel 6 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT6,OTG host channel 6 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT6,OTG host channel 6 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK6,OTG host channel 6 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ6,OTG host channel 6 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA6,OTG host channel 6 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5E0++0x17 line.long 0x0 "OTG_HCCHAR7,OTG host channel 7 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT7,OTG host channel 7 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT7,OTG host channel 7 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK7,OTG host channel 7 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ7,OTG host channel 7 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA7,OTG host channel 7 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x600++0x17 line.long 0x0 "OTG_HCCHAR8,OTG host channel 8 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT8,OTG host channel 8 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT8,OTG host channel 8 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK8,OTG host channel 8 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ8,OTG host channel 8 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA8,OTG host channel 8 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x620++0x17 line.long 0x0 "OTG_HCCHAR9,OTG host channel 9 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT9,OTG host channel 9 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT9,OTG host channel 9 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK9,OTG host channel 9 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ9,OTG host channel 9 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA9,OTG host channel 9 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x640++0x17 line.long 0x0 "OTG_HCCHAR10,OTG host channel 10 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT10,OTG host channel 10 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT10,OTG host channel 10 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK10,OTG host channel 10 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ10,OTG host channel 10 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA10,OTG host channel 10 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x660++0x17 line.long 0x0 "OTG_HCCHAR11,OTG host channel 11 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT11,OTG host channel 11 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT11,OTG host channel 11 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK11,OTG host channel 11 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ11,OTG host channel 11 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA11,OTG host channel 11 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x680++0x17 line.long 0x0 "OTG_HCCHAR12,OTG host channel 12 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT12,OTG host channel 12 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT12,OTG host channel 12 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK12,OTG host channel 12 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ12,OTG host channel 12 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA12,OTG host channel 12 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6A0++0x17 line.long 0x0 "OTG_HCCHAR13,OTG host channel 13 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT13,OTG host channel 13 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT13,OTG host channel 13 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK13,OTG host channel 13 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ13,OTG host channel 13 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA13,OTG host channel 13 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6C0++0x17 line.long 0x0 "OTG_HCCHAR14,OTG host channel 14 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT14,OTG host channel 14 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT14,OTG host channel 14 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK14,OTG host channel 14 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ14,OTG host channel 14 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA14,OTG host channel 14 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6E0++0x17 line.long 0x0 "OTG_HCCHAR15,OTG host channel 15 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT15,OTG host channel 15 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT15,OTG host channel 15 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK15,OTG host channel 15 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ15,OTG host channel 15 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA15,OTG host channel 15 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x800++0x7 line.long 0x0 "OTG_DCFG,OTG device configuration register" bitfld.long 0x0 24.--25. "PERSCHIVL,Periodic schedule interval" "0: 25% of (micro)frame,1: 50% of (micro)frame,2: 75% of (micro)frame,?" newline bitfld.long 0x0 15. "ERRATIM,Erratic error interrupt mask" "0: Early suspend interrupt is generated on erratic..,1: Mask early suspend interrupt on erratic error" newline bitfld.long 0x0 11.--12. "PFIVL,Periodic frame interval" "0: 80% of the frame interval,1: 85% of the frame interval,2: 90% of the frame interval,3: 95% of the frame interval" newline hexmask.long.byte 0x0 4.--10. 1. "DAD,Device address" newline bitfld.long 0x0 2. "NZLSOHSK,Non-zero-length status OUT handshake" "0: Send the received OUT packet to the application..,1: Send a STALL handshake on a nonzero-length.." newline bitfld.long 0x0 0.--1. "DSPD,Device speed" "0: High speed,1: Full speed,?,?" line.long 0x4 "OTG_DCTL,OTG device control register" bitfld.long 0x4 18. "DSBESLRJCT,Deep sleep BESL reject" "0,1" newline bitfld.long 0x4 11. "POPRGDNE,Power-on programming done" "0,1" newline bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1" newline bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1" newline bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1" newline bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1" newline bitfld.long 0x4 4.--6. "TCTL,Test control" "0: Test mode disabled,1: Test_J mode,2: Test_K mode,3: Test_SE0_NAK mode,4: Test_Packet mode,5: Test_Force_Enable,?,?" newline rbitfld.long 0x4 3. "GONSTS,Global OUT NAK status" "0: A handshake is sent based on the FIFO status and..,1: No data is written to the Rx FIFO irrespective.." newline rbitfld.long 0x4 2. "GINSTS,Global IN NAK status" "0: A handshake is sent out based on the data..,1: A NAK handshake is sent out on all non-periodic.." newline bitfld.long 0x4 1. "SDIS,Soft disconnect" "0: Normal operation. When this bit is cleared after..,1: The core generates a device disconnect event to.." newline bitfld.long 0x4 0. "RWUSIG,Remote wake-up signaling" "0,1" rgroup.long 0x808++0x3 line.long 0x0 "OTG_DSTS,OTG device status register" bitfld.long 0x0 22.--23. "DEVLNSTS,Device line status" "0,1,2,3" newline hexmask.long.word 0x0 8.--21. 1. "FNSOF,Frame number of the received SOF" newline bitfld.long 0x0 3. "EERR,Erratic error" "0,1" newline bitfld.long 0x0 1.--2. "ENUMSPD,Enumerated speed" "0: High Speed,1: Full Speed,?,?" newline bitfld.long 0x0 0. "SUSPSTS,Suspend status" "0,1" group.long 0x810++0x7 line.long 0x0 "OTG_DIEPMSK,OTG device IN endpoint common interrupt mask register" bitfld.long 0x0 13. "NAKM,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 8. "TXFURM,FIFO underrun mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 6. "INEPNEM,IN endpoint NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 5. "INEPNMM,IN token received with EP mismatch mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 4. "ITTXFEMSK,IN token received when Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 3. "TOM,Timeout condition mask (Non-isochronous endpoints)" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x4 "OTG_DOEPMSK,OTG device OUT endpoint common interrupt mask register" bitfld.long 0x4 14. "NYETMSK,NYET interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 13. "NAKMSK,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 12. "BERRM,Babble error interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 8. "OUTPKTERRM,Out packet error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 6. "B2BSTUPM,Back-to-back SETUP packets received mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 5. "STSPHSRXM,Status phase received for control write mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 4. "OTEPDM,OUT token received when endpoint disabled mask. Applies to control OUT endpoints only." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 3. "STUPM,STUPM: SETUP phase done mask. Applies to control endpoints only." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" rgroup.long 0x818++0x3 line.long 0x0 "OTG_DAINT,OTG device all endpoints interrupt register" hexmask.long.word 0x0 16.--31. 1. "OEPINT,OUT endpoint interrupt bits" newline hexmask.long.word 0x0 0.--15. 1. "IEPINT,IN endpoint interrupt bits" group.long 0x81C++0x3 line.long 0x0 "OTG_DAINTMSK,OTG all endpoints interrupt mask register" hexmask.long.word 0x0 16.--31. 1. "OEPM,OUT EP interrupt mask bits" newline hexmask.long.word 0x0 0.--15. 1. "IEPM,IN EP interrupt mask bits" group.long 0x830++0x7 line.long 0x0 "OTG_DTHRCTL,OTG device threshold control register" bitfld.long 0x0 27. "ARPEN,Arbiter parking enable" "0,1" newline hexmask.long.word 0x0 17.--25. 1. "RXTHRLEN,Receive threshold length" newline bitfld.long 0x0 16. "RXTHREN,Receive threshold enable" "0,1" newline hexmask.long.word 0x0 2.--10. 1. "TXTHRLEN,Transmit threshold length" newline bitfld.long 0x0 1. "ISOTHREN,ISO IN endpoint threshold enable" "0,1" newline bitfld.long 0x0 0. "NONISOTHREN,Nonisochronous IN endpoints threshold enable" "0,1" line.long 0x4 "OTG_DIEPEMPMSK,OTG device IN endpoint FIFO empty interrupt mask register" hexmask.long.word 0x4 0.--15. 1. "INEPTXFEM,IN EP Tx FIFO empty interrupt mask bits" group.long 0x900++0x3 line.long 0x0 "OTG_DIEPCTL0,OTG device IN endpoint 0 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x900++0x3 line.long 0x0 "OTG_DIEPCTL0_ALTERNATE,OTG device IN endpoint 0 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x908++0x3 line.long 0x0 "OTG_DIEPINT0,OTG device IN endpoint 0 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x910++0x7 line.long 0x0 "OTG_DIEPTSIZ0,OTG device IN endpoint 0 transfer size register" bitfld.long 0x0 19.--20. "PKTCNT,Packet count" "0,1,2,3" newline hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA0,OTG device IN endpoint 0 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x918++0x3 line.long 0x0 "OTG_DTXFSTS0,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x920++0x3 line.long 0x0 "OTG_DIEPCTL1,OTG device IN endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x920++0x3 line.long 0x0 "OTG_DIEPCTL1_ALTERNATE,OTG device IN endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x928++0x3 line.long 0x0 "OTG_DIEPINT1,OTG device IN endpoint 1 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x930++0x7 line.long 0x0 "OTG_DIEPTSIZ1,OTG device IN endpoint 1 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA1,OTG device IN endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x938++0x3 line.long 0x0 "OTG_DTXFSTS1,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x940++0x3 line.long 0x0 "OTG_DIEPCTL2,OTG device IN endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x940++0x3 line.long 0x0 "OTG_DIEPCTL2_ALTERNATE,OTG device IN endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x948++0x3 line.long 0x0 "OTG_DIEPINT2,OTG device IN endpoint 2 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x950++0x7 line.long 0x0 "OTG_DIEPTSIZ2,OTG device IN endpoint 2 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA2,OTG device IN endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x958++0x3 line.long 0x0 "OTG_DTXFSTS2,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x960++0x3 line.long 0x0 "OTG_DIEPCTL3,OTG device IN endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x960++0x3 line.long 0x0 "OTG_DIEPCTL3_ALTERNATE,OTG device IN endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x968++0x3 line.long 0x0 "OTG_DIEPINT3,OTG device IN endpoint 3 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x970++0x7 line.long 0x0 "OTG_DIEPTSIZ3,OTG device IN endpoint 3 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA3,OTG device IN endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x978++0x3 line.long 0x0 "OTG_DTXFSTS3,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x980++0x3 line.long 0x0 "OTG_DIEPCTL4,OTG device IN endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x980++0x3 line.long 0x0 "OTG_DIEPCTL4_ALTERNATE,OTG device IN endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x988++0x3 line.long 0x0 "OTG_DIEPINT4,OTG device IN endpoint 4 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x990++0x7 line.long 0x0 "OTG_DIEPTSIZ4,OTG device IN endpoint 4 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA4,OTG device IN endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x998++0x3 line.long 0x0 "OTG_DTXFSTS4,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9A0++0x3 line.long 0x0 "OTG_DIEPCTL5,OTG device IN endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9A0++0x3 line.long 0x0 "OTG_DIEPCTL5_ALTERNATE,OTG device IN endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9A8++0x3 line.long 0x0 "OTG_DIEPINT5,OTG device IN endpoint 5 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9B0++0x7 line.long 0x0 "OTG_DIEPTSIZ5,OTG device IN endpoint 5 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA5,OTG device IN endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9B8++0x3 line.long 0x0 "OTG_DTXFSTS5,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9C0++0x3 line.long 0x0 "OTG_DIEPCTL6,OTG device IN endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9C0++0x3 line.long 0x0 "OTG_DIEPCTL6_ALTERNATE,OTG device IN endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9C8++0x3 line.long 0x0 "OTG_DIEPINT6,OTG device IN endpoint 6 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9D0++0x7 line.long 0x0 "OTG_DIEPTSIZ6,OTG device IN endpoint 6 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA6,OTG device IN endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9D8++0x3 line.long 0x0 "OTG_DTXFSTS6,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9E0++0x3 line.long 0x0 "OTG_DIEPCTL7,OTG device IN endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9E0++0x3 line.long 0x0 "OTG_DIEPCTL7_ALTERNATE,OTG device IN endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9E8++0x3 line.long 0x0 "OTG_DIEPINT7,OTG device IN endpoint 7 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9F0++0x7 line.long 0x0 "OTG_DIEPTSIZ7,OTG device IN endpoint 7 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA7,OTG device IN endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9F8++0x3 line.long 0x0 "OTG_DTXFSTS7,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0xA00++0x3 line.long 0x0 "OTG_DIEPCTL8,OTG device IN endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xA00++0x3 line.long 0x0 "OTG_DIEPCTL8_ALTERNATE,OTG device IN endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xA08++0x3 line.long 0x0 "OTG_DIEPINT8,OTG device IN endpoint 8 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xA10++0x7 line.long 0x0 "OTG_DIEPTSIZ8,OTG device IN endpoint 8 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA8,OTG device IN endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0xA18++0x3 line.long 0x0 "OTG_DTXFSTS8,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0xB00++0x3 line.long 0x0 "OTG_DOEPCTL0,OTG device control OUT endpoint 0 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline rbitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline rbitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline rbitfld.long 0x0 0.--1. "MPSIZ,Maximum packet size" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes" group.long 0xB08++0x3 line.long 0x0 "OTG_DOEPINT0,OTG device OUT endpoint 0 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB10++0x7 line.long 0x0 "OTG_DOEPTSIZ0,OTG device OUT endpoint 0 transfer size register" bitfld.long 0x0 29.--30. "STUPCNT,SETUP packet count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline bitfld.long 0x0 19. "PKTCNT,Packet count" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA0,OTG device OUT endpoint 0 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB20++0x3 line.long 0x0 "OTG_DOEPCTL1,OTG device OUT endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB20++0x3 line.long 0x0 "OTG_DOEPCTL1_ALTERNATE,OTG device OUT endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB28++0x3 line.long 0x0 "OTG_DOEPINT1,OTG device OUT endpoint 1 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB30++0x7 line.long 0x0 "OTG_DOEPTSIZ1,OTG device OUT endpoint 1 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA1,OTG device OUT endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB40++0x3 line.long 0x0 "OTG_DOEPCTL2,OTG device OUT endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB40++0x3 line.long 0x0 "OTG_DOEPCTL2_ALTERNATE,OTG device OUT endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB48++0x3 line.long 0x0 "OTG_DOEPINT2,OTG device OUT endpoint 2 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB50++0x7 line.long 0x0 "OTG_DOEPTSIZ2,OTG device OUT endpoint 2 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA2,OTG device OUT endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB60++0x3 line.long 0x0 "OTG_DOEPCTL3,OTG device OUT endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB60++0x3 line.long 0x0 "OTG_DOEPCTL3_ALTERNATE,OTG device OUT endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB68++0x3 line.long 0x0 "OTG_DOEPINT3,OTG device OUT endpoint 3 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB70++0x7 line.long 0x0 "OTG_DOEPTSIZ3,OTG device OUT endpoint 3 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA3,OTG device OUT endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB80++0x3 line.long 0x0 "OTG_DOEPCTL4,OTG device OUT endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB80++0x3 line.long 0x0 "OTG_DOEPCTL4_ALTERNATE,OTG device OUT endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB88++0x3 line.long 0x0 "OTG_DOEPINT4,OTG device OUT endpoint 4 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB90++0x7 line.long 0x0 "OTG_DOEPTSIZ4,OTG device OUT endpoint 4 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA4,OTG device OUT endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBA0++0x3 line.long 0x0 "OTG_DOEPCTL5,OTG device OUT endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBA0++0x3 line.long 0x0 "OTG_DOEPCTL5_ALTERNATE,OTG device OUT endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBA8++0x3 line.long 0x0 "OTG_DOEPINT5,OTG device OUT endpoint 5 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBB0++0x7 line.long 0x0 "OTG_DOEPTSIZ5,OTG device OUT endpoint 5 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA5,OTG device OUT endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBC0++0x3 line.long 0x0 "OTG_DOEPCTL6,OTG device OUT endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBC0++0x3 line.long 0x0 "OTG_DOEPCTL6_ALTERNATE,OTG device OUT endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBC8++0x3 line.long 0x0 "OTG_DOEPINT6,OTG device OUT endpoint 6 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBD0++0x7 line.long 0x0 "OTG_DOEPTSIZ6,OTG device OUT endpoint 6 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA6,OTG device OUT endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBE0++0x3 line.long 0x0 "OTG_DOEPCTL7,OTG device OUT endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBE0++0x3 line.long 0x0 "OTG_DOEPCTL7_ALTERNATE,OTG device OUT endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBE8++0x3 line.long 0x0 "OTG_DOEPINT7,OTG device OUT endpoint 7 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBF0++0x7 line.long 0x0 "OTG_DOEPTSIZ7,OTG device OUT endpoint 7 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA7,OTG device OUT endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xC00++0x3 line.long 0x0 "OTG_DOEPCTL8,OTG device OUT endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xC00++0x3 line.long 0x0 "OTG_DOEPCTL8_ALTERNATE,OTG device OUT endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xC08++0x3 line.long 0x0 "OTG_DOEPINT8,OTG device OUT endpoint 8 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xC10++0x7 line.long 0x0 "OTG_DOEPTSIZ8,OTG device OUT endpoint 8 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA8,OTG device OUT endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xE00++0x7 line.long 0x0 "OTG_PCGCCTL,OTG power and clock gating control register" rbitfld.long 0x0 7. "SUSP,Deep Sleep" "0,1" newline rbitfld.long 0x0 6. "PHYSLEEP,PHY in Sleep" "0,1" newline bitfld.long 0x0 5. "ENL1GTG,Enable sleep clock gating" "0,1" newline rbitfld.long 0x0 4. "PHYSUSP,PHY suspended" "0,1" newline bitfld.long 0x0 1. "GATEHCLK,Gate HCLK" "0,1" newline bitfld.long 0x0 0. "STPPCLK,Stop PHY clock" "0,1" line.long 0x4 "OTG_PCGCCTL1,OTG power and clock gating control register 1" bitfld.long 0x4 3. "RAMGATEEN,Enable RAM clock gating" "0,1" newline bitfld.long 0x4 1.--2. "CNTGATECLK,Counter for clock gating" "0: 64 clocks,1: 128 clocks,?,?" newline bitfld.long 0x4 0. "GATEEN,Enable active clock gating" "0,1" tree.end tree "OTG2" base ad:0x48080000 group.long 0x0++0x17 line.long 0x0 "OTG_GOTGCTL,OTG control and status register" rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0: Device mode,1: Host mode" newline bitfld.long 0x0 20. "OTGVER,OTG version" "0: OTG Version 1.3. OTG1.3 is obsolete for new..,1: OTG Version 2.0. In this version the core.." newline rbitfld.long 0x0 19. "BSVLD,B-session valid" "0: B-session is not valid.,1: B-session is valid." newline rbitfld.long 0x0 18. "ASVLD,A-session valid" "0: A-session is not valid,1: A-session is valid" newline rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0: Long debounce time used for physical connections..,1: Short debounce time used for soft connections.." newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0: The OTG controller is in A-device mode,1: The OTG controller is in B-device mode" newline bitfld.long 0x0 12. "EHEN,Embedded host enable" "0: OTG A device state machine is selected,1: Embedded host state machine is selected" newline bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value." "0: Bvalid value is '0' when BVALOEN = 1,1: Bvalid value is '1' when BVALOEN = 1" newline bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0: Override is disabled and Bvalid signal from the..,?" newline bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value." "0: Avalid value is '0' when AVALOEN = 1,1: Avalid value is '1' when AVALOEN = 1" newline bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable." "0: Override is disabled and Avalid signal from the..,1: Internally Avalid received from the PHY is.." newline bitfld.long 0x0 3. "VBVALOVAL,V less than sub>BUS less than /sub> valid override value." "0: vbusvalid value is '0' when VBVALOEN = 1,1: vbusvalid value is '1' when VBVALOEN = 1" newline bitfld.long 0x0 2. "VBVALOEN,V less than sub>BUS less than /sub> valid override enable." "0: Override is disabled and vbusvalid signal from..,1: Internally vbusvalid received from the PHY is.." line.long 0x4 "OTG_GOTGINT,OTG interrupt register" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" newline bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_GAHBCFG,OTG AHB configuration register" bitfld.long 0x8 8. "PTXFELVL,Periodic Tx FIFO empty level" "0: PTXFE (in OTG_GINTSTS) interrupt indicates that..,1: PTXFE (in OTG_GINTSTS) interrupt indicates that.." newline bitfld.long 0x8 7. "TXFELVL,Tx FIFO empty level" "0: The TXFE (in OTG_DIEPINTx) interrupt indicates..,1: The TXFE (in OTG_DIEPINTx) interrupt indicates.." newline bitfld.long 0x8 5. "DMAEN,DMA enabled" "0: The core operates in slave mode,1: The core operates in DMA mode" newline hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" newline bitfld.long 0x8 0. "GINTMSK,Global interrupt mask" "0: Mask the interrupt assertion to the application.,1: Unmask the interrupt assertion to the application." line.long 0xC "OTG_GUSBCFG,OTG USB configuration register" bitfld.long 0xC 30. "FDMOD,Force device mode" "0: Normal mode,1: Force device mode" newline bitfld.long 0xC 29. "FHMOD,Force host mode" "0: Normal mode,1: Force host mode" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing selection" "0: Data line pulsing using utmi_txvalid (default),1: Data line pulsing using utmi_termsel" newline bitfld.long 0xC 15. "PHYLPC,PHY Low-power clock select" "0: 480 MHz internal PLL clock,1: 48 MHz external clock" newline hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" newline bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_GRSTCTL,OTG reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" newline rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled" "0,1" newline hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x10 5. "TXFFLSH,Tx FIFO flush" "0,1" newline bitfld.long 0x10 4. "RXFFLSH,Rx FIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" newline bitfld.long 0x10 1. "PSRST,Partial soft reset" "0,1" newline bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_GINTSTS,OTG core interrupt register [alternate]" bitfld.long 0x14 31. "WKUPINT,Resume/remote wake-up detected interrupt" "0,1" newline bitfld.long 0x14 30. "SRQINT,Session request/new session detected interrupt" "0,1" newline bitfld.long 0x14 29. "DISCINT,Disconnect detected interrupt" "0,1" newline bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" newline bitfld.long 0x14 27. "LPMINT,LPM interrupt" "0,1" newline rbitfld.long 0x14 26. "PTXFE,Periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" newline rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" newline bitfld.long 0x14 23. "RSTDET,Reset detected interrupt" "0,1" newline bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" newline bitfld.long 0x14 21. "IPXFR,Incomplete periodic transfer" "0,1" newline bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" newline rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" newline bitfld.long 0x14 15. "EOPF,End of periodic frame interrupt" "0,1" newline bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1" newline bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" newline bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" newline bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" newline rbitfld.long 0x14 7. "GONAKEFF,Global OUT NAK effective" "0,1" newline rbitfld.long 0x14 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 4. "RXFLVL,Rx FIFO non-empty" "0,1" newline bitfld.long 0x14 3. "SOF,Start of frame" "0,1" newline rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" newline bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode" group.long 0x14++0x7 line.long 0x0 "OTG_GINTSTS_ALTERNATE,OTG core interrupt register [alternate]" bitfld.long 0x0 31. "WKUPINT,Resume/remote wake-up detected interrupt" "0,1" newline bitfld.long 0x0 30. "SRQINT,Session request/new session detected interrupt" "0,1" newline bitfld.long 0x0 29. "DISCINT,Disconnect detected interrupt" "0,1" newline bitfld.long 0x0 28. "CIDSCHG,Connector ID status change" "0,1" newline bitfld.long 0x0 27. "LPMINT,LPM interrupt" "0,1" newline rbitfld.long 0x0 26. "PTXFE,Periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x0 25. "HCINT,Host channels interrupt" "0,1" newline rbitfld.long 0x0 24. "HPRTINT,Host port interrupt" "0,1" newline bitfld.long 0x0 23. "RSTDET,Reset detected interrupt" "0,1" newline bitfld.long 0x0 22. "DATAFSUSP,Data fetch suspended" "0,1" newline bitfld.long 0x0 21. "INCOMPISOOUT,Incomplete isochronous OUT transfer" "0,1" newline bitfld.long 0x0 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1" newline rbitfld.long 0x0 19. "OEPINT,OUT endpoint interrupt" "0,1" newline rbitfld.long 0x0 18. "IEPINT,IN endpoint interrupt" "0,1" newline bitfld.long 0x0 15. "EOPF,End of periodic frame interrupt" "0,1" newline bitfld.long 0x0 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1" newline bitfld.long 0x0 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x0 12. "USBRST,USB reset" "0,1" newline bitfld.long 0x0 11. "USBSUSP,USB suspend" "0,1" newline bitfld.long 0x0 10. "ESUSP,Early suspend" "0,1" newline rbitfld.long 0x0 7. "GONAKEFF,Global OUT NAK effective" "0,1" newline rbitfld.long 0x0 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1" newline rbitfld.long 0x0 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x0 4. "RXFLVL,Rx FIFO non-empty" "0,1" newline bitfld.long 0x0 3. "SOF,Start of frame" "0,1" newline rbitfld.long 0x0 2. "OTGINT,OTG interrupt" "0,1" newline bitfld.long 0x0 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x0 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode" line.long 0x4 "OTG_GINTMSK,OTG interrupt mask register [alternate]" bitfld.long 0x4 31. "WUIM,Resume/remote wake-up detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 29. "DISCINT,Disconnect detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 26. "PTXFEM,Periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 25. "HCIM,Host channels interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline rbitfld.long 0x4 24. "PRTIM,Host port interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 21. "IPXFRM,Incomplete periodic transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 5. "NPTXFEM,Non-periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" group.long 0x18++0x3 line.long 0x0 "OTG_GINTMSK_ALTERNATE,OTG interrupt mask register [alternate]" bitfld.long 0x0 31. "WUIM,Resume/remote wake-up detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 23. "RSTDETM,Reset detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 22. "FSUSPM,Data fetch suspended mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 21. "IISOOXFRM,Incomplete isochronous OUT transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 20. "IISOIXFRM,Incomplete isochronous IN transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 19. "OEPINT,OUT endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 18. "IEPINT,IN endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 15. "EOPFM,End of periodic frame interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 14. "ISOODRPM,Isochronous OUT packet dropped interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 13. "ENUMDNEM,Enumeration done mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 12. "USBRST,USB reset mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 11. "USBSUSPM,USB suspend mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 10. "ESUSPM,Early suspend mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 7. "GONAKEFFM,Global OUT NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 6. "GINAKEFFM,Global non-periodic IN NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" rgroup.long 0x1C++0x3 line.long 0x0 "OTG_GRXSTSR,OTG receive status debug read register [alternate]" bitfld.long 0x0 27. "STSPHST,Status phase start" "0,1" newline hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_GRXSTSR_ALTERNATE,OTG receive status debug read register [alternate]" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_GRXSTSP,OTG status read and pop registers" bitfld.long 0x4 27. "STSPHST,Status phase start" "0,1" newline hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x4 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" rgroup.long 0x20++0x3 line.long 0x0 "OTG_GRXSTSP_ALTERNATE,OTG status read and pop registers" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_GRXFSIZ,OTG receive FIFO size register" hexmask.long.word 0x0 0.--15. 1. "RXFD,Rx FIFO depth" line.long 0x4 "OTG_HNPTXFSIZ,OTG host non-periodic transmit FIFO size register [alternate]" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Non-periodic Tx FIFO depth" newline hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Non-periodic transmit RAM start address" group.long 0x28++0x3 line.long 0x0 "OTG_HNPTXFSIZ_ALTERNATE,OTG host non-periodic transmit FIFO size register [alternate]" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 Tx FIFO depth" newline hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start address" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HNPTXSTS,OTG non-periodic transmit FIFO/queue status register" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the non-periodic transmit request queue" newline hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Non-periodic transmit request queue space available" newline hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Non-periodic Tx FIFO space available" group.long 0x38++0x7 line.long 0x0 "OTG_GCCFG,OTG general core configuration register" bitfld.long 0x0 28. "IDPULLUPDIS,Disable ID pin pull-up" "0: Enables ID pin pull-up,1: Disable ID pin pull-up" newline bitfld.long 0x0 26. "BCDEN,Force Battery charging (BC) mode" "0: Normal USB mode,1: Battery Charging mode" newline bitfld.long 0x0 25. "FORCEHOSTPD,Force host mode pull-downs" "0: Do not force host mode pull-downs,1: Force host mode pull-downs" newline bitfld.long 0x0 23. "VBVALOVAL,Software override value of the VBUS B-session detection" "0: B-session inactive,1: B-session active" newline bitfld.long 0x0 22. "SDEN,Secondary detection enable" "0: Secondary detection disabled,1: Secondary detection enabled" newline bitfld.long 0x0 20. "PDEN,Primary detection enable" "0: Primary detection disabled,1: Primary detection enabled" newline bitfld.long 0x0 19. "DCDEN,Data Contact Detection enable" "0: Data Contact Detection disabled,1: Data Contact Detection enabled" newline bitfld.long 0x0 18. "HVDMSRCEN,Host CDP port Voltage source enable on DM" "0: DM voltage source disabled,1: DM Voltage source enabled" newline bitfld.long 0x0 17. "HCDPDETEN,Host CDP port voltage detector enable on DP" "0: DP voltage detection disabled,1: DP voltage detection enabled" newline bitfld.long 0x0 16. "HCDPEN,Host CDP behavior enable" "0: Disable CDP behavior,1: Enable CDP behavior" newline rbitfld.long 0x0 4. "VBUSVLD,VBUS valid indicator" "0: VBUS is below VBUS valid threshold,1: VBUS is above VBUS valid threshold" newline rbitfld.long 0x0 3. "SESSVLD,VBUS session indicator" "0: VBUS is below VBUS session threshold,1: VBUS is above VBUS session threshold" newline rbitfld.long 0x0 2. "FSVMINUS,Single-Ended DM indicator" "0: DM voltage at low level,1: DM voltage at high level" newline rbitfld.long 0x0 1. "FSVPLUS,Single-Ended DP indicator" "0: DM voltage at low level,1: DM voltage at high level" newline rbitfld.long 0x0 0. "CHGDET,Charger detection result of the current mode (primary or secondary)." "0: Low value on pin,1: High value on pin" line.long 0x4 "OTG_CID,OTG core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x54++0x3 line.long 0x0 "OTG_GLPMCFG,OTG core LPM configuration register" bitfld.long 0x0 28. "ENBESL,Enable best effort service latency" "0: The core works as described in the following..,1: The core works as described in the LPM Errata:" newline rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" newline bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep state resume OK" "0: The application or host cannot start resume from..,1: The application or host can start resume from.." newline rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0: Core not in L1,1: Core in L1" newline rbitfld.long 0x0 13.--14. "LPMRSP,LPM response" "0: ERROR (No handshake response),1: STALL,2: NYET,3: ACK" newline bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" newline bitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service latency" newline bitfld.long 0x0 1. "LPMACK,LPM token acknowledge enable" "0: NYET,1: ACK" newline bitfld.long 0x0 0. "LPMEN,LPM support enable" "0: LPM capability is not enabled,1: LPM capability is enabled" group.long 0x100++0x23 line.long 0x0 "OTG_HPTXFSIZ,OTG host periodic transmit FIFO size register" hexmask.long.word 0x0 16.--31. 1. "PTXFSIZ,Host periodic Tx FIFO depth" newline hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic Tx FIFO start address" line.long 0x4 "OTG_DIEPTXF1,OTG device IN endpoint transmit FIFO 1 size register" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x8 "OTG_DIEPTXF2,OTG device IN endpoint transmit FIFO 2 size register" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0xC "OTG_DIEPTXF3,OTG device IN endpoint transmit FIFO 3 size register" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x10 "OTG_DIEPTXF4,OTG device IN endpoint transmit FIFO 4 size register" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x14 "OTG_DIEPTXF5,OTG device IN endpoint transmit FIFO 5 size register" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x18 "OTG_DIEPTXF6,OTG device IN endpoint transmit FIFO 6 size register" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x1C "OTG_DIEPTXF7,OTG device IN endpoint transmit FIFO 7 size register" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x20 "OTG_DIEPTXF8,OTG device IN endpoint transmit FIFO 8 size register" hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" group.long 0x400++0x7 line.long 0x0 "OTG_HCFG,OTG host configuration register" rbitfld.long 0x0 2. "FSLSS,FS- and LS-only support" "0,1" newline bitfld.long 0x0 0.--1. "FSLSPCS,FS/LS PHY clock select" "?,1: PHY clock is running at 48 MHz,2: Select 6 MHz PHY clock frequency,?" line.long 0x4 "OTG_HFIR,OTG host frame interval register" bitfld.long 0x4 16. "RLDCTRL,Reload control" "0: The HFIR cannot be reloaded dynamically,1: The HFIR can be dynamically reloaded during run.." newline hexmask.long.word 0x4 0.--15. 1. "FRIVL,Frame interval" rgroup.long 0x408++0x3 line.long 0x0 "OTG_HFNUM,OTG host frame number/frame time remaining register" hexmask.long.word 0x0 16.--31. 1. "FTREM,Frame time remaining" newline hexmask.long.word 0x0 0.--15. 1. "FRNUM,Frame number" rgroup.long 0x410++0x7 line.long 0x0 "OTG_HPTXSTS,OTG_Host periodic transmit FIFO/queue status register" hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,Top of the periodic transmit request queue" newline hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,Periodic transmit request queue space available" newline hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,Periodic transmit data FIFO space available" line.long 0x4 "OTG_HAINT,OTG host all channels interrupt register" hexmask.long.word 0x4 0.--15. 1. "HAINT,Channel interrupts" group.long 0x418++0x3 line.long 0x0 "OTG_HAINTMSK,OTG host all channels interrupt mask register" hexmask.long.word 0x0 0.--15. 1. "HAINTM,Channel interrupt mask" group.long 0x440++0x3 line.long 0x0 "OTG_HPRT,OTG host port control and status register" rbitfld.long 0x0 17.--18. "PSPD,Port speed" "0: High speed,1: Full speed,2: Low speed,?" newline hexmask.long.byte 0x0 13.--16. 1. "PTCTL,Port test control" newline bitfld.long 0x0 12. "PPWR,Port power" "0: Power off,1: Power on" newline rbitfld.long 0x0 10.--11. "PLSTS,Port line status" "0,1,2,3" newline bitfld.long 0x0 8. "PRST,Port reset" "0: Port not in reset,1: Port in reset" newline bitfld.long 0x0 7. "PSUSP,Port suspend" "0: Port not in suspend mode,1: Port in suspend mode" newline bitfld.long 0x0 6. "PRES,Port resume" "0: No resume driven,1: Resume driven" newline bitfld.long 0x0 5. "POCCHNG,Port overcurrent change" "0,1" newline rbitfld.long 0x0 4. "POCA,Port overcurrent active" "0: No overcurrent condition,1: Overcurrent condition" newline bitfld.long 0x0 3. "PENCHNG,Port enable/disable change" "0,1" newline bitfld.long 0x0 2. "PENA,Port enable" "0: Port disabled,1: Port enabled" newline bitfld.long 0x0 1. "PCDET,Port connect detected" "0,1" newline rbitfld.long 0x0 0. "PCSTS,Port connect status" "0: No device is attached to the port,1: A device is attached to the port" group.long 0x500++0x17 line.long 0x0 "OTG_HCCHAR0,OTG host channel 0 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT0,OTG host channel 0 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT0,OTG host channel 0 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK0,OTG host channel 0 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ0,OTG host channel 0 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA0,OTG host channel 0 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x520++0x17 line.long 0x0 "OTG_HCCHAR1,OTG host channel 1 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT1,OTG host channel 1 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT1,OTG host channel 1 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK1,OTG host channel 1 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ1,OTG host channel 1 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA1,OTG host channel 1 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x540++0x17 line.long 0x0 "OTG_HCCHAR2,OTG host channel 2 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT2,OTG host channel 2 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT2,OTG host channel 2 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK2,OTG host channel 2 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ2,OTG host channel 2 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA2,OTG host channel 2 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x560++0x17 line.long 0x0 "OTG_HCCHAR3,OTG host channel 3 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT3,OTG host channel 3 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT3,OTG host channel 3 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK3,OTG host channel 3 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ3,OTG host channel 3 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA3,OTG host channel 3 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x580++0x17 line.long 0x0 "OTG_HCCHAR4,OTG host channel 4 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT4,OTG host channel 4 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT4,OTG host channel 4 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK4,OTG host channel 4 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ4,OTG host channel 4 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA4,OTG host channel 4 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5A0++0x17 line.long 0x0 "OTG_HCCHAR5,OTG host channel 5 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT5,OTG host channel 5 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT5,OTG host channel 5 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK5,OTG host channel 5 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ5,OTG host channel 5 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA5,OTG host channel 5 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5C0++0x17 line.long 0x0 "OTG_HCCHAR6,OTG host channel 6 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT6,OTG host channel 6 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT6,OTG host channel 6 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK6,OTG host channel 6 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ6,OTG host channel 6 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA6,OTG host channel 6 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5E0++0x17 line.long 0x0 "OTG_HCCHAR7,OTG host channel 7 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT7,OTG host channel 7 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT7,OTG host channel 7 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK7,OTG host channel 7 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ7,OTG host channel 7 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA7,OTG host channel 7 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x600++0x17 line.long 0x0 "OTG_HCCHAR8,OTG host channel 8 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT8,OTG host channel 8 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT8,OTG host channel 8 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK8,OTG host channel 8 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ8,OTG host channel 8 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA8,OTG host channel 8 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x620++0x17 line.long 0x0 "OTG_HCCHAR9,OTG host channel 9 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT9,OTG host channel 9 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT9,OTG host channel 9 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK9,OTG host channel 9 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ9,OTG host channel 9 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA9,OTG host channel 9 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x640++0x17 line.long 0x0 "OTG_HCCHAR10,OTG host channel 10 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT10,OTG host channel 10 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT10,OTG host channel 10 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK10,OTG host channel 10 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ10,OTG host channel 10 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA10,OTG host channel 10 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x660++0x17 line.long 0x0 "OTG_HCCHAR11,OTG host channel 11 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT11,OTG host channel 11 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT11,OTG host channel 11 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK11,OTG host channel 11 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ11,OTG host channel 11 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA11,OTG host channel 11 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x680++0x17 line.long 0x0 "OTG_HCCHAR12,OTG host channel 12 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT12,OTG host channel 12 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT12,OTG host channel 12 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK12,OTG host channel 12 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ12,OTG host channel 12 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA12,OTG host channel 12 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6A0++0x17 line.long 0x0 "OTG_HCCHAR13,OTG host channel 13 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT13,OTG host channel 13 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT13,OTG host channel 13 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK13,OTG host channel 13 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ13,OTG host channel 13 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA13,OTG host channel 13 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6C0++0x17 line.long 0x0 "OTG_HCCHAR14,OTG host channel 14 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT14,OTG host channel 14 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT14,OTG host channel 14 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK14,OTG host channel 14 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ14,OTG host channel 14 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA14,OTG host channel 14 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6E0++0x17 line.long 0x0 "OTG_HCCHAR15,OTG host channel 15 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT15,OTG host channel 15 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT15,OTG host channel 15 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK15,OTG host channel 15 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ15,OTG host channel 15 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA15,OTG host channel 15 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x800++0x7 line.long 0x0 "OTG_DCFG,OTG device configuration register" bitfld.long 0x0 24.--25. "PERSCHIVL,Periodic schedule interval" "0: 25% of (micro)frame,1: 50% of (micro)frame,2: 75% of (micro)frame,?" newline bitfld.long 0x0 15. "ERRATIM,Erratic error interrupt mask" "0: Early suspend interrupt is generated on erratic..,1: Mask early suspend interrupt on erratic error" newline bitfld.long 0x0 11.--12. "PFIVL,Periodic frame interval" "0: 80% of the frame interval,1: 85% of the frame interval,2: 90% of the frame interval,3: 95% of the frame interval" newline hexmask.long.byte 0x0 4.--10. 1. "DAD,Device address" newline bitfld.long 0x0 2. "NZLSOHSK,Non-zero-length status OUT handshake" "0: Send the received OUT packet to the application..,1: Send a STALL handshake on a nonzero-length.." newline bitfld.long 0x0 0.--1. "DSPD,Device speed" "0: High speed,1: Full speed,?,?" line.long 0x4 "OTG_DCTL,OTG device control register" bitfld.long 0x4 18. "DSBESLRJCT,Deep sleep BESL reject" "0,1" newline bitfld.long 0x4 11. "POPRGDNE,Power-on programming done" "0,1" newline bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1" newline bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1" newline bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1" newline bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1" newline bitfld.long 0x4 4.--6. "TCTL,Test control" "0: Test mode disabled,1: Test_J mode,2: Test_K mode,3: Test_SE0_NAK mode,4: Test_Packet mode,5: Test_Force_Enable,?,?" newline rbitfld.long 0x4 3. "GONSTS,Global OUT NAK status" "0: A handshake is sent based on the FIFO status and..,1: No data is written to the Rx FIFO irrespective.." newline rbitfld.long 0x4 2. "GINSTS,Global IN NAK status" "0: A handshake is sent out based on the data..,1: A NAK handshake is sent out on all non-periodic.." newline bitfld.long 0x4 1. "SDIS,Soft disconnect" "0: Normal operation. When this bit is cleared after..,1: The core generates a device disconnect event to.." newline bitfld.long 0x4 0. "RWUSIG,Remote wake-up signaling" "0,1" rgroup.long 0x808++0x3 line.long 0x0 "OTG_DSTS,OTG device status register" bitfld.long 0x0 22.--23. "DEVLNSTS,Device line status" "0,1,2,3" newline hexmask.long.word 0x0 8.--21. 1. "FNSOF,Frame number of the received SOF" newline bitfld.long 0x0 3. "EERR,Erratic error" "0,1" newline bitfld.long 0x0 1.--2. "ENUMSPD,Enumerated speed" "0: High Speed,1: Full Speed,?,?" newline bitfld.long 0x0 0. "SUSPSTS,Suspend status" "0,1" group.long 0x810++0x7 line.long 0x0 "OTG_DIEPMSK,OTG device IN endpoint common interrupt mask register" bitfld.long 0x0 13. "NAKM,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 8. "TXFURM,FIFO underrun mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 6. "INEPNEM,IN endpoint NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 5. "INEPNMM,IN token received with EP mismatch mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 4. "ITTXFEMSK,IN token received when Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 3. "TOM,Timeout condition mask (Non-isochronous endpoints)" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x4 "OTG_DOEPMSK,OTG device OUT endpoint common interrupt mask register" bitfld.long 0x4 14. "NYETMSK,NYET interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 13. "NAKMSK,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 12. "BERRM,Babble error interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 8. "OUTPKTERRM,Out packet error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 6. "B2BSTUPM,Back-to-back SETUP packets received mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 5. "STSPHSRXM,Status phase received for control write mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 4. "OTEPDM,OUT token received when endpoint disabled mask. Applies to control OUT endpoints only." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 3. "STUPM,STUPM: SETUP phase done mask. Applies to control endpoints only." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" rgroup.long 0x818++0x3 line.long 0x0 "OTG_DAINT,OTG device all endpoints interrupt register" hexmask.long.word 0x0 16.--31. 1. "OEPINT,OUT endpoint interrupt bits" newline hexmask.long.word 0x0 0.--15. 1. "IEPINT,IN endpoint interrupt bits" group.long 0x81C++0x3 line.long 0x0 "OTG_DAINTMSK,OTG all endpoints interrupt mask register" hexmask.long.word 0x0 16.--31. 1. "OEPM,OUT EP interrupt mask bits" newline hexmask.long.word 0x0 0.--15. 1. "IEPM,IN EP interrupt mask bits" group.long 0x830++0x7 line.long 0x0 "OTG_DTHRCTL,OTG device threshold control register" bitfld.long 0x0 27. "ARPEN,Arbiter parking enable" "0,1" newline hexmask.long.word 0x0 17.--25. 1. "RXTHRLEN,Receive threshold length" newline bitfld.long 0x0 16. "RXTHREN,Receive threshold enable" "0,1" newline hexmask.long.word 0x0 2.--10. 1. "TXTHRLEN,Transmit threshold length" newline bitfld.long 0x0 1. "ISOTHREN,ISO IN endpoint threshold enable" "0,1" newline bitfld.long 0x0 0. "NONISOTHREN,Nonisochronous IN endpoints threshold enable" "0,1" line.long 0x4 "OTG_DIEPEMPMSK,OTG device IN endpoint FIFO empty interrupt mask register" hexmask.long.word 0x4 0.--15. 1. "INEPTXFEM,IN EP Tx FIFO empty interrupt mask bits" group.long 0x900++0x3 line.long 0x0 "OTG_DIEPCTL0,OTG device IN endpoint 0 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x900++0x3 line.long 0x0 "OTG_DIEPCTL0_ALTERNATE,OTG device IN endpoint 0 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x908++0x3 line.long 0x0 "OTG_DIEPINT0,OTG device IN endpoint 0 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x910++0x7 line.long 0x0 "OTG_DIEPTSIZ0,OTG device IN endpoint 0 transfer size register" bitfld.long 0x0 19.--20. "PKTCNT,Packet count" "0,1,2,3" newline hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA0,OTG device IN endpoint 0 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x918++0x3 line.long 0x0 "OTG_DTXFSTS0,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x920++0x3 line.long 0x0 "OTG_DIEPCTL1,OTG device IN endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x920++0x3 line.long 0x0 "OTG_DIEPCTL1_ALTERNATE,OTG device IN endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x928++0x3 line.long 0x0 "OTG_DIEPINT1,OTG device IN endpoint 1 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x930++0x7 line.long 0x0 "OTG_DIEPTSIZ1,OTG device IN endpoint 1 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA1,OTG device IN endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x938++0x3 line.long 0x0 "OTG_DTXFSTS1,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x940++0x3 line.long 0x0 "OTG_DIEPCTL2,OTG device IN endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x940++0x3 line.long 0x0 "OTG_DIEPCTL2_ALTERNATE,OTG device IN endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x948++0x3 line.long 0x0 "OTG_DIEPINT2,OTG device IN endpoint 2 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x950++0x7 line.long 0x0 "OTG_DIEPTSIZ2,OTG device IN endpoint 2 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA2,OTG device IN endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x958++0x3 line.long 0x0 "OTG_DTXFSTS2,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x960++0x3 line.long 0x0 "OTG_DIEPCTL3,OTG device IN endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x960++0x3 line.long 0x0 "OTG_DIEPCTL3_ALTERNATE,OTG device IN endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x968++0x3 line.long 0x0 "OTG_DIEPINT3,OTG device IN endpoint 3 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x970++0x7 line.long 0x0 "OTG_DIEPTSIZ3,OTG device IN endpoint 3 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA3,OTG device IN endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x978++0x3 line.long 0x0 "OTG_DTXFSTS3,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x980++0x3 line.long 0x0 "OTG_DIEPCTL4,OTG device IN endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x980++0x3 line.long 0x0 "OTG_DIEPCTL4_ALTERNATE,OTG device IN endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x988++0x3 line.long 0x0 "OTG_DIEPINT4,OTG device IN endpoint 4 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x990++0x7 line.long 0x0 "OTG_DIEPTSIZ4,OTG device IN endpoint 4 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA4,OTG device IN endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x998++0x3 line.long 0x0 "OTG_DTXFSTS4,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9A0++0x3 line.long 0x0 "OTG_DIEPCTL5,OTG device IN endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9A0++0x3 line.long 0x0 "OTG_DIEPCTL5_ALTERNATE,OTG device IN endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9A8++0x3 line.long 0x0 "OTG_DIEPINT5,OTG device IN endpoint 5 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9B0++0x7 line.long 0x0 "OTG_DIEPTSIZ5,OTG device IN endpoint 5 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA5,OTG device IN endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9B8++0x3 line.long 0x0 "OTG_DTXFSTS5,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9C0++0x3 line.long 0x0 "OTG_DIEPCTL6,OTG device IN endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9C0++0x3 line.long 0x0 "OTG_DIEPCTL6_ALTERNATE,OTG device IN endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9C8++0x3 line.long 0x0 "OTG_DIEPINT6,OTG device IN endpoint 6 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9D0++0x7 line.long 0x0 "OTG_DIEPTSIZ6,OTG device IN endpoint 6 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA6,OTG device IN endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9D8++0x3 line.long 0x0 "OTG_DTXFSTS6,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9E0++0x3 line.long 0x0 "OTG_DIEPCTL7,OTG device IN endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9E0++0x3 line.long 0x0 "OTG_DIEPCTL7_ALTERNATE,OTG device IN endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9E8++0x3 line.long 0x0 "OTG_DIEPINT7,OTG device IN endpoint 7 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9F0++0x7 line.long 0x0 "OTG_DIEPTSIZ7,OTG device IN endpoint 7 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA7,OTG device IN endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9F8++0x3 line.long 0x0 "OTG_DTXFSTS7,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0xA00++0x3 line.long 0x0 "OTG_DIEPCTL8,OTG device IN endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xA00++0x3 line.long 0x0 "OTG_DIEPCTL8_ALTERNATE,OTG device IN endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xA08++0x3 line.long 0x0 "OTG_DIEPINT8,OTG device IN endpoint 8 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xA10++0x7 line.long 0x0 "OTG_DIEPTSIZ8,OTG device IN endpoint 8 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA8,OTG device IN endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0xA18++0x3 line.long 0x0 "OTG_DTXFSTS8,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0xB00++0x3 line.long 0x0 "OTG_DOEPCTL0,OTG device control OUT endpoint 0 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline rbitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline rbitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline rbitfld.long 0x0 0.--1. "MPSIZ,Maximum packet size" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes" group.long 0xB08++0x3 line.long 0x0 "OTG_DOEPINT0,OTG device OUT endpoint 0 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB10++0x7 line.long 0x0 "OTG_DOEPTSIZ0,OTG device OUT endpoint 0 transfer size register" bitfld.long 0x0 29.--30. "STUPCNT,SETUP packet count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline bitfld.long 0x0 19. "PKTCNT,Packet count" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA0,OTG device OUT endpoint 0 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB20++0x3 line.long 0x0 "OTG_DOEPCTL1,OTG device OUT endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB20++0x3 line.long 0x0 "OTG_DOEPCTL1_ALTERNATE,OTG device OUT endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB28++0x3 line.long 0x0 "OTG_DOEPINT1,OTG device OUT endpoint 1 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB30++0x7 line.long 0x0 "OTG_DOEPTSIZ1,OTG device OUT endpoint 1 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA1,OTG device OUT endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB40++0x3 line.long 0x0 "OTG_DOEPCTL2,OTG device OUT endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB40++0x3 line.long 0x0 "OTG_DOEPCTL2_ALTERNATE,OTG device OUT endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB48++0x3 line.long 0x0 "OTG_DOEPINT2,OTG device OUT endpoint 2 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB50++0x7 line.long 0x0 "OTG_DOEPTSIZ2,OTG device OUT endpoint 2 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA2,OTG device OUT endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB60++0x3 line.long 0x0 "OTG_DOEPCTL3,OTG device OUT endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB60++0x3 line.long 0x0 "OTG_DOEPCTL3_ALTERNATE,OTG device OUT endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB68++0x3 line.long 0x0 "OTG_DOEPINT3,OTG device OUT endpoint 3 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB70++0x7 line.long 0x0 "OTG_DOEPTSIZ3,OTG device OUT endpoint 3 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA3,OTG device OUT endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB80++0x3 line.long 0x0 "OTG_DOEPCTL4,OTG device OUT endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB80++0x3 line.long 0x0 "OTG_DOEPCTL4_ALTERNATE,OTG device OUT endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB88++0x3 line.long 0x0 "OTG_DOEPINT4,OTG device OUT endpoint 4 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB90++0x7 line.long 0x0 "OTG_DOEPTSIZ4,OTG device OUT endpoint 4 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA4,OTG device OUT endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBA0++0x3 line.long 0x0 "OTG_DOEPCTL5,OTG device OUT endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBA0++0x3 line.long 0x0 "OTG_DOEPCTL5_ALTERNATE,OTG device OUT endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBA8++0x3 line.long 0x0 "OTG_DOEPINT5,OTG device OUT endpoint 5 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBB0++0x7 line.long 0x0 "OTG_DOEPTSIZ5,OTG device OUT endpoint 5 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA5,OTG device OUT endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBC0++0x3 line.long 0x0 "OTG_DOEPCTL6,OTG device OUT endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBC0++0x3 line.long 0x0 "OTG_DOEPCTL6_ALTERNATE,OTG device OUT endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBC8++0x3 line.long 0x0 "OTG_DOEPINT6,OTG device OUT endpoint 6 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBD0++0x7 line.long 0x0 "OTG_DOEPTSIZ6,OTG device OUT endpoint 6 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA6,OTG device OUT endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBE0++0x3 line.long 0x0 "OTG_DOEPCTL7,OTG device OUT endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBE0++0x3 line.long 0x0 "OTG_DOEPCTL7_ALTERNATE,OTG device OUT endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBE8++0x3 line.long 0x0 "OTG_DOEPINT7,OTG device OUT endpoint 7 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBF0++0x7 line.long 0x0 "OTG_DOEPTSIZ7,OTG device OUT endpoint 7 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA7,OTG device OUT endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xC00++0x3 line.long 0x0 "OTG_DOEPCTL8,OTG device OUT endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xC00++0x3 line.long 0x0 "OTG_DOEPCTL8_ALTERNATE,OTG device OUT endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xC08++0x3 line.long 0x0 "OTG_DOEPINT8,OTG device OUT endpoint 8 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xC10++0x7 line.long 0x0 "OTG_DOEPTSIZ8,OTG device OUT endpoint 8 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA8,OTG device OUT endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xE00++0x7 line.long 0x0 "OTG_PCGCCTL,OTG power and clock gating control register" rbitfld.long 0x0 7. "SUSP,Deep Sleep" "0,1" newline rbitfld.long 0x0 6. "PHYSLEEP,PHY in Sleep" "0,1" newline bitfld.long 0x0 5. "ENL1GTG,Enable sleep clock gating" "0,1" newline rbitfld.long 0x0 4. "PHYSUSP,PHY suspended" "0,1" newline bitfld.long 0x0 1. "GATEHCLK,Gate HCLK" "0,1" newline bitfld.long 0x0 0. "STPPCLK,Stop PHY clock" "0,1" line.long 0x4 "OTG_PCGCCTL1,OTG power and clock gating control register 1" bitfld.long 0x4 3. "RAMGATEEN,Enable RAM clock gating" "0,1" newline bitfld.long 0x4 1.--2. "CNTGATECLK,Counter for clock gating" "0: 64 clocks,1: 128 clocks,?,?" newline bitfld.long 0x4 0. "GATEEN,Enable active clock gating" "0,1" tree.end tree "OTG2_S" base ad:0x58080000 group.long 0x0++0x17 line.long 0x0 "OTG_GOTGCTL,OTG control and status register" rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0: Device mode,1: Host mode" newline bitfld.long 0x0 20. "OTGVER,OTG version" "0: OTG Version 1.3. OTG1.3 is obsolete for new..,1: OTG Version 2.0. In this version the core.." newline rbitfld.long 0x0 19. "BSVLD,B-session valid" "0: B-session is not valid.,1: B-session is valid." newline rbitfld.long 0x0 18. "ASVLD,A-session valid" "0: A-session is not valid,1: A-session is valid" newline rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0: Long debounce time used for physical connections..,1: Short debounce time used for soft connections.." newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0: The OTG controller is in A-device mode,1: The OTG controller is in B-device mode" newline bitfld.long 0x0 12. "EHEN,Embedded host enable" "0: OTG A device state machine is selected,1: Embedded host state machine is selected" newline bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value." "0: Bvalid value is '0' when BVALOEN = 1,1: Bvalid value is '1' when BVALOEN = 1" newline bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0: Override is disabled and Bvalid signal from the..,?" newline bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value." "0: Avalid value is '0' when AVALOEN = 1,1: Avalid value is '1' when AVALOEN = 1" newline bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable." "0: Override is disabled and Avalid signal from the..,1: Internally Avalid received from the PHY is.." newline bitfld.long 0x0 3. "VBVALOVAL,V less than sub>BUS less than /sub> valid override value." "0: vbusvalid value is '0' when VBVALOEN = 1,1: vbusvalid value is '1' when VBVALOEN = 1" newline bitfld.long 0x0 2. "VBVALOEN,V less than sub>BUS less than /sub> valid override enable." "0: Override is disabled and vbusvalid signal from..,1: Internally vbusvalid received from the PHY is.." line.long 0x4 "OTG_GOTGINT,OTG interrupt register" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" newline bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_GAHBCFG,OTG AHB configuration register" bitfld.long 0x8 8. "PTXFELVL,Periodic Tx FIFO empty level" "0: PTXFE (in OTG_GINTSTS) interrupt indicates that..,1: PTXFE (in OTG_GINTSTS) interrupt indicates that.." newline bitfld.long 0x8 7. "TXFELVL,Tx FIFO empty level" "0: The TXFE (in OTG_DIEPINTx) interrupt indicates..,1: The TXFE (in OTG_DIEPINTx) interrupt indicates.." newline bitfld.long 0x8 5. "DMAEN,DMA enabled" "0: The core operates in slave mode,1: The core operates in DMA mode" newline hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" newline bitfld.long 0x8 0. "GINTMSK,Global interrupt mask" "0: Mask the interrupt assertion to the application.,1: Unmask the interrupt assertion to the application." line.long 0xC "OTG_GUSBCFG,OTG USB configuration register" bitfld.long 0xC 30. "FDMOD,Force device mode" "0: Normal mode,1: Force device mode" newline bitfld.long 0xC 29. "FHMOD,Force host mode" "0: Normal mode,1: Force host mode" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing selection" "0: Data line pulsing using utmi_txvalid (default),1: Data line pulsing using utmi_termsel" newline bitfld.long 0xC 15. "PHYLPC,PHY Low-power clock select" "0: 480 MHz internal PLL clock,1: 48 MHz external clock" newline hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" newline bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_GRSTCTL,OTG reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" newline rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled" "0,1" newline hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x10 5. "TXFFLSH,Tx FIFO flush" "0,1" newline bitfld.long 0x10 4. "RXFFLSH,Rx FIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" newline bitfld.long 0x10 1. "PSRST,Partial soft reset" "0,1" newline bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_GINTSTS,OTG core interrupt register [alternate]" bitfld.long 0x14 31. "WKUPINT,Resume/remote wake-up detected interrupt" "0,1" newline bitfld.long 0x14 30. "SRQINT,Session request/new session detected interrupt" "0,1" newline bitfld.long 0x14 29. "DISCINT,Disconnect detected interrupt" "0,1" newline bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" newline bitfld.long 0x14 27. "LPMINT,LPM interrupt" "0,1" newline rbitfld.long 0x14 26. "PTXFE,Periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" newline rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" newline bitfld.long 0x14 23. "RSTDET,Reset detected interrupt" "0,1" newline bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" newline bitfld.long 0x14 21. "IPXFR,Incomplete periodic transfer" "0,1" newline bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" newline rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" newline bitfld.long 0x14 15. "EOPF,End of periodic frame interrupt" "0,1" newline bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1" newline bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" newline bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" newline bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" newline rbitfld.long 0x14 7. "GONAKEFF,Global OUT NAK effective" "0,1" newline rbitfld.long 0x14 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 4. "RXFLVL,Rx FIFO non-empty" "0,1" newline bitfld.long 0x14 3. "SOF,Start of frame" "0,1" newline rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" newline bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode" group.long 0x14++0x7 line.long 0x0 "OTG_GINTSTS_ALTERNATE,OTG core interrupt register [alternate]" bitfld.long 0x0 31. "WKUPINT,Resume/remote wake-up detected interrupt" "0,1" newline bitfld.long 0x0 30. "SRQINT,Session request/new session detected interrupt" "0,1" newline bitfld.long 0x0 29. "DISCINT,Disconnect detected interrupt" "0,1" newline bitfld.long 0x0 28. "CIDSCHG,Connector ID status change" "0,1" newline bitfld.long 0x0 27. "LPMINT,LPM interrupt" "0,1" newline rbitfld.long 0x0 26. "PTXFE,Periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x0 25. "HCINT,Host channels interrupt" "0,1" newline rbitfld.long 0x0 24. "HPRTINT,Host port interrupt" "0,1" newline bitfld.long 0x0 23. "RSTDET,Reset detected interrupt" "0,1" newline bitfld.long 0x0 22. "DATAFSUSP,Data fetch suspended" "0,1" newline bitfld.long 0x0 21. "INCOMPISOOUT,Incomplete isochronous OUT transfer" "0,1" newline bitfld.long 0x0 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1" newline rbitfld.long 0x0 19. "OEPINT,OUT endpoint interrupt" "0,1" newline rbitfld.long 0x0 18. "IEPINT,IN endpoint interrupt" "0,1" newline bitfld.long 0x0 15. "EOPF,End of periodic frame interrupt" "0,1" newline bitfld.long 0x0 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1" newline bitfld.long 0x0 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x0 12. "USBRST,USB reset" "0,1" newline bitfld.long 0x0 11. "USBSUSP,USB suspend" "0,1" newline bitfld.long 0x0 10. "ESUSP,Early suspend" "0,1" newline rbitfld.long 0x0 7. "GONAKEFF,Global OUT NAK effective" "0,1" newline rbitfld.long 0x0 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1" newline rbitfld.long 0x0 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x0 4. "RXFLVL,Rx FIFO non-empty" "0,1" newline bitfld.long 0x0 3. "SOF,Start of frame" "0,1" newline rbitfld.long 0x0 2. "OTGINT,OTG interrupt" "0,1" newline bitfld.long 0x0 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x0 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode" line.long 0x4 "OTG_GINTMSK,OTG interrupt mask register [alternate]" bitfld.long 0x4 31. "WUIM,Resume/remote wake-up detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 29. "DISCINT,Disconnect detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 26. "PTXFEM,Periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 25. "HCIM,Host channels interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline rbitfld.long 0x4 24. "PRTIM,Host port interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 21. "IPXFRM,Incomplete periodic transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 5. "NPTXFEM,Non-periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" group.long 0x18++0x3 line.long 0x0 "OTG_GINTMSK_ALTERNATE,OTG interrupt mask register [alternate]" bitfld.long 0x0 31. "WUIM,Resume/remote wake-up detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 23. "RSTDETM,Reset detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 22. "FSUSPM,Data fetch suspended mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 21. "IISOOXFRM,Incomplete isochronous OUT transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 20. "IISOIXFRM,Incomplete isochronous IN transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 19. "OEPINT,OUT endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 18. "IEPINT,IN endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 15. "EOPFM,End of periodic frame interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 14. "ISOODRPM,Isochronous OUT packet dropped interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 13. "ENUMDNEM,Enumeration done mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 12. "USBRST,USB reset mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 11. "USBSUSPM,USB suspend mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 10. "ESUSPM,Early suspend mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 7. "GONAKEFFM,Global OUT NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 6. "GINAKEFFM,Global non-periodic IN NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" rgroup.long 0x1C++0x3 line.long 0x0 "OTG_GRXSTSR,OTG receive status debug read register [alternate]" bitfld.long 0x0 27. "STSPHST,Status phase start" "0,1" newline hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_GRXSTSR_ALTERNATE,OTG receive status debug read register [alternate]" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_GRXSTSP,OTG status read and pop registers" bitfld.long 0x4 27. "STSPHST,Status phase start" "0,1" newline hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x4 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" rgroup.long 0x20++0x3 line.long 0x0 "OTG_GRXSTSP_ALTERNATE,OTG status read and pop registers" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_GRXFSIZ,OTG receive FIFO size register" hexmask.long.word 0x0 0.--15. 1. "RXFD,Rx FIFO depth" line.long 0x4 "OTG_HNPTXFSIZ,OTG host non-periodic transmit FIFO size register [alternate]" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Non-periodic Tx FIFO depth" newline hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Non-periodic transmit RAM start address" group.long 0x28++0x3 line.long 0x0 "OTG_HNPTXFSIZ_ALTERNATE,OTG host non-periodic transmit FIFO size register [alternate]" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 Tx FIFO depth" newline hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start address" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HNPTXSTS,OTG non-periodic transmit FIFO/queue status register" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the non-periodic transmit request queue" newline hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Non-periodic transmit request queue space available" newline hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Non-periodic Tx FIFO space available" group.long 0x38++0x7 line.long 0x0 "OTG_GCCFG,OTG general core configuration register" bitfld.long 0x0 28. "IDPULLUPDIS,Disable ID pin pull-up" "0: Enables ID pin pull-up,1: Disable ID pin pull-up" newline bitfld.long 0x0 26. "BCDEN,Force Battery charging (BC) mode" "0: Normal USB mode,1: Battery Charging mode" newline bitfld.long 0x0 25. "FORCEHOSTPD,Force host mode pull-downs" "0: Do not force host mode pull-downs,1: Force host mode pull-downs" newline bitfld.long 0x0 23. "VBVALOVAL,Software override value of the VBUS B-session detection" "0: B-session inactive,1: B-session active" newline bitfld.long 0x0 22. "SDEN,Secondary detection enable" "0: Secondary detection disabled,1: Secondary detection enabled" newline bitfld.long 0x0 20. "PDEN,Primary detection enable" "0: Primary detection disabled,1: Primary detection enabled" newline bitfld.long 0x0 19. "DCDEN,Data Contact Detection enable" "0: Data Contact Detection disabled,1: Data Contact Detection enabled" newline bitfld.long 0x0 18. "HVDMSRCEN,Host CDP port Voltage source enable on DM" "0: DM voltage source disabled,1: DM Voltage source enabled" newline bitfld.long 0x0 17. "HCDPDETEN,Host CDP port voltage detector enable on DP" "0: DP voltage detection disabled,1: DP voltage detection enabled" newline bitfld.long 0x0 16. "HCDPEN,Host CDP behavior enable" "0: Disable CDP behavior,1: Enable CDP behavior" newline rbitfld.long 0x0 4. "VBUSVLD,VBUS valid indicator" "0: VBUS is below VBUS valid threshold,1: VBUS is above VBUS valid threshold" newline rbitfld.long 0x0 3. "SESSVLD,VBUS session indicator" "0: VBUS is below VBUS session threshold,1: VBUS is above VBUS session threshold" newline rbitfld.long 0x0 2. "FSVMINUS,Single-Ended DM indicator" "0: DM voltage at low level,1: DM voltage at high level" newline rbitfld.long 0x0 1. "FSVPLUS,Single-Ended DP indicator" "0: DM voltage at low level,1: DM voltage at high level" newline rbitfld.long 0x0 0. "CHGDET,Charger detection result of the current mode (primary or secondary)." "0: Low value on pin,1: High value on pin" line.long 0x4 "OTG_CID,OTG core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x54++0x3 line.long 0x0 "OTG_GLPMCFG,OTG core LPM configuration register" bitfld.long 0x0 28. "ENBESL,Enable best effort service latency" "0: The core works as described in the following..,1: The core works as described in the LPM Errata:" newline rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" newline bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep state resume OK" "0: The application or host cannot start resume from..,1: The application or host can start resume from.." newline rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0: Core not in L1,1: Core in L1" newline rbitfld.long 0x0 13.--14. "LPMRSP,LPM response" "0: ERROR (No handshake response),1: STALL,2: NYET,3: ACK" newline bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" newline bitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service latency" newline bitfld.long 0x0 1. "LPMACK,LPM token acknowledge enable" "0: NYET,1: ACK" newline bitfld.long 0x0 0. "LPMEN,LPM support enable" "0: LPM capability is not enabled,1: LPM capability is enabled" group.long 0x100++0x23 line.long 0x0 "OTG_HPTXFSIZ,OTG host periodic transmit FIFO size register" hexmask.long.word 0x0 16.--31. 1. "PTXFSIZ,Host periodic Tx FIFO depth" newline hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic Tx FIFO start address" line.long 0x4 "OTG_DIEPTXF1,OTG device IN endpoint transmit FIFO 1 size register" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x8 "OTG_DIEPTXF2,OTG device IN endpoint transmit FIFO 2 size register" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0xC "OTG_DIEPTXF3,OTG device IN endpoint transmit FIFO 3 size register" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x10 "OTG_DIEPTXF4,OTG device IN endpoint transmit FIFO 4 size register" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x14 "OTG_DIEPTXF5,OTG device IN endpoint transmit FIFO 5 size register" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x18 "OTG_DIEPTXF6,OTG device IN endpoint transmit FIFO 6 size register" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x1C "OTG_DIEPTXF7,OTG device IN endpoint transmit FIFO 7 size register" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x20 "OTG_DIEPTXF8,OTG device IN endpoint transmit FIFO 8 size register" hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" group.long 0x400++0x7 line.long 0x0 "OTG_HCFG,OTG host configuration register" rbitfld.long 0x0 2. "FSLSS,FS- and LS-only support" "0,1" newline bitfld.long 0x0 0.--1. "FSLSPCS,FS/LS PHY clock select" "?,1: PHY clock is running at 48 MHz,2: Select 6 MHz PHY clock frequency,?" line.long 0x4 "OTG_HFIR,OTG host frame interval register" bitfld.long 0x4 16. "RLDCTRL,Reload control" "0: The HFIR cannot be reloaded dynamically,1: The HFIR can be dynamically reloaded during run.." newline hexmask.long.word 0x4 0.--15. 1. "FRIVL,Frame interval" rgroup.long 0x408++0x3 line.long 0x0 "OTG_HFNUM,OTG host frame number/frame time remaining register" hexmask.long.word 0x0 16.--31. 1. "FTREM,Frame time remaining" newline hexmask.long.word 0x0 0.--15. 1. "FRNUM,Frame number" rgroup.long 0x410++0x7 line.long 0x0 "OTG_HPTXSTS,OTG_Host periodic transmit FIFO/queue status register" hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,Top of the periodic transmit request queue" newline hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,Periodic transmit request queue space available" newline hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,Periodic transmit data FIFO space available" line.long 0x4 "OTG_HAINT,OTG host all channels interrupt register" hexmask.long.word 0x4 0.--15. 1. "HAINT,Channel interrupts" group.long 0x418++0x3 line.long 0x0 "OTG_HAINTMSK,OTG host all channels interrupt mask register" hexmask.long.word 0x0 0.--15. 1. "HAINTM,Channel interrupt mask" group.long 0x440++0x3 line.long 0x0 "OTG_HPRT,OTG host port control and status register" rbitfld.long 0x0 17.--18. "PSPD,Port speed" "0: High speed,1: Full speed,2: Low speed,?" newline hexmask.long.byte 0x0 13.--16. 1. "PTCTL,Port test control" newline bitfld.long 0x0 12. "PPWR,Port power" "0: Power off,1: Power on" newline rbitfld.long 0x0 10.--11. "PLSTS,Port line status" "0,1,2,3" newline bitfld.long 0x0 8. "PRST,Port reset" "0: Port not in reset,1: Port in reset" newline bitfld.long 0x0 7. "PSUSP,Port suspend" "0: Port not in suspend mode,1: Port in suspend mode" newline bitfld.long 0x0 6. "PRES,Port resume" "0: No resume driven,1: Resume driven" newline bitfld.long 0x0 5. "POCCHNG,Port overcurrent change" "0,1" newline rbitfld.long 0x0 4. "POCA,Port overcurrent active" "0: No overcurrent condition,1: Overcurrent condition" newline bitfld.long 0x0 3. "PENCHNG,Port enable/disable change" "0,1" newline bitfld.long 0x0 2. "PENA,Port enable" "0: Port disabled,1: Port enabled" newline bitfld.long 0x0 1. "PCDET,Port connect detected" "0,1" newline rbitfld.long 0x0 0. "PCSTS,Port connect status" "0: No device is attached to the port,1: A device is attached to the port" group.long 0x500++0x17 line.long 0x0 "OTG_HCCHAR0,OTG host channel 0 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT0,OTG host channel 0 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT0,OTG host channel 0 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK0,OTG host channel 0 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ0,OTG host channel 0 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA0,OTG host channel 0 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x520++0x17 line.long 0x0 "OTG_HCCHAR1,OTG host channel 1 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT1,OTG host channel 1 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT1,OTG host channel 1 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK1,OTG host channel 1 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ1,OTG host channel 1 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA1,OTG host channel 1 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x540++0x17 line.long 0x0 "OTG_HCCHAR2,OTG host channel 2 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT2,OTG host channel 2 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT2,OTG host channel 2 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK2,OTG host channel 2 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ2,OTG host channel 2 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA2,OTG host channel 2 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x560++0x17 line.long 0x0 "OTG_HCCHAR3,OTG host channel 3 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT3,OTG host channel 3 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT3,OTG host channel 3 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK3,OTG host channel 3 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ3,OTG host channel 3 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA3,OTG host channel 3 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x580++0x17 line.long 0x0 "OTG_HCCHAR4,OTG host channel 4 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT4,OTG host channel 4 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT4,OTG host channel 4 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK4,OTG host channel 4 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ4,OTG host channel 4 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA4,OTG host channel 4 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5A0++0x17 line.long 0x0 "OTG_HCCHAR5,OTG host channel 5 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT5,OTG host channel 5 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT5,OTG host channel 5 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK5,OTG host channel 5 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ5,OTG host channel 5 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA5,OTG host channel 5 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5C0++0x17 line.long 0x0 "OTG_HCCHAR6,OTG host channel 6 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT6,OTG host channel 6 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT6,OTG host channel 6 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK6,OTG host channel 6 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ6,OTG host channel 6 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA6,OTG host channel 6 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x5E0++0x17 line.long 0x0 "OTG_HCCHAR7,OTG host channel 7 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT7,OTG host channel 7 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT7,OTG host channel 7 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK7,OTG host channel 7 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ7,OTG host channel 7 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA7,OTG host channel 7 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x600++0x17 line.long 0x0 "OTG_HCCHAR8,OTG host channel 8 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT8,OTG host channel 8 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT8,OTG host channel 8 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK8,OTG host channel 8 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ8,OTG host channel 8 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA8,OTG host channel 8 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x620++0x17 line.long 0x0 "OTG_HCCHAR9,OTG host channel 9 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT9,OTG host channel 9 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT9,OTG host channel 9 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK9,OTG host channel 9 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ9,OTG host channel 9 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA9,OTG host channel 9 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x640++0x17 line.long 0x0 "OTG_HCCHAR10,OTG host channel 10 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT10,OTG host channel 10 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT10,OTG host channel 10 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK10,OTG host channel 10 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ10,OTG host channel 10 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA10,OTG host channel 10 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x660++0x17 line.long 0x0 "OTG_HCCHAR11,OTG host channel 11 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT11,OTG host channel 11 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT11,OTG host channel 11 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK11,OTG host channel 11 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ11,OTG host channel 11 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA11,OTG host channel 11 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x680++0x17 line.long 0x0 "OTG_HCCHAR12,OTG host channel 12 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT12,OTG host channel 12 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT12,OTG host channel 12 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK12,OTG host channel 12 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ12,OTG host channel 12 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA12,OTG host channel 12 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6A0++0x17 line.long 0x0 "OTG_HCCHAR13,OTG host channel 13 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT13,OTG host channel 13 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT13,OTG host channel 13 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK13,OTG host channel 13 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ13,OTG host channel 13 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA13,OTG host channel 13 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6C0++0x17 line.long 0x0 "OTG_HCCHAR14,OTG host channel 14 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT14,OTG host channel 14 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT14,OTG host channel 14 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK14,OTG host channel 14 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ14,OTG host channel 14 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA14,OTG host channel 14 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x6E0++0x17 line.long 0x0 "OTG_HCCHAR15,OTG host channel 15 characteristics register" bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled" newline bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" newline bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "?,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" newline hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT15,OTG host channel 15 split control register" bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" newline bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." newline hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" newline hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT15,OTG host channel 15 interrupt register" bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1" newline bitfld.long 0x8 8. "BBERR,Babble error." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error." "0,1" newline bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1" newline bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1" newline bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" newline bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK15,OTG host channel 15 interrupt mask register" bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x10 "OTG_HCTSIZ15,OTG host channel 15 transfer size register" bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" newline bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA15,OTG host channel 15 DMA address register" hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x800++0x7 line.long 0x0 "OTG_DCFG,OTG device configuration register" bitfld.long 0x0 24.--25. "PERSCHIVL,Periodic schedule interval" "0: 25% of (micro)frame,1: 50% of (micro)frame,2: 75% of (micro)frame,?" newline bitfld.long 0x0 15. "ERRATIM,Erratic error interrupt mask" "0: Early suspend interrupt is generated on erratic..,1: Mask early suspend interrupt on erratic error" newline bitfld.long 0x0 11.--12. "PFIVL,Periodic frame interval" "0: 80% of the frame interval,1: 85% of the frame interval,2: 90% of the frame interval,3: 95% of the frame interval" newline hexmask.long.byte 0x0 4.--10. 1. "DAD,Device address" newline bitfld.long 0x0 2. "NZLSOHSK,Non-zero-length status OUT handshake" "0: Send the received OUT packet to the application..,1: Send a STALL handshake on a nonzero-length.." newline bitfld.long 0x0 0.--1. "DSPD,Device speed" "0: High speed,1: Full speed,?,?" line.long 0x4 "OTG_DCTL,OTG device control register" bitfld.long 0x4 18. "DSBESLRJCT,Deep sleep BESL reject" "0,1" newline bitfld.long 0x4 11. "POPRGDNE,Power-on programming done" "0,1" newline bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1" newline bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1" newline bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1" newline bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1" newline bitfld.long 0x4 4.--6. "TCTL,Test control" "0: Test mode disabled,1: Test_J mode,2: Test_K mode,3: Test_SE0_NAK mode,4: Test_Packet mode,5: Test_Force_Enable,?,?" newline rbitfld.long 0x4 3. "GONSTS,Global OUT NAK status" "0: A handshake is sent based on the FIFO status and..,1: No data is written to the Rx FIFO irrespective.." newline rbitfld.long 0x4 2. "GINSTS,Global IN NAK status" "0: A handshake is sent out based on the data..,1: A NAK handshake is sent out on all non-periodic.." newline bitfld.long 0x4 1. "SDIS,Soft disconnect" "0: Normal operation. When this bit is cleared after..,1: The core generates a device disconnect event to.." newline bitfld.long 0x4 0. "RWUSIG,Remote wake-up signaling" "0,1" rgroup.long 0x808++0x3 line.long 0x0 "OTG_DSTS,OTG device status register" bitfld.long 0x0 22.--23. "DEVLNSTS,Device line status" "0,1,2,3" newline hexmask.long.word 0x0 8.--21. 1. "FNSOF,Frame number of the received SOF" newline bitfld.long 0x0 3. "EERR,Erratic error" "0,1" newline bitfld.long 0x0 1.--2. "ENUMSPD,Enumerated speed" "0: High Speed,1: Full Speed,?,?" newline bitfld.long 0x0 0. "SUSPSTS,Suspend status" "0,1" group.long 0x810++0x7 line.long 0x0 "OTG_DIEPMSK,OTG device IN endpoint common interrupt mask register" bitfld.long 0x0 13. "NAKM,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 8. "TXFURM,FIFO underrun mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 6. "INEPNEM,IN endpoint NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 5. "INEPNMM,IN token received with EP mismatch mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 4. "ITTXFEMSK,IN token received when Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 3. "TOM,Timeout condition mask (Non-isochronous endpoints)" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" line.long 0x4 "OTG_DOEPMSK,OTG device OUT endpoint common interrupt mask register" bitfld.long 0x4 14. "NYETMSK,NYET interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 13. "NAKMSK,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 12. "BERRM,Babble error interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 8. "OUTPKTERRM,Out packet error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 6. "B2BSTUPM,Back-to-back SETUP packets received mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 5. "STSPHSRXM,Status phase received for control write mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 4. "OTEPDM,OUT token received when endpoint disabled mask. Applies to control OUT endpoints only." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 3. "STUPM,STUPM: SETUP phase done mask. Applies to control endpoints only." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" rgroup.long 0x818++0x3 line.long 0x0 "OTG_DAINT,OTG device all endpoints interrupt register" hexmask.long.word 0x0 16.--31. 1. "OEPINT,OUT endpoint interrupt bits" newline hexmask.long.word 0x0 0.--15. 1. "IEPINT,IN endpoint interrupt bits" group.long 0x81C++0x3 line.long 0x0 "OTG_DAINTMSK,OTG all endpoints interrupt mask register" hexmask.long.word 0x0 16.--31. 1. "OEPM,OUT EP interrupt mask bits" newline hexmask.long.word 0x0 0.--15. 1. "IEPM,IN EP interrupt mask bits" group.long 0x830++0x7 line.long 0x0 "OTG_DTHRCTL,OTG device threshold control register" bitfld.long 0x0 27. "ARPEN,Arbiter parking enable" "0,1" newline hexmask.long.word 0x0 17.--25. 1. "RXTHRLEN,Receive threshold length" newline bitfld.long 0x0 16. "RXTHREN,Receive threshold enable" "0,1" newline hexmask.long.word 0x0 2.--10. 1. "TXTHRLEN,Transmit threshold length" newline bitfld.long 0x0 1. "ISOTHREN,ISO IN endpoint threshold enable" "0,1" newline bitfld.long 0x0 0. "NONISOTHREN,Nonisochronous IN endpoints threshold enable" "0,1" line.long 0x4 "OTG_DIEPEMPMSK,OTG device IN endpoint FIFO empty interrupt mask register" hexmask.long.word 0x4 0.--15. 1. "INEPTXFEM,IN EP Tx FIFO empty interrupt mask bits" group.long 0x900++0x3 line.long 0x0 "OTG_DIEPCTL0,OTG device IN endpoint 0 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x900++0x3 line.long 0x0 "OTG_DIEPCTL0_ALTERNATE,OTG device IN endpoint 0 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x908++0x3 line.long 0x0 "OTG_DIEPINT0,OTG device IN endpoint 0 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x910++0x7 line.long 0x0 "OTG_DIEPTSIZ0,OTG device IN endpoint 0 transfer size register" bitfld.long 0x0 19.--20. "PKTCNT,Packet count" "0,1,2,3" newline hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA0,OTG device IN endpoint 0 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x918++0x3 line.long 0x0 "OTG_DTXFSTS0,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x920++0x3 line.long 0x0 "OTG_DIEPCTL1,OTG device IN endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x920++0x3 line.long 0x0 "OTG_DIEPCTL1_ALTERNATE,OTG device IN endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x928++0x3 line.long 0x0 "OTG_DIEPINT1,OTG device IN endpoint 1 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x930++0x7 line.long 0x0 "OTG_DIEPTSIZ1,OTG device IN endpoint 1 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA1,OTG device IN endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x938++0x3 line.long 0x0 "OTG_DTXFSTS1,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x940++0x3 line.long 0x0 "OTG_DIEPCTL2,OTG device IN endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x940++0x3 line.long 0x0 "OTG_DIEPCTL2_ALTERNATE,OTG device IN endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x948++0x3 line.long 0x0 "OTG_DIEPINT2,OTG device IN endpoint 2 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x950++0x7 line.long 0x0 "OTG_DIEPTSIZ2,OTG device IN endpoint 2 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA2,OTG device IN endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x958++0x3 line.long 0x0 "OTG_DTXFSTS2,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x960++0x3 line.long 0x0 "OTG_DIEPCTL3,OTG device IN endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x960++0x3 line.long 0x0 "OTG_DIEPCTL3_ALTERNATE,OTG device IN endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x968++0x3 line.long 0x0 "OTG_DIEPINT3,OTG device IN endpoint 3 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x970++0x7 line.long 0x0 "OTG_DIEPTSIZ3,OTG device IN endpoint 3 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA3,OTG device IN endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x978++0x3 line.long 0x0 "OTG_DTXFSTS3,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x980++0x3 line.long 0x0 "OTG_DIEPCTL4,OTG device IN endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x980++0x3 line.long 0x0 "OTG_DIEPCTL4_ALTERNATE,OTG device IN endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x988++0x3 line.long 0x0 "OTG_DIEPINT4,OTG device IN endpoint 4 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x990++0x7 line.long 0x0 "OTG_DIEPTSIZ4,OTG device IN endpoint 4 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA4,OTG device IN endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x998++0x3 line.long 0x0 "OTG_DTXFSTS4,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9A0++0x3 line.long 0x0 "OTG_DIEPCTL5,OTG device IN endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9A0++0x3 line.long 0x0 "OTG_DIEPCTL5_ALTERNATE,OTG device IN endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9A8++0x3 line.long 0x0 "OTG_DIEPINT5,OTG device IN endpoint 5 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9B0++0x7 line.long 0x0 "OTG_DIEPTSIZ5,OTG device IN endpoint 5 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA5,OTG device IN endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9B8++0x3 line.long 0x0 "OTG_DTXFSTS5,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9C0++0x3 line.long 0x0 "OTG_DIEPCTL6,OTG device IN endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9C0++0x3 line.long 0x0 "OTG_DIEPCTL6_ALTERNATE,OTG device IN endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9C8++0x3 line.long 0x0 "OTG_DIEPINT6,OTG device IN endpoint 6 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9D0++0x7 line.long 0x0 "OTG_DIEPTSIZ6,OTG device IN endpoint 6 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA6,OTG device IN endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9D8++0x3 line.long 0x0 "OTG_DTXFSTS6,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0x9E0++0x3 line.long 0x0 "OTG_DIEPCTL7,OTG device IN endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9E0++0x3 line.long 0x0 "OTG_DIEPCTL7_ALTERNATE,OTG device IN endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9E8++0x3 line.long 0x0 "OTG_DIEPINT7,OTG device IN endpoint 7 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9F0++0x7 line.long 0x0 "OTG_DIEPTSIZ7,OTG device IN endpoint 7 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA7,OTG device IN endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0x9F8++0x3 line.long 0x0 "OTG_DTXFSTS7,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0xA00++0x3 line.long 0x0 "OTG_DIEPCTL8,OTG device IN endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xA00++0x3 line.long 0x0 "OTG_DIEPCTL8_ALTERNATE,OTG device IN endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xA08++0x3 line.long 0x0 "OTG_DIEPINT8,OTG device IN endpoint 8 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" newline bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" newline bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xA10++0x7 line.long 0x0 "OTG_DIEPTSIZ8,OTG device IN endpoint 8 transfer size register" bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA8,OTG device IN endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" rgroup.long 0xA18++0x3 line.long 0x0 "OTG_DTXFSTS8,OTG device IN endpoint transmit FIFO status register" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" group.long 0xB00++0x3 line.long 0x0 "OTG_DOEPCTL0,OTG device control OUT endpoint 0 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline rbitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline rbitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline rbitfld.long 0x0 0.--1. "MPSIZ,Maximum packet size" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes" group.long 0xB08++0x3 line.long 0x0 "OTG_DOEPINT0,OTG device OUT endpoint 0 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB10++0x7 line.long 0x0 "OTG_DOEPTSIZ0,OTG device OUT endpoint 0 transfer size register" bitfld.long 0x0 29.--30. "STUPCNT,SETUP packet count" "?,1: 1 packet,2: 2 packets,3: 3 packets" newline bitfld.long 0x0 19. "PKTCNT,Packet count" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA0,OTG device OUT endpoint 0 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB20++0x3 line.long 0x0 "OTG_DOEPCTL1,OTG device OUT endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB20++0x3 line.long 0x0 "OTG_DOEPCTL1_ALTERNATE,OTG device OUT endpoint 1 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB28++0x3 line.long 0x0 "OTG_DOEPINT1,OTG device OUT endpoint 1 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB30++0x7 line.long 0x0 "OTG_DOEPTSIZ1,OTG device OUT endpoint 1 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA1,OTG device OUT endpoint 1 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB40++0x3 line.long 0x0 "OTG_DOEPCTL2,OTG device OUT endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB40++0x3 line.long 0x0 "OTG_DOEPCTL2_ALTERNATE,OTG device OUT endpoint 2 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB48++0x3 line.long 0x0 "OTG_DOEPINT2,OTG device OUT endpoint 2 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB50++0x7 line.long 0x0 "OTG_DOEPTSIZ2,OTG device OUT endpoint 2 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA2,OTG device OUT endpoint 2 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB60++0x3 line.long 0x0 "OTG_DOEPCTL3,OTG device OUT endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB60++0x3 line.long 0x0 "OTG_DOEPCTL3_ALTERNATE,OTG device OUT endpoint 3 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB68++0x3 line.long 0x0 "OTG_DOEPINT3,OTG device OUT endpoint 3 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB70++0x7 line.long 0x0 "OTG_DOEPTSIZ3,OTG device OUT endpoint 3 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA3,OTG device OUT endpoint 3 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB80++0x3 line.long 0x0 "OTG_DOEPCTL4,OTG device OUT endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB80++0x3 line.long 0x0 "OTG_DOEPCTL4_ALTERNATE,OTG device OUT endpoint 4 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB88++0x3 line.long 0x0 "OTG_DOEPINT4,OTG device OUT endpoint 4 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB90++0x7 line.long 0x0 "OTG_DOEPTSIZ4,OTG device OUT endpoint 4 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA4,OTG device OUT endpoint 4 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBA0++0x3 line.long 0x0 "OTG_DOEPCTL5,OTG device OUT endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBA0++0x3 line.long 0x0 "OTG_DOEPCTL5_ALTERNATE,OTG device OUT endpoint 5 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBA8++0x3 line.long 0x0 "OTG_DOEPINT5,OTG device OUT endpoint 5 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBB0++0x7 line.long 0x0 "OTG_DOEPTSIZ5,OTG device OUT endpoint 5 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA5,OTG device OUT endpoint 5 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBC0++0x3 line.long 0x0 "OTG_DOEPCTL6,OTG device OUT endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBC0++0x3 line.long 0x0 "OTG_DOEPCTL6_ALTERNATE,OTG device OUT endpoint 6 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBC8++0x3 line.long 0x0 "OTG_DOEPINT6,OTG device OUT endpoint 6 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBD0++0x7 line.long 0x0 "OTG_DOEPTSIZ6,OTG device OUT endpoint 6 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA6,OTG device OUT endpoint 6 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBE0++0x3 line.long 0x0 "OTG_DOEPCTL7,OTG device OUT endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBE0++0x3 line.long 0x0 "OTG_DOEPCTL7_ALTERNATE,OTG device OUT endpoint 7 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBE8++0x3 line.long 0x0 "OTG_DOEPINT7,OTG device OUT endpoint 7 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBF0++0x7 line.long 0x0 "OTG_DOEPTSIZ7,OTG device OUT endpoint 7 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA7,OTG device OUT endpoint 7 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xC00++0x3 line.long 0x0 "OTG_DOEPCTL8,OTG device OUT endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" newline bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xC00++0x3 line.long 0x0 "OTG_DOEPCTL8_ALTERNATE,OTG device OUT endpoint 8 control register [alternate]" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" newline bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" newline bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xC08++0x3 line.long 0x0 "OTG_DOEPINT8,OTG device OUT endpoint 8 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" newline bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" newline bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" newline bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" newline bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xC10++0x7 line.long 0x0 "OTG_DOEPTSIZ8,OTG device OUT endpoint 8 transfer size register" bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA8,OTG device OUT endpoint 8 DMA address register" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xE00++0x7 line.long 0x0 "OTG_PCGCCTL,OTG power and clock gating control register" rbitfld.long 0x0 7. "SUSP,Deep Sleep" "0,1" newline rbitfld.long 0x0 6. "PHYSLEEP,PHY in Sleep" "0,1" newline bitfld.long 0x0 5. "ENL1GTG,Enable sleep clock gating" "0,1" newline rbitfld.long 0x0 4. "PHYSUSP,PHY suspended" "0,1" newline bitfld.long 0x0 1. "GATEHCLK,Gate HCLK" "0,1" newline bitfld.long 0x0 0. "STPPCLK,Stop PHY clock" "0,1" line.long 0x4 "OTG_PCGCCTL1,OTG power and clock gating control register 1" bitfld.long 0x4 3. "RAMGATEEN,Enable RAM clock gating" "0,1" newline bitfld.long 0x4 1.--2. "CNTGATECLK,Counter for clock gating" "0: 64 clocks,1: 128 clocks,?,?" newline bitfld.long 0x4 0. "GATEEN,Enable active clock gating" "0,1" tree.end tree.end sif (cpuis("STM32N655*")||cpuis("STM32N657*")) tree "PKA (Public Key Accelerator)" base ad:0x0 tree "PKA" base ad:0x44022000 group.long 0x0++0x3 line.long 0x0 "PKA_CR,PKA control register" bitfld.long 0x0 21. "OPERRIE,Operation error interrupt enable" "0: No interrupt is generated when OPERRF flag is..,1: An interrupt is generated when OPERRF flag is.." bitfld.long 0x0 20. "ADDRERRIE,Address error interrupt enable" "0: No interrupt is generated when ADDRERRF flag is..,1: An interrupt is generated when ADDRERRF flag is.." newline bitfld.long 0x0 19. "RAMERRIE,RAM error interrupt enable" "0: No interrupt is generated when RAMERRF flag is..,1: An interrupt is generated when RAMERRF flag is.." bitfld.long 0x0 17. "PROCENDIE,End of operation interrupt enable" "0: No interrupt is generated when PROCENDF flag is..,1: An interrupt is generated when PROCENDF flag is.." newline hexmask.long.byte 0x0 8.--13. 1. "MODE,PKA operation code" bitfld.long 0x0 1. "START,start the operation" "0,1" newline bitfld.long 0x0 0. "EN,PKA enable." "0: Disable PKA,1: Enable PKA.PKA becomes functional when INITOK is.." rgroup.long 0x4++0x3 line.long 0x0 "PKA_SR,PKA status register" bitfld.long 0x0 21. "OPERRF,Operation error flag" "0: No event error,1: An illegal or unknown operation has been.." bitfld.long 0x0 20. "ADDRERRF,Address error flag" "0: No address error,1: Address access is out of range (unmapped address)" newline bitfld.long 0x0 19. "RAMERRF,PKA RAM error flag" "0: No PKA RAM access error,1: An AHB access to the PKA RAM occurred while the.." bitfld.long 0x0 17. "PROCENDF,PKA End of Operation flag" "0: Operation in progress,1: PKA operation is completed. This flag is set.." newline bitfld.long 0x0 16. "BUSY,PKA operation is in progress" "0: No operation is in progress (default),1: An operation is in progress" bitfld.long 0x0 1. "LMF,Limited mode flag" "0: All values documented in MODE bitfield can be..,1: Only ECDSA verification (MODE = 0x26) is.." newline bitfld.long 0x0 0. "INITOK,PKA initialization OK" "0: PKA is not initialized correctly. START bit..,1: PKA is initialized correctly and can be used.." wgroup.long 0x8++0x3 line.long 0x0 "PKA_CLRFR,PKA clear flag register" bitfld.long 0x0 21. "OPERRFC,Clear operation error flag" "0: No action,1: Clear the OPERRF flag in PKA_SR" bitfld.long 0x0 20. "ADDRERRFC,Clear address error flag" "0: No action,1: Clear the ADDRERRF flag in PKA_SR" newline bitfld.long 0x0 19. "RAMERRFC,Clear PKA RAM error flag" "0: No action,1: Clear the RAMERRF flag in PKA_SR" bitfld.long 0x0 17. "PROCENDFC,Clear PKA End of Operation flag" "0: No action,1: Clear the PROCENDF flag in PKA_SR" tree.end tree "PKA_S" base ad:0x54022000 group.long 0x0++0x3 line.long 0x0 "PKA_CR,PKA control register" bitfld.long 0x0 21. "OPERRIE,Operation error interrupt enable" "0: No interrupt is generated when OPERRF flag is..,1: An interrupt is generated when OPERRF flag is.." bitfld.long 0x0 20. "ADDRERRIE,Address error interrupt enable" "0: No interrupt is generated when ADDRERRF flag is..,1: An interrupt is generated when ADDRERRF flag is.." newline bitfld.long 0x0 19. "RAMERRIE,RAM error interrupt enable" "0: No interrupt is generated when RAMERRF flag is..,1: An interrupt is generated when RAMERRF flag is.." bitfld.long 0x0 17. "PROCENDIE,End of operation interrupt enable" "0: No interrupt is generated when PROCENDF flag is..,1: An interrupt is generated when PROCENDF flag is.." newline hexmask.long.byte 0x0 8.--13. 1. "MODE,PKA operation code" bitfld.long 0x0 1. "START,start the operation" "0,1" newline bitfld.long 0x0 0. "EN,PKA enable." "0: Disable PKA,1: Enable PKA.PKA becomes functional when INITOK is.." rgroup.long 0x4++0x3 line.long 0x0 "PKA_SR,PKA status register" bitfld.long 0x0 21. "OPERRF,Operation error flag" "0: No event error,1: An illegal or unknown operation has been.." bitfld.long 0x0 20. "ADDRERRF,Address error flag" "0: No address error,1: Address access is out of range (unmapped address)" newline bitfld.long 0x0 19. "RAMERRF,PKA RAM error flag" "0: No PKA RAM access error,1: An AHB access to the PKA RAM occurred while the.." bitfld.long 0x0 17. "PROCENDF,PKA End of Operation flag" "0: Operation in progress,1: PKA operation is completed. This flag is set.." newline bitfld.long 0x0 16. "BUSY,PKA operation is in progress" "0: No operation is in progress (default),1: An operation is in progress" bitfld.long 0x0 1. "LMF,Limited mode flag" "0: All values documented in MODE bitfield can be..,1: Only ECDSA verification (MODE = 0x26) is.." newline bitfld.long 0x0 0. "INITOK,PKA initialization OK" "0: PKA is not initialized correctly. START bit..,1: PKA is initialized correctly and can be used.." wgroup.long 0x8++0x3 line.long 0x0 "PKA_CLRFR,PKA clear flag register" bitfld.long 0x0 21. "OPERRFC,Clear operation error flag" "0: No action,1: Clear the OPERRF flag in PKA_SR" bitfld.long 0x0 20. "ADDRERRFC,Clear address error flag" "0: No action,1: Clear the ADDRERRF flag in PKA_SR" newline bitfld.long 0x0 19. "RAMERRFC,Clear PKA RAM error flag" "0: No action,1: Clear the RAMERRF flag in PKA_SR" bitfld.long 0x0 17. "PROCENDFC,Clear PKA End of Operation flag" "0: No action,1: Clear the PROCENDF flag in PKA_SR" tree.end tree.end endif tree "PSSI (Parallel Synchronous Slave Interface)" base ad:0x0 tree "PSSI" base ad:0x48026400 group.long 0x0++0x3 line.long 0x0 "PSSI_CR,PSSI control register" bitfld.long 0x0 31. "OUTEN,Data direction selection bit" "0: Receive mode: data is input synchronously with..,1: Transmit mode: data is output synchronously with.." bitfld.long 0x0 30. "DMAEN,DMA enable bit" "0: DMA transfers are disabled. The user application..,1: DMA transfers are enabled (default.." newline bitfld.long 0x0 29. "CKSRC,Clock source" "0: External clock (PSSI_PDCK in input),1: Internal clock (PSSI_PDCK in output)" bitfld.long 0x0 18.--20. "DERDYCFG,Data enable and ready configuration" "0: PSSI_DE and PSSI_RDY both disabled,1: Only PSSI_RDY enabled,2: Only PSSI_DE enabled,3: Both PSSI_RDY and PSSI_DE alternate functions..,4: Both PSSI_RDY and PSSI_DE features enabled -..,5: Only PSSI_RDY function enabled but mapped to..,6: Only PSSI_DE function enabled but mapped to..,7: Both PSSI_RDY and PSSI_DE features enabled -.." newline bitfld.long 0x0 14. "ENABLE,PSSI enable" "0: PSSI disabled,1: PSSI enabled" bitfld.long 0x0 10.--11. "EDM,Extended data mode" "0: Interface captures 8-bit data on every parallel..,?,?,3: The interface captures 16-bit data on every.." newline bitfld.long 0x0 8. "RDYPOL,Ready (PSSI_RDY) polarity" "0: PSSI_RDY active low (0 indicates that the..,1: PSSI_RDY active high (1 indicates that the.." bitfld.long 0x0 6. "DEPOL,Data enable (PSSI_DE) polarity" "0: PSSI_DE active low (0 indicates that data is..,1: PSSI_DE active high (1 indicates that data is.." newline bitfld.long 0x0 5. "CKPOL,Parallel data clock polarity" "0: Falling edge active for inputs or rising edge..,1: Rising edge active for inputs or falling edge.." rgroup.long 0x4++0x7 line.long 0x0 "PSSI_SR,PSSI status register" bitfld.long 0x0 3. "RTT1B,FIFO is ready to transfer one byte" "0: FIFO is not ready for a 1-byte transfer,1: FIFO is ready for a one byte (32-bit) transfer." bitfld.long 0x0 2. "RTT4B,FIFO is ready to transfer four bytes" "0: FIFO is not ready for a four-byte transfer,1: FIFO is ready for a four-byte (32-bit) transfer." line.long 0x4 "PSSI_RIS,PSSI raw interrupt status register" bitfld.long 0x4 1. "OVR_RIS,Data buffer overrun/underrun raw interrupt status" "0: No overrun/underrun occurred,1: An overrun/underrun occurred: overrun in receive.." group.long 0xC++0x3 line.long 0x0 "PSSI_IER,PSSI interrupt enable register" bitfld.long 0x0 1. "OVR_IE,Data buffer overrun/underrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if either an overrun.." rgroup.long 0x10++0x3 line.long 0x0 "PSSI_MIS,PSSI masked interrupt status register" bitfld.long 0x0 1. "OVR_MIS,Data buffer overrun/underrun masked interrupt status" "0: No interrupt is generated when an..,1: An interrupt is generated if there is either an.." wgroup.long 0x14++0x3 line.long 0x0 "PSSI_ICR,PSSI interrupt clear register" bitfld.long 0x0 1. "OVR_ISC,Data buffer overrun/underrun interrupt status clear" "0,1" group.long 0x28++0x3 line.long 0x0 "PSSI_DR,PSSI data register" hexmask.long.byte 0x0 24.--31. 1. "BYTE3,Data byte 3" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,Data byte 2" newline hexmask.long.byte 0x0 8.--15. 1. "BYTE1,Data byte 1" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,Data byte 0" tree.end tree "PSSI_S" base ad:0x58026400 group.long 0x0++0x3 line.long 0x0 "PSSI_CR,PSSI control register" bitfld.long 0x0 31. "OUTEN,Data direction selection bit" "0: Receive mode: data is input synchronously with..,1: Transmit mode: data is output synchronously with.." bitfld.long 0x0 30. "DMAEN,DMA enable bit" "0: DMA transfers are disabled. The user application..,1: DMA transfers are enabled (default.." newline bitfld.long 0x0 29. "CKSRC,Clock source" "0: External clock (PSSI_PDCK in input),1: Internal clock (PSSI_PDCK in output)" bitfld.long 0x0 18.--20. "DERDYCFG,Data enable and ready configuration" "0: PSSI_DE and PSSI_RDY both disabled,1: Only PSSI_RDY enabled,2: Only PSSI_DE enabled,3: Both PSSI_RDY and PSSI_DE alternate functions..,4: Both PSSI_RDY and PSSI_DE features enabled -..,5: Only PSSI_RDY function enabled but mapped to..,6: Only PSSI_DE function enabled but mapped to..,7: Both PSSI_RDY and PSSI_DE features enabled -.." newline bitfld.long 0x0 14. "ENABLE,PSSI enable" "0: PSSI disabled,1: PSSI enabled" bitfld.long 0x0 10.--11. "EDM,Extended data mode" "0: Interface captures 8-bit data on every parallel..,?,?,3: The interface captures 16-bit data on every.." newline bitfld.long 0x0 8. "RDYPOL,Ready (PSSI_RDY) polarity" "0: PSSI_RDY active low (0 indicates that the..,1: PSSI_RDY active high (1 indicates that the.." bitfld.long 0x0 6. "DEPOL,Data enable (PSSI_DE) polarity" "0: PSSI_DE active low (0 indicates that data is..,1: PSSI_DE active high (1 indicates that data is.." newline bitfld.long 0x0 5. "CKPOL,Parallel data clock polarity" "0: Falling edge active for inputs or rising edge..,1: Rising edge active for inputs or falling edge.." rgroup.long 0x4++0x7 line.long 0x0 "PSSI_SR,PSSI status register" bitfld.long 0x0 3. "RTT1B,FIFO is ready to transfer one byte" "0: FIFO is not ready for a 1-byte transfer,1: FIFO is ready for a one byte (32-bit) transfer." bitfld.long 0x0 2. "RTT4B,FIFO is ready to transfer four bytes" "0: FIFO is not ready for a four-byte transfer,1: FIFO is ready for a four-byte (32-bit) transfer." line.long 0x4 "PSSI_RIS,PSSI raw interrupt status register" bitfld.long 0x4 1. "OVR_RIS,Data buffer overrun/underrun raw interrupt status" "0: No overrun/underrun occurred,1: An overrun/underrun occurred: overrun in receive.." group.long 0xC++0x3 line.long 0x0 "PSSI_IER,PSSI interrupt enable register" bitfld.long 0x0 1. "OVR_IE,Data buffer overrun/underrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if either an overrun.." rgroup.long 0x10++0x3 line.long 0x0 "PSSI_MIS,PSSI masked interrupt status register" bitfld.long 0x0 1. "OVR_MIS,Data buffer overrun/underrun masked interrupt status" "0: No interrupt is generated when an..,1: An interrupt is generated if there is either an.." wgroup.long 0x14++0x3 line.long 0x0 "PSSI_ICR,PSSI interrupt clear register" bitfld.long 0x0 1. "OVR_ISC,Data buffer overrun/underrun interrupt status clear" "0,1" group.long 0x28++0x3 line.long 0x0 "PSSI_DR,PSSI data register" hexmask.long.byte 0x0 24.--31. 1. "BYTE3,Data byte 3" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,Data byte 2" newline hexmask.long.byte 0x0 8.--15. 1. "BYTE1,Data byte 1" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,Data byte 0" tree.end tree.end tree "PWR (Power Control)" base ad:0x0 tree "PWR" base ad:0x46024800 group.long 0x0++0xF line.long 0x0 "PWR_CR1,PWR control register 1" hexmask.long.byte 0x0 16.--20. 1. "POPL,pwr_on pulse low configuration." bitfld.long 0x0 5. "LPDS08V,SMPS low-power mode enable (SVOS high only)" "0: SMPS low-power mode disabled,1: SMPS low-power mode enabled (high-efficiency.." newline bitfld.long 0x0 4. "MODE_PDN,Enables the pull down on output voltage during power-down mode" "0: Pull-down disabled. The output is in high..,1: Pull-down enabled" bitfld.long 0x0 2. "SDEN,SMPS step-down converter enable" "0: SMPS step-down converter disabled,1: SMPS step-down converter enabled (default)" line.long 0x4 "PWR_CR2,PWR control register 2" rbitfld.long 0x4 8. "PVDO,Programmable voltage detect output" "0: Voltage level on PVD_IN is equal or higher than..,1: Voltage level on PVD_IN is lower than the.." bitfld.long 0x4 0. "PVDEN,Programmable voltage detector enable" "0: PVD disabled,1: PVD enabled" line.long 0x8 "PWR_CR3,PWR control register 3" rbitfld.long 0x8 9. "VCOREH,Monitored V less than sub>DDCORE less than /sub> level above high threshold" "0: V less than sub>DDCORE less than /sub> level..,1: V less than sub>DDCORE less than /sub> level.." rbitfld.long 0x8 8. "VCOREL,Monitored V less than sub>DDCORE less than /sub> level above low threshold" "0: V less than sub>DDCORE less than /sub> level..,1: V less than sub>DDCORE less than /sub> level.." newline bitfld.long 0x8 4. "VCORELLS,V less than sub>DDCORE less than /sub> voltage detector low-level selection" "0: V less than sub>DDCORE less than /sub>..,1: V less than sub>DDCORE less than /sub>.." bitfld.long 0x8 0. "VCOREMONEN,V less than sub>DDCORE less than /sub> monitoring enable" "0: V less than sub>DDCORE less than /sub>..,1: V less than sub>DDCORE less than /sub>.." line.long 0xC "PWR_CR4,PWR control register 4" bitfld.long 0xC 4. "TCMFLXRBSEN,I-TCM FLEXMEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode)" "0: I-TCM FLEXMEM backup supply disabled,1: I-TCM FLEXMEM backup supply enabled in Standby.." bitfld.long 0xC 0. "TCMRBSEN,I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode)" "0: I-TCM and D-TCM RAMs backup supply disabled,1: I-TCM and D-TCM RAMs backup supply enabled in.." group.long 0x20++0x1F line.long 0x0 "PWR_VOSCR,PWR voltage scaling control register" rbitfld.long 0x0 17. "ACTVOSRDY,Voltage level ready bit for currently used ACTVOS" "0: Voltage level invalid above or below current..,1: Voltage level valid at current ACTVOS" rbitfld.long 0x0 16. "ACTVOS,VOS currently applied for V less than sub>CORE less than /sub> voltage scaling selection" "0,1" newline rbitfld.long 0x0 1. "VOSRDY,VOS ready bit for V less than sub>CORE less than /sub> voltage scaling output selection" "0: Not ready voltage level below VOS selected level,1: Ready voltage level at or above VOS selected level" bitfld.long 0x0 0. "VOS,Voltage scaling selection according to performance" "0: VOS low level (default),1: VOS high level" line.long 0x4 "PWR_BDCR1,PWR backup domain control register 1" rbitfld.long 0x4 19. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature below high threshold level,1: Temperature equal or above high threshold level" rbitfld.long 0x4 18. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature above low threshold level,1: Temperature equal or below low threshold level" newline rbitfld.long 0x4 17. "VBATH,V less than sub>BAT less than /sub> level monitoring versus high threshold" "0: V less than sub>BAT less than /sub> level below..,1: V less than sub>BAT less than /sub> level equal.." rbitfld.long 0x4 16. "VBATL,V less than sub>BAT less than /sub> level monitoring versus low threshold" "0: V less than sub>BAT less than /sub> level above..,1: V less than sub>BAT less than /sub> level equal.." newline bitfld.long 0x4 0. "MONEN,V less than sub>BAT less than /sub> and temperature monitoring enable" "0: V less than sub>BAT less than /sub> and..,1: V less than sub>BAT less than /sub> and.." line.long 0x8 "PWR_BDCR2,PWR backup domain control register 2" bitfld.long 0x8 0. "BKPRBSEN,Backup RAM backup supply enable (used to maintain BKPRAM content in Standby and V less than sub>BAT less than /sub> modes)." "0: BKPSRAM backup supply disabled,1: BKPSRAM backup supply enabled" line.long 0xC "PWR_DBPCR,PWR disable backup protection control register" bitfld.long 0xC 0. "DBP,Disable backup domain write protection" "0: Write access to backup domain disabled,1: Write access to backup domain enabled" line.long 0x10 "PWR_CPUCR,PWR CPU control register" bitfld.long 0x10 16. "SVOS,System Stop mode voltage scaling selection" "0: SVOS low,1: SVOS high (default)" rbitfld.long 0x10 9. "SBF,Standby flag" "0: System has not been in Standby mode.,1: System has been in Standby mode." newline rbitfld.long 0x10 8. "STOPF,Stop flag" "0: System has not been in Stop mode.,1: System has been in Stop mode." bitfld.long 0x10 1. "CSSF,Clear Standby and Stop flags (always read as 0)" "0: No effect,1: When written clear the CPU flags (STOPF SBF)." newline bitfld.long 0x10 0. "PDDS,Power-down deepsleep selection" "0: Stop mode when device enters deepsleep,1: Standby mode when device enters deepsleep" line.long 0x14 "PWR_SVMCR1,PWR supply voltage monitoring control register 1" bitfld.long 0x14 25. "VDDIO4VRSTBY,V less than sub>DDIO4 less than /sub> I/O voltage range Standby mode" "0: VDDIO4VRSEL not retained in Standby mode,1: VDDIO4VRSEL retained in Standby mode" bitfld.long 0x14 24. "VDDIO4VRSEL,V less than sub>DDIO4 less than /sub> I/O voltage range selection" "0: 3v3 voltage range selected. If V less than..,1: 1v8 voltage range selected. HSLV_VDDIO4 option.." newline rbitfld.long 0x14 16. "VDDIO4RDY,V less than sub>DDIO4 less than /sub>ready" "0: V less than sub>DDIO4 less than /sub> is below..,1: V less than sub>DDIO4 less than /sub> is equal.." bitfld.long 0x14 8. "VDDIO4SV,V less than sub>DDIO4 less than /sub>independent I/O supply valid." "0: V less than sub>DDIO4 less than /sub> is not..,1: V less than sub>DDIO4 less than /sub> is valid." newline bitfld.long 0x14 0. "VDDIO4VMEN,V less than sub>DDIO4 less than /sub>independent I/O voltage monitor enable" "0: V less than sub>DDIO4 less than /sub> voltage..,1: V less than sub>DDIO4 less than /sub> voltage.." line.long 0x18 "PWR_SVMCR2,PWR supply voltage monitoring control register 2" bitfld.long 0x18 25. "VDDIO5VRSTBY,V less than sub>DDIO5 less than /sub> I/O voltage range Standby mode" "0: VDDIO5VRSEL not retained in Standby mode,1: VDDIO5VRSEL retained in Standby mod." bitfld.long 0x18 24. "VDDIO5VRSEL,V less than sub>DDIO5 less than /sub> I/O voltage range selection" "0: 3v3 voltage range selected. If V less than..,1: 1v8 voltage range selected. HSLV_VDDIO5 option.." newline rbitfld.long 0x18 16. "VDDIO5RDY,V less than sub>DDIO5 less than /sub>ready" "0: V less than sub>DDIO5 less than /sub> is below..,1: V less than sub>DDIO5 less than /sub> is equal.." bitfld.long 0x18 8. "VDDIO5SV,V less than sub>DDIO5 less than /sub>independent supply valid" "0: V less than sub>DDIO5 less than /sub> is not..,1: V less than sub>DDIO5 less than /sub> is valid." newline bitfld.long 0x18 0. "VDDIO5VMEN,V less than sub>DDIO5 less than /sub>independent voltage monitor enable" "0: V less than sub>DDIO5 less than /sub>voltage..,1: V less than sub>DDIO5 less than /sub>voltage.." line.long 0x1C "PWR_SVMCR3,PWR supply voltage monitoring control register 3" bitfld.long 0x1C 26. "VDDIO3VRSEL,V less than sub>DDIO3 less than /sub> I/O voltage range selection" "0: 3v3 voltage range selected. If V less than..,1: 1v8 voltage range selected. HSLV_VDDIO3 option.." bitfld.long 0x1C 25. "VDDIO2VRSEL,V less than sub>DDIO2 less than /sub> I/O voltage range selection" "0: 3v3 voltage range selected. If V less than..,1: 1v8 voltage range selected. HSLV_VDDIO2 option.." newline bitfld.long 0x1C 24. "VDDIOVRSEL,V less than sub>DD less than /sub> I/O voltage range selection" "0: 3v3 voltage range selected. If V less than..,1: 1v8 voltage range selected. HSLV_VDD option bit.." rbitfld.long 0x1C 20. "ARDY,V less than sub>DDA18ADC less than /sub>ready" "0: V less than sub>DDA18ADC less than /sub> is..,1: V less than sub>DDA18ADC less than /sub> is.." newline rbitfld.long 0x1C 18. "USB33RDY,V less than sub>DD33USB less than /sub>ready" "0: V less than sub>DD33USB less than /sub> is below..,1: V less than sub>DD33USB less than /sub> is equal.." rbitfld.long 0x1C 17. "VDDIO3RDY,V less than sub>DDIO3 less than /sub>ready" "0: V less than sub>DDIO3 less than /sub> is below..,1: V less than sub>DDIO3 less than /sub> is equal.." newline rbitfld.long 0x1C 16. "VDDIO2RDY,V less than sub>DDIO2 less than /sub>ready" "0: V less than sub>DDIO2 less than /sub> is below..,1: V less than sub>DDIO2 less than /sub> is equal.." bitfld.long 0x1C 12. "ASV,V less than sub>DDA18ADC less than /sub>independent supply valid" "0: V less than sub>DDA18ADC less than /sub> is not..,1: V less than sub>DDA18ADC less than /sub> is valid." newline bitfld.long 0x1C 10. "USB33SV,V less than sub>DD33USB less than /sub>independent supply valid" "0: V less than sub>DD33USB less than /sub> is not..,1: V less than sub>DD33USB less than /sub> is valid." bitfld.long 0x1C 9. "VDDIO3SV,V less than sub>DDIO3 less than /sub>independent supply valid" "0: V less than sub>DDIO3 less than /sub> is not..,1: V less than sub>DDIO3 less than /sub> is valid." newline bitfld.long 0x1C 8. "VDDIO2SV,V less than sub>DDIO2 less than /sub>independent supply valid." "0: V less than sub>DDIO2 less than /sub> is not..,1: V less than sub>DDIO2 less than /sub> is valid." bitfld.long 0x1C 4. "AVMEN,V less than sub>DDA18ADC less than /sub>independent ADC voltage monitor enable" "0: V less than sub>DDA18ADC less than /sub> voltage..,1: V less than sub>DDA18ADC less than /sub> voltage.." newline bitfld.long 0x1C 2. "USB33VMEN,V less than sub>DD33USB less than /sub>independent USB 33 voltage monitor enable." "0: V less than sub>DD33USB less than /sub> voltage..,1: V less than sub>DD33USB less than /sub> voltage.." bitfld.long 0x1C 1. "VDDIO3VMEN,V less than sub>DDIO3 less than /sub>independent voltage monitor enable" "0: V less than sub>DDIO3 less than /sub> voltage..,1: V less than sub>DDIO3 less than /sub> voltage.." newline bitfld.long 0x1C 0. "VDDIO2VMEN,V less than sub>DDIO2 less than /sub>independent voltage monitor enable" "0: V less than sub>DDIO2 less than /sub> voltage..,1: V less than sub>DDIO2 less than /sub> voltage.." wgroup.long 0x50++0x3 line.long 0x0 "PWR_WKUPCR,PWR wake-up clear register" bitfld.long 0x0 3. "WKUPC4,Clear wake-up flag for WKUP4 pin" "0: No effect,1: Writing 1 clears WKUPF4 in PWR_WKUPSR." bitfld.long 0x0 2. "WKUPC3,Clear wake-up flag for WKUP3 pin" "0: No effect,1: Writing 1 clears WKUPF3 in PWR_WKUPSR." newline bitfld.long 0x0 1. "WKUPC2,Clear wake-up flag for WKUP2 pin" "0: No effect,1: Writing 1 clears WKUPF2 in PWR_WKUPSR." bitfld.long 0x0 0. "WKUPC1,Clear wake-up flag for WKUP1 pin" "0: No effect,1: Writing 1 clears WKUPF1 in PWR_WKUPSR." rgroup.long 0x54++0x3 line.long 0x0 "PWR_WKUPSR,PWR wake-up status register" bitfld.long 0x0 3. "WKUPF4,Wake-up flag for WKUP4 pin before enable" "0: No wake-up event occurred,1: A wake-up event was received from WKUP4 pin." bitfld.long 0x0 2. "WKUPF3,Wake-up flag for WKUP3 pin before enable" "0: No wake-up event occurred,1: A wake-up event was received from WKUP3 pin." newline bitfld.long 0x0 1. "WKUPF2,Wake-up flag for WKUP2 pin before enable" "0: No wake-up event occurred,1: A wake-up event was received from WKUP2 pin." bitfld.long 0x0 0. "WKUPF1,Wake-up flag for WKUP1 pin before enable" "0: No wake-up event occurred,1: A wake-up event was received from WKUP1 pin." group.long 0x58++0x3 line.long 0x0 "PWR_WKUPEPR,PWR wake-up enable and polarity register" bitfld.long 0x0 22.--23. "WKUPPUPD4,Wake-up pull configuration for WKUP4 pin" "0: No pulls,1: Pull-up,2: Pull-down,?" bitfld.long 0x0 20.--21. "WKUPPUPD3,Wake-up pull configuration for WKUP3 pin" "0: No pulls,1: Pull-up,2: Pull-down,?" newline bitfld.long 0x0 18.--19. "WKUPPUPD2,Wake-up pull configuration for WKUP2 pin" "0: No pulls,1: Pull-up,2: Pull-down,?" bitfld.long 0x0 16.--17. "WKUPPUPD1,Wake-up pull configuration for WKUP1 pin" "0: No pulls,1: Pull-up,2: Pull-down,?" newline bitfld.long 0x0 11. "WKUPP4,Wake-up polarity bit for WKUP4 pin" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x0 10. "WKUPP3,Wake-up polarity bit for WKUP3 pin" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x0 9. "WKUPP2,Wake-up polarity bit for WKUP2 pin" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x0 8. "WKUPP1,Wake-up polarity bit for WKUP1 pin" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x0 3. "WKUPEN4,Enable WKUP4 pin" "0: An event on WKUP4 pin does not wake up the..,1: A rising or falling edge on WKUP4 pin wakes up.." bitfld.long 0x0 2. "WKUPEN3,Enable WKUP3 pin" "0: An event on WKUP3 pin does not wake up the..,1: A rising or falling edge on WKUP3 pin wakes up.." newline bitfld.long 0x0 1. "WKUPEN2,Enable WKUP2 pin" "0: An event on WKUP2 pin does not wake up the..,1: A rising or falling edge on WKUP2 pin wakes up.." bitfld.long 0x0 0. "WKUPEN1,Enable WKUP1 pin" "0: An event on WKUP1 pin does not wake up the..,1: A rising or falling edge on WKUP1 pin wakes up.." group.long 0x70++0x7 line.long 0x0 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x0 19. "WKUPSEC4,WKUP4 pin secure protection" "0: Bits related to WKUP4 pin in PWR_WKUPCR..,1: Bits related to WKUP4 pin in PWR_WKUPCR.." bitfld.long 0x0 18. "WKUPSEC3,WKUP3 pin secure protection" "0: Bits related to WKUP3 pin in PWR_WKUPCR..,1: Bits related to WKUP3 pin in PWR_WKUPCR.." newline bitfld.long 0x0 17. "WKUPSEC2,WKUP2 pin secure protection" "0: Bits related to WKUP2 pin in PWR_WKUPCR..,1: Bits related to WKUP2 pin in PWR_WKUPCR.." bitfld.long 0x0 16. "WKUPSEC1,WKUP1 pin secure protection" "0: Bits related to WKUP1 pin in PWR_WKUPCR..,1: Bits related to WKUP1 pin in PWR_WKUPCR.." newline bitfld.long 0x0 7. "SEC7,Peripheral voltage monitor secure protection" "0: PWR_SVMCR1 PWR_SVMCR2 and PWR_SVMCR3 can be read..,1: PWR_SVMCR1 PWR_SVMCR2 and PWR_SVMCR3 can be read.." bitfld.long 0x0 6. "SEC6,CPU power control secure protection" "0: PWR_CPUCR can be read and written with secure or..,1: PWR_CPUCR can be read and written only with.." newline bitfld.long 0x0 5. "SEC5,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPCR can be read..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPCR can be read.." bitfld.long 0x0 4. "SEC4,Voltage scaling selection secure protection" "0: PWR_VOSCR can be read and written with secure or..,1: PWR_VOSCR can be read and written only with.." newline bitfld.long 0x0 3. "SEC3,I-TCM D-TCM and I-TCM FLEXMEM low power control secure protection" "0: PWR_CR4 can be read and written with secure or..,1: PWR_CR4 can be read and written only with secure.." bitfld.long 0x0 2. "SEC2,V less than sub>DDCORE less than /sub> monitor secure protection" "0: PWR_CR3 can be read and written with secure or..,1: PWR_CR3 can be read and written only with secure.." newline bitfld.long 0x0 1. "SEC1,Programmable voltage detector secure protection" "0: PWR_CR2 can be read and written with secure or..,1: PWR_CR2 can be read and written only with secure.." bitfld.long 0x0 0. "SEC0,System supply configuration secure protection" "0: PWR_CR1 can be read and written with secure or..,1: PWR_CR1 can be read and written only with secure.." line.long 0x4 "PWR_PRIVCFGR,PWR privilege configuration register" bitfld.long 0x4 19. "WKUPPRIV4,WKUP4 pin privileged protection" "0: Bits related to WKUP4 pin in PWR_WKUPCR..,1: Bits related to WKUP4 pin in PWR_WKUPCR.." bitfld.long 0x4 18. "WKUPPRIV3,WKUP3 pin privileged protection" "0: Bits related to WKUP3 pin in PWR_WKUPCR..,1: Bits related to WKUP3 pin in PWR_WKUPCR.." newline bitfld.long 0x4 17. "WKUPPRIV2,WKUP2 pin privileged protection" "0: Bits related to WKUP2 pin in PWR_WKUPCR..,1: Bits related to WKUP2 pin in PWR_WKUPCR.." bitfld.long 0x4 16. "WKUPPRIV1,WKUP1 pin privileged protection" "0: Bits related to WKUP1 pin in PWR_WKUPCR..,1: Bits related to WKUP1 pin in PWR_WKUPCR.." newline bitfld.long 0x4 7. "PRIV7,Peripheral voltage monitor privileged protection" "0: PWR_SVMCR1 PWR_SVMCR2 and PWR_SVMCR3 can be read..,1: PWR_SVMCR1 PWR_SVMCR2 and PWR_SVMCR3 can be read.." bitfld.long 0x4 6. "PRIV6,CPU power control privileged protection" "0: PWR_CPUCR can be read and written with..,1: PWR_CPUCR can be read and written only with.." newline bitfld.long 0x4 5. "PRIV5,Backup domain privileged protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPCR can be read..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPCR can be read.." bitfld.long 0x4 4. "PRIV4,Voltage scaling selection privileged protection" "0: PWR_VOSCR can be read and written with..,1: PWR_VOSCR can be read and written only with.." newline bitfld.long 0x4 3. "PRIV3,I-TCM D-TCM and I-TCM FLEX MEM low power control privileged protection" "0: PWR_CR4 can be read and written with privileged..,1: PWR_CR4 can be read and written only with.." bitfld.long 0x4 2. "PRIV2,V less than sub>DDCORE less than /sub> monitor privileged protection" "0: PWR_CR3 can be read and written with privileged..,1: PWR_CR3 can be read and written only with.." newline bitfld.long 0x4 1. "PRIV1,Programmable voltage detector privileged protection" "0: PWR_CR2 can be read and written with privileged..,1: PWR_CR2 can be read and written only with.." bitfld.long 0x4 0. "PRIV0,System supply configuration privileged protection" "0: PWR_CR1 can be read and written with privileged..,1: PWR_CR1 can be read and written only with.." tree.end tree "PWR_S" base ad:0x56024800 group.long 0x0++0xF line.long 0x0 "PWR_CR1,PWR control register 1" hexmask.long.byte 0x0 16.--20. 1. "POPL,pwr_on pulse low configuration." bitfld.long 0x0 5. "LPDS08V,SMPS low-power mode enable (SVOS high only)" "0: SMPS low-power mode disabled,1: SMPS low-power mode enabled (high-efficiency.." newline bitfld.long 0x0 4. "MODE_PDN,Enables the pull down on output voltage during power-down mode" "0: Pull-down disabled. The output is in high..,1: Pull-down enabled" bitfld.long 0x0 2. "SDEN,SMPS step-down converter enable" "0: SMPS step-down converter disabled,1: SMPS step-down converter enabled (default)" line.long 0x4 "PWR_CR2,PWR control register 2" rbitfld.long 0x4 8. "PVDO,Programmable voltage detect output" "0: Voltage level on PVD_IN is equal or higher than..,1: Voltage level on PVD_IN is lower than the.." bitfld.long 0x4 0. "PVDEN,Programmable voltage detector enable" "0: PVD disabled,1: PVD enabled" line.long 0x8 "PWR_CR3,PWR control register 3" rbitfld.long 0x8 9. "VCOREH,Monitored V less than sub>DDCORE less than /sub> level above high threshold" "0: V less than sub>DDCORE less than /sub> level..,1: V less than sub>DDCORE less than /sub> level.." rbitfld.long 0x8 8. "VCOREL,Monitored V less than sub>DDCORE less than /sub> level above low threshold" "0: V less than sub>DDCORE less than /sub> level..,1: V less than sub>DDCORE less than /sub> level.." newline bitfld.long 0x8 4. "VCORELLS,V less than sub>DDCORE less than /sub> voltage detector low-level selection" "0: V less than sub>DDCORE less than /sub>..,1: V less than sub>DDCORE less than /sub>.." bitfld.long 0x8 0. "VCOREMONEN,V less than sub>DDCORE less than /sub> monitoring enable" "0: V less than sub>DDCORE less than /sub>..,1: V less than sub>DDCORE less than /sub>.." line.long 0xC "PWR_CR4,PWR control register 4" bitfld.long 0xC 4. "TCMFLXRBSEN,I-TCM FLEXMEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode)" "0: I-TCM FLEXMEM backup supply disabled,1: I-TCM FLEXMEM backup supply enabled in Standby.." bitfld.long 0xC 0. "TCMRBSEN,I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode)" "0: I-TCM and D-TCM RAMs backup supply disabled,1: I-TCM and D-TCM RAMs backup supply enabled in.." group.long 0x20++0x1F line.long 0x0 "PWR_VOSCR,PWR voltage scaling control register" rbitfld.long 0x0 17. "ACTVOSRDY,Voltage level ready bit for currently used ACTVOS" "0: Voltage level invalid above or below current..,1: Voltage level valid at current ACTVOS" rbitfld.long 0x0 16. "ACTVOS,VOS currently applied for V less than sub>CORE less than /sub> voltage scaling selection" "0,1" newline rbitfld.long 0x0 1. "VOSRDY,VOS ready bit for V less than sub>CORE less than /sub> voltage scaling output selection" "0: Not ready voltage level below VOS selected level,1: Ready voltage level at or above VOS selected level" bitfld.long 0x0 0. "VOS,Voltage scaling selection according to performance" "0: VOS low level (default),1: VOS high level" line.long 0x4 "PWR_BDCR1,PWR backup domain control register 1" rbitfld.long 0x4 19. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature below high threshold level,1: Temperature equal or above high threshold level" rbitfld.long 0x4 18. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature above low threshold level,1: Temperature equal or below low threshold level" newline rbitfld.long 0x4 17. "VBATH,V less than sub>BAT less than /sub> level monitoring versus high threshold" "0: V less than sub>BAT less than /sub> level below..,1: V less than sub>BAT less than /sub> level equal.." rbitfld.long 0x4 16. "VBATL,V less than sub>BAT less than /sub> level monitoring versus low threshold" "0: V less than sub>BAT less than /sub> level above..,1: V less than sub>BAT less than /sub> level equal.." newline bitfld.long 0x4 0. "MONEN,V less than sub>BAT less than /sub> and temperature monitoring enable" "0: V less than sub>BAT less than /sub> and..,1: V less than sub>BAT less than /sub> and.." line.long 0x8 "PWR_BDCR2,PWR backup domain control register 2" bitfld.long 0x8 0. "BKPRBSEN,Backup RAM backup supply enable (used to maintain BKPRAM content in Standby and V less than sub>BAT less than /sub> modes)." "0: BKPSRAM backup supply disabled,1: BKPSRAM backup supply enabled" line.long 0xC "PWR_DBPCR,PWR disable backup protection control register" bitfld.long 0xC 0. "DBP,Disable backup domain write protection" "0: Write access to backup domain disabled,1: Write access to backup domain enabled" line.long 0x10 "PWR_CPUCR,PWR CPU control register" bitfld.long 0x10 16. "SVOS,System Stop mode voltage scaling selection" "0: SVOS low,1: SVOS high (default)" rbitfld.long 0x10 9. "SBF,Standby flag" "0: System has not been in Standby mode.,1: System has been in Standby mode." newline rbitfld.long 0x10 8. "STOPF,Stop flag" "0: System has not been in Stop mode.,1: System has been in Stop mode." bitfld.long 0x10 1. "CSSF,Clear Standby and Stop flags (always read as 0)" "0: No effect,1: When written clear the CPU flags (STOPF SBF)." newline bitfld.long 0x10 0. "PDDS,Power-down deepsleep selection" "0: Stop mode when device enters deepsleep,1: Standby mode when device enters deepsleep" line.long 0x14 "PWR_SVMCR1,PWR supply voltage monitoring control register 1" bitfld.long 0x14 25. "VDDIO4VRSTBY,V less than sub>DDIO4 less than /sub> I/O voltage range Standby mode" "0: VDDIO4VRSEL not retained in Standby mode,1: VDDIO4VRSEL retained in Standby mode" bitfld.long 0x14 24. "VDDIO4VRSEL,V less than sub>DDIO4 less than /sub> I/O voltage range selection" "0: 3v3 voltage range selected. If V less than..,1: 1v8 voltage range selected. HSLV_VDDIO4 option.." newline rbitfld.long 0x14 16. "VDDIO4RDY,V less than sub>DDIO4 less than /sub>ready" "0: V less than sub>DDIO4 less than /sub> is below..,1: V less than sub>DDIO4 less than /sub> is equal.." bitfld.long 0x14 8. "VDDIO4SV,V less than sub>DDIO4 less than /sub>independent I/O supply valid." "0: V less than sub>DDIO4 less than /sub> is not..,1: V less than sub>DDIO4 less than /sub> is valid." newline bitfld.long 0x14 0. "VDDIO4VMEN,V less than sub>DDIO4 less than /sub>independent I/O voltage monitor enable" "0: V less than sub>DDIO4 less than /sub> voltage..,1: V less than sub>DDIO4 less than /sub> voltage.." line.long 0x18 "PWR_SVMCR2,PWR supply voltage monitoring control register 2" bitfld.long 0x18 25. "VDDIO5VRSTBY,V less than sub>DDIO5 less than /sub> I/O voltage range Standby mode" "0: VDDIO5VRSEL not retained in Standby mode,1: VDDIO5VRSEL retained in Standby mod." bitfld.long 0x18 24. "VDDIO5VRSEL,V less than sub>DDIO5 less than /sub> I/O voltage range selection" "0: 3v3 voltage range selected. If V less than..,1: 1v8 voltage range selected. HSLV_VDDIO5 option.." newline rbitfld.long 0x18 16. "VDDIO5RDY,V less than sub>DDIO5 less than /sub>ready" "0: V less than sub>DDIO5 less than /sub> is below..,1: V less than sub>DDIO5 less than /sub> is equal.." bitfld.long 0x18 8. "VDDIO5SV,V less than sub>DDIO5 less than /sub>independent supply valid" "0: V less than sub>DDIO5 less than /sub> is not..,1: V less than sub>DDIO5 less than /sub> is valid." newline bitfld.long 0x18 0. "VDDIO5VMEN,V less than sub>DDIO5 less than /sub>independent voltage monitor enable" "0: V less than sub>DDIO5 less than /sub>voltage..,1: V less than sub>DDIO5 less than /sub>voltage.." line.long 0x1C "PWR_SVMCR3,PWR supply voltage monitoring control register 3" bitfld.long 0x1C 26. "VDDIO3VRSEL,V less than sub>DDIO3 less than /sub> I/O voltage range selection" "0: 3v3 voltage range selected. If V less than..,1: 1v8 voltage range selected. HSLV_VDDIO3 option.." bitfld.long 0x1C 25. "VDDIO2VRSEL,V less than sub>DDIO2 less than /sub> I/O voltage range selection" "0: 3v3 voltage range selected. If V less than..,1: 1v8 voltage range selected. HSLV_VDDIO2 option.." newline bitfld.long 0x1C 24. "VDDIOVRSEL,V less than sub>DD less than /sub> I/O voltage range selection" "0: 3v3 voltage range selected. If V less than..,1: 1v8 voltage range selected. HSLV_VDD option bit.." rbitfld.long 0x1C 20. "ARDY,V less than sub>DDA18ADC less than /sub>ready" "0: V less than sub>DDA18ADC less than /sub> is..,1: V less than sub>DDA18ADC less than /sub> is.." newline rbitfld.long 0x1C 18. "USB33RDY,V less than sub>DD33USB less than /sub>ready" "0: V less than sub>DD33USB less than /sub> is below..,1: V less than sub>DD33USB less than /sub> is equal.." rbitfld.long 0x1C 17. "VDDIO3RDY,V less than sub>DDIO3 less than /sub>ready" "0: V less than sub>DDIO3 less than /sub> is below..,1: V less than sub>DDIO3 less than /sub> is equal.." newline rbitfld.long 0x1C 16. "VDDIO2RDY,V less than sub>DDIO2 less than /sub>ready" "0: V less than sub>DDIO2 less than /sub> is below..,1: V less than sub>DDIO2 less than /sub> is equal.." bitfld.long 0x1C 12. "ASV,V less than sub>DDA18ADC less than /sub>independent supply valid" "0: V less than sub>DDA18ADC less than /sub> is not..,1: V less than sub>DDA18ADC less than /sub> is valid." newline bitfld.long 0x1C 10. "USB33SV,V less than sub>DD33USB less than /sub>independent supply valid" "0: V less than sub>DD33USB less than /sub> is not..,1: V less than sub>DD33USB less than /sub> is valid." bitfld.long 0x1C 9. "VDDIO3SV,V less than sub>DDIO3 less than /sub>independent supply valid" "0: V less than sub>DDIO3 less than /sub> is not..,1: V less than sub>DDIO3 less than /sub> is valid." newline bitfld.long 0x1C 8. "VDDIO2SV,V less than sub>DDIO2 less than /sub>independent supply valid." "0: V less than sub>DDIO2 less than /sub> is not..,1: V less than sub>DDIO2 less than /sub> is valid." bitfld.long 0x1C 4. "AVMEN,V less than sub>DDA18ADC less than /sub>independent ADC voltage monitor enable" "0: V less than sub>DDA18ADC less than /sub> voltage..,1: V less than sub>DDA18ADC less than /sub> voltage.." newline bitfld.long 0x1C 2. "USB33VMEN,V less than sub>DD33USB less than /sub>independent USB 33 voltage monitor enable." "0: V less than sub>DD33USB less than /sub> voltage..,1: V less than sub>DD33USB less than /sub> voltage.." bitfld.long 0x1C 1. "VDDIO3VMEN,V less than sub>DDIO3 less than /sub>independent voltage monitor enable" "0: V less than sub>DDIO3 less than /sub> voltage..,1: V less than sub>DDIO3 less than /sub> voltage.." newline bitfld.long 0x1C 0. "VDDIO2VMEN,V less than sub>DDIO2 less than /sub>independent voltage monitor enable" "0: V less than sub>DDIO2 less than /sub> voltage..,1: V less than sub>DDIO2 less than /sub> voltage.." wgroup.long 0x50++0x3 line.long 0x0 "PWR_WKUPCR,PWR wake-up clear register" bitfld.long 0x0 3. "WKUPC4,Clear wake-up flag for WKUP4 pin" "0: No effect,1: Writing 1 clears WKUPF4 in PWR_WKUPSR." bitfld.long 0x0 2. "WKUPC3,Clear wake-up flag for WKUP3 pin" "0: No effect,1: Writing 1 clears WKUPF3 in PWR_WKUPSR." newline bitfld.long 0x0 1. "WKUPC2,Clear wake-up flag for WKUP2 pin" "0: No effect,1: Writing 1 clears WKUPF2 in PWR_WKUPSR." bitfld.long 0x0 0. "WKUPC1,Clear wake-up flag for WKUP1 pin" "0: No effect,1: Writing 1 clears WKUPF1 in PWR_WKUPSR." rgroup.long 0x54++0x3 line.long 0x0 "PWR_WKUPSR,PWR wake-up status register" bitfld.long 0x0 3. "WKUPF4,Wake-up flag for WKUP4 pin before enable" "0: No wake-up event occurred,1: A wake-up event was received from WKUP4 pin." bitfld.long 0x0 2. "WKUPF3,Wake-up flag for WKUP3 pin before enable" "0: No wake-up event occurred,1: A wake-up event was received from WKUP3 pin." newline bitfld.long 0x0 1. "WKUPF2,Wake-up flag for WKUP2 pin before enable" "0: No wake-up event occurred,1: A wake-up event was received from WKUP2 pin." bitfld.long 0x0 0. "WKUPF1,Wake-up flag for WKUP1 pin before enable" "0: No wake-up event occurred,1: A wake-up event was received from WKUP1 pin." group.long 0x58++0x3 line.long 0x0 "PWR_WKUPEPR,PWR wake-up enable and polarity register" bitfld.long 0x0 22.--23. "WKUPPUPD4,Wake-up pull configuration for WKUP4 pin" "0: No pulls,1: Pull-up,2: Pull-down,?" bitfld.long 0x0 20.--21. "WKUPPUPD3,Wake-up pull configuration for WKUP3 pin" "0: No pulls,1: Pull-up,2: Pull-down,?" newline bitfld.long 0x0 18.--19. "WKUPPUPD2,Wake-up pull configuration for WKUP2 pin" "0: No pulls,1: Pull-up,2: Pull-down,?" bitfld.long 0x0 16.--17. "WKUPPUPD1,Wake-up pull configuration for WKUP1 pin" "0: No pulls,1: Pull-up,2: Pull-down,?" newline bitfld.long 0x0 11. "WKUPP4,Wake-up polarity bit for WKUP4 pin" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x0 10. "WKUPP3,Wake-up polarity bit for WKUP3 pin" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x0 9. "WKUPP2,Wake-up polarity bit for WKUP2 pin" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" bitfld.long 0x0 8. "WKUPP1,Wake-up polarity bit for WKUP1 pin" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x0 3. "WKUPEN4,Enable WKUP4 pin" "0: An event on WKUP4 pin does not wake up the..,1: A rising or falling edge on WKUP4 pin wakes up.." bitfld.long 0x0 2. "WKUPEN3,Enable WKUP3 pin" "0: An event on WKUP3 pin does not wake up the..,1: A rising or falling edge on WKUP3 pin wakes up.." newline bitfld.long 0x0 1. "WKUPEN2,Enable WKUP2 pin" "0: An event on WKUP2 pin does not wake up the..,1: A rising or falling edge on WKUP2 pin wakes up.." bitfld.long 0x0 0. "WKUPEN1,Enable WKUP1 pin" "0: An event on WKUP1 pin does not wake up the..,1: A rising or falling edge on WKUP1 pin wakes up.." group.long 0x70++0x7 line.long 0x0 "PWR_SECCFGR,PWR security configuration register" bitfld.long 0x0 19. "WKUPSEC4,WKUP4 pin secure protection" "0: Bits related to WKUP4 pin in PWR_WKUPCR..,1: Bits related to WKUP4 pin in PWR_WKUPCR.." bitfld.long 0x0 18. "WKUPSEC3,WKUP3 pin secure protection" "0: Bits related to WKUP3 pin in PWR_WKUPCR..,1: Bits related to WKUP3 pin in PWR_WKUPCR.." newline bitfld.long 0x0 17. "WKUPSEC2,WKUP2 pin secure protection" "0: Bits related to WKUP2 pin in PWR_WKUPCR..,1: Bits related to WKUP2 pin in PWR_WKUPCR.." bitfld.long 0x0 16. "WKUPSEC1,WKUP1 pin secure protection" "0: Bits related to WKUP1 pin in PWR_WKUPCR..,1: Bits related to WKUP1 pin in PWR_WKUPCR.." newline bitfld.long 0x0 7. "SEC7,Peripheral voltage monitor secure protection" "0: PWR_SVMCR1 PWR_SVMCR2 and PWR_SVMCR3 can be read..,1: PWR_SVMCR1 PWR_SVMCR2 and PWR_SVMCR3 can be read.." bitfld.long 0x0 6. "SEC6,CPU power control secure protection" "0: PWR_CPUCR can be read and written with secure or..,1: PWR_CPUCR can be read and written only with.." newline bitfld.long 0x0 5. "SEC5,Backup domain secure protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPCR can be read..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPCR can be read.." bitfld.long 0x0 4. "SEC4,Voltage scaling selection secure protection" "0: PWR_VOSCR can be read and written with secure or..,1: PWR_VOSCR can be read and written only with.." newline bitfld.long 0x0 3. "SEC3,I-TCM D-TCM and I-TCM FLEXMEM low power control secure protection" "0: PWR_CR4 can be read and written with secure or..,1: PWR_CR4 can be read and written only with secure.." bitfld.long 0x0 2. "SEC2,V less than sub>DDCORE less than /sub> monitor secure protection" "0: PWR_CR3 can be read and written with secure or..,1: PWR_CR3 can be read and written only with secure.." newline bitfld.long 0x0 1. "SEC1,Programmable voltage detector secure protection" "0: PWR_CR2 can be read and written with secure or..,1: PWR_CR2 can be read and written only with secure.." bitfld.long 0x0 0. "SEC0,System supply configuration secure protection" "0: PWR_CR1 can be read and written with secure or..,1: PWR_CR1 can be read and written only with secure.." line.long 0x4 "PWR_PRIVCFGR,PWR privilege configuration register" bitfld.long 0x4 19. "WKUPPRIV4,WKUP4 pin privileged protection" "0: Bits related to WKUP4 pin in PWR_WKUPCR..,1: Bits related to WKUP4 pin in PWR_WKUPCR.." bitfld.long 0x4 18. "WKUPPRIV3,WKUP3 pin privileged protection" "0: Bits related to WKUP3 pin in PWR_WKUPCR..,1: Bits related to WKUP3 pin in PWR_WKUPCR.." newline bitfld.long 0x4 17. "WKUPPRIV2,WKUP2 pin privileged protection" "0: Bits related to WKUP2 pin in PWR_WKUPCR..,1: Bits related to WKUP2 pin in PWR_WKUPCR.." bitfld.long 0x4 16. "WKUPPRIV1,WKUP1 pin privileged protection" "0: Bits related to WKUP1 pin in PWR_WKUPCR..,1: Bits related to WKUP1 pin in PWR_WKUPCR.." newline bitfld.long 0x4 7. "PRIV7,Peripheral voltage monitor privileged protection" "0: PWR_SVMCR1 PWR_SVMCR2 and PWR_SVMCR3 can be read..,1: PWR_SVMCR1 PWR_SVMCR2 and PWR_SVMCR3 can be read.." bitfld.long 0x4 6. "PRIV6,CPU power control privileged protection" "0: PWR_CPUCR can be read and written with..,1: PWR_CPUCR can be read and written only with.." newline bitfld.long 0x4 5. "PRIV5,Backup domain privileged protection" "0: PWR_BDCR1 PWR_BDCR2 and PWR_DBPCR can be read..,1: PWR_BDCR1 PWR_BDCR2 and PWR_DBPCR can be read.." bitfld.long 0x4 4. "PRIV4,Voltage scaling selection privileged protection" "0: PWR_VOSCR can be read and written with..,1: PWR_VOSCR can be read and written only with.." newline bitfld.long 0x4 3. "PRIV3,I-TCM D-TCM and I-TCM FLEX MEM low power control privileged protection" "0: PWR_CR4 can be read and written with privileged..,1: PWR_CR4 can be read and written only with.." bitfld.long 0x4 2. "PRIV2,V less than sub>DDCORE less than /sub> monitor privileged protection" "0: PWR_CR3 can be read and written with privileged..,1: PWR_CR3 can be read and written only with.." newline bitfld.long 0x4 1. "PRIV1,Programmable voltage detector privileged protection" "0: PWR_CR2 can be read and written with privileged..,1: PWR_CR2 can be read and written only with.." bitfld.long 0x4 0. "PRIV0,System supply configuration privileged protection" "0: PWR_CR1 can be read and written with privileged..,1: PWR_CR1 can be read and written only with.." tree.end tree.end tree "RAMCFG (SRAM Configuration Controller)" base ad:0x0 tree "RAMCFG" base ad:0x42023000 group.long 0x0++0x3 line.long 0x0 "RAMCFG_AXISRAM1CR,RAMCFG AXISRAM1 control register" bitfld.long 0x0 8. "SRAMER,SRAM erase." "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x8++0x3 line.long 0x0 "RAMCFG_AXISRAM1ISR,RAMCFG AXISRAM1 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x28++0x3 line.long 0x0 "RAMCFG_AXISRAM1ERKEYR,RAMCFG AXISRAM1 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x80++0x3 line.long 0x0 "RAMCFG_AXISRAM2CR,RAMCFG AXISRAM2 control register" bitfld.long 0x0 20. "SRAMSD,Shutdown AXISRAMx" "0: AXISRAMx memory is powered.,1: AXISRAMx memory is in shutdown and its content.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x88++0x3 line.long 0x0 "RAMCFG_AXISRAM2ISR,RAMCFG AXISRAM2 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0xA8++0x3 line.long 0x0 "RAMCFG_AXISRAM2ERKEYR,RAMCFG AXISRAM2 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x100++0x3 line.long 0x0 "RAMCFG_AXISRAM3CR,RAMCFG AXISRAM3 control register" bitfld.long 0x0 20. "SRAMSD,Shutdown AXISRAMx" "0: AXISRAMx memory is powered.,1: AXISRAMx memory is in shutdown and its content.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x108++0x3 line.long 0x0 "RAMCFG_AXISRAM3ISR,RAMCFG AXISRAM3 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x128++0x3 line.long 0x0 "RAMCFG_AXISRAM3ERKEYR,RAMCFG AXISRAM3 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x180++0x3 line.long 0x0 "RAMCFG_AXISRAM4CR,RAMCFG AXISRAM4 control register" bitfld.long 0x0 20. "SRAMSD,Shutdown AXISRAMx" "0: AXISRAMx memory is powered.,1: AXISRAMx memory is in shutdown and its content.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x188++0x3 line.long 0x0 "RAMCFG_AXISRAM4ISR,RAMCFG AXISRAM4 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x1A8++0x3 line.long 0x0 "RAMCFG_AXISRAM4ERKEYR,RAMCFG AXISRAM4 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x200++0x3 line.long 0x0 "RAMCFG_AXISRAM5CR,RAMCFG AXISRAM5 control register" bitfld.long 0x0 20. "SRAMSD,Shutdown AXISRAMx" "0: AXISRAMx memory is powered.,1: AXISRAMx memory is in shutdown and its content.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x208++0x3 line.long 0x0 "RAMCFG_AXISRAM5ISR,RAMCFG AXISRAM5 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x228++0x3 line.long 0x0 "RAMCFG_AXISRAM5ERKEYR,RAMCFG AXISRAM5 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x280++0x3 line.long 0x0 "RAMCFG_AXISRAM6CR,RAMCFG AXISRAM6 control register" bitfld.long 0x0 20. "SRAMSD,Shutdown AXISRAMx" "0: AXISRAMx memory is powered.,1: AXISRAMx memory is in shutdown and its content.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x288++0x3 line.long 0x0 "RAMCFG_AXISRAM6ISR,RAMCFG AXISRAM6 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x2A8++0x3 line.long 0x0 "RAMCFG_AXISRAM6ERKEYR,RAMCFG AXISRAM6 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x300++0x3 line.long 0x0 "RAMCFG_AHBSRAM1CR,RAMCFG AHBSRAM1 control register" bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x308++0x3 line.long 0x0 "RAMCFG_AHBSRAM1ISR,RAMCFG AHBSRAM1 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x328++0x3 line.long 0x0 "RAMCFG_AHBSRAM1ERKEYR,RAMCFG AHBSRAM1 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x380++0x3 line.long 0x0 "RAMCFG_AHBSRAM2CR,RAMCFG AHBSRAM2 control register" bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x388++0x3 line.long 0x0 "RAMCFG_AHBSRAM2ISR,RAMCFG AHBSRAM2 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x3A8++0x3 line.long 0x0 "RAMCFG_AHBSRAM2ERKEYR,RAMCFG AHBSRAM2 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x400++0x3 line.long 0x0 "RAMCFG_VENCRAMCR,RAMCFG VENCRAM control register" bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x408++0x3 line.long 0x0 "RAMCFG_VENCRAMISR,RAMCFG VENCRAM interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x428++0x3 line.long 0x0 "RAMCFG_VENCRAMERKEYR,RAMCFG VENCRAM erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x480++0x7 line.long 0x0 "RAMCFG_BKPSRAMCR,RAMCFG BKPSRAM control register" bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" bitfld.long 0x0 4. "ALE,Address latch enable" "0: Failing address not stored in..,1: Failing address stored in RAMCFG_BKPSRAMESEAR or.." newline bitfld.long 0x0 0. "ECCE,ECC enable" "0: ECC disabled,1: ECC enabled" line.long 0x4 "RAMCFG_BKPSRAMIER,RAMCFG BKPSRAM interrupt enable register" bitfld.long 0x4 1. "DEIE,ECC double error interrupt enable" "0: Double error interrupt disabled,1: Double error interrupt enabled" bitfld.long 0x4 0. "SEIE,ECC single error interrupt enable" "0: Single error interrupt disabled,1: Single error interrupt enabled" rgroup.long 0x488++0x3 line.long 0x0 "RAMCFG_BKPSRAMISR,RAMCFG BKPSRAM interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" bitfld.long 0x0 1. "DED,ECC double-error interrupt enable" "0: No double error,1: Double error detected" newline bitfld.long 0x0 0. "SEC,ECC single error detected" "0: No single error detected,1: Single error detected and corrected" wgroup.long 0x48C++0xB line.long 0x0 "RAMCFG_BKPSRAMESEAR,RAMCFG BKPSRAM single error address register" hexmask.long.word 0x0 0.--10. 1. "ESEA,ECC single error address" line.long 0x4 "RAMCFG_BKPSRAMEDEAR,RAMCFG BKPSRAM double error address register" hexmask.long.word 0x4 0.--10. 1. "EDEA,ECC double error address" line.long 0x8 "RAMCFG_BKPSRAMICR,RAMCFG BKPSRAM interrupt clear register" bitfld.long 0x8 1. "CDED,Clear ECC double-error interrupt" "0,1" bitfld.long 0x8 0. "CSED,Clear ECC single-error interrupt" "0,1" wgroup.long 0x4A4++0x7 line.long 0x0 "RAMCFG_BKPSRAMECCKEYR,RAMCFG BKPSRAM ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECC write protection key" line.long 0x4 "RAMCFG_BKPSRAMERKEYR,RAMCFG BKPSRAM erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x500++0x3 line.long 0x0 "RAMCFG_FLEXRAMCR,RAMCFG FLEXRAM control register" bitfld.long 0x0 24. "DTCMCFG,Configuration of the FLEXMEM D-TCM extension" "0: FLEXMEM D-TCM extension allocated as AXI RAM,1: FLEXMEM D-TCM extension allocated as DTCM" bitfld.long 0x0 16.--17. "ITCMCFG,Configuration of the FLEXMEM I-TCM extension" "0: FLEXMEM I-TCM extension entirely allocated as..,1: First 64 Kbytes (and corresponding ECC)..,2: FLEXMEM I-TCM extension entirely allocated as..,?" newline bitfld.long 0x0 12. "SRAMHWERDIS,SRAM hardware erase disable" "0: Erase operation done after a system reset,1: No erase operation done after a system reset.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x508++0x3 line.long 0x0 "RAMCFG_FLEXRAMISR,RAMCFG FLEXRAM interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x528++0x3 line.long 0x0 "RAMCFG_FLEXRAMERKEYR,RAMCFG FLEXRAM erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end tree "RAMCFG_S" base ad:0x52023000 group.long 0x0++0x3 line.long 0x0 "RAMCFG_AXISRAM1CR,RAMCFG AXISRAM1 control register" bitfld.long 0x0 8. "SRAMER,SRAM erase." "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x8++0x3 line.long 0x0 "RAMCFG_AXISRAM1ISR,RAMCFG AXISRAM1 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x28++0x3 line.long 0x0 "RAMCFG_AXISRAM1ERKEYR,RAMCFG AXISRAM1 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x80++0x3 line.long 0x0 "RAMCFG_AXISRAM2CR,RAMCFG AXISRAM2 control register" bitfld.long 0x0 20. "SRAMSD,Shutdown AXISRAMx" "0: AXISRAMx memory is powered.,1: AXISRAMx memory is in shutdown and its content.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x88++0x3 line.long 0x0 "RAMCFG_AXISRAM2ISR,RAMCFG AXISRAM2 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0xA8++0x3 line.long 0x0 "RAMCFG_AXISRAM2ERKEYR,RAMCFG AXISRAM2 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x100++0x3 line.long 0x0 "RAMCFG_AXISRAM3CR,RAMCFG AXISRAM3 control register" bitfld.long 0x0 20. "SRAMSD,Shutdown AXISRAMx" "0: AXISRAMx memory is powered.,1: AXISRAMx memory is in shutdown and its content.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x108++0x3 line.long 0x0 "RAMCFG_AXISRAM3ISR,RAMCFG AXISRAM3 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x128++0x3 line.long 0x0 "RAMCFG_AXISRAM3ERKEYR,RAMCFG AXISRAM3 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x180++0x3 line.long 0x0 "RAMCFG_AXISRAM4CR,RAMCFG AXISRAM4 control register" bitfld.long 0x0 20. "SRAMSD,Shutdown AXISRAMx" "0: AXISRAMx memory is powered.,1: AXISRAMx memory is in shutdown and its content.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x188++0x3 line.long 0x0 "RAMCFG_AXISRAM4ISR,RAMCFG AXISRAM4 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x1A8++0x3 line.long 0x0 "RAMCFG_AXISRAM4ERKEYR,RAMCFG AXISRAM4 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x200++0x3 line.long 0x0 "RAMCFG_AXISRAM5CR,RAMCFG AXISRAM5 control register" bitfld.long 0x0 20. "SRAMSD,Shutdown AXISRAMx" "0: AXISRAMx memory is powered.,1: AXISRAMx memory is in shutdown and its content.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x208++0x3 line.long 0x0 "RAMCFG_AXISRAM5ISR,RAMCFG AXISRAM5 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x228++0x3 line.long 0x0 "RAMCFG_AXISRAM5ERKEYR,RAMCFG AXISRAM5 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x280++0x3 line.long 0x0 "RAMCFG_AXISRAM6CR,RAMCFG AXISRAM6 control register" bitfld.long 0x0 20. "SRAMSD,Shutdown AXISRAMx" "0: AXISRAMx memory is powered.,1: AXISRAMx memory is in shutdown and its content.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x288++0x3 line.long 0x0 "RAMCFG_AXISRAM6ISR,RAMCFG AXISRAM6 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x2A8++0x3 line.long 0x0 "RAMCFG_AXISRAM6ERKEYR,RAMCFG AXISRAM6 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x300++0x3 line.long 0x0 "RAMCFG_AHBSRAM1CR,RAMCFG AHBSRAM1 control register" bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x308++0x3 line.long 0x0 "RAMCFG_AHBSRAM1ISR,RAMCFG AHBSRAM1 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x328++0x3 line.long 0x0 "RAMCFG_AHBSRAM1ERKEYR,RAMCFG AHBSRAM1 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x380++0x3 line.long 0x0 "RAMCFG_AHBSRAM2CR,RAMCFG AHBSRAM2 control register" bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x388++0x3 line.long 0x0 "RAMCFG_AHBSRAM2ISR,RAMCFG AHBSRAM2 interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x3A8++0x3 line.long 0x0 "RAMCFG_AHBSRAM2ERKEYR,RAMCFG AHBSRAM2 erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x400++0x3 line.long 0x0 "RAMCFG_VENCRAMCR,RAMCFG VENCRAM control register" bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x408++0x3 line.long 0x0 "RAMCFG_VENCRAMISR,RAMCFG VENCRAM interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x428++0x3 line.long 0x0 "RAMCFG_VENCRAMERKEYR,RAMCFG VENCRAM erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x480++0x7 line.long 0x0 "RAMCFG_BKPSRAMCR,RAMCFG BKPSRAM control register" bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" bitfld.long 0x0 4. "ALE,Address latch enable" "0: Failing address not stored in..,1: Failing address stored in RAMCFG_BKPSRAMESEAR or.." newline bitfld.long 0x0 0. "ECCE,ECC enable" "0: ECC disabled,1: ECC enabled" line.long 0x4 "RAMCFG_BKPSRAMIER,RAMCFG BKPSRAM interrupt enable register" bitfld.long 0x4 1. "DEIE,ECC double error interrupt enable" "0: Double error interrupt disabled,1: Double error interrupt enabled" bitfld.long 0x4 0. "SEIE,ECC single error interrupt enable" "0: Single error interrupt disabled,1: Single error interrupt enabled" rgroup.long 0x488++0x3 line.long 0x0 "RAMCFG_BKPSRAMISR,RAMCFG BKPSRAM interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" bitfld.long 0x0 1. "DED,ECC double-error interrupt enable" "0: No double error,1: Double error detected" newline bitfld.long 0x0 0. "SEC,ECC single error detected" "0: No single error detected,1: Single error detected and corrected" wgroup.long 0x48C++0xB line.long 0x0 "RAMCFG_BKPSRAMESEAR,RAMCFG BKPSRAM single error address register" hexmask.long.word 0x0 0.--10. 1. "ESEA,ECC single error address" line.long 0x4 "RAMCFG_BKPSRAMEDEAR,RAMCFG BKPSRAM double error address register" hexmask.long.word 0x4 0.--10. 1. "EDEA,ECC double error address" line.long 0x8 "RAMCFG_BKPSRAMICR,RAMCFG BKPSRAM interrupt clear register" bitfld.long 0x8 1. "CDED,Clear ECC double-error interrupt" "0,1" bitfld.long 0x8 0. "CSED,Clear ECC single-error interrupt" "0,1" wgroup.long 0x4A4++0x7 line.long 0x0 "RAMCFG_BKPSRAMECCKEYR,RAMCFG BKPSRAM ECC key register" hexmask.long.byte 0x0 0.--7. 1. "ECCKEY,ECC write protection key" line.long 0x4 "RAMCFG_BKPSRAMERKEYR,RAMCFG BKPSRAM erase key register" hexmask.long.byte 0x4 0.--7. 1. "ERASEKEY,Erase write protection key" group.long 0x500++0x3 line.long 0x0 "RAMCFG_FLEXRAMCR,RAMCFG FLEXRAM control register" bitfld.long 0x0 24. "DTCMCFG,Configuration of the FLEXMEM D-TCM extension" "0: FLEXMEM D-TCM extension allocated as AXI RAM,1: FLEXMEM D-TCM extension allocated as DTCM" bitfld.long 0x0 16.--17. "ITCMCFG,Configuration of the FLEXMEM I-TCM extension" "0: FLEXMEM I-TCM extension entirely allocated as..,1: First 64 Kbytes (and corresponding ECC)..,2: FLEXMEM I-TCM extension entirely allocated as..,?" newline bitfld.long 0x0 12. "SRAMHWERDIS,SRAM hardware erase disable" "0: Erase operation done after a system reset,1: No erase operation done after a system reset.." bitfld.long 0x0 8. "SRAMER,SRAM erase" "0: No erase operation ongoing,1: Erase operation ongoing" rgroup.long 0x508++0x3 line.long 0x0 "RAMCFG_FLEXRAMISR,RAMCFG FLEXRAM interrupt status register" bitfld.long 0x0 8. "SRAMBUSY,SRAM busy with erase operation" "0: No erase operation ongoing,1: Erase operation ongoing" wgroup.long 0x528++0x3 line.long 0x0 "RAMCFG_FLEXRAMERKEYR,RAMCFG FLEXRAM erase key register" hexmask.long.byte 0x0 0.--7. 1. "ERASEKEY,Erase write protection key" tree.end tree.end tree "RCC (Reset and Clock Control)" base ad:0x0 tree "RCC" base ad:0x46028000 group.long 0x0++0x3 line.long 0x0 "RCC_CR,RCC control register" bitfld.long 0x0 11. "PLL4ON,PLL4 enable in Run/Sleep mode." "0: PLL4 is OFF (default after reset),1: PLL4 is ON" newline bitfld.long 0x0 10. "PLL3ON,PLL3 enable in Run/Sleep mode." "0: PLL3 is OFF (default after reset),1: PLL3 is ON" newline bitfld.long 0x0 9. "PLL2ON,PLL2 enable in Run/Sleep mode." "0: PLL2 is OFF (default after reset),1: PLL2 is ON" newline bitfld.long 0x0 8. "PLL1ON,PLL1 enable in Run/Sleep mode." "0: PLL1 is OFF (default after reset),1: PLL1 is ON" newline bitfld.long 0x0 4. "HSEON,HSE oscillator enable in Run/Sleep mode." "0: HSE is OFF (default after reset),1: HSE is ON" newline bitfld.long 0x0 3. "HSION,HSI oscillator enable in Run/Sleep mode." "0: HSI is OFF,1: HSI is ON (default after reset)" newline bitfld.long 0x0 2. "MSION,MSI oscillator enable in Run/Sleep mode." "0: MSI is OFF (default after reset),1: MSI is ON" newline bitfld.long 0x0 1. "LSEON,LSE oscillator enable in Run/Sleep mode." "0: LSE is OFF (default after reset),1: LSE is ON" newline bitfld.long 0x0 0. "LSION,LSI oscillator enable in Run/Sleep mode." "0: LSI is OFF (default after reset),1: LSI is ON" rgroup.long 0x4++0x3 line.long 0x0 "RCC_SR,RCC status register" bitfld.long 0x0 11. "PLL4RDY,PLL4 clock ready flag" "0: PLL4 unlocked (default after reset),1: PLL4 locked" newline bitfld.long 0x0 10. "PLL3RDY,PLL3 clock ready flag" "0: PLL3 unlocked (default after reset),1: PLL3 locked" newline bitfld.long 0x0 9. "PLL2RDY,PLL2 clock ready flag" "0: PLL2 unlocked (default after reset),1: PLL2 locked" newline bitfld.long 0x0 8. "PLL1RDY,PLL1 clock ready flag" "0: PLL1 unlocked (default after reset),1: PLL1 locked" newline bitfld.long 0x0 4. "HSERDY,HSE clock ready flag" "0: HSE is not ready (default after reset),1: HSE is ready" newline bitfld.long 0x0 3. "HSIRDY,HSI clock ready flag" "0: HSI is not ready,1: HSI is ready (default after reset)" newline bitfld.long 0x0 2. "MSIRDY,MSI clock ready flag" "0: MSI is not ready (default after reset),1: MSI is ready" newline bitfld.long 0x0 1. "LSERDY,LSE clock ready flag" "0: LSE is not ready (default after reset),1: LSE is ready" newline bitfld.long 0x0 0. "LSIRDY,LSI clock ready flag" "0: LSI is not ready (default after reset),1: LSI is ready" group.long 0x8++0x3 line.long 0x0 "RCC_STOPCR,RCC Stop mode control register" bitfld.long 0x0 3. "HSISTOPEN,HSI oscillator enable in Stop mode." "0: HSI is OFF,1: HSI is ON (default after reset)" newline bitfld.long 0x0 2. "MSISTOPEN,MSI oscillator enable in Stop mode." "0: MSI is OFF (default after reset),1: MSI is ON" newline bitfld.long 0x0 1. "LSESTOPEN,LSE oscillator enable in Stop mode." "0: LSE is OFF (default after reset),1: LSE is ON" newline bitfld.long 0x0 0. "LSISTOPEN,LSI oscillator enable in Stop mode." "0: LSI is OFF (default after reset),1: LSI is ON" group.long 0x20++0x7 line.long 0x0 "RCC_CFGR1,RCC configuration register 1" rbitfld.long 0x0 28.--29. "SYSSWS,System clock switch status" "0: hsi_ck selected as system clock (default after..,1: msi_ck selected as system clock,2: hse_ck selected as system clock,3: ic2_ck selected as system clock" newline bitfld.long 0x0 24.--25. "SYSSW,System clock switch selection" "0: hsi_ck selected as system clock (default after..,1: msi_ck selected as system clock,2: hse_ck selected as system clock,3: ic2_ck selected as system clock" newline rbitfld.long 0x0 20.--21. "CPUSWS,CPU clock switch status" "0: hsi_ck selected as system clock (default after..,1: msi_ck selected as system clock,2: hse_ck selected as system clock,3: ic1_ck selected as system clock" newline bitfld.long 0x0 16.--17. "CPUSW,CPU clock switch selection" "0: hsi_ck selected as system clock (default after..,1: msi_ck selected as system clock,2: hse_ck selected as system clock,3: ic1_ck selected as system clock" newline bitfld.long 0x0 0. "STOPWUCK,System clock selection after a wake up from system Stop." "0: HSI selected as wake up clock from system Stop..,1: CSI selected as wake up clock from system Stop" line.long 0x4 "RCC_CFGR2,RCC configuration register 2" bitfld.long 0x4 24.--25. "TIMPRE,Timers clocks prescaler selection" "0: timg_ck = sys_bus_ck (default after reset),1: timg_ck = sys_bus_ck / 2,2: timg_ck = sys_bus_ck / 4,?" newline bitfld.long 0x4 20.--22. "HPRE,AHB clock prescaler" "0: sys_bus2_ck= sys_bus_ck,1: sys_bus2_ck = sys_bus_ck / 2 (default after reset),2: sys_bus2_ck= sys_bus_ck / 4,3: sys_bus2_ck = sys_bus_ck / 8,4: sys_bus2_ck = sys_bus_ck / 16,5: sys_bus2_ck = sys_bus_ck / 32,6: sys_bus2_ck = sys_bus_ck / 64,7: sys_bus2_ck = sys_bus_ck / 128" newline bitfld.long 0x4 16.--18. "PPRE5,CPU domain APB5 prescaler" "0: rcc_pclk5 = sys_bus2_ck (default after reset),1: rcc_pclk5 = sys_bus2_ck / 2,2: rcc_pclk1 = sys_bus2_ck / 4,3: rcc_pclk1 = sys_bus2_ck / 8,4: rcc_pclk1 = sys_bus2_ck / 16,5: rcc_pclk1 = sys_bus2_ck / 32,6: rcc_pclk1 = sys_bus2_ck / 64,7: rcc_pclk1 = sys_bus2_ck / 128" newline bitfld.long 0x4 12.--14. "PPRE4,CPU domain APB4 prescaler" "0: rcc_pclk4 = sys_bus2_ck (default after reset),1: rcc_pclk4 = sys_bus2_ck / 2,2: rcc_pclk1 = sys_bus2_ck / 4,3: rcc_pclk1 = sys_bus2_ck / 8,4: rcc_pclk1 = sys_bus2_ck / 16,5: rcc_pclk1 = sys_bus2_ck / 32,6: rcc_pclk1 = sys_bus2_ck / 64,7: rcc_pclk1 = sys_bus2_ck / 128" newline bitfld.long 0x4 4.--6. "PPRE2,CPU domain APB2 prescaler" "0: rcc_pclk2 = sys_bus2_ck (default after reset),1: rcc_pclk2 = sys_bus2_ck / 2,2: rcc_pclk1 = sys_bus2_ck / 4,3: rcc_pclk1 = sys_bus2_ck / 8,4: rcc_pclk1 = sys_bus2_ck / 16,5: rcc_pclk1 = sys_bus2_ck / 32,6: rcc_pclk1 = sys_bus2_ck / 64,7: rcc_pclk1 = sys_bus2_ck / 128" newline bitfld.long 0x4 0.--2. "PPRE1,CPU domain APB1 prescaler" "0: rcc_pclk1 = sys_bus2_ck (default after reset),1: rcc_pclk1 = sys_bus2_ck / 2,2: rcc_pclk1 = sys_bus2_ck / 4,3: rcc_pclk1 = sys_bus2_ck / 8,4: rcc_pclk1 = sys_bus2_ck / 16,5: rcc_pclk1 = sys_bus2_ck / 32,6: rcc_pclk1 = sys_bus2_ck / 64,7: rcc_pclk1 = sys_bus2_ck / 128" rgroup.long 0x28++0x3 line.long 0x0 "RCC_CKPROTR,RCC clock protection register" bitfld.long 0x0 28.--29. "FMCSELS,FMC clock selection current status" "0: hclk5 selected as FMC clock (default after reset),1: per_ck selected as FMC clock,2: ic3_ck selected as FMC clock,3: ic4_ck selected as FMC clock" newline bitfld.long 0x0 24.--25. "XSPI1SELS,XSPI1 clock selection current status" "0: hclk5 selected as XSPI1 clock (default after..,1: per_ck selected as XSPI1 clock,2: ic3_ck selected as XSPI1 clock,3: ic4_ck selected as XSPI1 clock" newline bitfld.long 0x0 20.--21. "XSPI2SELS,XSPI2 clock selection current status" "0: hclk5 selected as XSPI2 clock (default after..,1: per_ck selected as XSPI2 clock,2: ic3_ck selected as XSPI2 clock,3: ic4_ck selected as XSPI2 clock" newline bitfld.long 0x0 16.--17. "XSPI3SELS,XSPI3 clock selection current status" "0: hclk5 selected as XSPI3 clock (default after..,1: per_ck selected as XSPI3 clock,2: ic3_ck selected as XSPI3 clock,3: ic4_ck selected as XSPI3 clock" group.long 0x2C++0xB line.long 0x0 "RCC_BDCR,RCC backup domain protection register" bitfld.long 0x0 31. "VSWRST,VSW domain software reset." "0: VSW domain is not reset (default after reset),1: VSW domain is reset" line.long 0x4 "RCC_HWRSR,RCC reset status register for hardware" rbitfld.long 0x4 30. "LPWRRSTF,Illegal Stop or Standby flag." "0: no illegal reset occurred (default after..,1: illegal Stop or Standby reset occurred" newline rbitfld.long 0x4 28. "WWDGRSTF,Window watchdog reset flag" "0: no Window Watchdog Reset occurred from WWDG..,1: Window Watchdog Reset occurred from WWDG" newline rbitfld.long 0x4 26. "IWDGRSTF,Independent Watchdog reset flag." "0: no Independent Watchdog Reset occurred (default..,1: Independent Watchdog Reset occurred" newline rbitfld.long 0x4 24. "SFTRSTF,Software system reset flag (1)" "0: no Software System reset occurred (default after..,1: a Software System reset has been generated by.." newline rbitfld.long 0x4 23. "PORRSTF,POR/PDR flag." "0: no POR/PDR reset occurred,1: POR/PDR reset occurred (default after power-on.." newline rbitfld.long 0x4 22. "PINRSTF,Pin reset flag (NRST)" "0: no reset from pin occurred,1: Reset from Pin occurred (default after power-on.." newline rbitfld.long 0x4 21. "BORRSTF,BOR flag" "0: no BOR occurred,1: BOR occurred (default after power-on reset)" newline rbitfld.long 0x4 17. "LCKRSTF,CPU lockup reset flag." "0: No reset from CPU lockup occurred,1: Reset from CPU lockup occurred" newline bitfld.long 0x4 16. "RMVF,Remove reset flag" "0: clear of the reset flags not activated (default..,1: clear the value of the reset flags" line.long 0x8 "RCC_RSR,RCC reset register" rbitfld.long 0x8 30. "LPWRRSTF,Illegal Stop or Standby flag." "0: no illegal reset occurred (default after..,1: illegal Stop or Standby reset occurred" newline rbitfld.long 0x8 28. "WWDGRSTF,Window Watchdog reset flag" "0: no Window Watchdog reset occurred from WWDG..,1: Window Watchdog reset occurred from WWDG" newline rbitfld.long 0x8 26. "IWDGRSTF,Independent Watchdog reset flag." "0: no Independent Watchdog reset occurred (default..,1: Independent Watchdog reset occurred" newline rbitfld.long 0x8 24. "SFTRSTF,Software System reset flag (1)" "0: no Software System reset occurred (default after..,1: a Software System reset has been generated by.." newline rbitfld.long 0x8 23. "PORRSTF,POR/PDR flag." "0: no POR/PDR reset occurred,1: POR/PDR reset occurred (default after power-on.." newline rbitfld.long 0x8 22. "PINRSTF,Pin reset flag (NRST)" "0: no reset from Pin occurred,1: Reset from Pin occurred (default after power-on.." newline rbitfld.long 0x8 21. "BORRSTF,BOR flag" "0: no BOR occurred,1: BOR occurred (default after power-on reset)" newline rbitfld.long 0x8 17. "LCKRSTF,CPU lockup reset flag." "0: No reset from CPU lockup occurred,1: Reset from CPU lockup occurred" newline bitfld.long 0x8 16. "RMVF,Remove reset flag" "0: clear of the reset flags not activated (default..,1: clear the value of the reset flags" group.long 0x40++0xF line.long 0x0 "RCC_LSECFGR,RCC LSE configuration register" bitfld.long 0x0 18.--19. "LSEDRV,LSE oscillator driving capability" "0: Lowest drive (default after reset),1: Medium low drive,2: Medium high drive,3: Highest drive" newline bitfld.long 0x0 17. "LSEGFON,LSE clock glitch filter enable" "0: LSE clock glitch filter is disabled (default..,1: LSE clock glitch filter is enabled" newline bitfld.long 0x0 16. "LSEEXT,LSE clock type in Bypass mode" "0: LSE in analog mode (default after reset),1: LSE in digital mode" newline bitfld.long 0x0 15. "LSEBYP,LSE clock bypass" "0: LSE oscillator not bypassed (default after reset),1: LSE oscillator bypassed with an external clock" newline rbitfld.long 0x0 9. "LSECSSD,LSE clock security system (CSS) failure detection" "0: No failure detected on the oscillator (default..,1: Failure detected on the oscillator" newline bitfld.long 0x0 8. "LSECSSRA,LSE clock security system (CSS) re-arm function" "0: Writing 0 has no effect (default after reset),1: Writing 1 generates a re-arm pulse for the.." newline bitfld.long 0x0 7. "LSECSSON,LSE clock security system (CSS) enable" "0: clock Security System on the LSE oscillator OFF..,1: clock Security System on the LSE oscillator ON" line.long 0x4 "RCC_MSICFGR,RCC MSI configuration register" hexmask.long.byte 0x4 23.--30. 1. "MSICAL,MSI clock calibration" newline hexmask.long.byte 0x4 16.--20. 1. "MSITRIM,MSI clock trimming" newline bitfld.long 0x4 9. "MSIFREQSEL,MSI oscillator frequency select" "0: MSI oscillator frequency is 4 MHz (default after..,1: MSI oscillator frequency is 16 MHz" line.long 0x8 "RCC_HSICFGR,RCC HSI configuration register" hexmask.long.word 0x8 23.--31. 1. "HSICAL,HSI clock calibration" newline hexmask.long.byte 0x8 16.--22. 1. "HSITRIM,HSI clock trimming" newline bitfld.long 0x8 7.--8. "HSIDIV,HSI clock divider" "0: hsi_ck = hsi_osc_ck (default after reset),1: hsi_ck = hsi_osc_ck / 2,?,?" line.long 0xC "RCC_HSIMCR,RCC HSI monitor control register" bitfld.long 0xC 31. "HSIMONEN,HSI clock period monitor enable" "0: Writing '0' disables the HSI clock period..,1: Writing '1' enables the HSI clock period.." newline hexmask.long.byte 0xC 16.--21. 1. "HSIDEV,HSI clock count deviation value" newline hexmask.long.word 0xC 0.--10. 1. "HSIREF,HSI clock cycle counter reference value." rgroup.long 0x50++0x3 line.long 0x0 "RCC_HSIMSR,RCC HSI monitor status register" hexmask.long.word 0x0 0.--10. 1. "HSIVAL,HSI clock cycle counter measured value." group.long 0x54++0x3 line.long 0x0 "RCC_HSECFGR,RCC HSE configuration register" bitfld.long 0x0 18.--19. "HSEDRV,HSE oscillator driving capability" "0: Lowest drive (default after reset),1: Medium low drive,2: Medium high drive,3: Highest drive" newline bitfld.long 0x0 17. "HSEGFON,HSE clock glitch filter enable" "0: LSE clock glitch filter is disabled (default..,1: LSE clock glitch filter is enabled" newline bitfld.long 0x0 16. "HSEEXT,HSE clock type in Bypass mode" "0: HSE in analog mode (default after reset),1: HSE in digital mode" newline bitfld.long 0x0 15. "HSEBYP,HSE clock bypass" "0: HSE oscillator not bypassed (default after reset),1: HSE oscillator bypassed with an external clock" newline hexmask.long.byte 0x0 11.--14. 1. "HSECSSBPRE,HSE clock security system (CSS) bypass divider" newline bitfld.long 0x0 10. "HSECSSBYP,HSE clock security system (CSS) bypass enable" "0: clock Security System Bypass of the HSE..,1: clock Security System Bypass on the HSE.." newline rbitfld.long 0x0 9. "HSECSSD,HSE clock security system (CSS) failure detection" "0: No failure detected on the oscillator (default..,1: Failure detected on the oscillator" newline bitfld.long 0x0 8. "HSECSSRA,HSE clock security system (CSS) re-arm function" "0: Writing 0 has no effect (default after reset),1: Writing 1 generates a re-arm pulse for the.." newline bitfld.long 0x0 7. "HSECSSON,HSE clock security system (CSS) enable" "0: clock Security System on the HSE oscillator OFF..,1: clock Security System on the HSE oscillator ON" newline bitfld.long 0x0 6. "HSEDIV2BYP,HSE div2 oscillator clock in Bypass mode" "0: HSE: hse_div2_osc_ck = hse_osc_ck/2 (default..,1: HSE: hse_div2_osc_ck = hse_osc_ck" group.long 0x80++0xB line.long 0x0 "RCC_PLL1CFGR1,RCC PLL1 configuration register 1" bitfld.long 0x0 28.--30. "PLL1SEL,PLL1 source selection of the reference clock" "0: hsi_ck selected as reference clock,1: msi_ck selected as reference clock,2: hse_ck selected as reference clock,3: I2S_CKIN selected as reference clock,?,?,?,?" newline bitfld.long 0x0 27. "PLL1BYP,PLL1 bypass" "0: PLL output is driven by the VCO via the optional..,1: PLL output is bypassed and driven by the PLL.." newline hexmask.long.byte 0x0 20.--25. 1. "PLL1DIVM,PLL1 reference input clock divide frequency ratio" newline hexmask.long.word 0x0 8.--19. 1. "PLL1DIVN,PLL1 Integer part for the VCO multiplication factor" line.long 0x4 "RCC_PLL1CFGR2,RCC PLL1 configuration register 2" hexmask.long.tbyte 0x4 0.--23. 1. "PLL1DIVNFRAC,PLL1 Fractional part of the VCO multiplication factor" line.long 0x8 "RCC_PLL1CFGR3,RCC PLL1 configuration register 3" bitfld.long 0x8 30. "PLL1PDIVEN,PLL1 post divider POSTDIV1 POSTDIV2 and PLL clock output enable" "0: POSTDIV1 and POSTDIV2 are powered down,1: POSTDIV1 and POSTDIV2 dividers are active.." newline bitfld.long 0x8 27.--29. "PLL1PDIV1,PLL1 VCO frequency divider level 1" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline bitfld.long 0x8 24.--26. "PLL1PDIV2,PLL1 VCO frequency divider level 2" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline hexmask.long.byte 0x8 16.--20. 1. "PLL1MODSPR,PLL1 Modulation Spread depth adjustment" newline hexmask.long.byte 0x8 8.--11. 1. "PLL1MODDIV,PLL1 Modulation Division frequency adjustment" newline bitfld.long 0x8 4. "PLL1MODSPRDW,PLL1 Modulation Spread-Spectrum Down" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x8 3. "PLL1MODDSEN,PLL1 Modulation Spread-Spectrum (and Fractional Divide) enable" "0: Modulation Spread-Spectrum and Fractional Divide..,1: Modulation Spread-Spectrum and Fractional Divide.." newline bitfld.long 0x8 2. "PLL1MODSSDIS,PLL1 Modulation Spread-Spectrum Disable" "0: Modulation Spread-Spectrum is active (and..,1: Fractional Divide is active (and the Modulation.." newline bitfld.long 0x8 1. "PLL1DACEN,PLL1 noise canceling DAC enable in fractional mode." "0: DAC is not active (default after reset),1: DAC is active" newline bitfld.long 0x8 0. "PLL1MODSSRST,PLL1 Modulation Spread Spectrum reset" "0: The PLL1 modulation Spread Spectrum reset module..,1: The PLL1 modulation Spread Spectrum reset module.." group.long 0x90++0xB line.long 0x0 "RCC_PLL2CFGR1,RCC PLL2 configuration register 1" bitfld.long 0x0 28.--30. "PLL2SEL,PLL2 source selection of the reference clock" "0: hsi_ck selected as reference clock,1: msi_ck selected as reference clock,2: hse_ck selected as reference clock,3: I2S_CKIN selected as reference clock,?,?,?,?" newline bitfld.long 0x0 27. "PLL2BYP,PLL2 bypass" "0: PLL output is driven by the VCO via the optional..,1: PLL output is bypassed and driven by the PLL.." newline hexmask.long.byte 0x0 20.--25. 1. "PLL2DIVM,PLL2 reference input clock divide frequency ratio" newline hexmask.long.word 0x0 8.--19. 1. "PLL2DIVN,PLL2 Integer part for the VCO multiplication factor" line.long 0x4 "RCC_PLL2CFGR2,RCC PLL2 configuration register 2" hexmask.long.tbyte 0x4 0.--23. 1. "PLL2DIVNFRAC,PLL2 Fractional part of the VCO multiplication factor" line.long 0x8 "RCC_PLL2CFGR3,RCC PLL2 configuration register 3" bitfld.long 0x8 30. "PLL2PDIVEN,PLL2 post divider POSTDIV1 POSTDIV2 and PLL clock output enable" "0: POSTDIV1 and POSTDIV2 are powered down,1: POSTDIV1 and POSTDIV2 dividers are active.." newline bitfld.long 0x8 27.--29. "PLL2PDIV1,PLL2 VCO frequency divider level 1" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline bitfld.long 0x8 24.--26. "PLL2PDIV2,PLL2 VCO frequency divider level 2" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline hexmask.long.byte 0x8 16.--20. 1. "PLL2MODSPR,PLL2 Modulation Spread depth adjustment" newline hexmask.long.byte 0x8 8.--11. 1. "PLL2MODDIV,PLL2 Modulation Division frequency adjustment" newline bitfld.long 0x8 4. "PLL2MODSPRDW,PLL2 Modulation Down Spread" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x8 3. "PLL2MODDSEN,PLL2 Modulation Spread-Spectrum (and Fractional Divide) enable" "0: Modulation Spread-Spectrum and Fractional Divide..,1: Modulation Spread-Spectrum and Fractional Divide.." newline bitfld.long 0x8 2. "PLL2MODSSDIS,PLL2 Modulation Spread-Spectrum Disable" "0: Modulation Spread-Spectrum is active (and..,1: Fractional Divide is active (and the Modulation.." newline bitfld.long 0x8 1. "PLL2DACEN,PLL2 noise canceling DAC enable in fractional mode." "0: DAC is not active (default after reset),1: DAC is active" newline bitfld.long 0x8 0. "PLL2MODSSRST,PLL2 Modulation Spread Spectrum reset" "0: The PLL2 Modulation Spread Spectrum reset module..,1: The PLL2 Modulation Spread Spectrum reset module.." group.long 0xA0++0xB line.long 0x0 "RCC_PLL3CFGR1,RCC PLL3 configuration register 1" bitfld.long 0x0 28.--30. "PLL3SEL,PLL3 source selection of the reference clock" "0: hsi_ck selected as reference clock,1: msi_ck selected as reference clock,2: hse_ck selected as reference clock,3: I2S_CKIN selected as reference clock,?,?,?,?" newline bitfld.long 0x0 27. "PLL3BYP,PLL3 bypass" "0: PLL output is driven by the VCO via the optional..,1: PLL output is bypassed and driven by the PLL.." newline hexmask.long.byte 0x0 20.--25. 1. "PLL3DIVM,PLL3 reference input clock divide frequency ratio" newline hexmask.long.word 0x0 8.--19. 1. "PLL3DIVN,PLL3 Integer part for the VCO multiplication factor" line.long 0x4 "RCC_PLL3CFGR2,RCC PLL3 configuration register 2" hexmask.long.tbyte 0x4 0.--23. 1. "PLL3DIVNFRAC,PLL3 Fractional part of the VCO multiplication factor" line.long 0x8 "RCC_PLL3CFGR3,RCC PLL3 configuration register 3" bitfld.long 0x8 30. "PLL3PDIVEN,PLL3 post divider POSTDIV1 POSTDIV2 and PLL clock output enable" "0: POSTDIV1 and POSTDIV2 are powered down,1: POSTDIV1 and POSTDIV2 dividers are active.." newline bitfld.long 0x8 27.--29. "PLL3PDIV1,PLL3 VCO frequency divider level 1" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline bitfld.long 0x8 24.--26. "PLL3PDIV2,PLL3 VCO frequency divider level 2" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline hexmask.long.byte 0x8 16.--20. 1. "PLL3MODSPR,PLL3 Modulation Spread depth adjustment" newline hexmask.long.byte 0x8 8.--11. 1. "PLL3MODDIV,PLL3 Modulation Division frequency adjustment" newline bitfld.long 0x8 4. "PLL3MODSPRDW,PLL3 Modulation Down Spread" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x8 3. "PLL3MODDSEN,PLL3 Modulation Spread-Spectrum (and Fractional Divide) enable" "0: Modulation Spread-Spectrum and Fractional Divide..,1: Modulation Spread-Spectrum and Fractional Divide.." newline bitfld.long 0x8 2. "PLL3MODSSDIS,PLL3 Modulation Spread-Spectrum Disable" "0: Modulation Spread-Spectrum is active (and..,1: Fractional Divide is active (and the Modulation.." newline bitfld.long 0x8 1. "PLL3DACEN,PLL3 noise canceling DAC enable in fractional mode." "0: DAC is not active (default after reset),1: DAC is active" newline bitfld.long 0x8 0. "PLL3MODSSRST,PLL3 Modulation Spread Spectrum reset" "0: The PLL3 modulation Spread Spectrum reset module..,1: The PLL3 modulation Spread Spectrum reset module.." group.long 0xB0++0xB line.long 0x0 "RCC_PLL4CFGR1,RCC PLL4 configuration register 1" bitfld.long 0x0 28.--30. "PLL4SEL,PLL4 source selection of the reference clock" "0: hsi_ck selected as reference clock,1: msi_ck selected as reference clock,2: hse_ck selected as reference clock,3: I2S_CKIN selected as reference clock,?,?,?,?" newline bitfld.long 0x0 27. "PLL4BYP,PLL4 bypass" "0: PLL output is driven by the VCO via the optional..,1: PLL output is bypassed and driven by the PLL.." newline hexmask.long.byte 0x0 20.--25. 1. "PLL4DIVM,PLL4 reference input clock divide frequency ratio" newline hexmask.long.word 0x0 8.--19. 1. "PLL4DIVN,PLL4 Integer part for the VCO multiplication factor" line.long 0x4 "RCC_PLL4CFGR2,RCC PLL4 configuration register 2" hexmask.long.tbyte 0x4 0.--23. 1. "PLL4DIVNFRAC,PLL4 Fractional part of the VCO multiplication factor" line.long 0x8 "RCC_PLL4CFGR3,RCC PLL4 configuration register 3" bitfld.long 0x8 30. "PLL4PDIVEN,PLL4 post divider POSTDIV1 POSTDIV2 and PLL clock output enable" "0: POSTDIV1 and POSTDIV2 are powered down,1: POSTDIV1 and POSTDIV2 dividers are active.." newline bitfld.long 0x8 27.--29. "PLL4PDIV1,PLL4 VCO frequency divider level 1" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline bitfld.long 0x8 24.--26. "PLL4PDIV2,PLL4 VCO frequency divider level 2" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline hexmask.long.byte 0x8 16.--20. 1. "PLL4MODSPR,PLL4 Modulation Spread depth adjustment" newline hexmask.long.byte 0x8 8.--11. 1. "PLL4MODDIV,PLL4 Modulation Division frequency adjustment" newline bitfld.long 0x8 4. "PLL4MODSPRDW,PLL4 Modulation Down Spread" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x8 3. "PLL4MODDSEN,PLL4 Modulation Spread-Spectrum (and Fractional Divide) enable" "0: Modulation Spread-Spectrum and Fractional Divide..,1: Modulation Spread-Spectrum and Fractional Divide.." newline bitfld.long 0x8 2. "PLL4MODSSDIS,PLL4 Modulation Spread-Spectrum Disable" "0: Modulation Spread-Spectrum is active (and..,1: Fractional Divide is active (and the Modulation.." newline bitfld.long 0x8 1. "PLL4DACEN,PLL4 noise canceling DAC enable in fractional mode." "0: DAC is not active (default after reset),1: DAC is active" newline bitfld.long 0x8 0. "PLL4MODSSRST,PLL4 Modulation Spread Spectrum reset" "0: The PLL4 modulation Spread Spectrum reset module..,1: The PLL4 modulation Spread Spectrum reset module.." group.long 0xC4++0x4F line.long 0x0 "RCC_IC1CFGR,RCC IC1 configuration register" bitfld.long 0x0 28.--29. "IC1SEL,Divider IC1 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x0 16.--23. 1. "IC1INT,Divider IC1 integer division factor" line.long 0x4 "RCC_IC2CFGR,RCC IC2 configuration register" bitfld.long 0x4 28.--29. "IC2SEL,Divider IC2 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x4 16.--23. 1. "IC2INT,Divider IC2 integer division factor" line.long 0x8 "RCC_IC3CFGR,RCC IC3 configuration register" bitfld.long 0x8 28.--29. "IC3SEL,Divider IC3 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x8 16.--23. 1. "IC3INT,Divider IC3 integer division factor" line.long 0xC "RCC_IC4CFGR,RCC IC4 configuration register" bitfld.long 0xC 28.--29. "IC4SEL,Divider IC4 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0xC 16.--23. 1. "IC4INT,Divider IC4 integer division factor" line.long 0x10 "RCC_IC5CFGR,RCC IC5 configuration register" bitfld.long 0x10 28.--29. "IC5SEL,Divider IC5 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x10 16.--23. 1. "IC5INT,Divider IC5 integer division factor" line.long 0x14 "RCC_IC6CFGR,RCC IC6 configuration register" bitfld.long 0x14 28.--29. "IC6SEL,Divider IC6 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x14 16.--23. 1. "IC6INT,Divider IC6 integer division factor" line.long 0x18 "RCC_IC7CFGR,RCC IC7 configuration register" bitfld.long 0x18 28.--29. "IC7SEL,Divider IC7 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected (default after reset),2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x18 16.--23. 1. "IC7INT,Divider IC7 integer division factor" line.long 0x1C "RCC_IC8CFGR,RCC IC8 configuration register" bitfld.long 0x1C 28.--29. "IC8SEL,Divider IC8 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected (default after reset),2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x1C 16.--23. 1. "IC8INT,Divider IC8 integer division factor" line.long 0x20 "RCC_IC9CFGR,RCC IC9 configuration register" bitfld.long 0x20 28.--29. "IC9SEL,Divider IC9 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected (default after reset),2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x20 16.--23. 1. "IC9INT,Divider IC9 integer division factor" line.long 0x24 "RCC_IC10CFGR,RCC IC10 configuration register" bitfld.long 0x24 28.--29. "IC10SEL,Divider IC10 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected (default after reset),2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x24 16.--23. 1. "IC10INT,Divider IC10 integer division factor" line.long 0x28 "RCC_IC11CFGR,RCC IC11 configuration register" bitfld.long 0x28 28.--29. "IC11SEL,Divider IC11 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x28 16.--23. 1. "IC11INT,Divider IC11 integer division factor" line.long 0x2C "RCC_IC12CFGR,RCC IC12 configuration register" bitfld.long 0x2C 28.--29. "IC12SEL,Divider IC12 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x2C 16.--23. 1. "IC12INT,Divider IC12 integer division factor" line.long 0x30 "RCC_IC13CFGR,RCC IC13 configuration register" bitfld.long 0x30 28.--29. "IC13SEL,Divider IC13 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x30 16.--23. 1. "IC13INT,Divider IC13 integer division factor" line.long 0x34 "RCC_IC14CFGR,RCC IC14 configuration register" bitfld.long 0x34 28.--29. "IC14SEL,Divider IC14 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x34 16.--23. 1. "IC14INT,Divider IC14 integer division factor" line.long 0x38 "RCC_IC15CFGR,RCC IC15 configuration register" bitfld.long 0x38 28.--29. "IC15SEL,Divider IC15 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x38 16.--23. 1. "IC15INT,Divider IC15 integer division factor" line.long 0x3C "RCC_IC16CFGR,RCC IC16 configuration register" bitfld.long 0x3C 28.--29. "IC16SEL,Divider IC16 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x3C 16.--23. 1. "IC16INT,Divider IC16 integer division factor" line.long 0x40 "RCC_IC17CFGR,RCC IC17 configuration register" bitfld.long 0x40 28.--29. "IC17SEL,Divider IC17 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x40 16.--23. 1. "IC17INT,Divider IC17 integer division factor" line.long 0x44 "RCC_IC18CFGR,RCC IC18 configuration register" bitfld.long 0x44 28.--29. "IC18SEL,Divider IC18 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x44 16.--23. 1. "IC18INT,Divider IC18 integer division factor" line.long 0x48 "RCC_IC19CFGR,RCC IC19 configuration register" bitfld.long 0x48 28.--29. "IC19SEL,Divider IC19 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x48 16.--23. 1. "IC19INT,Divider IC19 integer division factor" line.long 0x4C "RCC_IC20CFGR,RCC IC20 configuration register" bitfld.long 0x4C 28.--29. "IC20SEL,Divider IC20 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x4C 16.--23. 1. "IC20INT,Divider IC20 integer division factor" group.long 0x124++0x3 line.long 0x0 "RCC_CIER,RCC clock-source interrupt enable register" bitfld.long 0x0 24. "WKUPIE,CPU wakeup from Stop interrupt enable" "0: Wakeup interrupt disabled (default after reset),1: Wakeup interrupt enabled" newline bitfld.long 0x0 17. "HSECSSIE,HSE clock security system (CSS) interrupt enable" "0: HSE CSS interrupt disabled,1: HSE CSS interrupt enabled (default after reset)" newline bitfld.long 0x0 16. "LSECSSIE,LSE clock security system (CSS) interrupt enable" "0: LSE CSS interrupt disabled (default after reset),1: LSE CSS interrupt enabled" newline bitfld.long 0x0 11. "PLL4RDYIE,PLL4 ready interrupt enable" "0: PLL4 lock interrupt disabled (default after reset),1: PLL4 lock interrupt enabled" newline bitfld.long 0x0 10. "PLL3RDYIE,PLL3 ready interrupt enable" "0: PLL3 lock interrupt disabled (default after reset),1: PLL3 lock interrupt enabled" newline bitfld.long 0x0 9. "PLL2RDYIE,PLL2 ready interrupt enable" "0: PLL2 lock interrupt disabled (default after reset),1: PLL2 lock interrupt enabled" newline bitfld.long 0x0 8. "PLL1RDYIE,PLL1 ready interrupt enable" "0: PLL1 lock interrupt disabled (default after reset),1: PLL1 lock interrupt enabled" newline bitfld.long 0x0 4. "HSERDYIE,HSE ready interrupt enable" "0: HSE ready interrupt disabled (default after reset),1: HSE ready interrupt enabled" newline bitfld.long 0x0 3. "HSIRDYIE,HSI ready interrupt enable" "0: HSI ready interrupt disabled (default after reset),1: HSI ready interrupt enabled" newline bitfld.long 0x0 2. "MSIRDYIE,MSI ready interrupt enable" "0: MSI ready interrupt disabled (default after reset),1: MSI ready interrupt enabled" newline bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0: LSE ready interrupt disabled (default after reset),1: LSE ready interrupt enabled" newline bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0: LSI ready interrupt disabled (default after reset),1: LSI ready interrupt enabled" rgroup.long 0x128++0x3 line.long 0x0 "RCC_CIFR,RCC clock-source interrupt flag register" bitfld.long 0x0 24. "WKUPF,CPU wakeup from Stop interrupt flag" "0: no wakeup interrupt caused by the PWR (default..,1: wakeup interrupt caused by the PWR" newline bitfld.long 0x0 17. "HSECSSF,HSE ready interrupt flag" "0: no clock ready interrupt caused by the HSE..,1: clock ready interrupt caused by the HSE" newline bitfld.long 0x0 16. "LSECSSF,LSE ready interrupt flag" "0: no clock ready interrupt caused by the LSE..,1: clock ready interrupt caused by the LSE" newline bitfld.long 0x0 11. "PLL4RDYF,PLL4 ready interrupt flag" "0: no clock ready interrupt caused by the PLL4..,1: clock ready interrupt caused by the PLL4" newline bitfld.long 0x0 10. "PLL3RDYF,PLL3 ready interrupt flag" "0: no clock ready interrupt caused by the PLL3..,1: clock ready interrupt caused by the PLL3" newline bitfld.long 0x0 9. "PLL2RDYF,PLL2 ready interrupt flag" "0: no clock ready interrupt caused by the PLL2..,1: clock ready interrupt caused by the PLL2" newline bitfld.long 0x0 8. "PLL1RDYF,PLL1 ready interrupt flag" "0: no clock ready interrupt caused by the PLL1..,1: clock ready interrupt caused by the PLL1" newline bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0: no clock ready interrupt caused by the HSE..,1: clock ready interrupt caused by the HSE" newline bitfld.long 0x0 3. "HSIRDYF,HSI ready interrupt flag" "0: no clock ready interrupt caused by the HSI..,1: clock ready interrupt caused by the HSI" newline bitfld.long 0x0 2. "MSIRDYF,MSI ready interrupt flag" "0: no clock ready interrupt caused by the MSI..,1: clock ready interrupt caused by the MSI" newline bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: no clock ready interrupt caused by the LSE..,1: clock ready interrupt caused by the LSE" newline bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: no clock ready interrupt caused by the LSI..,1: clock ready interrupt caused by the LSI" wgroup.long 0x12C++0x3 line.long 0x0 "RCC_CICR,RCC clock-source interrupt Clear register" bitfld.long 0x0 24. "WKUPFC,CPU Wakeup ready interrupt clear" "0: WKUPF not modified (default after reset),1: WKUPF cleared" newline bitfld.long 0x0 17. "HSECSSC,HSE ready interrupt clear" "0: HSECSSF not modified (default after reset),1: HSECSSF cleared" newline bitfld.long 0x0 16. "LSECSSC,LSE ready interrupt clear" "0: LSECSSF not modified (default after reset),1: LSECSSF cleared" newline bitfld.long 0x0 11. "PLL4RDYC,PLL4 ready interrupt clear" "0: PLL4RDYF not modified (default after reset),1: PLL4RDYF cleared" newline bitfld.long 0x0 10. "PLL3RDYC,PLL3 ready interrupt clear" "0: PLL3RDYF not modified (default after reset),1: PLL3RDYF cleared" newline bitfld.long 0x0 9. "PLL2RDYC,PLL2 ready interrupt clear" "0: PLL2RDYF not modified (default after reset),1: PLL2RDYF cleared" newline bitfld.long 0x0 8. "PLL1RDYC,PLL1 ready interrupt clear" "0: PLL1RDYF not modified (default after reset),1: PLL1RDYF cleared" newline bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0: HSERDYF not modified (default after reset),1: HSERDYF cleared" newline bitfld.long 0x0 3. "HSIRDYC,HSI ready interrupt clear" "0: HSIRDYF not modified (default after reset),1: HSIRDYF cleared" newline bitfld.long 0x0 2. "MSIRDYC,MSI ready interrupt clear" "0: MSIRDYF not modified (default after reset),1: MSIRDYF cleared" newline bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: LSERDYF not modified (default after reset),1: LSERDYF cleared" newline bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: LSIRDYF not modified (default after reset),1: LSIRDYF cleared" group.long 0x144++0x23 line.long 0x0 "RCC_CCIPR1,RCC clock configuration for independent peripheral register1" bitfld.long 0x0 20.--21. "DCMIPPSEL,Source selection for the DCMIPP kernel clock" "0: pclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic17_ck selected as reference clock,3: hsi_div_ck selected as reference clock" newline hexmask.long.byte 0x0 8.--15. 1. "ADCPRE,ADC12 Prog clock divider selection (for clock ck_icn_p_adf1)" newline bitfld.long 0x0 4.--6. "ADC12SEL,Source selection for the ADC12 kernel clock" "0: hclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,7: timg_ck selected as reference clock" newline bitfld.long 0x0 0.--2. "ADF1SEL,Source selection for the ADF1 kernel clock" "0: hclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,7: timg_ck selected as reference clock" line.long 0x4 "RCC_CCIPR2,RCC clock configuration for independent peripheral register 2" bitfld.long 0x4 24. "ETH1GTXCLKSEL,Set and reset by software." "0: MII,1: RGMII" newline bitfld.long 0x4 20. "ETH1REFCLKSEL,Set and reset by software" "0,1" newline bitfld.long 0x4 16.--18. "ETH1SEL,Set and reset by software" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--13. "ETH1CLKSEL,Source selection for the ETH1 kernel clock" "0: hclke selected as reference clock,1: per_ck selected as reference clock,2: ic12_ck selected as reference clock,3: hse_ck selected as reference clock" newline rbitfld.long 0x4 8. "ETH1PWRDOWNACK,Set and reset by software." "0: Power-down sequence start not yet acknowledged.,1: Power-down sequence start acknowledged" newline hexmask.long.byte 0x4 4.--7. 1. "ETH1PTPDIV,ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp)" newline bitfld.long 0x4 0.--1. "ETH1PTPSEL,Source selection for the ETH1 kernel clock" "0: hclke selected as reference clock,1: per_ck selected as reference clock,2: ic13_ck selected as reference clock,3: hse_ck selected as reference clock" line.long 0x8 "RCC_CCIPR3,RCC clock configuration for independent peripheral register3" bitfld.long 0x8 8. "DFTSEL,Source selection for the DFT kernel clock" "0: jtag_tck selected as reference clock (default..,1: pclk3 selected as reference clock" newline bitfld.long 0x8 4.--5. "FMCSEL,Source selection for the FMC kernel clock" "0: hclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic3_ck selected as reference clock,3: ic4_ck selected as reference clock" newline bitfld.long 0x8 0.--1. "FDCANSEL,Source selection for the FDCAN kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic19_ck selected as reference clock,3: hse_ck selected as reference clock" line.long 0xC "RCC_CCIPR4,RCC clock configuration for independent peripheral register4" bitfld.long 0xC 24.--25. "LTDCSEL,Source selection for the LTDC kernel clock" "0: pclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic16_ck selected as reference clock,3: hsi_div_ck selected as reference clock" newline bitfld.long 0xC 20.--22. "I3C2SEL,Source selection for the I3C2 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" newline bitfld.long 0xC 16.--18. "I3C1SEL,Source selection for the I3C1 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" newline bitfld.long 0xC 12.--14. "I2C4SEL,Source selection for the I2C4 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" newline bitfld.long 0xC 8.--10. "I2C3SEL,Source selection for the I2C3 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" newline bitfld.long 0xC 4.--6. "I2C2SEL,Source selection for the I2C2 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" newline bitfld.long 0xC 0.--2. "I2C1SEL,Source selection for the I2C1 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" line.long 0x10 "RCC_CCIPR5,RCC lock configuration for independent peripheral register5" bitfld.long 0x10 16.--18. "MDF1SEL,Source selection for the MDF1 kernel clock" "0: hclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,7: timg_ck selected as reference clock" newline hexmask.long.byte 0x10 12.--15. 1. "MCO2PRE,MCO2 Prog clock divider selection (for clock ck_icn_p_mce4)" newline bitfld.long 0x10 8.--10. "MCO2SEL,Source selection for the MCO2 kernel clock" "0: hsi_div_ck selected as reference clock (default..,1: lse_ck selected as reference clock,2: msi_ck selected as reference clock,3: lsi_ck selected as reference clock,4: hse_ck selected as reference clock,5: ic15_ck selected as reference clock,6: ic20_ck selected as reference clock,7: sysb_ck selected as reference clock" newline hexmask.long.byte 0x10 4.--7. 1. "MCO1PRE,MCO1 Prog clock divider selection (for clock ck_icn_p_mce3)" newline bitfld.long 0x10 0.--2. "MCO1SEL,Source selection for the MCO1 kernel clock" "0: hsi_div_ck selected as reference clock (default..,1: lse_ck selected as reference clock,2: msi_ck selected as reference clock,3: lsi_ck selected as reference clock,4: hse_ck selected as reference clock,5: ic5_ck selected as reference clock,6: ic10_ck selected as reference clock,7: sysa_ck selected as reference clock" line.long 0x14 "RCC_CCIPR6,RCC clock configuration for independent peripheral register6" bitfld.long 0x14 24. "OTGPHY2CKREFSEL,Set and reset by software" "0,1" newline bitfld.long 0x14 20.--21. "OTGPHY2SEL,Source selection for the OTGPHY2 kernel clock" "0: hse_ck selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: hse_div2_osc_ck selected as reference clock" newline bitfld.long 0x14 16. "OTGPHY1CKREFSEL,Set and reset by software" "0,1" newline bitfld.long 0x14 12.--13. "OTGPHY1SEL,Source selection for the OTGPHY1 kernel clock" "0: hse_ck selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: hse_div2_osc_ck selected as reference clock" newline bitfld.long 0x14 8.--9. "XSPI3SEL,Source selection for the XSPI3 kernel clock" "0: hclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic3_ck selected as reference clock,3: ic4_ck selected as reference clock" newline bitfld.long 0x14 4.--5. "XSPI2SEL,Source selection for the XSPI2 kernel clock" "0: hclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic3_ck selected as reference clock,3: ic4_ck selected as reference clock" newline bitfld.long 0x14 0.--1. "XSPI1SEL,Source selection for the XSPI1 kernel clock" "0: hclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic3_ck selected as reference clock,3: ic4_ck selected as reference clock" line.long 0x18 "RCC_CCIPR7,RCC clock configuration for independent peripheral register7" bitfld.long 0x18 24.--26. "SAI2SEL,Source selection for the SAI2 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,7: spdif_symb_ck selected as reference clock" newline bitfld.long 0x18 20.--22. "SAI1SEL,Source selection for the SAI1 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,7: spdif_symb_ck selected as reference clock" newline hexmask.long.byte 0x18 12.--17. 1. "RTCPRE,RTC Prog clock divider selection (for clock ck_icn_p_risaf)" newline bitfld.long 0x18 8.--9. "RTCSEL,Source selection for the RTC kernel clock" "?,1: lse_ck selected as reference clock,2: lsi_ck selected as reference clock,3: hse_rtc_ck selected as reference clock" newline bitfld.long 0x18 4.--5. "PSSISEL,Source selection for the PSSI kernel clock" "0: hclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic20_ck selected as reference clock,3: hsi_div_ck selected as reference clock" newline bitfld.long 0x18 0.--2. "PERSEL,Source selection for the PER kernel clock" "0: hsi_ck selected as reference clock,1: msi_ck selected as reference clock,2: hse_ck selected as reference clock,3: ic19_ck selected as reference clock,4: ic5_ck selected as reference clock,5: ic10_ck selected as reference clock,6: ic15_ck selected as reference clock,7: ic20_ck selected as reference clock" line.long 0x1C "RCC_CCIPR8,RCC clock configuration for independent peripheral register8" bitfld.long 0x1C 4.--5. "SDMMC2SEL,Source selection for the SDMMC2 kernel clock" "0: hclku selected as reference clock,1: per_ck selected as reference clock,2: ic4_ck selected as reference clock,3: ic5_ck selected as reference clock" newline bitfld.long 0x1C 0.--1. "SDMMC1SEL,Source selection for the SDMMC1 kernel clock" "0: hclku selected as reference clock,1: per_ck selected as reference clock,2: ic4_ck selected as reference clock,3: ic5_ck selected as reference clock" line.long 0x20 "RCC_CCIPR9,RCC clock configuration for independent peripheral register9" bitfld.long 0x20 24.--26. "SPI6SEL,Source selection for the SPI6 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic8_ck selected as reference clock,3: ic9_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,?" newline bitfld.long 0x20 20.--22. "SPI5SEL,Source selection for the SPI5 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: hse_ck selected as reference clock,?" newline bitfld.long 0x20 16.--18. "SPI4SEL,Source selection for the SPI4 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: hse_ck selected as reference clock,?" newline bitfld.long 0x20 12.--14. "SPI3SEL,Source selection for the SPI3 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic8_ck selected as reference clock,3: ic9_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,?" newline bitfld.long 0x20 8.--10. "SPI2SEL,Source selection for the SPI2 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic8_ck selected as reference clock,3: ic9_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,?" newline bitfld.long 0x20 4.--6. "SPI1SEL,Source selection for the SPI1 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic8_ck selected as reference clock,3: ic9_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,?" newline bitfld.long 0x20 0.--2. "SPDIFRX1SEL,Source selection for the SPDIFRX1 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,?" group.long 0x170++0xB line.long 0x0 "RCC_CCIPR12,RCC clock configuration for independent peripheral register12" bitfld.long 0x0 24.--26. "LPTIM5SEL,Source selection for the LPTIM5 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: lse_ck selected as reference clock,4: lsi_ck selected as reference clock,5: timg_ck selected as reference clock,?,?" newline bitfld.long 0x0 20.--22. "LPTIM4SEL,Source selection for the LPTIM4 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: lse_ck selected as reference clock,4: lsi_ck selected as reference clock,5: timg_ck selected as reference clock,?,?" newline bitfld.long 0x0 16.--18. "LPTIM3SEL,Source selection for the LPTIM3 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: lse_ck selected as reference clock,4: lsi_ck selected as reference clock,5: timg_ck selected as reference clock,?,?" newline bitfld.long 0x0 12.--14. "LPTIM2SEL,Source selection for the LPTIM2 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: lse_ck selected as reference clock,4: lsi_ck selected as reference clock,5: timg_ck selected as reference clock,?,?" newline bitfld.long 0x0 8.--10. "LPTIM1SEL,Source selection for the LPTIM1 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: lse_ck selected as reference clock,4: lsi_ck selected as reference clock,5: timg_ck selected as reference clock,?,?" line.long 0x4 "RCC_CCIPR13,RCC clock configuration for independent peripheral register13" bitfld.long 0x4 28.--30. "UART8SEL,Source selection for the UART8 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 24.--26. "UART7SEL,Source selection for the UART7 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 20.--22. "USART6SEL,Source selection for the USART6 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 16.--18. "UART5SEL,Source selection for the UART5 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 12.--14. "UART4SEL,Source selection for the UART4 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 8.--10. "USART3SEL,Source selection for the USART3 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 4.--6. "USART2SEL,Source selection for the USART2 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 0.--2. "USART1SEL,Source selection for the USART1 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" line.long 0x8 "RCC_CCIPR14,RCC clock configuration for independent peripheral register14" bitfld.long 0x8 8.--10. "LPUART1SEL,Source selection for the LPUART1 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x8 4.--6. "USART10SEL,Source selection for the USART10 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x8 0.--2. "UART9SEL,Source selection for the UART9 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" group.long 0x204++0x2B line.long 0x0 "RCC_BUSRSTR,RCC SoC buses reset register" bitfld.long 0x0 13. "NOCRST,NOC reset" "0: NOC is not under reset (default after reset),1: NOC is under reset" newline bitfld.long 0x0 12. "APB5RST,APB5 reset" "0: APB5 is not under reset (default after reset),1: APB5 is under reset" newline bitfld.long 0x0 11. "APB4RST,APB4 reset" "0: APB4 is not under reset (default after reset),1: APB4 is under reset" newline bitfld.long 0x0 10. "APB3RST,APB3 reset" "0: APB3 is not under reset (default after reset),1: APB3 is under reset" newline bitfld.long 0x0 9. "APB2RST,APB2 reset" "0: APB2 is not under reset (default after reset),1: APB2 is under reset" newline bitfld.long 0x0 8. "APB1RST,APB1 reset" "0: APB1 is not under reset (default after reset),1: APB1 is under reset" newline bitfld.long 0x0 7. "AHB5RST,AHB5 reset" "0: AHB5 is not under reset (default after reset),1: AHB5 is under reset" newline bitfld.long 0x0 6. "AHB4RST,AHB4 reset" "0: AHB4 is not under reset (default after reset),1: AHB4 is under reset" newline bitfld.long 0x0 5. "AHB3RST,AHB3 reset" "0: AHB3 is not under reset (default after reset),1: AHB3 is under reset" newline bitfld.long 0x0 4. "AHB2RST,AHB2 reset" "0: AHB2 is not under reset (default after reset),1: AHB2 is under reset" newline bitfld.long 0x0 3. "AHB1RST,AHB1 reset" "0: AHB1 is not under reset (default after reset),1: AHB1 is under reset" newline bitfld.long 0x0 2. "AHBMRST,AHBM reset" "0: AHBM is not under reset (default after reset),1: AHBM is under reset" newline bitfld.long 0x0 0. "ACLKNRST,ACLKN reset" "0: ACLKN is not under reset (default after reset),1: ACLKN is under reset" line.long 0x4 "RCC_MISCRSTR,RCC miscellaneous configurations reset register" bitfld.long 0x4 8. "SDMMC2DLLRST,SDMMC2DLL reset" "0: SDMMC2DLL is not under reset (default after reset),1: SDMMC2DLL is under reset" newline bitfld.long 0x4 7. "SDMMC1DLLRST,SDMMC1DLL reset" "0: SDMMC1DLL is not under reset (default after reset),1: SDMMC1DLL is under reset" newline bitfld.long 0x4 5. "XSPIPHY2RST,XSPIPHY2 reset" "0: XSPIPHY2 is not under reset (default after reset),1: XSPIPHY2 is under reset" newline bitfld.long 0x4 4. "XSPIPHY1RST,XSPIPHY1 reset" "0: XSPIPHY1 is not under reset (default after reset),1: XSPIPHY1 is under reset" newline bitfld.long 0x4 0. "DBGRST,DBG reset" "0: DBG is not under reset (default after reset),1: DBG is under reset" line.long 0x8 "RCC_MEMRSTR,RCC memories reset register" bitfld.long 0x8 12. "BOOTROMRST,BOOTROM reset" "0: BOOTROM is not under reset (default after reset),1: BOOTROM is under reset" newline bitfld.long 0x8 11. "VENCRAMRST,VENCRAM reset" "0: VENCRAM is not under reset (default after reset),1: VENCRAM is under reset" newline bitfld.long 0x8 10. "NPUCACHERAMRST,NPUCACHERAM reset" "0: NPUCACHERAM is not under reset (default after..,1: NPUCACHERAM is under reset" newline bitfld.long 0x8 9. "FLEXRAMRST,FLEXRAM reset" "0: FLEXRAM is not under reset (default after reset),1: FLEXRAM is under reset" newline bitfld.long 0x8 8. "AXISRAM2RST,AXISRAM2 reset" "0: AXISRAM2 is not under reset (default after reset),1: AXISRAM2 is under reset" newline bitfld.long 0x8 7. "AXISRAM1RST,AXISRAM1 reset" "0: AXISRAM1 is not under reset (default after reset),1: AXISRAM1 is under reset" newline bitfld.long 0x8 5. "AHBSRAM2RST,AHBSRAM2 reset" "0: AHBSRAM2 is not under reset (default after reset),1: AHBSRAM2 is under reset" newline bitfld.long 0x8 4. "AHBSRAM1RST,AHBSRAM1 reset" "0: AHBSRAM1 is not under reset (default after reset),1: AHBSRAM1 is under reset" newline bitfld.long 0x8 3. "AXISRAM6RST,AXISRAM6 reset" "0: AXISRAM6 is not under reset (default after reset),1: AXISRAM6 is under reset" newline bitfld.long 0x8 2. "AXISRAM5RST,AXISRAM5 reset" "0: AXISRAM5 is not under reset (default after reset),1: AXISRAM5 is under reset" newline bitfld.long 0x8 1. "AXISRAM4RST,AXISRAM4reset" "0: AXISRAM4 is not under reset (default after reset),1: AXISRAM4 is under reset" newline bitfld.long 0x8 0. "AXISRAM3RST,AXISRAM3 reset" "0: AXISRAM3 is not under reset (default after reset),1: AXISRAM3 is under reset" line.long 0xC "RCC_AHB1RSTR,RCC AHB1 Reset register" bitfld.long 0xC 5. "ADC12RST,ADC12 reset" "0: ADC12 is not under reset (default after reset),1: ADC12 is under reset" newline bitfld.long 0xC 4. "GPDMA1RST,GPDMA1 reset" "0: GPDMA1 is not under reset (default after reset),1: GPDMA1 is under reset" line.long 0x10 "RCC_AHB2RSTR,RCC AHB2 reset register" bitfld.long 0x10 17. "ADF1RST,ADF1 reset" "0: ADF1 is not under reset (default after reset),1: ADF1 is under reset" newline bitfld.long 0x10 16. "MDF1RST,MDF1 reset" "0: MDF1 is not under reset (default after reset),1: MDF1 is under reset" newline bitfld.long 0x10 12. "RAMCFGRST,RAMCFG reset" "0: RAMCFG is not under reset (default after reset),1: RAMCFG is under reset" line.long 0x14 "RCC_AHB3RSTR,RCC AHB3 reset register" bitfld.long 0x14 10. "IACRST,IAC reset" "0: IAC is not under reset (default after reset),1: IAC is under reset" newline bitfld.long 0x14 8. "PKARST,PKA reset" "0: PKA is not under reset (default after reset),1: PKA is under reset" newline bitfld.long 0x14 4. "SAESRST,SAES reset" "0: SAES is not under reset (default after reset),1: SAES is under reset" newline bitfld.long 0x14 2. "CRYPRST,CRYP reset" "0: CRYP is not under reset (default after reset),1: CRYP is under reset" newline bitfld.long 0x14 1. "HASHRST,HASH reset" "0: HASH is not under reset (default after reset),1: HASH is under reset" newline bitfld.long 0x14 0. "RNGRST,RNG reset" "0: RNG is not under reset (default after reset),1: RNG is under reset" line.long 0x18 "RCC_AHB4RSTR,RCC AHB4 reset register" bitfld.long 0x18 19. "CRCRST,CRC reset" "0: CRC is not under reset (default after reset),1: CRC is under reset" newline bitfld.long 0x18 18. "PWRRST,PWR reset" "0: PWR is not under reset (default after reset),1: PWR is under reset" newline bitfld.long 0x18 16. "GPIOQRST,GPIOQ reset" "0: GPIOQ is not under reset (default after reset),1: GPIOQ is under reset" newline bitfld.long 0x18 15. "GPIOPRST,GPIOP reset" "0: GPIOP is not under reset (default after reset),1: GPIOP is under reset" newline bitfld.long 0x18 14. "GPIOORST,GPIOO reset" "0: GPIOO is not under reset (default after reset),1: GPIOO is under reset" newline bitfld.long 0x18 13. "GPIONRST,GPION reset" "0: GPION is not under reset (default after reset),1: GPION is under reset" newline bitfld.long 0x18 7. "GPIOHRST,GPIOH reset" "0: GPIOH is not under reset (default after reset),1: GPIOH is under reset" newline bitfld.long 0x18 6. "GPIOGRST,GPIOG reset" "0: GPIOG is not under reset (default after reset),1: GPIOG is under reset" newline bitfld.long 0x18 5. "GPIOFRST,GPIOF reset" "0: GPIOF is not under reset (default after reset),1: GPIOF is under reset" newline bitfld.long 0x18 4. "GPIOERST,GPIOE reset" "0: GPIOE is not under reset (default after reset),1: GPIOE is under reset" newline bitfld.long 0x18 3. "GPIODRST,GPIOD reset" "0: GPIOD is not under reset (default after reset),1: GPIOD is under reset" newline bitfld.long 0x18 2. "GPIOCRST,GPIOC reset" "0: GPIOC is not under reset (default after reset),1: GPIOC is under reset" newline bitfld.long 0x18 1. "GPIOBRST,GPIOB reset" "0: GPIOB is not under reset (default after reset),1: GPIOB is under reset" newline bitfld.long 0x18 0. "GPIOARST,GPIOA reset" "0: GPIOA is not under reset (default after reset),1: GPIOA is under reset" line.long 0x1C "RCC_AHB5RSTR,RCC AHB5 reset register" bitfld.long 0x1C 31. "NPURST,NPU reset" "0: NPU is not under reset (default after reset),1: NPU is under reset" newline bitfld.long 0x1C 30. "NPUCACHERST,NPUCACHE reset" "0: NPUCACHE is not under reset (default after reset),1: NPUCACHE is under reset" newline bitfld.long 0x1C 29. "OTG2RST,OTG2 reset" "0: OTG2 is not under reset (default after reset),1: OTG2 is under reset" newline bitfld.long 0x1C 28. "OTGPHY2RST,OTGPHY2 reset" "0: OTGPHY2 is not under reset (default after reset),1: OTGPHY2 is under reset" newline bitfld.long 0x1C 27. "OTGPHY1RST,OTGPHY1 reset" "0: OTGPHY1 is not under reset (default after reset),1: OTGPHY1 is under reset" newline bitfld.long 0x1C 26. "OTG1RST,OTG1 reset" "0: OTG1 is not under reset (default after reset),1: OTG1 is under reset" newline bitfld.long 0x1C 25. "ETH1RST,ETH1 reset" "0: ETH1 is not under reset (default after reset),1: ETH1 is under reset" newline bitfld.long 0x1C 24. "SYSCFGOTGHSPHY2RST,SYSCFGOTGHSPHY2 reset" "0: SYSCFGOTGHSPHY2 is not under reset (default..,1: SYSCFGOTGHSPHY2 is under reset" newline bitfld.long 0x1C 23. "SYSCFGOTGHSPHY1RST,SYSCFGOTGHSPHY1 reset" "0: SYSCFGOTGHSPHY1 is not under reset (default..,1: SYSCFGOTGHSPHY1 is under reset" newline bitfld.long 0x1C 20. "GPURST,GPU reset" "0: GPU is not under reset (default after reset),1: GPU is under reset" newline bitfld.long 0x1C 19. "GFXMMURST,GFXMMU reset" "0: GFXMMU is not under reset (default after reset),1: GFXMMU is under reset" newline bitfld.long 0x1C 18. "MCE4RST,MCE4 reset" "0: MCE4 is not under reset (default after reset),1: MCE4 is under reset" newline bitfld.long 0x1C 17. "XSPI3RST,XSPI3 reset" "0: XSPI3 is not under reset (default after reset),1: XSPI3 is under reset" newline bitfld.long 0x1C 13. "XSPIMRST,XSPIM reset" "0: XSPIM is not under reset (default after reset),1: XSPIM is under reset" newline bitfld.long 0x1C 12. "XSPI2RST,XSPI2 reset" "0: XSPI2 is not under reset (default after reset),1: XSPI2 is under reset" newline bitfld.long 0x1C 8. "SDMMC1RST,SDMMC1 reset" "0: SDMMC1 is not under reset (default after reset),1: SDMMC1 is under reset" newline bitfld.long 0x1C 7. "SDMMC2RST,SDMMC2 reset" "0: SDMMC2 is not under reset (default after reset),1: SDMMC2 is under reset" newline bitfld.long 0x1C 6. "PSSIRST,PSSI reset" "0: PSSI is not under reset (default after reset),1: PSSI is under reset" newline bitfld.long 0x1C 5. "XSPI1RST,XSPI1 reset" "0: XSPI1 is not under reset (default after reset),1: XSPI1 is under reset" newline bitfld.long 0x1C 4. "FMCRST,FMC reset" "0: FMC is not under reset (default after reset),1: FMC is under reset" newline bitfld.long 0x1C 3. "JPEGRST,JPEG reset" "0: JPEG is not under reset (default after reset),1: JPEG is under reset" newline bitfld.long 0x1C 1. "DMA2DRST,DMA2D reset" "0: DMA2D is not under reset (default after reset),1: DMA2D is under reset" newline bitfld.long 0x1C 0. "HPDMA1RST,HPDMA1 reset" "0: HPDMA1 is not under reset (default after reset),1: HPDMA1 is under reset" line.long 0x20 "RCC_APB1LRSTR,RCC APB1L reset register" bitfld.long 0x20 31. "UART8RST,UART8 reset" "0: UART8 is not under reset (default after reset),1: UART8 is under reset" newline bitfld.long 0x20 30. "UART7RST,UART7 reset" "0: UART7 is not under reset (default after reset),1: UART7 is under reset" newline bitfld.long 0x20 25. "I3C2RST,I3C2 reset" "0: I3C2 is not under reset (default after reset),1: I3C2 is under reset" newline bitfld.long 0x20 24. "I3C1RST,I3C1 reset" "0: I3C1 is not under reset (default after reset),1: I3C1 is under reset" newline bitfld.long 0x20 23. "I2C3RST,I2C3 reset" "0: I2C3 is not under reset (default after reset),1: I2C3 is under reset" newline bitfld.long 0x20 22. "I2C2RST,I2C2 reset" "0: I2C2 is not under reset (default after reset),1: I2C2 is under reset" newline bitfld.long 0x20 21. "I2C1RST,I2C1 reset" "0: I2C1 is not under reset (default after reset),1: I2C1 is under reset" newline bitfld.long 0x20 20. "UART5RST,UART5 reset" "0: UART5 is not under reset (default after reset),1: UART5 is under reset" newline bitfld.long 0x20 19. "UART4RST,UART4 reset" "0: UART4 is not under reset (default after reset),1: UART4 is under reset" newline bitfld.long 0x20 18. "USART3RST,USART3 reset" "0: USART3 is not under reset (default after reset),1: USART3 is under reset" newline bitfld.long 0x20 17. "USART2RST,USART2 reset" "0: USART2 is not under reset (default after reset),1: USART2 is under reset" newline bitfld.long 0x20 16. "SPDIFRX1RST,SPDIFRX1 reset" "0: SPDIFRX1 is not under reset (default after reset),1: SPDIFRX1 is under reset" newline bitfld.long 0x20 15. "SPI3RST,SPI3 reset" "0: SPI3 is not under reset (default after reset),1: SPI3 is under reset" newline bitfld.long 0x20 14. "SPI2RST,SPI2 reset" "0: SPI2 is not under reset (default after reset),1: SPI2 is under reset" newline bitfld.long 0x20 13. "TIM11RST,TIM11 reset" "0: TIM11 is not under reset (default after reset),1: TIM11 is under reset" newline bitfld.long 0x20 12. "TIM10RST,TIM10 reset" "0: TIM10 is not under reset (default after reset),1: TIM10 is under reset" newline bitfld.long 0x20 11. "WWDGRST,WWDG reset" "0: WWDG is not under reset (default after reset),1: WWDG is under reset" newline bitfld.long 0x20 9. "LPTIM1RST,LPTIM1 reset" "0: LPTIM1 is not under reset (default after reset),1: LPTIM1 is under reset" newline bitfld.long 0x20 8. "TIM14RST,TIM14 reset" "0: TIM14 is not under reset (default after reset),1: TIM14 is under reset" newline bitfld.long 0x20 7. "TIM13RST,TIM13 reset" "0: TIM13 is not under reset (default after reset),1: TIM13 is under reset" newline bitfld.long 0x20 6. "TIM12RST,TIM12 reset" "0: TIM12 is not under reset (default after reset),1: TIM12 is under reset" newline bitfld.long 0x20 5. "TIM7RST,TIM7 reset" "0: TIM7 is not under reset (default after reset),1: TIM7 is under reset" newline bitfld.long 0x20 4. "TIM6RST,TIM6 reset" "0: TIM6 is not under reset (default after reset),1: TIM6 is under reset" newline bitfld.long 0x20 3. "TIM5RST,TIM5 reset" "0: TIM5 is not under reset (default after reset),1: TIM5 is under reset" newline bitfld.long 0x20 2. "TIM4RST,TIM4 reset" "0: TIM4 is not under reset (default after reset),1: TIM4 is under reset" newline bitfld.long 0x20 1. "TIM3RST,TIM3 reset" "0: TIM3 is not under reset (default after reset),1: TIM3 is under reset" newline bitfld.long 0x20 0. "TIM2RST,TIM2 reset" "0: TIM2 is not under reset (default after reset),1: TIM2 is under reset" line.long 0x24 "RCC_APB1HRSTR,RCC APB1H reset register" bitfld.long 0x24 18. "UCPD1RST,UCPD1 reset" "0: UCPD1 is not under reset (default after reset),1: UCPD1 is under reset" newline bitfld.long 0x24 8. "FDCANRST,FDCAN reset" "0: FDCAN is not under reset (default after reset),1: FDCAN is under reset" newline bitfld.long 0x24 5. "MDIOSRST,MDIOS reset" "0: MDIOS is not under reset (default after reset),1: MDIOS is under reset" line.long 0x28 "RCC_APB2RSTR,RCC APB2 reset register" bitfld.long 0x28 22. "SAI2RST,SAI2 reset" "0: SAI2 is not under reset (default after reset),1: SAI2 is under reset" newline bitfld.long 0x28 21. "SAI1RST,SAI1 reset" "0: SAI1 is not under reset (default after reset),1: SAI1 is under reset" newline bitfld.long 0x28 20. "SPI5RST,SPI5 reset" "0: SPI5 is not under reset (default after reset),1: SPI5 is under reset" newline bitfld.long 0x28 19. "TIM9RST,TIM9 reset" "0: TIM9 is not under reset (default after reset),1: TIM9 is under reset" newline bitfld.long 0x28 18. "TIM17RST,TIM17 reset" "0: TIM17 is not under reset (default after reset),1: TIM17 is under reset" newline bitfld.long 0x28 17. "TIM16RST,TIM16 reset" "0: TIM16 is not under reset (default after reset),1: TIM16 is under reset" newline bitfld.long 0x28 16. "TIM15RST,TIM15 reset" "0: TIM15 is not under reset (default after reset),1: TIM15 is under reset" newline bitfld.long 0x28 15. "TIM18RST,TIM18 reset" "0: TIM18 is not under reset (default after reset),1: TIM18 is under reset" newline bitfld.long 0x28 13. "SPI4RST,SPI4 reset" "0: SPI4 is not under reset (default after reset),1: SPI4 is under reset" newline bitfld.long 0x28 12. "SPI1RST,SPI1 reset" "0: SPI1 is not under reset (default after reset),1: SPI1 is under reset" newline bitfld.long 0x28 7. "USART10RST,USART10 reset" "0: USART10 is not under reset (default after reset),1: USART10 is under reset" newline bitfld.long 0x28 6. "UART9RST,UART9 reset" "0: UART9 is not under reset (default after reset),1: UART9 is under reset" newline bitfld.long 0x28 5. "USART6RST,USART6 reset" "0: USART6 is not under reset (default after reset),1: USART6 is under reset" newline bitfld.long 0x28 4. "USART1RST,USART1 reset" "0: USART1 is not under reset (default after reset),1: USART1 is under reset" newline bitfld.long 0x28 1. "TIM8RST,TIM8 reset" "0: TIM8 is not under reset (default after reset),1: TIM8 is under reset" newline bitfld.long 0x28 0. "TIM1RST,TIM1 reset" "0: TIM1 is not under reset (default after reset),1: TIM1 is under reset" group.long 0x234++0x8B line.long 0x0 "RCC_APB4LRSTR,RCC APB4L reset register" bitfld.long 0x0 31. "SERFRST,SERF reset" "0: SERF is not under reset (default after reset),1: SERF is under reset" newline bitfld.long 0x0 23. "R2GNPURST,R2GNPU reset" "0: R2GNPU is not under reset (default after reset),1: R2GNPU is under reset" newline bitfld.long 0x0 22. "R2GRETRST,R2GRET reset" "0: R2GRET is not under reset (default after reset),1: R2GRET is under reset" newline bitfld.long 0x0 16. "RTCRST,RTC reset" "0: RTC is not under reset (default after reset),1: RTC is under reset" newline bitfld.long 0x0 15. "VREFBUFRST,VREFBUF reset" "0: VREFBUF is not under reset (default after reset),1: VREFBUF is under reset" newline bitfld.long 0x0 12. "LPTIM5RST,LPTIM5 reset" "0: LPTIM5 is not under reset (default after reset),1: LPTIM5 is under reset" newline bitfld.long 0x0 11. "LPTIM4RST,LPTIM4 reset" "0: LPTIM4 is not under reset (default after reset),1: LPTIM4 is under reset" newline bitfld.long 0x0 10. "LPTIM3RST,LPTIM3 reset" "0: LPTIM3 is not under reset (default after reset),1: LPTIM3 is under reset" newline bitfld.long 0x0 9. "LPTIM2RST,LPTIM2 reset" "0: LPTIM2 is not under reset (default after reset),1: LPTIM2 is under reset" newline bitfld.long 0x0 7. "I2C4RST,I2C4 reset" "0: I2C4 is not under reset (default after reset),1: I2C4 is under reset" newline bitfld.long 0x0 5. "SPI6RST,SPI6 reset" "0: SPI6 is not under reset (default after reset),1: SPI6 is under reset" newline bitfld.long 0x0 3. "LPUART1RST,LPUART1 reset" "0: LPUART1 is not under reset (default after reset),1: LPUART1 is under reset" newline bitfld.long 0x0 2. "HDPRST,HDP reset" "0: HDP is not under reset (default after reset),1: HDP is under reset" line.long 0x4 "RCC_APB4HRSTR,RCC APB4H reset register" bitfld.long 0x4 4. "BUSPERFMRST,BUSPERFM reset" "0: BUSPERFM is not under reset (default after reset),1: BUSPERFM is under reset" newline bitfld.long 0x4 2. "DTSRST,DTS reset" "0: DTS is not under reset (default after reset),1: DTS is under reset" newline bitfld.long 0x4 0. "SYSCFGRST,SYSCFG reset" "0: SYSCFG is not under reset (default after reset),1: SYSCFG is under reset" line.long 0x8 "RCC_APB5RSTR,RCC APB5 reset register" bitfld.long 0x8 6. "CSIRST,CSI reset" "0: CSI is not under reset (default after reset),1: CSI is under reset" newline bitfld.long 0x8 5. "VENCRST,VENC reset" "0: VENC is not under reset (default after reset),1: VENC is under reset" newline bitfld.long 0x8 4. "GFXTIMRST,GFXTIM reset" "0: GFXTIM is not under reset (default after reset),1: GFXTIM is under reset" newline bitfld.long 0x8 2. "DCMIPPRST,DCMIPP reset" "0: DCMIPP is not under reset (default after reset),1: DCMIPP is under reset" newline bitfld.long 0x8 1. "LTDCRST,LTDC reset" "0: LTDC is not under reset (default after reset),1: LTDC is under reset" line.long 0xC "RCC_DIVENR,RCC IC dividers enable register" bitfld.long 0xC 19. "IC20EN,IC20 enable" "0: IC20 is disabled (default after reset),1: IC20 is enabled" newline bitfld.long 0xC 18. "IC19EN,IC19 enable" "0: IC19 is disabled (default after reset),1: IC19 is enabled" newline bitfld.long 0xC 17. "IC18EN,IC18 enable" "0: IC18 is disabled (default after reset),1: IC18 is enabled" newline bitfld.long 0xC 16. "IC17EN,IC17 enable" "0: IC17 is disabled (default after reset),1: IC17 is enabled" newline bitfld.long 0xC 15. "IC16EN,IC16 enable" "0: IC16 is disabled (default after reset),1: IC16 is enabled" newline bitfld.long 0xC 14. "IC15EN,IC15 enable" "0: IC15 is disabled (default after reset),1: IC15 is enabled" newline bitfld.long 0xC 13. "IC14EN,IC14 enable" "0: IC14 is disabled (default after reset),1: IC14 is enabled" newline bitfld.long 0xC 12. "IC13EN,IC13 enable" "0: IC13 is disabled (default after reset),1: IC13 is enabled" newline bitfld.long 0xC 11. "IC12EN,IC12 enable" "0: IC12 is disabled (default after reset),1: IC12 is enabled" newline bitfld.long 0xC 10. "IC11EN,IC11 enable" "0: IC11 is disabled (default after reset),1: IC11 is enabled" newline bitfld.long 0xC 9. "IC10EN,IC10 enable" "0: IC10 is disabled (default after reset),1: IC10 is enabled" newline bitfld.long 0xC 8. "IC9EN,IC9 enable" "0: IC9 is disabled (default after reset),1: IC9 is enabled" newline bitfld.long 0xC 7. "IC8EN,IC8 enable" "0: IC8 is disabled (default after reset),1: IC8 is enabled" newline bitfld.long 0xC 6. "IC7EN,IC7 enable" "0: IC7 is disabled (default after reset),1: IC7 is enabled" newline bitfld.long 0xC 5. "IC6EN,IC6 enable" "0: IC6 is disabled (default after reset),1: IC6 is enabled" newline bitfld.long 0xC 4. "IC5EN,IC5 enable" "0: IC5 is disabled (default after reset),1: IC5 is enabled" newline bitfld.long 0xC 3. "IC4EN,IC4 enable" "0: IC4 is disabled (default after reset),1: IC4 is enabled" newline bitfld.long 0xC 2. "IC3EN,IC3 enable" "0: IC3 is disabled (default after reset),1: IC3 is enabled" newline bitfld.long 0xC 1. "IC2EN,IC2 enable" "0: IC2 is disabled (default after reset),1: IC2 is enabled" newline bitfld.long 0xC 0. "IC1EN,IC1 enable" "0: IC1 is disabled (default after reset),1: IC1 is enabled" line.long 0x10 "RCC_BUSENR,RCC SoC buses enable register" bitfld.long 0x10 12. "APB5EN,APB5 enable" "0: APB5 is disabled (default after reset),1: APB5 is enabled" newline bitfld.long 0x10 11. "APB4EN,APB4 enable" "0: APB4 is disabled (default after reset),1: APB4 is enabled" newline bitfld.long 0x10 10. "APB3EN,APB3 enable" "0: APB3 is disabled (default after reset),1: APB3 is enabled" newline bitfld.long 0x10 9. "APB2EN,APB2 enable" "0: APB2 is disabled (default after reset),1: APB2 is enabled" newline bitfld.long 0x10 8. "APB1EN,APB1 enable" "0: APB1 is disabled (default after reset),1: APB1 is enabled" newline bitfld.long 0x10 7. "AHB5EN,AHB5 enable" "0: AHB5 is disabled (default after reset),1: AHB5 is enabled" newline bitfld.long 0x10 6. "AHB4EN,AHB4 enable" "0: AHB4 is disabled (default after reset),1: AHB4 is enabled" newline bitfld.long 0x10 5. "AHB3EN,AHB3 enable" "0: AHB3 is disabled (default after reset),1: AHB3 is enabled" newline bitfld.long 0x10 4. "AHB2EN,AHB2 enable" "0: AHB2 is disabled (default after reset),1: AHB2 is enabled" newline bitfld.long 0x10 3. "AHB1EN,AHB1 enable" "0: AHB1 is disabled (default after reset),1: AHB1 is enabled" newline bitfld.long 0x10 2. "AHBMEN,AHBM enable" "0: AHBM is disabled (default after reset),1: AHBM is enabled" newline bitfld.long 0x10 1. "ACLKNCEN,ACLKNC enable" "0: ACLKNC is disabled,1: ACLKNC is enabled (default after reset)" newline bitfld.long 0x10 0. "ACLKNEN,ACLKN enable" "0: ACLKN is disabled,1: ACLKN is enabled (default after reset)" line.long 0x14 "RCC_MISCENR,RCC miscellaneous configuration enable register" bitfld.long 0x14 6. "PEREN,PER enable" "0: PER is disabled (default after reset),1: PER is enabled" newline bitfld.long 0x14 3. "XSPIPHYCOMPEN,XSPIPHYCOMP enable" "0: XSPIPHYCOMP is disabled (default after reset),1: XSPIPHYCOMP is enabled" newline bitfld.long 0x14 2. "MCO2EN,MCO2 enable" "0: MCO2 is disabled (default after reset),1: MCO2 is enabled" newline bitfld.long 0x14 1. "MCO1EN,MCO1 enable" "0: MCO1 is disabled (default after reset),1: MCO1 is enabled" newline bitfld.long 0x14 0. "DBGEN,DBG enable" "0: DBG is disabled (default after reset),1: DBG is enabled" line.long 0x18 "RCC_MEMENR,RCC memory enable register" bitfld.long 0x18 12. "BOOTROMEN,BOOTROM enable" "0: BOOTROM is disabled,1: BOOTROM is enabled (default after reset)" newline bitfld.long 0x18 11. "VENCRAMEN,VENCRAM enable" "0: VENCRAM is disabled (default after reset),1: VENCRAM is enabled" newline bitfld.long 0x18 10. "NPUCACHERAMEN,NPUCACHERAM enable" "0: NPUCACHERAM is disabled (default after reset),1: NPUCACHERAM is enabled" newline bitfld.long 0x18 9. "FLEXRAMEN,FLEXRAM enable" "0: FLEXRAM is disabled,1: FLEXRAM is enabled (default after reset)" newline bitfld.long 0x18 8. "AXISRAM2EN,AXISRAM2 enable" "0: AXISRAM2 is disabled,1: AXISRAM2 is enabled (default after reset)" newline bitfld.long 0x18 7. "AXISRAM1EN,AXISRAM1 enable" "0: AXISRAM1 is disabled,1: AXISRAM1 is enabled (default after reset)" newline bitfld.long 0x18 6. "BKPSRAMEN,BKPSRAM enable" "0: BKPSRAM is disabled,1: BKPSRAM is enabled (default after reset)" newline bitfld.long 0x18 5. "AHBSRAM2EN,AHBSRAM2 enable" "0: AHBSRAM2 is disabled,1: AHBSRAM2 is enabled (default after reset)" newline bitfld.long 0x18 4. "AHBSRAM1EN,AHBSRAM1 enable" "0: AHBSRAM1 is disabled,1: AHBSRAM1 is enabled (default after reset)" newline bitfld.long 0x18 3. "AXISRAM6EN,AXISRAM6 enable" "0: AXISRAM6 is disabled,1: AXISRAM6 is enabled (default after reset)" newline bitfld.long 0x18 2. "AXISRAM5EN,AXISRAM5 enable" "0: AXISRAM5 is disabled,1: AXISRAM5 is enabled (default after reset)" newline bitfld.long 0x18 1. "AXISRAM4EN,AXISRAM4 enable" "0: AXISRAM4 is disabled,1: AXISRAM4 is enabled (default after reset)" newline bitfld.long 0x18 0. "AXISRAM3EN,AXISRAM3 enable" "0: AXISRAM3 is disabled,1: AXISRAM3 is enabled (default after reset)" line.long 0x1C "RCC_AHB1ENR,RCC AHB1 enable register" bitfld.long 0x1C 5. "ADC12EN,ADC12 enable" "0: ADC12 is disabled (default after reset),1: ADC12 is enabled" newline bitfld.long 0x1C 4. "GPDMA1EN,GPDMA1 enable" "0: GPDMA1 is disabled (default after reset),1: GPDMA1 is enabled" line.long 0x20 "RCC_AHB2ENR,RCC AHB2 enable register" bitfld.long 0x20 17. "ADF1EN,ADF enable" "0: ADF is disabled (default after reset),1: ADF is enabled" newline bitfld.long 0x20 16. "MDF1EN,MDF1 enable" "0: MDF1 is disabled (default after reset),1: MDF1 is enabled" newline bitfld.long 0x20 12. "RAMCFGEN,RAMCFG enable" "0: RAMCFG is disabled,1: RAMCFG is enabled (default after reset)" line.long 0x24 "RCC_AHB3ENR,RCC AHB3 enable register" bitfld.long 0x24 14. "RISAFEN,RISAF enable" "0: RISAF is disabled,1: RISAF is enabled (default after reset)" newline bitfld.long 0x24 10. "IACEN,IAC enable" "0: IAC is disabled,1: IAC is enabled (default after reset)" newline bitfld.long 0x24 9. "RIFSCEN,RIFSC enable" "0: RIFSC is disabled,1: RIFSC is enabled (default after reset)" newline bitfld.long 0x24 8. "PKAEN,PKA enable" "0: PKA is disabled (default after reset),1: PKA is enabled" newline bitfld.long 0x24 4. "SAESEN,SAES enable" "0: SAES is disabled (default after reset),1: SAES is enabled" newline bitfld.long 0x24 2. "CRYPEN,CRYP enable" "0: CRYP is disabled (default after reset),1: CRYP is enabled" newline bitfld.long 0x24 1. "HASHEN,HASH enable" "0: HASH is disabled (default after reset),1: HASH is enabled" newline bitfld.long 0x24 0. "RNGEN,RNG enable" "0: RNG is disabled (default after reset),1: RNG is enabled" line.long 0x28 "RCC_AHB4ENR,RCC AHB4 enable register" bitfld.long 0x28 19. "CRCEN,CRC enable" "0: CRC is disabled (default after reset),1: CRC is enabled" newline bitfld.long 0x28 18. "PWREN,PWR enable" "0: PWR is disabled,1: PWR is enabled (default after reset)" newline bitfld.long 0x28 16. "GPIOQEN,GPIOQ enable" "0: GPIOQ is disabled (default after reset),1: GPIOQ is enabled" newline bitfld.long 0x28 15. "GPIOPEN,GPIOP enable" "0: GPIOP is disabled (default after reset),1: GPIOP is enabled" newline bitfld.long 0x28 14. "GPIOOEN,GPIOO enable" "0: GPIOO is disabled (default after reset),1: GPIOO is enabled" newline bitfld.long 0x28 13. "GPIONEN,GPION enable" "0: GPION is disabled (default after reset),1: GPION is enabled" newline bitfld.long 0x28 7. "GPIOHEN,GPIOH enable" "0: GPIOH is disabled (default after reset),1: GPIOH is enabled" newline bitfld.long 0x28 6. "GPIOGEN,GPIOG enable" "0: GPIOG is disabled (default after reset),1: GPIOG is enabled" newline bitfld.long 0x28 5. "GPIOFEN,GPIOF enable" "0: GPIOF is disabled (default after reset),1: GPIOF is enabled" newline bitfld.long 0x28 4. "GPIOEEN,GPIOE enable" "0: GPIOE is disabled (default after reset),1: GPIOE is enabled" newline bitfld.long 0x28 3. "GPIODEN,GPIOD enable" "0: GPIOD is disabled (default after reset),1: GPIOD is enabled" newline bitfld.long 0x28 2. "GPIOCEN,GPIOC enable" "0: GPIOC is disabled (default after reset),1: GPIOC is enabled" newline bitfld.long 0x28 1. "GPIOBEN,GPIOB enable" "0: GPIOB is disabled (default after reset),1: GPIOB is enabled" newline bitfld.long 0x28 0. "GPIOAEN,GPIOA enable" "0: GPIOA is disabled (default after reset),1: GPIOA is enabled" line.long 0x2C "RCC_AHB5ENR,RCC AHB5 enable register" bitfld.long 0x2C 31. "NPUEN,NPU enable" "0: NPU is disabled (default after reset),1: NPU is enabled" newline bitfld.long 0x2C 30. "NPUCACHEEN,NPUCACHE enable" "0: NPUCACHE is disabled (default after reset),1: NPUCACHE is enabled" newline bitfld.long 0x2C 29. "OTG2EN,OTG2 enable" "0: OTG2 is disabled (default after reset),1: OTG2 is enabled" newline bitfld.long 0x2C 28. "OTGPHY2EN,OTGPHY2 enable" "0: OTGPHY2 is disabled (default after reset),1: OTGPHY2 is enabled" newline bitfld.long 0x2C 27. "OTGPHY1EN,OTGPHY1 enable" "0: OTGPHY1 is disabled (default after reset),1: OTGPHY1 is enabled" newline bitfld.long 0x2C 26. "OTG1EN,OTG1 enable" "0: OTG1 is disabled (default after reset),1: OTG1 is enabled" newline bitfld.long 0x2C 25. "ETH1EN,ETH1 enable" "0: ETH1 is disabled (default after reset),1: ETH1 is enabled" newline bitfld.long 0x2C 24. "ETH1RXEN,ETH1RX enable" "0: ETH1RX is disabled (default after reset),1: ETH1RX is enabled" newline bitfld.long 0x2C 23. "ETH1TXEN,ETH1TX enable" "0: ETH1TX is disabled (default after reset),1: ETH1TX is enabled" newline bitfld.long 0x2C 22. "ETH1MACEN,ETH1MAC enable" "0: ETH1MAC is disabled (default after reset),1: ETH1MAC is enabled" newline bitfld.long 0x2C 20. "GPUEN,GPU enable" "0: GPU is disabled (default after reset),1: GPU is enabled" newline bitfld.long 0x2C 19. "GFXMMUEN,GFXMMU enable" "0: GFXMMU is disabled (default after reset),1: GFXMMU is enabled" newline bitfld.long 0x2C 18. "MCE4EN,MCE4 enable" "0: MCE4 is disabled (default after reset),1: MCE4 is enabled" newline bitfld.long 0x2C 17. "XSPI3EN,XSPI3 enable" "0: XSPI3 is disabled (default after reset),1: XSPI3 is enabled" newline bitfld.long 0x2C 16. "MCE3EN,MCE3 enable" "0: MCE3 is disabled (default after reset),1: MCE3 is enabled" newline bitfld.long 0x2C 15. "MCE2EN,MCE2 enable" "0: MCE2 is disabled (default after reset),1: MCE2 is enabled" newline bitfld.long 0x2C 14. "MCE1EN,MCE1 enable" "0: MCE1 is disabled (default after reset),1: MCE1 is enabled" newline bitfld.long 0x2C 13. "XSPIMEN,XSPIM enable" "0: XSPIM is disabled (default after reset),1: XSPIM is enabled" newline bitfld.long 0x2C 12. "XSPI2EN,XSPI2 enable" "0: XSPI2 is disabled (default after reset),1: XSPI2 is enabled" newline bitfld.long 0x2C 8. "SDMMC1EN,SDMMC1 enable" "0: SDMMC1 is disabled (default after reset),1: SDMMC1 is enabled" newline bitfld.long 0x2C 7. "SDMMC2EN,SDMMC2 enable" "0: SDMMC2 is disabled (default after reset),1: SDMMC2 is enabled" newline bitfld.long 0x2C 6. "PSSIEN,PSSI enable" "0: PSSI is disabled (default after reset),1: PSSI is enabled" newline bitfld.long 0x2C 5. "XSPI1EN,XSPI1 enable" "0: XSPI1 is disabled (default after reset),1: XSPI1 is enabled" newline bitfld.long 0x2C 4. "FMCEN,FMC enable" "0: FMC is disabled (default after reset),1: FMC is enabled" newline bitfld.long 0x2C 3. "JPEGEN,JPEG enable" "0: JPEG is disabled (default after reset),1: JPEG is enabled" newline bitfld.long 0x2C 1. "DMA2DEN,DMA2D enable" "0: DMA2D is disabled (default after reset),1: DMA2D is enabled" newline bitfld.long 0x2C 0. "HPDMA1EN,HPDMA1 enable" "0: HPDMA1 is disabled (default after reset),1: HPDMA1 is enabled" line.long 0x30 "RCC_APB1LENR,RCC APB1L enable register" bitfld.long 0x30 31. "UART8EN,UART8 enable" "0: UART8 is disabled (default after reset),1: UART8 is enabled" newline bitfld.long 0x30 30. "UART7EN,UART7 enable" "0: UART7 is disabled (default after reset),1: UART7 is enabled" newline bitfld.long 0x30 25. "I3C2EN,I3C2 enable" "0: I3C2 is disabled (default after reset),1: I3C2 is enabled" newline bitfld.long 0x30 24. "I3C1EN,I3C1 enable" "0: I3C1 is disabled (default after reset),1: I3C1 is enabled" newline bitfld.long 0x30 23. "I2C3EN,I2C3 enable" "0: I2C3 is disabled (default after reset),1: I2C3 is enabled" newline bitfld.long 0x30 22. "I2C2EN,I2C2 enable" "0: I2C2 is disabled (default after reset),1: I2C2 is enabled" newline bitfld.long 0x30 21. "I2C1EN,I2C1 enable" "0: I2C1 is disabled (default after reset),1: I2C1 is enabled" newline bitfld.long 0x30 20. "UART5EN,UART5 enable" "0: UART5 is disabled (default after reset),1: UART5 is enabled" newline bitfld.long 0x30 19. "UART4EN,UART4 enable" "0: UART4 is disabled (default after reset),1: UART4 is enabled" newline bitfld.long 0x30 18. "USART3EN,USART3 enable" "0: USART3 is disabled (default after reset),1: USART3 is enabled" newline bitfld.long 0x30 17. "USART2EN,USART2 enable" "0: USART2 is disabled (default after reset),1: USART2 is enabled" newline bitfld.long 0x30 16. "SPDIFRX1EN,SPDIFRX1 enable" "0: SPDIFRX1 is disabled (default after reset),1: SPDIFRX1 is enabled" newline bitfld.long 0x30 15. "SPI3EN,SPI3 enable" "0: SPI3 is disabled (default after reset),1: SPI3 is enabled" newline bitfld.long 0x30 14. "SPI2EN,SPI2 enable" "0: SPI2 is disabled (default after reset),1: SPI2 is enabled" newline bitfld.long 0x30 13. "TIM11EN,TIM11 enable" "0: TIM11 is disabled (default after reset),1: TIM11 is enabled" newline bitfld.long 0x30 12. "TIM10EN,TIM10 enable" "0: TIM10 is disabled (default after reset),1: TIM10 is enabled" newline bitfld.long 0x30 11. "WWDGEN,WWDG enable" "0: WWDG is disabled (default after reset),1: WWDG is enabled" newline bitfld.long 0x30 9. "LPTIM1EN,LPTIM1 enable" "0: LPTIM1 is disabled (default after reset),1: LPTIM1 is enabled" newline bitfld.long 0x30 8. "TIM14EN,TIM14 enable" "0: TIM14 is disabled (default after reset),1: TIM14 is enabled" newline bitfld.long 0x30 7. "TIM13EN,TIM13 enable" "0: TIM13 is disabled (default after reset),1: TIM13 is enabled" newline bitfld.long 0x30 6. "TIM12EN,TIM12 enable" "0: TIM12 is disabled (default after reset),1: TIM12 is enabled" newline bitfld.long 0x30 5. "TIM7EN,TIM7 enable" "0: TIM7 is disabled (default after reset),1: TIM7 is enabled" newline bitfld.long 0x30 4. "TIM6EN,TIM6 enable" "0: TIM6 is disabled (default after reset),1: TIM6 is enabled" newline bitfld.long 0x30 3. "TIM5EN,TIM5 enable" "0: TIM5 is disabled (default after reset),1: TIM5 is enabled" newline bitfld.long 0x30 2. "TIM4EN,TIM4 enable" "0: TIM4 is disabled (default after reset),1: TIM4 is enabled" newline bitfld.long 0x30 1. "TIM3EN,TIM3 enable" "0: TIM3 is disabled (default after reset),1: TIM3 is enabled" newline bitfld.long 0x30 0. "TIM2EN,TIM2 enable" "0: TIM2 is disabled (default after reset),1: TIM2 is enabled" line.long 0x34 "RCC_APB1HENR,RCC APB1H enable register" bitfld.long 0x34 18. "UCPD1EN,UCPD1 enable" "0: UCPD1 is disabled (default after reset),1: UCPD1 is enabled" newline bitfld.long 0x34 8. "FDCANEN,FDCAN enable" "0: FDCAN is disabled (default after reset),1: FDCAN is enabled" newline bitfld.long 0x34 5. "MDIOSEN,MDIOS enable" "0: MDIOS is disabled (default after reset),1: MDIOS is enabled" line.long 0x38 "RCC_APB2ENR,RCC APB2 enable register" bitfld.long 0x38 22. "SAI2EN,SAI2 enable" "0: SAI2 is disabled (default after reset),1: SAI2 is enabled" newline bitfld.long 0x38 21. "SAI1EN,SAI1 enable" "0: SAI1 is disabled (default after reset),1: SAI1 is enabled" newline bitfld.long 0x38 20. "SPI5EN,SPI5 enable" "0: SPI5 is disabled (default after reset),1: SPI5 is enabled" newline bitfld.long 0x38 19. "TIM9EN,TIM9 enable" "0: TIM9 is disabled (default after reset),1: TIM9 is enabled" newline bitfld.long 0x38 18. "TIM17EN,TIM17 enable" "0: TIM17 is disabled (default after reset),1: TIM17 is enabled" newline bitfld.long 0x38 17. "TIM16EN,TIM16 enable" "0: TIM16 is disabled (default after reset),1: TIM16 is enabled" newline bitfld.long 0x38 16. "TIM15EN,TIM15 enable" "0: TIM15 is disabled (default after reset),1: TIM15 is enabled" newline bitfld.long 0x38 15. "TIM18EN,TIM18 enable" "0: TIM18 is disabled (default after reset),1: TIM18 is enabled" newline bitfld.long 0x38 13. "SPI4EN,SPI4 enable" "0: SPI4 is disabled (default after reset),1: SPI4 is enabled" newline bitfld.long 0x38 12. "SPI1EN,SPI1 enable" "0: SPI1 is disabled (default after reset),1: SPI1 is enabled" newline bitfld.long 0x38 7. "USART10EN,USART10 enable" "0: USART10 is disabled (default after reset),1: USART10 is enabled" newline bitfld.long 0x38 6. "UART9EN,UART9 enable" "0: UART9 is disabled (default after reset),1: UART9 is enabled" newline bitfld.long 0x38 5. "USART6EN,USART6 enable" "0: USART6 is disabled (default after reset),1: USART6 is enabled" newline bitfld.long 0x38 4. "USART1EN,USART1 enable" "0: USART1 is disabled (default after reset),1: USART1 is enabled" newline bitfld.long 0x38 1. "TIM8EN,TIM8 enable" "0: TIM8 is disabled (default after reset),1: TIM8 is enabled" newline bitfld.long 0x38 0. "TIM1EN,TIM1 enable" "0: TIM1 is disabled (default after reset),1: TIM1 is enabled" line.long 0x3C "RCC_APB3ENR,RCC APB3 enable register" bitfld.long 0x3C 2. "DFTEN,DFT enable" "0: DFT is disabled (default after reset),1: DFT is enabled" line.long 0x40 "RCC_APB4LENR,RCC APB4L enable register" bitfld.long 0x40 31. "SERFEN,SERF enable" "0: SERF is disabled (default after reset),1: SERF is enabled" newline bitfld.long 0x40 23. "R2GNPUEN,R2GNPU enable" "0: R2GNPU is disabled (default after reset),1: R2GNPU is enabled" newline bitfld.long 0x40 22. "R2GRETEN,R2GRET enable" "0: R2GRET is disabled (default after reset),1: R2GRET is enabled" newline bitfld.long 0x40 17. "RTCAPBEN,RTCAPB enable" "0: RTCAPB is disabled (default after reset),1: RTCAPB is enabled" newline bitfld.long 0x40 16. "RTCEN,RTC enable" "0: RTC is disabled (default after reset),1: RTC is enabled" newline bitfld.long 0x40 15. "VREFBUFEN,VREFBUF enable" "0: VREFBUF is disabled (default after reset),1: VREFBUF is enabled" newline bitfld.long 0x40 12. "LPTIM5EN,LPTIM5 enable" "0: LPTIM5 is disabled (default after reset),1: LPTIM5 is enabled" newline bitfld.long 0x40 11. "LPTIM4EN,LPTIM4 enable" "0: LPTIM4 is disabled (default after reset),1: LPTIM4 is enabled" newline bitfld.long 0x40 10. "LPTIM3EN,LPTIM3 enable" "0: LPTIM3 is disabled (default after reset),1: LPTIM3 is enabled" newline bitfld.long 0x40 9. "LPTIM2EN,LPTIM2 enable" "0: LPTIM2 is disabled (default after reset),1: LPTIM2 is enabled" newline bitfld.long 0x40 7. "I2C4EN,I2C4 enable" "0: I2C4 is disabled (default after reset),1: I2C4 is enabled" newline bitfld.long 0x40 5. "SPI6EN,SPI6 enable" "0: SPI6 is disabled (default after reset),1: SPI6 is enabled" newline bitfld.long 0x40 3. "LPUART1EN,LPUART1 enable" "0: LPUART1 is disabled (default after reset),1: LPUART1 is enabled" newline bitfld.long 0x40 2. "HDPEN,HDP enable" "0: HDP is disabled (default after reset),1: HDP is enabled" line.long 0x44 "RCC_APB4HENR,RCC APB4H enable register" bitfld.long 0x44 4. "BUSPERFMEN,BUSPERFM enable" "0: BUSPERFM is disabled (default after reset),1: BUSPERFM is enabled" newline bitfld.long 0x44 2. "DTSEN,DTS enable" "0: DTS is disabled (default after reset),1: DTS is enabled" newline bitfld.long 0x44 1. "BSECEN,BSEC enable" "0: BSEC is disabled,1: BSEC is enabled (default after reset)" newline bitfld.long 0x44 0. "SYSCFGEN,SYSCFG enable" "0: SYSCFG is disabled (default after reset),1: SYSCFG is enabled" line.long 0x48 "RCC_APB5ENR,RCC APB5 enable register" bitfld.long 0x48 6. "CSIEN,CSI enable" "0: CSI is disabled (default after reset),1: CSI is enabled" newline bitfld.long 0x48 5. "VENCEN,VENC enable" "0: VENC is disabled (default after reset),1: VENC is enabled" newline bitfld.long 0x48 4. "GFXTIMEN,GFXTIM enable" "0: GFXTIM is disabled (default after reset),1: GFXTIM is enabled" newline bitfld.long 0x48 2. "DCMIPPEN,DCMIPP enable" "0: DCMIPP is disabled (default after reset),1: DCMIPP is enabled" newline bitfld.long 0x48 1. "LTDCEN,LTDC enable" "0: LTDC is disabled (default after reset),1: LTDC is enabled" line.long 0x4C "RCC_DIVLPENR,RCC dividers Sleep enable register" bitfld.long 0x4C 19. "IC20LPEN,IC20 sleep enable" "0: IC20 is disabled in Sleep mode (default after..,1: IC20 is enabled in Sleep mode" newline bitfld.long 0x4C 18. "IC19LPEN,IC19 sleep enable" "0: IC19 is disabled in Sleep mode (default after..,1: IC19 is enabled in Sleep mode" newline bitfld.long 0x4C 17. "IC18LPEN,IC18 sleep enable" "0: IC18 is disabled in Sleep mode (default after..,1: IC18 is enabled in Sleep mode" newline bitfld.long 0x4C 16. "IC17LPEN,IC17 sleep enable" "0: IC17 is disabled in Sleep mode (default after..,1: IC17 is enabled in Sleep mode" newline bitfld.long 0x4C 15. "IC16LPEN,IC16 sleep enable" "0: IC16 is disabled in Sleep mode (default after..,1: IC16 is enabled in Sleep mode" newline bitfld.long 0x4C 14. "IC15LPEN,IC15 sleep enable" "0: IC15 is disabled in Sleep mode (default after..,1: IC15 is enabled in Sleep mode" newline bitfld.long 0x4C 13. "IC14LPEN,IC14 sleep enable" "0: IC14 is disabled in Sleep mode (default after..,1: IC14 is enabled in Sleep mode" newline bitfld.long 0x4C 12. "IC13LPEN,IC13 sleep enable" "0: IC13 is disabled in Sleep mode (default after..,1: IC13 is enabled in Sleep mode" newline bitfld.long 0x4C 11. "IC12LPEN,IC12 sleep enable" "0: IC12 is disabled in Sleep mode (default after..,1: IC12 is enabled in Sleep mode" newline bitfld.long 0x4C 10. "IC11LPEN,IC11 sleep enable" "0: IC11 is disabled in Sleep mode (default after..,1: IC11 is enabled in Sleep mode" newline bitfld.long 0x4C 9. "IC10LPEN,IC10 sleep enable" "0: IC10 is disabled in Sleep mode (default after..,1: IC10 is enabled in Sleep mode" newline bitfld.long 0x4C 8. "IC9LPEN,IC9 sleep enable" "0: IC9 is disabled in Sleep mode (default after..,1: IC9 is enabled in Sleep mode" newline bitfld.long 0x4C 7. "IC8LPEN,IC8 sleep enable" "0: IC8 is disabled in Sleep mode (default after..,1: IC8 is enabled in Sleep mode" newline bitfld.long 0x4C 6. "IC7LPEN,IC7 sleep enable" "0: IC7 is disabled in Sleep mode (default after..,1: IC7 is enabled in Sleep mode" newline bitfld.long 0x4C 5. "IC6LPEN,IC6 sleep enable" "0: IC6 is disabled in Sleep mode (default after..,1: IC6 is enabled in Sleep mode" newline bitfld.long 0x4C 4. "IC5LPEN,IC5 sleep enable" "0: IC5 is disabled in Sleep mode (default after..,1: IC5 is enabled in Sleep mode" newline bitfld.long 0x4C 3. "IC4LPEN,IC4 sleep enable" "0: IC4 is disabled in Sleep mode (default after..,1: IC4 is enabled in Sleep mode" newline bitfld.long 0x4C 2. "IC3LPEN,IC3 sleep enable" "0: IC3 is disabled in Sleep mode (default after..,1: IC3 is enabled in Sleep mode" newline bitfld.long 0x4C 1. "IC2LPEN,IC2 sleep enable" "0: IC2 is disabled in Sleep mode (default after..,1: IC2 is enabled in Sleep mode" newline bitfld.long 0x4C 0. "IC1LPEN,IC1 sleep enable" "0: IC1 is disabled in Sleep mode (default after..,1: IC1 is enabled in Sleep mode" line.long 0x50 "RCC_BUSLPENR,RCC SoC buses Sleep enable register" bitfld.long 0x50 12. "APB5LPEN,APB5 sleep enable" "0: APB5 is disabled in Sleep mode (default after..,1: APB5 is enabled in Sleep mode" newline bitfld.long 0x50 11. "APB4LPEN,APB4 sleep enable" "0: APB4 is disabled in Sleep mode (default after..,1: APB4 is enabled in Sleep mode" newline bitfld.long 0x50 10. "APB3LPEN,APB3 sleep enable" "0: APB3 is disabled in Sleep mode (default after..,1: APB3 is enabled in Sleep mode" newline bitfld.long 0x50 9. "APB2LPEN,APB2 sleep enable" "0: APB2 is disabled in Sleep mode (default after..,1: APB2 is enabled in Sleep mode" newline bitfld.long 0x50 8. "APB1LPEN,APB1 sleep enable" "0: APB1 is disabled in Sleep mode (default after..,1: APB1 is enabled in Sleep mode" newline bitfld.long 0x50 7. "AHB5LPEN,AHB5 sleep enable" "0: AHB5 is disabled in Sleep mode (default after..,1: AHB5 is enabled in Sleep mode" newline bitfld.long 0x50 6. "AHB4LPEN,AHB4 sleep enable" "0: AHB4 is disabled in Sleep mode (default after..,1: AHB4 is enabled in Sleep mode" newline bitfld.long 0x50 5. "AHB3LPEN,AHB3 sleep enable" "0: AHB3 is disabled in Sleep mode (default after..,1: AHB3 is enabled in Sleep mode" newline bitfld.long 0x50 4. "AHB2LPEN,AHB2 sleep enable" "0: AHB2 is disabled in Sleep mode (default after..,1: AHB2 is enabled in Sleep mode" newline bitfld.long 0x50 3. "AHB1LPEN,AHB1 sleep enable" "0: AHB1 is disabled in Sleep mode (default after..,1: AHB1 is enabled in Sleep mode" newline bitfld.long 0x50 2. "AHBMLPEN,AHBM sleep enable" "0: AHBM is disabled in Sleep mode (default after..,1: AHBM is enabled in Sleep mode" newline bitfld.long 0x50 1. "ACLKNCLPEN,ACLKNC sleep enable" "0: ACLKNC is disabled in Sleep mode,1: ACLKNC is enabled in Sleep mode (default after.." newline bitfld.long 0x50 0. "ACLKNLPEN,ACLKN sleep enable" "0: ACLKN is disabled in Sleep mode,1: ACLKN is enabled in Sleep mode (default after.." line.long 0x54 "RCC_MISCLPENR,RCC miscellaneous configurations Sleep enable register" bitfld.long 0x54 6. "PERLPEN,PER sleep enable" "0: PER is disabled in Sleep mode (default after..,1: PER is enabled in Sleep mode" newline bitfld.long 0x54 3. "XSPIPHYCOMPLPEN,XSPIPHYCOMP sleep enable" "0: XSPIPHYCOMP is disabled in Sleep mode (default..,1: XSPIPHYCOMP is enabled in Sleep mode" newline bitfld.long 0x54 0. "DBGLPEN,DBG sleep enable" "0: DBG is disabled in Sleep mode (default after..,1: DBG is enabled in Sleep mode" line.long 0x58 "RCC_MEMLPENR,RCC memory Sleep enable register" bitfld.long 0x58 12. "BOOTROMLPEN,BOOTROM sleep enable" "0: BOOTROM is disabled in Sleep mode (default after..,1: BOOTROM is enabled in Sleep mode" newline bitfld.long 0x58 11. "VENCRAMLPEN,VENCRAM sleep enable" "0: VENCRAM is disabled in Sleep mode (default after..,1: VENCRAM is enabled in Sleep mode" newline bitfld.long 0x58 10. "NPUCACHERAMLPEN,NPUCACHERAM sleep enable" "0: NPUCACHERAM is disabled in Sleep mode (default..,1: NPUCACHERAM is enabled in Sleep mode" newline bitfld.long 0x58 9. "FLEXRAMLPEN,FLEXRAM sleep enable" "0: FLEXRAM is disabled in Sleep mode (default after..,1: FLEXRAM is enabled in Sleep mode" newline bitfld.long 0x58 8. "AXISRAM2LPEN,AXISRAM2 sleep enable" "0: AXISRAM2 is disabled in Sleep mode (default..,1: AXISRAM2 is enabled in Sleep mode" newline bitfld.long 0x58 7. "AXISRAM1LPEN,AXISRAM1 sleep enable" "0: AXISRAM1 is disabled in Sleep mode (default..,1: AXISRAM1 is enabled in Sleep mode" newline bitfld.long 0x58 6. "BKPSRAMLPEN,BKPSRAM sleep enable" "0: BKPSRAM is disabled in Sleep mode (default after..,1: BKPSRAM is enabled in Sleep mode" newline bitfld.long 0x58 5. "AHBSRAM2LPEN,AHBSRAM2 sleep enable" "0: AHBSRAM2 is disabled in Sleep mode (default..,1: AHBSRAM2 is enabled in Sleep mode" newline bitfld.long 0x58 4. "AHBSRAM1LPEN,AHBSRAM1 sleep enable" "0: AHBSRAM1 is disabled in Sleep mode (default..,1: AHBSRAM1 is enabled in Sleep mode" newline bitfld.long 0x58 3. "AXISRAM6LPEN,AXISRAM6 sleep enable" "0: AXISRAM6 is disabled in Sleep mode (default..,1: AXISRAM6 is enabled in Sleep mode" newline bitfld.long 0x58 2. "AXISRAM5LPEN,AXISRAM5 sleep enable" "0: AXISRAM5 is disabled in Sleep mode (default..,1: AXISRAM5 is enabled in Sleep mode" newline bitfld.long 0x58 1. "AXISRAM4LPEN,AXISRAM4 sleep enable" "0: AXISRAM4 is disabled in Sleep mode (default..,1: AXISRAM4 is enabled in Sleep mode" newline bitfld.long 0x58 0. "AXISRAM3LPEN,AXISRAM3 sleep enable" "0: AXISRAM3 is disabled in Sleep mode (default..,1: AXISRAM3 is enabled in Sleep mode" line.long 0x5C "RCC_AHB1LPENR,RCC AHB1 Sleep enable register" bitfld.long 0x5C 5. "ADC12LPEN,ADC12 sleep enable" "0: ADC12 is disabled in Sleep mode (default after..,1: ADC12 is enabled in Sleep mode" newline bitfld.long 0x5C 4. "GPDMA1LPEN,GPDMA1 sleep enable" "0: GPDMA1 is disabled in Sleep mode (default after..,1: GPDMA1 is enabled in Sleep mode" line.long 0x60 "RCC_AHB2LPENR,RCC AHB2 Sleep enable register" bitfld.long 0x60 17. "ADF1LPEN,ADF1 sleep enable" "0: ADF1 is disabled in Sleep mode (default after..,1: ADF1 is enabled in Sleep mode" newline bitfld.long 0x60 16. "MDF1LPEN,MDF1 sleep enable" "0: MDF1 is disabled in Sleep mode (default after..,1: MDF1 is enabled in Sleep mode" newline bitfld.long 0x60 12. "RAMCFGLPEN,RAMCFG sleep enable" "0: RAMCFG is disabled in Sleep mode (default after..,1: RAMCFG is enabled in Sleep mode" line.long 0x64 "RCC_AHB3LPENR,RCC AHB3 Sleep enable register" bitfld.long 0x64 14. "RISAFLPEN,RISAF sleep enable" "0: RISAF is disabled in Sleep mode (default after..,1: RISAF is enabled in Sleep mode" newline bitfld.long 0x64 10. "IACLPEN,IAC sleep enable" "0: IAC is disabled in Sleep mode,1: IAC is enabled in Sleep mode (default after reset)" newline bitfld.long 0x64 9. "RIFSCLPEN,RIFSC sleep enable" "0: RIFSC is disabled in Sleep mode (default after..,1: RIFSC is enabled in Sleep mode" newline bitfld.long 0x64 8. "PKALPEN,PKA sleep enable" "0: PKA is disabled in Sleep mode (default after..,1: PKA is enabled in Sleep mode" newline bitfld.long 0x64 4. "SAESLPEN,SAES sleep enable" "0: SAES is disabled in Sleep mode (default after..,1: SAES is enabled in Sleep mode" newline bitfld.long 0x64 2. "CRYPLPEN,CRYP sleep enable" "0: CRYP is disabled in Sleep mode (default after..,1: CRYP is enabled in Sleep mode" newline bitfld.long 0x64 1. "HASHLPEN,HASH sleep enable" "0: HASH is disabled in Sleep mode (default after..,1: HASH is enabled in Sleep mode" newline bitfld.long 0x64 0. "RNGLPEN,RNG sleep enable" "0: RNG is disabled in Sleep mode (default after..,1: RNG is enabled in Sleep mode" line.long 0x68 "RCC_AHB4LPENR,RCC AHB4 Sleep enable register" bitfld.long 0x68 19. "CRCLPEN,CRC sleep enable" "0: CRC is disabled in Sleep mode (default after..,1: CRC is enabled in Sleep mode" newline bitfld.long 0x68 18. "PWRLPEN,PWR sleep enable" "0: PWR is disabled in Sleep mode,1: PWR is enabled in Sleep mode (default after reset)" newline bitfld.long 0x68 16. "GPIOQLPEN,GPIOQ sleep enable" "0: GPIOQ is disabled in Sleep mode (default after..,1: GPIOQ is enabled in Sleep mode" newline bitfld.long 0x68 15. "GPIOPLPEN,GPIOP sleep enable" "0: GPIOP is disabled in Sleep mode (default after..,1: GPIOP is enabled in Sleep mode" newline bitfld.long 0x68 14. "GPIOOLPEN,GPIOO sleep enable" "0: GPIOO is disabled in Sleep mode (default after..,1: GPIOO is enabled in Sleep mode" newline bitfld.long 0x68 13. "GPIONLPEN,GPION sleep enable" "0: GPION is disabled in Sleep mode (default after..,1: GPION is enabled in Sleep mode" newline bitfld.long 0x68 7. "GPIOHLPEN,GPIOH sleep enable" "0: GPIOH is disabled in Sleep mode (default after..,1: GPIOH is enabled in Sleep mode" newline bitfld.long 0x68 6. "GPIOGLPEN,GPIOG sleep enable" "0: GPIOG is disabled in Sleep mode (default after..,1: GPIOG is enabled in Sleep mode" newline bitfld.long 0x68 5. "GPIOFLPEN,GPIOF sleep enable" "0: GPIOF is disabled in Sleep mode (default after..,1: GPIOF is enabled in Sleep mode" newline bitfld.long 0x68 4. "GPIOELPEN,GPIOE sleep enable" "0: GPIOE is disabled in Sleep mode (default after..,1: GPIOE is enabled in Sleep mode" newline bitfld.long 0x68 3. "GPIODLPEN,GPIOD sleep enable" "0: GPIOD is disabled in Sleep mode (default after..,1: GPIOD is enabled in Sleep mode" newline bitfld.long 0x68 2. "GPIOCLPEN,GPIOC sleep enable" "0: GPIOC is disabled in Sleep mode (default after..,1: GPIOC is enabled in Sleep mode" newline bitfld.long 0x68 1. "GPIOBLPEN,GPIOB sleep enable" "0: GPIOB is disabled in Sleep mode (default after..,1: GPIOB is enabled in Sleep mode" newline bitfld.long 0x68 0. "GPIOALPEN,GPIOA sleep enable" "0: GPIOA is disabled in Sleep mode (default after..,1: GPIOA is enabled in Sleep mode" line.long 0x6C "RCC_AHB5LPENR,RCC AHB5 Sleep enable register" bitfld.long 0x6C 31. "NPULPEN,NPU sleep enable" "0: NPU is disabled in Sleep mode (default after..,1: NPU is enabled in Sleep mode" newline bitfld.long 0x6C 30. "NPUCACHELPEN,NPUCACHE sleep enable" "0: NPUCACHE is disabled in Sleep mode (default..,1: NPUCACHE is enabled in Sleep mode" newline bitfld.long 0x6C 29. "OTG2LPEN,OTG2 sleep enable" "0: OTG2 is disabled in Sleep mode (default after..,1: OTG2 is enabled in Sleep mode" newline bitfld.long 0x6C 28. "OTGPHY2LPEN,OTGPHY2 sleep enable" "0: OTGPHY2 is disabled in Sleep mode (default after..,1: OTGPHY2 is enabled in Sleep mode" newline bitfld.long 0x6C 27. "OTGPHY1LPEN,OTGPHY1 sleep enable" "0: OTGPHY1 is disabled in Sleep mode (default after..,1: OTGPHY1 is enabled in Sleep mode" newline bitfld.long 0x6C 26. "OTG1LPEN,OTG1 sleep enable" "0: OTG1 is disabled in Sleep mode (default after..,1: OTG1 is enabled in Sleep mode" newline bitfld.long 0x6C 25. "ETH1LPEN,ETH1 sleep enable" "0: ETH1 is disabled in Sleep mode (default after..,1: ETH1 is enabled in Sleep mode" newline bitfld.long 0x6C 24. "ETH1RXLPEN,ETH1RX sleep enable" "0: ETH1RX is disabled in Sleep mode (default after..,1: ETH1RX is enabled in Sleep mode" newline bitfld.long 0x6C 23. "ETH1TXLPEN,ETH1TX sleep enable" "0: ETH1TX is disabled in Sleep mode (default after..,1: ETH1TX is enabled in Sleep mode" newline bitfld.long 0x6C 22. "ETH1MACLPEN,ETH1MAC sleep enable" "0: ETH1MAC is disabled in Sleep mode (default after..,1: ETH1MAC is enabled in Sleep mode" newline bitfld.long 0x6C 20. "GPULPEN,GPU sleep enable" "0: GPU is disabled in Sleep mode (default after..,1: GPU is enabled in Sleep mode" newline bitfld.long 0x6C 19. "GFXMMULPEN,GFXMMU sleep enable" "0: GFXMMU is disabled in Sleep mode (default after..,1: GFXMMU is enabled in Sleep mode" newline bitfld.long 0x6C 18. "MCE4LPEN,MCE4 sleep enable" "0: MCE4 is disabled in Sleep mode (default after..,1: MCE4 is enabled in Sleep mode" newline bitfld.long 0x6C 17. "XSPI3LPEN,XSPI3 sleep enable" "0: XSPI3 is disabled in Sleep mode (default after..,1: XSPI3 is enabled in Sleep mode" newline bitfld.long 0x6C 16. "MCE3LPEN,MCE3 sleep enable" "0: MCE3 is disabled in Sleep mode (default after..,1: MCE3 is enabled in Sleep mode" newline bitfld.long 0x6C 15. "MCE2LPEN,MCE2 sleep enable" "0: MCE2 is disabled in Sleep mode (default after..,1: MCE2 is enabled in Sleep mode" newline bitfld.long 0x6C 14. "MCE1LPEN,MCE1 sleep enable" "0: MCE1 is disabled in Sleep mode (default after..,1: MCE1 is enabled in Sleep mode" newline bitfld.long 0x6C 13. "XSPIMLPEN,XSPIM sleep enable" "0: XSPIM is disabled in Sleep mode (default after..,1: XSPIM is enabled in Sleep mode" newline bitfld.long 0x6C 12. "XSPI2LPEN,XSPI2 sleep enable" "0: XSPI2 is disabled in Sleep mode (default after..,1: XSPI2 is enabled in Sleep mode" newline bitfld.long 0x6C 8. "SDMMC1LPEN,SDMMC1 sleep enable" "0: SDMMC1 is disabled in Sleep mode (default after..,1: SDMMC1 is enabled in Sleep mode" newline bitfld.long 0x6C 7. "SDMMC2LPEN,SDMMC2 sleep enable" "0: SDMMC2 is disabled in Sleep mode (default after..,1: SDMMC2 is enabled in Sleep mode" newline bitfld.long 0x6C 6. "PSSILPEN,PSSI sleep enable" "0: PSSI is disabled in Sleep mode (default after..,1: PSSI is enabled in Sleep mode" newline bitfld.long 0x6C 5. "XSPI1LPEN,XSPI1 sleep enable" "0: XSPI1 is disabled in Sleep mode (default after..,1: XSPI1 is enabled in Sleep mode" newline bitfld.long 0x6C 4. "FMCLPEN,FMC sleep enable" "0: FMC is disabled in Sleep mode (default after..,1: FMC is enabled in Sleep mode" newline bitfld.long 0x6C 3. "JPEGLPEN,JPEG sleep enable" "0: JPEG is disabled in Sleep mode (default after..,1: JPEG is enabled in Sleep mode" newline bitfld.long 0x6C 1. "DMA2DLPEN,DMA2D sleep enable" "0: DMA2D is disabled in Sleep mode (default after..,1: DMA2D is enabled in Sleep mode" newline bitfld.long 0x6C 0. "HPDMA1LPEN,HPDMA1 sleep enable" "0: HPDMA1 is disabled in Sleep mode (default after..,1: HPDMA1 is enabled in Sleep mode" line.long 0x70 "RCC_APB1LLPENR,RCC APB1L Sleep enable register" bitfld.long 0x70 31. "UART8LPEN,UART8 sleep enable" "0: UART8 is disabled in Sleep mode (default after..,1: UART8 is enabled in Sleep mode" newline bitfld.long 0x70 30. "UART7LPEN,UART7 sleep enable" "0: UART7 is disabled in Sleep mode (default after..,1: UART7 is enabled in Sleep mode" newline bitfld.long 0x70 25. "I3C2LPEN,I3C2 sleep enable" "0: I3C2 is disabled in Sleep mode (default after..,1: I3C2 is enabled in Sleep mode" newline bitfld.long 0x70 24. "I3C1LPEN,I3C1 sleep enable" "0: I3C1 is disabled in Sleep mode (default after..,1: I3C1 is enabled in Sleep mode" newline bitfld.long 0x70 23. "I2C3LPEN,I2C3 sleep enable" "0: I2C3 is disabled in Sleep mode (default after..,1: I2C3 is enabled in Sleep mode" newline bitfld.long 0x70 22. "I2C2LPEN,I2C2 sleep enable" "0: I2C2 is disabled in Sleep mode (default after..,1: I2C2 is enabled in Sleep mode" newline bitfld.long 0x70 21. "I2C1LPEN,I2C1 sleep enable" "0: I2C1 is disabled in Sleep mode (default after..,1: I2C1 is enabled in Sleep mode" newline bitfld.long 0x70 20. "UART5LPEN,UART5 sleep enable" "0: UART5 is disabled in Sleep mode (default after..,1: UART5 is enabled in Sleep mode" newline bitfld.long 0x70 19. "UART4LPEN,UART4 sleep enable" "0: UART4 is disabled in Sleep mode (default after..,1: UART4 is enabled in Sleep mode" newline bitfld.long 0x70 18. "USART3LPEN,USART3 sleep enable" "0: USART3 is disabled in Sleep mode (default after..,1: USART3 is enabled in Sleep mode" newline bitfld.long 0x70 17. "USART2LPEN,USART2 sleep enable" "0: USART2 is disabled in Sleep mode (default after..,1: USART2 is enabled in Sleep mode" newline bitfld.long 0x70 16. "SPDIFRX1LPEN,SPDIFRX1 sleep enable" "0: SPDIFRX1 is disabled in Sleep mode (default..,1: SPDIFRX1 is enabled in Sleep mode" newline bitfld.long 0x70 15. "SPI3LPEN,SPI3 sleep enable" "0: SPI3 is disabled in Sleep mode (default after..,1: SPI3 is enabled in Sleep mode" newline bitfld.long 0x70 14. "SPI2LPEN,SPI2 sleep enable" "0: SPI2 is disabled in Sleep mode (default after..,1: SPI2 is enabled in Sleep mode" newline bitfld.long 0x70 13. "TIM11LPEN,TIM11 sleep enable" "0: TIM11 is disabled in Sleep mode (default after..,1: TIM11 is enabled in Sleep mode" newline bitfld.long 0x70 12. "TIM10LPEN,TIM10 sleep enable" "0: TIM10 is disabled in Sleep mode (default after..,1: TIM10 is enabled in Sleep mode" newline bitfld.long 0x70 11. "WWDGLPEN,WWDG sleep enable" "0: WWDG is disabled in Sleep mode (default after..,1: WWDG is enabled in Sleep mode" newline bitfld.long 0x70 9. "LPTIM1LPEN,LPTIM1 sleep enable" "0: LPTIM1 is disabled in Sleep mode (default after..,1: LPTIM1 is enabled in Sleep mode" newline bitfld.long 0x70 8. "TIM14LPEN,TIM14 sleep enable" "0: TIM14 is disabled in Sleep mode (default after..,1: TIM14 is enabled in Sleep mode" newline bitfld.long 0x70 7. "TIM13LPEN,TIM13 sleep enable" "0: TIM13 is disabled in Sleep mode (default after..,1: TIM13 is enabled in Sleep mode" newline bitfld.long 0x70 6. "TIM12LPEN,TIM12 sleep enable" "0: TIM12 is disabled in Sleep mode (default after..,1: TIM12 is enabled in Sleep mode" newline bitfld.long 0x70 5. "TIM7LPEN,TIM7 sleep enable" "0: TIM7 is disabled in Sleep mode (default after..,1: TIM7 is enabled in Sleep mode" newline bitfld.long 0x70 4. "TIM6LPEN,TIM6 sleep enable" "0: TIM6 is disabled in Sleep mode (default after..,1: TIM6 is enabled in Sleep mode" newline bitfld.long 0x70 3. "TIM5LPEN,TIM5 sleep enable" "0: TIM5 is disabled in Sleep mode (default after..,1: TIM5 is enabled in Sleep mode" newline bitfld.long 0x70 2. "TIM4LPEN,TIM4 sleep enable" "0: TIM4 is disabled in Sleep mode (default after..,1: TIM4 is enabled in Sleep mode" newline bitfld.long 0x70 1. "TIM3LPEN,TIM3 sleep enable" "0: TIM3 is disabled in Sleep mode (default after..,1: TIM3 is enabled in Sleep mode" newline bitfld.long 0x70 0. "TIM2LPEN,TIM2 sleep enable" "0: TIM2 is disabled in Sleep mode (default after..,1: TIM2 is enabled in Sleep mode" line.long 0x74 "RCC_APB1HLPENR,RCC APB1H Sleep enable register" bitfld.long 0x74 18. "UCPD1LPEN,UCPD1 sleep enable" "0: UCPD1 is disabled in Sleep mode (default after..,1: UCPD1 is enabled in Sleep mode" newline bitfld.long 0x74 8. "FDCANLPEN,FDCAN sleep enable" "0: FDCAN is disabled in Sleep mode (default after..,1: FDCAN is enabled in Sleep mode" newline bitfld.long 0x74 5. "MDIOSLPEN,MDIOS sleep enable" "0: MDIOS is disabled in Sleep mode (default after..,1: MDIOS is enabled in Sleep mode" line.long 0x78 "RCC_APB2LPENR,RCC APB2 Sleep enable register" bitfld.long 0x78 22. "SAI2LPEN,SAI2 sleep enable" "0: SAI2 is disabled in Sleep mode (default after..,1: SAI2 is enabled in Sleep mode" newline bitfld.long 0x78 21. "SAI1LPEN,SAI1 sleep enable" "0: SAI1 is disabled in Sleep mode (default after..,1: SAI1 is enabled in Sleep mode" newline bitfld.long 0x78 20. "SPI5LPEN,SPI5 sleep enable" "0: SPI5 is disabled in Sleep mode (default after..,1: SPI5 is enabled in Sleep mode" newline bitfld.long 0x78 19. "TIM9LPEN,TIM9 sleep enable" "0: TIM9 is disabled in Sleep mode (default after..,1: TIM9 is enabled in Sleep mode" newline bitfld.long 0x78 18. "TIM17LPEN,TIM17 sleep enable" "0: TIM17 is disabled in Sleep mode (default after..,1: TIM17 is enabled in Sleep mode" newline bitfld.long 0x78 17. "TIM16LPEN,TIM16 sleep enable" "0: TIM16 is disabled in Sleep mode (default after..,1: TIM16 is enabled in Sleep mode" newline bitfld.long 0x78 16. "TIM15LPEN,TIM15 sleep enable" "0: TIM15 is disabled in Sleep mode (default after..,1: TIM15 is enabled in Sleep mode" newline bitfld.long 0x78 15. "TIM18LPEN,TIM18 sleep enable" "0: TIM18 is disabled in Sleep mode (default after..,1: TIM18 is enabled in Sleep mode" newline bitfld.long 0x78 13. "SPI4LPEN,SPI4 sleep enable" "0: SPI4 is disabled in Sleep mode (default after..,1: SPI4 is enabled in Sleep mode" newline bitfld.long 0x78 12. "SPI1LPEN,SPI1 sleep enable" "0: SPI1 is disabled in Sleep mode (default after..,1: SPI1 is enabled in Sleep mode" newline bitfld.long 0x78 7. "USART10LPEN,USART10 sleep enable" "0: USART10 is disabled in Sleep mode (default after..,1: USART10 is enabled in Sleep mode" newline bitfld.long 0x78 6. "UART9LPEN,UART9 sleep enable" "0: UART9 is disabled in Sleep mode (default after..,1: UART9 is enabled in Sleep mode" newline bitfld.long 0x78 5. "USART6LPEN,USART6 sleep enable" "0: USART6 is disabled in Sleep mode (default after..,1: USART6 is enabled in Sleep mode" newline bitfld.long 0x78 4. "USART1LPEN,USART1 sleep enable" "0: USART1 is disabled in Sleep mode (default after..,1: USART1 is enabled in Sleep mode" newline bitfld.long 0x78 1. "TIM8LPEN,TIM8 sleep enable" "0: TIM8 is disabled in Sleep mode (default after..,1: TIM8 is enabled in Sleep mode" newline bitfld.long 0x78 0. "TIM1LPEN,TIM1 sleep enable" "0: TIM1 is disabled in Sleep mode (default after..,1: TIM1 is enabled in Sleep mode" line.long 0x7C "RCC_APB3LPENR,RCC APB3 Sleep enable register" bitfld.long 0x7C 2. "DFTLPEN,DFT sleep enable" "0: DFT is disabled in Sleep mode (default after..,1: DFT is enabled in Sleep mode" line.long 0x80 "RCC_APB4LLPENR,RCC APB4L Sleep enable register" bitfld.long 0x80 31. "SERFLPEN,SERF sleep enable" "0: SERF is disabled in Sleep mode (default after..,1: SERF is enabled in Sleep mode" newline bitfld.long 0x80 23. "R2GNPULPEN,R2GNPU sleep enable" "0: R2GNPU is disabled in Sleep mode (default after..,1: R2GNPU is enabled in Sleep mode" newline bitfld.long 0x80 22. "R2GRETLPEN,R2GRET sleep enable" "0: R2GRET is disabled in Sleep mode (default after..,1: R2GRET is enabled in Sleep mode" newline bitfld.long 0x80 17. "RTCAPBLPEN,RTCAPB sleep enable" "0: RTCAPB is disabled in Sleep mode (default after..,1: RTCAPB is enabled in Sleep mode" newline bitfld.long 0x80 16. "RTCLPEN,RTC sleep enable" "0: RTC is disabled in Sleep mode (default after..,1: RTC is enabled in Sleep mode" newline bitfld.long 0x80 15. "VREFBUFLPEN,VREFBUF sleep enable" "0: VREFBUF is disabled in Sleep mode (default after..,1: VREFBUF is enabled in Sleep mode" newline bitfld.long 0x80 12. "LPTIM5LPEN,LPTIM5 sleep enable" "0: LPTIM5 is disabled in Sleep mode (default after..,1: LPTIM5 is enabled in Sleep mode" newline bitfld.long 0x80 11. "LPTIM4LPEN,LPTIM4 sleep enable" "0: LPTIM4 is disabled in Sleep mode (default after..,1: LPTIM4 is enabled in Sleep mode" newline bitfld.long 0x80 10. "LPTIM3LPEN,LPTIM3 sleep enable" "0: LPTIM3 is disabled in Sleep mode (default after..,1: LPTIM3 is enabled in Sleep mode" newline bitfld.long 0x80 9. "LPTIM2LPEN,LPTIM2 sleep enable" "0: LPTIM2 is disabled in Sleep mode (default after..,1: LPTIM2 is enabled in Sleep mode" newline bitfld.long 0x80 7. "I2C4LPEN,I2C4 sleep enable" "0: I2C4 is disabled in Sleep mode (default after..,1: I2C4 is enabled in Sleep mode" newline bitfld.long 0x80 5. "SPI6LPEN,SPI6 sleep enable" "0: SPI6 is disabled in Sleep mode (default after..,1: SPI6 is enabled in Sleep mode" newline bitfld.long 0x80 3. "LPUART1LPEN,LPUART1 sleep enable" "0: LPUART1 is disabled in Sleep mode (default after..,1: LPUART1 is enabled in Sleep mode" newline bitfld.long 0x80 2. "HDPLPEN,HDP sleep enable" "0: HDP is disabled in Sleep mode (default after..,1: HDP is enabled in Sleep mode" line.long 0x84 "RCC_APB4HLPENR,RCC APB4H Sleep enable register" bitfld.long 0x84 4. "BUSPERFMLPEN,BUSPERFM sleep enable" "0: BUSPERFM is disabled in Sleep mode (default..,1: BUSPERFM is enabled in Sleep mode" newline bitfld.long 0x84 2. "DTSLPEN,DTS sleep enable" "0: DTS is disabled in Sleep mode (default after..,1: DTS is enabled in Sleep mode" newline bitfld.long 0x84 1. "BSECLPEN,BSEC sleep enable" "0: BSEC is disabled in Sleep mode,1: BSEC is enabled in Sleep mode (default after.." newline bitfld.long 0x84 0. "SYSCFGLPEN,SYSCFG sleep enable" "0: SYSCFG is disabled in Sleep mode (default after..,1: SYSCFG is enabled in Sleep mode" line.long 0x88 "RCC_APB5LPENR,RCC APB5 Sleep enable register" bitfld.long 0x88 6. "CSILPEN,CSI sleep enable" "0: CSI is disabled in Sleep mode (default after..,1: CSI is enabled in Sleep mode" newline bitfld.long 0x88 5. "VENCLPEN,VENC sleep enable" "0: VENC is disabled in Sleep mode (default after..,1: VENC is enabled in Sleep mode" newline bitfld.long 0x88 4. "GFXTIMLPEN,GFXTIM sleep enable" "0: GFXTIM is disabled in Sleep mode (default after..,1: GFXTIM is enabled in Sleep mode" newline bitfld.long 0x88 2. "DCMIPPLPEN,DCMIPP sleep enable" "0: DCMIPP is disabled in Sleep mode (default after..,1: DCMIPP is enabled in Sleep mode" newline bitfld.long 0x88 1. "LTDCLPEN,LTDC sleep enable" "0: LTDC is disabled in Sleep mode (default after..,1: LTDC is enabled in Sleep mode" group.long 0x44C++0x3 line.long 0x0 "RCC_RDCR,RCC APB5 Sleep enable register" hexmask.long.byte 0x0 24.--27. 1. "EADLY,BOOTROM sleep enable" newline hexmask.long.byte 0x0 16.--20. 1. "MRD,BOOTROM sleep enable" group.long 0x780++0x7 line.long 0x0 "RCC_SECCFGR0,RCC oscillator secure configuration register0" bitfld.long 0x0 4. "HSESEC,Defines the secure protection of the HSE oscillator configuration bits." "0: HSE configuration bits are accessible by..,1: HSE configuration bits are accessible by secure.." newline bitfld.long 0x0 3. "HSISEC,Defines the secure protection of the HSI oscillator configuration bits." "0: HSI configuration bits are accessible by..,1: HSI configuration bits are accessible by secure.." newline bitfld.long 0x0 2. "MSISEC,Defines the secure protection of the MSI oscillator configuration bits." "0: MSI configuration bits are accessible by..,1: MSI configuration bits are accessible by secure.." newline bitfld.long 0x0 1. "LSESEC,Defines the secure protection of the LSE oscillator configuration bits." "0: LSE configuration bits are accessible by..,1: LSE configuration bits are accessible by secure.." newline bitfld.long 0x0 0. "LSISEC,Defines the secure protection of the LSI oscillator configuration bits." "0: LSI configuration bits are accessible by..,1: LSI configuration bits are accessible by secure.." line.long 0x4 "RCC_PRIVCFGR0,RCC oscillator privilege configuration register0" bitfld.long 0x4 4. "HSEPV,Defines the privilege protection of the HSE oscillator configuration bits." "0: HSE configuration bits are accessible by..,1: HSE configuration bits are accessible by.." newline bitfld.long 0x4 3. "HSIPV,Defines the privilege protection of the HSI oscillator configuration bits." "0: HSI configuration bits are accessible by..,1: HSI configuration bits are accessible by.." newline bitfld.long 0x4 2. "MSIPV,Defines the privilege protection of the MSI oscillator configuration bits." "0: MSI configuration bits are accessible by..,1: MSI configuration bits are accessible by.." newline bitfld.long 0x4 1. "LSEPV,Defines the privilege protection of the LSE oscillator configuration bits." "0: LSE configuration bits are accessible by..,1: LSE configuration bits are accessible by.." newline bitfld.long 0x4 0. "LSIPV,Defines the privilege protection of the LSI oscillator configuration bits." "0: LSI configuration bits are accessible by..,1: LSI configuration bits are accessible by.." wgroup.long 0x788++0x3 line.long 0x0 "RCC_LOCKCFGR0,RCC oscillator lock configuration register0" bitfld.long 0x0 4. "HSELOCK,Defines the lock protection of the HSE oscillator configuration bits." "0: HSE configuration bits are accessible by..,1: HSE configuration bits are accessible by lock.." newline bitfld.long 0x0 3. "HSILOCK,Defines the lock protection of the HSI oscillator configuration bits." "0: HSI configuration bits are accessible by..,1: HSI configuration bits are accessible by lock.." newline bitfld.long 0x0 2. "MSILOCK,Defines the lock protection of the MSI oscillator configuration bits." "0: MSI configuration bits are accessible by..,1: MSI configuration bits are accessible by lock.." newline bitfld.long 0x0 1. "LSELOCK,Defines the lock protection of the LSE oscillator configuration bits." "0: LSE configuration bits are accessible by..,1: LSE configuration bits are accessible by lock.." newline bitfld.long 0x0 0. "LSILOCK,Defines the lock protection of the LSI oscillator configuration bits." "0: LSI configuration bits are accessible by..,1: LSI configuration bits are accessible by lock.." group.long 0x78C++0xB line.long 0x0 "RCC_PUBCFGR0,RCC oscillator public configuration register0" bitfld.long 0x0 4. "HSEPUB,Defines the public protection of the HSE oscillator configuration bits." "0: HSE configuration bits are accessible by..,1: HSE configuration bits are accessible by public.." newline bitfld.long 0x0 3. "HSIPUB,Defines the public protection of the HSI oscillator configuration bits." "0: HSI configuration bits are accessible by..,1: HSI configuration bits are accessible by public.." newline bitfld.long 0x0 2. "MSIPUB,Defines the public protection of the MSI oscillator configuration bits." "0: MSI configuration bits are accessible by..,1: MSI configuration bits are accessible by public.." newline bitfld.long 0x0 1. "LSEPUB,Defines the public protection of the LSE oscillator configuration bits." "0: LSE configuration bits are accessible by..,1: LSE configuration bits are accessible by public.." newline bitfld.long 0x0 0. "LSIPUB,Defines the public protection of the LSI oscillator configuration bits." "0: LSI configuration bits are accessible by..,1: LSI configuration bits are accessible by public.." line.long 0x4 "RCC_SECCFGR1,RCC PLL secure configuration register1" bitfld.long 0x4 3. "PLL4SEC,Defines the secure protection of the PLL4 PLL configuration bits." "0: PLL4 configuration bits are accessible by..,1: PLL4 configuration bits are accessible by secure.." newline bitfld.long 0x4 2. "PLL3SEC,Defines the secure protection of the PLL3 PLL configuration bits." "0: PLL3 configuration bits are accessible by..,1: PLL3 configuration bits are accessible by secure.." newline bitfld.long 0x4 1. "PLL2SEC,Defines the secure protection of the PLL2 PLL configuration bits." "0: PLL2 configuration bits are accessible by..,1: PLL2 configuration bits are accessible by secure.." newline bitfld.long 0x4 0. "PLL1SEC,Defines the secure protection of the PLL1 PLL configuration bits." "0: PLL1 configuration bits are accessible by..,1: PLL1 configuration bits are accessible by secure.." line.long 0x8 "RCC_PRIVCFGR1,RCC PLL privilege configuration register1" bitfld.long 0x8 3. "PLL4PV,Defines the privilege protection of the PLL4 PLL configuration bits." "0: PLL4 configuration bits are accessible by..,1: PLL4 configuration bits are accessible by.." newline bitfld.long 0x8 2. "PLL3PV,Defines the privilege protection of the PLL3 PLL configuration bits." "0: PLL3 configuration bits are accessible by..,1: PLL3 configuration bits are accessible by.." newline bitfld.long 0x8 1. "PLL2PV,Defines the privilege protection of the PLL2 PLL configuration bits." "0: PLL2 configuration bits are accessible by..,1: PLL2 configuration bits are accessible by.." newline bitfld.long 0x8 0. "PLL1PV,Defines the privilege protection of the PLL1 PLL configuration bits." "0: PLL1 configuration bits are accessible by..,1: PLL1 configuration bits are accessible by.." wgroup.long 0x798++0x3 line.long 0x0 "RCC_LOCKCFGR1,RCC PLL lock configuration register1" bitfld.long 0x0 3. "PLL4LOCK,Defines the lock protection of the PLL4 PLL configuration bits." "0: PLL4 configuration bits are accessible by..,1: PLL4 configuration bits are accessible by lock.." newline bitfld.long 0x0 2. "PLL3LOCK,Defines the lock protection of the PLL3 PLL configuration bits." "0: PLL3 configuration bits are accessible by..,1: PLL3 configuration bits are accessible by lock.." newline bitfld.long 0x0 1. "PLL2LOCK,Defines the lock protection of the PLL2 PLL configuration bits." "0: PLL2 configuration bits are accessible by..,1: PLL2 configuration bits are accessible by lock.." newline bitfld.long 0x0 0. "PLL1LOCK,Defines the lock protection of the PLL1 PLL configuration bits." "0: PLL1 configuration bits are accessible by..,1: PLL1 configuration bits are accessible by lock.." group.long 0x79C++0xB line.long 0x0 "RCC_PUBCFGR1,RCC PLL public configuration register1" bitfld.long 0x0 3. "PLL4PUB,Defines the public protection of the PLL4 PLL configuration bits." "0: PLL4 configuration bits are accessible by..,1: PLL4 configuration bits are accessible by public.." newline bitfld.long 0x0 2. "PLL3PUB,Defines the public protection of the PLL3 PLL configuration bits." "0: PLL3 configuration bits are accessible by..,1: PLL3 configuration bits are accessible by public.." newline bitfld.long 0x0 1. "PLL2PUB,Defines the public protection of the PLL2 PLL configuration bits." "0: PLL2 configuration bits are accessible by..,1: PLL2 configuration bits are accessible by public.." newline bitfld.long 0x0 0. "PLL1PUB,Defines the public protection of the PLL1 PLL configuration bits." "0: PLL1 configuration bits are accessible by..,1: PLL1 configuration bits are accessible by public.." line.long 0x4 "RCC_SECCFGR2,RCC divider secure configuration register2" bitfld.long 0x4 19. "IC20SEC,Defines the secure protection of the IC20 divider configuration bits." "0: IC20 configuration bits are accessible by..,1: IC20 configuration bits are accessible by secure.." newline bitfld.long 0x4 18. "IC19SEC,Defines the secure protection of the IC19 divider configuration bits." "0: IC19 configuration bits are accessible by..,1: IC19 configuration bits are accessible by secure.." newline bitfld.long 0x4 17. "IC18SEC,Defines the secure protection of the IC18 divider configuration bits." "0: IC18 configuration bits are accessible by..,1: IC18 configuration bits are accessible by secure.." newline bitfld.long 0x4 16. "IC17SEC,Defines the secure protection of the IC17 divider configuration bits." "0: IC17 configuration bits are accessible by..,1: IC17 configuration bits are accessible by secure.." newline bitfld.long 0x4 15. "IC16SEC,Defines the secure protection of the IC16 divider configuration bits." "0: IC16 configuration bits are accessible by..,1: IC16 configuration bits are accessible by secure.." newline bitfld.long 0x4 14. "IC15SEC,Defines the secure protection of the IC15 divider configuration bits." "0: IC15 configuration bits are accessible by..,1: IC15 configuration bits are accessible by secure.." newline bitfld.long 0x4 13. "IC14SEC,Defines the secure protection of the IC14 divider configuration bits." "0: IC14 configuration bits are accessible by..,1: IC14 configuration bits are accessible by secure.." newline bitfld.long 0x4 12. "IC13SEC,Defines the secure protection of the IC13 divider configuration bits." "0: IC13 configuration bits are accessible by..,1: IC13 configuration bits are accessible by secure.." newline bitfld.long 0x4 11. "IC12SEC,Defines the secure protection of the IC12 divider configuration bits." "0: IC12 configuration bits are accessible by..,1: IC12 configuration bits are accessible by secure.." newline bitfld.long 0x4 10. "IC11SEC,Defines the secure protection of the IC11 divider configuration bits." "0: IC11 configuration bits are accessible by..,1: IC11 configuration bits are accessible by secure.." newline bitfld.long 0x4 9. "IC10SEC,Defines the secure protection of the IC10 divider configuration bits." "0: IC10 configuration bits are accessible by..,1: IC10 configuration bits are accessible by secure.." newline bitfld.long 0x4 8. "IC9SEC,Defines the secure protection of the IC9 divider configuration bits." "0: IC9 configuration bits are accessible by..,1: IC9 configuration bits are accessible by secure.." newline bitfld.long 0x4 7. "IC8SEC,Defines the secure protection of the IC8 divider configuration bits." "0: IC8 configuration bits are accessible by..,1: IC8 configuration bits are accessible by secure.." newline bitfld.long 0x4 6. "IC7SEC,Defines the secure protection of the IC7 divider configuration bits." "0: IC7 configuration bits are accessible by..,1: IC7 configuration bits are accessible by secure.." newline bitfld.long 0x4 5. "IC6SEC,Defines the secure protection of the IC6 divider configuration bits." "0: IC6 configuration bits are accessible by..,1: IC6 configuration bits are accessible by secure.." newline bitfld.long 0x4 4. "IC5SEC,Defines the secure protection of the IC5 divider configuration bits." "0: IC5 configuration bits are accessible by..,1: IC5 configuration bits are accessible by secure.." newline bitfld.long 0x4 3. "IC4SEC,Defines the secure protection of the IC4 divider configuration bits." "0: IC4 configuration bits are accessible by..,1: IC4 configuration bits are accessible by secure.." newline bitfld.long 0x4 2. "IC3SEC,Defines the secure protection of the IC3 divider configuration bits." "0: IC3 configuration bits are accessible by..,1: IC3 configuration bits are accessible by secure.." newline bitfld.long 0x4 1. "IC2SEC,Defines the secure protection of the IC2 divider configuration bits." "0: IC2 configuration bits are accessible by..,1: IC2 configuration bits are accessible by secure.." newline bitfld.long 0x4 0. "IC1SEC,Defines the secure protection of the IC1 divider configuration bits." "0: IC1 configuration bits are accessible by..,1: IC1 configuration bits are accessible by secure.." line.long 0x8 "RCC_PRIVCFGR2,RCC divider privilege configuration register2" bitfld.long 0x8 19. "IC20PV,Defines the privilege protection of the IC20 divider configuration bits." "0: IC20 configuration bits are accessible by..,1: IC20 configuration bits are accessible by.." newline bitfld.long 0x8 18. "IC19PV,Defines the privilege protection of the IC19 divider configuration bits." "0: IC19 configuration bits are accessible by..,1: IC19 configuration bits are accessible by.." newline bitfld.long 0x8 17. "IC18PV,Defines the privilege protection of the IC18 divider configuration bits." "0: IC18 configuration bits are accessible by..,1: IC18 configuration bits are accessible by.." newline bitfld.long 0x8 16. "IC17PV,Defines the privilege protection of the IC17 divider configuration bits." "0: IC17 configuration bits are accessible by..,1: IC17 configuration bits are accessible by.." newline bitfld.long 0x8 15. "IC16PV,Defines the privilege protection of the IC16 divider configuration bits." "0: IC16 configuration bits are accessible by..,1: IC16 configuration bits are accessible by.." newline bitfld.long 0x8 14. "IC15PV,Defines the privilege protection of the IC15 divider configuration bits." "0: IC15 configuration bits are accessible by..,1: IC15 configuration bits are accessible by.." newline bitfld.long 0x8 13. "IC14PV,Defines the privilege protection of the IC14 divider configuration bits." "0: IC14 configuration bits are accessible by..,1: IC14 configuration bits are accessible by.." newline bitfld.long 0x8 12. "IC13PV,Defines the privilege protection of the IC13 divider configuration bits." "0: IC13 configuration bits are accessible by..,1: IC13 configuration bits are accessible by.." newline bitfld.long 0x8 11. "IC12PV,Defines the privilege protection of the IC12 divider configuration bits." "0: IC12 configuration bits are accessible by..,1: IC12 configuration bits are accessible by.." newline bitfld.long 0x8 10. "IC11PV,Defines the privilege protection of the IC11 divider configuration bits." "0: IC11 configuration bits are accessible by..,1: IC11 configuration bits are accessible by.." newline bitfld.long 0x8 9. "IC10PV,Defines the privilege protection of the IC10 divider configuration bits." "0: IC10 configuration bits are accessible by..,1: IC10 configuration bits are accessible by.." newline bitfld.long 0x8 8. "IC9PV,Defines the privilege protection of the IC9 divider configuration bits." "0: IC9 configuration bits are accessible by..,1: IC9 configuration bits are accessible by.." newline bitfld.long 0x8 7. "IC8PV,Defines the privilege protection of the IC8 divider configuration bits." "0: IC8 configuration bits are accessible by..,1: IC8 configuration bits are accessible by.." newline bitfld.long 0x8 6. "IC7PV,Defines the privilege protection of the IC7 divider configuration bits." "0: IC7 configuration bits are accessible by..,1: IC7 configuration bits are accessible by.." newline bitfld.long 0x8 5. "IC6PV,Defines the privilege protection of the IC6 divider configuration bits." "0: IC6 configuration bits are accessible by..,1: IC6 configuration bits are accessible by.." newline bitfld.long 0x8 4. "IC5PV,Defines the privilege protection of the IC5 divider configuration bits." "0: IC5 configuration bits are accessible by..,1: IC5 configuration bits are accessible by.." newline bitfld.long 0x8 3. "IC4PV,Defines the privilege protection of the IC4 divider configuration bits." "0: IC4 configuration bits are accessible by..,1: IC4 configuration bits are accessible by.." newline bitfld.long 0x8 2. "IC3PV,Defines the privilege protection of the IC3 divider configuration bits." "0: IC3 configuration bits are accessible by..,1: IC3 configuration bits are accessible by.." newline bitfld.long 0x8 1. "IC2PV,Defines the privilege protection of the IC2 divider configuration bits." "0: IC2 configuration bits are accessible by..,1: IC2 configuration bits are accessible by.." newline bitfld.long 0x8 0. "IC1PV,Defines the privilege protection of the IC1 divider configuration bits." "0: IC1 configuration bits are accessible by..,1: IC1 configuration bits are accessible by.." wgroup.long 0x7A8++0x3 line.long 0x0 "RCC_LOCKCFGR2,RCC divider lock configuration register2" bitfld.long 0x0 19. "IC20LOCK,Defines the lock protection of the IC20 divider configuration bits." "0: IC20 configuration bits are accessible by..,1: IC20 configuration bits are accessible by lock.." newline bitfld.long 0x0 18. "IC19LOCK,Defines the lock protection of the IC19 divider configuration bits." "0: IC19 configuration bits are accessible by..,1: IC19 configuration bits are accessible by lock.." newline bitfld.long 0x0 17. "IC18LOCK,Defines the lock protection of the IC18 divider configuration bits." "0: IC18 configuration bits are accessible by..,1: IC18 configuration bits are accessible by lock.." newline bitfld.long 0x0 16. "IC17LOCK,Defines the lock protection of the IC17 divider configuration bits." "0: IC17 configuration bits are accessible by..,1: IC17 configuration bits are accessible by lock.." newline bitfld.long 0x0 15. "IC16LOCK,Defines the lock protection of the IC16 divider configuration bits." "0: IC16 configuration bits are accessible by..,1: IC16 configuration bits are accessible by lock.." newline bitfld.long 0x0 14. "IC15LOCK,Defines the lock protection of the IC15 divider configuration bits." "0: IC15 configuration bits are accessible by..,1: IC15 configuration bits are accessible by lock.." newline bitfld.long 0x0 13. "IC14LOCK,Defines the lock protection of the IC14 divider configuration bits." "0: IC14 configuration bits are accessible by..,1: IC14 configuration bits are accessible by lock.." newline bitfld.long 0x0 12. "IC13LOCK,Defines the lock protection of the IC13 divider configuration bits." "0: IC13 configuration bits are accessible by..,1: IC13 configuration bits are accessible by lock.." newline bitfld.long 0x0 11. "IC12LOCK,Defines the lock protection of the IC12 divider configuration bits." "0: IC12 configuration bits are accessible by..,1: IC12 configuration bits are accessible by lock.." newline bitfld.long 0x0 10. "IC11LOCK,Defines the lock protection of the IC11 divider configuration bits." "0: IC11 configuration bits are accessible by..,1: IC11 configuration bits are accessible by lock.." newline bitfld.long 0x0 9. "IC10LOCK,Defines the lock protection of the IC10 divider configuration bits." "0: IC10 configuration bits are accessible by..,1: IC10 configuration bits are accessible by lock.." newline bitfld.long 0x0 8. "IC9LOCK,Defines the lock protection of the IC9 divider configuration bits." "0: IC9 configuration bits are accessible by..,1: IC9 configuration bits are accessible by lock.." newline bitfld.long 0x0 7. "IC8LOCK,Defines the lock protection of the IC8 divider configuration bits." "0: IC8 configuration bits are accessible by..,1: IC8 configuration bits are accessible by lock.." newline bitfld.long 0x0 6. "IC7LOCK,Defines the lock protection of the IC7 divider configuration bits." "0: IC7 configuration bits are accessible by..,1: IC7 configuration bits are accessible by lock.." newline bitfld.long 0x0 5. "IC6LOCK,Defines the lock protection of the IC6 divider configuration bits." "0: IC6 configuration bits are accessible by..,1: IC6 configuration bits are accessible by lock.." newline bitfld.long 0x0 4. "IC5LOCK,Defines the lock protection of the IC5 divider configuration bits." "0: IC5 configuration bits are accessible by..,1: IC5 configuration bits are accessible by lock.." newline bitfld.long 0x0 3. "IC4LOCK,Defines the lock protection of the IC4 divider configuration bits." "0: IC4 configuration bits are accessible by..,1: IC4 configuration bits are accessible by lock.." newline bitfld.long 0x0 2. "IC3LOCK,Defines the lock protection of the IC3 divider configuration bits." "0: IC3 configuration bits are accessible by..,1: IC3 configuration bits are accessible by lock.." newline bitfld.long 0x0 1. "IC2LOCK,Defines the lock protection of the IC2 divider configuration bits." "0: IC2 configuration bits are accessible by..,1: IC2 configuration bits are accessible by lock.." newline bitfld.long 0x0 0. "IC1LOCK,Defines the lock protection of the IC1 divider configuration bits." "0: IC1 configuration bits are accessible by..,1: IC1 configuration bits are accessible by lock.." group.long 0x7AC++0xB line.long 0x0 "RCC_PUBCFGR2,RCC divider public configuration register2" bitfld.long 0x0 19. "IC20PUB,Defines the public protection of the IC20 divider configuration bits." "0: IC20 configuration bits are accessible by..,1: IC20 configuration bits are accessible by public.." newline bitfld.long 0x0 18. "IC19PUB,Defines the public protection of the IC19 divider configuration bits." "0: IC19 configuration bits are accessible by..,1: IC19 configuration bits are accessible by public.." newline bitfld.long 0x0 17. "IC18PUB,Defines the public protection of the IC18 divider configuration bits." "0: IC18 configuration bits are accessible by..,1: IC18 configuration bits are accessible by public.." newline bitfld.long 0x0 16. "IC17PUB,Defines the public protection of the IC17 divider configuration bits." "0: IC17 configuration bits are accessible by..,1: IC17 configuration bits are accessible by public.." newline bitfld.long 0x0 15. "IC16PUB,Defines the public protection of the IC16 divider configuration bits." "0: IC16 configuration bits are accessible by..,1: IC16 configuration bits are accessible by public.." newline bitfld.long 0x0 14. "IC15PUB,Defines the public protection of the IC15 divider configuration bits." "0: IC15 configuration bits are accessible by..,1: IC15 configuration bits are accessible by public.." newline bitfld.long 0x0 13. "IC14PUB,Defines the public protection of the IC14 divider configuration bits." "0: IC14 configuration bits are accessible by..,1: IC14 configuration bits are accessible by public.." newline bitfld.long 0x0 12. "IC13PUB,Defines the public protection of the IC13 divider configuration bits." "0: IC13 configuration bits are accessible by..,1: IC13 configuration bits are accessible by public.." newline bitfld.long 0x0 11. "IC12PUB,Defines the public protection of the IC12 divider configuration bits." "0: IC12 configuration bits are accessible by..,1: IC12 configuration bits are accessible by public.." newline bitfld.long 0x0 10. "IC11PUB,Defines the public protection of the IC11 divider configuration bits." "0: IC11 configuration bits are accessible by..,1: IC11 configuration bits are accessible by public.." newline bitfld.long 0x0 9. "IC10PUB,Defines the public protection of the IC10 divider configuration bits." "0: IC10 configuration bits are accessible by..,1: IC10 configuration bits are accessible by public.." newline bitfld.long 0x0 8. "IC9PUB,Defines the public protection of the IC9 divider configuration bits." "0: IC9 configuration bits are accessible by..,1: IC9 configuration bits are accessible by public.." newline bitfld.long 0x0 7. "IC8PUB,Defines the public protection of the IC8 divider configuration bits." "0: IC8 configuration bits are accessible by..,1: IC8 configuration bits are accessible by public.." newline bitfld.long 0x0 6. "IC7PUB,Defines the public protection of the IC7 divider configuration bits." "0: IC7 configuration bits are accessible by..,1: IC7 configuration bits are accessible by public.." newline bitfld.long 0x0 5. "IC6PUB,Defines the public protection of the IC6 divider configuration bits." "0: IC6 configuration bits are accessible by..,1: IC6 configuration bits are accessible by public.." newline bitfld.long 0x0 4. "IC5PUB,Defines the public protection of the IC5 divider configuration bits." "0: IC5 configuration bits are accessible by..,1: IC5 configuration bits are accessible by public.." newline bitfld.long 0x0 3. "IC4PUB,Defines the public protection of the IC4 divider configuration bits." "0: IC4 configuration bits are accessible by..,1: IC4 configuration bits are accessible by public.." newline bitfld.long 0x0 2. "IC3PUB,Defines the public protection of the IC3 divider configuration bits." "0: IC3 configuration bits are accessible by..,1: IC3 configuration bits are accessible by public.." newline bitfld.long 0x0 1. "IC2PUB,Defines the public protection of the IC2 divider configuration bits." "0: IC2 configuration bits are accessible by..,1: IC2 configuration bits are accessible by public.." newline bitfld.long 0x0 0. "IC1PUB,Defines the public protection of the IC1 divider configuration bits." "0: IC1 configuration bits are accessible by..,1: IC1 configuration bits are accessible by public.." line.long 0x4 "RCC_SECCFGR3,RCC system secure configuration register3" bitfld.long 0x4 6. "DFTSEC,Defines the secure protection of the DFT system configuration bits." "0: DFT configuration bits are accessible by..,1: DFT configuration bits are accessible by secure.." newline bitfld.long 0x4 5. "RSTSEC,Defines the secure protection of the RST system configuration bits." "0: RST configuration bits are accessible by..,1: RST configuration bits are accessible by secure.." newline bitfld.long 0x4 4. "INTSEC,Defines the secure protection of the INT system configuration bits." "0: INT configuration bits are accessible by..,1: INT configuration bits are accessible by secure.." newline bitfld.long 0x4 3. "PERSEC,Defines the secure protection of the PER system configuration bits." "0: PER configuration bits are accessible by..,1: PER configuration bits are accessible by secure.." newline bitfld.long 0x4 2. "BUSSEC,Defines the secure protection of the BUS system configuration bits." "0: BUS configuration bits are accessible by..,1: BUS configuration bits are accessible by secure.." newline bitfld.long 0x4 1. "SYSSEC,Defines the secure protection of the SYS system configuration bits." "0: SYS configuration bits are accessible by..,1: SYS configuration bits are accessible by secure.." newline bitfld.long 0x4 0. "MODSEC,Defines the secure protection of the MOD system configuration bits." "0: MOD configuration bits are accessible by..,1: MOD configuration bits are accessible by secure.." line.long 0x8 "RCC_PRIVCFGR3,RCC system privilege configuration register3" bitfld.long 0x8 6. "DFTPV,Defines the privilege protection of the DFT system configuration bits." "0: DFT configuration bits are accessible by..,1: DFT configuration bits are accessible by.." newline bitfld.long 0x8 5. "RSTPV,Defines the privilege protection of the RST system configuration bits." "0: RST configuration bits are accessible by..,1: RST configuration bits are accessible by.." newline bitfld.long 0x8 4. "INTPV,Defines the privilege protection of the INT system configuration bits." "0: INT configuration bits are accessible by..,1: INT configuration bits are accessible by.." newline bitfld.long 0x8 3. "PERPV,Defines the privilege protection of the PER system configuration bits." "0: PER configuration bits are accessible by..,1: PER configuration bits are accessible by.." newline bitfld.long 0x8 2. "BUSPV,Defines the privilege protection of the BUS system configuration bits." "0: BUS configuration bits are accessible by..,1: BUS configuration bits are accessible by.." newline bitfld.long 0x8 1. "SYSPV,Defines the privilege protection of the SYS system configuration bits." "0: SYS configuration bits are accessible by..,1: SYS configuration bits are accessible by.." newline bitfld.long 0x8 0. "MODPV,Defines the privilege protection of the MOD system configuration bits." "0: MOD configuration bits are accessible by..,1: MOD configuration bits are accessible by.." wgroup.long 0x7B8++0x3 line.long 0x0 "RCC_LOCKCFGR3,RCC system lock configuration register3" bitfld.long 0x0 6. "DFTLOCK,Defines the lock protection of the DFT system configuration bits." "0: DFT configuration bits are accessible by..,1: DFT configuration bits are accessible by lock.." newline bitfld.long 0x0 5. "RSTLOCK,Defines the lock protection of the RST system configuration bits." "0: RST configuration bits are accessible by..,1: RST configuration bits are accessible by lock.." newline bitfld.long 0x0 4. "INTLOCK,Defines the lock protection of the INT system configuration bits." "0: INT configuration bits are accessible by..,1: INT configuration bits are accessible by lock.." newline bitfld.long 0x0 3. "PERLOCK,Defines the lock protection of the PER system configuration bits." "0: PER configuration bits are accessible by..,1: PER configuration bits are accessible by lock.." newline bitfld.long 0x0 2. "BUSLOCK,Defines the lock protection of the BUS system configuration bits." "0: BUS configuration bits are accessible by..,1: BUS configuration bits are accessible by lock.." newline bitfld.long 0x0 1. "SYSLOCK,Defines the lock protection of the SYS system configuration bits." "0: SYS configuration bits are accessible by..,1: SYS configuration bits are accessible by lock.." newline bitfld.long 0x0 0. "MODLOCK,Defines the lock protection of the MOD system configuration bits." "0: MOD configuration bits are accessible by..,1: MOD configuration bits are accessible by lock.." group.long 0x7BC++0xB line.long 0x0 "RCC_PUBCFGR3,RCC system public configuration register3" bitfld.long 0x0 6. "DFTPUB,Defines the public protection of the DFT system configuration bits." "0: DFT configuration bits are accessible by..,1: DFT configuration bits are accessible by public.." newline bitfld.long 0x0 5. "RSTPUB,Defines the public protection of the RST system configuration bits." "0: RST configuration bits are accessible by..,1: RST configuration bits are accessible by public.." newline bitfld.long 0x0 4. "INTPUB,Defines the public protection of the INT system configuration bits." "0: INT configuration bits are accessible by..,1: INT configuration bits are accessible by public.." newline bitfld.long 0x0 3. "PERPUB,Defines the public protection of the PER system configuration bits." "0: PER configuration bits are accessible by..,1: PER configuration bits are accessible by public.." newline bitfld.long 0x0 2. "BUSPUB,Defines the public protection of the BUS system configuration bits." "0: BUS configuration bits are accessible by..,1: BUS configuration bits are accessible by public.." newline bitfld.long 0x0 1. "SYSPUB,Defines the public protection of the SYS system configuration bits." "0: SYS configuration bits are accessible by..,1: SYS configuration bits are accessible by public.." newline bitfld.long 0x0 0. "MODPUB,Defines the public protection of the MOD system configuration bits." "0: MOD configuration bits are accessible by..,1: MOD configuration bits are accessible by public.." line.long 0x4 "RCC_SECCFGR4,RCC bus secure configuration register4" bitfld.long 0x4 13. "NOCSEC,Defines the secure protection of the NOC bus configuration bits." "0: NOC configuration bits are accessible by..,1: NOC configuration bits are accessible by secure.." newline bitfld.long 0x4 12. "APB5SEC,Defines the secure protection of the APB5 bus configuration bits." "0: APB5 configuration bits are accessible by..,1: APB5 configuration bits are accessible by secure.." newline bitfld.long 0x4 11. "APB4SEC,Defines the secure protection of the APB4 bus configuration bits." "0: APB4 configuration bits are accessible by..,1: APB4 configuration bits are accessible by secure.." newline bitfld.long 0x4 10. "APB3SEC,Defines the secure protection of the APB3 bus configuration bits." "0: APB3 configuration bits are accessible by..,1: APB3 configuration bits are accessible by secure.." newline bitfld.long 0x4 9. "APB2SEC,Defines the secure protection of the APB2 bus configuration bits." "0: APB2 configuration bits are accessible by..,1: APB2 configuration bits are accessible by secure.." newline bitfld.long 0x4 8. "APB1SEC,Defines the secure protection of the APB1 bus configuration bits." "0: APB1 configuration bits are accessible by..,1: APB1 configuration bits are accessible by secure.." newline bitfld.long 0x4 7. "AHB5SEC,Defines the secure protection of the AHB5 bus configuration bits." "0: AHB5 configuration bits are accessible by..,1: AHB5 configuration bits are accessible by secure.." newline bitfld.long 0x4 6. "AHB4SEC,Defines the secure protection of the AHB4 bus configuration bits." "0: AHB4 configuration bits are accessible by..,1: AHB4 configuration bits are accessible by secure.." newline bitfld.long 0x4 5. "AHB3SEC,Defines the secure protection of the AHB3 bus configuration bits." "0: AHB3 configuration bits are accessible by..,1: AHB3 configuration bits are accessible by secure.." newline bitfld.long 0x4 4. "AHB2SEC,Defines the secure protection of the AHB2 bus configuration bits." "0: AHB2 configuration bits are accessible by..,1: AHB2 configuration bits are accessible by secure.." newline bitfld.long 0x4 3. "AHB1SEC,Defines the secure protection of the AHB1 bus configuration bits." "0: AHB1 configuration bits are accessible by..,1: AHB1 configuration bits are accessible by secure.." newline bitfld.long 0x4 2. "AHBMSEC,Defines the secure protection of the AHBM bus configuration bits." "0: AHBM configuration bits are accessible by..,1: AHBM configuration bits are accessible by secure.." newline bitfld.long 0x4 1. "ACLKNCSEC,Defines the secure protection of the ACLKNC bus configuration bits." "0: ACLKNC configuration bits are accessible by..,1: ACLKNC configuration bits are accessible by.." newline bitfld.long 0x4 0. "ACLKNSEC,Defines the secure protection of the ACLKN bus configuration bits." "0: ACLKN configuration bits are accessible by..,1: ACLKN configuration bits are accessible by.." line.long 0x8 "RCC_PRIVCFGR4,RCC bus privilege configuration register4" bitfld.long 0x8 13. "NOCPV,Defines the privilege protection of the NOC bus configuration bits." "0: NOC configuration bits are accessible by..,1: NOC configuration bits are accessible by.." newline bitfld.long 0x8 12. "APB5PV,Defines the privilege protection of the APB5 bus configuration bits." "0: APB5 configuration bits are accessible by..,1: APB5 configuration bits are accessible by.." newline bitfld.long 0x8 11. "APB4PV,Defines the privilege protection of the APB4 bus configuration bits." "0: APB4 configuration bits are accessible by..,1: APB4 configuration bits are accessible by.." newline bitfld.long 0x8 10. "APB3PV,Defines the privilege protection of the APB3 bus configuration bits." "0: APB3 configuration bits are accessible by..,1: APB3 configuration bits are accessible by.." newline bitfld.long 0x8 9. "APB2PV,Defines the privilege protection of the APB2 bus configuration bits." "0: APB2 configuration bits are accessible by..,1: APB2 configuration bits are accessible by.." newline bitfld.long 0x8 8. "APB1PV,Defines the privilege protection of the APB1 bus configuration bits." "0: APB1 configuration bits are accessible by..,1: APB1 configuration bits are accessible by.." newline bitfld.long 0x8 7. "AHB5PV,Defines the privilege protection of the AHB5 bus configuration bits." "0: AHB5 configuration bits are accessible by..,1: AHB5 configuration bits are accessible by.." newline bitfld.long 0x8 6. "AHB4PV,Defines the privilege protection of the AHB4 bus configuration bits." "0: AHB4 configuration bits are accessible by..,1: AHB4 configuration bits are accessible by.." newline bitfld.long 0x8 5. "AHB3PV,Defines the privilege protection of the AHB3 bus configuration bits." "0: AHB3 configuration bits are accessible by..,1: AHB3 configuration bits are accessible by.." newline bitfld.long 0x8 4. "AHB2PV,Defines the privilege protection of the AHB2 bus configuration bits." "0: AHB2 configuration bits are accessible by..,1: AHB2 configuration bits are accessible by.." newline bitfld.long 0x8 3. "AHB1PV,Defines the privilege protection of the AHB1 bus configuration bits." "0: AHB1 configuration bits are accessible by..,1: AHB1 configuration bits are accessible by.." newline bitfld.long 0x8 2. "AHBMPV,Defines the privilege protection of the AHBM bus configuration bits." "0: AHBM configuration bits are accessible by..,1: AHBM configuration bits are accessible by.." newline bitfld.long 0x8 1. "ACLKNCPV,Defines the privilege protection of the ACLKNC bus configuration bits." "0: ACLKNC configuration bits are accessible by..,1: ACLKNC configuration bits are accessible by.." newline bitfld.long 0x8 0. "ACLKNPV,Defines the privilege protection of the ACLKN bus configuration bits." "0: ACLKN configuration bits are accessible by..,1: ACLKN configuration bits are accessible by.." wgroup.long 0x7C8++0x3 line.long 0x0 "RCC_LOCKCFGR4,RCC bus lock configuration register4" bitfld.long 0x0 13. "NOCLOCK,Defines the lock protection of the NOC bus configuration bits." "0: NOC configuration bits are accessible by..,1: NOC configuration bits are accessible by lock.." newline bitfld.long 0x0 12. "APB5LOCK,Defines the lock protection of the APB5 bus configuration bits." "0: APB5 configuration bits are accessible by..,1: APB5 configuration bits are accessible by lock.." newline bitfld.long 0x0 11. "APB4LOCK,Defines the lock protection of the APB4 bus configuration bits." "0: APB4 configuration bits are accessible by..,1: APB4 configuration bits are accessible by lock.." newline bitfld.long 0x0 10. "APB3LOCK,Defines the lock protection of the APB3 bus configuration bits." "0: APB3 configuration bits are accessible by..,1: APB3 configuration bits are accessible by lock.." newline bitfld.long 0x0 9. "APB2LOCK,Defines the lock protection of the APB2 bus configuration bits." "0: APB2 configuration bits are accessible by..,1: APB2 configuration bits are accessible by lock.." newline bitfld.long 0x0 8. "APB1LOCK,Defines the lock protection of the APB1 bus configuration bits." "0: APB1 configuration bits are accessible by..,1: APB1 configuration bits are accessible by lock.." newline bitfld.long 0x0 7. "AHB5LOCK,Defines the lock protection of the AHB5 bus configuration bits." "0: AHB5 configuration bits are accessible by..,1: AHB5 configuration bits are accessible by lock.." newline bitfld.long 0x0 6. "AHB4LOCK,Defines the lock protection of the AHB4 bus configuration bits." "0: AHB4 configuration bits are accessible by..,1: AHB4 configuration bits are accessible by lock.." newline bitfld.long 0x0 5. "AHB3LOCK,Defines the lock protection of the AHB3 bus configuration bits." "0: AHB3 configuration bits are accessible by..,1: AHB3 configuration bits are accessible by lock.." newline bitfld.long 0x0 4. "AHB2LOCK,Defines the lock protection of the AHB2 bus configuration bits." "0: AHB2 configuration bits are accessible by..,1: AHB2 configuration bits are accessible by lock.." newline bitfld.long 0x0 3. "AHB1LOCK,Defines the lock protection of the AHB1 bus configuration bits." "0: AHB1 configuration bits are accessible by..,1: AHB1 configuration bits are accessible by lock.." newline bitfld.long 0x0 2. "AHBMLOCK,Defines the lock protection of the AHBM bus configuration bits." "0: AHBM configuration bits are accessible by..,1: AHBM configuration bits are accessible by lock.." newline bitfld.long 0x0 1. "ACLKNCLOCK,Defines the lock protection of the ACLKNC bus configuration bits." "0: ACLKNC configuration bits are accessible by..,1: ACLKNC configuration bits are accessible by lock.." newline bitfld.long 0x0 0. "ACLKNLOCK,Defines the lock protection of the ACLKN bus configuration bits." "0: ACLKN configuration bits are accessible by..,1: ACLKN configuration bits are accessible by lock.." group.long 0x7CC++0x7 line.long 0x0 "RCC_PUBCFGR4,RCC bus public configuration register4" bitfld.long 0x0 13. "NOCPUB,Defines the public protection of the NOC bus configuration bits." "0: NOC configuration bits are accessible by..,1: NOC configuration bits are accessible by public.." newline bitfld.long 0x0 12. "APB5PUB,Defines the public protection of the APB5 bus configuration bits." "0: APB5 configuration bits are accessible by..,1: APB5 configuration bits are accessible by public.." newline bitfld.long 0x0 11. "APB4PUB,Defines the public protection of the APB4 bus configuration bits." "0: APB4 configuration bits are accessible by..,1: APB4 configuration bits are accessible by public.." newline bitfld.long 0x0 10. "APB3PUB,Defines the public protection of the APB3 bus configuration bits." "0: APB3 configuration bits are accessible by..,1: APB3 configuration bits are accessible by public.." newline bitfld.long 0x0 9. "APB2PUB,Defines the public protection of the APB2 bus configuration bits." "0: APB2 configuration bits are accessible by..,1: APB2 configuration bits are accessible by public.." newline bitfld.long 0x0 8. "APB1PUB,Defines the public protection of the APB1 bus configuration bits." "0: APB1 configuration bits are accessible by..,1: APB1 configuration bits are accessible by public.." newline bitfld.long 0x0 7. "AHB5PUB,Defines the public protection of the AHB5 bus configuration bits." "0: AHB5 configuration bits are accessible by..,1: AHB5 configuration bits are accessible by public.." newline bitfld.long 0x0 6. "AHB4PUB,Defines the public protection of the AHB4 bus configuration bits." "0: AHB4 configuration bits are accessible by..,1: AHB4 configuration bits are accessible by public.." newline bitfld.long 0x0 5. "AHB3PUB,Defines the public protection of the AHB3 bus configuration bits." "0: AHB3 configuration bits are accessible by..,1: AHB3 configuration bits are accessible by public.." newline bitfld.long 0x0 4. "AHB2PUB,Defines the public protection of the AHB2 bus configuration bits." "0: AHB2 configuration bits are accessible by..,1: AHB2 configuration bits are accessible by public.." newline bitfld.long 0x0 3. "AHB1PUB,Defines the public protection of the AHB1 bus configuration bits." "0: AHB1 configuration bits are accessible by..,1: AHB1 configuration bits are accessible by public.." newline bitfld.long 0x0 2. "AHBMPUB,Defines the public protection of the AHBM bus configuration bits." "0: AHBM configuration bits are accessible by..,1: AHBM configuration bits are accessible by public.." newline bitfld.long 0x0 1. "ACLKNCPUB,Defines the public protection of the ACLKNC bus configuration bits." "0: ACLKNC configuration bits are accessible by..,1: ACLKNC configuration bits are accessible by.." newline bitfld.long 0x0 0. "ACLKNPUB,Defines the public protection of the ACLKN bus configuration bits." "0: ACLKN configuration bits are accessible by..,1: ACLKN configuration bits are accessible by.." line.long 0x4 "RCC_PUBCFGR5,RCC bus public configuration register4" bitfld.long 0x4 11. "VENCRAMPUB,Defines the public protection of the VENCRAM bus configuration bits." "0: VENCRAM configuration bits are accessible by..,1: VENCRAM configuration bits are accessible by.." newline bitfld.long 0x4 10. "NPUCACHERAMPUB,Defines the public protection of the NPUCACHERAM bus configuration bits." "0: NPUCACHERAM configuration bits are accessible by..,1: NPUCACHERAM configuration bits are accessible by.." newline bitfld.long 0x4 9. "FLEXRAMPUB,Defines the public protection of the FLEXRAM bus configuration bits." "0: FLEXRAM configuration bits are accessible by..,1: FLEXRAM configuration bits are accessible by.." newline bitfld.long 0x4 8. "AXISRAM2PUB,Defines the public protection of the AXISRAM2 bus configuration bits." "0: AXISRAM2 configuration bits are accessible by..,1: AXISRAM2 configuration bits are accessible by.." newline bitfld.long 0x4 7. "AXISRAM1PUB,Defines the public protection of the AXISRAM1 bus configuration bits." "0: AXISRAM1 configuration bits are accessible by..,1: AXISRAM1 configuration bits are accessible by.." newline bitfld.long 0x4 6. "BKPSRAMPUB,Defines the public protection of the BKPSRAM bus configuration bits." "0: BKPSRAM configuration bits are accessible by..,1: BKPSRAM configuration bits are accessible by.." newline bitfld.long 0x4 5. "AHBSRAM2PUB,Defines the public protection of the AHBSRAM2 bus configuration bits." "0: AHBSRAM2 configuration bits are accessible by..,1: AHBSRAM2 configuration bits are accessible by.." newline bitfld.long 0x4 4. "AHBSRAM1PUB,Defines the public protection of the AHBSRAM1 bus configuration bits." "0: AHBSRAM1 configuration bits are accessible by..,1: AHBSRAM1 configuration bits are accessible by.." newline bitfld.long 0x4 3. "AXISRAM6PUB,Defines the public protection of the AXISRAM6 bus configuration bits." "0: AXISRAM6 configuration bits are accessible by..,1: AXISRAM6 configuration bits are accessible by.." newline bitfld.long 0x4 2. "AXISRAM5PUB,Defines the public protection of the AXISRAM5 bus configuration bits." "0: AXISRAM5 configuration bits are accessible by..,1: AXISRAM5 configuration bits are accessible by.." newline bitfld.long 0x4 1. "AXISRAM4PUB,Defines the public protection of the AXISRAM4 bus configuration bits." "0: AXISRAM4 configuration bits are accessible by..,1: AXISRAM4 configuration bits are accessible by.." newline bitfld.long 0x4 0. "AXISRAM3PUB,Defines the public protection of the AXISRAM3 bus configuration bits." "0: AXISRAM3 configuration bits are accessible by..,1: AXISRAM3 configuration bits are accessible by.." wgroup.long 0x800++0x3 line.long 0x0 "RCC_CSR,RCC control set register" bitfld.long 0x0 11. "PLL4ONS,PLL4 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 10. "PLL3ONS,PLL3 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 9. "PLL2ONS,PLL2 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 8. "PLL1ONS,PLL1 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 4. "HSEONS,HSE oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 3. "HSIONS,HSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 2. "MSIONS,MSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 1. "LSEONS,LSE oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 0. "LSIONS,LSI oscillator enable in Run/Sleep mode." "0,1" wgroup.long 0x808++0x3 line.long 0x0 "RCC_STOPCSR,RCC Stop configuration register" bitfld.long 0x0 1. "HSISTOPENS,HSISTOPENS" "0,1" newline bitfld.long 0x0 0. "MSISTOPENS,MSISTOPENS" "0,1" wgroup.long 0xA04++0x2B line.long 0x0 "RCC_BUSRSTSR,RCC bus reset set register" bitfld.long 0x0 13. "NOCRSTS,NOC reset" "0,1" newline bitfld.long 0x0 12. "APB5RSTS,APB5 reset" "0,1" newline bitfld.long 0x0 11. "APB4RSTS,APB4 reset" "0,1" newline bitfld.long 0x0 10. "APB3RSTS,APB3 reset" "0,1" newline bitfld.long 0x0 9. "APB2RSTS,APB2 reset" "0,1" newline bitfld.long 0x0 8. "APB1RSTS,APB1 reset" "0,1" newline bitfld.long 0x0 7. "AHB5RSTS,AHB5 reset" "0,1" newline bitfld.long 0x0 6. "AHB4RSTS,AHB4 reset" "0,1" newline bitfld.long 0x0 5. "AHB3RSTS,AHB3 reset" "0,1" newline bitfld.long 0x0 4. "AHB2RSTS,AHB2 reset" "0,1" newline bitfld.long 0x0 3. "AHB1RSTS,AHB1 reset" "0,1" newline bitfld.long 0x0 2. "AHBMRSTS,AHBM reset" "0,1" newline bitfld.long 0x0 0. "ACLKNRSTS,ACLKN reset" "0,1" line.long 0x4 "RCC_MISCRSTSR,RCC miscellaneous reset register" bitfld.long 0x4 8. "SDMMC2DLLRSTS,SDMMC2DLL reset" "0,1" newline bitfld.long 0x4 7. "SDMMC1DLLRSTS,SDMMC1DLL reset" "0,1" newline bitfld.long 0x4 5. "XSPIPHY2RSTS,XSPIPHY2 reset" "0,1" newline bitfld.long 0x4 4. "XSPIPHY1RSTS,XSPIPHY1 reset" "0,1" newline bitfld.long 0x4 0. "DBGRSTS,DBG reset" "0,1" line.long 0x8 "RCC_MEMRSTSR,RCC memory reset register" bitfld.long 0x8 12. "BOOTROMRSTS,BOOTROM reset" "0,1" newline bitfld.long 0x8 11. "VENCRAMRSTS,VENCRAM reset" "0,1" newline bitfld.long 0x8 10. "NPUCACHERAMRSTS,NPUCACHERAM reset" "0,1" newline bitfld.long 0x8 9. "FLEXRAMRSTS,FLEXRAM reset" "0,1" newline bitfld.long 0x8 8. "AXISRAM2RSTS,AXISRAM2 reset" "0,1" newline bitfld.long 0x8 7. "AXISRAM1RSTS,AXISRAM1 reset" "0,1" newline bitfld.long 0x8 5. "AHBSRAM2RSTS,AHBSRAM2 reset" "0,1" newline bitfld.long 0x8 4. "AHBSRAM1RSTS,AHBSRAM1 reset" "0,1" newline bitfld.long 0x8 3. "AXISRAM6RSTS,AXISRAM6 reset" "0,1" newline bitfld.long 0x8 2. "AXISRAM5RSTS,AXISRAM5 reset" "0,1" newline bitfld.long 0x8 1. "AXISRAM4RSTS,AXISRAM4 reset" "0,1" newline bitfld.long 0x8 0. "AXISRAM3RSTS,AXISRAM3 reset" "0,1" line.long 0xC "RCC_AHB1RSTSR,RCC AHB1 reset register" bitfld.long 0xC 5. "ADC12RSTS,ADC12 reset" "0,1" newline bitfld.long 0xC 4. "GPDMA1RSTS,GPDMA1 reset" "0,1" line.long 0x10 "RCC_AHB2RSTSR,RCC AHB2 reset register" bitfld.long 0x10 17. "ADF1RSTS,ADF1 reset" "0,1" newline bitfld.long 0x10 16. "MDF1RSTS,MDF1 reset" "0,1" newline bitfld.long 0x10 12. "RAMCFGRSTS,RAMCFG reset" "0,1" line.long 0x14 "RCC_AHB3RSTSR,RCC AHB3 reset register" bitfld.long 0x14 10. "IACRSTS,IAC reset" "0,1" newline bitfld.long 0x14 8. "PKARSTS,PKA reset" "0,1" newline bitfld.long 0x14 4. "SAESRSTS,SAES reset" "0,1" newline bitfld.long 0x14 2. "CRYPRSTS,CRYP reset" "0,1" newline bitfld.long 0x14 1. "HASHRSTS,HASH reset" "0,1" newline bitfld.long 0x14 0. "RNGRSTS,RNG reset" "0,1" line.long 0x18 "RCC_AHB4RSTSR,RCC AHB4 reset register" bitfld.long 0x18 19. "CRCRSTS,CRC reset" "0,1" newline bitfld.long 0x18 18. "PWRRSTS,PWR reset" "0,1" newline bitfld.long 0x18 16. "GPIOQRSTS,GPIOQ reset" "0,1" newline bitfld.long 0x18 15. "GPIOPRSTS,GPIOP reset" "0,1" newline bitfld.long 0x18 14. "GPIOORSTS,GPIOO reset" "0,1" newline bitfld.long 0x18 13. "GPIONRSTS,GPION reset" "0,1" newline bitfld.long 0x18 7. "GPIOHRSTS,GPIOH reset" "0,1" newline bitfld.long 0x18 6. "GPIOGRSTS,GPIOG reset" "0,1" newline bitfld.long 0x18 5. "GPIOFRSTS,GPIOF reset" "0,1" newline bitfld.long 0x18 4. "GPIOERSTS,GPIOE reset" "0,1" newline bitfld.long 0x18 3. "GPIODRSTS,GPIOD reset" "0,1" newline bitfld.long 0x18 2. "GPIOCRSTS,GPIOC reset" "0,1" newline bitfld.long 0x18 1. "GPIOBRSTS,GPIOB reset" "0,1" newline bitfld.long 0x18 0. "GPIOARSTS,GPIOA reset" "0,1" line.long 0x1C "RCC_AHB5RSTSR,RCC AHB5 reset register" bitfld.long 0x1C 31. "NPURSTS,NPU reset" "0,1" newline bitfld.long 0x1C 30. "NPUCACHERSTS,NPUCACHE reset" "0,1" newline bitfld.long 0x1C 29. "OTG2RSTS,OTG2 reset" "0,1" newline bitfld.long 0x1C 28. "OTGPHY2RSTS,OTGPHY2 reset" "0,1" newline bitfld.long 0x1C 27. "OTGPHY1RSTS,OTGPHY1 reset" "0,1" newline bitfld.long 0x1C 26. "OTG1RSTS,OTG1 reset" "0,1" newline bitfld.long 0x1C 25. "ETH1RSTS,ETH1 reset" "0,1" newline bitfld.long 0x1C 24. "SYSCFGOTGHSPHY2RSTS,SYSCFGOTGHSPHY2 reset" "0,1" newline bitfld.long 0x1C 23. "SYSCFGOTGHSPHY1RSTS,SYSCFGOTGHSPHY1 reset" "0,1" newline bitfld.long 0x1C 20. "GPURSTS,GPU reset" "0,1" newline bitfld.long 0x1C 19. "GFXMMURSTS,GFXMMU reset" "0,1" newline bitfld.long 0x1C 18. "MCE4RSTS,MCE4 reset" "0,1" newline bitfld.long 0x1C 17. "XSPI3RSTS,XSPI3 reset" "0,1" newline bitfld.long 0x1C 13. "XSPIMRSTS,XSPIM reset" "0,1" newline bitfld.long 0x1C 12. "XSPI2RSTS,XSPI2 reset" "0,1" newline bitfld.long 0x1C 8. "SDMMC1RSTS,SDMMC1 reset" "0,1" newline bitfld.long 0x1C 7. "SDMMC2RSTS,SDMMC2 reset" "0,1" newline bitfld.long 0x1C 6. "PSSIRSTS,PSSI reset" "0,1" newline bitfld.long 0x1C 5. "XSPI1RSTS,XSPI1 reset" "0,1" newline bitfld.long 0x1C 4. "FMCRSTS,FMC reset" "0,1" newline bitfld.long 0x1C 3. "JPEGRSTS,JPEG reset" "0,1" newline bitfld.long 0x1C 1. "DMA2DRSTS,DMA2D reset" "0,1" newline bitfld.long 0x1C 0. "HPDMA1RSTS,HPDMA1 reset" "0,1" line.long 0x20 "RCC_APB1LRSTSR,RCC APB1L reset register" bitfld.long 0x20 31. "UART8RSTS,UART8 reset" "0,1" newline bitfld.long 0x20 30. "UART7RSTS,UART7 reset" "0,1" newline bitfld.long 0x20 25. "I3C2RSTS,I3C2 reset" "0,1" newline bitfld.long 0x20 24. "I3C1RSTS,I3C1 reset" "0,1" newline bitfld.long 0x20 23. "I2C3RSTS,I2C3 reset" "0,1" newline bitfld.long 0x20 22. "I2C2RSTS,I2C2 reset" "0,1" newline bitfld.long 0x20 21. "I2C1RSTS,I2C1 reset" "0,1" newline bitfld.long 0x20 20. "UART5RSTS,UART5 reset" "0,1" newline bitfld.long 0x20 19. "UART4RSTS,UART4 reset" "0,1" newline bitfld.long 0x20 18. "USART3RSTS,USART3 reset" "0,1" newline bitfld.long 0x20 17. "USART2RSTS,USART2 reset" "0,1" newline bitfld.long 0x20 16. "SPDIFRX1RSTS,SPDIFRX1 reset" "0,1" newline bitfld.long 0x20 15. "SPI3RSTS,SPI3 reset" "0,1" newline bitfld.long 0x20 14. "SPI2RSTS,SPI2 reset" "0,1" newline bitfld.long 0x20 13. "TIM11RSTS,TIM11 reset" "0,1" newline bitfld.long 0x20 12. "TIM10RSTS,TIM10 reset" "0,1" newline bitfld.long 0x20 11. "WWDGRSTS,WWDG reset" "0,1" newline bitfld.long 0x20 9. "LPTIM1RSTS,LPTIM1 reset" "0,1" newline bitfld.long 0x20 8. "TIM14RSTS,TIM14 reset" "0,1" newline bitfld.long 0x20 7. "TIM13RSTS,TIM13 reset" "0,1" newline bitfld.long 0x20 6. "TIM12RSTS,TIM12 reset" "0,1" newline bitfld.long 0x20 5. "TIM7RSTS,TIM7 reset" "0,1" newline bitfld.long 0x20 4. "TIM6RSTS,TIM6 reset" "0,1" newline bitfld.long 0x20 3. "TIM5RSTS,TIM5 reset" "0,1" newline bitfld.long 0x20 2. "TIM4RSTS,TIM4 reset" "0,1" newline bitfld.long 0x20 1. "TIM3RSTS,TIM3 reset" "0,1" newline bitfld.long 0x20 0. "TIM2RSTS,TIM2 reset" "0,1" line.long 0x24 "RCC_APB1HRSTSR,RCC APB1H reset register" bitfld.long 0x24 18. "UCPD1RSTS,UCPD1 reset" "0,1" newline bitfld.long 0x24 8. "FDCANRSTS,FDCAN reset" "0,1" newline bitfld.long 0x24 5. "MDIOSRSTS,MDIOS reset" "0,1" line.long 0x28 "RCC_APB2RSTSR,RCC APB2 reset register" bitfld.long 0x28 22. "SAI2RSTS,SAI2 reset" "0,1" newline bitfld.long 0x28 21. "SAI1RSTS,SAI1 reset" "0,1" newline bitfld.long 0x28 20. "SPI5RSTS,SPI5 reset" "0,1" newline bitfld.long 0x28 19. "TIM9RSTS,TIM9 reset" "0,1" newline bitfld.long 0x28 18. "TIM17RSTS,TIM17 reset" "0,1" newline bitfld.long 0x28 17. "TIM16RSTS,TIM16 reset" "0,1" newline bitfld.long 0x28 16. "TIM15RSTS,TIM15 reset" "0,1" newline bitfld.long 0x28 15. "TIM18RSTS,TIM18 reset" "0,1" newline bitfld.long 0x28 13. "SPI4RSTS,SPI4 reset" "0,1" newline bitfld.long 0x28 12. "SPI1RSTS,SPI1 reset" "0,1" newline bitfld.long 0x28 7. "USART10RSTS,USART10 reset" "0,1" newline bitfld.long 0x28 6. "UART9RSTS,UART9 reset" "0,1" newline bitfld.long 0x28 5. "USART6RSTS,USART6 reset" "0,1" newline bitfld.long 0x28 4. "USART1RSTS,USART1 reset" "0,1" newline bitfld.long 0x28 1. "TIM8RSTS,TIM8 reset" "0,1" newline bitfld.long 0x28 0. "TIM1RSTS,TIM1 reset" "0,1" wgroup.long 0xA34++0x8B line.long 0x0 "RCC_APB4LRSTSR,RCC APB4L reset register" bitfld.long 0x0 31. "SERFRSTS,SERF reset" "0,1" newline bitfld.long 0x0 23. "R2GNPURSTS,R2GNPU reset" "0,1" newline bitfld.long 0x0 22. "R2GRETRSTS,R2GRET reset" "0,1" newline bitfld.long 0x0 16. "RTCRSTS,RTC reset" "0,1" newline bitfld.long 0x0 15. "VREFBUFRSTS,VREFBUF reset" "0,1" newline bitfld.long 0x0 12. "LPTIM5RSTS,LPTIM5 reset" "0,1" newline bitfld.long 0x0 11. "LPTIM4RSTS,LPTIM4 reset" "0,1" newline bitfld.long 0x0 10. "LPTIM3RSTS,LPTIM3 reset" "0,1" newline bitfld.long 0x0 9. "LPTIM2RSTS,LPTIM2 reset" "0,1" newline bitfld.long 0x0 7. "I2C4RSTS,I2C4 reset" "0,1" newline bitfld.long 0x0 5. "SPI6RSTS,SPI6 reset" "0,1" newline bitfld.long 0x0 3. "LPUART1RSTS,LPUART1 reset" "0,1" newline bitfld.long 0x0 2. "HDPRSTS,HDP reset" "0,1" line.long 0x4 "RCC_APB4HRSTSR,RCC APB4H reset register" bitfld.long 0x4 4. "BUSPERFMRSTS,BUSPERFM reset" "0,1" newline bitfld.long 0x4 2. "DTSRSTS,DTS reset" "0,1" newline bitfld.long 0x4 0. "SYSCFGRSTS,SYSCFG reset" "0,1" line.long 0x8 "RCC_APB5RSTSR,RCC APB5 reset register" bitfld.long 0x8 6. "CSIRSTS,CSI reset" "0,1" newline bitfld.long 0x8 5. "VENCRSTS,VENC reset" "0,1" newline bitfld.long 0x8 4. "GFXTIMRSTS,GFXTIM reset" "0,1" newline bitfld.long 0x8 2. "DCMIPPRSTS,DCMIPP reset" "0,1" newline bitfld.long 0x8 1. "LTDCRSTS,LTDC reset" "0,1" line.long 0xC "RCC_DIVENSR,RCC Divider enable register" bitfld.long 0xC 19. "IC20ENS,IC20 enable" "0,1" newline bitfld.long 0xC 18. "IC19ENS,IC19 enable" "0,1" newline bitfld.long 0xC 17. "IC18ENS,IC18 enable" "0,1" newline bitfld.long 0xC 16. "IC17ENS,IC17 enable" "0,1" newline bitfld.long 0xC 15. "IC16ENS,IC16 enable" "0,1" newline bitfld.long 0xC 14. "IC15ENS,IC15 enable" "0,1" newline bitfld.long 0xC 13. "IC14ENS,IC14 enable" "0,1" newline bitfld.long 0xC 12. "IC13ENS,IC13 enable" "0,1" newline bitfld.long 0xC 11. "IC12ENS,IC12 enable" "0,1" newline bitfld.long 0xC 10. "IC11ENS,IC11 enable" "0,1" newline bitfld.long 0xC 9. "IC10ENS,IC10 enable" "0,1" newline bitfld.long 0xC 8. "IC9ENS,IC9 enable" "0,1" newline bitfld.long 0xC 7. "IC8ENS,IC8 enable" "0,1" newline bitfld.long 0xC 6. "IC7ENS,IC7 enable" "0,1" newline bitfld.long 0xC 5. "IC6ENS,IC6 enable" "0,1" newline bitfld.long 0xC 4. "IC5ENS,IC5 enable" "0,1" newline bitfld.long 0xC 3. "IC4ENS,IC4 enable" "0,1" newline bitfld.long 0xC 2. "IC3ENS,IC3 enable" "0,1" newline bitfld.long 0xC 1. "IC2ENS,IC2 enable" "0,1" newline bitfld.long 0xC 0. "IC1ENS,IC1 enable" "0,1" line.long 0x10 "RCC_BUSENSR,RCC bus enable register" bitfld.long 0x10 12. "APB5ENS,APB5 enable" "0,1" newline bitfld.long 0x10 11. "APB4ENS,APB4 enable" "0,1" newline bitfld.long 0x10 10. "APB3ENS,APB3 enable" "0,1" newline bitfld.long 0x10 9. "APB2ENS,APB2 enable" "0,1" newline bitfld.long 0x10 8. "APB1ENS,APB1 enable" "0,1" newline bitfld.long 0x10 7. "AHB5ENS,AHB5 enable" "0,1" newline bitfld.long 0x10 6. "AHB4ENS,AHB4 enable" "0,1" newline bitfld.long 0x10 5. "AHB3ENS,AHB3 enable" "0,1" newline bitfld.long 0x10 4. "AHB2ENS,AHB2 enable" "0,1" newline bitfld.long 0x10 3. "AHB1ENS,AHB1 enable" "0,1" newline bitfld.long 0x10 2. "AHBMENS,AHBM enable" "0,1" newline bitfld.long 0x10 1. "ACLKNCENS,ACLKNC enable" "0,1" newline bitfld.long 0x10 0. "ACLKNENS,ACLKN enable" "0,1" line.long 0x14 "RCC_MISCENSR,RCC miscellaneous enable register" bitfld.long 0x14 6. "PERENS,PER enable" "0,1" newline bitfld.long 0x14 3. "XSPIPHYCOMPENS,XSPIPHYCOMP enable" "0,1" newline bitfld.long 0x14 2. "MCO2ENS,MCO2 enable" "0,1" newline bitfld.long 0x14 1. "MCO1ENS,MCO1 enable" "0,1" newline bitfld.long 0x14 0. "DBGENS,DBG enable" "0,1" line.long 0x18 "RCC_MEMENSR,RCC memory enable register" bitfld.long 0x18 12. "BOOTROMENS,BOOTROM enable" "0,1" newline bitfld.long 0x18 11. "VENCRAMENS,VENCRAM enable" "0,1" newline bitfld.long 0x18 10. "NPUCACHERAMENS,NPUCACHERAM enable" "0,1" newline bitfld.long 0x18 9. "FLEXRAMENS,FLEXRAM enable" "0,1" newline bitfld.long 0x18 8. "AXISRAM2ENS,AXISRAM2 enable" "0,1" newline bitfld.long 0x18 7. "AXISRAM1ENS,AXISRAM1 enable" "0,1" newline bitfld.long 0x18 6. "BKPSRAMENS,BKPSRAM enable" "0,1" newline bitfld.long 0x18 5. "AHBSRAM2ENS,AHBSRAM2 enable" "0,1" newline bitfld.long 0x18 4. "AHBSRAM1ENS,AHBSRAM1 enable" "0,1" newline bitfld.long 0x18 3. "AXISRAM6ENS,AXISRAM6 enable" "0,1" newline bitfld.long 0x18 2. "AXISRAM5ENS,AXISRAM5 enable" "0,1" newline bitfld.long 0x18 1. "AXISRAM4ENS,AXISRAM4 enable" "0,1" newline bitfld.long 0x18 0. "AXISRAM3ENS,AXISRAM3 enable" "0,1" line.long 0x1C "RCC_AHB1ENSR,RCC AHB1 enable register" bitfld.long 0x1C 5. "ADC12ENS,ADC12 enable" "0,1" newline bitfld.long 0x1C 4. "GPDMA1ENS,GPDMA1 enable" "0,1" line.long 0x20 "RCC_AHB2ENSR,RCC AHB2 enable register" bitfld.long 0x20 17. "ADF1ENS,ADF1 enable" "0,1" newline bitfld.long 0x20 16. "MDF1ENS,MDF1 enable" "0,1" newline bitfld.long 0x20 12. "RAMCFGENS,RAMCFG enable" "0,1" line.long 0x24 "RCC_AHB3ENSR,RCC AHB3 enable register" bitfld.long 0x24 14. "RISAFENS,RISAF enable" "0,1" newline bitfld.long 0x24 10. "IACENS,IAC enable" "0,1" newline bitfld.long 0x24 9. "RIFSCENS,RIFSC enable" "0,1" newline bitfld.long 0x24 8. "PKAENS,PKA enable" "0,1" newline bitfld.long 0x24 4. "SAESENS,SAES enable" "0,1" newline bitfld.long 0x24 2. "CRYPENS,CRYP enable" "0,1" newline bitfld.long 0x24 1. "HASHENS,HASH enable" "0,1" newline bitfld.long 0x24 0. "RNGENS,RNG enable" "0,1" line.long 0x28 "RCC_AHB4ENSR,RCC AHB4 enable register" bitfld.long 0x28 19. "CRCENS,CRC enable" "0,1" newline bitfld.long 0x28 18. "PWRENS,PWR enable" "0,1" newline bitfld.long 0x28 16. "GPIOQENS,GPIOQ enable" "0,1" newline bitfld.long 0x28 15. "GPIOPENS,GPIOP enable" "0,1" newline bitfld.long 0x28 14. "GPIOOENS,GPIOO enable" "0,1" newline bitfld.long 0x28 13. "GPIONENS,GPION enable" "0,1" newline bitfld.long 0x28 7. "GPIOHENS,GPIOH enable" "0,1" newline bitfld.long 0x28 6. "GPIOGENS,GPIOG enable" "0,1" newline bitfld.long 0x28 5. "GPIOFENS,GPIOF enable" "0,1" newline bitfld.long 0x28 4. "GPIOEENS,GPIOE enable" "0,1" newline bitfld.long 0x28 3. "GPIODENS,GPIOD enable" "0,1" newline bitfld.long 0x28 2. "GPIOCENS,GPIOC enable" "0,1" newline bitfld.long 0x28 1. "GPIOBENS,GPIOB enable" "0,1" newline bitfld.long 0x28 0. "GPIOAENS,GPIOA enable" "0,1" line.long 0x2C "RCC_AHB5ENSR,RCC AHB5 enable register" bitfld.long 0x2C 31. "NPUENS,NPU enable" "0,1" newline bitfld.long 0x2C 30. "NPUCACHEENS,NPUCACHE enable" "0,1" newline bitfld.long 0x2C 29. "OTG2ENS,OTG2 enable" "0,1" newline bitfld.long 0x2C 28. "OTGPHY2ENS,OTGPHY2 enable" "0,1" newline bitfld.long 0x2C 27. "OTGPHY1ENS,OTGPHY1 enable" "0,1" newline bitfld.long 0x2C 26. "OTG1ENS,OTG1 enable" "0,1" newline bitfld.long 0x2C 25. "ETH1ENS,ETH1 enable" "0,1" newline bitfld.long 0x2C 24. "ETH1RXENS,ETH1RX enable" "0,1" newline bitfld.long 0x2C 23. "ETH1TXENS,ETH1TX enable" "0,1" newline bitfld.long 0x2C 22. "ETH1MACENS,ETH1MAC enable" "0,1" newline bitfld.long 0x2C 20. "GPUENS,GPU enable" "0,1" newline bitfld.long 0x2C 19. "GFXMMUENS,GFXMMU enable" "0,1" newline bitfld.long 0x2C 18. "MCE4ENS,MCE4 enable" "0,1" newline bitfld.long 0x2C 17. "XSPI3ENS,XSPI3 enable" "0,1" newline bitfld.long 0x2C 16. "MCE3ENS,MCE3 enable" "0,1" newline bitfld.long 0x2C 15. "MCE2ENS,MCE2 enable" "0,1" newline bitfld.long 0x2C 14. "MCE1ENS,MCE1 enable" "0,1" newline bitfld.long 0x2C 13. "XSPIMENS,XSPIM enable" "0,1" newline bitfld.long 0x2C 12. "XSPI2ENS,XSPI2 enable" "0,1" newline bitfld.long 0x2C 8. "SDMMC1ENS,SDMMC1 enable" "0,1" newline bitfld.long 0x2C 7. "SDMMC2ENS,SDMMC2 enable" "0,1" newline bitfld.long 0x2C 6. "PSSIENS,PSSI enable" "0,1" newline bitfld.long 0x2C 5. "XSPI1ENS,XSPI1 enable" "0,1" newline bitfld.long 0x2C 4. "FMCENS,FMC enable" "0,1" newline bitfld.long 0x2C 3. "JPEGENS,JPEG enable" "0,1" newline bitfld.long 0x2C 1. "DMA2DENS,DMA2D enable" "0,1" newline bitfld.long 0x2C 0. "HPDMA1ENS,HPDMA1 enable" "0,1" line.long 0x30 "RCC_APB1LENSR,RCC APB1L enable register" bitfld.long 0x30 31. "UART8ENS,UART8 enable" "0,1" newline bitfld.long 0x30 30. "UART7ENS,UART7 enable" "0,1" newline bitfld.long 0x30 25. "I3C2ENS,I3C2 enable" "0,1" newline bitfld.long 0x30 24. "I3C1ENS,I3C1 enable" "0,1" newline bitfld.long 0x30 23. "I2C3ENS,I2C3 enable" "0,1" newline bitfld.long 0x30 22. "I2C2ENS,I2C2 enable" "0,1" newline bitfld.long 0x30 21. "I2C1ENS,I2C1 enable" "0,1" newline bitfld.long 0x30 20. "UART5ENS,UART5 enable" "0,1" newline bitfld.long 0x30 19. "UART4ENS,UART4 enable" "0,1" newline bitfld.long 0x30 18. "USART3ENS,USART3 enable" "0,1" newline bitfld.long 0x30 17. "USART2ENS,USART2 enable" "0,1" newline bitfld.long 0x30 16. "SPDIFRX1ENS,SPDIFRX1 enable" "0,1" newline bitfld.long 0x30 15. "SPI3ENS,SPI3 enable" "0,1" newline bitfld.long 0x30 14. "SPI2ENS,SPI2 enable" "0,1" newline bitfld.long 0x30 13. "TIM11ENS,TIM11 enable" "0,1" newline bitfld.long 0x30 12. "TIM10ENS,TIM10 enable" "0,1" newline bitfld.long 0x30 11. "WWDGENS,WWDG enable" "0,1" newline bitfld.long 0x30 9. "LPTIM1ENS,LPTIM1 enable" "0,1" newline bitfld.long 0x30 8. "TIM14ENS,TIM14 enable" "0,1" newline bitfld.long 0x30 7. "TIM13ENS,TIM13 enable" "0,1" newline bitfld.long 0x30 6. "TIM12ENS,TIM12 enable" "0,1" newline bitfld.long 0x30 5. "TIM7ENS,TIM7 enable" "0,1" newline bitfld.long 0x30 4. "TIM6ENS,TIM6 enable" "0,1" newline bitfld.long 0x30 3. "TIM5ENS,TIM5 enable" "0,1" newline bitfld.long 0x30 2. "TIM4ENS,TIM4 enable" "0,1" newline bitfld.long 0x30 1. "TIM3ENS,TIM3 enable" "0,1" newline bitfld.long 0x30 0. "TIM2ENS,TIM2 enable" "0,1" line.long 0x34 "RCC_APB1HENSR,RCC APB1H enable register" bitfld.long 0x34 18. "UCPD1ENS,UCPD1 enable" "0,1" newline bitfld.long 0x34 8. "FDCANENS,FDCAN enable" "0,1" newline bitfld.long 0x34 5. "MDIOSENS,MDIOS enable" "0,1" line.long 0x38 "RCC_APB2ENSR,RCC APB2 enable register" bitfld.long 0x38 22. "SAI2ENS,SAI2 enable" "0,1" newline bitfld.long 0x38 21. "SAI1ENS,SAI1 enable" "0,1" newline bitfld.long 0x38 20. "SPI5ENS,SPI5 enable" "0,1" newline bitfld.long 0x38 19. "TIM9ENS,TIM9 enable" "0,1" newline bitfld.long 0x38 18. "TIM17ENS,TIM17 enable" "0,1" newline bitfld.long 0x38 17. "TIM16ENS,TIM16 enable" "0,1" newline bitfld.long 0x38 16. "TIM15ENS,TIM15 enable" "0,1" newline bitfld.long 0x38 15. "TIM18ENS,TIM18 enable" "0,1" newline bitfld.long 0x38 13. "SPI4ENS,SPI4 enable" "0,1" newline bitfld.long 0x38 12. "SPI1ENS,SPI1 enable" "0,1" newline bitfld.long 0x38 7. "USART10ENS,USART10 enable" "0,1" newline bitfld.long 0x38 6. "UART9ENS,UART9 enable" "0,1" newline bitfld.long 0x38 5. "USART6ENS,USART6 enable" "0,1" newline bitfld.long 0x38 4. "USART1ENS,USART1 enable" "0,1" newline bitfld.long 0x38 1. "TIM8ENS,TIM8 enable" "0,1" newline bitfld.long 0x38 0. "TIM1ENS,TIM1 enable" "0,1" line.long 0x3C "RCC_APB3ENSR,RCC APB3 enable register" bitfld.long 0x3C 2. "DFTENS,DFT enable" "0,1" line.long 0x40 "RCC_APB4LENSR,RCC APB4L enable register" bitfld.long 0x40 31. "SERFENS,SERF enable" "0,1" newline bitfld.long 0x40 23. "R2GNPUENS,R2GNPU enable" "0,1" newline bitfld.long 0x40 22. "R2GRETENS,R2GRET enable" "0,1" newline bitfld.long 0x40 17. "RTCAPBENS,RTCAPB enable" "0,1" newline bitfld.long 0x40 16. "RTCENS,RTC enable" "0,1" newline bitfld.long 0x40 15. "VREFBUFENS,VREFBUF enable" "0,1" newline bitfld.long 0x40 12. "LPTIM5ENS,LPTIM5 enable" "0,1" newline bitfld.long 0x40 11. "LPTIM4ENS,LPTIM4 enable" "0,1" newline bitfld.long 0x40 10. "LPTIM3ENS,LPTIM3 enable" "0,1" newline bitfld.long 0x40 9. "LPTIM2ENS,LPTIM2 enable" "0,1" newline bitfld.long 0x40 7. "I2C4ENS,I2C4 enable" "0,1" newline bitfld.long 0x40 5. "SPI6ENS,SPI6 enable" "0,1" newline bitfld.long 0x40 3. "LPUART1ENS,LPUART1 enable" "0,1" newline bitfld.long 0x40 2. "HDPENS,HDP enable" "0,1" line.long 0x44 "RCC_APB4HENSR,RCC APB4H enable register" bitfld.long 0x44 4. "BUSPERFMENS,BUSPERFM enable" "0,1" newline bitfld.long 0x44 2. "DTSENS,DTS enable" "0,1" newline bitfld.long 0x44 1. "BSECENS,BSEC enable" "0,1" newline bitfld.long 0x44 0. "SYSCFGENS,SYSCFG enable" "0,1" line.long 0x48 "RCC_APB5ENSR,RCC APB5 enable register" bitfld.long 0x48 6. "CSIENS,CSI enable" "0,1" newline bitfld.long 0x48 5. "VENCENS,VENC enable" "0,1" newline bitfld.long 0x48 4. "GFXTIMENS,GFXTIM enable" "0,1" newline bitfld.long 0x48 2. "DCMIPPENS,DCMIPP enable" "0,1" newline bitfld.long 0x48 1. "LTDCENS,LTDC enable" "0,1" line.long 0x4C "RCC_DIVLPENSR,RCC divider Sleep enable register" bitfld.long 0x4C 19. "IC20LPENS,IC20 sleep enable" "0,1" newline bitfld.long 0x4C 18. "IC19LPENS,IC19 sleep enable" "0,1" newline bitfld.long 0x4C 17. "IC18LPENS,IC18 sleep enable" "0,1" newline bitfld.long 0x4C 16. "IC17LPENS,IC17 sleep enable" "0,1" newline bitfld.long 0x4C 15. "IC16LPENS,IC16 sleep enable" "0,1" newline bitfld.long 0x4C 14. "IC15LPENS,IC15 sleep enable" "0,1" newline bitfld.long 0x4C 13. "IC14LPENS,IC14 sleep enable" "0,1" newline bitfld.long 0x4C 12. "IC13LPENS,IC13 sleep enable" "0,1" newline bitfld.long 0x4C 11. "IC12LPENS,IC12 sleep enable" "0,1" newline bitfld.long 0x4C 10. "IC11LPENS,IC11 sleep enable" "0,1" newline bitfld.long 0x4C 9. "IC10LPENS,IC10 sleep enable" "0,1" newline bitfld.long 0x4C 8. "IC9LPENS,IC9 sleep enable" "0,1" newline bitfld.long 0x4C 7. "IC8LPENS,IC8 sleep enable" "0,1" newline bitfld.long 0x4C 6. "IC7LPENS,IC7 sleep enable" "0,1" newline bitfld.long 0x4C 5. "IC6LPENS,IC6 sleep enable" "0,1" newline bitfld.long 0x4C 4. "IC5LPENS,IC5 sleep enable" "0,1" newline bitfld.long 0x4C 3. "IC4LPENS,IC4 sleep enable" "0,1" newline bitfld.long 0x4C 2. "IC3LPENS,IC3 sleep enable" "0,1" newline bitfld.long 0x4C 1. "IC2LPENS,IC2 sleep enable" "0,1" newline bitfld.long 0x4C 0. "IC1LPENS,IC1 sleep enable" "0,1" line.long 0x50 "RCC_BUSLPENSR,RCC bus Sleep enable register" bitfld.long 0x50 12. "APB5LPENS,APB5 sleep enable" "0,1" newline bitfld.long 0x50 11. "APB4LPENS,APB4 sleep enable" "0,1" newline bitfld.long 0x50 10. "APB3LPENS,APB3 sleep enable" "0,1" newline bitfld.long 0x50 9. "APB2LPENS,APB2 sleep enable" "0,1" newline bitfld.long 0x50 8. "APB1LPENS,APB1 sleep enable" "0,1" newline bitfld.long 0x50 7. "AHB5LPENS,AHB5 sleep enable" "0,1" newline bitfld.long 0x50 6. "AHB4LPENS,AHB4 sleep enable" "0,1" newline bitfld.long 0x50 5. "AHB3LPENS,AHB3 sleep enable" "0,1" newline bitfld.long 0x50 4. "AHB2LPENS,AHB2 sleep enable" "0,1" newline bitfld.long 0x50 3. "AHB1LPENS,AHB1 sleep enable" "0,1" newline bitfld.long 0x50 2. "AHBMLPENS,AHBM sleep enable" "0,1" newline bitfld.long 0x50 1. "ACLKNCLPENS,ACLKNC sleep enable" "0,1" newline bitfld.long 0x50 0. "ACLKNLPENS,ACLKN sleep enable" "0,1" line.long 0x54 "RCC_MISCLPENSR,RCC miscellaneous Sleep enable register" bitfld.long 0x54 6. "PERLPENS,PER sleep enable" "0,1" newline bitfld.long 0x54 3. "XSPIPHYCOMPLPENS,XSPIPHYCOMP sleep enable" "0,1" newline bitfld.long 0x54 0. "DBGLPENS,DBG sleep enable" "0,1" line.long 0x58 "RCC_MEMLPENSR,RCC memory sleep enable register" bitfld.long 0x58 12. "BOOTROMLPENS,BOOTROM sleep enable" "0,1" newline bitfld.long 0x58 11. "VENCRAMLPENS,VENCRAM sleep enable" "0,1" newline bitfld.long 0x58 10. "NPUCACHERAMLPENS,NPUCACHERAM sleep enable" "0,1" newline bitfld.long 0x58 9. "FLEXRAMLPENS,FLEXRAM sleep enable" "0,1" newline bitfld.long 0x58 8. "AXISRAM2LPENS,AXISRAM2 sleep enable" "0,1" newline bitfld.long 0x58 7. "AXISRAM1LPENS,AXISRAM1 sleep enable" "0,1" newline bitfld.long 0x58 6. "BKPSRAMLPENS,BKPSRAM sleep enable" "0,1" newline bitfld.long 0x58 5. "AHBSRAM2LPENS,AHBSRAM2 sleep enable" "0,1" newline bitfld.long 0x58 4. "AHBSRAM1LPENS,AHBSRAM1 sleep enable" "0,1" newline bitfld.long 0x58 3. "AXISRAM6LPENS,AXISRAM6 sleep enable" "0,1" newline bitfld.long 0x58 2. "AXISRAM5LPENS,AXISRAM5 sleep enable" "0,1" newline bitfld.long 0x58 1. "AXISRAM4LPENS,AXISRAM4 sleep enable" "0,1" newline bitfld.long 0x58 0. "AXISRAM3LPENS,AXISRAM3 sleep enable" "0,1" line.long 0x5C "RCC_AHB1LPENSR,RCC AHB1 Sleep enable register" bitfld.long 0x5C 5. "ADC12LPENS,ADC12 sleep enable" "0,1" newline bitfld.long 0x5C 4. "GPDMA1LPENS,GPDMA1 sleep enable" "0,1" line.long 0x60 "RCC_AHB2LPENSR,RCC AHB2 Sleep enable register" bitfld.long 0x60 17. "ADF1LPENS,ADF1 sleep enable" "0,1" newline bitfld.long 0x60 16. "MDF1LPENS,MDF1 sleep enable" "0,1" newline bitfld.long 0x60 12. "RAMCFGLPENS,RAMCFG sleep enable" "0,1" line.long 0x64 "RCC_AHB3LPENSR,RCC AHB3 Sleep enable register" bitfld.long 0x64 14. "RISAFLPENS,RISAF sleep enable" "0,1" newline bitfld.long 0x64 10. "IACLPENS,IAC sleep enable" "0,1" newline bitfld.long 0x64 9. "RIFSCLPENS,RIFSC sleep enable" "0,1" newline bitfld.long 0x64 8. "PKALPENS,PKA sleep enable" "0,1" newline bitfld.long 0x64 4. "SAESLPENS,SAES sleep enable" "0,1" newline bitfld.long 0x64 2. "CRYPLPENS,CRYP sleep enable" "0,1" newline bitfld.long 0x64 1. "HASHLPENS,HASH sleep enable" "0,1" newline bitfld.long 0x64 0. "RNGLPENS,RNG sleep enable" "0,1" line.long 0x68 "RCC_AHB4LPENSR,RCC AHB4 Sleep enable register" bitfld.long 0x68 19. "CRCLPENS,CRC sleep enable" "0,1" newline bitfld.long 0x68 18. "PWRLPENS,PWR sleep enable" "0,1" newline bitfld.long 0x68 16. "GPIOQLPENS,GPIOQ sleep enable" "0,1" newline bitfld.long 0x68 15. "GPIOPLPENS,GPIOP sleep enable" "0,1" newline bitfld.long 0x68 14. "GPIOOLPENS,GPIOO sleep enable" "0,1" newline bitfld.long 0x68 13. "GPIONLPENS,GPION sleep enable" "0,1" newline bitfld.long 0x68 7. "GPIOHLPENS,GPIOH sleep enable" "0,1" newline bitfld.long 0x68 6. "GPIOGLPENS,GPIOG sleep enable" "0,1" newline bitfld.long 0x68 5. "GPIOFLPENS,GPIOF sleep enable" "0,1" newline bitfld.long 0x68 4. "GPIOELPENS,GPIOE sleep enable" "0,1" newline bitfld.long 0x68 3. "GPIODLPENS,GPIOD sleep enable" "0,1" newline bitfld.long 0x68 2. "GPIOCLPENS,GPIOC sleep enable" "0,1" newline bitfld.long 0x68 1. "GPIOBLPENS,GPIOB sleep enable" "0,1" newline bitfld.long 0x68 0. "GPIOALPENS,GPIOA sleep enable" "0,1" line.long 0x6C "RCC_AHB5LPENSR,RCC AHB5 Sleep enable register" bitfld.long 0x6C 31. "NPULPENS,NPU sleep enable" "0,1" newline bitfld.long 0x6C 30. "NPUCACHELPENS,NPUCACHE sleep enable" "0,1" newline bitfld.long 0x6C 29. "OTG2LPENS,OTG2 sleep enable" "0,1" newline bitfld.long 0x6C 28. "OTGPHY2LPENS,OTGPHY2 sleep enable" "0,1" newline bitfld.long 0x6C 27. "OTGPHY1LPENS,OTGPHY1 sleep enable" "0,1" newline bitfld.long 0x6C 26. "OTG1LPENS,OTG1 sleep enable" "0,1" newline bitfld.long 0x6C 25. "ETH1LPENS,ETH1 sleep enable" "0,1" newline bitfld.long 0x6C 24. "ETH1RXLPENS,ETH1RX sleep enable" "0,1" newline bitfld.long 0x6C 23. "ETH1TXLPENS,ETH1TX sleep enable" "0,1" newline bitfld.long 0x6C 22. "ETH1MACLPENS,ETH1MAC sleep enable" "0,1" newline bitfld.long 0x6C 20. "GPULPENS,GPU sleep enable" "0,1" newline bitfld.long 0x6C 19. "GFXMMULPENS,GFXMMU sleep enable" "0,1" newline bitfld.long 0x6C 18. "MCE4LPENS,MCE4 sleep enable" "0,1" newline bitfld.long 0x6C 17. "XSPI3LPENS,XSPI3 sleep enable" "0,1" newline bitfld.long 0x6C 16. "MCE3LPENS,MCE3 sleep enable" "0,1" newline bitfld.long 0x6C 15. "MCE2LPENS,MCE2 sleep enable" "0,1" newline bitfld.long 0x6C 14. "MCE1LPENS,MCE1 sleep enable" "0,1" newline bitfld.long 0x6C 13. "XSPIMLPENS,XSPIM sleep enable" "0,1" newline bitfld.long 0x6C 12. "XSPI2LPENS,XSPI2 sleep enable" "0,1" newline bitfld.long 0x6C 8. "SDMMC1LPENS,SDMMC1 sleep enable" "0,1" newline bitfld.long 0x6C 7. "SDMMC2LPENS,SDMMC2 sleep enable" "0,1" newline bitfld.long 0x6C 6. "PSSILPENS,PSSI sleep enable" "0,1" newline bitfld.long 0x6C 5. "XSPI1LPENS,XSPI1 sleep enable" "0,1" newline bitfld.long 0x6C 4. "FMCLPENS,FMC sleep enable" "0,1" newline bitfld.long 0x6C 3. "JPEGLPENS,JPEG sleep enable" "0,1" newline bitfld.long 0x6C 1. "DMA2DLPENS,DMA2D sleep enable" "0,1" newline bitfld.long 0x6C 0. "HPDMA1LPENS,HPDMA1 sleep enable" "0,1" line.long 0x70 "RCC_APB1LLPENSR,RCC APB1L Sleep enable register" bitfld.long 0x70 31. "UART8LPENS,UART8 sleep enable" "0,1" newline bitfld.long 0x70 30. "UART7LPENS,UART7 sleep enable" "0,1" newline bitfld.long 0x70 25. "I3C2LPENS,I3C2 sleep enable" "0,1" newline bitfld.long 0x70 24. "I3C1LPENS,I3C1 sleep enable" "0,1" newline bitfld.long 0x70 23. "I2C3LPENS,I2C3 sleep enable" "0,1" newline bitfld.long 0x70 22. "I2C2LPENS,I2C2 sleep enable" "0,1" newline bitfld.long 0x70 21. "I2C1LPENS,I2C1 sleep enable" "0,1" newline bitfld.long 0x70 20. "UART5LPENS,UART5 sleep enable" "0,1" newline bitfld.long 0x70 19. "UART4LPENS,UART4 sleep enable" "0,1" newline bitfld.long 0x70 18. "USART3LPENS,USART3 sleep enable" "0,1" newline bitfld.long 0x70 17. "USART2LPENS,USART2 sleep enable" "0,1" newline bitfld.long 0x70 16. "SPDIFRX1LPENS,SPDIFRX1 sleep enable" "0,1" newline bitfld.long 0x70 15. "SPI3LPENS,SPI3 sleep enable" "0,1" newline bitfld.long 0x70 14. "SPI2LPENS,SPI2 sleep enable" "0,1" newline bitfld.long 0x70 13. "TIM11LPENS,TIM11 sleep enable" "0,1" newline bitfld.long 0x70 12. "TIM10LPENS,TIM10 sleep enable" "0,1" newline bitfld.long 0x70 11. "WWDGLPENS,WWDG sleep enable" "0,1" newline bitfld.long 0x70 9. "LPTIM1LPENS,LPTIM1 sleep enable" "0,1" newline bitfld.long 0x70 8. "TIM14LPENS,TIM14 sleep enable" "0,1" newline bitfld.long 0x70 7. "TIM13LPENS,TIM13 sleep enable" "0,1" newline bitfld.long 0x70 6. "TIM12LPENS,TIM12 sleep enable" "0,1" newline bitfld.long 0x70 5. "TIM7LPENS,TIM7 sleep enable" "0,1" newline bitfld.long 0x70 4. "TIM6LPENS,TIM6 sleep enable" "0,1" newline bitfld.long 0x70 3. "TIM5LPENS,TIM5 sleep enable" "0,1" newline bitfld.long 0x70 2. "TIM4LPENS,TIM4 sleep enable" "0,1" newline bitfld.long 0x70 1. "TIM3LPENS,TIM3 sleep enable" "0,1" newline bitfld.long 0x70 0. "TIM2LPENS,TIM2 sleep enable" "0,1" line.long 0x74 "RCC_APB1HLPENSR,RCC APB1H Sleep enable register" bitfld.long 0x74 18. "UCPD1LPENS,UCPD1 sleep enable" "0,1" newline bitfld.long 0x74 8. "FDCANLPENS,FDCAN sleep enable" "0,1" newline bitfld.long 0x74 5. "MDIOSLPENS,MDIOS sleep enable" "0,1" line.long 0x78 "RCC_APB2LPENSR,RCC APB2 Sleep enable register" bitfld.long 0x78 22. "SAI2LPENS,SAI2 sleep enable" "0,1" newline bitfld.long 0x78 21. "SAI1LPENS,SAI1 sleep enable" "0,1" newline bitfld.long 0x78 20. "SPI5LPENS,SPI5 sleep enable" "0,1" newline bitfld.long 0x78 19. "TIM9LPENS,TIM9 sleep enable" "0,1" newline bitfld.long 0x78 18. "TIM17LPENS,TIM17 sleep enable" "0,1" newline bitfld.long 0x78 17. "TIM16LPENS,TIM16 sleep enable" "0,1" newline bitfld.long 0x78 16. "TIM15LPENS,TIM15 sleep enable" "0,1" newline bitfld.long 0x78 15. "TIM18LPENS,TIM18 sleep enable" "0,1" newline bitfld.long 0x78 13. "SPI4LPENS,SPI4 sleep enable" "0,1" newline bitfld.long 0x78 12. "SPI1LPENS,SPI1 sleep enable" "0,1" newline bitfld.long 0x78 7. "USART10LPENS,USART10 sleep enable" "0,1" newline bitfld.long 0x78 6. "UART9LPENS,UART9 sleep enable" "0,1" newline bitfld.long 0x78 5. "USART6LPENS,USART6 sleep enable" "0,1" newline bitfld.long 0x78 4. "USART1LPENS,USART1 sleep enable" "0,1" newline bitfld.long 0x78 1. "TIM8LPENS,TIM8 sleep enable" "0,1" newline bitfld.long 0x78 0. "TIM1LPENS,TIM1 sleep enable" "0,1" line.long 0x7C "RCC_APB3LPENSR,RCC APB3 Sleep enable register" bitfld.long 0x7C 2. "DFTLPENS,DFT sleep enable" "0,1" line.long 0x80 "RCC_APB4LLPENSR,RCC APB4L Sleep enable register" bitfld.long 0x80 31. "SERFLPENS,SERF sleep enable" "0,1" newline bitfld.long 0x80 23. "R2GNPULPENS,R2GNPU sleep enable" "0,1" newline bitfld.long 0x80 22. "R2GRETLPENS,R2GRET sleep enable" "0,1" newline bitfld.long 0x80 17. "RTCAPBLPENS,RTCAPB sleep enable" "0,1" newline bitfld.long 0x80 16. "RTCLPENS,RTC sleep enable" "0,1" newline bitfld.long 0x80 15. "VREFBUFLPENS,VREFBUF sleep enable" "0,1" newline bitfld.long 0x80 12. "LPTIM5LPENS,LPTIM5 sleep enable" "0,1" newline bitfld.long 0x80 11. "LPTIM4LPENS,LPTIM4 sleep enable" "0,1" newline bitfld.long 0x80 10. "LPTIM3LPENS,LPTIM3 sleep enable" "0,1" newline bitfld.long 0x80 9. "LPTIM2LPENS,LPTIM2 sleep enable" "0,1" newline bitfld.long 0x80 7. "I2C4LPENS,I2C4 sleep enable" "0,1" newline bitfld.long 0x80 5. "SPI6LPENS,SPI6 sleep enable" "0,1" newline bitfld.long 0x80 3. "LPUART1LPENS,LPUART1 sleep enable" "0,1" newline bitfld.long 0x80 2. "HDPLPENS,HDP sleep enable" "0,1" line.long 0x84 "RCC_APB4HLPENSR,RCC APB4H Sleep enable register" bitfld.long 0x84 4. "BUSPERFMLPENS,BUSPERFM sleep enable" "0,1" newline bitfld.long 0x84 2. "DTSLPENS,DTS sleep enable" "0,1" newline bitfld.long 0x84 1. "BSECLPENS,BSEC sleep enable" "0,1" newline bitfld.long 0x84 0. "SYSCFGLPENS,SYSCFG sleep enable" "0,1" line.long 0x88 "RCC_APB5LPENSR,RCC APB5 Sleep enable register" bitfld.long 0x88 6. "CSILPENS,CSI sleep enable" "0,1" newline bitfld.long 0x88 5. "VENCLPENS,VENC sleep enable" "0,1" newline bitfld.long 0x88 4. "GFXTIMLPENS,GFXTIM sleep enable" "0,1" newline bitfld.long 0x88 2. "DCMIPPLPENS,DCMIPP sleep enable" "0,1" newline bitfld.long 0x88 1. "LTDCLPENS,LTDC sleep enable" "0,1" wgroup.long 0xF84++0x3 line.long 0x0 "RCC_PRIVCFGSR0,RCC oscillator privilege configuration register0" bitfld.long 0x0 4. "HSEPVS,Defines the privilege protection of the HSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "HSIPVS,Defines the privilege protection of the HSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "MSIPVS,Defines the privilege protection of the MSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "LSEPVS,Defines the privilege protection of the LSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "LSIPVS,Defines the privilege protection of the LSI configuration bits (enable ready divider)." "0,1" wgroup.long 0xF8C++0x3 line.long 0x0 "RCC_PUBCFGSR0,RCC oscillator public configuration register0" bitfld.long 0x0 4. "HSEPUBS,Defines the public protection of the HSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "HSIPUBS,Defines the public protection of the HSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "MSIPUBS,Defines the public protection of the MSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "LSEPUBS,Defines the public protection of the LSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "LSIPUBS,Defines the public protection of the LSI configuration bits (enable ready divider)." "0,1" wgroup.long 0xF94++0x3 line.long 0x0 "RCC_PRIVCFGSR1,RCC PLL privilege configuration register1" bitfld.long 0x0 3. "PLL4PVS,Defines the privilege protection of the PLL4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "PLL3PVS,Defines the privilege protection of the PLL3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "PLL2PVS,Defines the privilege protection of the PLL2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "PLL1PVS,Defines the privilege protection of the PLL1 configuration bits (enable ready divider)." "0,1" wgroup.long 0xF9C++0x3 line.long 0x0 "RCC_PUBCFGSR1,RCC PLL public configuration register1" bitfld.long 0x0 3. "PLL4PUBS,Defines the public protection of the PLL4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "PLL3PUBS,Defines the public protection of the PLL3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "PLL2PUBS,Defines the public protection of the PLL2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "PLL1PUBS,Defines the public protection of the PLL1 configuration bits (enable ready divider)." "0,1" wgroup.long 0xFA4++0x3 line.long 0x0 "RCC_PRIVCFGSR2,RCC divider privilege configuration register2" bitfld.long 0x0 19. "IC20PVS,Defines the privilege protection of the IC20 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 18. "IC19PVS,Defines the privilege protection of the IC19 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 17. "IC18PVS,Defines the privilege protection of the IC18 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 16. "IC17PVS,Defines the privilege protection of the IC17 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 15. "IC16PVS,Defines the privilege protection of the IC16 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 14. "IC15PVS,Defines the privilege protection of the IC15 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 13. "IC14PVS,Defines the privilege protection of the IC14 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "IC13PVS,Defines the privilege protection of the IC13 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "IC12PVS,Defines the privilege protection of the IC12 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "IC11PVS,Defines the privilege protection of the IC11 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "IC10PVS,Defines the privilege protection of the IC10 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "IC9PVS,Defines the privilege protection of the IC9 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "IC8PVS,Defines the privilege protection of the IC8 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "IC7PVS,Defines the privilege protection of the IC7 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "IC6PVS,Defines the privilege protection of the IC6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "IC5PVS,Defines the privilege protection of the IC5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "IC4PVS,Defines the privilege protection of the IC4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "IC3PVS,Defines the privilege protection of the IC3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "IC2PVS,Defines the privilege protection of the IC2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "IC1PVS,Defines the privilege protection of the IC1 configuration bits (enable ready divider)." "0,1" wgroup.long 0xFAC++0x13 line.long 0x0 "RCC_PUBCFGSR2,RCC divider public configuration register2" bitfld.long 0x0 19. "IC20PUBS,Defines the public protection of the IC20 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 18. "IC19PUBS,Defines the public protection of the IC19 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 17. "IC18PUBS,Defines the public protection of the IC18 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 16. "IC17PUBS,Defines the public protection of the IC17 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 15. "IC16PUBS,Defines the public protection of the IC16 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 14. "IC15PUBS,Defines the public protection of the IC15 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 13. "IC14PUBS,Defines the public protection of the IC14 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "IC13PUBS,Defines the public protection of the IC13 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "IC12PUBS,Defines the public protection of the IC12 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "IC11PUBS,Defines the public protection of the IC11 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "IC10PUBS,Defines the public protection of the IC10 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "IC9PUBS,Defines the public protection of the IC9 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "IC8PUBS,Defines the public protection of the IC8 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "IC7PUBS,Defines the public protection of the IC7 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "IC6PUBS,Defines the public protection of the IC6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "IC5PUBS,Defines the public protection of the IC5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "IC4PUBS,Defines the public protection of the IC4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "IC3PUBS,Defines the public protection of the IC3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "IC2PUBS,Defines the public protection of the IC2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "IC1PUBS,Defines the public protection of the IC1 configuration bits (enable ready divider)." "0,1" line.long 0x4 "RCC_SECCFGSR3,RCC system secure configuration register3" bitfld.long 0x4 6. "DFTSECS,Defines the secure protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 5. "RSTSECS,Defines the secure protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 4. "INTSECS,Defines the secure protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 3. "PERSECS,Defines the secure protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 2. "BUSSECS,Defines the secure protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 1. "SYSSECS,Defines the secure protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 0. "MODSECS,Defines the secure protection of the MOD configuration bits (enable ready divider)." "0,1" line.long 0x8 "RCC_PRIVCFGSR3,RCC system privilege configuration register3" bitfld.long 0x8 6. "DFTPVS,Defines the privilege protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 5. "RSTPVS,Defines the privilege protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 4. "INTPVS,Defines the privilege protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 3. "PERPVS,Defines the privilege protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 2. "BUSPVS,Defines the privilege protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 1. "SYSPVS,Defines the privilege protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 0. "MODPVS,Defines the privilege protection of the MOD configuration bits (enable ready divider)." "0,1" line.long 0xC "RCC_LOCKCFGSR3,RCC system lock configuration register3" bitfld.long 0xC 6. "DFTLOCKS,Defines the lock protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 5. "RSTLOCKS,Defines the lock protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 4. "INTLOCKS,Defines the lock protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 3. "PERLOCKS,Defines the lock protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 2. "BUSLOCKS,Defines the lock protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 1. "SYSLOCKS,Defines the lock protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 0. "MODLOCKS,Defines the lock protection of the MOD configuration bits (enable ready divider)." "0,1" line.long 0x10 "RCC_PUBCFGSR3,RCC system public configuration register3" bitfld.long 0x10 6. "DFTPUBS,Defines the public protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 5. "RSTPUBS,Defines the public protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 4. "INTPUBS,Defines the public protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 3. "PERPUBS,Defines the public protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 2. "BUSPUBS,Defines the public protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 1. "SYSPUBS,Defines the public protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 0. "MODPUBS,Defines the public protection of the MOD configuration bits (enable ready divider)." "0,1" wgroup.long 0xFC4++0x3 line.long 0x0 "RCC_PRIVCFGSR4,RCC privilege configuration register4" bitfld.long 0x0 13. "NOCPVS,Defines the privilege protection of the NOC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "APB5PVS,Defines the privilege protection of the APB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "APB4PVS,Defines the privilege protection of the APB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "APB3PVS,Defines the privilege protection of the APB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "APB2PVS,Defines the privilege protection of the APB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "APB1PVS,Defines the privilege protection of the APB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "AHB5PVS,Defines the privilege protection of the AHB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "AHB4PVS,Defines the privilege protection of the AHB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "AHB3PVS,Defines the privilege protection of the AHB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "AHB2PVS,Defines the privilege protection of the AHB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "AHB1PVS,Defines the privilege protection of the AHB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "AHBMPVS,Defines the privilege protection of the AHBM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "ACLKNCPVS,Defines the privilege protection of the ACLKNC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "ACLKNPVS,Defines the privilege protection of the ACLKN configuration bits (enable ready divider)." "0,1" wgroup.long 0xFCC++0x7 line.long 0x0 "RCC_PUBCFGSR4,RCC public configuration register4" bitfld.long 0x0 13. "NOCPUBS,Defines the public protection of the NOC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "APB5PUBS,Defines the public protection of the APB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "APB4PUBS,Defines the public protection of the APB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "APB3PUBS,Defines the public protection of the APB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "APB2PUBS,Defines the public protection of the APB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "APB1PUBS,Defines the public protection of the APB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "AHB5PUBS,Defines the public protection of the AHB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "AHB4PUBS,Defines the public protection of the AHB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "AHB3PUBS,Defines the public protection of the AHB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "AHB2PUBS,Defines the public protection of the AHB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "AHB1PUBS,Defines the public protection of the AHB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "AHBMPUBS,Defines the public protection of the AHBM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "ACLKNCPUBS,Defines the public protection of the ACLKNC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "ACLKNPUBS,Defines the public protection of the ACLKN configuration bits (enable ready divider)." "0,1" line.long 0x4 "RCC_PUBCFGSR5,RCC public configuration register4" bitfld.long 0x4 11. "VENCRAMPUBS,Defines the public protection of the VENCRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 10. "NPUCACHERAMPUBS,Defines the public protection of the NPUCACHERAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 9. "FLEXRAMPUBS,Defines the public protection of the FLEXRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 8. "AXISRAM2PUBS,Defines the public protection of the AXISRAM2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 7. "AXISRAM1PUBS,Defines the public protection of the AXISRAM1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 6. "BKPSRAMPUBS,Defines the public protection of the BKPSRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 5. "AHBSRAM2PUBS,Defines the public protection of the AHBSRAM2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 4. "AHBSRAM1PUBS,Defines the public protection of the AHBSRAM1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 3. "AXISRAM6PUBS,Defines the public protection of the AXISRAM6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 2. "AXISRAM5PUBS,Defines the public protection of the AXISRAM5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 1. "AXISRAM4PUBS,Defines the public protection of the AXISRAM4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 0. "AXISRAM3PUBS,Defines the public protection of the AXISRAM3 configuration bits (enable ready divider)." "0,1" wgroup.long 0x1000++0x3 line.long 0x0 "RCC_CCR,RCC control Clear register" bitfld.long 0x0 11. "PLL4ONC,PLL4 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 10. "PLL3ONC,PLL3 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 9. "PLL2ONC,PLL2 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 8. "PLL1ONC,PLL1 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 4. "HSEONC,HSE oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 3. "HSIONC,HSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 2. "MSIONC,MSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 1. "LSEONC,LSE oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 0. "LSIONC,LSI oscillator enable in Run/Sleep mode." "0,1" wgroup.long 0x1008++0x3 line.long 0x0 "RCC_STOPCCR,RCC StopCCR configuration register" bitfld.long 0x0 3. "HSISTOPENC,HSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 2. "MSISTOPENC,MSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 1. "LSESTOPENC,LSE oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 0. "LSISTOPENC,LSI oscillator enable in Run/Sleep mode." "0,1" wgroup.long 0x1204++0x2B line.long 0x0 "RCC_BUSRSTCR,RCC bus reset register" bitfld.long 0x0 13. "NOCRSTC,NOC reset" "0,1" newline bitfld.long 0x0 12. "APB5RSTC,APB5 reset" "0,1" newline bitfld.long 0x0 11. "APB4RSTC,APB4 reset" "0,1" newline bitfld.long 0x0 10. "APB3RSTC,APB3 reset" "0,1" newline bitfld.long 0x0 9. "APB2RSTC,APB2 reset" "0,1" newline bitfld.long 0x0 8. "APB1RSTC,APB1 reset" "0,1" newline bitfld.long 0x0 7. "AHB5RSTC,AHB5 reset" "0,1" newline bitfld.long 0x0 6. "AHB4RSTC,AHB4 reset" "0,1" newline bitfld.long 0x0 5. "AHB3RSTC,AHB3 reset" "0,1" newline bitfld.long 0x0 4. "AHB2RSTC,AHB2 reset" "0,1" newline bitfld.long 0x0 3. "AHB1RSTC,AHB1 reset" "0,1" newline bitfld.long 0x0 2. "AHBMRSTC,AHBM reset" "0,1" newline bitfld.long 0x0 0. "ACLKNRSTC,ACLKN reset" "0,1" line.long 0x4 "RCC_MISCRSTCR,RCC miscellaneous reset register" bitfld.long 0x4 8. "SDMMC2DLLRSTC,SDMMC2DLL reset" "0,1" newline bitfld.long 0x4 7. "SDMMC1DLLRSTC,SDMMC1DLL reset" "0,1" newline bitfld.long 0x4 5. "XSPIPHY2RSTC,XSPIPHY2 reset" "0,1" newline bitfld.long 0x4 4. "XSPIPHY1RSTC,XSPIPHY1 reset" "0,1" newline bitfld.long 0x4 0. "DBGRSTC,DBG reset" "0,1" line.long 0x8 "RCC_MEMRSTCR,RCC memory reset register" bitfld.long 0x8 12. "BOOTROMRSTC,BOOTROM reset" "0,1" newline bitfld.long 0x8 11. "VENCRAMRSTC,VENCRAM reset" "0,1" newline bitfld.long 0x8 10. "NPUCACHERAMRSTC,NPUCACHERAM reset" "0,1" newline bitfld.long 0x8 9. "FLEXRAMRSTC,FLEXRAM reset" "0,1" newline bitfld.long 0x8 8. "AXISRAM2RSTC,AXISRAM2 reset" "0,1" newline bitfld.long 0x8 7. "AXISRAM1RSTC,AXISRAM1 reset" "0,1" newline bitfld.long 0x8 5. "AHBSRAM2RSTC,AHBSRAM2 reset" "0,1" newline bitfld.long 0x8 4. "AHBSRAM1RSTC,AHBSRAM1 reset" "0,1" newline bitfld.long 0x8 3. "AXISRAM6RSTC,AXISRAM6 reset" "0,1" newline bitfld.long 0x8 2. "AXISRAM5RSTC,AXISRAM5 reset" "0,1" newline bitfld.long 0x8 1. "AXISRAM4RSTC,AXISRAM4 reset" "0,1" newline bitfld.long 0x8 0. "AXISRAM3RSTC,AXISRAM3 reset" "0,1" line.long 0xC "RCC_AHB1RSTCR,RCC AHB1 reset register" bitfld.long 0xC 5. "ADC12RSTC,ADC12 reset" "0,1" newline bitfld.long 0xC 4. "GPDMA1RSTC,GPDMA1 reset" "0,1" line.long 0x10 "RCC_AHB2RSTCR,RCC AHB2 Reset register" bitfld.long 0x10 17. "ADF1RSTC,ADF1 reset" "0,1" newline bitfld.long 0x10 16. "MDF1RSTC,MDF1 reset" "0,1" newline bitfld.long 0x10 12. "RAMCFGRSTC,RAMCFG reset" "0,1" line.long 0x14 "RCC_AHB3RSTCR,RCC AHB3 reset register" bitfld.long 0x14 10. "IACRSTC,IAC reset" "0,1" newline bitfld.long 0x14 8. "PKARSTC,PKA reset" "0,1" newline bitfld.long 0x14 4. "SAESRSTC,SAES reset" "0,1" newline bitfld.long 0x14 2. "CRYPRSTC,CRYP reset" "0,1" newline bitfld.long 0x14 1. "HASHRSTC,HASH reset" "0,1" newline bitfld.long 0x14 0. "RNGRSTC,RNG reset" "0,1" line.long 0x18 "RCC_AHB4RSTCR,RCC AHB4 reset register" bitfld.long 0x18 19. "CRCRSTC,CRC reset" "0,1" newline bitfld.long 0x18 18. "PWRRSTC,PWR reset" "0,1" newline bitfld.long 0x18 16. "GPIOQRSTC,GPIOQ reset" "0,1" newline bitfld.long 0x18 15. "GPIOPRSTC,GPIOP reset" "0,1" newline bitfld.long 0x18 14. "GPIOORSTC,GPIOO reset" "0,1" newline bitfld.long 0x18 13. "GPIONRSTC,GPION reset" "0,1" newline bitfld.long 0x18 7. "GPIOHRSTC,GPIOH reset" "0,1" newline bitfld.long 0x18 6. "GPIOGRSTC,GPIOG reset" "0,1" newline bitfld.long 0x18 5. "GPIOFRSTC,GPIOF reset" "0,1" newline bitfld.long 0x18 4. "GPIOERSTC,GPIOE reset" "0,1" newline bitfld.long 0x18 3. "GPIODRSTC,GPIOD reset" "0,1" newline bitfld.long 0x18 2. "GPIOCRSTC,GPIOC reset" "0,1" newline bitfld.long 0x18 1. "GPIOBRSTC,GPIOB reset" "0,1" newline bitfld.long 0x18 0. "GPIOARSTC,GPIOA reset" "0,1" line.long 0x1C "RCC_AHB5RSTCR,RCC AHB5 reset register" bitfld.long 0x1C 31. "NPURSTC,NPU reset" "0,1" newline bitfld.long 0x1C 30. "NPUCACHERSTC,NPUCACHE reset" "0,1" newline bitfld.long 0x1C 29. "OTG2RSTC,OTG2 reset" "0,1" newline bitfld.long 0x1C 28. "OTGPHY2RSTC,OTGPHY2 reset" "0,1" newline bitfld.long 0x1C 27. "OTGPHY1RSTC,OTGPHY1 reset" "0,1" newline bitfld.long 0x1C 26. "OTG1RSTC,OTG1 reset" "0,1" newline bitfld.long 0x1C 25. "ETH1RSTC,ETH1 reset" "0,1" newline bitfld.long 0x1C 24. "SYSCFGOTGHSPHY2RSTC,SYSCFGOTGHSPHY2 reset" "0,1" newline bitfld.long 0x1C 23. "SYSCFGOTGHSPHY1RSTC,SYSCFGOTGHSPHY1 reset" "0,1" newline bitfld.long 0x1C 20. "GPURSTC,GPU reset" "0,1" newline bitfld.long 0x1C 19. "GFXMMURSTC,GFXMMU reset" "0,1" newline bitfld.long 0x1C 18. "MCE4RSTC,MCE4 reset" "0,1" newline bitfld.long 0x1C 17. "XSPI3RSTC,XSPI3 reset" "0,1" newline bitfld.long 0x1C 13. "XSPIMRSTC,XSPIM reset" "0,1" newline bitfld.long 0x1C 12. "XSPI2RSTC,XSPI2 reset" "0,1" newline bitfld.long 0x1C 8. "SDMMC1RSTC,SDMMC1 reset" "0,1" newline bitfld.long 0x1C 7. "SDMMC2RSTC,SDMMC2 reset" "0,1" newline bitfld.long 0x1C 6. "PSSIRSTC,PSSI reset" "0,1" newline bitfld.long 0x1C 5. "XSPI1RSTC,XSPI1 reset" "0,1" newline bitfld.long 0x1C 4. "FMCRSTC,FMC reset" "0,1" newline bitfld.long 0x1C 3. "JPEGRSTC,JPEG reset" "0,1" newline bitfld.long 0x1C 1. "DMA2DRSTC,DMA2D reset" "0,1" newline bitfld.long 0x1C 0. "HPDMA1RSTC,HPDMA1 reset" "0,1" line.long 0x20 "RCC_APB1LRSTCR,RCC APB1L reset register" bitfld.long 0x20 31. "UART8RSTC,UART8 reset" "0,1" newline bitfld.long 0x20 30. "UART7RSTC,UART7 reset" "0,1" newline bitfld.long 0x20 25. "I3C2RSTC,I3C2 reset" "0,1" newline bitfld.long 0x20 24. "I3C1RSTC,I3C1 reset" "0,1" newline bitfld.long 0x20 23. "I2C3RSTC,I2C3 reset" "0,1" newline bitfld.long 0x20 22. "I2C2RSTC,I2C2 reset" "0,1" newline bitfld.long 0x20 21. "I2C1RSTC,I2C1 reset" "0,1" newline bitfld.long 0x20 20. "UART5RSTC,UART5 reset" "0,1" newline bitfld.long 0x20 19. "UART4RSTC,UART4 reset" "0,1" newline bitfld.long 0x20 18. "USART3RSTC,USART3 reset" "0,1" newline bitfld.long 0x20 17. "USART2RSTC,USART2 reset" "0,1" newline bitfld.long 0x20 16. "SPDIFRX1RSTC,SPDIFRX1 reset" "0,1" newline bitfld.long 0x20 15. "SPI3RSTC,SPI3 reset" "0,1" newline bitfld.long 0x20 14. "SPI2RSTC,SPI2 reset" "0,1" newline bitfld.long 0x20 13. "TIM11RSTC,TIM11 reset" "0,1" newline bitfld.long 0x20 12. "TIM10RSTC,TIM10 reset" "0,1" newline bitfld.long 0x20 11. "WWDGRSTC,WWDG reset" "0,1" newline bitfld.long 0x20 9. "LPTIM1RSTC,LPTIM1 reset" "0,1" newline bitfld.long 0x20 8. "TIM14RSTC,TIM14 reset" "0,1" newline bitfld.long 0x20 7. "TIM13RSTC,TIM13 reset" "0,1" newline bitfld.long 0x20 6. "TIM12RSTC,TIM12 reset" "0,1" newline bitfld.long 0x20 5. "TIM7RSTC,TIM7 reset" "0,1" newline bitfld.long 0x20 4. "TIM6RSTC,TIM6 reset" "0,1" newline bitfld.long 0x20 3. "TIM5RSTC,TIM5 reset" "0,1" newline bitfld.long 0x20 2. "TIM4RSTC,TIM4 reset" "0,1" newline bitfld.long 0x20 1. "TIM3RSTC,TIM3 reset" "0,1" newline bitfld.long 0x20 0. "TIM2RSTC,TIM2 reset" "0,1" line.long 0x24 "RCC_APB1HRSTCR,RCC APB1H reset register" bitfld.long 0x24 18. "UCPD1RSTC,UCPD1 reset" "0,1" newline bitfld.long 0x24 8. "FDCANRSTC,FDCAN reset" "0,1" newline bitfld.long 0x24 5. "MDIOSRSTC,MDIOS reset" "0,1" line.long 0x28 "RCC_APB2RSTCR,RCC APB2 reset register" bitfld.long 0x28 22. "SAI2RSTC,SAI2 reset" "0,1" newline bitfld.long 0x28 21. "SAI1RSTC,SAI1 reset" "0,1" newline bitfld.long 0x28 20. "SPI5RSTC,SPI5 reset" "0,1" newline bitfld.long 0x28 19. "TIM9RSTC,TIM9 reset" "0,1" newline bitfld.long 0x28 18. "TIM17RSTC,TIM17 reset" "0,1" newline bitfld.long 0x28 17. "TIM16RSTC,TIM16 reset" "0,1" newline bitfld.long 0x28 16. "TIM15RSTC,TIM15 reset" "0,1" newline bitfld.long 0x28 15. "TIM18RSTC,TIM18 reset" "0,1" newline bitfld.long 0x28 13. "SPI4RSTC,SPI4 reset" "0,1" newline bitfld.long 0x28 12. "SPI1RSTC,SPI1 reset" "0,1" newline bitfld.long 0x28 7. "USART10RSTC,USART10 reset" "0,1" newline bitfld.long 0x28 6. "UART9RSTC,UART9 reset" "0,1" newline bitfld.long 0x28 5. "USART6RSTC,USART6 reset" "0,1" newline bitfld.long 0x28 4. "USART1RSTC,USART1 reset" "0,1" newline bitfld.long 0x28 1. "TIM8RSTC,TIM8 reset" "0,1" newline bitfld.long 0x28 0. "TIM1RSTC,TIM1 reset" "0,1" wgroup.long 0x1234++0x8B line.long 0x0 "RCC_APB4LRSTCR,RCC APB4L reset register" bitfld.long 0x0 31. "SERFRSTC,SERF reset" "0,1" newline bitfld.long 0x0 23. "R2GNPURSTC,R2GNPU reset" "0,1" newline bitfld.long 0x0 22. "R2GRETRSTC,R2GRET reset" "0,1" newline bitfld.long 0x0 16. "RTCRSTC,RTC reset" "0,1" newline bitfld.long 0x0 15. "VREFBUFRSTC,VREFBUF reset" "0,1" newline bitfld.long 0x0 12. "LPTIM5RSTC,LPTIM5 reset" "0,1" newline bitfld.long 0x0 11. "LPTIM4RSTC,LPTIM4 reset" "0,1" newline bitfld.long 0x0 10. "LPTIM3RSTC,LPTIM3 reset" "0,1" newline bitfld.long 0x0 9. "LPTIM2RSTC,LPTIM2 reset" "0,1" newline bitfld.long 0x0 7. "I2C4RSTC,I2C4 reset" "0,1" newline bitfld.long 0x0 5. "SPI6RSTC,SPI6 reset" "0,1" newline bitfld.long 0x0 3. "LPUART1RSTC,LPUART1 reset" "0,1" newline bitfld.long 0x0 2. "HDPRSTC,HDP reset" "0,1" line.long 0x4 "RCC_APB4HRSTCR,RCC APB4H reset register" bitfld.long 0x4 4. "BUSPERFMRSTC,BUSPERFM reset" "0,1" newline bitfld.long 0x4 2. "DTSRSTC,DTS reset" "0,1" newline bitfld.long 0x4 0. "SYSCFGRSTC,SYSCFG reset" "0,1" line.long 0x8 "RCC_APB5RSTCR,RCC APB5 reset register" bitfld.long 0x8 6. "CSIRSTC,CSI reset" "0,1" newline bitfld.long 0x8 5. "VENCRSTC,VENC reset" "0,1" newline bitfld.long 0x8 4. "GFXTIMRSTC,GFXTIM reset" "0,1" newline bitfld.long 0x8 2. "DCMIPPRSTC,DCMIPP reset" "0,1" newline bitfld.long 0x8 1. "LTDCRSTC,LTDC reset" "0,1" line.long 0xC "RCC_DIVENCR,RCC divider enable register" bitfld.long 0xC 19. "IC20ENC,IC20 enable" "0,1" newline bitfld.long 0xC 18. "IC19ENC,IC19 enable" "0,1" newline bitfld.long 0xC 17. "IC18ENC,IC18 enable" "0,1" newline bitfld.long 0xC 16. "IC17ENC,IC17 enable" "0,1" newline bitfld.long 0xC 15. "IC16ENC,IC16 enable" "0,1" newline bitfld.long 0xC 14. "IC15ENC,IC15 enable" "0,1" newline bitfld.long 0xC 13. "IC14ENC,IC14 enable" "0,1" newline bitfld.long 0xC 12. "IC13ENC,IC13 enable" "0,1" newline bitfld.long 0xC 11. "IC12ENC,IC12 enable" "0,1" newline bitfld.long 0xC 10. "IC11ENC,IC11 enable" "0,1" newline bitfld.long 0xC 9. "IC10ENC,IC10 enable" "0,1" newline bitfld.long 0xC 8. "IC9ENC,IC9 enable" "0,1" newline bitfld.long 0xC 7. "IC8ENC,IC8 enable" "0,1" newline bitfld.long 0xC 6. "IC7ENC,IC7 enable" "0,1" newline bitfld.long 0xC 5. "IC6ENC,IC6 enable" "0,1" newline bitfld.long 0xC 4. "IC5ENC,IC5 enable" "0,1" newline bitfld.long 0xC 3. "IC4ENC,IC4 enable" "0,1" newline bitfld.long 0xC 2. "IC3ENC,IC3 enable" "0,1" newline bitfld.long 0xC 1. "IC2ENC,IC2 enable" "0,1" newline bitfld.long 0xC 0. "IC1ENC,IC1 enable" "0,1" line.long 0x10 "RCC_BUSENCR,RCC bus enable register" bitfld.long 0x10 12. "APB5ENC,APB5 enable" "0,1" newline bitfld.long 0x10 11. "APB4ENC,APB4 enable" "0,1" newline bitfld.long 0x10 10. "APB3ENC,APB3 enable" "0,1" newline bitfld.long 0x10 9. "APB2ENC,APB2 enable" "0,1" newline bitfld.long 0x10 8. "APB1ENC,APB1 enable" "0,1" newline bitfld.long 0x10 7. "AHB5ENC,AHB5 enable" "0,1" newline bitfld.long 0x10 6. "AHB4ENC,AHB4 enable" "0,1" newline bitfld.long 0x10 5. "AHB3ENC,AHB3 enable" "0,1" newline bitfld.long 0x10 4. "AHB2ENC,AHB2 enable" "0,1" newline bitfld.long 0x10 3. "AHB1ENC,AHB1 enable" "0,1" newline bitfld.long 0x10 2. "AHBMENC,AHBM enable" "0,1" newline bitfld.long 0x10 1. "ACLKNCENC,ACLKNC enable" "0,1" newline bitfld.long 0x10 0. "ACLKNENC,ACLKN enable" "0,1" line.long 0x14 "RCC_MISCENCR,RCC miscellaneous enable register" bitfld.long 0x14 6. "PERENC,PER enable" "0,1" newline bitfld.long 0x14 3. "XSPIPHYCOMPENC,XSPIPHYCOMP enable" "0,1" newline bitfld.long 0x14 2. "MCO2ENC,MCO2 enable" "0,1" newline bitfld.long 0x14 1. "MCO1ENC,MCO1 enable" "0,1" newline bitfld.long 0x14 0. "DBGENC,DBG enable" "0,1" line.long 0x18 "RCC_MEMENCR,RCC memory enable register" bitfld.long 0x18 12. "BOOTROMENC,BOOTROM enable" "0,1" newline bitfld.long 0x18 11. "VENCRAMENC,VENCRAM enable" "0,1" newline bitfld.long 0x18 10. "NPUCACHERAMENC,NPUCACHERAM enable" "0,1" newline bitfld.long 0x18 9. "FLEXRAMENC,FLEXRAM enable" "0,1" newline bitfld.long 0x18 8. "AXISRAM2ENC,AXISRAM2 enable" "0,1" newline bitfld.long 0x18 7. "AXISRAM1ENC,AXISRAM1 enable" "0,1" newline bitfld.long 0x18 6. "BKPSRAMENC,BKPSRAM enable" "0,1" newline bitfld.long 0x18 5. "AHBSRAM2ENC,AHBSRAM2 enable" "0,1" newline bitfld.long 0x18 4. "AHBSRAM1ENC,AHBSRAM1 enable" "0,1" newline bitfld.long 0x18 3. "AXISRAM6ENC,AXISRAM6 enable" "0,1" newline bitfld.long 0x18 2. "AXISRAM5ENC,AXISRAM5 enable" "0,1" newline bitfld.long 0x18 1. "AXISRAM4ENC,AXISRAM4 enable" "0,1" newline bitfld.long 0x18 0. "AXISRAM3ENC,AXISRAM3 enable" "0,1" line.long 0x1C "RCC_AHB1ENCR,RCC AHB1 enable register" bitfld.long 0x1C 5. "ADC12ENC,ADC12 enable" "0,1" newline bitfld.long 0x1C 4. "GPDMA1ENC,GPDMA1 enable" "0,1" line.long 0x20 "RCC_AHB2ENCR,RCC AHB2 enable register" bitfld.long 0x20 17. "ADF1ENC,ADF1 enable" "0,1" newline bitfld.long 0x20 16. "MDF1ENC,MDF1 enable" "0,1" newline bitfld.long 0x20 12. "RAMCFGENC,RAMCFG enable" "0,1" line.long 0x24 "RCC_AHB3ENCR,RCC AHB3 enable register" bitfld.long 0x24 14. "RISAFENC,RISAF enable" "0,1" newline bitfld.long 0x24 10. "IACENC,IAC enable" "0,1" newline bitfld.long 0x24 9. "RIFSCENC,RIFSC enable" "0,1" newline bitfld.long 0x24 8. "PKAENC,PKA enable" "0,1" newline bitfld.long 0x24 4. "SAESENC,SAES enable" "0,1" newline bitfld.long 0x24 2. "CRYPENC,CRYP enable" "0,1" newline bitfld.long 0x24 1. "HASHENC,HASH enable" "0,1" newline bitfld.long 0x24 0. "RNGENC,RNG enable" "0,1" line.long 0x28 "RCC_AHB4ENCR,RCC AHB4 enable register" bitfld.long 0x28 19. "CRCENC,CRC enable" "0,1" newline bitfld.long 0x28 18. "PWRENC,PWR enable" "0,1" newline bitfld.long 0x28 16. "GPIOQENC,GPIOQ enable" "0,1" newline bitfld.long 0x28 15. "GPIOPENC,GPIOP enable" "0,1" newline bitfld.long 0x28 14. "GPIOOENC,GPIOO enable" "0,1" newline bitfld.long 0x28 13. "GPIONENC,GPION enable" "0,1" newline bitfld.long 0x28 7. "GPIOHENC,GPIOH enable" "0,1" newline bitfld.long 0x28 6. "GPIOGENC,GPIOG enable" "0,1" newline bitfld.long 0x28 5. "GPIOFENC,GPIOF enable" "0,1" newline bitfld.long 0x28 4. "GPIOEENC,GPIOE enable" "0,1" newline bitfld.long 0x28 3. "GPIODENC,GPIOD enable" "0,1" newline bitfld.long 0x28 2. "GPIOCENC,GPIOC enable" "0,1" newline bitfld.long 0x28 1. "GPIOBENC,GPIOB enable" "0,1" newline bitfld.long 0x28 0. "GPIOAENC,GPIOA enable" "0,1" line.long 0x2C "RCC_AHB5ENCR,RCC AHB5 enable register" bitfld.long 0x2C 31. "NPUENC,NPU enable" "0,1" newline bitfld.long 0x2C 30. "NPUCACHEENC,NPUCACHE enable" "0,1" newline bitfld.long 0x2C 29. "OTG2ENC,OTG2 enable" "0,1" newline bitfld.long 0x2C 28. "OTGPHY2ENC,OTGPHY2 enable" "0,1" newline bitfld.long 0x2C 27. "OTGPHY1ENC,OTGPHY1 enable" "0,1" newline bitfld.long 0x2C 26. "OTG1ENC,OTG1 enable" "0,1" newline bitfld.long 0x2C 25. "ETH1ENC,ETH1 enable" "0,1" newline bitfld.long 0x2C 24. "ETH1RXENC,ETH1RX enable" "0,1" newline bitfld.long 0x2C 23. "ETH1TXENC,ETH1TX enable" "0,1" newline bitfld.long 0x2C 22. "ETH1MACENC,ETH1MAC enable" "0,1" newline bitfld.long 0x2C 20. "GPUENC,GPU enable" "0,1" newline bitfld.long 0x2C 19. "GFXMMUENC,GFXMMU enable" "0,1" newline bitfld.long 0x2C 18. "MCE4ENC,MCE4 enable" "0,1" newline bitfld.long 0x2C 17. "XSPI3ENC,XSPI3 enable" "0,1" newline bitfld.long 0x2C 16. "MCE3ENC,MCE3 enable" "0,1" newline bitfld.long 0x2C 15. "MCE2ENC,MCE2 enable" "0,1" newline bitfld.long 0x2C 14. "MCE1ENC,MCE1 enable" "0,1" newline bitfld.long 0x2C 13. "XSPIMENC,XSPIM enable" "0,1" newline bitfld.long 0x2C 12. "XSPI2ENC,XSPI2 enable" "0,1" newline bitfld.long 0x2C 8. "SDMMC1ENC,SDMMC1 enable" "0,1" newline bitfld.long 0x2C 7. "SDMMC2ENC,SDMMC2 enable" "0,1" newline bitfld.long 0x2C 6. "PSSIENC,PSSI enable" "0,1" newline bitfld.long 0x2C 5. "XSPI1ENC,XSPI1 enable" "0,1" newline bitfld.long 0x2C 4. "FMCENC,FMC enable" "0,1" newline bitfld.long 0x2C 3. "JPEGENC,JPEG enable" "0,1" newline bitfld.long 0x2C 1. "DMA2DENC,DMA2D enable" "0,1" newline bitfld.long 0x2C 0. "HPDMA1ENC,HPDMA1 enable" "0,1" line.long 0x30 "RCC_APB1LENCR,RCC APB1L enable register" bitfld.long 0x30 31. "UART8ENC,UART8 enable" "0,1" newline bitfld.long 0x30 30. "UART7ENC,UART7 enable" "0,1" newline bitfld.long 0x30 25. "I3C2ENC,I3C2 enable" "0,1" newline bitfld.long 0x30 24. "I3C1ENC,I3C1 enable" "0,1" newline bitfld.long 0x30 23. "I2C3ENC,I2C3 enable" "0,1" newline bitfld.long 0x30 22. "I2C2ENC,I2C2 enable" "0,1" newline bitfld.long 0x30 21. "I2C1ENC,I2C1 enable" "0,1" newline bitfld.long 0x30 20. "UART5ENC,UART5 enable" "0,1" newline bitfld.long 0x30 19. "UART4ENC,UART4 enable" "0,1" newline bitfld.long 0x30 18. "USART3ENC,USART3 enable" "0,1" newline bitfld.long 0x30 17. "USART2ENC,USART2 enable" "0,1" newline bitfld.long 0x30 16. "SPDIFRX1ENC,SPDIFRX1 enable" "0,1" newline bitfld.long 0x30 15. "SPI3ENC,SPI3 enable" "0,1" newline bitfld.long 0x30 14. "SPI2ENC,SPI2 enable" "0,1" newline bitfld.long 0x30 13. "TIM11ENC,TIM11 enable" "0,1" newline bitfld.long 0x30 12. "TIM10ENC,TIM10 enable" "0,1" newline bitfld.long 0x30 9. "LPTIM1ENC,LPTIM1 enable" "0,1" newline bitfld.long 0x30 8. "TIM14ENC,TIM14 enable" "0,1" newline bitfld.long 0x30 7. "TIM13ENC,TIM13 enable" "0,1" newline bitfld.long 0x30 6. "TIM12ENC,TIM12 enable" "0,1" newline bitfld.long 0x30 5. "TIM7ENC,TIM7 enable" "0,1" newline bitfld.long 0x30 4. "TIM6ENC,TIM6 enable" "0,1" newline bitfld.long 0x30 3. "TIM5ENC,TIM5 enable" "0,1" newline bitfld.long 0x30 2. "TIM4ENC,TIM4 enable" "0,1" newline bitfld.long 0x30 1. "TIM3ENC,TIM3 enable" "0,1" newline bitfld.long 0x30 0. "TIM2ENC,TIM2 enable" "0,1" line.long 0x34 "RCC_APB1HENCR,RCC APB1H enable register" bitfld.long 0x34 18. "UCPD1ENC,UCPD1 enable" "0,1" newline bitfld.long 0x34 8. "FDCANENC,FDCAN enable" "0,1" newline bitfld.long 0x34 5. "MDIOSENC,MDIOS enable" "0,1" line.long 0x38 "RCC_APB2ENCR,RCC APB2 enable register" bitfld.long 0x38 22. "SAI2ENC,SAI2 enable" "0,1" newline bitfld.long 0x38 21. "SAI1ENC,SAI1 enable" "0,1" newline bitfld.long 0x38 20. "SPI5ENC,SPI5 enable" "0,1" newline bitfld.long 0x38 19. "TIM9ENC,TIM9 enable" "0,1" newline bitfld.long 0x38 18. "TIM17ENC,TIM17 enable" "0,1" newline bitfld.long 0x38 17. "TIM16ENC,TIM16 enable" "0,1" newline bitfld.long 0x38 16. "TIM15ENC,TIM15 enable" "0,1" newline bitfld.long 0x38 15. "TIM18ENC,TIM18 enable" "0,1" newline bitfld.long 0x38 13. "SPI4ENC,SPI4 enable" "0,1" newline bitfld.long 0x38 12. "SPI1ENC,SPI1 enable" "0,1" newline bitfld.long 0x38 7. "USART10ENC,USART10 enable" "0,1" newline bitfld.long 0x38 6. "UART9ENC,UART9 enable" "0,1" newline bitfld.long 0x38 5. "USART6ENC,USART6 enable" "0,1" newline bitfld.long 0x38 4. "USART1ENC,USART1 enable" "0,1" newline bitfld.long 0x38 1. "TIM8ENC,TIM8 enable" "0,1" newline bitfld.long 0x38 0. "TIM1ENC,TIM1 enable" "0,1" line.long 0x3C "RCC_APB3ENCR,RCC APB3 enable register" bitfld.long 0x3C 2. "DFTENC,DFT enable" "0,1" line.long 0x40 "RCC_APB4LENCR,RCC APB4L enable register" bitfld.long 0x40 31. "SERFENC,SERF enable" "0,1" newline bitfld.long 0x40 23. "R2GNPUENC,R2GNPU enable" "0,1" newline bitfld.long 0x40 22. "R2GRETENC,R2GRET enable" "0,1" newline bitfld.long 0x40 17. "RTCAPBENC,RTCAPB enable" "0,1" newline bitfld.long 0x40 16. "RTCENC,RTC enable" "0,1" newline bitfld.long 0x40 15. "VREFBUFENC,VREFBUF enable" "0,1" newline bitfld.long 0x40 12. "LPTIM5ENC,LPTIM5 enable" "0,1" newline bitfld.long 0x40 11. "LPTIM4ENC,LPTIM4 enable" "0,1" newline bitfld.long 0x40 10. "LPTIM3ENC,LPTIM3 enable" "0,1" newline bitfld.long 0x40 9. "LPTIM2ENC,LPTIM2 enable" "0,1" newline bitfld.long 0x40 7. "I2C4ENC,I2C4 enable" "0,1" newline bitfld.long 0x40 5. "SPI6ENC,SPI6 enable" "0,1" newline bitfld.long 0x40 3. "LPUART1ENC,LPUART1 enable" "0,1" newline bitfld.long 0x40 2. "HDPENC,HDP enable" "0,1" line.long 0x44 "RCC_APB4HENCR,RCC APB4H enable register" bitfld.long 0x44 4. "BUSPERFMENC,BUSPERFM enable" "0,1" newline bitfld.long 0x44 2. "DTSENC,DTS enable" "0,1" newline bitfld.long 0x44 1. "BSECENC,BSEC enable" "0,1" newline bitfld.long 0x44 0. "SYSCFGENC,SYSCFG enable" "0,1" line.long 0x48 "RCC_APB5ENCR,RCC APB5 enable register" bitfld.long 0x48 6. "CSIENC,CSI enable" "0,1" newline bitfld.long 0x48 5. "VENCENC,VENC enable" "0,1" newline bitfld.long 0x48 4. "GFXTIMENC,GFXTIM enable" "0,1" newline bitfld.long 0x48 2. "DCMIPPENC,DCMIPP enable" "0,1" newline bitfld.long 0x48 1. "LTDCENC,LTDC enable" "0,1" line.long 0x4C "RCC_DIVLPENCR,RCC divider Sleep enable register" bitfld.long 0x4C 19. "IC20LPENC,IC20 sleep enable" "0,1" newline bitfld.long 0x4C 18. "IC19LPENC,IC19 sleep enable" "0,1" newline bitfld.long 0x4C 17. "IC18LPENC,IC18 sleep enable" "0,1" newline bitfld.long 0x4C 16. "IC17LPENC,IC17 sleep enable" "0,1" newline bitfld.long 0x4C 15. "IC16LPENC,IC16 sleep enable" "0,1" newline bitfld.long 0x4C 14. "IC15LPENC,IC15 sleep enable" "0,1" newline bitfld.long 0x4C 13. "IC14LPENC,IC14 sleep enable" "0,1" newline bitfld.long 0x4C 12. "IC13LPENC,IC13 sleep enable" "0,1" newline bitfld.long 0x4C 11. "IC12LPENC,IC12 sleep enable" "0,1" newline bitfld.long 0x4C 10. "IC11LPENC,IC11 sleep enable" "0,1" newline bitfld.long 0x4C 9. "IC10LPENC,IC10 sleep enable" "0,1" newline bitfld.long 0x4C 8. "IC9LPENC,IC9 sleep enable" "0,1" newline bitfld.long 0x4C 7. "IC8LPENC,IC8 sleep enable" "0,1" newline bitfld.long 0x4C 6. "IC7LPENC,IC7 sleep enable" "0,1" newline bitfld.long 0x4C 5. "IC6LPENC,IC6 sleep enable" "0,1" newline bitfld.long 0x4C 4. "IC5LPENC,IC5 sleep enable" "0,1" newline bitfld.long 0x4C 3. "IC4LPENC,IC4 sleep enable" "0,1" newline bitfld.long 0x4C 2. "IC3LPENC,IC3 sleep enable" "0,1" newline bitfld.long 0x4C 1. "IC2LPENC,IC2 sleep enable" "0,1" newline bitfld.long 0x4C 0. "IC1LPENC,IC1 sleep enable" "0,1" line.long 0x50 "RCC_BUSLPENCR,RCC bus Sleep enable register" bitfld.long 0x50 12. "APB5LPENC,APB5 sleep enable" "0,1" newline bitfld.long 0x50 11. "APB4LPENC,APB4 sleep enable" "0,1" newline bitfld.long 0x50 10. "APB3LPENC,APB3 sleep enable" "0,1" newline bitfld.long 0x50 9. "APB2LPENC,APB2 sleep enable" "0,1" newline bitfld.long 0x50 8. "APB1LPENC,APB1 sleep enable" "0,1" newline bitfld.long 0x50 7. "AHB5LPENC,AHB5 sleep enable" "0,1" newline bitfld.long 0x50 6. "AHB4LPENC,AHB4 sleep enable" "0,1" newline bitfld.long 0x50 5. "AHB3LPENC,AHB3 sleep enable" "0,1" newline bitfld.long 0x50 4. "AHB2LPENC,AHB2 sleep enable" "0,1" newline bitfld.long 0x50 3. "AHB1LPENC,AHB1 sleep enable" "0,1" newline bitfld.long 0x50 2. "AHBMLPENC,AHBM sleep enable" "0,1" newline bitfld.long 0x50 1. "ACLKNCLPENC,ACLKNC sleep enable" "0,1" newline bitfld.long 0x50 0. "ACLKNLPENC,ACLKN sleep enable" "0,1" line.long 0x54 "RCC_MISCLPENCR,RCC miscellaneous Sleep enable register" bitfld.long 0x54 6. "PERLPENC,PER sleep enable" "0,1" newline bitfld.long 0x54 3. "XSPIPHYCOMPLPENC,XSPIPHYCOMP sleep enable" "0,1" newline bitfld.long 0x54 0. "DBGLPENC,DBG sleep enable" "0,1" line.long 0x58 "RCC_MEMLPENCR,RCC memory Sleep enable register" bitfld.long 0x58 12. "BOOTROMLPENC,BOOTROM sleep enable" "0,1" newline bitfld.long 0x58 11. "VENCRAMLPENC,VENCRAM sleep enable" "0,1" newline bitfld.long 0x58 10. "NPUCACHERAMLPENC,NPUCACHERAM sleep enable" "0,1" newline bitfld.long 0x58 9. "FLEXRAMLPENC,FLEXRAM sleep enable" "0,1" newline bitfld.long 0x58 8. "AXISRAM2LPENC,AXISRAM2 sleep enable" "0,1" newline bitfld.long 0x58 7. "AXISRAM1LPENC,AXISRAM1 sleep enable" "0,1" newline bitfld.long 0x58 6. "BKPSRAMLPENC,BKPSRAM sleep enable" "0,1" newline bitfld.long 0x58 5. "AHBSRAM2LPENC,AHBSRAM2 sleep enable" "0,1" newline bitfld.long 0x58 4. "AHBSRAM1LPENC,AHBSRAM1 sleep enable" "0,1" newline bitfld.long 0x58 3. "AXISRAM6LPENC,AXISRAM6 sleep enable" "0,1" newline bitfld.long 0x58 2. "AXISRAM5LPENC,AXISRAM5 sleep enable" "0,1" newline bitfld.long 0x58 1. "AXISRAM4LPENC,AXISRAM4 sleep enable" "0,1" newline bitfld.long 0x58 0. "AXISRAM3LPENC,AXISRAM3 sleep enable" "0,1" line.long 0x5C "RCC_AHB1LPENCR,RCC AHB1 Sleep enable register" bitfld.long 0x5C 5. "ADC12LPENC,ADC12 sleep enable" "0,1" newline bitfld.long 0x5C 4. "GPDMA1LPENC,GPDMA1 sleep enable" "0,1" line.long 0x60 "RCC_AHB2LPENCR,RCC AHB2 Sleep enable register" bitfld.long 0x60 17. "ADF1LPENC,ADF1 sleep enable" "0,1" newline bitfld.long 0x60 16. "MDF1LPENC,MDF1 sleep enable" "0,1" newline bitfld.long 0x60 12. "RAMCFGLPENC,RAMCFG sleep enable" "0,1" line.long 0x64 "RCC_AHB3LPENCR,RCC AHB3 Sleep enable register" bitfld.long 0x64 14. "RISAFLPENC,RISAF sleep enable" "0,1" newline bitfld.long 0x64 10. "IACLPENC,IAC sleep enable" "0,1" newline bitfld.long 0x64 9. "RIFSCLPENC,RIFSC sleep enable" "0,1" newline bitfld.long 0x64 8. "PKALPENC,PKA sleep enable" "0,1" newline bitfld.long 0x64 4. "SAESLPENC,SAES sleep enable" "0,1" newline bitfld.long 0x64 2. "CRYPLPENC,CRYP sleep enable" "0,1" newline bitfld.long 0x64 1. "HASHLPENC,HASH sleep enable" "0,1" newline bitfld.long 0x64 0. "RNGLPENC,RNG sleep enable" "0,1" line.long 0x68 "RCC_AHB4LPENCR,RCC AHB4 Sleep enable register" bitfld.long 0x68 19. "CRCLPENC,CRC sleep enable" "0,1" newline bitfld.long 0x68 18. "PWRLPENC,PWR sleep enable" "0,1" newline bitfld.long 0x68 16. "GPIOQLPENC,GPIOQ sleep enable" "0,1" newline bitfld.long 0x68 15. "GPIOPLPENC,GPIOP sleep enable" "0,1" newline bitfld.long 0x68 14. "GPIOOLPENC,GPIOO sleep enable" "0,1" newline bitfld.long 0x68 13. "GPIONLPENC,GPION sleep enable" "0,1" newline bitfld.long 0x68 7. "GPIOHLPENC,GPIOH sleep enable" "0,1" newline bitfld.long 0x68 6. "GPIOGLPENC,GPIOG sleep enable" "0,1" newline bitfld.long 0x68 5. "GPIOFLPENC,GPIOF sleep enable" "0,1" newline bitfld.long 0x68 4. "GPIOELPENC,GPIOE sleep enable" "0,1" newline bitfld.long 0x68 3. "GPIODLPENC,GPIOD sleep enable" "0,1" newline bitfld.long 0x68 2. "GPIOCLPENC,GPIOC sleep enable" "0,1" newline bitfld.long 0x68 1. "GPIOBLPENC,GPIOB sleep enable" "0,1" newline bitfld.long 0x68 0. "GPIOALPENC,GPIOA sleep enable" "0,1" line.long 0x6C "RCC_AHB5LPENCR,RCC AHB5 Sleep enable register" bitfld.long 0x6C 31. "NPULPENC,NPU sleep enable" "0,1" newline bitfld.long 0x6C 30. "NPUCACHELPENC,NPUCACHE sleep enable" "0,1" newline bitfld.long 0x6C 29. "OTG2LPENC,OTG2 sleep enable" "0,1" newline bitfld.long 0x6C 28. "OTGPHY2LPENC,OTGPHY2 sleep enable" "0,1" newline bitfld.long 0x6C 27. "OTGPHY1LPENC,OTGPHY1 sleep enable" "0,1" newline bitfld.long 0x6C 26. "OTG1LPENC,OTG1 sleep enable" "0,1" newline bitfld.long 0x6C 25. "ETH1LPENC,ETH1 sleep enable" "0,1" newline bitfld.long 0x6C 24. "ETH1RXLPENC,ETH1RX sleep enable" "0,1" newline bitfld.long 0x6C 23. "ETH1TXLPENC,ETH1TX sleep enable" "0,1" newline bitfld.long 0x6C 22. "ETH1MACLPENC,ETH1MAC sleep enable" "0,1" newline bitfld.long 0x6C 20. "GPULPENC,GPU sleep enable" "0,1" newline bitfld.long 0x6C 19. "GFXMMULPENC,GFXMMU sleep enable" "0,1" newline bitfld.long 0x6C 18. "MCE4LPENC,MCE4 sleep enable" "0,1" newline bitfld.long 0x6C 17. "XSPI3LPENC,XSPI3 sleep enable" "0,1" newline bitfld.long 0x6C 16. "MCE3LPENC,MCE3 sleep enable" "0,1" newline bitfld.long 0x6C 15. "MCE2LPENC,MCE2 sleep enable" "0,1" newline bitfld.long 0x6C 14. "MCE1LPENC,MCE1 sleep enable" "0,1" newline bitfld.long 0x6C 13. "XSPIMLPENC,XSPIM sleep enable" "0,1" newline bitfld.long 0x6C 12. "XSPI2LPENC,XSPI2 sleep enable" "0,1" newline bitfld.long 0x6C 8. "SDMMC1LPENC,SDMMC1 sleep enable" "0,1" newline bitfld.long 0x6C 7. "SDMMC2LPENC,SDMMC2 sleep enable" "0,1" newline bitfld.long 0x6C 6. "PSSILPENC,PSSI sleep enable" "0,1" newline bitfld.long 0x6C 5. "XSPI1LPENC,XSPI1 sleep enable" "0,1" newline bitfld.long 0x6C 4. "FMCLPENC,FMC sleep enable" "0,1" newline bitfld.long 0x6C 3. "JPEGLPENC,JPEG sleep enable" "0,1" newline bitfld.long 0x6C 1. "DMA2DLPENC,DMA2D sleep enable" "0,1" newline bitfld.long 0x6C 0. "HPDMA1LPENC,HPDMA1 sleep enable" "0,1" line.long 0x70 "RCC_APB1LLPENCR,RCC APB1L Sleep enable register" bitfld.long 0x70 31. "UART8LPENC,UART8 sleep enable" "0,1" newline bitfld.long 0x70 30. "UART7LPENC,UART7 sleep enable" "0,1" newline bitfld.long 0x70 25. "I3C2LPENC,I3C2 sleep enable" "0,1" newline bitfld.long 0x70 24. "I3C1LPENC,I3C1 sleep enable" "0,1" newline bitfld.long 0x70 23. "I2C3LPENC,I2C3 sleep enable" "0,1" newline bitfld.long 0x70 22. "I2C2LPENC,I2C2 sleep enable" "0,1" newline bitfld.long 0x70 21. "I2C1LPENC,I2C1 sleep enable" "0,1" newline bitfld.long 0x70 20. "UART5LPENC,UART5 sleep enable" "0,1" newline bitfld.long 0x70 19. "UART4LPENC,UART4 sleep enable" "0,1" newline bitfld.long 0x70 18. "USART3LPENC,USART3 sleep enable" "0,1" newline bitfld.long 0x70 17. "USART2LPENC,USART2 sleep enable" "0,1" newline bitfld.long 0x70 16. "SPDIFRX1LPENC,SPDIFRX1 sleep enable" "0,1" newline bitfld.long 0x70 15. "SPI3LPENC,SPI3 sleep enable" "0,1" newline bitfld.long 0x70 14. "SPI2LPENC,SPI2 sleep enable" "0,1" newline bitfld.long 0x70 13. "TIM11LPENC,TIM11 sleep enable" "0,1" newline bitfld.long 0x70 12. "TIM10LPENC,TIM10 sleep enable" "0,1" newline bitfld.long 0x70 11. "WWDGLPENC,WWDG sleep enable" "0,1" newline bitfld.long 0x70 9. "LPTIM1LPENC,LPTIM1 sleep enable" "0,1" newline bitfld.long 0x70 8. "TIM14LPENC,TIM14 sleep enable" "0,1" newline bitfld.long 0x70 7. "TIM13LPENC,TIM13 sleep enable" "0,1" newline bitfld.long 0x70 6. "TIM12LPENC,TIM12 sleep enable" "0,1" newline bitfld.long 0x70 5. "TIM7LPENC,TIM7 sleep enable" "0,1" newline bitfld.long 0x70 4. "TIM6LPENC,TIM6 sleep enable" "0,1" newline bitfld.long 0x70 3. "TIM5LPENC,TIM5 sleep enable" "0,1" newline bitfld.long 0x70 2. "TIM4LPENC,TIM4 sleep enable" "0,1" newline bitfld.long 0x70 1. "TIM3LPENC,TIM3 sleep enable" "0,1" newline bitfld.long 0x70 0. "TIM2LPENC,TIM2 sleep enable" "0,1" line.long 0x74 "RCC_APB1HLPENCR,RCC APB1H Sleep enable register" bitfld.long 0x74 18. "UCPD1LPENC,UCPD1 sleep enable" "0,1" newline bitfld.long 0x74 8. "FDCANLPENC,FDCAN sleep enable" "0,1" newline bitfld.long 0x74 5. "MDIOSLPENC,MDIOS sleep enable" "0,1" line.long 0x78 "RCC_APB2LPENCR,RCC APB2 Sleep enable register" bitfld.long 0x78 22. "SAI2LPENC,SAI2 sleep enable" "0,1" newline bitfld.long 0x78 21. "SAI1LPENC,SAI1 sleep enable" "0,1" newline bitfld.long 0x78 20. "SPI5LPENC,SPI5 sleep enable" "0,1" newline bitfld.long 0x78 19. "TIM9LPENC,TIM9 sleep enable" "0,1" newline bitfld.long 0x78 18. "TIM17LPENC,TIM17 sleep enable" "0,1" newline bitfld.long 0x78 17. "TIM16LPENC,TIM16 sleep enable" "0,1" newline bitfld.long 0x78 16. "TIM15LPENC,TIM15 sleep enable" "0,1" newline bitfld.long 0x78 15. "TIM18LPENC,TIM18 sleep enable" "0,1" newline bitfld.long 0x78 13. "SPI4LPENC,SPI4 sleep enable" "0,1" newline bitfld.long 0x78 12. "SPI1LPENC,SPI1 sleep enable" "0,1" newline bitfld.long 0x78 7. "USART10LPENC,USART10 sleep enable" "0,1" newline bitfld.long 0x78 6. "UART9LPENC,UART9 sleep enable" "0,1" newline bitfld.long 0x78 5. "USART6LPENC,USART6 sleep enable" "0,1" newline bitfld.long 0x78 4. "USART1LPENC,USART1 sleep enable" "0,1" newline bitfld.long 0x78 1. "TIM8LPENC,TIM8 sleep enable" "0,1" newline bitfld.long 0x78 0. "TIM1LPENC,TIM1 sleep enable" "0,1" line.long 0x7C "RCC_APB3LPENCR,RCC APB3 Sleep enable register" bitfld.long 0x7C 2. "DFTLPENC,DFT sleep enable" "0,1" line.long 0x80 "RCC_APB4LLPENCR,RCC APB4L Sleep enable register" bitfld.long 0x80 31. "SERFLPENC,SERF sleep enable" "0,1" newline bitfld.long 0x80 23. "R2GNPULPENC,R2GNPU sleep enable" "0,1" newline bitfld.long 0x80 22. "R2GRETLPENC,R2GRET sleep enable" "0,1" newline bitfld.long 0x80 17. "RTCAPBLPENC,RTCAPB sleep enable" "0,1" newline bitfld.long 0x80 16. "RTCLPENC,RTC sleep enable" "0,1" newline bitfld.long 0x80 15. "VREFBUFLPENC,VREFBUF sleep enable" "0,1" newline bitfld.long 0x80 12. "LPTIM5LPENC,LPTIM5 sleep enable" "0,1" newline bitfld.long 0x80 11. "LPTIM4LPENC,LPTIM4 sleep enable" "0,1" newline bitfld.long 0x80 10. "LPTIM3LPENC,LPTIM3 sleep enable" "0,1" newline bitfld.long 0x80 9. "LPTIM2LPENC,LPTIM2 sleep enable" "0,1" newline bitfld.long 0x80 7. "I2C4LPENC,I2C4 sleep enable" "0,1" newline bitfld.long 0x80 5. "SPI6LPENC,SPI6 sleep enable" "0,1" newline bitfld.long 0x80 3. "LPUART1LPENC,LPUART1 sleep enable" "0,1" newline bitfld.long 0x80 2. "HDPLPENC,HDP sleep enable" "0,1" line.long 0x84 "RCC_APB4HLPENCR,RCC APB4H Sleep enable register" bitfld.long 0x84 4. "BUSPERFMLPENC,BUSPERFM sleep enable" "0,1" newline bitfld.long 0x84 2. "DTSLPENC,DTS sleep enable" "0,1" newline bitfld.long 0x84 1. "BSECLPENC,BSEC sleep enable" "0,1" newline bitfld.long 0x84 0. "SYSCFGLPENC,SYSCFG sleep enable" "0,1" line.long 0x88 "RCC_APB5LPENCR,RCC APB5 Sleep enable register" bitfld.long 0x88 6. "CSILPENC,CSI sleep enable" "0,1" newline bitfld.long 0x88 5. "VENCLPENC,VENC sleep enable" "0,1" newline bitfld.long 0x88 4. "GFXTIMLPENC,GFXTIM sleep enable" "0,1" newline bitfld.long 0x88 2. "DCMIPPLPENC,DCMIPP sleep enable" "0,1" newline bitfld.long 0x88 1. "LTDCLPENC,LTDC sleep enable" "0,1" wgroup.long 0x1784++0x3 line.long 0x0 "RCC_PRIVCFGCR0,RCC oscillator privilege configuration register0" bitfld.long 0x0 4. "HSEPVC,Defines the privilege protection of the HSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "HSIPVC,Defines the privilege protection of the HSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "MSIPVC,Defines the privilege protection of the MSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "LSEPVC,Defines the privilege protection of the LSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "LSIPVC,Defines the privilege protection of the LSI configuration bits (enable ready divider)." "0,1" wgroup.long 0x178C++0x3 line.long 0x0 "RCC_PUBCFGCR0,RCC oscillator public configuration register0" bitfld.long 0x0 4. "HSEPUBC,Defines the public protection of the HSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "HSIPUBC,Defines the public protection of the HSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "MSIPUBC,Defines the public protection of the MSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "LSEPUBC,Defines the public protection of the LSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "LSIPUBC,Defines the public protection of the LSI configuration bits (enable ready divider)." "0,1" wgroup.long 0x1794++0x3 line.long 0x0 "RCC_PRIVCFGCR1,RCC PLL privilege configuration register1" bitfld.long 0x0 3. "PLL4PVC,Defines the privilege protection of the PLL4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "PLL3PVC,Defines the privilege protection of the PLL3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "PLL2PVC,Defines the privilege protection of the PLL2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "PLL1PVC,Defines the privilege protection of the PLL1 configuration bits (enable ready divider)." "0,1" wgroup.long 0x179C++0x3 line.long 0x0 "RCC_PUBCFGCR1,RCC PLL public configuration register1" bitfld.long 0x0 3. "PLL4PUBC,Defines the public protection of the PLL4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "PLL3PUBC,Defines the public protection of the PLL3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "PLL2PUBC,Defines the public protection of the PLL2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "PLL1PUBC,Defines the public protection of the PLL1 configuration bits (enable ready divider)." "0,1" wgroup.long 0x17A4++0x3 line.long 0x0 "RCC_PRIVCFGCR2,RCC divider privilege configuration register2" bitfld.long 0x0 19. "IC20PVC,Defines the privilege protection of the IC20 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 18. "IC19PVC,Defines the privilege protection of the IC19 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 17. "IC18PVC,Defines the privilege protection of the IC18 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 16. "IC17PVC,Defines the privilege protection of the IC17 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 15. "IC16PVC,Defines the privilege protection of the IC16 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 14. "IC15PVC,Defines the privilege protection of the IC15 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 13. "IC14PVC,Defines the privilege protection of the IC14 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "IC13PVC,Defines the privilege protection of the IC13 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "IC12PVC,Defines the privilege protection of the IC12 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "IC11PVC,Defines the privilege protection of the IC11 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "IC10PVC,Defines the privilege protection of the IC10 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "IC9PVC,Defines the privilege protection of the IC9 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "IC8PVC,Defines the privilege protection of the IC8 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "IC7PVC,Defines the privilege protection of the IC7 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "IC6PVC,Defines the privilege protection of the IC6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "IC5PVC,Defines the privilege protection of the IC5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "IC4PVC,Defines the privilege protection of the IC4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "IC3PVC,Defines the privilege protection of the IC3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "IC2PVC,Defines the privilege protection of the IC2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "IC1PVC,Defines the privilege protection of the IC1 configuration bits (enable ready divider)." "0,1" wgroup.long 0x17AC++0x3 line.long 0x0 "RCC_PUBCFGCR2,RCC divider public configuration register2" bitfld.long 0x0 19. "IC20PUBC,Defines the public protection of the IC20 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 18. "IC19PUBC,Defines the public protection of the IC19 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 17. "IC18PUBC,Defines the public protection of the IC18 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 16. "IC17PUBC,Defines the public protection of the IC17 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 15. "IC16PUBC,Defines the public protection of the IC16 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 14. "IC15PUBC,Defines the public protection of the IC15 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 13. "IC14PUBC,Defines the public protection of the IC14 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "IC13PUBC,Defines the public protection of the IC13 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "IC12PUBC,Defines the public protection of the IC12 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "IC11PUBC,Defines the public protection of the IC11 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "IC10PUBC,Defines the public protection of the IC10 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "IC9PUBC,Defines the public protection of the IC9 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "IC8PUBC,Defines the public protection of the IC8 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "IC7PUBC,Defines the public protection of the IC7 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "IC6PUBC,Defines the public protection of the IC6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "IC5PUBC,Defines the public protection of the IC5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "IC4PUBC,Defines the public protection of the IC4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "IC3PUBC,Defines the public protection of the IC3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "IC2PUBC,Defines the public protection of the IC2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "IC1PUBC,Defines the public protection of the IC1 configuration bits (enable ready divider)." "0,1" wgroup.long 0x17B4++0x3 line.long 0x0 "RCC_PRIVCFGCR3,RCC system privilege configuration register3" bitfld.long 0x0 6. "DFTPVC,Defines the privilege protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "RSTPVC,Defines the privilege protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "INTPVC,Defines the privilege protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "PERPVC,Defines the privilege protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "BUSPVC,Defines the privilege protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "SYSPVC,Defines the privilege protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "MODPVC,Defines the privilege protection of the MOD configuration bits (enable ready divider)." "0,1" wgroup.long 0x17BC++0x3 line.long 0x0 "RCC_PUBCFGCR3,RCC system public configuration register3" bitfld.long 0x0 6. "DFTPUBC,Defines the public protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "RSTPUBC,Defines the public protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "INTPUBC,Defines the public protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "PERPUBC,Defines the public protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "BUSPUBC,Defines the public protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "SYSPUBC,Defines the public protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "MODPUBC,Defines the public protection of the MOD configuration bits (enable ready divider)." "0,1" wgroup.long 0x17C4++0x3 line.long 0x0 "RCC_PRIVCFGCR4,RCC privilege configuration register4" bitfld.long 0x0 13. "NOCPVC,Defines the privilege protection of the NOC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "APB5PVC,Defines the privilege protection of the APB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "APB4PVC,Defines the privilege protection of the APB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "APB3PVC,Defines the privilege protection of the APB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "APB2PVC,Defines the privilege protection of the APB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "APB1PVC,Defines the privilege protection of the APB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "AHB5PVC,Defines the privilege protection of the AHB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "AHB4PVC,Defines the privilege protection of the AHB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "AHB3PVC,Defines the privilege protection of the AHB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "AHB2PVC,Defines the privilege protection of the AHB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "AHB1PVC,Defines the privilege protection of the AHB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "AHBMPVC,Defines the privilege protection of the AHBM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "ACLKNCPVC,Defines the privilege protection of the ACLKNC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "ACLKNPVC,Defines the privilege protection of the ACLKN configuration bits (enable ready divider)." "0,1" wgroup.long 0x17CC++0x7 line.long 0x0 "RCC_PUBCFGCR4,RCC public configuration register4" bitfld.long 0x0 13. "NOCPUBC,Defines the public protection of the NOC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "APB5PUBC,Defines the public protection of the APB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "APB4PUBC,Defines the public protection of the APB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "APB3PUBC,Defines the public protection of the APB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "APB2PUBC,Defines the public protection of the APB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "APB1PUBC,Defines the public protection of the APB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "AHB5PUBC,Defines the public protection of the AHB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "AHB4PUBC,Defines the public protection of the AHB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "AHB3PUBC,Defines the public protection of the AHB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "AHB2PUBC,Defines the public protection of the AHB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "AHB1PUBC,Defines the public protection of the AHB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "AHBMPUBC,Defines the public protection of the AHBM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "ACLKNCPUBC,Defines the public protection of the ACLKNC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "ACLKNPUBC,Defines the public protection of the ACLKN configuration bits (enable ready divider)." "0,1" line.long 0x4 "RCC_PUBCFGCR5,RCC public configuration register4" bitfld.long 0x4 11. "VENCRAMPUBC,Defines the public protection of the VENCRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 10. "CACHEAXIRAMPUBC,Defines the public protection of the NPUCACHERAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 9. "FLEXRAMPUBC,Defines the public protection of the FLEXRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 8. "AXISRAM2PUBC,Defines the public protection of the AXISRAM2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 7. "AXISRAM1PUBC,Defines the public protection of the AXISRAM1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 6. "BKPSRAMPUBC,Defines the public protection of the BKPSRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 5. "AHBSRAM2PUBC,Defines the public protection of the AHBSRAM2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 4. "AHBSRAM1PUBC,Defines the public protection of the AHBSRAM1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 3. "AXISRAM6PUBC,Defines the public protection of the AXISRAM6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 2. "AXISRAM5PUBC,Defines the public protection of the AXISRAM5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 1. "AXISRAM4PUBC,Defines the public protection of the AXISRAM4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 0. "AXISRAM3PUBC,Defines the public protection of the AXISRAM3 configuration bits (enable ready divider)." "0,1" tree.end tree "RCC_S" base ad:0x56028000 group.long 0x0++0x3 line.long 0x0 "RCC_CR,RCC control register" bitfld.long 0x0 11. "PLL4ON,PLL4 enable in Run/Sleep mode." "0: PLL4 is OFF (default after reset),1: PLL4 is ON" newline bitfld.long 0x0 10. "PLL3ON,PLL3 enable in Run/Sleep mode." "0: PLL3 is OFF (default after reset),1: PLL3 is ON" newline bitfld.long 0x0 9. "PLL2ON,PLL2 enable in Run/Sleep mode." "0: PLL2 is OFF (default after reset),1: PLL2 is ON" newline bitfld.long 0x0 8. "PLL1ON,PLL1 enable in Run/Sleep mode." "0: PLL1 is OFF (default after reset),1: PLL1 is ON" newline bitfld.long 0x0 4. "HSEON,HSE oscillator enable in Run/Sleep mode." "0: HSE is OFF (default after reset),1: HSE is ON" newline bitfld.long 0x0 3. "HSION,HSI oscillator enable in Run/Sleep mode." "0: HSI is OFF,1: HSI is ON (default after reset)" newline bitfld.long 0x0 2. "MSION,MSI oscillator enable in Run/Sleep mode." "0: MSI is OFF (default after reset),1: MSI is ON" newline bitfld.long 0x0 1. "LSEON,LSE oscillator enable in Run/Sleep mode." "0: LSE is OFF (default after reset),1: LSE is ON" newline bitfld.long 0x0 0. "LSION,LSI oscillator enable in Run/Sleep mode." "0: LSI is OFF (default after reset),1: LSI is ON" rgroup.long 0x4++0x3 line.long 0x0 "RCC_SR,RCC status register" bitfld.long 0x0 11. "PLL4RDY,PLL4 clock ready flag" "0: PLL4 unlocked (default after reset),1: PLL4 locked" newline bitfld.long 0x0 10. "PLL3RDY,PLL3 clock ready flag" "0: PLL3 unlocked (default after reset),1: PLL3 locked" newline bitfld.long 0x0 9. "PLL2RDY,PLL2 clock ready flag" "0: PLL2 unlocked (default after reset),1: PLL2 locked" newline bitfld.long 0x0 8. "PLL1RDY,PLL1 clock ready flag" "0: PLL1 unlocked (default after reset),1: PLL1 locked" newline bitfld.long 0x0 4. "HSERDY,HSE clock ready flag" "0: HSE is not ready (default after reset),1: HSE is ready" newline bitfld.long 0x0 3. "HSIRDY,HSI clock ready flag" "0: HSI is not ready,1: HSI is ready (default after reset)" newline bitfld.long 0x0 2. "MSIRDY,MSI clock ready flag" "0: MSI is not ready (default after reset),1: MSI is ready" newline bitfld.long 0x0 1. "LSERDY,LSE clock ready flag" "0: LSE is not ready (default after reset),1: LSE is ready" newline bitfld.long 0x0 0. "LSIRDY,LSI clock ready flag" "0: LSI is not ready (default after reset),1: LSI is ready" group.long 0x8++0x3 line.long 0x0 "RCC_STOPCR,RCC Stop mode control register" bitfld.long 0x0 3. "HSISTOPEN,HSI oscillator enable in Stop mode." "0: HSI is OFF,1: HSI is ON (default after reset)" newline bitfld.long 0x0 2. "MSISTOPEN,MSI oscillator enable in Stop mode." "0: MSI is OFF (default after reset),1: MSI is ON" newline bitfld.long 0x0 1. "LSESTOPEN,LSE oscillator enable in Stop mode." "0: LSE is OFF (default after reset),1: LSE is ON" newline bitfld.long 0x0 0. "LSISTOPEN,LSI oscillator enable in Stop mode." "0: LSI is OFF (default after reset),1: LSI is ON" group.long 0x20++0x7 line.long 0x0 "RCC_CFGR1,RCC configuration register 1" rbitfld.long 0x0 28.--29. "SYSSWS,System clock switch status" "0: hsi_ck selected as system clock (default after..,1: msi_ck selected as system clock,2: hse_ck selected as system clock,3: ic2_ck selected as system clock" newline bitfld.long 0x0 24.--25. "SYSSW,System clock switch selection" "0: hsi_ck selected as system clock (default after..,1: msi_ck selected as system clock,2: hse_ck selected as system clock,3: ic2_ck selected as system clock" newline rbitfld.long 0x0 20.--21. "CPUSWS,CPU clock switch status" "0: hsi_ck selected as system clock (default after..,1: msi_ck selected as system clock,2: hse_ck selected as system clock,3: ic1_ck selected as system clock" newline bitfld.long 0x0 16.--17. "CPUSW,CPU clock switch selection" "0: hsi_ck selected as system clock (default after..,1: msi_ck selected as system clock,2: hse_ck selected as system clock,3: ic1_ck selected as system clock" newline bitfld.long 0x0 0. "STOPWUCK,System clock selection after a wake up from system Stop." "0: HSI selected as wake up clock from system Stop..,1: CSI selected as wake up clock from system Stop" line.long 0x4 "RCC_CFGR2,RCC configuration register 2" bitfld.long 0x4 24.--25. "TIMPRE,Timers clocks prescaler selection" "0: timg_ck = sys_bus_ck (default after reset),1: timg_ck = sys_bus_ck / 2,2: timg_ck = sys_bus_ck / 4,?" newline bitfld.long 0x4 20.--22. "HPRE,AHB clock prescaler" "0: sys_bus2_ck= sys_bus_ck,1: sys_bus2_ck = sys_bus_ck / 2 (default after reset),2: sys_bus2_ck= sys_bus_ck / 4,3: sys_bus2_ck = sys_bus_ck / 8,4: sys_bus2_ck = sys_bus_ck / 16,5: sys_bus2_ck = sys_bus_ck / 32,6: sys_bus2_ck = sys_bus_ck / 64,7: sys_bus2_ck = sys_bus_ck / 128" newline bitfld.long 0x4 16.--18. "PPRE5,CPU domain APB5 prescaler" "0: rcc_pclk5 = sys_bus2_ck (default after reset),1: rcc_pclk5 = sys_bus2_ck / 2,2: rcc_pclk1 = sys_bus2_ck / 4,3: rcc_pclk1 = sys_bus2_ck / 8,4: rcc_pclk1 = sys_bus2_ck / 16,5: rcc_pclk1 = sys_bus2_ck / 32,6: rcc_pclk1 = sys_bus2_ck / 64,7: rcc_pclk1 = sys_bus2_ck / 128" newline bitfld.long 0x4 12.--14. "PPRE4,CPU domain APB4 prescaler" "0: rcc_pclk4 = sys_bus2_ck (default after reset),1: rcc_pclk4 = sys_bus2_ck / 2,2: rcc_pclk1 = sys_bus2_ck / 4,3: rcc_pclk1 = sys_bus2_ck / 8,4: rcc_pclk1 = sys_bus2_ck / 16,5: rcc_pclk1 = sys_bus2_ck / 32,6: rcc_pclk1 = sys_bus2_ck / 64,7: rcc_pclk1 = sys_bus2_ck / 128" newline bitfld.long 0x4 4.--6. "PPRE2,CPU domain APB2 prescaler" "0: rcc_pclk2 = sys_bus2_ck (default after reset),1: rcc_pclk2 = sys_bus2_ck / 2,2: rcc_pclk1 = sys_bus2_ck / 4,3: rcc_pclk1 = sys_bus2_ck / 8,4: rcc_pclk1 = sys_bus2_ck / 16,5: rcc_pclk1 = sys_bus2_ck / 32,6: rcc_pclk1 = sys_bus2_ck / 64,7: rcc_pclk1 = sys_bus2_ck / 128" newline bitfld.long 0x4 0.--2. "PPRE1,CPU domain APB1 prescaler" "0: rcc_pclk1 = sys_bus2_ck (default after reset),1: rcc_pclk1 = sys_bus2_ck / 2,2: rcc_pclk1 = sys_bus2_ck / 4,3: rcc_pclk1 = sys_bus2_ck / 8,4: rcc_pclk1 = sys_bus2_ck / 16,5: rcc_pclk1 = sys_bus2_ck / 32,6: rcc_pclk1 = sys_bus2_ck / 64,7: rcc_pclk1 = sys_bus2_ck / 128" rgroup.long 0x28++0x3 line.long 0x0 "RCC_CKPROTR,RCC clock protection register" bitfld.long 0x0 28.--29. "FMCSELS,FMC clock selection current status" "0: hclk5 selected as FMC clock (default after reset),1: per_ck selected as FMC clock,2: ic3_ck selected as FMC clock,3: ic4_ck selected as FMC clock" newline bitfld.long 0x0 24.--25. "XSPI1SELS,XSPI1 clock selection current status" "0: hclk5 selected as XSPI1 clock (default after..,1: per_ck selected as XSPI1 clock,2: ic3_ck selected as XSPI1 clock,3: ic4_ck selected as XSPI1 clock" newline bitfld.long 0x0 20.--21. "XSPI2SELS,XSPI2 clock selection current status" "0: hclk5 selected as XSPI2 clock (default after..,1: per_ck selected as XSPI2 clock,2: ic3_ck selected as XSPI2 clock,3: ic4_ck selected as XSPI2 clock" newline bitfld.long 0x0 16.--17. "XSPI3SELS,XSPI3 clock selection current status" "0: hclk5 selected as XSPI3 clock (default after..,1: per_ck selected as XSPI3 clock,2: ic3_ck selected as XSPI3 clock,3: ic4_ck selected as XSPI3 clock" group.long 0x2C++0xB line.long 0x0 "RCC_BDCR,RCC backup domain protection register" bitfld.long 0x0 31. "VSWRST,VSW domain software reset." "0: VSW domain is not reset (default after reset),1: VSW domain is reset" line.long 0x4 "RCC_HWRSR,RCC reset status register for hardware" rbitfld.long 0x4 30. "LPWRRSTF,Illegal Stop or Standby flag." "0: no illegal reset occurred (default after..,1: illegal Stop or Standby reset occurred" newline rbitfld.long 0x4 28. "WWDGRSTF,Window watchdog reset flag" "0: no Window Watchdog Reset occurred from WWDG..,1: Window Watchdog Reset occurred from WWDG" newline rbitfld.long 0x4 26. "IWDGRSTF,Independent Watchdog reset flag." "0: no Independent Watchdog Reset occurred (default..,1: Independent Watchdog Reset occurred" newline rbitfld.long 0x4 24. "SFTRSTF,Software system reset flag (1)" "0: no Software System reset occurred (default after..,1: a Software System reset has been generated by.." newline rbitfld.long 0x4 23. "PORRSTF,POR/PDR flag." "0: no POR/PDR reset occurred,1: POR/PDR reset occurred (default after power-on.." newline rbitfld.long 0x4 22. "PINRSTF,Pin reset flag (NRST)" "0: no reset from pin occurred,1: Reset from Pin occurred (default after power-on.." newline rbitfld.long 0x4 21. "BORRSTF,BOR flag" "0: no BOR occurred,1: BOR occurred (default after power-on reset)" newline rbitfld.long 0x4 17. "LCKRSTF,CPU lockup reset flag." "0: No reset from CPU lockup occurred,1: Reset from CPU lockup occurred" newline bitfld.long 0x4 16. "RMVF,Remove reset flag" "0: clear of the reset flags not activated (default..,1: clear the value of the reset flags" line.long 0x8 "RCC_RSR,RCC reset register" rbitfld.long 0x8 30. "LPWRRSTF,Illegal Stop or Standby flag." "0: no illegal reset occurred (default after..,1: illegal Stop or Standby reset occurred" newline rbitfld.long 0x8 28. "WWDGRSTF,Window Watchdog reset flag" "0: no Window Watchdog reset occurred from WWDG..,1: Window Watchdog reset occurred from WWDG" newline rbitfld.long 0x8 26. "IWDGRSTF,Independent Watchdog reset flag." "0: no Independent Watchdog reset occurred (default..,1: Independent Watchdog reset occurred" newline rbitfld.long 0x8 24. "SFTRSTF,Software System reset flag (1)" "0: no Software System reset occurred (default after..,1: a Software System reset has been generated by.." newline rbitfld.long 0x8 23. "PORRSTF,POR/PDR flag." "0: no POR/PDR reset occurred,1: POR/PDR reset occurred (default after power-on.." newline rbitfld.long 0x8 22. "PINRSTF,Pin reset flag (NRST)" "0: no reset from Pin occurred,1: Reset from Pin occurred (default after power-on.." newline rbitfld.long 0x8 21. "BORRSTF,BOR flag" "0: no BOR occurred,1: BOR occurred (default after power-on reset)" newline rbitfld.long 0x8 17. "LCKRSTF,CPU lockup reset flag." "0: No reset from CPU lockup occurred,1: Reset from CPU lockup occurred" newline bitfld.long 0x8 16. "RMVF,Remove reset flag" "0: clear of the reset flags not activated (default..,1: clear the value of the reset flags" group.long 0x40++0xF line.long 0x0 "RCC_LSECFGR,RCC LSE configuration register" bitfld.long 0x0 18.--19. "LSEDRV,LSE oscillator driving capability" "0: Lowest drive (default after reset),1: Medium low drive,2: Medium high drive,3: Highest drive" newline bitfld.long 0x0 17. "LSEGFON,LSE clock glitch filter enable" "0: LSE clock glitch filter is disabled (default..,1: LSE clock glitch filter is enabled" newline bitfld.long 0x0 16. "LSEEXT,LSE clock type in Bypass mode" "0: LSE in analog mode (default after reset),1: LSE in digital mode" newline bitfld.long 0x0 15. "LSEBYP,LSE clock bypass" "0: LSE oscillator not bypassed (default after reset),1: LSE oscillator bypassed with an external clock" newline rbitfld.long 0x0 9. "LSECSSD,LSE clock security system (CSS) failure detection" "0: No failure detected on the oscillator (default..,1: Failure detected on the oscillator" newline bitfld.long 0x0 8. "LSECSSRA,LSE clock security system (CSS) re-arm function" "0: Writing 0 has no effect (default after reset),1: Writing 1 generates a re-arm pulse for the.." newline bitfld.long 0x0 7. "LSECSSON,LSE clock security system (CSS) enable" "0: clock Security System on the LSE oscillator OFF..,1: clock Security System on the LSE oscillator ON" line.long 0x4 "RCC_MSICFGR,RCC MSI configuration register" hexmask.long.byte 0x4 23.--30. 1. "MSICAL,MSI clock calibration" newline hexmask.long.byte 0x4 16.--20. 1. "MSITRIM,MSI clock trimming" newline bitfld.long 0x4 9. "MSIFREQSEL,MSI oscillator frequency select" "0: MSI oscillator frequency is 4 MHz (default after..,1: MSI oscillator frequency is 16 MHz" line.long 0x8 "RCC_HSICFGR,RCC HSI configuration register" hexmask.long.word 0x8 23.--31. 1. "HSICAL,HSI clock calibration" newline hexmask.long.byte 0x8 16.--22. 1. "HSITRIM,HSI clock trimming" newline bitfld.long 0x8 7.--8. "HSIDIV,HSI clock divider" "0: hsi_ck = hsi_osc_ck (default after reset),1: hsi_ck = hsi_osc_ck / 2,?,?" line.long 0xC "RCC_HSIMCR,RCC HSI monitor control register" bitfld.long 0xC 31. "HSIMONEN,HSI clock period monitor enable" "0: Writing '0' disables the HSI clock period..,1: Writing '1' enables the HSI clock period.." newline hexmask.long.byte 0xC 16.--21. 1. "HSIDEV,HSI clock count deviation value" newline hexmask.long.word 0xC 0.--10. 1. "HSIREF,HSI clock cycle counter reference value." rgroup.long 0x50++0x3 line.long 0x0 "RCC_HSIMSR,RCC HSI monitor status register" hexmask.long.word 0x0 0.--10. 1. "HSIVAL,HSI clock cycle counter measured value." group.long 0x54++0x3 line.long 0x0 "RCC_HSECFGR,RCC HSE configuration register" bitfld.long 0x0 18.--19. "HSEDRV,HSE oscillator driving capability" "0: Lowest drive (default after reset),1: Medium low drive,2: Medium high drive,3: Highest drive" newline bitfld.long 0x0 17. "HSEGFON,HSE clock glitch filter enable" "0: LSE clock glitch filter is disabled (default..,1: LSE clock glitch filter is enabled" newline bitfld.long 0x0 16. "HSEEXT,HSE clock type in Bypass mode" "0: HSE in analog mode (default after reset),1: HSE in digital mode" newline bitfld.long 0x0 15. "HSEBYP,HSE clock bypass" "0: HSE oscillator not bypassed (default after reset),1: HSE oscillator bypassed with an external clock" newline hexmask.long.byte 0x0 11.--14. 1. "HSECSSBPRE,HSE clock security system (CSS) bypass divider" newline bitfld.long 0x0 10. "HSECSSBYP,HSE clock security system (CSS) bypass enable" "0: clock Security System Bypass of the HSE..,1: clock Security System Bypass on the HSE.." newline rbitfld.long 0x0 9. "HSECSSD,HSE clock security system (CSS) failure detection" "0: No failure detected on the oscillator (default..,1: Failure detected on the oscillator" newline bitfld.long 0x0 8. "HSECSSRA,HSE clock security system (CSS) re-arm function" "0: Writing 0 has no effect (default after reset),1: Writing 1 generates a re-arm pulse for the.." newline bitfld.long 0x0 7. "HSECSSON,HSE clock security system (CSS) enable" "0: clock Security System on the HSE oscillator OFF..,1: clock Security System on the HSE oscillator ON" newline bitfld.long 0x0 6. "HSEDIV2BYP,HSE div2 oscillator clock in Bypass mode" "0: HSE: hse_div2_osc_ck = hse_osc_ck/2 (default..,1: HSE: hse_div2_osc_ck = hse_osc_ck" group.long 0x80++0xB line.long 0x0 "RCC_PLL1CFGR1,RCC PLL1 configuration register 1" bitfld.long 0x0 28.--30. "PLL1SEL,PLL1 source selection of the reference clock" "0: hsi_ck selected as reference clock,1: msi_ck selected as reference clock,2: hse_ck selected as reference clock,3: I2S_CKIN selected as reference clock,?,?,?,?" newline bitfld.long 0x0 27. "PLL1BYP,PLL1 bypass" "0: PLL output is driven by the VCO via the optional..,1: PLL output is bypassed and driven by the PLL.." newline hexmask.long.byte 0x0 20.--25. 1. "PLL1DIVM,PLL1 reference input clock divide frequency ratio" newline hexmask.long.word 0x0 8.--19. 1. "PLL1DIVN,PLL1 Integer part for the VCO multiplication factor" line.long 0x4 "RCC_PLL1CFGR2,RCC PLL1 configuration register 2" hexmask.long.tbyte 0x4 0.--23. 1. "PLL1DIVNFRAC,PLL1 Fractional part of the VCO multiplication factor" line.long 0x8 "RCC_PLL1CFGR3,RCC PLL1 configuration register 3" bitfld.long 0x8 30. "PLL1PDIVEN,PLL1 post divider POSTDIV1 POSTDIV2 and PLL clock output enable" "0: POSTDIV1 and POSTDIV2 are powered down,1: POSTDIV1 and POSTDIV2 dividers are active.." newline bitfld.long 0x8 27.--29. "PLL1PDIV1,PLL1 VCO frequency divider level 1" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline bitfld.long 0x8 24.--26. "PLL1PDIV2,PLL1 VCO frequency divider level 2" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline hexmask.long.byte 0x8 16.--20. 1. "PLL1MODSPR,PLL1 Modulation Spread depth adjustment" newline hexmask.long.byte 0x8 8.--11. 1. "PLL1MODDIV,PLL1 Modulation Division frequency adjustment" newline bitfld.long 0x8 4. "PLL1MODSPRDW,PLL1 Modulation Spread-Spectrum Down" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x8 3. "PLL1MODDSEN,PLL1 Modulation Spread-Spectrum (and Fractional Divide) enable" "0: Modulation Spread-Spectrum and Fractional Divide..,1: Modulation Spread-Spectrum and Fractional Divide.." newline bitfld.long 0x8 2. "PLL1MODSSDIS,PLL1 Modulation Spread-Spectrum Disable" "0: Modulation Spread-Spectrum is active (and..,1: Fractional Divide is active (and the Modulation.." newline bitfld.long 0x8 1. "PLL1DACEN,PLL1 noise canceling DAC enable in fractional mode." "0: DAC is not active (default after reset),1: DAC is active" newline bitfld.long 0x8 0. "PLL1MODSSRST,PLL1 Modulation Spread Spectrum reset" "0: The PLL1 modulation Spread Spectrum reset module..,1: The PLL1 modulation Spread Spectrum reset module.." group.long 0x90++0xB line.long 0x0 "RCC_PLL2CFGR1,RCC PLL2 configuration register 1" bitfld.long 0x0 28.--30. "PLL2SEL,PLL2 source selection of the reference clock" "0: hsi_ck selected as reference clock,1: msi_ck selected as reference clock,2: hse_ck selected as reference clock,3: I2S_CKIN selected as reference clock,?,?,?,?" newline bitfld.long 0x0 27. "PLL2BYP,PLL2 bypass" "0: PLL output is driven by the VCO via the optional..,1: PLL output is bypassed and driven by the PLL.." newline hexmask.long.byte 0x0 20.--25. 1. "PLL2DIVM,PLL2 reference input clock divide frequency ratio" newline hexmask.long.word 0x0 8.--19. 1. "PLL2DIVN,PLL2 Integer part for the VCO multiplication factor" line.long 0x4 "RCC_PLL2CFGR2,RCC PLL2 configuration register 2" hexmask.long.tbyte 0x4 0.--23. 1. "PLL2DIVNFRAC,PLL2 Fractional part of the VCO multiplication factor" line.long 0x8 "RCC_PLL2CFGR3,RCC PLL2 configuration register 3" bitfld.long 0x8 30. "PLL2PDIVEN,PLL2 post divider POSTDIV1 POSTDIV2 and PLL clock output enable" "0: POSTDIV1 and POSTDIV2 are powered down,1: POSTDIV1 and POSTDIV2 dividers are active.." newline bitfld.long 0x8 27.--29. "PLL2PDIV1,PLL2 VCO frequency divider level 1" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline bitfld.long 0x8 24.--26. "PLL2PDIV2,PLL2 VCO frequency divider level 2" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline hexmask.long.byte 0x8 16.--20. 1. "PLL2MODSPR,PLL2 Modulation Spread depth adjustment" newline hexmask.long.byte 0x8 8.--11. 1. "PLL2MODDIV,PLL2 Modulation Division frequency adjustment" newline bitfld.long 0x8 4. "PLL2MODSPRDW,PLL2 Modulation Down Spread" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x8 3. "PLL2MODDSEN,PLL2 Modulation Spread-Spectrum (and Fractional Divide) enable" "0: Modulation Spread-Spectrum and Fractional Divide..,1: Modulation Spread-Spectrum and Fractional Divide.." newline bitfld.long 0x8 2. "PLL2MODSSDIS,PLL2 Modulation Spread-Spectrum Disable" "0: Modulation Spread-Spectrum is active (and..,1: Fractional Divide is active (and the Modulation.." newline bitfld.long 0x8 1. "PLL2DACEN,PLL2 noise canceling DAC enable in fractional mode." "0: DAC is not active (default after reset),1: DAC is active" newline bitfld.long 0x8 0. "PLL2MODSSRST,PLL2 Modulation Spread Spectrum reset" "0: The PLL2 Modulation Spread Spectrum reset module..,1: The PLL2 Modulation Spread Spectrum reset module.." group.long 0xA0++0xB line.long 0x0 "RCC_PLL3CFGR1,RCC PLL3 configuration register 1" bitfld.long 0x0 28.--30. "PLL3SEL,PLL3 source selection of the reference clock" "0: hsi_ck selected as reference clock,1: msi_ck selected as reference clock,2: hse_ck selected as reference clock,3: I2S_CKIN selected as reference clock,?,?,?,?" newline bitfld.long 0x0 27. "PLL3BYP,PLL3 bypass" "0: PLL output is driven by the VCO via the optional..,1: PLL output is bypassed and driven by the PLL.." newline hexmask.long.byte 0x0 20.--25. 1. "PLL3DIVM,PLL3 reference input clock divide frequency ratio" newline hexmask.long.word 0x0 8.--19. 1. "PLL3DIVN,PLL3 Integer part for the VCO multiplication factor" line.long 0x4 "RCC_PLL3CFGR2,RCC PLL3 configuration register 2" hexmask.long.tbyte 0x4 0.--23. 1. "PLL3DIVNFRAC,PLL3 Fractional part of the VCO multiplication factor" line.long 0x8 "RCC_PLL3CFGR3,RCC PLL3 configuration register 3" bitfld.long 0x8 30. "PLL3PDIVEN,PLL3 post divider POSTDIV1 POSTDIV2 and PLL clock output enable" "0: POSTDIV1 and POSTDIV2 are powered down,1: POSTDIV1 and POSTDIV2 dividers are active.." newline bitfld.long 0x8 27.--29. "PLL3PDIV1,PLL3 VCO frequency divider level 1" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline bitfld.long 0x8 24.--26. "PLL3PDIV2,PLL3 VCO frequency divider level 2" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline hexmask.long.byte 0x8 16.--20. 1. "PLL3MODSPR,PLL3 Modulation Spread depth adjustment" newline hexmask.long.byte 0x8 8.--11. 1. "PLL3MODDIV,PLL3 Modulation Division frequency adjustment" newline bitfld.long 0x8 4. "PLL3MODSPRDW,PLL3 Modulation Down Spread" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x8 3. "PLL3MODDSEN,PLL3 Modulation Spread-Spectrum (and Fractional Divide) enable" "0: Modulation Spread-Spectrum and Fractional Divide..,1: Modulation Spread-Spectrum and Fractional Divide.." newline bitfld.long 0x8 2. "PLL3MODSSDIS,PLL3 Modulation Spread-Spectrum Disable" "0: Modulation Spread-Spectrum is active (and..,1: Fractional Divide is active (and the Modulation.." newline bitfld.long 0x8 1. "PLL3DACEN,PLL3 noise canceling DAC enable in fractional mode." "0: DAC is not active (default after reset),1: DAC is active" newline bitfld.long 0x8 0. "PLL3MODSSRST,PLL3 Modulation Spread Spectrum reset" "0: The PLL3 modulation Spread Spectrum reset module..,1: The PLL3 modulation Spread Spectrum reset module.." group.long 0xB0++0xB line.long 0x0 "RCC_PLL4CFGR1,RCC PLL4 configuration register 1" bitfld.long 0x0 28.--30. "PLL4SEL,PLL4 source selection of the reference clock" "0: hsi_ck selected as reference clock,1: msi_ck selected as reference clock,2: hse_ck selected as reference clock,3: I2S_CKIN selected as reference clock,?,?,?,?" newline bitfld.long 0x0 27. "PLL4BYP,PLL4 bypass" "0: PLL output is driven by the VCO via the optional..,1: PLL output is bypassed and driven by the PLL.." newline hexmask.long.byte 0x0 20.--25. 1. "PLL4DIVM,PLL4 reference input clock divide frequency ratio" newline hexmask.long.word 0x0 8.--19. 1. "PLL4DIVN,PLL4 Integer part for the VCO multiplication factor" line.long 0x4 "RCC_PLL4CFGR2,RCC PLL4 configuration register 2" hexmask.long.tbyte 0x4 0.--23. 1. "PLL4DIVNFRAC,PLL4 Fractional part of the VCO multiplication factor" line.long 0x8 "RCC_PLL4CFGR3,RCC PLL4 configuration register 3" bitfld.long 0x8 30. "PLL4PDIVEN,PLL4 post divider POSTDIV1 POSTDIV2 and PLL clock output enable" "0: POSTDIV1 and POSTDIV2 are powered down,1: POSTDIV1 and POSTDIV2 dividers are active.." newline bitfld.long 0x8 27.--29. "PLL4PDIV1,PLL4 VCO frequency divider level 1" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline bitfld.long 0x8 24.--26. "PLL4PDIV2,PLL4 VCO frequency divider level 2" "0: Not applicable,1: VCO output is divided by 1 (minimum value)..,?,?,?,?,?,7: VCO output is divided by 7" newline hexmask.long.byte 0x8 16.--20. 1. "PLL4MODSPR,PLL4 Modulation Spread depth adjustment" newline hexmask.long.byte 0x8 8.--11. 1. "PLL4MODDIV,PLL4 Modulation Division frequency adjustment" newline bitfld.long 0x8 4. "PLL4MODSPRDW,PLL4 Modulation Down Spread" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x8 3. "PLL4MODDSEN,PLL4 Modulation Spread-Spectrum (and Fractional Divide) enable" "0: Modulation Spread-Spectrum and Fractional Divide..,1: Modulation Spread-Spectrum and Fractional Divide.." newline bitfld.long 0x8 2. "PLL4MODSSDIS,PLL4 Modulation Spread-Spectrum Disable" "0: Modulation Spread-Spectrum is active (and..,1: Fractional Divide is active (and the Modulation.." newline bitfld.long 0x8 1. "PLL4DACEN,PLL4 noise canceling DAC enable in fractional mode." "0: DAC is not active (default after reset),1: DAC is active" newline bitfld.long 0x8 0. "PLL4MODSSRST,PLL4 Modulation Spread Spectrum reset" "0: The PLL4 modulation Spread Spectrum reset module..,1: The PLL4 modulation Spread Spectrum reset module.." group.long 0xC4++0x4F line.long 0x0 "RCC_IC1CFGR,RCC IC1 configuration register" bitfld.long 0x0 28.--29. "IC1SEL,Divider IC1 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x0 16.--23. 1. "IC1INT,Divider IC1 integer division factor" line.long 0x4 "RCC_IC2CFGR,RCC IC2 configuration register" bitfld.long 0x4 28.--29. "IC2SEL,Divider IC2 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x4 16.--23. 1. "IC2INT,Divider IC2 integer division factor" line.long 0x8 "RCC_IC3CFGR,RCC IC3 configuration register" bitfld.long 0x8 28.--29. "IC3SEL,Divider IC3 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x8 16.--23. 1. "IC3INT,Divider IC3 integer division factor" line.long 0xC "RCC_IC4CFGR,RCC IC4 configuration register" bitfld.long 0xC 28.--29. "IC4SEL,Divider IC4 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0xC 16.--23. 1. "IC4INT,Divider IC4 integer division factor" line.long 0x10 "RCC_IC5CFGR,RCC IC5 configuration register" bitfld.long 0x10 28.--29. "IC5SEL,Divider IC5 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x10 16.--23. 1. "IC5INT,Divider IC5 integer division factor" line.long 0x14 "RCC_IC6CFGR,RCC IC6 configuration register" bitfld.long 0x14 28.--29. "IC6SEL,Divider IC6 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x14 16.--23. 1. "IC6INT,Divider IC6 integer division factor" line.long 0x18 "RCC_IC7CFGR,RCC IC7 configuration register" bitfld.long 0x18 28.--29. "IC7SEL,Divider IC7 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected (default after reset),2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x18 16.--23. 1. "IC7INT,Divider IC7 integer division factor" line.long 0x1C "RCC_IC8CFGR,RCC IC8 configuration register" bitfld.long 0x1C 28.--29. "IC8SEL,Divider IC8 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected (default after reset),2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x1C 16.--23. 1. "IC8INT,Divider IC8 integer division factor" line.long 0x20 "RCC_IC9CFGR,RCC IC9 configuration register" bitfld.long 0x20 28.--29. "IC9SEL,Divider IC9 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected (default after reset),2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x20 16.--23. 1. "IC9INT,Divider IC9 integer division factor" line.long 0x24 "RCC_IC10CFGR,RCC IC10 configuration register" bitfld.long 0x24 28.--29. "IC10SEL,Divider IC10 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected (default after reset),2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x24 16.--23. 1. "IC10INT,Divider IC10 integer division factor" line.long 0x28 "RCC_IC11CFGR,RCC IC11 configuration register" bitfld.long 0x28 28.--29. "IC11SEL,Divider IC11 Source Selection" "0: pll1_ck is selected (default after reset),1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x28 16.--23. 1. "IC11INT,Divider IC11 integer division factor" line.long 0x2C "RCC_IC12CFGR,RCC IC12 configuration register" bitfld.long 0x2C 28.--29. "IC12SEL,Divider IC12 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x2C 16.--23. 1. "IC12INT,Divider IC12 integer division factor" line.long 0x30 "RCC_IC13CFGR,RCC IC13 configuration register" bitfld.long 0x30 28.--29. "IC13SEL,Divider IC13 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x30 16.--23. 1. "IC13INT,Divider IC13 integer division factor" line.long 0x34 "RCC_IC14CFGR,RCC IC14 configuration register" bitfld.long 0x34 28.--29. "IC14SEL,Divider IC14 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x34 16.--23. 1. "IC14INT,Divider IC14 integer division factor" line.long 0x38 "RCC_IC15CFGR,RCC IC15 configuration register" bitfld.long 0x38 28.--29. "IC15SEL,Divider IC15 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x38 16.--23. 1. "IC15INT,Divider IC15 integer division factor" line.long 0x3C "RCC_IC16CFGR,RCC IC16 configuration register" bitfld.long 0x3C 28.--29. "IC16SEL,Divider IC16 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x3C 16.--23. 1. "IC16INT,Divider IC16 integer division factor" line.long 0x40 "RCC_IC17CFGR,RCC IC17 configuration register" bitfld.long 0x40 28.--29. "IC17SEL,Divider IC17 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x40 16.--23. 1. "IC17INT,Divider IC17 integer division factor" line.long 0x44 "RCC_IC18CFGR,RCC IC18 configuration register" bitfld.long 0x44 28.--29. "IC18SEL,Divider IC18 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x44 16.--23. 1. "IC18INT,Divider IC18 integer division factor" line.long 0x48 "RCC_IC19CFGR,RCC IC19 configuration register" bitfld.long 0x48 28.--29. "IC19SEL,Divider IC19 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x48 16.--23. 1. "IC19INT,Divider IC19 integer division factor" line.long 0x4C "RCC_IC20CFGR,RCC IC20 configuration register" bitfld.long 0x4C 28.--29. "IC20SEL,Divider IC20 Source Selection" "0: pll1_ck is selected,1: pll2_ck is selected,2: hsi_ck = hsi_osc_ck / 4,3: hsi_ck = hsi_osc_ck / 8" newline hexmask.long.byte 0x4C 16.--23. 1. "IC20INT,Divider IC20 integer division factor" group.long 0x124++0x3 line.long 0x0 "RCC_CIER,RCC clock-source interrupt enable register" bitfld.long 0x0 24. "WKUPIE,CPU wakeup from Stop interrupt enable" "0: Wakeup interrupt disabled (default after reset),1: Wakeup interrupt enabled" newline bitfld.long 0x0 17. "HSECSSIE,HSE clock security system (CSS) interrupt enable" "0: HSE CSS interrupt disabled,1: HSE CSS interrupt enabled (default after reset)" newline bitfld.long 0x0 16. "LSECSSIE,LSE clock security system (CSS) interrupt enable" "0: LSE CSS interrupt disabled (default after reset),1: LSE CSS interrupt enabled" newline bitfld.long 0x0 11. "PLL4RDYIE,PLL4 ready interrupt enable" "0: PLL4 lock interrupt disabled (default after reset),1: PLL4 lock interrupt enabled" newline bitfld.long 0x0 10. "PLL3RDYIE,PLL3 ready interrupt enable" "0: PLL3 lock interrupt disabled (default after reset),1: PLL3 lock interrupt enabled" newline bitfld.long 0x0 9. "PLL2RDYIE,PLL2 ready interrupt enable" "0: PLL2 lock interrupt disabled (default after reset),1: PLL2 lock interrupt enabled" newline bitfld.long 0x0 8. "PLL1RDYIE,PLL1 ready interrupt enable" "0: PLL1 lock interrupt disabled (default after reset),1: PLL1 lock interrupt enabled" newline bitfld.long 0x0 4. "HSERDYIE,HSE ready interrupt enable" "0: HSE ready interrupt disabled (default after reset),1: HSE ready interrupt enabled" newline bitfld.long 0x0 3. "HSIRDYIE,HSI ready interrupt enable" "0: HSI ready interrupt disabled (default after reset),1: HSI ready interrupt enabled" newline bitfld.long 0x0 2. "MSIRDYIE,MSI ready interrupt enable" "0: MSI ready interrupt disabled (default after reset),1: MSI ready interrupt enabled" newline bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0: LSE ready interrupt disabled (default after reset),1: LSE ready interrupt enabled" newline bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0: LSI ready interrupt disabled (default after reset),1: LSI ready interrupt enabled" rgroup.long 0x128++0x3 line.long 0x0 "RCC_CIFR,RCC clock-source interrupt flag register" bitfld.long 0x0 24. "WKUPF,CPU wakeup from Stop interrupt flag" "0: no wakeup interrupt caused by the PWR (default..,1: wakeup interrupt caused by the PWR" newline bitfld.long 0x0 17. "HSECSSF,HSE ready interrupt flag" "0: no clock ready interrupt caused by the HSE..,1: clock ready interrupt caused by the HSE" newline bitfld.long 0x0 16. "LSECSSF,LSE ready interrupt flag" "0: no clock ready interrupt caused by the LSE..,1: clock ready interrupt caused by the LSE" newline bitfld.long 0x0 11. "PLL4RDYF,PLL4 ready interrupt flag" "0: no clock ready interrupt caused by the PLL4..,1: clock ready interrupt caused by the PLL4" newline bitfld.long 0x0 10. "PLL3RDYF,PLL3 ready interrupt flag" "0: no clock ready interrupt caused by the PLL3..,1: clock ready interrupt caused by the PLL3" newline bitfld.long 0x0 9. "PLL2RDYF,PLL2 ready interrupt flag" "0: no clock ready interrupt caused by the PLL2..,1: clock ready interrupt caused by the PLL2" newline bitfld.long 0x0 8. "PLL1RDYF,PLL1 ready interrupt flag" "0: no clock ready interrupt caused by the PLL1..,1: clock ready interrupt caused by the PLL1" newline bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0: no clock ready interrupt caused by the HSE..,1: clock ready interrupt caused by the HSE" newline bitfld.long 0x0 3. "HSIRDYF,HSI ready interrupt flag" "0: no clock ready interrupt caused by the HSI..,1: clock ready interrupt caused by the HSI" newline bitfld.long 0x0 2. "MSIRDYF,MSI ready interrupt flag" "0: no clock ready interrupt caused by the MSI..,1: clock ready interrupt caused by the MSI" newline bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: no clock ready interrupt caused by the LSE..,1: clock ready interrupt caused by the LSE" newline bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: no clock ready interrupt caused by the LSI..,1: clock ready interrupt caused by the LSI" wgroup.long 0x12C++0x3 line.long 0x0 "RCC_CICR,RCC clock-source interrupt Clear register" bitfld.long 0x0 24. "WKUPFC,CPU Wakeup ready interrupt clear" "0: WKUPF not modified (default after reset),1: WKUPF cleared" newline bitfld.long 0x0 17. "HSECSSC,HSE ready interrupt clear" "0: HSECSSF not modified (default after reset),1: HSECSSF cleared" newline bitfld.long 0x0 16. "LSECSSC,LSE ready interrupt clear" "0: LSECSSF not modified (default after reset),1: LSECSSF cleared" newline bitfld.long 0x0 11. "PLL4RDYC,PLL4 ready interrupt clear" "0: PLL4RDYF not modified (default after reset),1: PLL4RDYF cleared" newline bitfld.long 0x0 10. "PLL3RDYC,PLL3 ready interrupt clear" "0: PLL3RDYF not modified (default after reset),1: PLL3RDYF cleared" newline bitfld.long 0x0 9. "PLL2RDYC,PLL2 ready interrupt clear" "0: PLL2RDYF not modified (default after reset),1: PLL2RDYF cleared" newline bitfld.long 0x0 8. "PLL1RDYC,PLL1 ready interrupt clear" "0: PLL1RDYF not modified (default after reset),1: PLL1RDYF cleared" newline bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0: HSERDYF not modified (default after reset),1: HSERDYF cleared" newline bitfld.long 0x0 3. "HSIRDYC,HSI ready interrupt clear" "0: HSIRDYF not modified (default after reset),1: HSIRDYF cleared" newline bitfld.long 0x0 2. "MSIRDYC,MSI ready interrupt clear" "0: MSIRDYF not modified (default after reset),1: MSIRDYF cleared" newline bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: LSERDYF not modified (default after reset),1: LSERDYF cleared" newline bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: LSIRDYF not modified (default after reset),1: LSIRDYF cleared" group.long 0x144++0x23 line.long 0x0 "RCC_CCIPR1,RCC clock configuration for independent peripheral register1" bitfld.long 0x0 20.--21. "DCMIPPSEL,Source selection for the DCMIPP kernel clock" "0: pclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic17_ck selected as reference clock,3: hsi_div_ck selected as reference clock" newline hexmask.long.byte 0x0 8.--15. 1. "ADCPRE,ADC12 Prog clock divider selection (for clock ck_icn_p_adf1)" newline bitfld.long 0x0 4.--6. "ADC12SEL,Source selection for the ADC12 kernel clock" "0: hclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,7: timg_ck selected as reference clock" newline bitfld.long 0x0 0.--2. "ADF1SEL,Source selection for the ADF1 kernel clock" "0: hclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,7: timg_ck selected as reference clock" line.long 0x4 "RCC_CCIPR2,RCC clock configuration for independent peripheral register 2" bitfld.long 0x4 24. "ETH1GTXCLKSEL,Set and reset by software." "0: MII,1: RGMII" newline bitfld.long 0x4 20. "ETH1REFCLKSEL,Set and reset by software" "0,1" newline bitfld.long 0x4 16.--18. "ETH1SEL,Set and reset by software" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--13. "ETH1CLKSEL,Source selection for the ETH1 kernel clock" "0: hclke selected as reference clock,1: per_ck selected as reference clock,2: ic12_ck selected as reference clock,3: hse_ck selected as reference clock" newline rbitfld.long 0x4 8. "ETH1PWRDOWNACK,Set and reset by software." "0: Power-down sequence start not yet acknowledged.,1: Power-down sequence start acknowledged" newline hexmask.long.byte 0x4 4.--7. 1. "ETH1PTPDIV,ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp)" newline bitfld.long 0x4 0.--1. "ETH1PTPSEL,Source selection for the ETH1 kernel clock" "0: hclke selected as reference clock,1: per_ck selected as reference clock,2: ic13_ck selected as reference clock,3: hse_ck selected as reference clock" line.long 0x8 "RCC_CCIPR3,RCC clock configuration for independent peripheral register3" bitfld.long 0x8 8. "DFTSEL,Source selection for the DFT kernel clock" "0: jtag_tck selected as reference clock (default..,1: pclk3 selected as reference clock" newline bitfld.long 0x8 4.--5. "FMCSEL,Source selection for the FMC kernel clock" "0: hclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic3_ck selected as reference clock,3: ic4_ck selected as reference clock" newline bitfld.long 0x8 0.--1. "FDCANSEL,Source selection for the FDCAN kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic19_ck selected as reference clock,3: hse_ck selected as reference clock" line.long 0xC "RCC_CCIPR4,RCC clock configuration for independent peripheral register4" bitfld.long 0xC 24.--25. "LTDCSEL,Source selection for the LTDC kernel clock" "0: pclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic16_ck selected as reference clock,3: hsi_div_ck selected as reference clock" newline bitfld.long 0xC 20.--22. "I3C2SEL,Source selection for the I3C2 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" newline bitfld.long 0xC 16.--18. "I3C1SEL,Source selection for the I3C1 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" newline bitfld.long 0xC 12.--14. "I2C4SEL,Source selection for the I2C4 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" newline bitfld.long 0xC 8.--10. "I2C3SEL,Source selection for the I2C3 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" newline bitfld.long 0xC 4.--6. "I2C2SEL,Source selection for the I2C2 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" newline bitfld.long 0xC 0.--2. "I2C1SEL,Source selection for the I2C1 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic10_ck selected as reference clock,3: ic15_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,?,?" line.long 0x10 "RCC_CCIPR5,RCC lock configuration for independent peripheral register5" bitfld.long 0x10 16.--18. "MDF1SEL,Source selection for the MDF1 kernel clock" "0: hclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,7: timg_ck selected as reference clock" newline hexmask.long.byte 0x10 12.--15. 1. "MCO2PRE,MCO2 Prog clock divider selection (for clock ck_icn_p_mce4)" newline bitfld.long 0x10 8.--10. "MCO2SEL,Source selection for the MCO2 kernel clock" "0: hsi_div_ck selected as reference clock (default..,1: lse_ck selected as reference clock,2: msi_ck selected as reference clock,3: lsi_ck selected as reference clock,4: hse_ck selected as reference clock,5: ic15_ck selected as reference clock,6: ic20_ck selected as reference clock,7: sysb_ck selected as reference clock" newline hexmask.long.byte 0x10 4.--7. 1. "MCO1PRE,MCO1 Prog clock divider selection (for clock ck_icn_p_mce3)" newline bitfld.long 0x10 0.--2. "MCO1SEL,Source selection for the MCO1 kernel clock" "0: hsi_div_ck selected as reference clock (default..,1: lse_ck selected as reference clock,2: msi_ck selected as reference clock,3: lsi_ck selected as reference clock,4: hse_ck selected as reference clock,5: ic5_ck selected as reference clock,6: ic10_ck selected as reference clock,7: sysa_ck selected as reference clock" line.long 0x14 "RCC_CCIPR6,RCC clock configuration for independent peripheral register6" bitfld.long 0x14 24. "OTGPHY2CKREFSEL,Set and reset by software" "0,1" newline bitfld.long 0x14 20.--21. "OTGPHY2SEL,Source selection for the OTGPHY2 kernel clock" "0: hse_ck selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: hse_div2_osc_ck selected as reference clock" newline bitfld.long 0x14 16. "OTGPHY1CKREFSEL,Set and reset by software" "0,1" newline bitfld.long 0x14 12.--13. "OTGPHY1SEL,Source selection for the OTGPHY1 kernel clock" "0: hse_ck selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: hse_div2_osc_ck selected as reference clock" newline bitfld.long 0x14 8.--9. "XSPI3SEL,Source selection for the XSPI3 kernel clock" "0: hclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic3_ck selected as reference clock,3: ic4_ck selected as reference clock" newline bitfld.long 0x14 4.--5. "XSPI2SEL,Source selection for the XSPI2 kernel clock" "0: hclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic3_ck selected as reference clock,3: ic4_ck selected as reference clock" newline bitfld.long 0x14 0.--1. "XSPI1SEL,Source selection for the XSPI1 kernel clock" "0: hclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic3_ck selected as reference clock,3: ic4_ck selected as reference clock" line.long 0x18 "RCC_CCIPR7,RCC clock configuration for independent peripheral register7" bitfld.long 0x18 24.--26. "SAI2SEL,Source selection for the SAI2 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,7: spdif_symb_ck selected as reference clock" newline bitfld.long 0x18 20.--22. "SAI1SEL,Source selection for the SAI1 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,7: spdif_symb_ck selected as reference clock" newline hexmask.long.byte 0x18 12.--17. 1. "RTCPRE,RTC Prog clock divider selection (for clock ck_icn_p_risaf)" newline bitfld.long 0x18 8.--9. "RTCSEL,Source selection for the RTC kernel clock" "?,1: lse_ck selected as reference clock,2: lsi_ck selected as reference clock,3: hse_rtc_ck selected as reference clock" newline bitfld.long 0x18 4.--5. "PSSISEL,Source selection for the PSSI kernel clock" "0: hclk5 selected as reference clock,1: per_ck selected as reference clock,2: ic20_ck selected as reference clock,3: hsi_div_ck selected as reference clock" newline bitfld.long 0x18 0.--2. "PERSEL,Source selection for the PER kernel clock" "0: hsi_ck selected as reference clock,1: msi_ck selected as reference clock,2: hse_ck selected as reference clock,3: ic19_ck selected as reference clock,4: ic5_ck selected as reference clock,5: ic10_ck selected as reference clock,6: ic15_ck selected as reference clock,7: ic20_ck selected as reference clock" line.long 0x1C "RCC_CCIPR8,RCC clock configuration for independent peripheral register8" bitfld.long 0x1C 4.--5. "SDMMC2SEL,Source selection for the SDMMC2 kernel clock" "0: hclku selected as reference clock,1: per_ck selected as reference clock,2: ic4_ck selected as reference clock,3: ic5_ck selected as reference clock" newline bitfld.long 0x1C 0.--1. "SDMMC1SEL,Source selection for the SDMMC1 kernel clock" "0: hclku selected as reference clock,1: per_ck selected as reference clock,2: ic4_ck selected as reference clock,3: ic5_ck selected as reference clock" line.long 0x20 "RCC_CCIPR9,RCC clock configuration for independent peripheral register9" bitfld.long 0x20 24.--26. "SPI6SEL,Source selection for the SPI6 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic8_ck selected as reference clock,3: ic9_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,?" newline bitfld.long 0x20 20.--22. "SPI5SEL,Source selection for the SPI5 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: hse_ck selected as reference clock,?" newline bitfld.long 0x20 16.--18. "SPI4SEL,Source selection for the SPI4 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: hse_ck selected as reference clock,?" newline bitfld.long 0x20 12.--14. "SPI3SEL,Source selection for the SPI3 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic8_ck selected as reference clock,3: ic9_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,?" newline bitfld.long 0x20 8.--10. "SPI2SEL,Source selection for the SPI2 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic8_ck selected as reference clock,3: ic9_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,?" newline bitfld.long 0x20 4.--6. "SPI1SEL,Source selection for the SPI1 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic8_ck selected as reference clock,3: ic9_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,?" newline bitfld.long 0x20 0.--2. "SPDIFRX1SEL,Source selection for the SPDIFRX1 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic7_ck selected as reference clock,3: ic8_ck selected as reference clock,4: msi_ck selected as reference clock,5: hsi_div_ck selected as reference clock,6: I2S_CKIN selected as reference clock,?" group.long 0x170++0xB line.long 0x0 "RCC_CCIPR12,RCC clock configuration for independent peripheral register12" bitfld.long 0x0 24.--26. "LPTIM5SEL,Source selection for the LPTIM5 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: lse_ck selected as reference clock,4: lsi_ck selected as reference clock,5: timg_ck selected as reference clock,?,?" newline bitfld.long 0x0 20.--22. "LPTIM4SEL,Source selection for the LPTIM4 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: lse_ck selected as reference clock,4: lsi_ck selected as reference clock,5: timg_ck selected as reference clock,?,?" newline bitfld.long 0x0 16.--18. "LPTIM3SEL,Source selection for the LPTIM3 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: lse_ck selected as reference clock,4: lsi_ck selected as reference clock,5: timg_ck selected as reference clock,?,?" newline bitfld.long 0x0 12.--14. "LPTIM2SEL,Source selection for the LPTIM2 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: lse_ck selected as reference clock,4: lsi_ck selected as reference clock,5: timg_ck selected as reference clock,?,?" newline bitfld.long 0x0 8.--10. "LPTIM1SEL,Source selection for the LPTIM1 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic15_ck selected as reference clock,3: lse_ck selected as reference clock,4: lsi_ck selected as reference clock,5: timg_ck selected as reference clock,?,?" line.long 0x4 "RCC_CCIPR13,RCC clock configuration for independent peripheral register13" bitfld.long 0x4 28.--30. "UART8SEL,Source selection for the UART8 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 24.--26. "UART7SEL,Source selection for the UART7 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 20.--22. "USART6SEL,Source selection for the USART6 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 16.--18. "UART5SEL,Source selection for the UART5 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 12.--14. "UART4SEL,Source selection for the UART4 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 8.--10. "USART3SEL,Source selection for the USART3 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 4.--6. "USART2SEL,Source selection for the USART2 kernel clock" "0: pclk1 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x4 0.--2. "USART1SEL,Source selection for the USART1 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" line.long 0x8 "RCC_CCIPR14,RCC clock configuration for independent peripheral register14" bitfld.long 0x8 8.--10. "LPUART1SEL,Source selection for the LPUART1 kernel clock" "0: pclk4 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x8 4.--6. "USART10SEL,Source selection for the USART10 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" newline bitfld.long 0x8 0.--2. "UART9SEL,Source selection for the UART9 kernel clock" "0: pclk2 selected as reference clock,1: per_ck selected as reference clock,2: ic9_ck selected as reference clock,3: ic14_ck selected as reference clock,4: lse_ck selected as reference clock,5: msi_ck selected as reference clock,6: hsi_div_ck selected as reference clock,?" group.long 0x204++0x2B line.long 0x0 "RCC_BUSRSTR,RCC SoC buses reset register" bitfld.long 0x0 13. "NOCRST,NOC reset" "0: NOC is not under reset (default after reset),1: NOC is under reset" newline bitfld.long 0x0 12. "APB5RST,APB5 reset" "0: APB5 is not under reset (default after reset),1: APB5 is under reset" newline bitfld.long 0x0 11. "APB4RST,APB4 reset" "0: APB4 is not under reset (default after reset),1: APB4 is under reset" newline bitfld.long 0x0 10. "APB3RST,APB3 reset" "0: APB3 is not under reset (default after reset),1: APB3 is under reset" newline bitfld.long 0x0 9. "APB2RST,APB2 reset" "0: APB2 is not under reset (default after reset),1: APB2 is under reset" newline bitfld.long 0x0 8. "APB1RST,APB1 reset" "0: APB1 is not under reset (default after reset),1: APB1 is under reset" newline bitfld.long 0x0 7. "AHB5RST,AHB5 reset" "0: AHB5 is not under reset (default after reset),1: AHB5 is under reset" newline bitfld.long 0x0 6. "AHB4RST,AHB4 reset" "0: AHB4 is not under reset (default after reset),1: AHB4 is under reset" newline bitfld.long 0x0 5. "AHB3RST,AHB3 reset" "0: AHB3 is not under reset (default after reset),1: AHB3 is under reset" newline bitfld.long 0x0 4. "AHB2RST,AHB2 reset" "0: AHB2 is not under reset (default after reset),1: AHB2 is under reset" newline bitfld.long 0x0 3. "AHB1RST,AHB1 reset" "0: AHB1 is not under reset (default after reset),1: AHB1 is under reset" newline bitfld.long 0x0 2. "AHBMRST,AHBM reset" "0: AHBM is not under reset (default after reset),1: AHBM is under reset" newline bitfld.long 0x0 0. "ACLKNRST,ACLKN reset" "0: ACLKN is not under reset (default after reset),1: ACLKN is under reset" line.long 0x4 "RCC_MISCRSTR,RCC miscellaneous configurations reset register" bitfld.long 0x4 8. "SDMMC2DLLRST,SDMMC2DLL reset" "0: SDMMC2DLL is not under reset (default after reset),1: SDMMC2DLL is under reset" newline bitfld.long 0x4 7. "SDMMC1DLLRST,SDMMC1DLL reset" "0: SDMMC1DLL is not under reset (default after reset),1: SDMMC1DLL is under reset" newline bitfld.long 0x4 5. "XSPIPHY2RST,XSPIPHY2 reset" "0: XSPIPHY2 is not under reset (default after reset),1: XSPIPHY2 is under reset" newline bitfld.long 0x4 4. "XSPIPHY1RST,XSPIPHY1 reset" "0: XSPIPHY1 is not under reset (default after reset),1: XSPIPHY1 is under reset" newline bitfld.long 0x4 0. "DBGRST,DBG reset" "0: DBG is not under reset (default after reset),1: DBG is under reset" line.long 0x8 "RCC_MEMRSTR,RCC memories reset register" bitfld.long 0x8 12. "BOOTROMRST,BOOTROM reset" "0: BOOTROM is not under reset (default after reset),1: BOOTROM is under reset" newline bitfld.long 0x8 11. "VENCRAMRST,VENCRAM reset" "0: VENCRAM is not under reset (default after reset),1: VENCRAM is under reset" newline bitfld.long 0x8 10. "NPUCACHERAMRST,NPUCACHERAM reset" "0: NPUCACHERAM is not under reset (default after..,1: NPUCACHERAM is under reset" newline bitfld.long 0x8 9. "FLEXRAMRST,FLEXRAM reset" "0: FLEXRAM is not under reset (default after reset),1: FLEXRAM is under reset" newline bitfld.long 0x8 8. "AXISRAM2RST,AXISRAM2 reset" "0: AXISRAM2 is not under reset (default after reset),1: AXISRAM2 is under reset" newline bitfld.long 0x8 7. "AXISRAM1RST,AXISRAM1 reset" "0: AXISRAM1 is not under reset (default after reset),1: AXISRAM1 is under reset" newline bitfld.long 0x8 5. "AHBSRAM2RST,AHBSRAM2 reset" "0: AHBSRAM2 is not under reset (default after reset),1: AHBSRAM2 is under reset" newline bitfld.long 0x8 4. "AHBSRAM1RST,AHBSRAM1 reset" "0: AHBSRAM1 is not under reset (default after reset),1: AHBSRAM1 is under reset" newline bitfld.long 0x8 3. "AXISRAM6RST,AXISRAM6 reset" "0: AXISRAM6 is not under reset (default after reset),1: AXISRAM6 is under reset" newline bitfld.long 0x8 2. "AXISRAM5RST,AXISRAM5 reset" "0: AXISRAM5 is not under reset (default after reset),1: AXISRAM5 is under reset" newline bitfld.long 0x8 1. "AXISRAM4RST,AXISRAM4reset" "0: AXISRAM4 is not under reset (default after reset),1: AXISRAM4 is under reset" newline bitfld.long 0x8 0. "AXISRAM3RST,AXISRAM3 reset" "0: AXISRAM3 is not under reset (default after reset),1: AXISRAM3 is under reset" line.long 0xC "RCC_AHB1RSTR,RCC AHB1 Reset register" bitfld.long 0xC 5. "ADC12RST,ADC12 reset" "0: ADC12 is not under reset (default after reset),1: ADC12 is under reset" newline bitfld.long 0xC 4. "GPDMA1RST,GPDMA1 reset" "0: GPDMA1 is not under reset (default after reset),1: GPDMA1 is under reset" line.long 0x10 "RCC_AHB2RSTR,RCC AHB2 reset register" bitfld.long 0x10 17. "ADF1RST,ADF1 reset" "0: ADF1 is not under reset (default after reset),1: ADF1 is under reset" newline bitfld.long 0x10 16. "MDF1RST,MDF1 reset" "0: MDF1 is not under reset (default after reset),1: MDF1 is under reset" newline bitfld.long 0x10 12. "RAMCFGRST,RAMCFG reset" "0: RAMCFG is not under reset (default after reset),1: RAMCFG is under reset" line.long 0x14 "RCC_AHB3RSTR,RCC AHB3 reset register" bitfld.long 0x14 10. "IACRST,IAC reset" "0: IAC is not under reset (default after reset),1: IAC is under reset" newline bitfld.long 0x14 8. "PKARST,PKA reset" "0: PKA is not under reset (default after reset),1: PKA is under reset" newline bitfld.long 0x14 4. "SAESRST,SAES reset" "0: SAES is not under reset (default after reset),1: SAES is under reset" newline bitfld.long 0x14 2. "CRYPRST,CRYP reset" "0: CRYP is not under reset (default after reset),1: CRYP is under reset" newline bitfld.long 0x14 1. "HASHRST,HASH reset" "0: HASH is not under reset (default after reset),1: HASH is under reset" newline bitfld.long 0x14 0. "RNGRST,RNG reset" "0: RNG is not under reset (default after reset),1: RNG is under reset" line.long 0x18 "RCC_AHB4RSTR,RCC AHB4 reset register" bitfld.long 0x18 19. "CRCRST,CRC reset" "0: CRC is not under reset (default after reset),1: CRC is under reset" newline bitfld.long 0x18 18. "PWRRST,PWR reset" "0: PWR is not under reset (default after reset),1: PWR is under reset" newline bitfld.long 0x18 16. "GPIOQRST,GPIOQ reset" "0: GPIOQ is not under reset (default after reset),1: GPIOQ is under reset" newline bitfld.long 0x18 15. "GPIOPRST,GPIOP reset" "0: GPIOP is not under reset (default after reset),1: GPIOP is under reset" newline bitfld.long 0x18 14. "GPIOORST,GPIOO reset" "0: GPIOO is not under reset (default after reset),1: GPIOO is under reset" newline bitfld.long 0x18 13. "GPIONRST,GPION reset" "0: GPION is not under reset (default after reset),1: GPION is under reset" newline bitfld.long 0x18 7. "GPIOHRST,GPIOH reset" "0: GPIOH is not under reset (default after reset),1: GPIOH is under reset" newline bitfld.long 0x18 6. "GPIOGRST,GPIOG reset" "0: GPIOG is not under reset (default after reset),1: GPIOG is under reset" newline bitfld.long 0x18 5. "GPIOFRST,GPIOF reset" "0: GPIOF is not under reset (default after reset),1: GPIOF is under reset" newline bitfld.long 0x18 4. "GPIOERST,GPIOE reset" "0: GPIOE is not under reset (default after reset),1: GPIOE is under reset" newline bitfld.long 0x18 3. "GPIODRST,GPIOD reset" "0: GPIOD is not under reset (default after reset),1: GPIOD is under reset" newline bitfld.long 0x18 2. "GPIOCRST,GPIOC reset" "0: GPIOC is not under reset (default after reset),1: GPIOC is under reset" newline bitfld.long 0x18 1. "GPIOBRST,GPIOB reset" "0: GPIOB is not under reset (default after reset),1: GPIOB is under reset" newline bitfld.long 0x18 0. "GPIOARST,GPIOA reset" "0: GPIOA is not under reset (default after reset),1: GPIOA is under reset" line.long 0x1C "RCC_AHB5RSTR,RCC AHB5 reset register" bitfld.long 0x1C 31. "NPURST,NPU reset" "0: NPU is not under reset (default after reset),1: NPU is under reset" newline bitfld.long 0x1C 30. "NPUCACHERST,NPUCACHE reset" "0: NPUCACHE is not under reset (default after reset),1: NPUCACHE is under reset" newline bitfld.long 0x1C 29. "OTG2RST,OTG2 reset" "0: OTG2 is not under reset (default after reset),1: OTG2 is under reset" newline bitfld.long 0x1C 28. "OTGPHY2RST,OTGPHY2 reset" "0: OTGPHY2 is not under reset (default after reset),1: OTGPHY2 is under reset" newline bitfld.long 0x1C 27. "OTGPHY1RST,OTGPHY1 reset" "0: OTGPHY1 is not under reset (default after reset),1: OTGPHY1 is under reset" newline bitfld.long 0x1C 26. "OTG1RST,OTG1 reset" "0: OTG1 is not under reset (default after reset),1: OTG1 is under reset" newline bitfld.long 0x1C 25. "ETH1RST,ETH1 reset" "0: ETH1 is not under reset (default after reset),1: ETH1 is under reset" newline bitfld.long 0x1C 24. "SYSCFGOTGHSPHY2RST,SYSCFGOTGHSPHY2 reset" "0: SYSCFGOTGHSPHY2 is not under reset (default..,1: SYSCFGOTGHSPHY2 is under reset" newline bitfld.long 0x1C 23. "SYSCFGOTGHSPHY1RST,SYSCFGOTGHSPHY1 reset" "0: SYSCFGOTGHSPHY1 is not under reset (default..,1: SYSCFGOTGHSPHY1 is under reset" newline bitfld.long 0x1C 20. "GPURST,GPU reset" "0: GPU is not under reset (default after reset),1: GPU is under reset" newline bitfld.long 0x1C 19. "GFXMMURST,GFXMMU reset" "0: GFXMMU is not under reset (default after reset),1: GFXMMU is under reset" newline bitfld.long 0x1C 18. "MCE4RST,MCE4 reset" "0: MCE4 is not under reset (default after reset),1: MCE4 is under reset" newline bitfld.long 0x1C 17. "XSPI3RST,XSPI3 reset" "0: XSPI3 is not under reset (default after reset),1: XSPI3 is under reset" newline bitfld.long 0x1C 13. "XSPIMRST,XSPIM reset" "0: XSPIM is not under reset (default after reset),1: XSPIM is under reset" newline bitfld.long 0x1C 12. "XSPI2RST,XSPI2 reset" "0: XSPI2 is not under reset (default after reset),1: XSPI2 is under reset" newline bitfld.long 0x1C 8. "SDMMC1RST,SDMMC1 reset" "0: SDMMC1 is not under reset (default after reset),1: SDMMC1 is under reset" newline bitfld.long 0x1C 7. "SDMMC2RST,SDMMC2 reset" "0: SDMMC2 is not under reset (default after reset),1: SDMMC2 is under reset" newline bitfld.long 0x1C 6. "PSSIRST,PSSI reset" "0: PSSI is not under reset (default after reset),1: PSSI is under reset" newline bitfld.long 0x1C 5. "XSPI1RST,XSPI1 reset" "0: XSPI1 is not under reset (default after reset),1: XSPI1 is under reset" newline bitfld.long 0x1C 4. "FMCRST,FMC reset" "0: FMC is not under reset (default after reset),1: FMC is under reset" newline bitfld.long 0x1C 3. "JPEGRST,JPEG reset" "0: JPEG is not under reset (default after reset),1: JPEG is under reset" newline bitfld.long 0x1C 1. "DMA2DRST,DMA2D reset" "0: DMA2D is not under reset (default after reset),1: DMA2D is under reset" newline bitfld.long 0x1C 0. "HPDMA1RST,HPDMA1 reset" "0: HPDMA1 is not under reset (default after reset),1: HPDMA1 is under reset" line.long 0x20 "RCC_APB1LRSTR,RCC APB1L reset register" bitfld.long 0x20 31. "UART8RST,UART8 reset" "0: UART8 is not under reset (default after reset),1: UART8 is under reset" newline bitfld.long 0x20 30. "UART7RST,UART7 reset" "0: UART7 is not under reset (default after reset),1: UART7 is under reset" newline bitfld.long 0x20 25. "I3C2RST,I3C2 reset" "0: I3C2 is not under reset (default after reset),1: I3C2 is under reset" newline bitfld.long 0x20 24. "I3C1RST,I3C1 reset" "0: I3C1 is not under reset (default after reset),1: I3C1 is under reset" newline bitfld.long 0x20 23. "I2C3RST,I2C3 reset" "0: I2C3 is not under reset (default after reset),1: I2C3 is under reset" newline bitfld.long 0x20 22. "I2C2RST,I2C2 reset" "0: I2C2 is not under reset (default after reset),1: I2C2 is under reset" newline bitfld.long 0x20 21. "I2C1RST,I2C1 reset" "0: I2C1 is not under reset (default after reset),1: I2C1 is under reset" newline bitfld.long 0x20 20. "UART5RST,UART5 reset" "0: UART5 is not under reset (default after reset),1: UART5 is under reset" newline bitfld.long 0x20 19. "UART4RST,UART4 reset" "0: UART4 is not under reset (default after reset),1: UART4 is under reset" newline bitfld.long 0x20 18. "USART3RST,USART3 reset" "0: USART3 is not under reset (default after reset),1: USART3 is under reset" newline bitfld.long 0x20 17. "USART2RST,USART2 reset" "0: USART2 is not under reset (default after reset),1: USART2 is under reset" newline bitfld.long 0x20 16. "SPDIFRX1RST,SPDIFRX1 reset" "0: SPDIFRX1 is not under reset (default after reset),1: SPDIFRX1 is under reset" newline bitfld.long 0x20 15. "SPI3RST,SPI3 reset" "0: SPI3 is not under reset (default after reset),1: SPI3 is under reset" newline bitfld.long 0x20 14. "SPI2RST,SPI2 reset" "0: SPI2 is not under reset (default after reset),1: SPI2 is under reset" newline bitfld.long 0x20 13. "TIM11RST,TIM11 reset" "0: TIM11 is not under reset (default after reset),1: TIM11 is under reset" newline bitfld.long 0x20 12. "TIM10RST,TIM10 reset" "0: TIM10 is not under reset (default after reset),1: TIM10 is under reset" newline bitfld.long 0x20 11. "WWDGRST,WWDG reset" "0: WWDG is not under reset (default after reset),1: WWDG is under reset" newline bitfld.long 0x20 9. "LPTIM1RST,LPTIM1 reset" "0: LPTIM1 is not under reset (default after reset),1: LPTIM1 is under reset" newline bitfld.long 0x20 8. "TIM14RST,TIM14 reset" "0: TIM14 is not under reset (default after reset),1: TIM14 is under reset" newline bitfld.long 0x20 7. "TIM13RST,TIM13 reset" "0: TIM13 is not under reset (default after reset),1: TIM13 is under reset" newline bitfld.long 0x20 6. "TIM12RST,TIM12 reset" "0: TIM12 is not under reset (default after reset),1: TIM12 is under reset" newline bitfld.long 0x20 5. "TIM7RST,TIM7 reset" "0: TIM7 is not under reset (default after reset),1: TIM7 is under reset" newline bitfld.long 0x20 4. "TIM6RST,TIM6 reset" "0: TIM6 is not under reset (default after reset),1: TIM6 is under reset" newline bitfld.long 0x20 3. "TIM5RST,TIM5 reset" "0: TIM5 is not under reset (default after reset),1: TIM5 is under reset" newline bitfld.long 0x20 2. "TIM4RST,TIM4 reset" "0: TIM4 is not under reset (default after reset),1: TIM4 is under reset" newline bitfld.long 0x20 1. "TIM3RST,TIM3 reset" "0: TIM3 is not under reset (default after reset),1: TIM3 is under reset" newline bitfld.long 0x20 0. "TIM2RST,TIM2 reset" "0: TIM2 is not under reset (default after reset),1: TIM2 is under reset" line.long 0x24 "RCC_APB1HRSTR,RCC APB1H reset register" bitfld.long 0x24 18. "UCPD1RST,UCPD1 reset" "0: UCPD1 is not under reset (default after reset),1: UCPD1 is under reset" newline bitfld.long 0x24 8. "FDCANRST,FDCAN reset" "0: FDCAN is not under reset (default after reset),1: FDCAN is under reset" newline bitfld.long 0x24 5. "MDIOSRST,MDIOS reset" "0: MDIOS is not under reset (default after reset),1: MDIOS is under reset" line.long 0x28 "RCC_APB2RSTR,RCC APB2 reset register" bitfld.long 0x28 22. "SAI2RST,SAI2 reset" "0: SAI2 is not under reset (default after reset),1: SAI2 is under reset" newline bitfld.long 0x28 21. "SAI1RST,SAI1 reset" "0: SAI1 is not under reset (default after reset),1: SAI1 is under reset" newline bitfld.long 0x28 20. "SPI5RST,SPI5 reset" "0: SPI5 is not under reset (default after reset),1: SPI5 is under reset" newline bitfld.long 0x28 19. "TIM9RST,TIM9 reset" "0: TIM9 is not under reset (default after reset),1: TIM9 is under reset" newline bitfld.long 0x28 18. "TIM17RST,TIM17 reset" "0: TIM17 is not under reset (default after reset),1: TIM17 is under reset" newline bitfld.long 0x28 17. "TIM16RST,TIM16 reset" "0: TIM16 is not under reset (default after reset),1: TIM16 is under reset" newline bitfld.long 0x28 16. "TIM15RST,TIM15 reset" "0: TIM15 is not under reset (default after reset),1: TIM15 is under reset" newline bitfld.long 0x28 15. "TIM18RST,TIM18 reset" "0: TIM18 is not under reset (default after reset),1: TIM18 is under reset" newline bitfld.long 0x28 13. "SPI4RST,SPI4 reset" "0: SPI4 is not under reset (default after reset),1: SPI4 is under reset" newline bitfld.long 0x28 12. "SPI1RST,SPI1 reset" "0: SPI1 is not under reset (default after reset),1: SPI1 is under reset" newline bitfld.long 0x28 7. "USART10RST,USART10 reset" "0: USART10 is not under reset (default after reset),1: USART10 is under reset" newline bitfld.long 0x28 6. "UART9RST,UART9 reset" "0: UART9 is not under reset (default after reset),1: UART9 is under reset" newline bitfld.long 0x28 5. "USART6RST,USART6 reset" "0: USART6 is not under reset (default after reset),1: USART6 is under reset" newline bitfld.long 0x28 4. "USART1RST,USART1 reset" "0: USART1 is not under reset (default after reset),1: USART1 is under reset" newline bitfld.long 0x28 1. "TIM8RST,TIM8 reset" "0: TIM8 is not under reset (default after reset),1: TIM8 is under reset" newline bitfld.long 0x28 0. "TIM1RST,TIM1 reset" "0: TIM1 is not under reset (default after reset),1: TIM1 is under reset" group.long 0x234++0x8B line.long 0x0 "RCC_APB4LRSTR,RCC APB4L reset register" bitfld.long 0x0 31. "SERFRST,SERF reset" "0: SERF is not under reset (default after reset),1: SERF is under reset" newline bitfld.long 0x0 23. "R2GNPURST,R2GNPU reset" "0: R2GNPU is not under reset (default after reset),1: R2GNPU is under reset" newline bitfld.long 0x0 22. "R2GRETRST,R2GRET reset" "0: R2GRET is not under reset (default after reset),1: R2GRET is under reset" newline bitfld.long 0x0 16. "RTCRST,RTC reset" "0: RTC is not under reset (default after reset),1: RTC is under reset" newline bitfld.long 0x0 15. "VREFBUFRST,VREFBUF reset" "0: VREFBUF is not under reset (default after reset),1: VREFBUF is under reset" newline bitfld.long 0x0 12. "LPTIM5RST,LPTIM5 reset" "0: LPTIM5 is not under reset (default after reset),1: LPTIM5 is under reset" newline bitfld.long 0x0 11. "LPTIM4RST,LPTIM4 reset" "0: LPTIM4 is not under reset (default after reset),1: LPTIM4 is under reset" newline bitfld.long 0x0 10. "LPTIM3RST,LPTIM3 reset" "0: LPTIM3 is not under reset (default after reset),1: LPTIM3 is under reset" newline bitfld.long 0x0 9. "LPTIM2RST,LPTIM2 reset" "0: LPTIM2 is not under reset (default after reset),1: LPTIM2 is under reset" newline bitfld.long 0x0 7. "I2C4RST,I2C4 reset" "0: I2C4 is not under reset (default after reset),1: I2C4 is under reset" newline bitfld.long 0x0 5. "SPI6RST,SPI6 reset" "0: SPI6 is not under reset (default after reset),1: SPI6 is under reset" newline bitfld.long 0x0 3. "LPUART1RST,LPUART1 reset" "0: LPUART1 is not under reset (default after reset),1: LPUART1 is under reset" newline bitfld.long 0x0 2. "HDPRST,HDP reset" "0: HDP is not under reset (default after reset),1: HDP is under reset" line.long 0x4 "RCC_APB4HRSTR,RCC APB4H reset register" bitfld.long 0x4 4. "BUSPERFMRST,BUSPERFM reset" "0: BUSPERFM is not under reset (default after reset),1: BUSPERFM is under reset" newline bitfld.long 0x4 2. "DTSRST,DTS reset" "0: DTS is not under reset (default after reset),1: DTS is under reset" newline bitfld.long 0x4 0. "SYSCFGRST,SYSCFG reset" "0: SYSCFG is not under reset (default after reset),1: SYSCFG is under reset" line.long 0x8 "RCC_APB5RSTR,RCC APB5 reset register" bitfld.long 0x8 6. "CSIRST,CSI reset" "0: CSI is not under reset (default after reset),1: CSI is under reset" newline bitfld.long 0x8 5. "VENCRST,VENC reset" "0: VENC is not under reset (default after reset),1: VENC is under reset" newline bitfld.long 0x8 4. "GFXTIMRST,GFXTIM reset" "0: GFXTIM is not under reset (default after reset),1: GFXTIM is under reset" newline bitfld.long 0x8 2. "DCMIPPRST,DCMIPP reset" "0: DCMIPP is not under reset (default after reset),1: DCMIPP is under reset" newline bitfld.long 0x8 1. "LTDCRST,LTDC reset" "0: LTDC is not under reset (default after reset),1: LTDC is under reset" line.long 0xC "RCC_DIVENR,RCC IC dividers enable register" bitfld.long 0xC 19. "IC20EN,IC20 enable" "0: IC20 is disabled (default after reset),1: IC20 is enabled" newline bitfld.long 0xC 18. "IC19EN,IC19 enable" "0: IC19 is disabled (default after reset),1: IC19 is enabled" newline bitfld.long 0xC 17. "IC18EN,IC18 enable" "0: IC18 is disabled (default after reset),1: IC18 is enabled" newline bitfld.long 0xC 16. "IC17EN,IC17 enable" "0: IC17 is disabled (default after reset),1: IC17 is enabled" newline bitfld.long 0xC 15. "IC16EN,IC16 enable" "0: IC16 is disabled (default after reset),1: IC16 is enabled" newline bitfld.long 0xC 14. "IC15EN,IC15 enable" "0: IC15 is disabled (default after reset),1: IC15 is enabled" newline bitfld.long 0xC 13. "IC14EN,IC14 enable" "0: IC14 is disabled (default after reset),1: IC14 is enabled" newline bitfld.long 0xC 12. "IC13EN,IC13 enable" "0: IC13 is disabled (default after reset),1: IC13 is enabled" newline bitfld.long 0xC 11. "IC12EN,IC12 enable" "0: IC12 is disabled (default after reset),1: IC12 is enabled" newline bitfld.long 0xC 10. "IC11EN,IC11 enable" "0: IC11 is disabled (default after reset),1: IC11 is enabled" newline bitfld.long 0xC 9. "IC10EN,IC10 enable" "0: IC10 is disabled (default after reset),1: IC10 is enabled" newline bitfld.long 0xC 8. "IC9EN,IC9 enable" "0: IC9 is disabled (default after reset),1: IC9 is enabled" newline bitfld.long 0xC 7. "IC8EN,IC8 enable" "0: IC8 is disabled (default after reset),1: IC8 is enabled" newline bitfld.long 0xC 6. "IC7EN,IC7 enable" "0: IC7 is disabled (default after reset),1: IC7 is enabled" newline bitfld.long 0xC 5. "IC6EN,IC6 enable" "0: IC6 is disabled (default after reset),1: IC6 is enabled" newline bitfld.long 0xC 4. "IC5EN,IC5 enable" "0: IC5 is disabled (default after reset),1: IC5 is enabled" newline bitfld.long 0xC 3. "IC4EN,IC4 enable" "0: IC4 is disabled (default after reset),1: IC4 is enabled" newline bitfld.long 0xC 2. "IC3EN,IC3 enable" "0: IC3 is disabled (default after reset),1: IC3 is enabled" newline bitfld.long 0xC 1. "IC2EN,IC2 enable" "0: IC2 is disabled (default after reset),1: IC2 is enabled" newline bitfld.long 0xC 0. "IC1EN,IC1 enable" "0: IC1 is disabled (default after reset),1: IC1 is enabled" line.long 0x10 "RCC_BUSENR,RCC SoC buses enable register" bitfld.long 0x10 12. "APB5EN,APB5 enable" "0: APB5 is disabled (default after reset),1: APB5 is enabled" newline bitfld.long 0x10 11. "APB4EN,APB4 enable" "0: APB4 is disabled (default after reset),1: APB4 is enabled" newline bitfld.long 0x10 10. "APB3EN,APB3 enable" "0: APB3 is disabled (default after reset),1: APB3 is enabled" newline bitfld.long 0x10 9. "APB2EN,APB2 enable" "0: APB2 is disabled (default after reset),1: APB2 is enabled" newline bitfld.long 0x10 8. "APB1EN,APB1 enable" "0: APB1 is disabled (default after reset),1: APB1 is enabled" newline bitfld.long 0x10 7. "AHB5EN,AHB5 enable" "0: AHB5 is disabled (default after reset),1: AHB5 is enabled" newline bitfld.long 0x10 6. "AHB4EN,AHB4 enable" "0: AHB4 is disabled (default after reset),1: AHB4 is enabled" newline bitfld.long 0x10 5. "AHB3EN,AHB3 enable" "0: AHB3 is disabled (default after reset),1: AHB3 is enabled" newline bitfld.long 0x10 4. "AHB2EN,AHB2 enable" "0: AHB2 is disabled (default after reset),1: AHB2 is enabled" newline bitfld.long 0x10 3. "AHB1EN,AHB1 enable" "0: AHB1 is disabled (default after reset),1: AHB1 is enabled" newline bitfld.long 0x10 2. "AHBMEN,AHBM enable" "0: AHBM is disabled (default after reset),1: AHBM is enabled" newline bitfld.long 0x10 1. "ACLKNCEN,ACLKNC enable" "0: ACLKNC is disabled,1: ACLKNC is enabled (default after reset)" newline bitfld.long 0x10 0. "ACLKNEN,ACLKN enable" "0: ACLKN is disabled,1: ACLKN is enabled (default after reset)" line.long 0x14 "RCC_MISCENR,RCC miscellaneous configuration enable register" bitfld.long 0x14 6. "PEREN,PER enable" "0: PER is disabled (default after reset),1: PER is enabled" newline bitfld.long 0x14 3. "XSPIPHYCOMPEN,XSPIPHYCOMP enable" "0: XSPIPHYCOMP is disabled (default after reset),1: XSPIPHYCOMP is enabled" newline bitfld.long 0x14 2. "MCO2EN,MCO2 enable" "0: MCO2 is disabled (default after reset),1: MCO2 is enabled" newline bitfld.long 0x14 1. "MCO1EN,MCO1 enable" "0: MCO1 is disabled (default after reset),1: MCO1 is enabled" newline bitfld.long 0x14 0. "DBGEN,DBG enable" "0: DBG is disabled (default after reset),1: DBG is enabled" line.long 0x18 "RCC_MEMENR,RCC memory enable register" bitfld.long 0x18 12. "BOOTROMEN,BOOTROM enable" "0: BOOTROM is disabled,1: BOOTROM is enabled (default after reset)" newline bitfld.long 0x18 11. "VENCRAMEN,VENCRAM enable" "0: VENCRAM is disabled (default after reset),1: VENCRAM is enabled" newline bitfld.long 0x18 10. "NPUCACHERAMEN,NPUCACHERAM enable" "0: NPUCACHERAM is disabled (default after reset),1: NPUCACHERAM is enabled" newline bitfld.long 0x18 9. "FLEXRAMEN,FLEXRAM enable" "0: FLEXRAM is disabled,1: FLEXRAM is enabled (default after reset)" newline bitfld.long 0x18 8. "AXISRAM2EN,AXISRAM2 enable" "0: AXISRAM2 is disabled,1: AXISRAM2 is enabled (default after reset)" newline bitfld.long 0x18 7. "AXISRAM1EN,AXISRAM1 enable" "0: AXISRAM1 is disabled,1: AXISRAM1 is enabled (default after reset)" newline bitfld.long 0x18 6. "BKPSRAMEN,BKPSRAM enable" "0: BKPSRAM is disabled,1: BKPSRAM is enabled (default after reset)" newline bitfld.long 0x18 5. "AHBSRAM2EN,AHBSRAM2 enable" "0: AHBSRAM2 is disabled,1: AHBSRAM2 is enabled (default after reset)" newline bitfld.long 0x18 4. "AHBSRAM1EN,AHBSRAM1 enable" "0: AHBSRAM1 is disabled,1: AHBSRAM1 is enabled (default after reset)" newline bitfld.long 0x18 3. "AXISRAM6EN,AXISRAM6 enable" "0: AXISRAM6 is disabled,1: AXISRAM6 is enabled (default after reset)" newline bitfld.long 0x18 2. "AXISRAM5EN,AXISRAM5 enable" "0: AXISRAM5 is disabled,1: AXISRAM5 is enabled (default after reset)" newline bitfld.long 0x18 1. "AXISRAM4EN,AXISRAM4 enable" "0: AXISRAM4 is disabled,1: AXISRAM4 is enabled (default after reset)" newline bitfld.long 0x18 0. "AXISRAM3EN,AXISRAM3 enable" "0: AXISRAM3 is disabled,1: AXISRAM3 is enabled (default after reset)" line.long 0x1C "RCC_AHB1ENR,RCC AHB1 enable register" bitfld.long 0x1C 5. "ADC12EN,ADC12 enable" "0: ADC12 is disabled (default after reset),1: ADC12 is enabled" newline bitfld.long 0x1C 4. "GPDMA1EN,GPDMA1 enable" "0: GPDMA1 is disabled (default after reset),1: GPDMA1 is enabled" line.long 0x20 "RCC_AHB2ENR,RCC AHB2 enable register" bitfld.long 0x20 17. "ADF1EN,ADF enable" "0: ADF is disabled (default after reset),1: ADF is enabled" newline bitfld.long 0x20 16. "MDF1EN,MDF1 enable" "0: MDF1 is disabled (default after reset),1: MDF1 is enabled" newline bitfld.long 0x20 12. "RAMCFGEN,RAMCFG enable" "0: RAMCFG is disabled,1: RAMCFG is enabled (default after reset)" line.long 0x24 "RCC_AHB3ENR,RCC AHB3 enable register" bitfld.long 0x24 14. "RISAFEN,RISAF enable" "0: RISAF is disabled,1: RISAF is enabled (default after reset)" newline bitfld.long 0x24 10. "IACEN,IAC enable" "0: IAC is disabled,1: IAC is enabled (default after reset)" newline bitfld.long 0x24 9. "RIFSCEN,RIFSC enable" "0: RIFSC is disabled,1: RIFSC is enabled (default after reset)" newline bitfld.long 0x24 8. "PKAEN,PKA enable" "0: PKA is disabled (default after reset),1: PKA is enabled" newline bitfld.long 0x24 4. "SAESEN,SAES enable" "0: SAES is disabled (default after reset),1: SAES is enabled" newline bitfld.long 0x24 2. "CRYPEN,CRYP enable" "0: CRYP is disabled (default after reset),1: CRYP is enabled" newline bitfld.long 0x24 1. "HASHEN,HASH enable" "0: HASH is disabled (default after reset),1: HASH is enabled" newline bitfld.long 0x24 0. "RNGEN,RNG enable" "0: RNG is disabled (default after reset),1: RNG is enabled" line.long 0x28 "RCC_AHB4ENR,RCC AHB4 enable register" bitfld.long 0x28 19. "CRCEN,CRC enable" "0: CRC is disabled (default after reset),1: CRC is enabled" newline bitfld.long 0x28 18. "PWREN,PWR enable" "0: PWR is disabled,1: PWR is enabled (default after reset)" newline bitfld.long 0x28 16. "GPIOQEN,GPIOQ enable" "0: GPIOQ is disabled (default after reset),1: GPIOQ is enabled" newline bitfld.long 0x28 15. "GPIOPEN,GPIOP enable" "0: GPIOP is disabled (default after reset),1: GPIOP is enabled" newline bitfld.long 0x28 14. "GPIOOEN,GPIOO enable" "0: GPIOO is disabled (default after reset),1: GPIOO is enabled" newline bitfld.long 0x28 13. "GPIONEN,GPION enable" "0: GPION is disabled (default after reset),1: GPION is enabled" newline bitfld.long 0x28 7. "GPIOHEN,GPIOH enable" "0: GPIOH is disabled (default after reset),1: GPIOH is enabled" newline bitfld.long 0x28 6. "GPIOGEN,GPIOG enable" "0: GPIOG is disabled (default after reset),1: GPIOG is enabled" newline bitfld.long 0x28 5. "GPIOFEN,GPIOF enable" "0: GPIOF is disabled (default after reset),1: GPIOF is enabled" newline bitfld.long 0x28 4. "GPIOEEN,GPIOE enable" "0: GPIOE is disabled (default after reset),1: GPIOE is enabled" newline bitfld.long 0x28 3. "GPIODEN,GPIOD enable" "0: GPIOD is disabled (default after reset),1: GPIOD is enabled" newline bitfld.long 0x28 2. "GPIOCEN,GPIOC enable" "0: GPIOC is disabled (default after reset),1: GPIOC is enabled" newline bitfld.long 0x28 1. "GPIOBEN,GPIOB enable" "0: GPIOB is disabled (default after reset),1: GPIOB is enabled" newline bitfld.long 0x28 0. "GPIOAEN,GPIOA enable" "0: GPIOA is disabled (default after reset),1: GPIOA is enabled" line.long 0x2C "RCC_AHB5ENR,RCC AHB5 enable register" bitfld.long 0x2C 31. "NPUEN,NPU enable" "0: NPU is disabled (default after reset),1: NPU is enabled" newline bitfld.long 0x2C 30. "NPUCACHEEN,NPUCACHE enable" "0: NPUCACHE is disabled (default after reset),1: NPUCACHE is enabled" newline bitfld.long 0x2C 29. "OTG2EN,OTG2 enable" "0: OTG2 is disabled (default after reset),1: OTG2 is enabled" newline bitfld.long 0x2C 28. "OTGPHY2EN,OTGPHY2 enable" "0: OTGPHY2 is disabled (default after reset),1: OTGPHY2 is enabled" newline bitfld.long 0x2C 27. "OTGPHY1EN,OTGPHY1 enable" "0: OTGPHY1 is disabled (default after reset),1: OTGPHY1 is enabled" newline bitfld.long 0x2C 26. "OTG1EN,OTG1 enable" "0: OTG1 is disabled (default after reset),1: OTG1 is enabled" newline bitfld.long 0x2C 25. "ETH1EN,ETH1 enable" "0: ETH1 is disabled (default after reset),1: ETH1 is enabled" newline bitfld.long 0x2C 24. "ETH1RXEN,ETH1RX enable" "0: ETH1RX is disabled (default after reset),1: ETH1RX is enabled" newline bitfld.long 0x2C 23. "ETH1TXEN,ETH1TX enable" "0: ETH1TX is disabled (default after reset),1: ETH1TX is enabled" newline bitfld.long 0x2C 22. "ETH1MACEN,ETH1MAC enable" "0: ETH1MAC is disabled (default after reset),1: ETH1MAC is enabled" newline bitfld.long 0x2C 20. "GPUEN,GPU enable" "0: GPU is disabled (default after reset),1: GPU is enabled" newline bitfld.long 0x2C 19. "GFXMMUEN,GFXMMU enable" "0: GFXMMU is disabled (default after reset),1: GFXMMU is enabled" newline bitfld.long 0x2C 18. "MCE4EN,MCE4 enable" "0: MCE4 is disabled (default after reset),1: MCE4 is enabled" newline bitfld.long 0x2C 17. "XSPI3EN,XSPI3 enable" "0: XSPI3 is disabled (default after reset),1: XSPI3 is enabled" newline bitfld.long 0x2C 16. "MCE3EN,MCE3 enable" "0: MCE3 is disabled (default after reset),1: MCE3 is enabled" newline bitfld.long 0x2C 15. "MCE2EN,MCE2 enable" "0: MCE2 is disabled (default after reset),1: MCE2 is enabled" newline bitfld.long 0x2C 14. "MCE1EN,MCE1 enable" "0: MCE1 is disabled (default after reset),1: MCE1 is enabled" newline bitfld.long 0x2C 13. "XSPIMEN,XSPIM enable" "0: XSPIM is disabled (default after reset),1: XSPIM is enabled" newline bitfld.long 0x2C 12. "XSPI2EN,XSPI2 enable" "0: XSPI2 is disabled (default after reset),1: XSPI2 is enabled" newline bitfld.long 0x2C 8. "SDMMC1EN,SDMMC1 enable" "0: SDMMC1 is disabled (default after reset),1: SDMMC1 is enabled" newline bitfld.long 0x2C 7. "SDMMC2EN,SDMMC2 enable" "0: SDMMC2 is disabled (default after reset),1: SDMMC2 is enabled" newline bitfld.long 0x2C 6. "PSSIEN,PSSI enable" "0: PSSI is disabled (default after reset),1: PSSI is enabled" newline bitfld.long 0x2C 5. "XSPI1EN,XSPI1 enable" "0: XSPI1 is disabled (default after reset),1: XSPI1 is enabled" newline bitfld.long 0x2C 4. "FMCEN,FMC enable" "0: FMC is disabled (default after reset),1: FMC is enabled" newline bitfld.long 0x2C 3. "JPEGEN,JPEG enable" "0: JPEG is disabled (default after reset),1: JPEG is enabled" newline bitfld.long 0x2C 1. "DMA2DEN,DMA2D enable" "0: DMA2D is disabled (default after reset),1: DMA2D is enabled" newline bitfld.long 0x2C 0. "HPDMA1EN,HPDMA1 enable" "0: HPDMA1 is disabled (default after reset),1: HPDMA1 is enabled" line.long 0x30 "RCC_APB1LENR,RCC APB1L enable register" bitfld.long 0x30 31. "UART8EN,UART8 enable" "0: UART8 is disabled (default after reset),1: UART8 is enabled" newline bitfld.long 0x30 30. "UART7EN,UART7 enable" "0: UART7 is disabled (default after reset),1: UART7 is enabled" newline bitfld.long 0x30 25. "I3C2EN,I3C2 enable" "0: I3C2 is disabled (default after reset),1: I3C2 is enabled" newline bitfld.long 0x30 24. "I3C1EN,I3C1 enable" "0: I3C1 is disabled (default after reset),1: I3C1 is enabled" newline bitfld.long 0x30 23. "I2C3EN,I2C3 enable" "0: I2C3 is disabled (default after reset),1: I2C3 is enabled" newline bitfld.long 0x30 22. "I2C2EN,I2C2 enable" "0: I2C2 is disabled (default after reset),1: I2C2 is enabled" newline bitfld.long 0x30 21. "I2C1EN,I2C1 enable" "0: I2C1 is disabled (default after reset),1: I2C1 is enabled" newline bitfld.long 0x30 20. "UART5EN,UART5 enable" "0: UART5 is disabled (default after reset),1: UART5 is enabled" newline bitfld.long 0x30 19. "UART4EN,UART4 enable" "0: UART4 is disabled (default after reset),1: UART4 is enabled" newline bitfld.long 0x30 18. "USART3EN,USART3 enable" "0: USART3 is disabled (default after reset),1: USART3 is enabled" newline bitfld.long 0x30 17. "USART2EN,USART2 enable" "0: USART2 is disabled (default after reset),1: USART2 is enabled" newline bitfld.long 0x30 16. "SPDIFRX1EN,SPDIFRX1 enable" "0: SPDIFRX1 is disabled (default after reset),1: SPDIFRX1 is enabled" newline bitfld.long 0x30 15. "SPI3EN,SPI3 enable" "0: SPI3 is disabled (default after reset),1: SPI3 is enabled" newline bitfld.long 0x30 14. "SPI2EN,SPI2 enable" "0: SPI2 is disabled (default after reset),1: SPI2 is enabled" newline bitfld.long 0x30 13. "TIM11EN,TIM11 enable" "0: TIM11 is disabled (default after reset),1: TIM11 is enabled" newline bitfld.long 0x30 12. "TIM10EN,TIM10 enable" "0: TIM10 is disabled (default after reset),1: TIM10 is enabled" newline bitfld.long 0x30 11. "WWDGEN,WWDG enable" "0: WWDG is disabled (default after reset),1: WWDG is enabled" newline bitfld.long 0x30 9. "LPTIM1EN,LPTIM1 enable" "0: LPTIM1 is disabled (default after reset),1: LPTIM1 is enabled" newline bitfld.long 0x30 8. "TIM14EN,TIM14 enable" "0: TIM14 is disabled (default after reset),1: TIM14 is enabled" newline bitfld.long 0x30 7. "TIM13EN,TIM13 enable" "0: TIM13 is disabled (default after reset),1: TIM13 is enabled" newline bitfld.long 0x30 6. "TIM12EN,TIM12 enable" "0: TIM12 is disabled (default after reset),1: TIM12 is enabled" newline bitfld.long 0x30 5. "TIM7EN,TIM7 enable" "0: TIM7 is disabled (default after reset),1: TIM7 is enabled" newline bitfld.long 0x30 4. "TIM6EN,TIM6 enable" "0: TIM6 is disabled (default after reset),1: TIM6 is enabled" newline bitfld.long 0x30 3. "TIM5EN,TIM5 enable" "0: TIM5 is disabled (default after reset),1: TIM5 is enabled" newline bitfld.long 0x30 2. "TIM4EN,TIM4 enable" "0: TIM4 is disabled (default after reset),1: TIM4 is enabled" newline bitfld.long 0x30 1. "TIM3EN,TIM3 enable" "0: TIM3 is disabled (default after reset),1: TIM3 is enabled" newline bitfld.long 0x30 0. "TIM2EN,TIM2 enable" "0: TIM2 is disabled (default after reset),1: TIM2 is enabled" line.long 0x34 "RCC_APB1HENR,RCC APB1H enable register" bitfld.long 0x34 18. "UCPD1EN,UCPD1 enable" "0: UCPD1 is disabled (default after reset),1: UCPD1 is enabled" newline bitfld.long 0x34 8. "FDCANEN,FDCAN enable" "0: FDCAN is disabled (default after reset),1: FDCAN is enabled" newline bitfld.long 0x34 5. "MDIOSEN,MDIOS enable" "0: MDIOS is disabled (default after reset),1: MDIOS is enabled" line.long 0x38 "RCC_APB2ENR,RCC APB2 enable register" bitfld.long 0x38 22. "SAI2EN,SAI2 enable" "0: SAI2 is disabled (default after reset),1: SAI2 is enabled" newline bitfld.long 0x38 21. "SAI1EN,SAI1 enable" "0: SAI1 is disabled (default after reset),1: SAI1 is enabled" newline bitfld.long 0x38 20. "SPI5EN,SPI5 enable" "0: SPI5 is disabled (default after reset),1: SPI5 is enabled" newline bitfld.long 0x38 19. "TIM9EN,TIM9 enable" "0: TIM9 is disabled (default after reset),1: TIM9 is enabled" newline bitfld.long 0x38 18. "TIM17EN,TIM17 enable" "0: TIM17 is disabled (default after reset),1: TIM17 is enabled" newline bitfld.long 0x38 17. "TIM16EN,TIM16 enable" "0: TIM16 is disabled (default after reset),1: TIM16 is enabled" newline bitfld.long 0x38 16. "TIM15EN,TIM15 enable" "0: TIM15 is disabled (default after reset),1: TIM15 is enabled" newline bitfld.long 0x38 15. "TIM18EN,TIM18 enable" "0: TIM18 is disabled (default after reset),1: TIM18 is enabled" newline bitfld.long 0x38 13. "SPI4EN,SPI4 enable" "0: SPI4 is disabled (default after reset),1: SPI4 is enabled" newline bitfld.long 0x38 12. "SPI1EN,SPI1 enable" "0: SPI1 is disabled (default after reset),1: SPI1 is enabled" newline bitfld.long 0x38 7. "USART10EN,USART10 enable" "0: USART10 is disabled (default after reset),1: USART10 is enabled" newline bitfld.long 0x38 6. "UART9EN,UART9 enable" "0: UART9 is disabled (default after reset),1: UART9 is enabled" newline bitfld.long 0x38 5. "USART6EN,USART6 enable" "0: USART6 is disabled (default after reset),1: USART6 is enabled" newline bitfld.long 0x38 4. "USART1EN,USART1 enable" "0: USART1 is disabled (default after reset),1: USART1 is enabled" newline bitfld.long 0x38 1. "TIM8EN,TIM8 enable" "0: TIM8 is disabled (default after reset),1: TIM8 is enabled" newline bitfld.long 0x38 0. "TIM1EN,TIM1 enable" "0: TIM1 is disabled (default after reset),1: TIM1 is enabled" line.long 0x3C "RCC_APB3ENR,RCC APB3 enable register" bitfld.long 0x3C 2. "DFTEN,DFT enable" "0: DFT is disabled (default after reset),1: DFT is enabled" line.long 0x40 "RCC_APB4LENR,RCC APB4L enable register" bitfld.long 0x40 31. "SERFEN,SERF enable" "0: SERF is disabled (default after reset),1: SERF is enabled" newline bitfld.long 0x40 23. "R2GNPUEN,R2GNPU enable" "0: R2GNPU is disabled (default after reset),1: R2GNPU is enabled" newline bitfld.long 0x40 22. "R2GRETEN,R2GRET enable" "0: R2GRET is disabled (default after reset),1: R2GRET is enabled" newline bitfld.long 0x40 17. "RTCAPBEN,RTCAPB enable" "0: RTCAPB is disabled (default after reset),1: RTCAPB is enabled" newline bitfld.long 0x40 16. "RTCEN,RTC enable" "0: RTC is disabled (default after reset),1: RTC is enabled" newline bitfld.long 0x40 15. "VREFBUFEN,VREFBUF enable" "0: VREFBUF is disabled (default after reset),1: VREFBUF is enabled" newline bitfld.long 0x40 12. "LPTIM5EN,LPTIM5 enable" "0: LPTIM5 is disabled (default after reset),1: LPTIM5 is enabled" newline bitfld.long 0x40 11. "LPTIM4EN,LPTIM4 enable" "0: LPTIM4 is disabled (default after reset),1: LPTIM4 is enabled" newline bitfld.long 0x40 10. "LPTIM3EN,LPTIM3 enable" "0: LPTIM3 is disabled (default after reset),1: LPTIM3 is enabled" newline bitfld.long 0x40 9. "LPTIM2EN,LPTIM2 enable" "0: LPTIM2 is disabled (default after reset),1: LPTIM2 is enabled" newline bitfld.long 0x40 7. "I2C4EN,I2C4 enable" "0: I2C4 is disabled (default after reset),1: I2C4 is enabled" newline bitfld.long 0x40 5. "SPI6EN,SPI6 enable" "0: SPI6 is disabled (default after reset),1: SPI6 is enabled" newline bitfld.long 0x40 3. "LPUART1EN,LPUART1 enable" "0: LPUART1 is disabled (default after reset),1: LPUART1 is enabled" newline bitfld.long 0x40 2. "HDPEN,HDP enable" "0: HDP is disabled (default after reset),1: HDP is enabled" line.long 0x44 "RCC_APB4HENR,RCC APB4H enable register" bitfld.long 0x44 4. "BUSPERFMEN,BUSPERFM enable" "0: BUSPERFM is disabled (default after reset),1: BUSPERFM is enabled" newline bitfld.long 0x44 2. "DTSEN,DTS enable" "0: DTS is disabled (default after reset),1: DTS is enabled" newline bitfld.long 0x44 1. "BSECEN,BSEC enable" "0: BSEC is disabled,1: BSEC is enabled (default after reset)" newline bitfld.long 0x44 0. "SYSCFGEN,SYSCFG enable" "0: SYSCFG is disabled (default after reset),1: SYSCFG is enabled" line.long 0x48 "RCC_APB5ENR,RCC APB5 enable register" bitfld.long 0x48 6. "CSIEN,CSI enable" "0: CSI is disabled (default after reset),1: CSI is enabled" newline bitfld.long 0x48 5. "VENCEN,VENC enable" "0: VENC is disabled (default after reset),1: VENC is enabled" newline bitfld.long 0x48 4. "GFXTIMEN,GFXTIM enable" "0: GFXTIM is disabled (default after reset),1: GFXTIM is enabled" newline bitfld.long 0x48 2. "DCMIPPEN,DCMIPP enable" "0: DCMIPP is disabled (default after reset),1: DCMIPP is enabled" newline bitfld.long 0x48 1. "LTDCEN,LTDC enable" "0: LTDC is disabled (default after reset),1: LTDC is enabled" line.long 0x4C "RCC_DIVLPENR,RCC dividers Sleep enable register" bitfld.long 0x4C 19. "IC20LPEN,IC20 sleep enable" "0: IC20 is disabled in Sleep mode (default after..,1: IC20 is enabled in Sleep mode" newline bitfld.long 0x4C 18. "IC19LPEN,IC19 sleep enable" "0: IC19 is disabled in Sleep mode (default after..,1: IC19 is enabled in Sleep mode" newline bitfld.long 0x4C 17. "IC18LPEN,IC18 sleep enable" "0: IC18 is disabled in Sleep mode (default after..,1: IC18 is enabled in Sleep mode" newline bitfld.long 0x4C 16. "IC17LPEN,IC17 sleep enable" "0: IC17 is disabled in Sleep mode (default after..,1: IC17 is enabled in Sleep mode" newline bitfld.long 0x4C 15. "IC16LPEN,IC16 sleep enable" "0: IC16 is disabled in Sleep mode (default after..,1: IC16 is enabled in Sleep mode" newline bitfld.long 0x4C 14. "IC15LPEN,IC15 sleep enable" "0: IC15 is disabled in Sleep mode (default after..,1: IC15 is enabled in Sleep mode" newline bitfld.long 0x4C 13. "IC14LPEN,IC14 sleep enable" "0: IC14 is disabled in Sleep mode (default after..,1: IC14 is enabled in Sleep mode" newline bitfld.long 0x4C 12. "IC13LPEN,IC13 sleep enable" "0: IC13 is disabled in Sleep mode (default after..,1: IC13 is enabled in Sleep mode" newline bitfld.long 0x4C 11. "IC12LPEN,IC12 sleep enable" "0: IC12 is disabled in Sleep mode (default after..,1: IC12 is enabled in Sleep mode" newline bitfld.long 0x4C 10. "IC11LPEN,IC11 sleep enable" "0: IC11 is disabled in Sleep mode (default after..,1: IC11 is enabled in Sleep mode" newline bitfld.long 0x4C 9. "IC10LPEN,IC10 sleep enable" "0: IC10 is disabled in Sleep mode (default after..,1: IC10 is enabled in Sleep mode" newline bitfld.long 0x4C 8. "IC9LPEN,IC9 sleep enable" "0: IC9 is disabled in Sleep mode (default after..,1: IC9 is enabled in Sleep mode" newline bitfld.long 0x4C 7. "IC8LPEN,IC8 sleep enable" "0: IC8 is disabled in Sleep mode (default after..,1: IC8 is enabled in Sleep mode" newline bitfld.long 0x4C 6. "IC7LPEN,IC7 sleep enable" "0: IC7 is disabled in Sleep mode (default after..,1: IC7 is enabled in Sleep mode" newline bitfld.long 0x4C 5. "IC6LPEN,IC6 sleep enable" "0: IC6 is disabled in Sleep mode (default after..,1: IC6 is enabled in Sleep mode" newline bitfld.long 0x4C 4. "IC5LPEN,IC5 sleep enable" "0: IC5 is disabled in Sleep mode (default after..,1: IC5 is enabled in Sleep mode" newline bitfld.long 0x4C 3. "IC4LPEN,IC4 sleep enable" "0: IC4 is disabled in Sleep mode (default after..,1: IC4 is enabled in Sleep mode" newline bitfld.long 0x4C 2. "IC3LPEN,IC3 sleep enable" "0: IC3 is disabled in Sleep mode (default after..,1: IC3 is enabled in Sleep mode" newline bitfld.long 0x4C 1. "IC2LPEN,IC2 sleep enable" "0: IC2 is disabled in Sleep mode (default after..,1: IC2 is enabled in Sleep mode" newline bitfld.long 0x4C 0. "IC1LPEN,IC1 sleep enable" "0: IC1 is disabled in Sleep mode (default after..,1: IC1 is enabled in Sleep mode" line.long 0x50 "RCC_BUSLPENR,RCC SoC buses Sleep enable register" bitfld.long 0x50 12. "APB5LPEN,APB5 sleep enable" "0: APB5 is disabled in Sleep mode (default after..,1: APB5 is enabled in Sleep mode" newline bitfld.long 0x50 11. "APB4LPEN,APB4 sleep enable" "0: APB4 is disabled in Sleep mode (default after..,1: APB4 is enabled in Sleep mode" newline bitfld.long 0x50 10. "APB3LPEN,APB3 sleep enable" "0: APB3 is disabled in Sleep mode (default after..,1: APB3 is enabled in Sleep mode" newline bitfld.long 0x50 9. "APB2LPEN,APB2 sleep enable" "0: APB2 is disabled in Sleep mode (default after..,1: APB2 is enabled in Sleep mode" newline bitfld.long 0x50 8. "APB1LPEN,APB1 sleep enable" "0: APB1 is disabled in Sleep mode (default after..,1: APB1 is enabled in Sleep mode" newline bitfld.long 0x50 7. "AHB5LPEN,AHB5 sleep enable" "0: AHB5 is disabled in Sleep mode (default after..,1: AHB5 is enabled in Sleep mode" newline bitfld.long 0x50 6. "AHB4LPEN,AHB4 sleep enable" "0: AHB4 is disabled in Sleep mode (default after..,1: AHB4 is enabled in Sleep mode" newline bitfld.long 0x50 5. "AHB3LPEN,AHB3 sleep enable" "0: AHB3 is disabled in Sleep mode (default after..,1: AHB3 is enabled in Sleep mode" newline bitfld.long 0x50 4. "AHB2LPEN,AHB2 sleep enable" "0: AHB2 is disabled in Sleep mode (default after..,1: AHB2 is enabled in Sleep mode" newline bitfld.long 0x50 3. "AHB1LPEN,AHB1 sleep enable" "0: AHB1 is disabled in Sleep mode (default after..,1: AHB1 is enabled in Sleep mode" newline bitfld.long 0x50 2. "AHBMLPEN,AHBM sleep enable" "0: AHBM is disabled in Sleep mode (default after..,1: AHBM is enabled in Sleep mode" newline bitfld.long 0x50 1. "ACLKNCLPEN,ACLKNC sleep enable" "0: ACLKNC is disabled in Sleep mode,1: ACLKNC is enabled in Sleep mode (default after.." newline bitfld.long 0x50 0. "ACLKNLPEN,ACLKN sleep enable" "0: ACLKN is disabled in Sleep mode,1: ACLKN is enabled in Sleep mode (default after.." line.long 0x54 "RCC_MISCLPENR,RCC miscellaneous configurations Sleep enable register" bitfld.long 0x54 6. "PERLPEN,PER sleep enable" "0: PER is disabled in Sleep mode (default after..,1: PER is enabled in Sleep mode" newline bitfld.long 0x54 3. "XSPIPHYCOMPLPEN,XSPIPHYCOMP sleep enable" "0: XSPIPHYCOMP is disabled in Sleep mode (default..,1: XSPIPHYCOMP is enabled in Sleep mode" newline bitfld.long 0x54 0. "DBGLPEN,DBG sleep enable" "0: DBG is disabled in Sleep mode (default after..,1: DBG is enabled in Sleep mode" line.long 0x58 "RCC_MEMLPENR,RCC memory Sleep enable register" bitfld.long 0x58 12. "BOOTROMLPEN,BOOTROM sleep enable" "0: BOOTROM is disabled in Sleep mode (default after..,1: BOOTROM is enabled in Sleep mode" newline bitfld.long 0x58 11. "VENCRAMLPEN,VENCRAM sleep enable" "0: VENCRAM is disabled in Sleep mode (default after..,1: VENCRAM is enabled in Sleep mode" newline bitfld.long 0x58 10. "NPUCACHERAMLPEN,NPUCACHERAM sleep enable" "0: NPUCACHERAM is disabled in Sleep mode (default..,1: NPUCACHERAM is enabled in Sleep mode" newline bitfld.long 0x58 9. "FLEXRAMLPEN,FLEXRAM sleep enable" "0: FLEXRAM is disabled in Sleep mode (default after..,1: FLEXRAM is enabled in Sleep mode" newline bitfld.long 0x58 8. "AXISRAM2LPEN,AXISRAM2 sleep enable" "0: AXISRAM2 is disabled in Sleep mode (default..,1: AXISRAM2 is enabled in Sleep mode" newline bitfld.long 0x58 7. "AXISRAM1LPEN,AXISRAM1 sleep enable" "0: AXISRAM1 is disabled in Sleep mode (default..,1: AXISRAM1 is enabled in Sleep mode" newline bitfld.long 0x58 6. "BKPSRAMLPEN,BKPSRAM sleep enable" "0: BKPSRAM is disabled in Sleep mode (default after..,1: BKPSRAM is enabled in Sleep mode" newline bitfld.long 0x58 5. "AHBSRAM2LPEN,AHBSRAM2 sleep enable" "0: AHBSRAM2 is disabled in Sleep mode (default..,1: AHBSRAM2 is enabled in Sleep mode" newline bitfld.long 0x58 4. "AHBSRAM1LPEN,AHBSRAM1 sleep enable" "0: AHBSRAM1 is disabled in Sleep mode (default..,1: AHBSRAM1 is enabled in Sleep mode" newline bitfld.long 0x58 3. "AXISRAM6LPEN,AXISRAM6 sleep enable" "0: AXISRAM6 is disabled in Sleep mode (default..,1: AXISRAM6 is enabled in Sleep mode" newline bitfld.long 0x58 2. "AXISRAM5LPEN,AXISRAM5 sleep enable" "0: AXISRAM5 is disabled in Sleep mode (default..,1: AXISRAM5 is enabled in Sleep mode" newline bitfld.long 0x58 1. "AXISRAM4LPEN,AXISRAM4 sleep enable" "0: AXISRAM4 is disabled in Sleep mode (default..,1: AXISRAM4 is enabled in Sleep mode" newline bitfld.long 0x58 0. "AXISRAM3LPEN,AXISRAM3 sleep enable" "0: AXISRAM3 is disabled in Sleep mode (default..,1: AXISRAM3 is enabled in Sleep mode" line.long 0x5C "RCC_AHB1LPENR,RCC AHB1 Sleep enable register" bitfld.long 0x5C 5. "ADC12LPEN,ADC12 sleep enable" "0: ADC12 is disabled in Sleep mode (default after..,1: ADC12 is enabled in Sleep mode" newline bitfld.long 0x5C 4. "GPDMA1LPEN,GPDMA1 sleep enable" "0: GPDMA1 is disabled in Sleep mode (default after..,1: GPDMA1 is enabled in Sleep mode" line.long 0x60 "RCC_AHB2LPENR,RCC AHB2 Sleep enable register" bitfld.long 0x60 17. "ADF1LPEN,ADF1 sleep enable" "0: ADF1 is disabled in Sleep mode (default after..,1: ADF1 is enabled in Sleep mode" newline bitfld.long 0x60 16. "MDF1LPEN,MDF1 sleep enable" "0: MDF1 is disabled in Sleep mode (default after..,1: MDF1 is enabled in Sleep mode" newline bitfld.long 0x60 12. "RAMCFGLPEN,RAMCFG sleep enable" "0: RAMCFG is disabled in Sleep mode (default after..,1: RAMCFG is enabled in Sleep mode" line.long 0x64 "RCC_AHB3LPENR,RCC AHB3 Sleep enable register" bitfld.long 0x64 14. "RISAFLPEN,RISAF sleep enable" "0: RISAF is disabled in Sleep mode (default after..,1: RISAF is enabled in Sleep mode" newline bitfld.long 0x64 10. "IACLPEN,IAC sleep enable" "0: IAC is disabled in Sleep mode,1: IAC is enabled in Sleep mode (default after reset)" newline bitfld.long 0x64 9. "RIFSCLPEN,RIFSC sleep enable" "0: RIFSC is disabled in Sleep mode (default after..,1: RIFSC is enabled in Sleep mode" newline bitfld.long 0x64 8. "PKALPEN,PKA sleep enable" "0: PKA is disabled in Sleep mode (default after..,1: PKA is enabled in Sleep mode" newline bitfld.long 0x64 4. "SAESLPEN,SAES sleep enable" "0: SAES is disabled in Sleep mode (default after..,1: SAES is enabled in Sleep mode" newline bitfld.long 0x64 2. "CRYPLPEN,CRYP sleep enable" "0: CRYP is disabled in Sleep mode (default after..,1: CRYP is enabled in Sleep mode" newline bitfld.long 0x64 1. "HASHLPEN,HASH sleep enable" "0: HASH is disabled in Sleep mode (default after..,1: HASH is enabled in Sleep mode" newline bitfld.long 0x64 0. "RNGLPEN,RNG sleep enable" "0: RNG is disabled in Sleep mode (default after..,1: RNG is enabled in Sleep mode" line.long 0x68 "RCC_AHB4LPENR,RCC AHB4 Sleep enable register" bitfld.long 0x68 19. "CRCLPEN,CRC sleep enable" "0: CRC is disabled in Sleep mode (default after..,1: CRC is enabled in Sleep mode" newline bitfld.long 0x68 18. "PWRLPEN,PWR sleep enable" "0: PWR is disabled in Sleep mode,1: PWR is enabled in Sleep mode (default after reset)" newline bitfld.long 0x68 16. "GPIOQLPEN,GPIOQ sleep enable" "0: GPIOQ is disabled in Sleep mode (default after..,1: GPIOQ is enabled in Sleep mode" newline bitfld.long 0x68 15. "GPIOPLPEN,GPIOP sleep enable" "0: GPIOP is disabled in Sleep mode (default after..,1: GPIOP is enabled in Sleep mode" newline bitfld.long 0x68 14. "GPIOOLPEN,GPIOO sleep enable" "0: GPIOO is disabled in Sleep mode (default after..,1: GPIOO is enabled in Sleep mode" newline bitfld.long 0x68 13. "GPIONLPEN,GPION sleep enable" "0: GPION is disabled in Sleep mode (default after..,1: GPION is enabled in Sleep mode" newline bitfld.long 0x68 7. "GPIOHLPEN,GPIOH sleep enable" "0: GPIOH is disabled in Sleep mode (default after..,1: GPIOH is enabled in Sleep mode" newline bitfld.long 0x68 6. "GPIOGLPEN,GPIOG sleep enable" "0: GPIOG is disabled in Sleep mode (default after..,1: GPIOG is enabled in Sleep mode" newline bitfld.long 0x68 5. "GPIOFLPEN,GPIOF sleep enable" "0: GPIOF is disabled in Sleep mode (default after..,1: GPIOF is enabled in Sleep mode" newline bitfld.long 0x68 4. "GPIOELPEN,GPIOE sleep enable" "0: GPIOE is disabled in Sleep mode (default after..,1: GPIOE is enabled in Sleep mode" newline bitfld.long 0x68 3. "GPIODLPEN,GPIOD sleep enable" "0: GPIOD is disabled in Sleep mode (default after..,1: GPIOD is enabled in Sleep mode" newline bitfld.long 0x68 2. "GPIOCLPEN,GPIOC sleep enable" "0: GPIOC is disabled in Sleep mode (default after..,1: GPIOC is enabled in Sleep mode" newline bitfld.long 0x68 1. "GPIOBLPEN,GPIOB sleep enable" "0: GPIOB is disabled in Sleep mode (default after..,1: GPIOB is enabled in Sleep mode" newline bitfld.long 0x68 0. "GPIOALPEN,GPIOA sleep enable" "0: GPIOA is disabled in Sleep mode (default after..,1: GPIOA is enabled in Sleep mode" line.long 0x6C "RCC_AHB5LPENR,RCC AHB5 Sleep enable register" bitfld.long 0x6C 31. "NPULPEN,NPU sleep enable" "0: NPU is disabled in Sleep mode (default after..,1: NPU is enabled in Sleep mode" newline bitfld.long 0x6C 30. "NPUCACHELPEN,NPUCACHE sleep enable" "0: NPUCACHE is disabled in Sleep mode (default..,1: NPUCACHE is enabled in Sleep mode" newline bitfld.long 0x6C 29. "OTG2LPEN,OTG2 sleep enable" "0: OTG2 is disabled in Sleep mode (default after..,1: OTG2 is enabled in Sleep mode" newline bitfld.long 0x6C 28. "OTGPHY2LPEN,OTGPHY2 sleep enable" "0: OTGPHY2 is disabled in Sleep mode (default after..,1: OTGPHY2 is enabled in Sleep mode" newline bitfld.long 0x6C 27. "OTGPHY1LPEN,OTGPHY1 sleep enable" "0: OTGPHY1 is disabled in Sleep mode (default after..,1: OTGPHY1 is enabled in Sleep mode" newline bitfld.long 0x6C 26. "OTG1LPEN,OTG1 sleep enable" "0: OTG1 is disabled in Sleep mode (default after..,1: OTG1 is enabled in Sleep mode" newline bitfld.long 0x6C 25. "ETH1LPEN,ETH1 sleep enable" "0: ETH1 is disabled in Sleep mode (default after..,1: ETH1 is enabled in Sleep mode" newline bitfld.long 0x6C 24. "ETH1RXLPEN,ETH1RX sleep enable" "0: ETH1RX is disabled in Sleep mode (default after..,1: ETH1RX is enabled in Sleep mode" newline bitfld.long 0x6C 23. "ETH1TXLPEN,ETH1TX sleep enable" "0: ETH1TX is disabled in Sleep mode (default after..,1: ETH1TX is enabled in Sleep mode" newline bitfld.long 0x6C 22. "ETH1MACLPEN,ETH1MAC sleep enable" "0: ETH1MAC is disabled in Sleep mode (default after..,1: ETH1MAC is enabled in Sleep mode" newline bitfld.long 0x6C 20. "GPULPEN,GPU sleep enable" "0: GPU is disabled in Sleep mode (default after..,1: GPU is enabled in Sleep mode" newline bitfld.long 0x6C 19. "GFXMMULPEN,GFXMMU sleep enable" "0: GFXMMU is disabled in Sleep mode (default after..,1: GFXMMU is enabled in Sleep mode" newline bitfld.long 0x6C 18. "MCE4LPEN,MCE4 sleep enable" "0: MCE4 is disabled in Sleep mode (default after..,1: MCE4 is enabled in Sleep mode" newline bitfld.long 0x6C 17. "XSPI3LPEN,XSPI3 sleep enable" "0: XSPI3 is disabled in Sleep mode (default after..,1: XSPI3 is enabled in Sleep mode" newline bitfld.long 0x6C 16. "MCE3LPEN,MCE3 sleep enable" "0: MCE3 is disabled in Sleep mode (default after..,1: MCE3 is enabled in Sleep mode" newline bitfld.long 0x6C 15. "MCE2LPEN,MCE2 sleep enable" "0: MCE2 is disabled in Sleep mode (default after..,1: MCE2 is enabled in Sleep mode" newline bitfld.long 0x6C 14. "MCE1LPEN,MCE1 sleep enable" "0: MCE1 is disabled in Sleep mode (default after..,1: MCE1 is enabled in Sleep mode" newline bitfld.long 0x6C 13. "XSPIMLPEN,XSPIM sleep enable" "0: XSPIM is disabled in Sleep mode (default after..,1: XSPIM is enabled in Sleep mode" newline bitfld.long 0x6C 12. "XSPI2LPEN,XSPI2 sleep enable" "0: XSPI2 is disabled in Sleep mode (default after..,1: XSPI2 is enabled in Sleep mode" newline bitfld.long 0x6C 8. "SDMMC1LPEN,SDMMC1 sleep enable" "0: SDMMC1 is disabled in Sleep mode (default after..,1: SDMMC1 is enabled in Sleep mode" newline bitfld.long 0x6C 7. "SDMMC2LPEN,SDMMC2 sleep enable" "0: SDMMC2 is disabled in Sleep mode (default after..,1: SDMMC2 is enabled in Sleep mode" newline bitfld.long 0x6C 6. "PSSILPEN,PSSI sleep enable" "0: PSSI is disabled in Sleep mode (default after..,1: PSSI is enabled in Sleep mode" newline bitfld.long 0x6C 5. "XSPI1LPEN,XSPI1 sleep enable" "0: XSPI1 is disabled in Sleep mode (default after..,1: XSPI1 is enabled in Sleep mode" newline bitfld.long 0x6C 4. "FMCLPEN,FMC sleep enable" "0: FMC is disabled in Sleep mode (default after..,1: FMC is enabled in Sleep mode" newline bitfld.long 0x6C 3. "JPEGLPEN,JPEG sleep enable" "0: JPEG is disabled in Sleep mode (default after..,1: JPEG is enabled in Sleep mode" newline bitfld.long 0x6C 1. "DMA2DLPEN,DMA2D sleep enable" "0: DMA2D is disabled in Sleep mode (default after..,1: DMA2D is enabled in Sleep mode" newline bitfld.long 0x6C 0. "HPDMA1LPEN,HPDMA1 sleep enable" "0: HPDMA1 is disabled in Sleep mode (default after..,1: HPDMA1 is enabled in Sleep mode" line.long 0x70 "RCC_APB1LLPENR,RCC APB1L Sleep enable register" bitfld.long 0x70 31. "UART8LPEN,UART8 sleep enable" "0: UART8 is disabled in Sleep mode (default after..,1: UART8 is enabled in Sleep mode" newline bitfld.long 0x70 30. "UART7LPEN,UART7 sleep enable" "0: UART7 is disabled in Sleep mode (default after..,1: UART7 is enabled in Sleep mode" newline bitfld.long 0x70 25. "I3C2LPEN,I3C2 sleep enable" "0: I3C2 is disabled in Sleep mode (default after..,1: I3C2 is enabled in Sleep mode" newline bitfld.long 0x70 24. "I3C1LPEN,I3C1 sleep enable" "0: I3C1 is disabled in Sleep mode (default after..,1: I3C1 is enabled in Sleep mode" newline bitfld.long 0x70 23. "I2C3LPEN,I2C3 sleep enable" "0: I2C3 is disabled in Sleep mode (default after..,1: I2C3 is enabled in Sleep mode" newline bitfld.long 0x70 22. "I2C2LPEN,I2C2 sleep enable" "0: I2C2 is disabled in Sleep mode (default after..,1: I2C2 is enabled in Sleep mode" newline bitfld.long 0x70 21. "I2C1LPEN,I2C1 sleep enable" "0: I2C1 is disabled in Sleep mode (default after..,1: I2C1 is enabled in Sleep mode" newline bitfld.long 0x70 20. "UART5LPEN,UART5 sleep enable" "0: UART5 is disabled in Sleep mode (default after..,1: UART5 is enabled in Sleep mode" newline bitfld.long 0x70 19. "UART4LPEN,UART4 sleep enable" "0: UART4 is disabled in Sleep mode (default after..,1: UART4 is enabled in Sleep mode" newline bitfld.long 0x70 18. "USART3LPEN,USART3 sleep enable" "0: USART3 is disabled in Sleep mode (default after..,1: USART3 is enabled in Sleep mode" newline bitfld.long 0x70 17. "USART2LPEN,USART2 sleep enable" "0: USART2 is disabled in Sleep mode (default after..,1: USART2 is enabled in Sleep mode" newline bitfld.long 0x70 16. "SPDIFRX1LPEN,SPDIFRX1 sleep enable" "0: SPDIFRX1 is disabled in Sleep mode (default..,1: SPDIFRX1 is enabled in Sleep mode" newline bitfld.long 0x70 15. "SPI3LPEN,SPI3 sleep enable" "0: SPI3 is disabled in Sleep mode (default after..,1: SPI3 is enabled in Sleep mode" newline bitfld.long 0x70 14. "SPI2LPEN,SPI2 sleep enable" "0: SPI2 is disabled in Sleep mode (default after..,1: SPI2 is enabled in Sleep mode" newline bitfld.long 0x70 13. "TIM11LPEN,TIM11 sleep enable" "0: TIM11 is disabled in Sleep mode (default after..,1: TIM11 is enabled in Sleep mode" newline bitfld.long 0x70 12. "TIM10LPEN,TIM10 sleep enable" "0: TIM10 is disabled in Sleep mode (default after..,1: TIM10 is enabled in Sleep mode" newline bitfld.long 0x70 11. "WWDGLPEN,WWDG sleep enable" "0: WWDG is disabled in Sleep mode (default after..,1: WWDG is enabled in Sleep mode" newline bitfld.long 0x70 9. "LPTIM1LPEN,LPTIM1 sleep enable" "0: LPTIM1 is disabled in Sleep mode (default after..,1: LPTIM1 is enabled in Sleep mode" newline bitfld.long 0x70 8. "TIM14LPEN,TIM14 sleep enable" "0: TIM14 is disabled in Sleep mode (default after..,1: TIM14 is enabled in Sleep mode" newline bitfld.long 0x70 7. "TIM13LPEN,TIM13 sleep enable" "0: TIM13 is disabled in Sleep mode (default after..,1: TIM13 is enabled in Sleep mode" newline bitfld.long 0x70 6. "TIM12LPEN,TIM12 sleep enable" "0: TIM12 is disabled in Sleep mode (default after..,1: TIM12 is enabled in Sleep mode" newline bitfld.long 0x70 5. "TIM7LPEN,TIM7 sleep enable" "0: TIM7 is disabled in Sleep mode (default after..,1: TIM7 is enabled in Sleep mode" newline bitfld.long 0x70 4. "TIM6LPEN,TIM6 sleep enable" "0: TIM6 is disabled in Sleep mode (default after..,1: TIM6 is enabled in Sleep mode" newline bitfld.long 0x70 3. "TIM5LPEN,TIM5 sleep enable" "0: TIM5 is disabled in Sleep mode (default after..,1: TIM5 is enabled in Sleep mode" newline bitfld.long 0x70 2. "TIM4LPEN,TIM4 sleep enable" "0: TIM4 is disabled in Sleep mode (default after..,1: TIM4 is enabled in Sleep mode" newline bitfld.long 0x70 1. "TIM3LPEN,TIM3 sleep enable" "0: TIM3 is disabled in Sleep mode (default after..,1: TIM3 is enabled in Sleep mode" newline bitfld.long 0x70 0. "TIM2LPEN,TIM2 sleep enable" "0: TIM2 is disabled in Sleep mode (default after..,1: TIM2 is enabled in Sleep mode" line.long 0x74 "RCC_APB1HLPENR,RCC APB1H Sleep enable register" bitfld.long 0x74 18. "UCPD1LPEN,UCPD1 sleep enable" "0: UCPD1 is disabled in Sleep mode (default after..,1: UCPD1 is enabled in Sleep mode" newline bitfld.long 0x74 8. "FDCANLPEN,FDCAN sleep enable" "0: FDCAN is disabled in Sleep mode (default after..,1: FDCAN is enabled in Sleep mode" newline bitfld.long 0x74 5. "MDIOSLPEN,MDIOS sleep enable" "0: MDIOS is disabled in Sleep mode (default after..,1: MDIOS is enabled in Sleep mode" line.long 0x78 "RCC_APB2LPENR,RCC APB2 Sleep enable register" bitfld.long 0x78 22. "SAI2LPEN,SAI2 sleep enable" "0: SAI2 is disabled in Sleep mode (default after..,1: SAI2 is enabled in Sleep mode" newline bitfld.long 0x78 21. "SAI1LPEN,SAI1 sleep enable" "0: SAI1 is disabled in Sleep mode (default after..,1: SAI1 is enabled in Sleep mode" newline bitfld.long 0x78 20. "SPI5LPEN,SPI5 sleep enable" "0: SPI5 is disabled in Sleep mode (default after..,1: SPI5 is enabled in Sleep mode" newline bitfld.long 0x78 19. "TIM9LPEN,TIM9 sleep enable" "0: TIM9 is disabled in Sleep mode (default after..,1: TIM9 is enabled in Sleep mode" newline bitfld.long 0x78 18. "TIM17LPEN,TIM17 sleep enable" "0: TIM17 is disabled in Sleep mode (default after..,1: TIM17 is enabled in Sleep mode" newline bitfld.long 0x78 17. "TIM16LPEN,TIM16 sleep enable" "0: TIM16 is disabled in Sleep mode (default after..,1: TIM16 is enabled in Sleep mode" newline bitfld.long 0x78 16. "TIM15LPEN,TIM15 sleep enable" "0: TIM15 is disabled in Sleep mode (default after..,1: TIM15 is enabled in Sleep mode" newline bitfld.long 0x78 15. "TIM18LPEN,TIM18 sleep enable" "0: TIM18 is disabled in Sleep mode (default after..,1: TIM18 is enabled in Sleep mode" newline bitfld.long 0x78 13. "SPI4LPEN,SPI4 sleep enable" "0: SPI4 is disabled in Sleep mode (default after..,1: SPI4 is enabled in Sleep mode" newline bitfld.long 0x78 12. "SPI1LPEN,SPI1 sleep enable" "0: SPI1 is disabled in Sleep mode (default after..,1: SPI1 is enabled in Sleep mode" newline bitfld.long 0x78 7. "USART10LPEN,USART10 sleep enable" "0: USART10 is disabled in Sleep mode (default after..,1: USART10 is enabled in Sleep mode" newline bitfld.long 0x78 6. "UART9LPEN,UART9 sleep enable" "0: UART9 is disabled in Sleep mode (default after..,1: UART9 is enabled in Sleep mode" newline bitfld.long 0x78 5. "USART6LPEN,USART6 sleep enable" "0: USART6 is disabled in Sleep mode (default after..,1: USART6 is enabled in Sleep mode" newline bitfld.long 0x78 4. "USART1LPEN,USART1 sleep enable" "0: USART1 is disabled in Sleep mode (default after..,1: USART1 is enabled in Sleep mode" newline bitfld.long 0x78 1. "TIM8LPEN,TIM8 sleep enable" "0: TIM8 is disabled in Sleep mode (default after..,1: TIM8 is enabled in Sleep mode" newline bitfld.long 0x78 0. "TIM1LPEN,TIM1 sleep enable" "0: TIM1 is disabled in Sleep mode (default after..,1: TIM1 is enabled in Sleep mode" line.long 0x7C "RCC_APB3LPENR,RCC APB3 Sleep enable register" bitfld.long 0x7C 2. "DFTLPEN,DFT sleep enable" "0: DFT is disabled in Sleep mode (default after..,1: DFT is enabled in Sleep mode" line.long 0x80 "RCC_APB4LLPENR,RCC APB4L Sleep enable register" bitfld.long 0x80 31. "SERFLPEN,SERF sleep enable" "0: SERF is disabled in Sleep mode (default after..,1: SERF is enabled in Sleep mode" newline bitfld.long 0x80 23. "R2GNPULPEN,R2GNPU sleep enable" "0: R2GNPU is disabled in Sleep mode (default after..,1: R2GNPU is enabled in Sleep mode" newline bitfld.long 0x80 22. "R2GRETLPEN,R2GRET sleep enable" "0: R2GRET is disabled in Sleep mode (default after..,1: R2GRET is enabled in Sleep mode" newline bitfld.long 0x80 17. "RTCAPBLPEN,RTCAPB sleep enable" "0: RTCAPB is disabled in Sleep mode (default after..,1: RTCAPB is enabled in Sleep mode" newline bitfld.long 0x80 16. "RTCLPEN,RTC sleep enable" "0: RTC is disabled in Sleep mode (default after..,1: RTC is enabled in Sleep mode" newline bitfld.long 0x80 15. "VREFBUFLPEN,VREFBUF sleep enable" "0: VREFBUF is disabled in Sleep mode (default after..,1: VREFBUF is enabled in Sleep mode" newline bitfld.long 0x80 12. "LPTIM5LPEN,LPTIM5 sleep enable" "0: LPTIM5 is disabled in Sleep mode (default after..,1: LPTIM5 is enabled in Sleep mode" newline bitfld.long 0x80 11. "LPTIM4LPEN,LPTIM4 sleep enable" "0: LPTIM4 is disabled in Sleep mode (default after..,1: LPTIM4 is enabled in Sleep mode" newline bitfld.long 0x80 10. "LPTIM3LPEN,LPTIM3 sleep enable" "0: LPTIM3 is disabled in Sleep mode (default after..,1: LPTIM3 is enabled in Sleep mode" newline bitfld.long 0x80 9. "LPTIM2LPEN,LPTIM2 sleep enable" "0: LPTIM2 is disabled in Sleep mode (default after..,1: LPTIM2 is enabled in Sleep mode" newline bitfld.long 0x80 7. "I2C4LPEN,I2C4 sleep enable" "0: I2C4 is disabled in Sleep mode (default after..,1: I2C4 is enabled in Sleep mode" newline bitfld.long 0x80 5. "SPI6LPEN,SPI6 sleep enable" "0: SPI6 is disabled in Sleep mode (default after..,1: SPI6 is enabled in Sleep mode" newline bitfld.long 0x80 3. "LPUART1LPEN,LPUART1 sleep enable" "0: LPUART1 is disabled in Sleep mode (default after..,1: LPUART1 is enabled in Sleep mode" newline bitfld.long 0x80 2. "HDPLPEN,HDP sleep enable" "0: HDP is disabled in Sleep mode (default after..,1: HDP is enabled in Sleep mode" line.long 0x84 "RCC_APB4HLPENR,RCC APB4H Sleep enable register" bitfld.long 0x84 4. "BUSPERFMLPEN,BUSPERFM sleep enable" "0: BUSPERFM is disabled in Sleep mode (default..,1: BUSPERFM is enabled in Sleep mode" newline bitfld.long 0x84 2. "DTSLPEN,DTS sleep enable" "0: DTS is disabled in Sleep mode (default after..,1: DTS is enabled in Sleep mode" newline bitfld.long 0x84 1. "BSECLPEN,BSEC sleep enable" "0: BSEC is disabled in Sleep mode,1: BSEC is enabled in Sleep mode (default after.." newline bitfld.long 0x84 0. "SYSCFGLPEN,SYSCFG sleep enable" "0: SYSCFG is disabled in Sleep mode (default after..,1: SYSCFG is enabled in Sleep mode" line.long 0x88 "RCC_APB5LPENR,RCC APB5 Sleep enable register" bitfld.long 0x88 6. "CSILPEN,CSI sleep enable" "0: CSI is disabled in Sleep mode (default after..,1: CSI is enabled in Sleep mode" newline bitfld.long 0x88 5. "VENCLPEN,VENC sleep enable" "0: VENC is disabled in Sleep mode (default after..,1: VENC is enabled in Sleep mode" newline bitfld.long 0x88 4. "GFXTIMLPEN,GFXTIM sleep enable" "0: GFXTIM is disabled in Sleep mode (default after..,1: GFXTIM is enabled in Sleep mode" newline bitfld.long 0x88 2. "DCMIPPLPEN,DCMIPP sleep enable" "0: DCMIPP is disabled in Sleep mode (default after..,1: DCMIPP is enabled in Sleep mode" newline bitfld.long 0x88 1. "LTDCLPEN,LTDC sleep enable" "0: LTDC is disabled in Sleep mode (default after..,1: LTDC is enabled in Sleep mode" group.long 0x44C++0x3 line.long 0x0 "RCC_RDCR,RCC APB5 Sleep enable register" hexmask.long.byte 0x0 24.--27. 1. "EADLY,BOOTROM sleep enable" newline hexmask.long.byte 0x0 16.--20. 1. "MRD,BOOTROM sleep enable" group.long 0x780++0x7 line.long 0x0 "RCC_SECCFGR0,RCC oscillator secure configuration register0" bitfld.long 0x0 4. "HSESEC,Defines the secure protection of the HSE oscillator configuration bits." "0: HSE configuration bits are accessible by..,1: HSE configuration bits are accessible by secure.." newline bitfld.long 0x0 3. "HSISEC,Defines the secure protection of the HSI oscillator configuration bits." "0: HSI configuration bits are accessible by..,1: HSI configuration bits are accessible by secure.." newline bitfld.long 0x0 2. "MSISEC,Defines the secure protection of the MSI oscillator configuration bits." "0: MSI configuration bits are accessible by..,1: MSI configuration bits are accessible by secure.." newline bitfld.long 0x0 1. "LSESEC,Defines the secure protection of the LSE oscillator configuration bits." "0: LSE configuration bits are accessible by..,1: LSE configuration bits are accessible by secure.." newline bitfld.long 0x0 0. "LSISEC,Defines the secure protection of the LSI oscillator configuration bits." "0: LSI configuration bits are accessible by..,1: LSI configuration bits are accessible by secure.." line.long 0x4 "RCC_PRIVCFGR0,RCC oscillator privilege configuration register0" bitfld.long 0x4 4. "HSEPV,Defines the privilege protection of the HSE oscillator configuration bits." "0: HSE configuration bits are accessible by..,1: HSE configuration bits are accessible by.." newline bitfld.long 0x4 3. "HSIPV,Defines the privilege protection of the HSI oscillator configuration bits." "0: HSI configuration bits are accessible by..,1: HSI configuration bits are accessible by.." newline bitfld.long 0x4 2. "MSIPV,Defines the privilege protection of the MSI oscillator configuration bits." "0: MSI configuration bits are accessible by..,1: MSI configuration bits are accessible by.." newline bitfld.long 0x4 1. "LSEPV,Defines the privilege protection of the LSE oscillator configuration bits." "0: LSE configuration bits are accessible by..,1: LSE configuration bits are accessible by.." newline bitfld.long 0x4 0. "LSIPV,Defines the privilege protection of the LSI oscillator configuration bits." "0: LSI configuration bits are accessible by..,1: LSI configuration bits are accessible by.." wgroup.long 0x788++0x3 line.long 0x0 "RCC_LOCKCFGR0,RCC oscillator lock configuration register0" bitfld.long 0x0 4. "HSELOCK,Defines the lock protection of the HSE oscillator configuration bits." "0: HSE configuration bits are accessible by..,1: HSE configuration bits are accessible by lock.." newline bitfld.long 0x0 3. "HSILOCK,Defines the lock protection of the HSI oscillator configuration bits." "0: HSI configuration bits are accessible by..,1: HSI configuration bits are accessible by lock.." newline bitfld.long 0x0 2. "MSILOCK,Defines the lock protection of the MSI oscillator configuration bits." "0: MSI configuration bits are accessible by..,1: MSI configuration bits are accessible by lock.." newline bitfld.long 0x0 1. "LSELOCK,Defines the lock protection of the LSE oscillator configuration bits." "0: LSE configuration bits are accessible by..,1: LSE configuration bits are accessible by lock.." newline bitfld.long 0x0 0. "LSILOCK,Defines the lock protection of the LSI oscillator configuration bits." "0: LSI configuration bits are accessible by..,1: LSI configuration bits are accessible by lock.." group.long 0x78C++0xB line.long 0x0 "RCC_PUBCFGR0,RCC oscillator public configuration register0" bitfld.long 0x0 4. "HSEPUB,Defines the public protection of the HSE oscillator configuration bits." "0: HSE configuration bits are accessible by..,1: HSE configuration bits are accessible by public.." newline bitfld.long 0x0 3. "HSIPUB,Defines the public protection of the HSI oscillator configuration bits." "0: HSI configuration bits are accessible by..,1: HSI configuration bits are accessible by public.." newline bitfld.long 0x0 2. "MSIPUB,Defines the public protection of the MSI oscillator configuration bits." "0: MSI configuration bits are accessible by..,1: MSI configuration bits are accessible by public.." newline bitfld.long 0x0 1. "LSEPUB,Defines the public protection of the LSE oscillator configuration bits." "0: LSE configuration bits are accessible by..,1: LSE configuration bits are accessible by public.." newline bitfld.long 0x0 0. "LSIPUB,Defines the public protection of the LSI oscillator configuration bits." "0: LSI configuration bits are accessible by..,1: LSI configuration bits are accessible by public.." line.long 0x4 "RCC_SECCFGR1,RCC PLL secure configuration register1" bitfld.long 0x4 3. "PLL4SEC,Defines the secure protection of the PLL4 PLL configuration bits." "0: PLL4 configuration bits are accessible by..,1: PLL4 configuration bits are accessible by secure.." newline bitfld.long 0x4 2. "PLL3SEC,Defines the secure protection of the PLL3 PLL configuration bits." "0: PLL3 configuration bits are accessible by..,1: PLL3 configuration bits are accessible by secure.." newline bitfld.long 0x4 1. "PLL2SEC,Defines the secure protection of the PLL2 PLL configuration bits." "0: PLL2 configuration bits are accessible by..,1: PLL2 configuration bits are accessible by secure.." newline bitfld.long 0x4 0. "PLL1SEC,Defines the secure protection of the PLL1 PLL configuration bits." "0: PLL1 configuration bits are accessible by..,1: PLL1 configuration bits are accessible by secure.." line.long 0x8 "RCC_PRIVCFGR1,RCC PLL privilege configuration register1" bitfld.long 0x8 3. "PLL4PV,Defines the privilege protection of the PLL4 PLL configuration bits." "0: PLL4 configuration bits are accessible by..,1: PLL4 configuration bits are accessible by.." newline bitfld.long 0x8 2. "PLL3PV,Defines the privilege protection of the PLL3 PLL configuration bits." "0: PLL3 configuration bits are accessible by..,1: PLL3 configuration bits are accessible by.." newline bitfld.long 0x8 1. "PLL2PV,Defines the privilege protection of the PLL2 PLL configuration bits." "0: PLL2 configuration bits are accessible by..,1: PLL2 configuration bits are accessible by.." newline bitfld.long 0x8 0. "PLL1PV,Defines the privilege protection of the PLL1 PLL configuration bits." "0: PLL1 configuration bits are accessible by..,1: PLL1 configuration bits are accessible by.." wgroup.long 0x798++0x3 line.long 0x0 "RCC_LOCKCFGR1,RCC PLL lock configuration register1" bitfld.long 0x0 3. "PLL4LOCK,Defines the lock protection of the PLL4 PLL configuration bits." "0: PLL4 configuration bits are accessible by..,1: PLL4 configuration bits are accessible by lock.." newline bitfld.long 0x0 2. "PLL3LOCK,Defines the lock protection of the PLL3 PLL configuration bits." "0: PLL3 configuration bits are accessible by..,1: PLL3 configuration bits are accessible by lock.." newline bitfld.long 0x0 1. "PLL2LOCK,Defines the lock protection of the PLL2 PLL configuration bits." "0: PLL2 configuration bits are accessible by..,1: PLL2 configuration bits are accessible by lock.." newline bitfld.long 0x0 0. "PLL1LOCK,Defines the lock protection of the PLL1 PLL configuration bits." "0: PLL1 configuration bits are accessible by..,1: PLL1 configuration bits are accessible by lock.." group.long 0x79C++0xB line.long 0x0 "RCC_PUBCFGR1,RCC PLL public configuration register1" bitfld.long 0x0 3. "PLL4PUB,Defines the public protection of the PLL4 PLL configuration bits." "0: PLL4 configuration bits are accessible by..,1: PLL4 configuration bits are accessible by public.." newline bitfld.long 0x0 2. "PLL3PUB,Defines the public protection of the PLL3 PLL configuration bits." "0: PLL3 configuration bits are accessible by..,1: PLL3 configuration bits are accessible by public.." newline bitfld.long 0x0 1. "PLL2PUB,Defines the public protection of the PLL2 PLL configuration bits." "0: PLL2 configuration bits are accessible by..,1: PLL2 configuration bits are accessible by public.." newline bitfld.long 0x0 0. "PLL1PUB,Defines the public protection of the PLL1 PLL configuration bits." "0: PLL1 configuration bits are accessible by..,1: PLL1 configuration bits are accessible by public.." line.long 0x4 "RCC_SECCFGR2,RCC divider secure configuration register2" bitfld.long 0x4 19. "IC20SEC,Defines the secure protection of the IC20 divider configuration bits." "0: IC20 configuration bits are accessible by..,1: IC20 configuration bits are accessible by secure.." newline bitfld.long 0x4 18. "IC19SEC,Defines the secure protection of the IC19 divider configuration bits." "0: IC19 configuration bits are accessible by..,1: IC19 configuration bits are accessible by secure.." newline bitfld.long 0x4 17. "IC18SEC,Defines the secure protection of the IC18 divider configuration bits." "0: IC18 configuration bits are accessible by..,1: IC18 configuration bits are accessible by secure.." newline bitfld.long 0x4 16. "IC17SEC,Defines the secure protection of the IC17 divider configuration bits." "0: IC17 configuration bits are accessible by..,1: IC17 configuration bits are accessible by secure.." newline bitfld.long 0x4 15. "IC16SEC,Defines the secure protection of the IC16 divider configuration bits." "0: IC16 configuration bits are accessible by..,1: IC16 configuration bits are accessible by secure.." newline bitfld.long 0x4 14. "IC15SEC,Defines the secure protection of the IC15 divider configuration bits." "0: IC15 configuration bits are accessible by..,1: IC15 configuration bits are accessible by secure.." newline bitfld.long 0x4 13. "IC14SEC,Defines the secure protection of the IC14 divider configuration bits." "0: IC14 configuration bits are accessible by..,1: IC14 configuration bits are accessible by secure.." newline bitfld.long 0x4 12. "IC13SEC,Defines the secure protection of the IC13 divider configuration bits." "0: IC13 configuration bits are accessible by..,1: IC13 configuration bits are accessible by secure.." newline bitfld.long 0x4 11. "IC12SEC,Defines the secure protection of the IC12 divider configuration bits." "0: IC12 configuration bits are accessible by..,1: IC12 configuration bits are accessible by secure.." newline bitfld.long 0x4 10. "IC11SEC,Defines the secure protection of the IC11 divider configuration bits." "0: IC11 configuration bits are accessible by..,1: IC11 configuration bits are accessible by secure.." newline bitfld.long 0x4 9. "IC10SEC,Defines the secure protection of the IC10 divider configuration bits." "0: IC10 configuration bits are accessible by..,1: IC10 configuration bits are accessible by secure.." newline bitfld.long 0x4 8. "IC9SEC,Defines the secure protection of the IC9 divider configuration bits." "0: IC9 configuration bits are accessible by..,1: IC9 configuration bits are accessible by secure.." newline bitfld.long 0x4 7. "IC8SEC,Defines the secure protection of the IC8 divider configuration bits." "0: IC8 configuration bits are accessible by..,1: IC8 configuration bits are accessible by secure.." newline bitfld.long 0x4 6. "IC7SEC,Defines the secure protection of the IC7 divider configuration bits." "0: IC7 configuration bits are accessible by..,1: IC7 configuration bits are accessible by secure.." newline bitfld.long 0x4 5. "IC6SEC,Defines the secure protection of the IC6 divider configuration bits." "0: IC6 configuration bits are accessible by..,1: IC6 configuration bits are accessible by secure.." newline bitfld.long 0x4 4. "IC5SEC,Defines the secure protection of the IC5 divider configuration bits." "0: IC5 configuration bits are accessible by..,1: IC5 configuration bits are accessible by secure.." newline bitfld.long 0x4 3. "IC4SEC,Defines the secure protection of the IC4 divider configuration bits." "0: IC4 configuration bits are accessible by..,1: IC4 configuration bits are accessible by secure.." newline bitfld.long 0x4 2. "IC3SEC,Defines the secure protection of the IC3 divider configuration bits." "0: IC3 configuration bits are accessible by..,1: IC3 configuration bits are accessible by secure.." newline bitfld.long 0x4 1. "IC2SEC,Defines the secure protection of the IC2 divider configuration bits." "0: IC2 configuration bits are accessible by..,1: IC2 configuration bits are accessible by secure.." newline bitfld.long 0x4 0. "IC1SEC,Defines the secure protection of the IC1 divider configuration bits." "0: IC1 configuration bits are accessible by..,1: IC1 configuration bits are accessible by secure.." line.long 0x8 "RCC_PRIVCFGR2,RCC divider privilege configuration register2" bitfld.long 0x8 19. "IC20PV,Defines the privilege protection of the IC20 divider configuration bits." "0: IC20 configuration bits are accessible by..,1: IC20 configuration bits are accessible by.." newline bitfld.long 0x8 18. "IC19PV,Defines the privilege protection of the IC19 divider configuration bits." "0: IC19 configuration bits are accessible by..,1: IC19 configuration bits are accessible by.." newline bitfld.long 0x8 17. "IC18PV,Defines the privilege protection of the IC18 divider configuration bits." "0: IC18 configuration bits are accessible by..,1: IC18 configuration bits are accessible by.." newline bitfld.long 0x8 16. "IC17PV,Defines the privilege protection of the IC17 divider configuration bits." "0: IC17 configuration bits are accessible by..,1: IC17 configuration bits are accessible by.." newline bitfld.long 0x8 15. "IC16PV,Defines the privilege protection of the IC16 divider configuration bits." "0: IC16 configuration bits are accessible by..,1: IC16 configuration bits are accessible by.." newline bitfld.long 0x8 14. "IC15PV,Defines the privilege protection of the IC15 divider configuration bits." "0: IC15 configuration bits are accessible by..,1: IC15 configuration bits are accessible by.." newline bitfld.long 0x8 13. "IC14PV,Defines the privilege protection of the IC14 divider configuration bits." "0: IC14 configuration bits are accessible by..,1: IC14 configuration bits are accessible by.." newline bitfld.long 0x8 12. "IC13PV,Defines the privilege protection of the IC13 divider configuration bits." "0: IC13 configuration bits are accessible by..,1: IC13 configuration bits are accessible by.." newline bitfld.long 0x8 11. "IC12PV,Defines the privilege protection of the IC12 divider configuration bits." "0: IC12 configuration bits are accessible by..,1: IC12 configuration bits are accessible by.." newline bitfld.long 0x8 10. "IC11PV,Defines the privilege protection of the IC11 divider configuration bits." "0: IC11 configuration bits are accessible by..,1: IC11 configuration bits are accessible by.." newline bitfld.long 0x8 9. "IC10PV,Defines the privilege protection of the IC10 divider configuration bits." "0: IC10 configuration bits are accessible by..,1: IC10 configuration bits are accessible by.." newline bitfld.long 0x8 8. "IC9PV,Defines the privilege protection of the IC9 divider configuration bits." "0: IC9 configuration bits are accessible by..,1: IC9 configuration bits are accessible by.." newline bitfld.long 0x8 7. "IC8PV,Defines the privilege protection of the IC8 divider configuration bits." "0: IC8 configuration bits are accessible by..,1: IC8 configuration bits are accessible by.." newline bitfld.long 0x8 6. "IC7PV,Defines the privilege protection of the IC7 divider configuration bits." "0: IC7 configuration bits are accessible by..,1: IC7 configuration bits are accessible by.." newline bitfld.long 0x8 5. "IC6PV,Defines the privilege protection of the IC6 divider configuration bits." "0: IC6 configuration bits are accessible by..,1: IC6 configuration bits are accessible by.." newline bitfld.long 0x8 4. "IC5PV,Defines the privilege protection of the IC5 divider configuration bits." "0: IC5 configuration bits are accessible by..,1: IC5 configuration bits are accessible by.." newline bitfld.long 0x8 3. "IC4PV,Defines the privilege protection of the IC4 divider configuration bits." "0: IC4 configuration bits are accessible by..,1: IC4 configuration bits are accessible by.." newline bitfld.long 0x8 2. "IC3PV,Defines the privilege protection of the IC3 divider configuration bits." "0: IC3 configuration bits are accessible by..,1: IC3 configuration bits are accessible by.." newline bitfld.long 0x8 1. "IC2PV,Defines the privilege protection of the IC2 divider configuration bits." "0: IC2 configuration bits are accessible by..,1: IC2 configuration bits are accessible by.." newline bitfld.long 0x8 0. "IC1PV,Defines the privilege protection of the IC1 divider configuration bits." "0: IC1 configuration bits are accessible by..,1: IC1 configuration bits are accessible by.." wgroup.long 0x7A8++0x3 line.long 0x0 "RCC_LOCKCFGR2,RCC divider lock configuration register2" bitfld.long 0x0 19. "IC20LOCK,Defines the lock protection of the IC20 divider configuration bits." "0: IC20 configuration bits are accessible by..,1: IC20 configuration bits are accessible by lock.." newline bitfld.long 0x0 18. "IC19LOCK,Defines the lock protection of the IC19 divider configuration bits." "0: IC19 configuration bits are accessible by..,1: IC19 configuration bits are accessible by lock.." newline bitfld.long 0x0 17. "IC18LOCK,Defines the lock protection of the IC18 divider configuration bits." "0: IC18 configuration bits are accessible by..,1: IC18 configuration bits are accessible by lock.." newline bitfld.long 0x0 16. "IC17LOCK,Defines the lock protection of the IC17 divider configuration bits." "0: IC17 configuration bits are accessible by..,1: IC17 configuration bits are accessible by lock.." newline bitfld.long 0x0 15. "IC16LOCK,Defines the lock protection of the IC16 divider configuration bits." "0: IC16 configuration bits are accessible by..,1: IC16 configuration bits are accessible by lock.." newline bitfld.long 0x0 14. "IC15LOCK,Defines the lock protection of the IC15 divider configuration bits." "0: IC15 configuration bits are accessible by..,1: IC15 configuration bits are accessible by lock.." newline bitfld.long 0x0 13. "IC14LOCK,Defines the lock protection of the IC14 divider configuration bits." "0: IC14 configuration bits are accessible by..,1: IC14 configuration bits are accessible by lock.." newline bitfld.long 0x0 12. "IC13LOCK,Defines the lock protection of the IC13 divider configuration bits." "0: IC13 configuration bits are accessible by..,1: IC13 configuration bits are accessible by lock.." newline bitfld.long 0x0 11. "IC12LOCK,Defines the lock protection of the IC12 divider configuration bits." "0: IC12 configuration bits are accessible by..,1: IC12 configuration bits are accessible by lock.." newline bitfld.long 0x0 10. "IC11LOCK,Defines the lock protection of the IC11 divider configuration bits." "0: IC11 configuration bits are accessible by..,1: IC11 configuration bits are accessible by lock.." newline bitfld.long 0x0 9. "IC10LOCK,Defines the lock protection of the IC10 divider configuration bits." "0: IC10 configuration bits are accessible by..,1: IC10 configuration bits are accessible by lock.." newline bitfld.long 0x0 8. "IC9LOCK,Defines the lock protection of the IC9 divider configuration bits." "0: IC9 configuration bits are accessible by..,1: IC9 configuration bits are accessible by lock.." newline bitfld.long 0x0 7. "IC8LOCK,Defines the lock protection of the IC8 divider configuration bits." "0: IC8 configuration bits are accessible by..,1: IC8 configuration bits are accessible by lock.." newline bitfld.long 0x0 6. "IC7LOCK,Defines the lock protection of the IC7 divider configuration bits." "0: IC7 configuration bits are accessible by..,1: IC7 configuration bits are accessible by lock.." newline bitfld.long 0x0 5. "IC6LOCK,Defines the lock protection of the IC6 divider configuration bits." "0: IC6 configuration bits are accessible by..,1: IC6 configuration bits are accessible by lock.." newline bitfld.long 0x0 4. "IC5LOCK,Defines the lock protection of the IC5 divider configuration bits." "0: IC5 configuration bits are accessible by..,1: IC5 configuration bits are accessible by lock.." newline bitfld.long 0x0 3. "IC4LOCK,Defines the lock protection of the IC4 divider configuration bits." "0: IC4 configuration bits are accessible by..,1: IC4 configuration bits are accessible by lock.." newline bitfld.long 0x0 2. "IC3LOCK,Defines the lock protection of the IC3 divider configuration bits." "0: IC3 configuration bits are accessible by..,1: IC3 configuration bits are accessible by lock.." newline bitfld.long 0x0 1. "IC2LOCK,Defines the lock protection of the IC2 divider configuration bits." "0: IC2 configuration bits are accessible by..,1: IC2 configuration bits are accessible by lock.." newline bitfld.long 0x0 0. "IC1LOCK,Defines the lock protection of the IC1 divider configuration bits." "0: IC1 configuration bits are accessible by..,1: IC1 configuration bits are accessible by lock.." group.long 0x7AC++0xB line.long 0x0 "RCC_PUBCFGR2,RCC divider public configuration register2" bitfld.long 0x0 19. "IC20PUB,Defines the public protection of the IC20 divider configuration bits." "0: IC20 configuration bits are accessible by..,1: IC20 configuration bits are accessible by public.." newline bitfld.long 0x0 18. "IC19PUB,Defines the public protection of the IC19 divider configuration bits." "0: IC19 configuration bits are accessible by..,1: IC19 configuration bits are accessible by public.." newline bitfld.long 0x0 17. "IC18PUB,Defines the public protection of the IC18 divider configuration bits." "0: IC18 configuration bits are accessible by..,1: IC18 configuration bits are accessible by public.." newline bitfld.long 0x0 16. "IC17PUB,Defines the public protection of the IC17 divider configuration bits." "0: IC17 configuration bits are accessible by..,1: IC17 configuration bits are accessible by public.." newline bitfld.long 0x0 15. "IC16PUB,Defines the public protection of the IC16 divider configuration bits." "0: IC16 configuration bits are accessible by..,1: IC16 configuration bits are accessible by public.." newline bitfld.long 0x0 14. "IC15PUB,Defines the public protection of the IC15 divider configuration bits." "0: IC15 configuration bits are accessible by..,1: IC15 configuration bits are accessible by public.." newline bitfld.long 0x0 13. "IC14PUB,Defines the public protection of the IC14 divider configuration bits." "0: IC14 configuration bits are accessible by..,1: IC14 configuration bits are accessible by public.." newline bitfld.long 0x0 12. "IC13PUB,Defines the public protection of the IC13 divider configuration bits." "0: IC13 configuration bits are accessible by..,1: IC13 configuration bits are accessible by public.." newline bitfld.long 0x0 11. "IC12PUB,Defines the public protection of the IC12 divider configuration bits." "0: IC12 configuration bits are accessible by..,1: IC12 configuration bits are accessible by public.." newline bitfld.long 0x0 10. "IC11PUB,Defines the public protection of the IC11 divider configuration bits." "0: IC11 configuration bits are accessible by..,1: IC11 configuration bits are accessible by public.." newline bitfld.long 0x0 9. "IC10PUB,Defines the public protection of the IC10 divider configuration bits." "0: IC10 configuration bits are accessible by..,1: IC10 configuration bits are accessible by public.." newline bitfld.long 0x0 8. "IC9PUB,Defines the public protection of the IC9 divider configuration bits." "0: IC9 configuration bits are accessible by..,1: IC9 configuration bits are accessible by public.." newline bitfld.long 0x0 7. "IC8PUB,Defines the public protection of the IC8 divider configuration bits." "0: IC8 configuration bits are accessible by..,1: IC8 configuration bits are accessible by public.." newline bitfld.long 0x0 6. "IC7PUB,Defines the public protection of the IC7 divider configuration bits." "0: IC7 configuration bits are accessible by..,1: IC7 configuration bits are accessible by public.." newline bitfld.long 0x0 5. "IC6PUB,Defines the public protection of the IC6 divider configuration bits." "0: IC6 configuration bits are accessible by..,1: IC6 configuration bits are accessible by public.." newline bitfld.long 0x0 4. "IC5PUB,Defines the public protection of the IC5 divider configuration bits." "0: IC5 configuration bits are accessible by..,1: IC5 configuration bits are accessible by public.." newline bitfld.long 0x0 3. "IC4PUB,Defines the public protection of the IC4 divider configuration bits." "0: IC4 configuration bits are accessible by..,1: IC4 configuration bits are accessible by public.." newline bitfld.long 0x0 2. "IC3PUB,Defines the public protection of the IC3 divider configuration bits." "0: IC3 configuration bits are accessible by..,1: IC3 configuration bits are accessible by public.." newline bitfld.long 0x0 1. "IC2PUB,Defines the public protection of the IC2 divider configuration bits." "0: IC2 configuration bits are accessible by..,1: IC2 configuration bits are accessible by public.." newline bitfld.long 0x0 0. "IC1PUB,Defines the public protection of the IC1 divider configuration bits." "0: IC1 configuration bits are accessible by..,1: IC1 configuration bits are accessible by public.." line.long 0x4 "RCC_SECCFGR3,RCC system secure configuration register3" bitfld.long 0x4 6. "DFTSEC,Defines the secure protection of the DFT system configuration bits." "0: DFT configuration bits are accessible by..,1: DFT configuration bits are accessible by secure.." newline bitfld.long 0x4 5. "RSTSEC,Defines the secure protection of the RST system configuration bits." "0: RST configuration bits are accessible by..,1: RST configuration bits are accessible by secure.." newline bitfld.long 0x4 4. "INTSEC,Defines the secure protection of the INT system configuration bits." "0: INT configuration bits are accessible by..,1: INT configuration bits are accessible by secure.." newline bitfld.long 0x4 3. "PERSEC,Defines the secure protection of the PER system configuration bits." "0: PER configuration bits are accessible by..,1: PER configuration bits are accessible by secure.." newline bitfld.long 0x4 2. "BUSSEC,Defines the secure protection of the BUS system configuration bits." "0: BUS configuration bits are accessible by..,1: BUS configuration bits are accessible by secure.." newline bitfld.long 0x4 1. "SYSSEC,Defines the secure protection of the SYS system configuration bits." "0: SYS configuration bits are accessible by..,1: SYS configuration bits are accessible by secure.." newline bitfld.long 0x4 0. "MODSEC,Defines the secure protection of the MOD system configuration bits." "0: MOD configuration bits are accessible by..,1: MOD configuration bits are accessible by secure.." line.long 0x8 "RCC_PRIVCFGR3,RCC system privilege configuration register3" bitfld.long 0x8 6. "DFTPV,Defines the privilege protection of the DFT system configuration bits." "0: DFT configuration bits are accessible by..,1: DFT configuration bits are accessible by.." newline bitfld.long 0x8 5. "RSTPV,Defines the privilege protection of the RST system configuration bits." "0: RST configuration bits are accessible by..,1: RST configuration bits are accessible by.." newline bitfld.long 0x8 4. "INTPV,Defines the privilege protection of the INT system configuration bits." "0: INT configuration bits are accessible by..,1: INT configuration bits are accessible by.." newline bitfld.long 0x8 3. "PERPV,Defines the privilege protection of the PER system configuration bits." "0: PER configuration bits are accessible by..,1: PER configuration bits are accessible by.." newline bitfld.long 0x8 2. "BUSPV,Defines the privilege protection of the BUS system configuration bits." "0: BUS configuration bits are accessible by..,1: BUS configuration bits are accessible by.." newline bitfld.long 0x8 1. "SYSPV,Defines the privilege protection of the SYS system configuration bits." "0: SYS configuration bits are accessible by..,1: SYS configuration bits are accessible by.." newline bitfld.long 0x8 0. "MODPV,Defines the privilege protection of the MOD system configuration bits." "0: MOD configuration bits are accessible by..,1: MOD configuration bits are accessible by.." wgroup.long 0x7B8++0x3 line.long 0x0 "RCC_LOCKCFGR3,RCC system lock configuration register3" bitfld.long 0x0 6. "DFTLOCK,Defines the lock protection of the DFT system configuration bits." "0: DFT configuration bits are accessible by..,1: DFT configuration bits are accessible by lock.." newline bitfld.long 0x0 5. "RSTLOCK,Defines the lock protection of the RST system configuration bits." "0: RST configuration bits are accessible by..,1: RST configuration bits are accessible by lock.." newline bitfld.long 0x0 4. "INTLOCK,Defines the lock protection of the INT system configuration bits." "0: INT configuration bits are accessible by..,1: INT configuration bits are accessible by lock.." newline bitfld.long 0x0 3. "PERLOCK,Defines the lock protection of the PER system configuration bits." "0: PER configuration bits are accessible by..,1: PER configuration bits are accessible by lock.." newline bitfld.long 0x0 2. "BUSLOCK,Defines the lock protection of the BUS system configuration bits." "0: BUS configuration bits are accessible by..,1: BUS configuration bits are accessible by lock.." newline bitfld.long 0x0 1. "SYSLOCK,Defines the lock protection of the SYS system configuration bits." "0: SYS configuration bits are accessible by..,1: SYS configuration bits are accessible by lock.." newline bitfld.long 0x0 0. "MODLOCK,Defines the lock protection of the MOD system configuration bits." "0: MOD configuration bits are accessible by..,1: MOD configuration bits are accessible by lock.." group.long 0x7BC++0xB line.long 0x0 "RCC_PUBCFGR3,RCC system public configuration register3" bitfld.long 0x0 6. "DFTPUB,Defines the public protection of the DFT system configuration bits." "0: DFT configuration bits are accessible by..,1: DFT configuration bits are accessible by public.." newline bitfld.long 0x0 5. "RSTPUB,Defines the public protection of the RST system configuration bits." "0: RST configuration bits are accessible by..,1: RST configuration bits are accessible by public.." newline bitfld.long 0x0 4. "INTPUB,Defines the public protection of the INT system configuration bits." "0: INT configuration bits are accessible by..,1: INT configuration bits are accessible by public.." newline bitfld.long 0x0 3. "PERPUB,Defines the public protection of the PER system configuration bits." "0: PER configuration bits are accessible by..,1: PER configuration bits are accessible by public.." newline bitfld.long 0x0 2. "BUSPUB,Defines the public protection of the BUS system configuration bits." "0: BUS configuration bits are accessible by..,1: BUS configuration bits are accessible by public.." newline bitfld.long 0x0 1. "SYSPUB,Defines the public protection of the SYS system configuration bits." "0: SYS configuration bits are accessible by..,1: SYS configuration bits are accessible by public.." newline bitfld.long 0x0 0. "MODPUB,Defines the public protection of the MOD system configuration bits." "0: MOD configuration bits are accessible by..,1: MOD configuration bits are accessible by public.." line.long 0x4 "RCC_SECCFGR4,RCC bus secure configuration register4" bitfld.long 0x4 13. "NOCSEC,Defines the secure protection of the NOC bus configuration bits." "0: NOC configuration bits are accessible by..,1: NOC configuration bits are accessible by secure.." newline bitfld.long 0x4 12. "APB5SEC,Defines the secure protection of the APB5 bus configuration bits." "0: APB5 configuration bits are accessible by..,1: APB5 configuration bits are accessible by secure.." newline bitfld.long 0x4 11. "APB4SEC,Defines the secure protection of the APB4 bus configuration bits." "0: APB4 configuration bits are accessible by..,1: APB4 configuration bits are accessible by secure.." newline bitfld.long 0x4 10. "APB3SEC,Defines the secure protection of the APB3 bus configuration bits." "0: APB3 configuration bits are accessible by..,1: APB3 configuration bits are accessible by secure.." newline bitfld.long 0x4 9. "APB2SEC,Defines the secure protection of the APB2 bus configuration bits." "0: APB2 configuration bits are accessible by..,1: APB2 configuration bits are accessible by secure.." newline bitfld.long 0x4 8. "APB1SEC,Defines the secure protection of the APB1 bus configuration bits." "0: APB1 configuration bits are accessible by..,1: APB1 configuration bits are accessible by secure.." newline bitfld.long 0x4 7. "AHB5SEC,Defines the secure protection of the AHB5 bus configuration bits." "0: AHB5 configuration bits are accessible by..,1: AHB5 configuration bits are accessible by secure.." newline bitfld.long 0x4 6. "AHB4SEC,Defines the secure protection of the AHB4 bus configuration bits." "0: AHB4 configuration bits are accessible by..,1: AHB4 configuration bits are accessible by secure.." newline bitfld.long 0x4 5. "AHB3SEC,Defines the secure protection of the AHB3 bus configuration bits." "0: AHB3 configuration bits are accessible by..,1: AHB3 configuration bits are accessible by secure.." newline bitfld.long 0x4 4. "AHB2SEC,Defines the secure protection of the AHB2 bus configuration bits." "0: AHB2 configuration bits are accessible by..,1: AHB2 configuration bits are accessible by secure.." newline bitfld.long 0x4 3. "AHB1SEC,Defines the secure protection of the AHB1 bus configuration bits." "0: AHB1 configuration bits are accessible by..,1: AHB1 configuration bits are accessible by secure.." newline bitfld.long 0x4 2. "AHBMSEC,Defines the secure protection of the AHBM bus configuration bits." "0: AHBM configuration bits are accessible by..,1: AHBM configuration bits are accessible by secure.." newline bitfld.long 0x4 1. "ACLKNCSEC,Defines the secure protection of the ACLKNC bus configuration bits." "0: ACLKNC configuration bits are accessible by..,1: ACLKNC configuration bits are accessible by.." newline bitfld.long 0x4 0. "ACLKNSEC,Defines the secure protection of the ACLKN bus configuration bits." "0: ACLKN configuration bits are accessible by..,1: ACLKN configuration bits are accessible by.." line.long 0x8 "RCC_PRIVCFGR4,RCC bus privilege configuration register4" bitfld.long 0x8 13. "NOCPV,Defines the privilege protection of the NOC bus configuration bits." "0: NOC configuration bits are accessible by..,1: NOC configuration bits are accessible by.." newline bitfld.long 0x8 12. "APB5PV,Defines the privilege protection of the APB5 bus configuration bits." "0: APB5 configuration bits are accessible by..,1: APB5 configuration bits are accessible by.." newline bitfld.long 0x8 11. "APB4PV,Defines the privilege protection of the APB4 bus configuration bits." "0: APB4 configuration bits are accessible by..,1: APB4 configuration bits are accessible by.." newline bitfld.long 0x8 10. "APB3PV,Defines the privilege protection of the APB3 bus configuration bits." "0: APB3 configuration bits are accessible by..,1: APB3 configuration bits are accessible by.." newline bitfld.long 0x8 9. "APB2PV,Defines the privilege protection of the APB2 bus configuration bits." "0: APB2 configuration bits are accessible by..,1: APB2 configuration bits are accessible by.." newline bitfld.long 0x8 8. "APB1PV,Defines the privilege protection of the APB1 bus configuration bits." "0: APB1 configuration bits are accessible by..,1: APB1 configuration bits are accessible by.." newline bitfld.long 0x8 7. "AHB5PV,Defines the privilege protection of the AHB5 bus configuration bits." "0: AHB5 configuration bits are accessible by..,1: AHB5 configuration bits are accessible by.." newline bitfld.long 0x8 6. "AHB4PV,Defines the privilege protection of the AHB4 bus configuration bits." "0: AHB4 configuration bits are accessible by..,1: AHB4 configuration bits are accessible by.." newline bitfld.long 0x8 5. "AHB3PV,Defines the privilege protection of the AHB3 bus configuration bits." "0: AHB3 configuration bits are accessible by..,1: AHB3 configuration bits are accessible by.." newline bitfld.long 0x8 4. "AHB2PV,Defines the privilege protection of the AHB2 bus configuration bits." "0: AHB2 configuration bits are accessible by..,1: AHB2 configuration bits are accessible by.." newline bitfld.long 0x8 3. "AHB1PV,Defines the privilege protection of the AHB1 bus configuration bits." "0: AHB1 configuration bits are accessible by..,1: AHB1 configuration bits are accessible by.." newline bitfld.long 0x8 2. "AHBMPV,Defines the privilege protection of the AHBM bus configuration bits." "0: AHBM configuration bits are accessible by..,1: AHBM configuration bits are accessible by.." newline bitfld.long 0x8 1. "ACLKNCPV,Defines the privilege protection of the ACLKNC bus configuration bits." "0: ACLKNC configuration bits are accessible by..,1: ACLKNC configuration bits are accessible by.." newline bitfld.long 0x8 0. "ACLKNPV,Defines the privilege protection of the ACLKN bus configuration bits." "0: ACLKN configuration bits are accessible by..,1: ACLKN configuration bits are accessible by.." wgroup.long 0x7C8++0x3 line.long 0x0 "RCC_LOCKCFGR4,RCC bus lock configuration register4" bitfld.long 0x0 13. "NOCLOCK,Defines the lock protection of the NOC bus configuration bits." "0: NOC configuration bits are accessible by..,1: NOC configuration bits are accessible by lock.." newline bitfld.long 0x0 12. "APB5LOCK,Defines the lock protection of the APB5 bus configuration bits." "0: APB5 configuration bits are accessible by..,1: APB5 configuration bits are accessible by lock.." newline bitfld.long 0x0 11. "APB4LOCK,Defines the lock protection of the APB4 bus configuration bits." "0: APB4 configuration bits are accessible by..,1: APB4 configuration bits are accessible by lock.." newline bitfld.long 0x0 10. "APB3LOCK,Defines the lock protection of the APB3 bus configuration bits." "0: APB3 configuration bits are accessible by..,1: APB3 configuration bits are accessible by lock.." newline bitfld.long 0x0 9. "APB2LOCK,Defines the lock protection of the APB2 bus configuration bits." "0: APB2 configuration bits are accessible by..,1: APB2 configuration bits are accessible by lock.." newline bitfld.long 0x0 8. "APB1LOCK,Defines the lock protection of the APB1 bus configuration bits." "0: APB1 configuration bits are accessible by..,1: APB1 configuration bits are accessible by lock.." newline bitfld.long 0x0 7. "AHB5LOCK,Defines the lock protection of the AHB5 bus configuration bits." "0: AHB5 configuration bits are accessible by..,1: AHB5 configuration bits are accessible by lock.." newline bitfld.long 0x0 6. "AHB4LOCK,Defines the lock protection of the AHB4 bus configuration bits." "0: AHB4 configuration bits are accessible by..,1: AHB4 configuration bits are accessible by lock.." newline bitfld.long 0x0 5. "AHB3LOCK,Defines the lock protection of the AHB3 bus configuration bits." "0: AHB3 configuration bits are accessible by..,1: AHB3 configuration bits are accessible by lock.." newline bitfld.long 0x0 4. "AHB2LOCK,Defines the lock protection of the AHB2 bus configuration bits." "0: AHB2 configuration bits are accessible by..,1: AHB2 configuration bits are accessible by lock.." newline bitfld.long 0x0 3. "AHB1LOCK,Defines the lock protection of the AHB1 bus configuration bits." "0: AHB1 configuration bits are accessible by..,1: AHB1 configuration bits are accessible by lock.." newline bitfld.long 0x0 2. "AHBMLOCK,Defines the lock protection of the AHBM bus configuration bits." "0: AHBM configuration bits are accessible by..,1: AHBM configuration bits are accessible by lock.." newline bitfld.long 0x0 1. "ACLKNCLOCK,Defines the lock protection of the ACLKNC bus configuration bits." "0: ACLKNC configuration bits are accessible by..,1: ACLKNC configuration bits are accessible by lock.." newline bitfld.long 0x0 0. "ACLKNLOCK,Defines the lock protection of the ACLKN bus configuration bits." "0: ACLKN configuration bits are accessible by..,1: ACLKN configuration bits are accessible by lock.." group.long 0x7CC++0x7 line.long 0x0 "RCC_PUBCFGR4,RCC bus public configuration register4" bitfld.long 0x0 13. "NOCPUB,Defines the public protection of the NOC bus configuration bits." "0: NOC configuration bits are accessible by..,1: NOC configuration bits are accessible by public.." newline bitfld.long 0x0 12. "APB5PUB,Defines the public protection of the APB5 bus configuration bits." "0: APB5 configuration bits are accessible by..,1: APB5 configuration bits are accessible by public.." newline bitfld.long 0x0 11. "APB4PUB,Defines the public protection of the APB4 bus configuration bits." "0: APB4 configuration bits are accessible by..,1: APB4 configuration bits are accessible by public.." newline bitfld.long 0x0 10. "APB3PUB,Defines the public protection of the APB3 bus configuration bits." "0: APB3 configuration bits are accessible by..,1: APB3 configuration bits are accessible by public.." newline bitfld.long 0x0 9. "APB2PUB,Defines the public protection of the APB2 bus configuration bits." "0: APB2 configuration bits are accessible by..,1: APB2 configuration bits are accessible by public.." newline bitfld.long 0x0 8. "APB1PUB,Defines the public protection of the APB1 bus configuration bits." "0: APB1 configuration bits are accessible by..,1: APB1 configuration bits are accessible by public.." newline bitfld.long 0x0 7. "AHB5PUB,Defines the public protection of the AHB5 bus configuration bits." "0: AHB5 configuration bits are accessible by..,1: AHB5 configuration bits are accessible by public.." newline bitfld.long 0x0 6. "AHB4PUB,Defines the public protection of the AHB4 bus configuration bits." "0: AHB4 configuration bits are accessible by..,1: AHB4 configuration bits are accessible by public.." newline bitfld.long 0x0 5. "AHB3PUB,Defines the public protection of the AHB3 bus configuration bits." "0: AHB3 configuration bits are accessible by..,1: AHB3 configuration bits are accessible by public.." newline bitfld.long 0x0 4. "AHB2PUB,Defines the public protection of the AHB2 bus configuration bits." "0: AHB2 configuration bits are accessible by..,1: AHB2 configuration bits are accessible by public.." newline bitfld.long 0x0 3. "AHB1PUB,Defines the public protection of the AHB1 bus configuration bits." "0: AHB1 configuration bits are accessible by..,1: AHB1 configuration bits are accessible by public.." newline bitfld.long 0x0 2. "AHBMPUB,Defines the public protection of the AHBM bus configuration bits." "0: AHBM configuration bits are accessible by..,1: AHBM configuration bits are accessible by public.." newline bitfld.long 0x0 1. "ACLKNCPUB,Defines the public protection of the ACLKNC bus configuration bits." "0: ACLKNC configuration bits are accessible by..,1: ACLKNC configuration bits are accessible by.." newline bitfld.long 0x0 0. "ACLKNPUB,Defines the public protection of the ACLKN bus configuration bits." "0: ACLKN configuration bits are accessible by..,1: ACLKN configuration bits are accessible by.." line.long 0x4 "RCC_PUBCFGR5,RCC bus public configuration register4" bitfld.long 0x4 11. "VENCRAMPUB,Defines the public protection of the VENCRAM bus configuration bits." "0: VENCRAM configuration bits are accessible by..,1: VENCRAM configuration bits are accessible by.." newline bitfld.long 0x4 10. "NPUCACHERAMPUB,Defines the public protection of the NPUCACHERAM bus configuration bits." "0: NPUCACHERAM configuration bits are accessible by..,1: NPUCACHERAM configuration bits are accessible by.." newline bitfld.long 0x4 9. "FLEXRAMPUB,Defines the public protection of the FLEXRAM bus configuration bits." "0: FLEXRAM configuration bits are accessible by..,1: FLEXRAM configuration bits are accessible by.." newline bitfld.long 0x4 8. "AXISRAM2PUB,Defines the public protection of the AXISRAM2 bus configuration bits." "0: AXISRAM2 configuration bits are accessible by..,1: AXISRAM2 configuration bits are accessible by.." newline bitfld.long 0x4 7. "AXISRAM1PUB,Defines the public protection of the AXISRAM1 bus configuration bits." "0: AXISRAM1 configuration bits are accessible by..,1: AXISRAM1 configuration bits are accessible by.." newline bitfld.long 0x4 6. "BKPSRAMPUB,Defines the public protection of the BKPSRAM bus configuration bits." "0: BKPSRAM configuration bits are accessible by..,1: BKPSRAM configuration bits are accessible by.." newline bitfld.long 0x4 5. "AHBSRAM2PUB,Defines the public protection of the AHBSRAM2 bus configuration bits." "0: AHBSRAM2 configuration bits are accessible by..,1: AHBSRAM2 configuration bits are accessible by.." newline bitfld.long 0x4 4. "AHBSRAM1PUB,Defines the public protection of the AHBSRAM1 bus configuration bits." "0: AHBSRAM1 configuration bits are accessible by..,1: AHBSRAM1 configuration bits are accessible by.." newline bitfld.long 0x4 3. "AXISRAM6PUB,Defines the public protection of the AXISRAM6 bus configuration bits." "0: AXISRAM6 configuration bits are accessible by..,1: AXISRAM6 configuration bits are accessible by.." newline bitfld.long 0x4 2. "AXISRAM5PUB,Defines the public protection of the AXISRAM5 bus configuration bits." "0: AXISRAM5 configuration bits are accessible by..,1: AXISRAM5 configuration bits are accessible by.." newline bitfld.long 0x4 1. "AXISRAM4PUB,Defines the public protection of the AXISRAM4 bus configuration bits." "0: AXISRAM4 configuration bits are accessible by..,1: AXISRAM4 configuration bits are accessible by.." newline bitfld.long 0x4 0. "AXISRAM3PUB,Defines the public protection of the AXISRAM3 bus configuration bits." "0: AXISRAM3 configuration bits are accessible by..,1: AXISRAM3 configuration bits are accessible by.." wgroup.long 0x800++0x3 line.long 0x0 "RCC_CSR,RCC control set register" bitfld.long 0x0 11. "PLL4ONS,PLL4 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 10. "PLL3ONS,PLL3 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 9. "PLL2ONS,PLL2 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 8. "PLL1ONS,PLL1 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 4. "HSEONS,HSE oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 3. "HSIONS,HSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 2. "MSIONS,MSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 1. "LSEONS,LSE oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 0. "LSIONS,LSI oscillator enable in Run/Sleep mode." "0,1" wgroup.long 0x808++0x3 line.long 0x0 "RCC_STOPCSR,RCC Stop configuration register" bitfld.long 0x0 1. "HSISTOPENS,HSISTOPENS" "0,1" newline bitfld.long 0x0 0. "MSISTOPENS,MSISTOPENS" "0,1" wgroup.long 0xA04++0x2B line.long 0x0 "RCC_BUSRSTSR,RCC bus reset set register" bitfld.long 0x0 13. "NOCRSTS,NOC reset" "0,1" newline bitfld.long 0x0 12. "APB5RSTS,APB5 reset" "0,1" newline bitfld.long 0x0 11. "APB4RSTS,APB4 reset" "0,1" newline bitfld.long 0x0 10. "APB3RSTS,APB3 reset" "0,1" newline bitfld.long 0x0 9. "APB2RSTS,APB2 reset" "0,1" newline bitfld.long 0x0 8. "APB1RSTS,APB1 reset" "0,1" newline bitfld.long 0x0 7. "AHB5RSTS,AHB5 reset" "0,1" newline bitfld.long 0x0 6. "AHB4RSTS,AHB4 reset" "0,1" newline bitfld.long 0x0 5. "AHB3RSTS,AHB3 reset" "0,1" newline bitfld.long 0x0 4. "AHB2RSTS,AHB2 reset" "0,1" newline bitfld.long 0x0 3. "AHB1RSTS,AHB1 reset" "0,1" newline bitfld.long 0x0 2. "AHBMRSTS,AHBM reset" "0,1" newline bitfld.long 0x0 0. "ACLKNRSTS,ACLKN reset" "0,1" line.long 0x4 "RCC_MISCRSTSR,RCC miscellaneous reset register" bitfld.long 0x4 8. "SDMMC2DLLRSTS,SDMMC2DLL reset" "0,1" newline bitfld.long 0x4 7. "SDMMC1DLLRSTS,SDMMC1DLL reset" "0,1" newline bitfld.long 0x4 5. "XSPIPHY2RSTS,XSPIPHY2 reset" "0,1" newline bitfld.long 0x4 4. "XSPIPHY1RSTS,XSPIPHY1 reset" "0,1" newline bitfld.long 0x4 0. "DBGRSTS,DBG reset" "0,1" line.long 0x8 "RCC_MEMRSTSR,RCC memory reset register" bitfld.long 0x8 12. "BOOTROMRSTS,BOOTROM reset" "0,1" newline bitfld.long 0x8 11. "VENCRAMRSTS,VENCRAM reset" "0,1" newline bitfld.long 0x8 10. "NPUCACHERAMRSTS,NPUCACHERAM reset" "0,1" newline bitfld.long 0x8 9. "FLEXRAMRSTS,FLEXRAM reset" "0,1" newline bitfld.long 0x8 8. "AXISRAM2RSTS,AXISRAM2 reset" "0,1" newline bitfld.long 0x8 7. "AXISRAM1RSTS,AXISRAM1 reset" "0,1" newline bitfld.long 0x8 5. "AHBSRAM2RSTS,AHBSRAM2 reset" "0,1" newline bitfld.long 0x8 4. "AHBSRAM1RSTS,AHBSRAM1 reset" "0,1" newline bitfld.long 0x8 3. "AXISRAM6RSTS,AXISRAM6 reset" "0,1" newline bitfld.long 0x8 2. "AXISRAM5RSTS,AXISRAM5 reset" "0,1" newline bitfld.long 0x8 1. "AXISRAM4RSTS,AXISRAM4 reset" "0,1" newline bitfld.long 0x8 0. "AXISRAM3RSTS,AXISRAM3 reset" "0,1" line.long 0xC "RCC_AHB1RSTSR,RCC AHB1 reset register" bitfld.long 0xC 5. "ADC12RSTS,ADC12 reset" "0,1" newline bitfld.long 0xC 4. "GPDMA1RSTS,GPDMA1 reset" "0,1" line.long 0x10 "RCC_AHB2RSTSR,RCC AHB2 reset register" bitfld.long 0x10 17. "ADF1RSTS,ADF1 reset" "0,1" newline bitfld.long 0x10 16. "MDF1RSTS,MDF1 reset" "0,1" newline bitfld.long 0x10 12. "RAMCFGRSTS,RAMCFG reset" "0,1" line.long 0x14 "RCC_AHB3RSTSR,RCC AHB3 reset register" bitfld.long 0x14 10. "IACRSTS,IAC reset" "0,1" newline bitfld.long 0x14 8. "PKARSTS,PKA reset" "0,1" newline bitfld.long 0x14 4. "SAESRSTS,SAES reset" "0,1" newline bitfld.long 0x14 2. "CRYPRSTS,CRYP reset" "0,1" newline bitfld.long 0x14 1. "HASHRSTS,HASH reset" "0,1" newline bitfld.long 0x14 0. "RNGRSTS,RNG reset" "0,1" line.long 0x18 "RCC_AHB4RSTSR,RCC AHB4 reset register" bitfld.long 0x18 19. "CRCRSTS,CRC reset" "0,1" newline bitfld.long 0x18 18. "PWRRSTS,PWR reset" "0,1" newline bitfld.long 0x18 16. "GPIOQRSTS,GPIOQ reset" "0,1" newline bitfld.long 0x18 15. "GPIOPRSTS,GPIOP reset" "0,1" newline bitfld.long 0x18 14. "GPIOORSTS,GPIOO reset" "0,1" newline bitfld.long 0x18 13. "GPIONRSTS,GPION reset" "0,1" newline bitfld.long 0x18 7. "GPIOHRSTS,GPIOH reset" "0,1" newline bitfld.long 0x18 6. "GPIOGRSTS,GPIOG reset" "0,1" newline bitfld.long 0x18 5. "GPIOFRSTS,GPIOF reset" "0,1" newline bitfld.long 0x18 4. "GPIOERSTS,GPIOE reset" "0,1" newline bitfld.long 0x18 3. "GPIODRSTS,GPIOD reset" "0,1" newline bitfld.long 0x18 2. "GPIOCRSTS,GPIOC reset" "0,1" newline bitfld.long 0x18 1. "GPIOBRSTS,GPIOB reset" "0,1" newline bitfld.long 0x18 0. "GPIOARSTS,GPIOA reset" "0,1" line.long 0x1C "RCC_AHB5RSTSR,RCC AHB5 reset register" bitfld.long 0x1C 31. "NPURSTS,NPU reset" "0,1" newline bitfld.long 0x1C 30. "NPUCACHERSTS,NPUCACHE reset" "0,1" newline bitfld.long 0x1C 29. "OTG2RSTS,OTG2 reset" "0,1" newline bitfld.long 0x1C 28. "OTGPHY2RSTS,OTGPHY2 reset" "0,1" newline bitfld.long 0x1C 27. "OTGPHY1RSTS,OTGPHY1 reset" "0,1" newline bitfld.long 0x1C 26. "OTG1RSTS,OTG1 reset" "0,1" newline bitfld.long 0x1C 25. "ETH1RSTS,ETH1 reset" "0,1" newline bitfld.long 0x1C 24. "SYSCFGOTGHSPHY2RSTS,SYSCFGOTGHSPHY2 reset" "0,1" newline bitfld.long 0x1C 23. "SYSCFGOTGHSPHY1RSTS,SYSCFGOTGHSPHY1 reset" "0,1" newline bitfld.long 0x1C 20. "GPURSTS,GPU reset" "0,1" newline bitfld.long 0x1C 19. "GFXMMURSTS,GFXMMU reset" "0,1" newline bitfld.long 0x1C 18. "MCE4RSTS,MCE4 reset" "0,1" newline bitfld.long 0x1C 17. "XSPI3RSTS,XSPI3 reset" "0,1" newline bitfld.long 0x1C 13. "XSPIMRSTS,XSPIM reset" "0,1" newline bitfld.long 0x1C 12. "XSPI2RSTS,XSPI2 reset" "0,1" newline bitfld.long 0x1C 8. "SDMMC1RSTS,SDMMC1 reset" "0,1" newline bitfld.long 0x1C 7. "SDMMC2RSTS,SDMMC2 reset" "0,1" newline bitfld.long 0x1C 6. "PSSIRSTS,PSSI reset" "0,1" newline bitfld.long 0x1C 5. "XSPI1RSTS,XSPI1 reset" "0,1" newline bitfld.long 0x1C 4. "FMCRSTS,FMC reset" "0,1" newline bitfld.long 0x1C 3. "JPEGRSTS,JPEG reset" "0,1" newline bitfld.long 0x1C 1. "DMA2DRSTS,DMA2D reset" "0,1" newline bitfld.long 0x1C 0. "HPDMA1RSTS,HPDMA1 reset" "0,1" line.long 0x20 "RCC_APB1LRSTSR,RCC APB1L reset register" bitfld.long 0x20 31. "UART8RSTS,UART8 reset" "0,1" newline bitfld.long 0x20 30. "UART7RSTS,UART7 reset" "0,1" newline bitfld.long 0x20 25. "I3C2RSTS,I3C2 reset" "0,1" newline bitfld.long 0x20 24. "I3C1RSTS,I3C1 reset" "0,1" newline bitfld.long 0x20 23. "I2C3RSTS,I2C3 reset" "0,1" newline bitfld.long 0x20 22. "I2C2RSTS,I2C2 reset" "0,1" newline bitfld.long 0x20 21. "I2C1RSTS,I2C1 reset" "0,1" newline bitfld.long 0x20 20. "UART5RSTS,UART5 reset" "0,1" newline bitfld.long 0x20 19. "UART4RSTS,UART4 reset" "0,1" newline bitfld.long 0x20 18. "USART3RSTS,USART3 reset" "0,1" newline bitfld.long 0x20 17. "USART2RSTS,USART2 reset" "0,1" newline bitfld.long 0x20 16. "SPDIFRX1RSTS,SPDIFRX1 reset" "0,1" newline bitfld.long 0x20 15. "SPI3RSTS,SPI3 reset" "0,1" newline bitfld.long 0x20 14. "SPI2RSTS,SPI2 reset" "0,1" newline bitfld.long 0x20 13. "TIM11RSTS,TIM11 reset" "0,1" newline bitfld.long 0x20 12. "TIM10RSTS,TIM10 reset" "0,1" newline bitfld.long 0x20 11. "WWDGRSTS,WWDG reset" "0,1" newline bitfld.long 0x20 9. "LPTIM1RSTS,LPTIM1 reset" "0,1" newline bitfld.long 0x20 8. "TIM14RSTS,TIM14 reset" "0,1" newline bitfld.long 0x20 7. "TIM13RSTS,TIM13 reset" "0,1" newline bitfld.long 0x20 6. "TIM12RSTS,TIM12 reset" "0,1" newline bitfld.long 0x20 5. "TIM7RSTS,TIM7 reset" "0,1" newline bitfld.long 0x20 4. "TIM6RSTS,TIM6 reset" "0,1" newline bitfld.long 0x20 3. "TIM5RSTS,TIM5 reset" "0,1" newline bitfld.long 0x20 2. "TIM4RSTS,TIM4 reset" "0,1" newline bitfld.long 0x20 1. "TIM3RSTS,TIM3 reset" "0,1" newline bitfld.long 0x20 0. "TIM2RSTS,TIM2 reset" "0,1" line.long 0x24 "RCC_APB1HRSTSR,RCC APB1H reset register" bitfld.long 0x24 18. "UCPD1RSTS,UCPD1 reset" "0,1" newline bitfld.long 0x24 8. "FDCANRSTS,FDCAN reset" "0,1" newline bitfld.long 0x24 5. "MDIOSRSTS,MDIOS reset" "0,1" line.long 0x28 "RCC_APB2RSTSR,RCC APB2 reset register" bitfld.long 0x28 22. "SAI2RSTS,SAI2 reset" "0,1" newline bitfld.long 0x28 21. "SAI1RSTS,SAI1 reset" "0,1" newline bitfld.long 0x28 20. "SPI5RSTS,SPI5 reset" "0,1" newline bitfld.long 0x28 19. "TIM9RSTS,TIM9 reset" "0,1" newline bitfld.long 0x28 18. "TIM17RSTS,TIM17 reset" "0,1" newline bitfld.long 0x28 17. "TIM16RSTS,TIM16 reset" "0,1" newline bitfld.long 0x28 16. "TIM15RSTS,TIM15 reset" "0,1" newline bitfld.long 0x28 15. "TIM18RSTS,TIM18 reset" "0,1" newline bitfld.long 0x28 13. "SPI4RSTS,SPI4 reset" "0,1" newline bitfld.long 0x28 12. "SPI1RSTS,SPI1 reset" "0,1" newline bitfld.long 0x28 7. "USART10RSTS,USART10 reset" "0,1" newline bitfld.long 0x28 6. "UART9RSTS,UART9 reset" "0,1" newline bitfld.long 0x28 5. "USART6RSTS,USART6 reset" "0,1" newline bitfld.long 0x28 4. "USART1RSTS,USART1 reset" "0,1" newline bitfld.long 0x28 1. "TIM8RSTS,TIM8 reset" "0,1" newline bitfld.long 0x28 0. "TIM1RSTS,TIM1 reset" "0,1" wgroup.long 0xA34++0x8B line.long 0x0 "RCC_APB4LRSTSR,RCC APB4L reset register" bitfld.long 0x0 31. "SERFRSTS,SERF reset" "0,1" newline bitfld.long 0x0 23. "R2GNPURSTS,R2GNPU reset" "0,1" newline bitfld.long 0x0 22. "R2GRETRSTS,R2GRET reset" "0,1" newline bitfld.long 0x0 16. "RTCRSTS,RTC reset" "0,1" newline bitfld.long 0x0 15. "VREFBUFRSTS,VREFBUF reset" "0,1" newline bitfld.long 0x0 12. "LPTIM5RSTS,LPTIM5 reset" "0,1" newline bitfld.long 0x0 11. "LPTIM4RSTS,LPTIM4 reset" "0,1" newline bitfld.long 0x0 10. "LPTIM3RSTS,LPTIM3 reset" "0,1" newline bitfld.long 0x0 9. "LPTIM2RSTS,LPTIM2 reset" "0,1" newline bitfld.long 0x0 7. "I2C4RSTS,I2C4 reset" "0,1" newline bitfld.long 0x0 5. "SPI6RSTS,SPI6 reset" "0,1" newline bitfld.long 0x0 3. "LPUART1RSTS,LPUART1 reset" "0,1" newline bitfld.long 0x0 2. "HDPRSTS,HDP reset" "0,1" line.long 0x4 "RCC_APB4HRSTSR,RCC APB4H reset register" bitfld.long 0x4 4. "BUSPERFMRSTS,BUSPERFM reset" "0,1" newline bitfld.long 0x4 2. "DTSRSTS,DTS reset" "0,1" newline bitfld.long 0x4 0. "SYSCFGRSTS,SYSCFG reset" "0,1" line.long 0x8 "RCC_APB5RSTSR,RCC APB5 reset register" bitfld.long 0x8 6. "CSIRSTS,CSI reset" "0,1" newline bitfld.long 0x8 5. "VENCRSTS,VENC reset" "0,1" newline bitfld.long 0x8 4. "GFXTIMRSTS,GFXTIM reset" "0,1" newline bitfld.long 0x8 2. "DCMIPPRSTS,DCMIPP reset" "0,1" newline bitfld.long 0x8 1. "LTDCRSTS,LTDC reset" "0,1" line.long 0xC "RCC_DIVENSR,RCC Divider enable register" bitfld.long 0xC 19. "IC20ENS,IC20 enable" "0,1" newline bitfld.long 0xC 18. "IC19ENS,IC19 enable" "0,1" newline bitfld.long 0xC 17. "IC18ENS,IC18 enable" "0,1" newline bitfld.long 0xC 16. "IC17ENS,IC17 enable" "0,1" newline bitfld.long 0xC 15. "IC16ENS,IC16 enable" "0,1" newline bitfld.long 0xC 14. "IC15ENS,IC15 enable" "0,1" newline bitfld.long 0xC 13. "IC14ENS,IC14 enable" "0,1" newline bitfld.long 0xC 12. "IC13ENS,IC13 enable" "0,1" newline bitfld.long 0xC 11. "IC12ENS,IC12 enable" "0,1" newline bitfld.long 0xC 10. "IC11ENS,IC11 enable" "0,1" newline bitfld.long 0xC 9. "IC10ENS,IC10 enable" "0,1" newline bitfld.long 0xC 8. "IC9ENS,IC9 enable" "0,1" newline bitfld.long 0xC 7. "IC8ENS,IC8 enable" "0,1" newline bitfld.long 0xC 6. "IC7ENS,IC7 enable" "0,1" newline bitfld.long 0xC 5. "IC6ENS,IC6 enable" "0,1" newline bitfld.long 0xC 4. "IC5ENS,IC5 enable" "0,1" newline bitfld.long 0xC 3. "IC4ENS,IC4 enable" "0,1" newline bitfld.long 0xC 2. "IC3ENS,IC3 enable" "0,1" newline bitfld.long 0xC 1. "IC2ENS,IC2 enable" "0,1" newline bitfld.long 0xC 0. "IC1ENS,IC1 enable" "0,1" line.long 0x10 "RCC_BUSENSR,RCC bus enable register" bitfld.long 0x10 12. "APB5ENS,APB5 enable" "0,1" newline bitfld.long 0x10 11. "APB4ENS,APB4 enable" "0,1" newline bitfld.long 0x10 10. "APB3ENS,APB3 enable" "0,1" newline bitfld.long 0x10 9. "APB2ENS,APB2 enable" "0,1" newline bitfld.long 0x10 8. "APB1ENS,APB1 enable" "0,1" newline bitfld.long 0x10 7. "AHB5ENS,AHB5 enable" "0,1" newline bitfld.long 0x10 6. "AHB4ENS,AHB4 enable" "0,1" newline bitfld.long 0x10 5. "AHB3ENS,AHB3 enable" "0,1" newline bitfld.long 0x10 4. "AHB2ENS,AHB2 enable" "0,1" newline bitfld.long 0x10 3. "AHB1ENS,AHB1 enable" "0,1" newline bitfld.long 0x10 2. "AHBMENS,AHBM enable" "0,1" newline bitfld.long 0x10 1. "ACLKNCENS,ACLKNC enable" "0,1" newline bitfld.long 0x10 0. "ACLKNENS,ACLKN enable" "0,1" line.long 0x14 "RCC_MISCENSR,RCC miscellaneous enable register" bitfld.long 0x14 6. "PERENS,PER enable" "0,1" newline bitfld.long 0x14 3. "XSPIPHYCOMPENS,XSPIPHYCOMP enable" "0,1" newline bitfld.long 0x14 2. "MCO2ENS,MCO2 enable" "0,1" newline bitfld.long 0x14 1. "MCO1ENS,MCO1 enable" "0,1" newline bitfld.long 0x14 0. "DBGENS,DBG enable" "0,1" line.long 0x18 "RCC_MEMENSR,RCC memory enable register" bitfld.long 0x18 12. "BOOTROMENS,BOOTROM enable" "0,1" newline bitfld.long 0x18 11. "VENCRAMENS,VENCRAM enable" "0,1" newline bitfld.long 0x18 10. "NPUCACHERAMENS,NPUCACHERAM enable" "0,1" newline bitfld.long 0x18 9. "FLEXRAMENS,FLEXRAM enable" "0,1" newline bitfld.long 0x18 8. "AXISRAM2ENS,AXISRAM2 enable" "0,1" newline bitfld.long 0x18 7. "AXISRAM1ENS,AXISRAM1 enable" "0,1" newline bitfld.long 0x18 6. "BKPSRAMENS,BKPSRAM enable" "0,1" newline bitfld.long 0x18 5. "AHBSRAM2ENS,AHBSRAM2 enable" "0,1" newline bitfld.long 0x18 4. "AHBSRAM1ENS,AHBSRAM1 enable" "0,1" newline bitfld.long 0x18 3. "AXISRAM6ENS,AXISRAM6 enable" "0,1" newline bitfld.long 0x18 2. "AXISRAM5ENS,AXISRAM5 enable" "0,1" newline bitfld.long 0x18 1. "AXISRAM4ENS,AXISRAM4 enable" "0,1" newline bitfld.long 0x18 0. "AXISRAM3ENS,AXISRAM3 enable" "0,1" line.long 0x1C "RCC_AHB1ENSR,RCC AHB1 enable register" bitfld.long 0x1C 5. "ADC12ENS,ADC12 enable" "0,1" newline bitfld.long 0x1C 4. "GPDMA1ENS,GPDMA1 enable" "0,1" line.long 0x20 "RCC_AHB2ENSR,RCC AHB2 enable register" bitfld.long 0x20 17. "ADF1ENS,ADF1 enable" "0,1" newline bitfld.long 0x20 16. "MDF1ENS,MDF1 enable" "0,1" newline bitfld.long 0x20 12. "RAMCFGENS,RAMCFG enable" "0,1" line.long 0x24 "RCC_AHB3ENSR,RCC AHB3 enable register" bitfld.long 0x24 14. "RISAFENS,RISAF enable" "0,1" newline bitfld.long 0x24 10. "IACENS,IAC enable" "0,1" newline bitfld.long 0x24 9. "RIFSCENS,RIFSC enable" "0,1" newline bitfld.long 0x24 8. "PKAENS,PKA enable" "0,1" newline bitfld.long 0x24 4. "SAESENS,SAES enable" "0,1" newline bitfld.long 0x24 2. "CRYPENS,CRYP enable" "0,1" newline bitfld.long 0x24 1. "HASHENS,HASH enable" "0,1" newline bitfld.long 0x24 0. "RNGENS,RNG enable" "0,1" line.long 0x28 "RCC_AHB4ENSR,RCC AHB4 enable register" bitfld.long 0x28 19. "CRCENS,CRC enable" "0,1" newline bitfld.long 0x28 18. "PWRENS,PWR enable" "0,1" newline bitfld.long 0x28 16. "GPIOQENS,GPIOQ enable" "0,1" newline bitfld.long 0x28 15. "GPIOPENS,GPIOP enable" "0,1" newline bitfld.long 0x28 14. "GPIOOENS,GPIOO enable" "0,1" newline bitfld.long 0x28 13. "GPIONENS,GPION enable" "0,1" newline bitfld.long 0x28 7. "GPIOHENS,GPIOH enable" "0,1" newline bitfld.long 0x28 6. "GPIOGENS,GPIOG enable" "0,1" newline bitfld.long 0x28 5. "GPIOFENS,GPIOF enable" "0,1" newline bitfld.long 0x28 4. "GPIOEENS,GPIOE enable" "0,1" newline bitfld.long 0x28 3. "GPIODENS,GPIOD enable" "0,1" newline bitfld.long 0x28 2. "GPIOCENS,GPIOC enable" "0,1" newline bitfld.long 0x28 1. "GPIOBENS,GPIOB enable" "0,1" newline bitfld.long 0x28 0. "GPIOAENS,GPIOA enable" "0,1" line.long 0x2C "RCC_AHB5ENSR,RCC AHB5 enable register" bitfld.long 0x2C 31. "NPUENS,NPU enable" "0,1" newline bitfld.long 0x2C 30. "NPUCACHEENS,NPUCACHE enable" "0,1" newline bitfld.long 0x2C 29. "OTG2ENS,OTG2 enable" "0,1" newline bitfld.long 0x2C 28. "OTGPHY2ENS,OTGPHY2 enable" "0,1" newline bitfld.long 0x2C 27. "OTGPHY1ENS,OTGPHY1 enable" "0,1" newline bitfld.long 0x2C 26. "OTG1ENS,OTG1 enable" "0,1" newline bitfld.long 0x2C 25. "ETH1ENS,ETH1 enable" "0,1" newline bitfld.long 0x2C 24. "ETH1RXENS,ETH1RX enable" "0,1" newline bitfld.long 0x2C 23. "ETH1TXENS,ETH1TX enable" "0,1" newline bitfld.long 0x2C 22. "ETH1MACENS,ETH1MAC enable" "0,1" newline bitfld.long 0x2C 20. "GPUENS,GPU enable" "0,1" newline bitfld.long 0x2C 19. "GFXMMUENS,GFXMMU enable" "0,1" newline bitfld.long 0x2C 18. "MCE4ENS,MCE4 enable" "0,1" newline bitfld.long 0x2C 17. "XSPI3ENS,XSPI3 enable" "0,1" newline bitfld.long 0x2C 16. "MCE3ENS,MCE3 enable" "0,1" newline bitfld.long 0x2C 15. "MCE2ENS,MCE2 enable" "0,1" newline bitfld.long 0x2C 14. "MCE1ENS,MCE1 enable" "0,1" newline bitfld.long 0x2C 13. "XSPIMENS,XSPIM enable" "0,1" newline bitfld.long 0x2C 12. "XSPI2ENS,XSPI2 enable" "0,1" newline bitfld.long 0x2C 8. "SDMMC1ENS,SDMMC1 enable" "0,1" newline bitfld.long 0x2C 7. "SDMMC2ENS,SDMMC2 enable" "0,1" newline bitfld.long 0x2C 6. "PSSIENS,PSSI enable" "0,1" newline bitfld.long 0x2C 5. "XSPI1ENS,XSPI1 enable" "0,1" newline bitfld.long 0x2C 4. "FMCENS,FMC enable" "0,1" newline bitfld.long 0x2C 3. "JPEGENS,JPEG enable" "0,1" newline bitfld.long 0x2C 1. "DMA2DENS,DMA2D enable" "0,1" newline bitfld.long 0x2C 0. "HPDMA1ENS,HPDMA1 enable" "0,1" line.long 0x30 "RCC_APB1LENSR,RCC APB1L enable register" bitfld.long 0x30 31. "UART8ENS,UART8 enable" "0,1" newline bitfld.long 0x30 30. "UART7ENS,UART7 enable" "0,1" newline bitfld.long 0x30 25. "I3C2ENS,I3C2 enable" "0,1" newline bitfld.long 0x30 24. "I3C1ENS,I3C1 enable" "0,1" newline bitfld.long 0x30 23. "I2C3ENS,I2C3 enable" "0,1" newline bitfld.long 0x30 22. "I2C2ENS,I2C2 enable" "0,1" newline bitfld.long 0x30 21. "I2C1ENS,I2C1 enable" "0,1" newline bitfld.long 0x30 20. "UART5ENS,UART5 enable" "0,1" newline bitfld.long 0x30 19. "UART4ENS,UART4 enable" "0,1" newline bitfld.long 0x30 18. "USART3ENS,USART3 enable" "0,1" newline bitfld.long 0x30 17. "USART2ENS,USART2 enable" "0,1" newline bitfld.long 0x30 16. "SPDIFRX1ENS,SPDIFRX1 enable" "0,1" newline bitfld.long 0x30 15. "SPI3ENS,SPI3 enable" "0,1" newline bitfld.long 0x30 14. "SPI2ENS,SPI2 enable" "0,1" newline bitfld.long 0x30 13. "TIM11ENS,TIM11 enable" "0,1" newline bitfld.long 0x30 12. "TIM10ENS,TIM10 enable" "0,1" newline bitfld.long 0x30 11. "WWDGENS,WWDG enable" "0,1" newline bitfld.long 0x30 9. "LPTIM1ENS,LPTIM1 enable" "0,1" newline bitfld.long 0x30 8. "TIM14ENS,TIM14 enable" "0,1" newline bitfld.long 0x30 7. "TIM13ENS,TIM13 enable" "0,1" newline bitfld.long 0x30 6. "TIM12ENS,TIM12 enable" "0,1" newline bitfld.long 0x30 5. "TIM7ENS,TIM7 enable" "0,1" newline bitfld.long 0x30 4. "TIM6ENS,TIM6 enable" "0,1" newline bitfld.long 0x30 3. "TIM5ENS,TIM5 enable" "0,1" newline bitfld.long 0x30 2. "TIM4ENS,TIM4 enable" "0,1" newline bitfld.long 0x30 1. "TIM3ENS,TIM3 enable" "0,1" newline bitfld.long 0x30 0. "TIM2ENS,TIM2 enable" "0,1" line.long 0x34 "RCC_APB1HENSR,RCC APB1H enable register" bitfld.long 0x34 18. "UCPD1ENS,UCPD1 enable" "0,1" newline bitfld.long 0x34 8. "FDCANENS,FDCAN enable" "0,1" newline bitfld.long 0x34 5. "MDIOSENS,MDIOS enable" "0,1" line.long 0x38 "RCC_APB2ENSR,RCC APB2 enable register" bitfld.long 0x38 22. "SAI2ENS,SAI2 enable" "0,1" newline bitfld.long 0x38 21. "SAI1ENS,SAI1 enable" "0,1" newline bitfld.long 0x38 20. "SPI5ENS,SPI5 enable" "0,1" newline bitfld.long 0x38 19. "TIM9ENS,TIM9 enable" "0,1" newline bitfld.long 0x38 18. "TIM17ENS,TIM17 enable" "0,1" newline bitfld.long 0x38 17. "TIM16ENS,TIM16 enable" "0,1" newline bitfld.long 0x38 16. "TIM15ENS,TIM15 enable" "0,1" newline bitfld.long 0x38 15. "TIM18ENS,TIM18 enable" "0,1" newline bitfld.long 0x38 13. "SPI4ENS,SPI4 enable" "0,1" newline bitfld.long 0x38 12. "SPI1ENS,SPI1 enable" "0,1" newline bitfld.long 0x38 7. "USART10ENS,USART10 enable" "0,1" newline bitfld.long 0x38 6. "UART9ENS,UART9 enable" "0,1" newline bitfld.long 0x38 5. "USART6ENS,USART6 enable" "0,1" newline bitfld.long 0x38 4. "USART1ENS,USART1 enable" "0,1" newline bitfld.long 0x38 1. "TIM8ENS,TIM8 enable" "0,1" newline bitfld.long 0x38 0. "TIM1ENS,TIM1 enable" "0,1" line.long 0x3C "RCC_APB3ENSR,RCC APB3 enable register" bitfld.long 0x3C 2. "DFTENS,DFT enable" "0,1" line.long 0x40 "RCC_APB4LENSR,RCC APB4L enable register" bitfld.long 0x40 31. "SERFENS,SERF enable" "0,1" newline bitfld.long 0x40 23. "R2GNPUENS,R2GNPU enable" "0,1" newline bitfld.long 0x40 22. "R2GRETENS,R2GRET enable" "0,1" newline bitfld.long 0x40 17. "RTCAPBENS,RTCAPB enable" "0,1" newline bitfld.long 0x40 16. "RTCENS,RTC enable" "0,1" newline bitfld.long 0x40 15. "VREFBUFENS,VREFBUF enable" "0,1" newline bitfld.long 0x40 12. "LPTIM5ENS,LPTIM5 enable" "0,1" newline bitfld.long 0x40 11. "LPTIM4ENS,LPTIM4 enable" "0,1" newline bitfld.long 0x40 10. "LPTIM3ENS,LPTIM3 enable" "0,1" newline bitfld.long 0x40 9. "LPTIM2ENS,LPTIM2 enable" "0,1" newline bitfld.long 0x40 7. "I2C4ENS,I2C4 enable" "0,1" newline bitfld.long 0x40 5. "SPI6ENS,SPI6 enable" "0,1" newline bitfld.long 0x40 3. "LPUART1ENS,LPUART1 enable" "0,1" newline bitfld.long 0x40 2. "HDPENS,HDP enable" "0,1" line.long 0x44 "RCC_APB4HENSR,RCC APB4H enable register" bitfld.long 0x44 4. "BUSPERFMENS,BUSPERFM enable" "0,1" newline bitfld.long 0x44 2. "DTSENS,DTS enable" "0,1" newline bitfld.long 0x44 1. "BSECENS,BSEC enable" "0,1" newline bitfld.long 0x44 0. "SYSCFGENS,SYSCFG enable" "0,1" line.long 0x48 "RCC_APB5ENSR,RCC APB5 enable register" bitfld.long 0x48 6. "CSIENS,CSI enable" "0,1" newline bitfld.long 0x48 5. "VENCENS,VENC enable" "0,1" newline bitfld.long 0x48 4. "GFXTIMENS,GFXTIM enable" "0,1" newline bitfld.long 0x48 2. "DCMIPPENS,DCMIPP enable" "0,1" newline bitfld.long 0x48 1. "LTDCENS,LTDC enable" "0,1" line.long 0x4C "RCC_DIVLPENSR,RCC divider Sleep enable register" bitfld.long 0x4C 19. "IC20LPENS,IC20 sleep enable" "0,1" newline bitfld.long 0x4C 18. "IC19LPENS,IC19 sleep enable" "0,1" newline bitfld.long 0x4C 17. "IC18LPENS,IC18 sleep enable" "0,1" newline bitfld.long 0x4C 16. "IC17LPENS,IC17 sleep enable" "0,1" newline bitfld.long 0x4C 15. "IC16LPENS,IC16 sleep enable" "0,1" newline bitfld.long 0x4C 14. "IC15LPENS,IC15 sleep enable" "0,1" newline bitfld.long 0x4C 13. "IC14LPENS,IC14 sleep enable" "0,1" newline bitfld.long 0x4C 12. "IC13LPENS,IC13 sleep enable" "0,1" newline bitfld.long 0x4C 11. "IC12LPENS,IC12 sleep enable" "0,1" newline bitfld.long 0x4C 10. "IC11LPENS,IC11 sleep enable" "0,1" newline bitfld.long 0x4C 9. "IC10LPENS,IC10 sleep enable" "0,1" newline bitfld.long 0x4C 8. "IC9LPENS,IC9 sleep enable" "0,1" newline bitfld.long 0x4C 7. "IC8LPENS,IC8 sleep enable" "0,1" newline bitfld.long 0x4C 6. "IC7LPENS,IC7 sleep enable" "0,1" newline bitfld.long 0x4C 5. "IC6LPENS,IC6 sleep enable" "0,1" newline bitfld.long 0x4C 4. "IC5LPENS,IC5 sleep enable" "0,1" newline bitfld.long 0x4C 3. "IC4LPENS,IC4 sleep enable" "0,1" newline bitfld.long 0x4C 2. "IC3LPENS,IC3 sleep enable" "0,1" newline bitfld.long 0x4C 1. "IC2LPENS,IC2 sleep enable" "0,1" newline bitfld.long 0x4C 0. "IC1LPENS,IC1 sleep enable" "0,1" line.long 0x50 "RCC_BUSLPENSR,RCC bus Sleep enable register" bitfld.long 0x50 12. "APB5LPENS,APB5 sleep enable" "0,1" newline bitfld.long 0x50 11. "APB4LPENS,APB4 sleep enable" "0,1" newline bitfld.long 0x50 10. "APB3LPENS,APB3 sleep enable" "0,1" newline bitfld.long 0x50 9. "APB2LPENS,APB2 sleep enable" "0,1" newline bitfld.long 0x50 8. "APB1LPENS,APB1 sleep enable" "0,1" newline bitfld.long 0x50 7. "AHB5LPENS,AHB5 sleep enable" "0,1" newline bitfld.long 0x50 6. "AHB4LPENS,AHB4 sleep enable" "0,1" newline bitfld.long 0x50 5. "AHB3LPENS,AHB3 sleep enable" "0,1" newline bitfld.long 0x50 4. "AHB2LPENS,AHB2 sleep enable" "0,1" newline bitfld.long 0x50 3. "AHB1LPENS,AHB1 sleep enable" "0,1" newline bitfld.long 0x50 2. "AHBMLPENS,AHBM sleep enable" "0,1" newline bitfld.long 0x50 1. "ACLKNCLPENS,ACLKNC sleep enable" "0,1" newline bitfld.long 0x50 0. "ACLKNLPENS,ACLKN sleep enable" "0,1" line.long 0x54 "RCC_MISCLPENSR,RCC miscellaneous Sleep enable register" bitfld.long 0x54 6. "PERLPENS,PER sleep enable" "0,1" newline bitfld.long 0x54 3. "XSPIPHYCOMPLPENS,XSPIPHYCOMP sleep enable" "0,1" newline bitfld.long 0x54 0. "DBGLPENS,DBG sleep enable" "0,1" line.long 0x58 "RCC_MEMLPENSR,RCC memory sleep enable register" bitfld.long 0x58 12. "BOOTROMLPENS,BOOTROM sleep enable" "0,1" newline bitfld.long 0x58 11. "VENCRAMLPENS,VENCRAM sleep enable" "0,1" newline bitfld.long 0x58 10. "NPUCACHERAMLPENS,NPUCACHERAM sleep enable" "0,1" newline bitfld.long 0x58 9. "FLEXRAMLPENS,FLEXRAM sleep enable" "0,1" newline bitfld.long 0x58 8. "AXISRAM2LPENS,AXISRAM2 sleep enable" "0,1" newline bitfld.long 0x58 7. "AXISRAM1LPENS,AXISRAM1 sleep enable" "0,1" newline bitfld.long 0x58 6. "BKPSRAMLPENS,BKPSRAM sleep enable" "0,1" newline bitfld.long 0x58 5. "AHBSRAM2LPENS,AHBSRAM2 sleep enable" "0,1" newline bitfld.long 0x58 4. "AHBSRAM1LPENS,AHBSRAM1 sleep enable" "0,1" newline bitfld.long 0x58 3. "AXISRAM6LPENS,AXISRAM6 sleep enable" "0,1" newline bitfld.long 0x58 2. "AXISRAM5LPENS,AXISRAM5 sleep enable" "0,1" newline bitfld.long 0x58 1. "AXISRAM4LPENS,AXISRAM4 sleep enable" "0,1" newline bitfld.long 0x58 0. "AXISRAM3LPENS,AXISRAM3 sleep enable" "0,1" line.long 0x5C "RCC_AHB1LPENSR,RCC AHB1 Sleep enable register" bitfld.long 0x5C 5. "ADC12LPENS,ADC12 sleep enable" "0,1" newline bitfld.long 0x5C 4. "GPDMA1LPENS,GPDMA1 sleep enable" "0,1" line.long 0x60 "RCC_AHB2LPENSR,RCC AHB2 Sleep enable register" bitfld.long 0x60 17. "ADF1LPENS,ADF1 sleep enable" "0,1" newline bitfld.long 0x60 16. "MDF1LPENS,MDF1 sleep enable" "0,1" newline bitfld.long 0x60 12. "RAMCFGLPENS,RAMCFG sleep enable" "0,1" line.long 0x64 "RCC_AHB3LPENSR,RCC AHB3 Sleep enable register" bitfld.long 0x64 14. "RISAFLPENS,RISAF sleep enable" "0,1" newline bitfld.long 0x64 10. "IACLPENS,IAC sleep enable" "0,1" newline bitfld.long 0x64 9. "RIFSCLPENS,RIFSC sleep enable" "0,1" newline bitfld.long 0x64 8. "PKALPENS,PKA sleep enable" "0,1" newline bitfld.long 0x64 4. "SAESLPENS,SAES sleep enable" "0,1" newline bitfld.long 0x64 2. "CRYPLPENS,CRYP sleep enable" "0,1" newline bitfld.long 0x64 1. "HASHLPENS,HASH sleep enable" "0,1" newline bitfld.long 0x64 0. "RNGLPENS,RNG sleep enable" "0,1" line.long 0x68 "RCC_AHB4LPENSR,RCC AHB4 Sleep enable register" bitfld.long 0x68 19. "CRCLPENS,CRC sleep enable" "0,1" newline bitfld.long 0x68 18. "PWRLPENS,PWR sleep enable" "0,1" newline bitfld.long 0x68 16. "GPIOQLPENS,GPIOQ sleep enable" "0,1" newline bitfld.long 0x68 15. "GPIOPLPENS,GPIOP sleep enable" "0,1" newline bitfld.long 0x68 14. "GPIOOLPENS,GPIOO sleep enable" "0,1" newline bitfld.long 0x68 13. "GPIONLPENS,GPION sleep enable" "0,1" newline bitfld.long 0x68 7. "GPIOHLPENS,GPIOH sleep enable" "0,1" newline bitfld.long 0x68 6. "GPIOGLPENS,GPIOG sleep enable" "0,1" newline bitfld.long 0x68 5. "GPIOFLPENS,GPIOF sleep enable" "0,1" newline bitfld.long 0x68 4. "GPIOELPENS,GPIOE sleep enable" "0,1" newline bitfld.long 0x68 3. "GPIODLPENS,GPIOD sleep enable" "0,1" newline bitfld.long 0x68 2. "GPIOCLPENS,GPIOC sleep enable" "0,1" newline bitfld.long 0x68 1. "GPIOBLPENS,GPIOB sleep enable" "0,1" newline bitfld.long 0x68 0. "GPIOALPENS,GPIOA sleep enable" "0,1" line.long 0x6C "RCC_AHB5LPENSR,RCC AHB5 Sleep enable register" bitfld.long 0x6C 31. "NPULPENS,NPU sleep enable" "0,1" newline bitfld.long 0x6C 30. "NPUCACHELPENS,NPUCACHE sleep enable" "0,1" newline bitfld.long 0x6C 29. "OTG2LPENS,OTG2 sleep enable" "0,1" newline bitfld.long 0x6C 28. "OTGPHY2LPENS,OTGPHY2 sleep enable" "0,1" newline bitfld.long 0x6C 27. "OTGPHY1LPENS,OTGPHY1 sleep enable" "0,1" newline bitfld.long 0x6C 26. "OTG1LPENS,OTG1 sleep enable" "0,1" newline bitfld.long 0x6C 25. "ETH1LPENS,ETH1 sleep enable" "0,1" newline bitfld.long 0x6C 24. "ETH1RXLPENS,ETH1RX sleep enable" "0,1" newline bitfld.long 0x6C 23. "ETH1TXLPENS,ETH1TX sleep enable" "0,1" newline bitfld.long 0x6C 22. "ETH1MACLPENS,ETH1MAC sleep enable" "0,1" newline bitfld.long 0x6C 20. "GPULPENS,GPU sleep enable" "0,1" newline bitfld.long 0x6C 19. "GFXMMULPENS,GFXMMU sleep enable" "0,1" newline bitfld.long 0x6C 18. "MCE4LPENS,MCE4 sleep enable" "0,1" newline bitfld.long 0x6C 17. "XSPI3LPENS,XSPI3 sleep enable" "0,1" newline bitfld.long 0x6C 16. "MCE3LPENS,MCE3 sleep enable" "0,1" newline bitfld.long 0x6C 15. "MCE2LPENS,MCE2 sleep enable" "0,1" newline bitfld.long 0x6C 14. "MCE1LPENS,MCE1 sleep enable" "0,1" newline bitfld.long 0x6C 13. "XSPIMLPENS,XSPIM sleep enable" "0,1" newline bitfld.long 0x6C 12. "XSPI2LPENS,XSPI2 sleep enable" "0,1" newline bitfld.long 0x6C 8. "SDMMC1LPENS,SDMMC1 sleep enable" "0,1" newline bitfld.long 0x6C 7. "SDMMC2LPENS,SDMMC2 sleep enable" "0,1" newline bitfld.long 0x6C 6. "PSSILPENS,PSSI sleep enable" "0,1" newline bitfld.long 0x6C 5. "XSPI1LPENS,XSPI1 sleep enable" "0,1" newline bitfld.long 0x6C 4. "FMCLPENS,FMC sleep enable" "0,1" newline bitfld.long 0x6C 3. "JPEGLPENS,JPEG sleep enable" "0,1" newline bitfld.long 0x6C 1. "DMA2DLPENS,DMA2D sleep enable" "0,1" newline bitfld.long 0x6C 0. "HPDMA1LPENS,HPDMA1 sleep enable" "0,1" line.long 0x70 "RCC_APB1LLPENSR,RCC APB1L Sleep enable register" bitfld.long 0x70 31. "UART8LPENS,UART8 sleep enable" "0,1" newline bitfld.long 0x70 30. "UART7LPENS,UART7 sleep enable" "0,1" newline bitfld.long 0x70 25. "I3C2LPENS,I3C2 sleep enable" "0,1" newline bitfld.long 0x70 24. "I3C1LPENS,I3C1 sleep enable" "0,1" newline bitfld.long 0x70 23. "I2C3LPENS,I2C3 sleep enable" "0,1" newline bitfld.long 0x70 22. "I2C2LPENS,I2C2 sleep enable" "0,1" newline bitfld.long 0x70 21. "I2C1LPENS,I2C1 sleep enable" "0,1" newline bitfld.long 0x70 20. "UART5LPENS,UART5 sleep enable" "0,1" newline bitfld.long 0x70 19. "UART4LPENS,UART4 sleep enable" "0,1" newline bitfld.long 0x70 18. "USART3LPENS,USART3 sleep enable" "0,1" newline bitfld.long 0x70 17. "USART2LPENS,USART2 sleep enable" "0,1" newline bitfld.long 0x70 16. "SPDIFRX1LPENS,SPDIFRX1 sleep enable" "0,1" newline bitfld.long 0x70 15. "SPI3LPENS,SPI3 sleep enable" "0,1" newline bitfld.long 0x70 14. "SPI2LPENS,SPI2 sleep enable" "0,1" newline bitfld.long 0x70 13. "TIM11LPENS,TIM11 sleep enable" "0,1" newline bitfld.long 0x70 12. "TIM10LPENS,TIM10 sleep enable" "0,1" newline bitfld.long 0x70 11. "WWDGLPENS,WWDG sleep enable" "0,1" newline bitfld.long 0x70 9. "LPTIM1LPENS,LPTIM1 sleep enable" "0,1" newline bitfld.long 0x70 8. "TIM14LPENS,TIM14 sleep enable" "0,1" newline bitfld.long 0x70 7. "TIM13LPENS,TIM13 sleep enable" "0,1" newline bitfld.long 0x70 6. "TIM12LPENS,TIM12 sleep enable" "0,1" newline bitfld.long 0x70 5. "TIM7LPENS,TIM7 sleep enable" "0,1" newline bitfld.long 0x70 4. "TIM6LPENS,TIM6 sleep enable" "0,1" newline bitfld.long 0x70 3. "TIM5LPENS,TIM5 sleep enable" "0,1" newline bitfld.long 0x70 2. "TIM4LPENS,TIM4 sleep enable" "0,1" newline bitfld.long 0x70 1. "TIM3LPENS,TIM3 sleep enable" "0,1" newline bitfld.long 0x70 0. "TIM2LPENS,TIM2 sleep enable" "0,1" line.long 0x74 "RCC_APB1HLPENSR,RCC APB1H Sleep enable register" bitfld.long 0x74 18. "UCPD1LPENS,UCPD1 sleep enable" "0,1" newline bitfld.long 0x74 8. "FDCANLPENS,FDCAN sleep enable" "0,1" newline bitfld.long 0x74 5. "MDIOSLPENS,MDIOS sleep enable" "0,1" line.long 0x78 "RCC_APB2LPENSR,RCC APB2 Sleep enable register" bitfld.long 0x78 22. "SAI2LPENS,SAI2 sleep enable" "0,1" newline bitfld.long 0x78 21. "SAI1LPENS,SAI1 sleep enable" "0,1" newline bitfld.long 0x78 20. "SPI5LPENS,SPI5 sleep enable" "0,1" newline bitfld.long 0x78 19. "TIM9LPENS,TIM9 sleep enable" "0,1" newline bitfld.long 0x78 18. "TIM17LPENS,TIM17 sleep enable" "0,1" newline bitfld.long 0x78 17. "TIM16LPENS,TIM16 sleep enable" "0,1" newline bitfld.long 0x78 16. "TIM15LPENS,TIM15 sleep enable" "0,1" newline bitfld.long 0x78 15. "TIM18LPENS,TIM18 sleep enable" "0,1" newline bitfld.long 0x78 13. "SPI4LPENS,SPI4 sleep enable" "0,1" newline bitfld.long 0x78 12. "SPI1LPENS,SPI1 sleep enable" "0,1" newline bitfld.long 0x78 7. "USART10LPENS,USART10 sleep enable" "0,1" newline bitfld.long 0x78 6. "UART9LPENS,UART9 sleep enable" "0,1" newline bitfld.long 0x78 5. "USART6LPENS,USART6 sleep enable" "0,1" newline bitfld.long 0x78 4. "USART1LPENS,USART1 sleep enable" "0,1" newline bitfld.long 0x78 1. "TIM8LPENS,TIM8 sleep enable" "0,1" newline bitfld.long 0x78 0. "TIM1LPENS,TIM1 sleep enable" "0,1" line.long 0x7C "RCC_APB3LPENSR,RCC APB3 Sleep enable register" bitfld.long 0x7C 2. "DFTLPENS,DFT sleep enable" "0,1" line.long 0x80 "RCC_APB4LLPENSR,RCC APB4L Sleep enable register" bitfld.long 0x80 31. "SERFLPENS,SERF sleep enable" "0,1" newline bitfld.long 0x80 23. "R2GNPULPENS,R2GNPU sleep enable" "0,1" newline bitfld.long 0x80 22. "R2GRETLPENS,R2GRET sleep enable" "0,1" newline bitfld.long 0x80 17. "RTCAPBLPENS,RTCAPB sleep enable" "0,1" newline bitfld.long 0x80 16. "RTCLPENS,RTC sleep enable" "0,1" newline bitfld.long 0x80 15. "VREFBUFLPENS,VREFBUF sleep enable" "0,1" newline bitfld.long 0x80 12. "LPTIM5LPENS,LPTIM5 sleep enable" "0,1" newline bitfld.long 0x80 11. "LPTIM4LPENS,LPTIM4 sleep enable" "0,1" newline bitfld.long 0x80 10. "LPTIM3LPENS,LPTIM3 sleep enable" "0,1" newline bitfld.long 0x80 9. "LPTIM2LPENS,LPTIM2 sleep enable" "0,1" newline bitfld.long 0x80 7. "I2C4LPENS,I2C4 sleep enable" "0,1" newline bitfld.long 0x80 5. "SPI6LPENS,SPI6 sleep enable" "0,1" newline bitfld.long 0x80 3. "LPUART1LPENS,LPUART1 sleep enable" "0,1" newline bitfld.long 0x80 2. "HDPLPENS,HDP sleep enable" "0,1" line.long 0x84 "RCC_APB4HLPENSR,RCC APB4H Sleep enable register" bitfld.long 0x84 4. "BUSPERFMLPENS,BUSPERFM sleep enable" "0,1" newline bitfld.long 0x84 2. "DTSLPENS,DTS sleep enable" "0,1" newline bitfld.long 0x84 1. "BSECLPENS,BSEC sleep enable" "0,1" newline bitfld.long 0x84 0. "SYSCFGLPENS,SYSCFG sleep enable" "0,1" line.long 0x88 "RCC_APB5LPENSR,RCC APB5 Sleep enable register" bitfld.long 0x88 6. "CSILPENS,CSI sleep enable" "0,1" newline bitfld.long 0x88 5. "VENCLPENS,VENC sleep enable" "0,1" newline bitfld.long 0x88 4. "GFXTIMLPENS,GFXTIM sleep enable" "0,1" newline bitfld.long 0x88 2. "DCMIPPLPENS,DCMIPP sleep enable" "0,1" newline bitfld.long 0x88 1. "LTDCLPENS,LTDC sleep enable" "0,1" wgroup.long 0xF84++0x3 line.long 0x0 "RCC_PRIVCFGSR0,RCC oscillator privilege configuration register0" bitfld.long 0x0 4. "HSEPVS,Defines the privilege protection of the HSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "HSIPVS,Defines the privilege protection of the HSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "MSIPVS,Defines the privilege protection of the MSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "LSEPVS,Defines the privilege protection of the LSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "LSIPVS,Defines the privilege protection of the LSI configuration bits (enable ready divider)." "0,1" wgroup.long 0xF8C++0x3 line.long 0x0 "RCC_PUBCFGSR0,RCC oscillator public configuration register0" bitfld.long 0x0 4. "HSEPUBS,Defines the public protection of the HSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "HSIPUBS,Defines the public protection of the HSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "MSIPUBS,Defines the public protection of the MSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "LSEPUBS,Defines the public protection of the LSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "LSIPUBS,Defines the public protection of the LSI configuration bits (enable ready divider)." "0,1" wgroup.long 0xF94++0x3 line.long 0x0 "RCC_PRIVCFGSR1,RCC PLL privilege configuration register1" bitfld.long 0x0 3. "PLL4PVS,Defines the privilege protection of the PLL4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "PLL3PVS,Defines the privilege protection of the PLL3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "PLL2PVS,Defines the privilege protection of the PLL2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "PLL1PVS,Defines the privilege protection of the PLL1 configuration bits (enable ready divider)." "0,1" wgroup.long 0xF9C++0x3 line.long 0x0 "RCC_PUBCFGSR1,RCC PLL public configuration register1" bitfld.long 0x0 3. "PLL4PUBS,Defines the public protection of the PLL4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "PLL3PUBS,Defines the public protection of the PLL3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "PLL2PUBS,Defines the public protection of the PLL2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "PLL1PUBS,Defines the public protection of the PLL1 configuration bits (enable ready divider)." "0,1" wgroup.long 0xFA4++0x3 line.long 0x0 "RCC_PRIVCFGSR2,RCC divider privilege configuration register2" bitfld.long 0x0 19. "IC20PVS,Defines the privilege protection of the IC20 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 18. "IC19PVS,Defines the privilege protection of the IC19 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 17. "IC18PVS,Defines the privilege protection of the IC18 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 16. "IC17PVS,Defines the privilege protection of the IC17 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 15. "IC16PVS,Defines the privilege protection of the IC16 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 14. "IC15PVS,Defines the privilege protection of the IC15 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 13. "IC14PVS,Defines the privilege protection of the IC14 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "IC13PVS,Defines the privilege protection of the IC13 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "IC12PVS,Defines the privilege protection of the IC12 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "IC11PVS,Defines the privilege protection of the IC11 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "IC10PVS,Defines the privilege protection of the IC10 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "IC9PVS,Defines the privilege protection of the IC9 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "IC8PVS,Defines the privilege protection of the IC8 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "IC7PVS,Defines the privilege protection of the IC7 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "IC6PVS,Defines the privilege protection of the IC6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "IC5PVS,Defines the privilege protection of the IC5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "IC4PVS,Defines the privilege protection of the IC4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "IC3PVS,Defines the privilege protection of the IC3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "IC2PVS,Defines the privilege protection of the IC2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "IC1PVS,Defines the privilege protection of the IC1 configuration bits (enable ready divider)." "0,1" wgroup.long 0xFAC++0x13 line.long 0x0 "RCC_PUBCFGSR2,RCC divider public configuration register2" bitfld.long 0x0 19. "IC20PUBS,Defines the public protection of the IC20 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 18. "IC19PUBS,Defines the public protection of the IC19 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 17. "IC18PUBS,Defines the public protection of the IC18 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 16. "IC17PUBS,Defines the public protection of the IC17 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 15. "IC16PUBS,Defines the public protection of the IC16 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 14. "IC15PUBS,Defines the public protection of the IC15 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 13. "IC14PUBS,Defines the public protection of the IC14 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "IC13PUBS,Defines the public protection of the IC13 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "IC12PUBS,Defines the public protection of the IC12 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "IC11PUBS,Defines the public protection of the IC11 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "IC10PUBS,Defines the public protection of the IC10 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "IC9PUBS,Defines the public protection of the IC9 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "IC8PUBS,Defines the public protection of the IC8 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "IC7PUBS,Defines the public protection of the IC7 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "IC6PUBS,Defines the public protection of the IC6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "IC5PUBS,Defines the public protection of the IC5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "IC4PUBS,Defines the public protection of the IC4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "IC3PUBS,Defines the public protection of the IC3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "IC2PUBS,Defines the public protection of the IC2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "IC1PUBS,Defines the public protection of the IC1 configuration bits (enable ready divider)." "0,1" line.long 0x4 "RCC_SECCFGSR3,RCC system secure configuration register3" bitfld.long 0x4 6. "DFTSECS,Defines the secure protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 5. "RSTSECS,Defines the secure protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 4. "INTSECS,Defines the secure protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 3. "PERSECS,Defines the secure protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 2. "BUSSECS,Defines the secure protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 1. "SYSSECS,Defines the secure protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 0. "MODSECS,Defines the secure protection of the MOD configuration bits (enable ready divider)." "0,1" line.long 0x8 "RCC_PRIVCFGSR3,RCC system privilege configuration register3" bitfld.long 0x8 6. "DFTPVS,Defines the privilege protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 5. "RSTPVS,Defines the privilege protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 4. "INTPVS,Defines the privilege protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 3. "PERPVS,Defines the privilege protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 2. "BUSPVS,Defines the privilege protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 1. "SYSPVS,Defines the privilege protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x8 0. "MODPVS,Defines the privilege protection of the MOD configuration bits (enable ready divider)." "0,1" line.long 0xC "RCC_LOCKCFGSR3,RCC system lock configuration register3" bitfld.long 0xC 6. "DFTLOCKS,Defines the lock protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 5. "RSTLOCKS,Defines the lock protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 4. "INTLOCKS,Defines the lock protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 3. "PERLOCKS,Defines the lock protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 2. "BUSLOCKS,Defines the lock protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 1. "SYSLOCKS,Defines the lock protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0xC 0. "MODLOCKS,Defines the lock protection of the MOD configuration bits (enable ready divider)." "0,1" line.long 0x10 "RCC_PUBCFGSR3,RCC system public configuration register3" bitfld.long 0x10 6. "DFTPUBS,Defines the public protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 5. "RSTPUBS,Defines the public protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 4. "INTPUBS,Defines the public protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 3. "PERPUBS,Defines the public protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 2. "BUSPUBS,Defines the public protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 1. "SYSPUBS,Defines the public protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x10 0. "MODPUBS,Defines the public protection of the MOD configuration bits (enable ready divider)." "0,1" wgroup.long 0xFC4++0x3 line.long 0x0 "RCC_PRIVCFGSR4,RCC privilege configuration register4" bitfld.long 0x0 13. "NOCPVS,Defines the privilege protection of the NOC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "APB5PVS,Defines the privilege protection of the APB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "APB4PVS,Defines the privilege protection of the APB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "APB3PVS,Defines the privilege protection of the APB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "APB2PVS,Defines the privilege protection of the APB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "APB1PVS,Defines the privilege protection of the APB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "AHB5PVS,Defines the privilege protection of the AHB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "AHB4PVS,Defines the privilege protection of the AHB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "AHB3PVS,Defines the privilege protection of the AHB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "AHB2PVS,Defines the privilege protection of the AHB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "AHB1PVS,Defines the privilege protection of the AHB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "AHBMPVS,Defines the privilege protection of the AHBM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "ACLKNCPVS,Defines the privilege protection of the ACLKNC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "ACLKNPVS,Defines the privilege protection of the ACLKN configuration bits (enable ready divider)." "0,1" wgroup.long 0xFCC++0x7 line.long 0x0 "RCC_PUBCFGSR4,RCC public configuration register4" bitfld.long 0x0 13. "NOCPUBS,Defines the public protection of the NOC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "APB5PUBS,Defines the public protection of the APB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "APB4PUBS,Defines the public protection of the APB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "APB3PUBS,Defines the public protection of the APB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "APB2PUBS,Defines the public protection of the APB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "APB1PUBS,Defines the public protection of the APB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "AHB5PUBS,Defines the public protection of the AHB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "AHB4PUBS,Defines the public protection of the AHB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "AHB3PUBS,Defines the public protection of the AHB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "AHB2PUBS,Defines the public protection of the AHB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "AHB1PUBS,Defines the public protection of the AHB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "AHBMPUBS,Defines the public protection of the AHBM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "ACLKNCPUBS,Defines the public protection of the ACLKNC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "ACLKNPUBS,Defines the public protection of the ACLKN configuration bits (enable ready divider)." "0,1" line.long 0x4 "RCC_PUBCFGSR5,RCC public configuration register4" bitfld.long 0x4 11. "VENCRAMPUBS,Defines the public protection of the VENCRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 10. "NPUCACHERAMPUBS,Defines the public protection of the NPUCACHERAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 9. "FLEXRAMPUBS,Defines the public protection of the FLEXRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 8. "AXISRAM2PUBS,Defines the public protection of the AXISRAM2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 7. "AXISRAM1PUBS,Defines the public protection of the AXISRAM1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 6. "BKPSRAMPUBS,Defines the public protection of the BKPSRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 5. "AHBSRAM2PUBS,Defines the public protection of the AHBSRAM2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 4. "AHBSRAM1PUBS,Defines the public protection of the AHBSRAM1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 3. "AXISRAM6PUBS,Defines the public protection of the AXISRAM6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 2. "AXISRAM5PUBS,Defines the public protection of the AXISRAM5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 1. "AXISRAM4PUBS,Defines the public protection of the AXISRAM4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 0. "AXISRAM3PUBS,Defines the public protection of the AXISRAM3 configuration bits (enable ready divider)." "0,1" wgroup.long 0x1000++0x3 line.long 0x0 "RCC_CCR,RCC control Clear register" bitfld.long 0x0 11. "PLL4ONC,PLL4 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 10. "PLL3ONC,PLL3 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 9. "PLL2ONC,PLL2 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 8. "PLL1ONC,PLL1 oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 4. "HSEONC,HSE oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 3. "HSIONC,HSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 2. "MSIONC,MSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 1. "LSEONC,LSE oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 0. "LSIONC,LSI oscillator enable in Run/Sleep mode." "0,1" wgroup.long 0x1008++0x3 line.long 0x0 "RCC_STOPCCR,RCC StopCCR configuration register" bitfld.long 0x0 3. "HSISTOPENC,HSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 2. "MSISTOPENC,MSI oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 1. "LSESTOPENC,LSE oscillator enable in Run/Sleep mode." "0,1" newline bitfld.long 0x0 0. "LSISTOPENC,LSI oscillator enable in Run/Sleep mode." "0,1" wgroup.long 0x1204++0x2B line.long 0x0 "RCC_BUSRSTCR,RCC bus reset register" bitfld.long 0x0 13. "NOCRSTC,NOC reset" "0,1" newline bitfld.long 0x0 12. "APB5RSTC,APB5 reset" "0,1" newline bitfld.long 0x0 11. "APB4RSTC,APB4 reset" "0,1" newline bitfld.long 0x0 10. "APB3RSTC,APB3 reset" "0,1" newline bitfld.long 0x0 9. "APB2RSTC,APB2 reset" "0,1" newline bitfld.long 0x0 8. "APB1RSTC,APB1 reset" "0,1" newline bitfld.long 0x0 7. "AHB5RSTC,AHB5 reset" "0,1" newline bitfld.long 0x0 6. "AHB4RSTC,AHB4 reset" "0,1" newline bitfld.long 0x0 5. "AHB3RSTC,AHB3 reset" "0,1" newline bitfld.long 0x0 4. "AHB2RSTC,AHB2 reset" "0,1" newline bitfld.long 0x0 3. "AHB1RSTC,AHB1 reset" "0,1" newline bitfld.long 0x0 2. "AHBMRSTC,AHBM reset" "0,1" newline bitfld.long 0x0 0. "ACLKNRSTC,ACLKN reset" "0,1" line.long 0x4 "RCC_MISCRSTCR,RCC miscellaneous reset register" bitfld.long 0x4 8. "SDMMC2DLLRSTC,SDMMC2DLL reset" "0,1" newline bitfld.long 0x4 7. "SDMMC1DLLRSTC,SDMMC1DLL reset" "0,1" newline bitfld.long 0x4 5. "XSPIPHY2RSTC,XSPIPHY2 reset" "0,1" newline bitfld.long 0x4 4. "XSPIPHY1RSTC,XSPIPHY1 reset" "0,1" newline bitfld.long 0x4 0. "DBGRSTC,DBG reset" "0,1" line.long 0x8 "RCC_MEMRSTCR,RCC memory reset register" bitfld.long 0x8 12. "BOOTROMRSTC,BOOTROM reset" "0,1" newline bitfld.long 0x8 11. "VENCRAMRSTC,VENCRAM reset" "0,1" newline bitfld.long 0x8 10. "NPUCACHERAMRSTC,NPUCACHERAM reset" "0,1" newline bitfld.long 0x8 9. "FLEXRAMRSTC,FLEXRAM reset" "0,1" newline bitfld.long 0x8 8. "AXISRAM2RSTC,AXISRAM2 reset" "0,1" newline bitfld.long 0x8 7. "AXISRAM1RSTC,AXISRAM1 reset" "0,1" newline bitfld.long 0x8 5. "AHBSRAM2RSTC,AHBSRAM2 reset" "0,1" newline bitfld.long 0x8 4. "AHBSRAM1RSTC,AHBSRAM1 reset" "0,1" newline bitfld.long 0x8 3. "AXISRAM6RSTC,AXISRAM6 reset" "0,1" newline bitfld.long 0x8 2. "AXISRAM5RSTC,AXISRAM5 reset" "0,1" newline bitfld.long 0x8 1. "AXISRAM4RSTC,AXISRAM4 reset" "0,1" newline bitfld.long 0x8 0. "AXISRAM3RSTC,AXISRAM3 reset" "0,1" line.long 0xC "RCC_AHB1RSTCR,RCC AHB1 reset register" bitfld.long 0xC 5. "ADC12RSTC,ADC12 reset" "0,1" newline bitfld.long 0xC 4. "GPDMA1RSTC,GPDMA1 reset" "0,1" line.long 0x10 "RCC_AHB2RSTCR,RCC AHB2 Reset register" bitfld.long 0x10 17. "ADF1RSTC,ADF1 reset" "0,1" newline bitfld.long 0x10 16. "MDF1RSTC,MDF1 reset" "0,1" newline bitfld.long 0x10 12. "RAMCFGRSTC,RAMCFG reset" "0,1" line.long 0x14 "RCC_AHB3RSTCR,RCC AHB3 reset register" bitfld.long 0x14 10. "IACRSTC,IAC reset" "0,1" newline bitfld.long 0x14 8. "PKARSTC,PKA reset" "0,1" newline bitfld.long 0x14 4. "SAESRSTC,SAES reset" "0,1" newline bitfld.long 0x14 2. "CRYPRSTC,CRYP reset" "0,1" newline bitfld.long 0x14 1. "HASHRSTC,HASH reset" "0,1" newline bitfld.long 0x14 0. "RNGRSTC,RNG reset" "0,1" line.long 0x18 "RCC_AHB4RSTCR,RCC AHB4 reset register" bitfld.long 0x18 19. "CRCRSTC,CRC reset" "0,1" newline bitfld.long 0x18 18. "PWRRSTC,PWR reset" "0,1" newline bitfld.long 0x18 16. "GPIOQRSTC,GPIOQ reset" "0,1" newline bitfld.long 0x18 15. "GPIOPRSTC,GPIOP reset" "0,1" newline bitfld.long 0x18 14. "GPIOORSTC,GPIOO reset" "0,1" newline bitfld.long 0x18 13. "GPIONRSTC,GPION reset" "0,1" newline bitfld.long 0x18 7. "GPIOHRSTC,GPIOH reset" "0,1" newline bitfld.long 0x18 6. "GPIOGRSTC,GPIOG reset" "0,1" newline bitfld.long 0x18 5. "GPIOFRSTC,GPIOF reset" "0,1" newline bitfld.long 0x18 4. "GPIOERSTC,GPIOE reset" "0,1" newline bitfld.long 0x18 3. "GPIODRSTC,GPIOD reset" "0,1" newline bitfld.long 0x18 2. "GPIOCRSTC,GPIOC reset" "0,1" newline bitfld.long 0x18 1. "GPIOBRSTC,GPIOB reset" "0,1" newline bitfld.long 0x18 0. "GPIOARSTC,GPIOA reset" "0,1" line.long 0x1C "RCC_AHB5RSTCR,RCC AHB5 reset register" bitfld.long 0x1C 31. "NPURSTC,NPU reset" "0,1" newline bitfld.long 0x1C 30. "NPUCACHERSTC,NPUCACHE reset" "0,1" newline bitfld.long 0x1C 29. "OTG2RSTC,OTG2 reset" "0,1" newline bitfld.long 0x1C 28. "OTGPHY2RSTC,OTGPHY2 reset" "0,1" newline bitfld.long 0x1C 27. "OTGPHY1RSTC,OTGPHY1 reset" "0,1" newline bitfld.long 0x1C 26. "OTG1RSTC,OTG1 reset" "0,1" newline bitfld.long 0x1C 25. "ETH1RSTC,ETH1 reset" "0,1" newline bitfld.long 0x1C 24. "SYSCFGOTGHSPHY2RSTC,SYSCFGOTGHSPHY2 reset" "0,1" newline bitfld.long 0x1C 23. "SYSCFGOTGHSPHY1RSTC,SYSCFGOTGHSPHY1 reset" "0,1" newline bitfld.long 0x1C 20. "GPURSTC,GPU reset" "0,1" newline bitfld.long 0x1C 19. "GFXMMURSTC,GFXMMU reset" "0,1" newline bitfld.long 0x1C 18. "MCE4RSTC,MCE4 reset" "0,1" newline bitfld.long 0x1C 17. "XSPI3RSTC,XSPI3 reset" "0,1" newline bitfld.long 0x1C 13. "XSPIMRSTC,XSPIM reset" "0,1" newline bitfld.long 0x1C 12. "XSPI2RSTC,XSPI2 reset" "0,1" newline bitfld.long 0x1C 8. "SDMMC1RSTC,SDMMC1 reset" "0,1" newline bitfld.long 0x1C 7. "SDMMC2RSTC,SDMMC2 reset" "0,1" newline bitfld.long 0x1C 6. "PSSIRSTC,PSSI reset" "0,1" newline bitfld.long 0x1C 5. "XSPI1RSTC,XSPI1 reset" "0,1" newline bitfld.long 0x1C 4. "FMCRSTC,FMC reset" "0,1" newline bitfld.long 0x1C 3. "JPEGRSTC,JPEG reset" "0,1" newline bitfld.long 0x1C 1. "DMA2DRSTC,DMA2D reset" "0,1" newline bitfld.long 0x1C 0. "HPDMA1RSTC,HPDMA1 reset" "0,1" line.long 0x20 "RCC_APB1LRSTCR,RCC APB1L reset register" bitfld.long 0x20 31. "UART8RSTC,UART8 reset" "0,1" newline bitfld.long 0x20 30. "UART7RSTC,UART7 reset" "0,1" newline bitfld.long 0x20 25. "I3C2RSTC,I3C2 reset" "0,1" newline bitfld.long 0x20 24. "I3C1RSTC,I3C1 reset" "0,1" newline bitfld.long 0x20 23. "I2C3RSTC,I2C3 reset" "0,1" newline bitfld.long 0x20 22. "I2C2RSTC,I2C2 reset" "0,1" newline bitfld.long 0x20 21. "I2C1RSTC,I2C1 reset" "0,1" newline bitfld.long 0x20 20. "UART5RSTC,UART5 reset" "0,1" newline bitfld.long 0x20 19. "UART4RSTC,UART4 reset" "0,1" newline bitfld.long 0x20 18. "USART3RSTC,USART3 reset" "0,1" newline bitfld.long 0x20 17. "USART2RSTC,USART2 reset" "0,1" newline bitfld.long 0x20 16. "SPDIFRX1RSTC,SPDIFRX1 reset" "0,1" newline bitfld.long 0x20 15. "SPI3RSTC,SPI3 reset" "0,1" newline bitfld.long 0x20 14. "SPI2RSTC,SPI2 reset" "0,1" newline bitfld.long 0x20 13. "TIM11RSTC,TIM11 reset" "0,1" newline bitfld.long 0x20 12. "TIM10RSTC,TIM10 reset" "0,1" newline bitfld.long 0x20 11. "WWDGRSTC,WWDG reset" "0,1" newline bitfld.long 0x20 9. "LPTIM1RSTC,LPTIM1 reset" "0,1" newline bitfld.long 0x20 8. "TIM14RSTC,TIM14 reset" "0,1" newline bitfld.long 0x20 7. "TIM13RSTC,TIM13 reset" "0,1" newline bitfld.long 0x20 6. "TIM12RSTC,TIM12 reset" "0,1" newline bitfld.long 0x20 5. "TIM7RSTC,TIM7 reset" "0,1" newline bitfld.long 0x20 4. "TIM6RSTC,TIM6 reset" "0,1" newline bitfld.long 0x20 3. "TIM5RSTC,TIM5 reset" "0,1" newline bitfld.long 0x20 2. "TIM4RSTC,TIM4 reset" "0,1" newline bitfld.long 0x20 1. "TIM3RSTC,TIM3 reset" "0,1" newline bitfld.long 0x20 0. "TIM2RSTC,TIM2 reset" "0,1" line.long 0x24 "RCC_APB1HRSTCR,RCC APB1H reset register" bitfld.long 0x24 18. "UCPD1RSTC,UCPD1 reset" "0,1" newline bitfld.long 0x24 8. "FDCANRSTC,FDCAN reset" "0,1" newline bitfld.long 0x24 5. "MDIOSRSTC,MDIOS reset" "0,1" line.long 0x28 "RCC_APB2RSTCR,RCC APB2 reset register" bitfld.long 0x28 22. "SAI2RSTC,SAI2 reset" "0,1" newline bitfld.long 0x28 21. "SAI1RSTC,SAI1 reset" "0,1" newline bitfld.long 0x28 20. "SPI5RSTC,SPI5 reset" "0,1" newline bitfld.long 0x28 19. "TIM9RSTC,TIM9 reset" "0,1" newline bitfld.long 0x28 18. "TIM17RSTC,TIM17 reset" "0,1" newline bitfld.long 0x28 17. "TIM16RSTC,TIM16 reset" "0,1" newline bitfld.long 0x28 16. "TIM15RSTC,TIM15 reset" "0,1" newline bitfld.long 0x28 15. "TIM18RSTC,TIM18 reset" "0,1" newline bitfld.long 0x28 13. "SPI4RSTC,SPI4 reset" "0,1" newline bitfld.long 0x28 12. "SPI1RSTC,SPI1 reset" "0,1" newline bitfld.long 0x28 7. "USART10RSTC,USART10 reset" "0,1" newline bitfld.long 0x28 6. "UART9RSTC,UART9 reset" "0,1" newline bitfld.long 0x28 5. "USART6RSTC,USART6 reset" "0,1" newline bitfld.long 0x28 4. "USART1RSTC,USART1 reset" "0,1" newline bitfld.long 0x28 1. "TIM8RSTC,TIM8 reset" "0,1" newline bitfld.long 0x28 0. "TIM1RSTC,TIM1 reset" "0,1" wgroup.long 0x1234++0x8B line.long 0x0 "RCC_APB4LRSTCR,RCC APB4L reset register" bitfld.long 0x0 31. "SERFRSTC,SERF reset" "0,1" newline bitfld.long 0x0 23. "R2GNPURSTC,R2GNPU reset" "0,1" newline bitfld.long 0x0 22. "R2GRETRSTC,R2GRET reset" "0,1" newline bitfld.long 0x0 16. "RTCRSTC,RTC reset" "0,1" newline bitfld.long 0x0 15. "VREFBUFRSTC,VREFBUF reset" "0,1" newline bitfld.long 0x0 12. "LPTIM5RSTC,LPTIM5 reset" "0,1" newline bitfld.long 0x0 11. "LPTIM4RSTC,LPTIM4 reset" "0,1" newline bitfld.long 0x0 10. "LPTIM3RSTC,LPTIM3 reset" "0,1" newline bitfld.long 0x0 9. "LPTIM2RSTC,LPTIM2 reset" "0,1" newline bitfld.long 0x0 7. "I2C4RSTC,I2C4 reset" "0,1" newline bitfld.long 0x0 5. "SPI6RSTC,SPI6 reset" "0,1" newline bitfld.long 0x0 3. "LPUART1RSTC,LPUART1 reset" "0,1" newline bitfld.long 0x0 2. "HDPRSTC,HDP reset" "0,1" line.long 0x4 "RCC_APB4HRSTCR,RCC APB4H reset register" bitfld.long 0x4 4. "BUSPERFMRSTC,BUSPERFM reset" "0,1" newline bitfld.long 0x4 2. "DTSRSTC,DTS reset" "0,1" newline bitfld.long 0x4 0. "SYSCFGRSTC,SYSCFG reset" "0,1" line.long 0x8 "RCC_APB5RSTCR,RCC APB5 reset register" bitfld.long 0x8 6. "CSIRSTC,CSI reset" "0,1" newline bitfld.long 0x8 5. "VENCRSTC,VENC reset" "0,1" newline bitfld.long 0x8 4. "GFXTIMRSTC,GFXTIM reset" "0,1" newline bitfld.long 0x8 2. "DCMIPPRSTC,DCMIPP reset" "0,1" newline bitfld.long 0x8 1. "LTDCRSTC,LTDC reset" "0,1" line.long 0xC "RCC_DIVENCR,RCC divider enable register" bitfld.long 0xC 19. "IC20ENC,IC20 enable" "0,1" newline bitfld.long 0xC 18. "IC19ENC,IC19 enable" "0,1" newline bitfld.long 0xC 17. "IC18ENC,IC18 enable" "0,1" newline bitfld.long 0xC 16. "IC17ENC,IC17 enable" "0,1" newline bitfld.long 0xC 15. "IC16ENC,IC16 enable" "0,1" newline bitfld.long 0xC 14. "IC15ENC,IC15 enable" "0,1" newline bitfld.long 0xC 13. "IC14ENC,IC14 enable" "0,1" newline bitfld.long 0xC 12. "IC13ENC,IC13 enable" "0,1" newline bitfld.long 0xC 11. "IC12ENC,IC12 enable" "0,1" newline bitfld.long 0xC 10. "IC11ENC,IC11 enable" "0,1" newline bitfld.long 0xC 9. "IC10ENC,IC10 enable" "0,1" newline bitfld.long 0xC 8. "IC9ENC,IC9 enable" "0,1" newline bitfld.long 0xC 7. "IC8ENC,IC8 enable" "0,1" newline bitfld.long 0xC 6. "IC7ENC,IC7 enable" "0,1" newline bitfld.long 0xC 5. "IC6ENC,IC6 enable" "0,1" newline bitfld.long 0xC 4. "IC5ENC,IC5 enable" "0,1" newline bitfld.long 0xC 3. "IC4ENC,IC4 enable" "0,1" newline bitfld.long 0xC 2. "IC3ENC,IC3 enable" "0,1" newline bitfld.long 0xC 1. "IC2ENC,IC2 enable" "0,1" newline bitfld.long 0xC 0. "IC1ENC,IC1 enable" "0,1" line.long 0x10 "RCC_BUSENCR,RCC bus enable register" bitfld.long 0x10 12. "APB5ENC,APB5 enable" "0,1" newline bitfld.long 0x10 11. "APB4ENC,APB4 enable" "0,1" newline bitfld.long 0x10 10. "APB3ENC,APB3 enable" "0,1" newline bitfld.long 0x10 9. "APB2ENC,APB2 enable" "0,1" newline bitfld.long 0x10 8. "APB1ENC,APB1 enable" "0,1" newline bitfld.long 0x10 7. "AHB5ENC,AHB5 enable" "0,1" newline bitfld.long 0x10 6. "AHB4ENC,AHB4 enable" "0,1" newline bitfld.long 0x10 5. "AHB3ENC,AHB3 enable" "0,1" newline bitfld.long 0x10 4. "AHB2ENC,AHB2 enable" "0,1" newline bitfld.long 0x10 3. "AHB1ENC,AHB1 enable" "0,1" newline bitfld.long 0x10 2. "AHBMENC,AHBM enable" "0,1" newline bitfld.long 0x10 1. "ACLKNCENC,ACLKNC enable" "0,1" newline bitfld.long 0x10 0. "ACLKNENC,ACLKN enable" "0,1" line.long 0x14 "RCC_MISCENCR,RCC miscellaneous enable register" bitfld.long 0x14 6. "PERENC,PER enable" "0,1" newline bitfld.long 0x14 3. "XSPIPHYCOMPENC,XSPIPHYCOMP enable" "0,1" newline bitfld.long 0x14 2. "MCO2ENC,MCO2 enable" "0,1" newline bitfld.long 0x14 1. "MCO1ENC,MCO1 enable" "0,1" newline bitfld.long 0x14 0. "DBGENC,DBG enable" "0,1" line.long 0x18 "RCC_MEMENCR,RCC memory enable register" bitfld.long 0x18 12. "BOOTROMENC,BOOTROM enable" "0,1" newline bitfld.long 0x18 11. "VENCRAMENC,VENCRAM enable" "0,1" newline bitfld.long 0x18 10. "NPUCACHERAMENC,NPUCACHERAM enable" "0,1" newline bitfld.long 0x18 9. "FLEXRAMENC,FLEXRAM enable" "0,1" newline bitfld.long 0x18 8. "AXISRAM2ENC,AXISRAM2 enable" "0,1" newline bitfld.long 0x18 7. "AXISRAM1ENC,AXISRAM1 enable" "0,1" newline bitfld.long 0x18 6. "BKPSRAMENC,BKPSRAM enable" "0,1" newline bitfld.long 0x18 5. "AHBSRAM2ENC,AHBSRAM2 enable" "0,1" newline bitfld.long 0x18 4. "AHBSRAM1ENC,AHBSRAM1 enable" "0,1" newline bitfld.long 0x18 3. "AXISRAM6ENC,AXISRAM6 enable" "0,1" newline bitfld.long 0x18 2. "AXISRAM5ENC,AXISRAM5 enable" "0,1" newline bitfld.long 0x18 1. "AXISRAM4ENC,AXISRAM4 enable" "0,1" newline bitfld.long 0x18 0. "AXISRAM3ENC,AXISRAM3 enable" "0,1" line.long 0x1C "RCC_AHB1ENCR,RCC AHB1 enable register" bitfld.long 0x1C 5. "ADC12ENC,ADC12 enable" "0,1" newline bitfld.long 0x1C 4. "GPDMA1ENC,GPDMA1 enable" "0,1" line.long 0x20 "RCC_AHB2ENCR,RCC AHB2 enable register" bitfld.long 0x20 17. "ADF1ENC,ADF1 enable" "0,1" newline bitfld.long 0x20 16. "MDF1ENC,MDF1 enable" "0,1" newline bitfld.long 0x20 12. "RAMCFGENC,RAMCFG enable" "0,1" line.long 0x24 "RCC_AHB3ENCR,RCC AHB3 enable register" bitfld.long 0x24 14. "RISAFENC,RISAF enable" "0,1" newline bitfld.long 0x24 10. "IACENC,IAC enable" "0,1" newline bitfld.long 0x24 9. "RIFSCENC,RIFSC enable" "0,1" newline bitfld.long 0x24 8. "PKAENC,PKA enable" "0,1" newline bitfld.long 0x24 4. "SAESENC,SAES enable" "0,1" newline bitfld.long 0x24 2. "CRYPENC,CRYP enable" "0,1" newline bitfld.long 0x24 1. "HASHENC,HASH enable" "0,1" newline bitfld.long 0x24 0. "RNGENC,RNG enable" "0,1" line.long 0x28 "RCC_AHB4ENCR,RCC AHB4 enable register" bitfld.long 0x28 19. "CRCENC,CRC enable" "0,1" newline bitfld.long 0x28 18. "PWRENC,PWR enable" "0,1" newline bitfld.long 0x28 16. "GPIOQENC,GPIOQ enable" "0,1" newline bitfld.long 0x28 15. "GPIOPENC,GPIOP enable" "0,1" newline bitfld.long 0x28 14. "GPIOOENC,GPIOO enable" "0,1" newline bitfld.long 0x28 13. "GPIONENC,GPION enable" "0,1" newline bitfld.long 0x28 7. "GPIOHENC,GPIOH enable" "0,1" newline bitfld.long 0x28 6. "GPIOGENC,GPIOG enable" "0,1" newline bitfld.long 0x28 5. "GPIOFENC,GPIOF enable" "0,1" newline bitfld.long 0x28 4. "GPIOEENC,GPIOE enable" "0,1" newline bitfld.long 0x28 3. "GPIODENC,GPIOD enable" "0,1" newline bitfld.long 0x28 2. "GPIOCENC,GPIOC enable" "0,1" newline bitfld.long 0x28 1. "GPIOBENC,GPIOB enable" "0,1" newline bitfld.long 0x28 0. "GPIOAENC,GPIOA enable" "0,1" line.long 0x2C "RCC_AHB5ENCR,RCC AHB5 enable register" bitfld.long 0x2C 31. "NPUENC,NPU enable" "0,1" newline bitfld.long 0x2C 30. "NPUCACHEENC,NPUCACHE enable" "0,1" newline bitfld.long 0x2C 29. "OTG2ENC,OTG2 enable" "0,1" newline bitfld.long 0x2C 28. "OTGPHY2ENC,OTGPHY2 enable" "0,1" newline bitfld.long 0x2C 27. "OTGPHY1ENC,OTGPHY1 enable" "0,1" newline bitfld.long 0x2C 26. "OTG1ENC,OTG1 enable" "0,1" newline bitfld.long 0x2C 25. "ETH1ENC,ETH1 enable" "0,1" newline bitfld.long 0x2C 24. "ETH1RXENC,ETH1RX enable" "0,1" newline bitfld.long 0x2C 23. "ETH1TXENC,ETH1TX enable" "0,1" newline bitfld.long 0x2C 22. "ETH1MACENC,ETH1MAC enable" "0,1" newline bitfld.long 0x2C 20. "GPUENC,GPU enable" "0,1" newline bitfld.long 0x2C 19. "GFXMMUENC,GFXMMU enable" "0,1" newline bitfld.long 0x2C 18. "MCE4ENC,MCE4 enable" "0,1" newline bitfld.long 0x2C 17. "XSPI3ENC,XSPI3 enable" "0,1" newline bitfld.long 0x2C 16. "MCE3ENC,MCE3 enable" "0,1" newline bitfld.long 0x2C 15. "MCE2ENC,MCE2 enable" "0,1" newline bitfld.long 0x2C 14. "MCE1ENC,MCE1 enable" "0,1" newline bitfld.long 0x2C 13. "XSPIMENC,XSPIM enable" "0,1" newline bitfld.long 0x2C 12. "XSPI2ENC,XSPI2 enable" "0,1" newline bitfld.long 0x2C 8. "SDMMC1ENC,SDMMC1 enable" "0,1" newline bitfld.long 0x2C 7. "SDMMC2ENC,SDMMC2 enable" "0,1" newline bitfld.long 0x2C 6. "PSSIENC,PSSI enable" "0,1" newline bitfld.long 0x2C 5. "XSPI1ENC,XSPI1 enable" "0,1" newline bitfld.long 0x2C 4. "FMCENC,FMC enable" "0,1" newline bitfld.long 0x2C 3. "JPEGENC,JPEG enable" "0,1" newline bitfld.long 0x2C 1. "DMA2DENC,DMA2D enable" "0,1" newline bitfld.long 0x2C 0. "HPDMA1ENC,HPDMA1 enable" "0,1" line.long 0x30 "RCC_APB1LENCR,RCC APB1L enable register" bitfld.long 0x30 31. "UART8ENC,UART8 enable" "0,1" newline bitfld.long 0x30 30. "UART7ENC,UART7 enable" "0,1" newline bitfld.long 0x30 25. "I3C2ENC,I3C2 enable" "0,1" newline bitfld.long 0x30 24. "I3C1ENC,I3C1 enable" "0,1" newline bitfld.long 0x30 23. "I2C3ENC,I2C3 enable" "0,1" newline bitfld.long 0x30 22. "I2C2ENC,I2C2 enable" "0,1" newline bitfld.long 0x30 21. "I2C1ENC,I2C1 enable" "0,1" newline bitfld.long 0x30 20. "UART5ENC,UART5 enable" "0,1" newline bitfld.long 0x30 19. "UART4ENC,UART4 enable" "0,1" newline bitfld.long 0x30 18. "USART3ENC,USART3 enable" "0,1" newline bitfld.long 0x30 17. "USART2ENC,USART2 enable" "0,1" newline bitfld.long 0x30 16. "SPDIFRX1ENC,SPDIFRX1 enable" "0,1" newline bitfld.long 0x30 15. "SPI3ENC,SPI3 enable" "0,1" newline bitfld.long 0x30 14. "SPI2ENC,SPI2 enable" "0,1" newline bitfld.long 0x30 13. "TIM11ENC,TIM11 enable" "0,1" newline bitfld.long 0x30 12. "TIM10ENC,TIM10 enable" "0,1" newline bitfld.long 0x30 9. "LPTIM1ENC,LPTIM1 enable" "0,1" newline bitfld.long 0x30 8. "TIM14ENC,TIM14 enable" "0,1" newline bitfld.long 0x30 7. "TIM13ENC,TIM13 enable" "0,1" newline bitfld.long 0x30 6. "TIM12ENC,TIM12 enable" "0,1" newline bitfld.long 0x30 5. "TIM7ENC,TIM7 enable" "0,1" newline bitfld.long 0x30 4. "TIM6ENC,TIM6 enable" "0,1" newline bitfld.long 0x30 3. "TIM5ENC,TIM5 enable" "0,1" newline bitfld.long 0x30 2. "TIM4ENC,TIM4 enable" "0,1" newline bitfld.long 0x30 1. "TIM3ENC,TIM3 enable" "0,1" newline bitfld.long 0x30 0. "TIM2ENC,TIM2 enable" "0,1" line.long 0x34 "RCC_APB1HENCR,RCC APB1H enable register" bitfld.long 0x34 18. "UCPD1ENC,UCPD1 enable" "0,1" newline bitfld.long 0x34 8. "FDCANENC,FDCAN enable" "0,1" newline bitfld.long 0x34 5. "MDIOSENC,MDIOS enable" "0,1" line.long 0x38 "RCC_APB2ENCR,RCC APB2 enable register" bitfld.long 0x38 22. "SAI2ENC,SAI2 enable" "0,1" newline bitfld.long 0x38 21. "SAI1ENC,SAI1 enable" "0,1" newline bitfld.long 0x38 20. "SPI5ENC,SPI5 enable" "0,1" newline bitfld.long 0x38 19. "TIM9ENC,TIM9 enable" "0,1" newline bitfld.long 0x38 18. "TIM17ENC,TIM17 enable" "0,1" newline bitfld.long 0x38 17. "TIM16ENC,TIM16 enable" "0,1" newline bitfld.long 0x38 16. "TIM15ENC,TIM15 enable" "0,1" newline bitfld.long 0x38 15. "TIM18ENC,TIM18 enable" "0,1" newline bitfld.long 0x38 13. "SPI4ENC,SPI4 enable" "0,1" newline bitfld.long 0x38 12. "SPI1ENC,SPI1 enable" "0,1" newline bitfld.long 0x38 7. "USART10ENC,USART10 enable" "0,1" newline bitfld.long 0x38 6. "UART9ENC,UART9 enable" "0,1" newline bitfld.long 0x38 5. "USART6ENC,USART6 enable" "0,1" newline bitfld.long 0x38 4. "USART1ENC,USART1 enable" "0,1" newline bitfld.long 0x38 1. "TIM8ENC,TIM8 enable" "0,1" newline bitfld.long 0x38 0. "TIM1ENC,TIM1 enable" "0,1" line.long 0x3C "RCC_APB3ENCR,RCC APB3 enable register" bitfld.long 0x3C 2. "DFTENC,DFT enable" "0,1" line.long 0x40 "RCC_APB4LENCR,RCC APB4L enable register" bitfld.long 0x40 31. "SERFENC,SERF enable" "0,1" newline bitfld.long 0x40 23. "R2GNPUENC,R2GNPU enable" "0,1" newline bitfld.long 0x40 22. "R2GRETENC,R2GRET enable" "0,1" newline bitfld.long 0x40 17. "RTCAPBENC,RTCAPB enable" "0,1" newline bitfld.long 0x40 16. "RTCENC,RTC enable" "0,1" newline bitfld.long 0x40 15. "VREFBUFENC,VREFBUF enable" "0,1" newline bitfld.long 0x40 12. "LPTIM5ENC,LPTIM5 enable" "0,1" newline bitfld.long 0x40 11. "LPTIM4ENC,LPTIM4 enable" "0,1" newline bitfld.long 0x40 10. "LPTIM3ENC,LPTIM3 enable" "0,1" newline bitfld.long 0x40 9. "LPTIM2ENC,LPTIM2 enable" "0,1" newline bitfld.long 0x40 7. "I2C4ENC,I2C4 enable" "0,1" newline bitfld.long 0x40 5. "SPI6ENC,SPI6 enable" "0,1" newline bitfld.long 0x40 3. "LPUART1ENC,LPUART1 enable" "0,1" newline bitfld.long 0x40 2. "HDPENC,HDP enable" "0,1" line.long 0x44 "RCC_APB4HENCR,RCC APB4H enable register" bitfld.long 0x44 4. "BUSPERFMENC,BUSPERFM enable" "0,1" newline bitfld.long 0x44 2. "DTSENC,DTS enable" "0,1" newline bitfld.long 0x44 1. "BSECENC,BSEC enable" "0,1" newline bitfld.long 0x44 0. "SYSCFGENC,SYSCFG enable" "0,1" line.long 0x48 "RCC_APB5ENCR,RCC APB5 enable register" bitfld.long 0x48 6. "CSIENC,CSI enable" "0,1" newline bitfld.long 0x48 5. "VENCENC,VENC enable" "0,1" newline bitfld.long 0x48 4. "GFXTIMENC,GFXTIM enable" "0,1" newline bitfld.long 0x48 2. "DCMIPPENC,DCMIPP enable" "0,1" newline bitfld.long 0x48 1. "LTDCENC,LTDC enable" "0,1" line.long 0x4C "RCC_DIVLPENCR,RCC divider Sleep enable register" bitfld.long 0x4C 19. "IC20LPENC,IC20 sleep enable" "0,1" newline bitfld.long 0x4C 18. "IC19LPENC,IC19 sleep enable" "0,1" newline bitfld.long 0x4C 17. "IC18LPENC,IC18 sleep enable" "0,1" newline bitfld.long 0x4C 16. "IC17LPENC,IC17 sleep enable" "0,1" newline bitfld.long 0x4C 15. "IC16LPENC,IC16 sleep enable" "0,1" newline bitfld.long 0x4C 14. "IC15LPENC,IC15 sleep enable" "0,1" newline bitfld.long 0x4C 13. "IC14LPENC,IC14 sleep enable" "0,1" newline bitfld.long 0x4C 12. "IC13LPENC,IC13 sleep enable" "0,1" newline bitfld.long 0x4C 11. "IC12LPENC,IC12 sleep enable" "0,1" newline bitfld.long 0x4C 10. "IC11LPENC,IC11 sleep enable" "0,1" newline bitfld.long 0x4C 9. "IC10LPENC,IC10 sleep enable" "0,1" newline bitfld.long 0x4C 8. "IC9LPENC,IC9 sleep enable" "0,1" newline bitfld.long 0x4C 7. "IC8LPENC,IC8 sleep enable" "0,1" newline bitfld.long 0x4C 6. "IC7LPENC,IC7 sleep enable" "0,1" newline bitfld.long 0x4C 5. "IC6LPENC,IC6 sleep enable" "0,1" newline bitfld.long 0x4C 4. "IC5LPENC,IC5 sleep enable" "0,1" newline bitfld.long 0x4C 3. "IC4LPENC,IC4 sleep enable" "0,1" newline bitfld.long 0x4C 2. "IC3LPENC,IC3 sleep enable" "0,1" newline bitfld.long 0x4C 1. "IC2LPENC,IC2 sleep enable" "0,1" newline bitfld.long 0x4C 0. "IC1LPENC,IC1 sleep enable" "0,1" line.long 0x50 "RCC_BUSLPENCR,RCC bus Sleep enable register" bitfld.long 0x50 12. "APB5LPENC,APB5 sleep enable" "0,1" newline bitfld.long 0x50 11. "APB4LPENC,APB4 sleep enable" "0,1" newline bitfld.long 0x50 10. "APB3LPENC,APB3 sleep enable" "0,1" newline bitfld.long 0x50 9. "APB2LPENC,APB2 sleep enable" "0,1" newline bitfld.long 0x50 8. "APB1LPENC,APB1 sleep enable" "0,1" newline bitfld.long 0x50 7. "AHB5LPENC,AHB5 sleep enable" "0,1" newline bitfld.long 0x50 6. "AHB4LPENC,AHB4 sleep enable" "0,1" newline bitfld.long 0x50 5. "AHB3LPENC,AHB3 sleep enable" "0,1" newline bitfld.long 0x50 4. "AHB2LPENC,AHB2 sleep enable" "0,1" newline bitfld.long 0x50 3. "AHB1LPENC,AHB1 sleep enable" "0,1" newline bitfld.long 0x50 2. "AHBMLPENC,AHBM sleep enable" "0,1" newline bitfld.long 0x50 1. "ACLKNCLPENC,ACLKNC sleep enable" "0,1" newline bitfld.long 0x50 0. "ACLKNLPENC,ACLKN sleep enable" "0,1" line.long 0x54 "RCC_MISCLPENCR,RCC miscellaneous Sleep enable register" bitfld.long 0x54 6. "PERLPENC,PER sleep enable" "0,1" newline bitfld.long 0x54 3. "XSPIPHYCOMPLPENC,XSPIPHYCOMP sleep enable" "0,1" newline bitfld.long 0x54 0. "DBGLPENC,DBG sleep enable" "0,1" line.long 0x58 "RCC_MEMLPENCR,RCC memory Sleep enable register" bitfld.long 0x58 12. "BOOTROMLPENC,BOOTROM sleep enable" "0,1" newline bitfld.long 0x58 11. "VENCRAMLPENC,VENCRAM sleep enable" "0,1" newline bitfld.long 0x58 10. "NPUCACHERAMLPENC,NPUCACHERAM sleep enable" "0,1" newline bitfld.long 0x58 9. "FLEXRAMLPENC,FLEXRAM sleep enable" "0,1" newline bitfld.long 0x58 8. "AXISRAM2LPENC,AXISRAM2 sleep enable" "0,1" newline bitfld.long 0x58 7. "AXISRAM1LPENC,AXISRAM1 sleep enable" "0,1" newline bitfld.long 0x58 6. "BKPSRAMLPENC,BKPSRAM sleep enable" "0,1" newline bitfld.long 0x58 5. "AHBSRAM2LPENC,AHBSRAM2 sleep enable" "0,1" newline bitfld.long 0x58 4. "AHBSRAM1LPENC,AHBSRAM1 sleep enable" "0,1" newline bitfld.long 0x58 3. "AXISRAM6LPENC,AXISRAM6 sleep enable" "0,1" newline bitfld.long 0x58 2. "AXISRAM5LPENC,AXISRAM5 sleep enable" "0,1" newline bitfld.long 0x58 1. "AXISRAM4LPENC,AXISRAM4 sleep enable" "0,1" newline bitfld.long 0x58 0. "AXISRAM3LPENC,AXISRAM3 sleep enable" "0,1" line.long 0x5C "RCC_AHB1LPENCR,RCC AHB1 Sleep enable register" bitfld.long 0x5C 5. "ADC12LPENC,ADC12 sleep enable" "0,1" newline bitfld.long 0x5C 4. "GPDMA1LPENC,GPDMA1 sleep enable" "0,1" line.long 0x60 "RCC_AHB2LPENCR,RCC AHB2 Sleep enable register" bitfld.long 0x60 17. "ADF1LPENC,ADF1 sleep enable" "0,1" newline bitfld.long 0x60 16. "MDF1LPENC,MDF1 sleep enable" "0,1" newline bitfld.long 0x60 12. "RAMCFGLPENC,RAMCFG sleep enable" "0,1" line.long 0x64 "RCC_AHB3LPENCR,RCC AHB3 Sleep enable register" bitfld.long 0x64 14. "RISAFLPENC,RISAF sleep enable" "0,1" newline bitfld.long 0x64 10. "IACLPENC,IAC sleep enable" "0,1" newline bitfld.long 0x64 9. "RIFSCLPENC,RIFSC sleep enable" "0,1" newline bitfld.long 0x64 8. "PKALPENC,PKA sleep enable" "0,1" newline bitfld.long 0x64 4. "SAESLPENC,SAES sleep enable" "0,1" newline bitfld.long 0x64 2. "CRYPLPENC,CRYP sleep enable" "0,1" newline bitfld.long 0x64 1. "HASHLPENC,HASH sleep enable" "0,1" newline bitfld.long 0x64 0. "RNGLPENC,RNG sleep enable" "0,1" line.long 0x68 "RCC_AHB4LPENCR,RCC AHB4 Sleep enable register" bitfld.long 0x68 19. "CRCLPENC,CRC sleep enable" "0,1" newline bitfld.long 0x68 18. "PWRLPENC,PWR sleep enable" "0,1" newline bitfld.long 0x68 16. "GPIOQLPENC,GPIOQ sleep enable" "0,1" newline bitfld.long 0x68 15. "GPIOPLPENC,GPIOP sleep enable" "0,1" newline bitfld.long 0x68 14. "GPIOOLPENC,GPIOO sleep enable" "0,1" newline bitfld.long 0x68 13. "GPIONLPENC,GPION sleep enable" "0,1" newline bitfld.long 0x68 7. "GPIOHLPENC,GPIOH sleep enable" "0,1" newline bitfld.long 0x68 6. "GPIOGLPENC,GPIOG sleep enable" "0,1" newline bitfld.long 0x68 5. "GPIOFLPENC,GPIOF sleep enable" "0,1" newline bitfld.long 0x68 4. "GPIOELPENC,GPIOE sleep enable" "0,1" newline bitfld.long 0x68 3. "GPIODLPENC,GPIOD sleep enable" "0,1" newline bitfld.long 0x68 2. "GPIOCLPENC,GPIOC sleep enable" "0,1" newline bitfld.long 0x68 1. "GPIOBLPENC,GPIOB sleep enable" "0,1" newline bitfld.long 0x68 0. "GPIOALPENC,GPIOA sleep enable" "0,1" line.long 0x6C "RCC_AHB5LPENCR,RCC AHB5 Sleep enable register" bitfld.long 0x6C 31. "NPULPENC,NPU sleep enable" "0,1" newline bitfld.long 0x6C 30. "NPUCACHELPENC,NPUCACHE sleep enable" "0,1" newline bitfld.long 0x6C 29. "OTG2LPENC,OTG2 sleep enable" "0,1" newline bitfld.long 0x6C 28. "OTGPHY2LPENC,OTGPHY2 sleep enable" "0,1" newline bitfld.long 0x6C 27. "OTGPHY1LPENC,OTGPHY1 sleep enable" "0,1" newline bitfld.long 0x6C 26. "OTG1LPENC,OTG1 sleep enable" "0,1" newline bitfld.long 0x6C 25. "ETH1LPENC,ETH1 sleep enable" "0,1" newline bitfld.long 0x6C 24. "ETH1RXLPENC,ETH1RX sleep enable" "0,1" newline bitfld.long 0x6C 23. "ETH1TXLPENC,ETH1TX sleep enable" "0,1" newline bitfld.long 0x6C 22. "ETH1MACLPENC,ETH1MAC sleep enable" "0,1" newline bitfld.long 0x6C 20. "GPULPENC,GPU sleep enable" "0,1" newline bitfld.long 0x6C 19. "GFXMMULPENC,GFXMMU sleep enable" "0,1" newline bitfld.long 0x6C 18. "MCE4LPENC,MCE4 sleep enable" "0,1" newline bitfld.long 0x6C 17. "XSPI3LPENC,XSPI3 sleep enable" "0,1" newline bitfld.long 0x6C 16. "MCE3LPENC,MCE3 sleep enable" "0,1" newline bitfld.long 0x6C 15. "MCE2LPENC,MCE2 sleep enable" "0,1" newline bitfld.long 0x6C 14. "MCE1LPENC,MCE1 sleep enable" "0,1" newline bitfld.long 0x6C 13. "XSPIMLPENC,XSPIM sleep enable" "0,1" newline bitfld.long 0x6C 12. "XSPI2LPENC,XSPI2 sleep enable" "0,1" newline bitfld.long 0x6C 8. "SDMMC1LPENC,SDMMC1 sleep enable" "0,1" newline bitfld.long 0x6C 7. "SDMMC2LPENC,SDMMC2 sleep enable" "0,1" newline bitfld.long 0x6C 6. "PSSILPENC,PSSI sleep enable" "0,1" newline bitfld.long 0x6C 5. "XSPI1LPENC,XSPI1 sleep enable" "0,1" newline bitfld.long 0x6C 4. "FMCLPENC,FMC sleep enable" "0,1" newline bitfld.long 0x6C 3. "JPEGLPENC,JPEG sleep enable" "0,1" newline bitfld.long 0x6C 1. "DMA2DLPENC,DMA2D sleep enable" "0,1" newline bitfld.long 0x6C 0. "HPDMA1LPENC,HPDMA1 sleep enable" "0,1" line.long 0x70 "RCC_APB1LLPENCR,RCC APB1L Sleep enable register" bitfld.long 0x70 31. "UART8LPENC,UART8 sleep enable" "0,1" newline bitfld.long 0x70 30. "UART7LPENC,UART7 sleep enable" "0,1" newline bitfld.long 0x70 25. "I3C2LPENC,I3C2 sleep enable" "0,1" newline bitfld.long 0x70 24. "I3C1LPENC,I3C1 sleep enable" "0,1" newline bitfld.long 0x70 23. "I2C3LPENC,I2C3 sleep enable" "0,1" newline bitfld.long 0x70 22. "I2C2LPENC,I2C2 sleep enable" "0,1" newline bitfld.long 0x70 21. "I2C1LPENC,I2C1 sleep enable" "0,1" newline bitfld.long 0x70 20. "UART5LPENC,UART5 sleep enable" "0,1" newline bitfld.long 0x70 19. "UART4LPENC,UART4 sleep enable" "0,1" newline bitfld.long 0x70 18. "USART3LPENC,USART3 sleep enable" "0,1" newline bitfld.long 0x70 17. "USART2LPENC,USART2 sleep enable" "0,1" newline bitfld.long 0x70 16. "SPDIFRX1LPENC,SPDIFRX1 sleep enable" "0,1" newline bitfld.long 0x70 15. "SPI3LPENC,SPI3 sleep enable" "0,1" newline bitfld.long 0x70 14. "SPI2LPENC,SPI2 sleep enable" "0,1" newline bitfld.long 0x70 13. "TIM11LPENC,TIM11 sleep enable" "0,1" newline bitfld.long 0x70 12. "TIM10LPENC,TIM10 sleep enable" "0,1" newline bitfld.long 0x70 11. "WWDGLPENC,WWDG sleep enable" "0,1" newline bitfld.long 0x70 9. "LPTIM1LPENC,LPTIM1 sleep enable" "0,1" newline bitfld.long 0x70 8. "TIM14LPENC,TIM14 sleep enable" "0,1" newline bitfld.long 0x70 7. "TIM13LPENC,TIM13 sleep enable" "0,1" newline bitfld.long 0x70 6. "TIM12LPENC,TIM12 sleep enable" "0,1" newline bitfld.long 0x70 5. "TIM7LPENC,TIM7 sleep enable" "0,1" newline bitfld.long 0x70 4. "TIM6LPENC,TIM6 sleep enable" "0,1" newline bitfld.long 0x70 3. "TIM5LPENC,TIM5 sleep enable" "0,1" newline bitfld.long 0x70 2. "TIM4LPENC,TIM4 sleep enable" "0,1" newline bitfld.long 0x70 1. "TIM3LPENC,TIM3 sleep enable" "0,1" newline bitfld.long 0x70 0. "TIM2LPENC,TIM2 sleep enable" "0,1" line.long 0x74 "RCC_APB1HLPENCR,RCC APB1H Sleep enable register" bitfld.long 0x74 18. "UCPD1LPENC,UCPD1 sleep enable" "0,1" newline bitfld.long 0x74 8. "FDCANLPENC,FDCAN sleep enable" "0,1" newline bitfld.long 0x74 5. "MDIOSLPENC,MDIOS sleep enable" "0,1" line.long 0x78 "RCC_APB2LPENCR,RCC APB2 Sleep enable register" bitfld.long 0x78 22. "SAI2LPENC,SAI2 sleep enable" "0,1" newline bitfld.long 0x78 21. "SAI1LPENC,SAI1 sleep enable" "0,1" newline bitfld.long 0x78 20. "SPI5LPENC,SPI5 sleep enable" "0,1" newline bitfld.long 0x78 19. "TIM9LPENC,TIM9 sleep enable" "0,1" newline bitfld.long 0x78 18. "TIM17LPENC,TIM17 sleep enable" "0,1" newline bitfld.long 0x78 17. "TIM16LPENC,TIM16 sleep enable" "0,1" newline bitfld.long 0x78 16. "TIM15LPENC,TIM15 sleep enable" "0,1" newline bitfld.long 0x78 15. "TIM18LPENC,TIM18 sleep enable" "0,1" newline bitfld.long 0x78 13. "SPI4LPENC,SPI4 sleep enable" "0,1" newline bitfld.long 0x78 12. "SPI1LPENC,SPI1 sleep enable" "0,1" newline bitfld.long 0x78 7. "USART10LPENC,USART10 sleep enable" "0,1" newline bitfld.long 0x78 6. "UART9LPENC,UART9 sleep enable" "0,1" newline bitfld.long 0x78 5. "USART6LPENC,USART6 sleep enable" "0,1" newline bitfld.long 0x78 4. "USART1LPENC,USART1 sleep enable" "0,1" newline bitfld.long 0x78 1. "TIM8LPENC,TIM8 sleep enable" "0,1" newline bitfld.long 0x78 0. "TIM1LPENC,TIM1 sleep enable" "0,1" line.long 0x7C "RCC_APB3LPENCR,RCC APB3 Sleep enable register" bitfld.long 0x7C 2. "DFTLPENC,DFT sleep enable" "0,1" line.long 0x80 "RCC_APB4LLPENCR,RCC APB4L Sleep enable register" bitfld.long 0x80 31. "SERFLPENC,SERF sleep enable" "0,1" newline bitfld.long 0x80 23. "R2GNPULPENC,R2GNPU sleep enable" "0,1" newline bitfld.long 0x80 22. "R2GRETLPENC,R2GRET sleep enable" "0,1" newline bitfld.long 0x80 17. "RTCAPBLPENC,RTCAPB sleep enable" "0,1" newline bitfld.long 0x80 16. "RTCLPENC,RTC sleep enable" "0,1" newline bitfld.long 0x80 15. "VREFBUFLPENC,VREFBUF sleep enable" "0,1" newline bitfld.long 0x80 12. "LPTIM5LPENC,LPTIM5 sleep enable" "0,1" newline bitfld.long 0x80 11. "LPTIM4LPENC,LPTIM4 sleep enable" "0,1" newline bitfld.long 0x80 10. "LPTIM3LPENC,LPTIM3 sleep enable" "0,1" newline bitfld.long 0x80 9. "LPTIM2LPENC,LPTIM2 sleep enable" "0,1" newline bitfld.long 0x80 7. "I2C4LPENC,I2C4 sleep enable" "0,1" newline bitfld.long 0x80 5. "SPI6LPENC,SPI6 sleep enable" "0,1" newline bitfld.long 0x80 3. "LPUART1LPENC,LPUART1 sleep enable" "0,1" newline bitfld.long 0x80 2. "HDPLPENC,HDP sleep enable" "0,1" line.long 0x84 "RCC_APB4HLPENCR,RCC APB4H Sleep enable register" bitfld.long 0x84 4. "BUSPERFMLPENC,BUSPERFM sleep enable" "0,1" newline bitfld.long 0x84 2. "DTSLPENC,DTS sleep enable" "0,1" newline bitfld.long 0x84 1. "BSECLPENC,BSEC sleep enable" "0,1" newline bitfld.long 0x84 0. "SYSCFGLPENC,SYSCFG sleep enable" "0,1" line.long 0x88 "RCC_APB5LPENCR,RCC APB5 Sleep enable register" bitfld.long 0x88 6. "CSILPENC,CSI sleep enable" "0,1" newline bitfld.long 0x88 5. "VENCLPENC,VENC sleep enable" "0,1" newline bitfld.long 0x88 4. "GFXTIMLPENC,GFXTIM sleep enable" "0,1" newline bitfld.long 0x88 2. "DCMIPPLPENC,DCMIPP sleep enable" "0,1" newline bitfld.long 0x88 1. "LTDCLPENC,LTDC sleep enable" "0,1" wgroup.long 0x1784++0x3 line.long 0x0 "RCC_PRIVCFGCR0,RCC oscillator privilege configuration register0" bitfld.long 0x0 4. "HSEPVC,Defines the privilege protection of the HSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "HSIPVC,Defines the privilege protection of the HSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "MSIPVC,Defines the privilege protection of the MSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "LSEPVC,Defines the privilege protection of the LSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "LSIPVC,Defines the privilege protection of the LSI configuration bits (enable ready divider)." "0,1" wgroup.long 0x178C++0x3 line.long 0x0 "RCC_PUBCFGCR0,RCC oscillator public configuration register0" bitfld.long 0x0 4. "HSEPUBC,Defines the public protection of the HSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "HSIPUBC,Defines the public protection of the HSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "MSIPUBC,Defines the public protection of the MSI configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "LSEPUBC,Defines the public protection of the LSE configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "LSIPUBC,Defines the public protection of the LSI configuration bits (enable ready divider)." "0,1" wgroup.long 0x1794++0x3 line.long 0x0 "RCC_PRIVCFGCR1,RCC PLL privilege configuration register1" bitfld.long 0x0 3. "PLL4PVC,Defines the privilege protection of the PLL4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "PLL3PVC,Defines the privilege protection of the PLL3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "PLL2PVC,Defines the privilege protection of the PLL2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "PLL1PVC,Defines the privilege protection of the PLL1 configuration bits (enable ready divider)." "0,1" wgroup.long 0x179C++0x3 line.long 0x0 "RCC_PUBCFGCR1,RCC PLL public configuration register1" bitfld.long 0x0 3. "PLL4PUBC,Defines the public protection of the PLL4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "PLL3PUBC,Defines the public protection of the PLL3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "PLL2PUBC,Defines the public protection of the PLL2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "PLL1PUBC,Defines the public protection of the PLL1 configuration bits (enable ready divider)." "0,1" wgroup.long 0x17A4++0x3 line.long 0x0 "RCC_PRIVCFGCR2,RCC divider privilege configuration register2" bitfld.long 0x0 19. "IC20PVC,Defines the privilege protection of the IC20 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 18. "IC19PVC,Defines the privilege protection of the IC19 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 17. "IC18PVC,Defines the privilege protection of the IC18 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 16. "IC17PVC,Defines the privilege protection of the IC17 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 15. "IC16PVC,Defines the privilege protection of the IC16 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 14. "IC15PVC,Defines the privilege protection of the IC15 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 13. "IC14PVC,Defines the privilege protection of the IC14 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "IC13PVC,Defines the privilege protection of the IC13 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "IC12PVC,Defines the privilege protection of the IC12 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "IC11PVC,Defines the privilege protection of the IC11 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "IC10PVC,Defines the privilege protection of the IC10 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "IC9PVC,Defines the privilege protection of the IC9 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "IC8PVC,Defines the privilege protection of the IC8 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "IC7PVC,Defines the privilege protection of the IC7 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "IC6PVC,Defines the privilege protection of the IC6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "IC5PVC,Defines the privilege protection of the IC5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "IC4PVC,Defines the privilege protection of the IC4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "IC3PVC,Defines the privilege protection of the IC3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "IC2PVC,Defines the privilege protection of the IC2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "IC1PVC,Defines the privilege protection of the IC1 configuration bits (enable ready divider)." "0,1" wgroup.long 0x17AC++0x3 line.long 0x0 "RCC_PUBCFGCR2,RCC divider public configuration register2" bitfld.long 0x0 19. "IC20PUBC,Defines the public protection of the IC20 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 18. "IC19PUBC,Defines the public protection of the IC19 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 17. "IC18PUBC,Defines the public protection of the IC18 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 16. "IC17PUBC,Defines the public protection of the IC17 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 15. "IC16PUBC,Defines the public protection of the IC16 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 14. "IC15PUBC,Defines the public protection of the IC15 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 13. "IC14PUBC,Defines the public protection of the IC14 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "IC13PUBC,Defines the public protection of the IC13 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "IC12PUBC,Defines the public protection of the IC12 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "IC11PUBC,Defines the public protection of the IC11 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "IC10PUBC,Defines the public protection of the IC10 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "IC9PUBC,Defines the public protection of the IC9 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "IC8PUBC,Defines the public protection of the IC8 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "IC7PUBC,Defines the public protection of the IC7 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "IC6PUBC,Defines the public protection of the IC6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "IC5PUBC,Defines the public protection of the IC5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "IC4PUBC,Defines the public protection of the IC4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "IC3PUBC,Defines the public protection of the IC3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "IC2PUBC,Defines the public protection of the IC2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "IC1PUBC,Defines the public protection of the IC1 configuration bits (enable ready divider)." "0,1" wgroup.long 0x17B4++0x3 line.long 0x0 "RCC_PRIVCFGCR3,RCC system privilege configuration register3" bitfld.long 0x0 6. "DFTPVC,Defines the privilege protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "RSTPVC,Defines the privilege protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "INTPVC,Defines the privilege protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "PERPVC,Defines the privilege protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "BUSPVC,Defines the privilege protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "SYSPVC,Defines the privilege protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "MODPVC,Defines the privilege protection of the MOD configuration bits (enable ready divider)." "0,1" wgroup.long 0x17BC++0x3 line.long 0x0 "RCC_PUBCFGCR3,RCC system public configuration register3" bitfld.long 0x0 6. "DFTPUBC,Defines the public protection of the DFT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "RSTPUBC,Defines the public protection of the RST configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "INTPUBC,Defines the public protection of the INT configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "PERPUBC,Defines the public protection of the PER configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "BUSPUBC,Defines the public protection of the BUS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "SYSPUBC,Defines the public protection of the SYS configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "MODPUBC,Defines the public protection of the MOD configuration bits (enable ready divider)." "0,1" wgroup.long 0x17C4++0x3 line.long 0x0 "RCC_PRIVCFGCR4,RCC privilege configuration register4" bitfld.long 0x0 13. "NOCPVC,Defines the privilege protection of the NOC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "APB5PVC,Defines the privilege protection of the APB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "APB4PVC,Defines the privilege protection of the APB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "APB3PVC,Defines the privilege protection of the APB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "APB2PVC,Defines the privilege protection of the APB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "APB1PVC,Defines the privilege protection of the APB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "AHB5PVC,Defines the privilege protection of the AHB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "AHB4PVC,Defines the privilege protection of the AHB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "AHB3PVC,Defines the privilege protection of the AHB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "AHB2PVC,Defines the privilege protection of the AHB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "AHB1PVC,Defines the privilege protection of the AHB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "AHBMPVC,Defines the privilege protection of the AHBM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "ACLKNCPVC,Defines the privilege protection of the ACLKNC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "ACLKNPVC,Defines the privilege protection of the ACLKN configuration bits (enable ready divider)." "0,1" wgroup.long 0x17CC++0x7 line.long 0x0 "RCC_PUBCFGCR4,RCC public configuration register4" bitfld.long 0x0 13. "NOCPUBC,Defines the public protection of the NOC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 12. "APB5PUBC,Defines the public protection of the APB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 11. "APB4PUBC,Defines the public protection of the APB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 10. "APB3PUBC,Defines the public protection of the APB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 9. "APB2PUBC,Defines the public protection of the APB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 8. "APB1PUBC,Defines the public protection of the APB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 7. "AHB5PUBC,Defines the public protection of the AHB5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 6. "AHB4PUBC,Defines the public protection of the AHB4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 5. "AHB3PUBC,Defines the public protection of the AHB3 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 4. "AHB2PUBC,Defines the public protection of the AHB2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 3. "AHB1PUBC,Defines the public protection of the AHB1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 2. "AHBMPUBC,Defines the public protection of the AHBM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 1. "ACLKNCPUBC,Defines the public protection of the ACLKNC configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x0 0. "ACLKNPUBC,Defines the public protection of the ACLKN configuration bits (enable ready divider)." "0,1" line.long 0x4 "RCC_PUBCFGCR5,RCC public configuration register4" bitfld.long 0x4 11. "VENCRAMPUBC,Defines the public protection of the VENCRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 10. "CACHEAXIRAMPUBC,Defines the public protection of the NPUCACHERAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 9. "FLEXRAMPUBC,Defines the public protection of the FLEXRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 8. "AXISRAM2PUBC,Defines the public protection of the AXISRAM2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 7. "AXISRAM1PUBC,Defines the public protection of the AXISRAM1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 6. "BKPSRAMPUBC,Defines the public protection of the BKPSRAM configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 5. "AHBSRAM2PUBC,Defines the public protection of the AHBSRAM2 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 4. "AHBSRAM1PUBC,Defines the public protection of the AHBSRAM1 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 3. "AXISRAM6PUBC,Defines the public protection of the AXISRAM6 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 2. "AXISRAM5PUBC,Defines the public protection of the AXISRAM5 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 1. "AXISRAM4PUBC,Defines the public protection of the AXISRAM4 configuration bits (enable ready divider)." "0,1" newline bitfld.long 0x4 0. "AXISRAM3PUBC,Defines the public protection of the AXISRAM3 configuration bits (enable ready divider)." "0,1" tree.end tree.end tree "RIFSC (Resource Isolation Framework Controller)" base ad:0x0 tree "RIFSC" base ad:0x44024000 group.long 0x0++0x3 line.long 0x0 "RIFSC_RISC_CR,RIFSC RISC slave configuration register x" bitfld.long 0x0 0. "GLOCK,Global lock" "0: RIFSC RISC registers are writable.,1: All writes to RIFSC RISC registers are ignored." group.long 0x10++0x17 line.long 0x0 "RIFSC_RISC_SECCFGR0,RIFSC RISC slave security configuration register 0" bitfld.long 0x0 31. "SEC31,security configuration for peripheral 31" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 30. "SEC30,security configuration for peripheral 30" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 29. "SEC29,security configuration for peripheral 29" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 28. "SEC28,security configuration for peripheral 28" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 27. "SEC27,security configuration for peripheral 27" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 26. "SEC26,security configuration for peripheral 26" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 25. "SEC25,security configuration for peripheral 25" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 24. "SEC24,security configuration for peripheral 24" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 23. "SEC23,security configuration for peripheral 23" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 22. "SEC22,security configuration for peripheral 22" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 21. "SEC21,security configuration for peripheral 21" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 20. "SEC20,security configuration for peripheral 20" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 19. "SEC19,security configuration for peripheral 19" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 18. "SEC18,security configuration for peripheral 18" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 17. "SEC17,security configuration for peripheral 17" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 16. "SEC16,security configuration for peripheral 16" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 15. "SEC15,security configuration for peripheral 15" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 14. "SEC14,security configuration for peripheral 14" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 13. "SEC13,security configuration for peripheral 13" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 12. "SEC12,security configuration for peripheral 12" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 11. "SEC11,security configuration for peripheral 11" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 10. "SEC10,security configuration for peripheral 10" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 9. "SEC9,security configuration for peripheral 9" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 8. "SEC8,security configuration for peripheral 8" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 7. "SEC7,security configuration for peripheral 7" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 6. "SEC6,security configuration for peripheral 6" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 5. "SEC5,security configuration for peripheral 5" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 4. "SEC4,security configuration for peripheral 4" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 3. "SEC3,security configuration for peripheral 3" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 2. "SEC2,security configuration for peripheral 2" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 1. "SEC1,security configuration for peripheral 1" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 0. "SEC0,security configuration for peripheral 0" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." line.long 0x4 "RIFSC_RISC_SECCFGR1,RIFSC RISC slave security configuration register 1" bitfld.long 0x4 31. "SEC63,security configuration for peripheral 63" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 30. "SEC62,security configuration for peripheral 62" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 29. "SEC61,security configuration for peripheral 61" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 28. "SEC60,security configuration for peripheral 60" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 27. "SEC59,security configuration for peripheral 59" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 26. "SEC58,security configuration for peripheral 58" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 25. "SEC57,security configuration for peripheral 57" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 24. "SEC56,security configuration for peripheral 56" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 23. "SEC55,security configuration for peripheral 55" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 22. "SEC54,security configuration for peripheral 54" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 21. "SEC53,security configuration for peripheral 53" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 20. "SEC52,security configuration for peripheral 52" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 19. "SEC51,security configuration for peripheral 51" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 18. "SEC50,security configuration for peripheral 50" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 17. "SEC49,security configuration for peripheral 49" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 16. "SEC48,security configuration for peripheral 48" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 15. "SEC47,security configuration for peripheral 47" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 14. "SEC46,security configuration for peripheral 46" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 13. "SEC45,security configuration for peripheral 45" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 12. "SEC44,security configuration for peripheral 44" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 11. "SEC43,security configuration for peripheral 43" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 10. "SEC42,security configuration for peripheral 42" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 9. "SEC41,security configuration for peripheral 41" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 8. "SEC40,security configuration for peripheral 40" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 7. "SEC39,security configuration for peripheral 39" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 6. "SEC38,security configuration for peripheral 38" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 5. "SEC37,security configuration for peripheral 37" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 4. "SEC36,security configuration for peripheral 36" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 3. "SEC35,security configuration for peripheral 35" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 2. "SEC34,security configuration for peripheral 34" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 1. "SEC33,security configuration for peripheral 33" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 0. "SEC32,security configuration for peripheral 32" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." line.long 0x8 "RIFSC_RISC_SECCFGR2,RIFSC RISC slave security configuration register 2" bitfld.long 0x8 31. "SEC95,security configuration for peripheral 95" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 30. "SEC94,security configuration for peripheral 94" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 29. "SEC93,security configuration for peripheral 93" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 28. "SEC92,security configuration for peripheral 92" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 27. "SEC91,security configuration for peripheral 91" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 26. "SEC90,security configuration for peripheral 90" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 25. "SEC89,security configuration for peripheral 89" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 24. "SEC88,security configuration for peripheral 88" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 23. "SEC87,security configuration for peripheral 87" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 22. "SEC86,security configuration for peripheral 86" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 21. "SEC85,security configuration for peripheral 85" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 20. "SEC84,security configuration for peripheral 84" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 19. "SEC83,security configuration for peripheral 83" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 18. "SEC82,security configuration for peripheral 82" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 17. "SEC81,security configuration for peripheral 81" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 16. "SEC80,security configuration for peripheral 80" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 15. "SEC79,security configuration for peripheral 79" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 14. "SEC78,security configuration for peripheral 78" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 13. "SEC77,security configuration for peripheral 77" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 12. "SEC76,security configuration for peripheral 76" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 11. "SEC75,security configuration for peripheral 75" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 10. "SEC74,security configuration for peripheral 74" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 9. "SEC73,security configuration for peripheral 73" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 8. "SEC72,security configuration for peripheral 72" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 7. "SEC71,security configuration for peripheral 71" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 6. "SEC70,security configuration for peripheral 70" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 5. "SEC69,security configuration for peripheral 69" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 4. "SEC68,security configuration for peripheral 68" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 3. "SEC67,security configuration for peripheral 67" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 2. "SEC66,security configuration for peripheral 66" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 1. "SEC65,security configuration for peripheral 65" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 0. "SEC64,security configuration for peripheral 64" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." line.long 0xC "RIFSC_RISC_SECCFGR3,RIFSC RISC slave security configuration register 3" bitfld.long 0xC 31. "SEC127,security configuration for peripheral 127" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 30. "SEC126,security configuration for peripheral 126" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 29. "SEC125,security configuration for peripheral 125" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 28. "SEC124,security configuration for peripheral 124" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 27. "SEC123,security configuration for peripheral 123" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 26. "SEC122,security configuration for peripheral 122" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 25. "SEC121,security configuration for peripheral 121" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 24. "SEC120,security configuration for peripheral 120" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 23. "SEC119,security configuration for peripheral 119" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 22. "SEC118,security configuration for peripheral 118" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 21. "SEC117,security configuration for peripheral 117" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 20. "SEC116,security configuration for peripheral 116" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 19. "SEC115,security configuration for peripheral 115" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 18. "SEC114,security configuration for peripheral 114" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 17. "SEC113,security configuration for peripheral 113" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 16. "SEC112,security configuration for peripheral 112" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 15. "SEC111,security configuration for peripheral 111" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 14. "SEC110,security configuration for peripheral 110" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 13. "SEC109,security configuration for peripheral 109" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 12. "SEC108,security configuration for peripheral 108" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 11. "SEC107,security configuration for peripheral 107" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 10. "SEC106,security configuration for peripheral 106" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 9. "SEC105,security configuration for peripheral 105" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 8. "SEC104,security configuration for peripheral 104" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 7. "SEC103,security configuration for peripheral 103" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 6. "SEC102,security configuration for peripheral 102" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 5. "SEC101,security configuration for peripheral 101" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 4. "SEC100,security configuration for peripheral 100" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 3. "SEC99,security configuration for peripheral 99" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 2. "SEC98,security configuration for peripheral 98" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 1. "SEC97,security configuration for peripheral 97" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 0. "SEC96,security configuration for peripheral 96" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." line.long 0x10 "RIFSC_RISC_SECCFGR4,RIFSC RISC slave security configuration register 4" bitfld.long 0x10 31. "SEC159,security configuration for peripheral 159" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 30. "SEC158,security configuration for peripheral 158" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 29. "SEC157,security configuration for peripheral 157" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 28. "SEC156,security configuration for peripheral 156" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 27. "SEC155,security configuration for peripheral 155" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 26. "SEC154,security configuration for peripheral 154" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 25. "SEC153,security configuration for peripheral 153" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 24. "SEC152,security configuration for peripheral 152" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 23. "SEC151,security configuration for peripheral 151" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 22. "SEC150,security configuration for peripheral 150" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 21. "SEC149,security configuration for peripheral 149" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 20. "SEC148,security configuration for peripheral 148" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 19. "SEC147,security configuration for peripheral 147" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 18. "SEC146,security configuration for peripheral 146" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 17. "SEC145,security configuration for peripheral 145" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 16. "SEC144,security configuration for peripheral 144" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 15. "SEC143,security configuration for peripheral 143" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 14. "SEC142,security configuration for peripheral 142" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 13. "SEC141,security configuration for peripheral 141" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 12. "SEC140,security configuration for peripheral 140" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 11. "SEC139,security configuration for peripheral 139" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 10. "SEC138,security configuration for peripheral 138" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 9. "SEC137,security configuration for peripheral 137" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 8. "SEC136,security configuration for peripheral 136" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 7. "SEC135,security configuration for peripheral 135" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 6. "SEC134,security configuration for peripheral 134" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 5. "SEC133,security configuration for peripheral 133" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 4. "SEC132,security configuration for peripheral 132" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 3. "SEC131,security configuration for peripheral 131" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 2. "SEC130,security configuration for peripheral 130" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 1. "SEC129,security configuration for peripheral 129" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 0. "SEC128,security configuration for peripheral 128" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." line.long 0x14 "RIFSC_RISC_SECCFGR5,RIFSC RISC slave security configuration register 5" bitfld.long 0x14 31. "SEC191,security configuration for peripheral 191" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 30. "SEC190,security configuration for peripheral 190" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 29. "SEC189,security configuration for peripheral 189" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 28. "SEC188,security configuration for peripheral 188" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 27. "SEC187,security configuration for peripheral 187" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 26. "SEC186,security configuration for peripheral 186" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 25. "SEC185,security configuration for peripheral 185" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 24. "SEC184,security configuration for peripheral 184" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 23. "SEC183,security configuration for peripheral 183" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 22. "SEC182,security configuration for peripheral 182" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 21. "SEC181,security configuration for peripheral 181" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 20. "SEC180,security configuration for peripheral 180" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 19. "SEC179,security configuration for peripheral 179" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 18. "SEC178,security configuration for peripheral 178" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 17. "SEC177,security configuration for peripheral 177" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 16. "SEC176,security configuration for peripheral 176" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 15. "SEC175,security configuration for peripheral 175" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 14. "SEC174,security configuration for peripheral 174" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 13. "SEC173,security configuration for peripheral 173" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 12. "SEC172,security configuration for peripheral 172" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 11. "SEC171,security configuration for peripheral 171" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 10. "SEC170,security configuration for peripheral 170" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 9. "SEC169,security configuration for peripheral 169" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 8. "SEC168,security configuration for peripheral 168" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 7. "SEC167,security configuration for peripheral 167" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 6. "SEC166,security configuration for peripheral 166" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 5. "SEC165,security configuration for peripheral 165" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 4. "SEC164,security configuration for peripheral 164" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 3. "SEC163,security configuration for peripheral 163" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 2. "SEC162,security configuration for peripheral 162" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 1. "SEC161,security configuration for peripheral 161" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 0. "SEC160,security configuration for peripheral 160" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." group.long 0x30++0x17 line.long 0x0 "RIFSC_RISC_PRIVCFGR0,RIFSC RISFC slave privileged register 0" bitfld.long 0x0 31. "PRIV31,privileged-only access permission for peripheral 31" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 30. "PRIV30,privileged-only access permission for peripheral 30" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 29. "PRIV29,privileged-only access permission for peripheral 29" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 28. "PRIV28,privileged-only access permission for peripheral 28" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 27. "PRIV27,privileged-only access permission for peripheral 27" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 26. "PRIV26,privileged-only access permission for peripheral 26" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 25. "PRIV25,privileged-only access permission for peripheral 25" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 24. "PRIV24,privileged-only access permission for peripheral 24" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 23. "PRIV23,privileged-only access permission for peripheral 23" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 22. "PRIV22,privileged-only access permission for peripheral 22" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 21. "PRIV21,privileged-only access permission for peripheral 21" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 20. "PRIV20,privileged-only access permission for peripheral 20" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 19. "PRIV19,privileged-only access permission for peripheral 19" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 18. "PRIV18,privileged-only access permission for peripheral 18" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 17. "PRIV17,privileged-only access permission for peripheral 17" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 16. "PRIV16,privileged-only access permission for peripheral 16" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 15. "PRIV15,privileged-only access permission for peripheral 15" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 14. "PRIV14,privileged-only access permission for peripheral 14" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 13. "PRIV13,privileged-only access permission for peripheral 13" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 12. "PRIV12,privileged-only access permission for peripheral 12" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 11. "PRIV11,privileged-only access permission for peripheral 11" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 10. "PRIV10,privileged-only access permission for peripheral 10" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 9. "PRIV9,privileged-only access permission for peripheral 9" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 8. "PRIV8,privileged-only access permission for peripheral 8" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 7. "PRIV7,privileged-only access permission for peripheral 7" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 6. "PRIV6,privileged-only access permission for peripheral 6" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 5. "PRIV5,privileged-only access permission for peripheral 5" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 4. "PRIV4,privileged-only access permission for peripheral 4" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 3. "PRIV3,privileged-only access permission for peripheral 3" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 2. "PRIV2,privileged-only access permission for peripheral 2" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 1. "PRIV1,privileged-only access permission for peripheral 1" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 0. "PRIV0,privileged-only access permission for peripheral 0" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." line.long 0x4 "RIFSC_RISC_PRIVCFGR1,RIFSC RISFC slave privileged register 1" bitfld.long 0x4 31. "PRIV63,privileged-only access permission for peripheral 63" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 30. "PRIV62,privileged-only access permission for peripheral 62" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 29. "PRIV61,privileged-only access permission for peripheral 61" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 28. "PRIV60,privileged-only access permission for peripheral 60" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 27. "PRIV59,privileged-only access permission for peripheral 59" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 26. "PRIV58,privileged-only access permission for peripheral 58" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 25. "PRIV57,privileged-only access permission for peripheral 57" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 24. "PRIV56,privileged-only access permission for peripheral 56" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 23. "PRIV55,privileged-only access permission for peripheral 55" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 22. "PRIV54,privileged-only access permission for peripheral 54" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 21. "PRIV53,privileged-only access permission for peripheral 53" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 20. "PRIV52,privileged-only access permission for peripheral 52" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 19. "PRIV51,privileged-only access permission for peripheral 51" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 18. "PRIV50,privileged-only access permission for peripheral 50" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 17. "PRIV49,privileged-only access permission for peripheral 49" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 16. "PRIV48,privileged-only access permission for peripheral 48" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 15. "PRIV47,privileged-only access permission for peripheral 47" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 14. "PRIV46,privileged-only access permission for peripheral 46" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 13. "PRIV45,privileged-only access permission for peripheral 45" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 12. "PRIV44,privileged-only access permission for peripheral 44" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 11. "PRIV43,privileged-only access permission for peripheral 43" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 10. "PRIV42,privileged-only access permission for peripheral 42" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 9. "PRIV41,privileged-only access permission for peripheral 41" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 8. "PRIV40,privileged-only access permission for peripheral 40" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 7. "PRIV39,privileged-only access permission for peripheral 39" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 6. "PRIV38,privileged-only access permission for peripheral 38" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 5. "PRIV37,privileged-only access permission for peripheral 37" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 4. "PRIV36,privileged-only access permission for peripheral 36" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 3. "PRIV35,privileged-only access permission for peripheral 35" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 2. "PRIV34,privileged-only access permission for peripheral 34" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 1. "PRIV33,privileged-only access permission for peripheral 33" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 0. "PRIV32,privileged-only access permission for peripheral 32" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." line.long 0x8 "RIFSC_RISC_PRIVCFGR2,RIFSC RISFC slave privileged register 2" bitfld.long 0x8 31. "PRIV95,privileged-only access permission for peripheral 95" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 30. "PRIV94,privileged-only access permission for peripheral 94" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 29. "PRIV93,privileged-only access permission for peripheral 93" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 28. "PRIV92,privileged-only access permission for peripheral 92" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 27. "PRIV91,privileged-only access permission for peripheral 91" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 26. "PRIV90,privileged-only access permission for peripheral 90" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 25. "PRIV89,privileged-only access permission for peripheral 89" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 24. "PRIV88,privileged-only access permission for peripheral 88" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 23. "PRIV87,privileged-only access permission for peripheral 87" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 22. "PRIV86,privileged-only access permission for peripheral 86" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 21. "PRIV85,privileged-only access permission for peripheral 85" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 20. "PRIV84,privileged-only access permission for peripheral 84" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 19. "PRIV83,privileged-only access permission for peripheral 83" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 18. "PRIV82,privileged-only access permission for peripheral 82" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 17. "PRIV81,privileged-only access permission for peripheral 81" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 16. "PRIV80,privileged-only access permission for peripheral 80" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 15. "PRIV79,privileged-only access permission for peripheral 79" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 14. "PRIV78,privileged-only access permission for peripheral 78" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 13. "PRIV77,privileged-only access permission for peripheral 77" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 12. "PRIV76,privileged-only access permission for peripheral 76" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 11. "PRIV75,privileged-only access permission for peripheral 75" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 10. "PRIV74,privileged-only access permission for peripheral 74" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 9. "PRIV73,privileged-only access permission for peripheral 73" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 8. "PRIV72,privileged-only access permission for peripheral 72" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 7. "PRIV71,privileged-only access permission for peripheral 71" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 6. "PRIV70,privileged-only access permission for peripheral 70" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 5. "PRIV69,privileged-only access permission for peripheral 69" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 4. "PRIV68,privileged-only access permission for peripheral 68" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 3. "PRIV67,privileged-only access permission for peripheral 67" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 2. "PRIV66,privileged-only access permission for peripheral 66" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 1. "PRIV65,privileged-only access permission for peripheral 65" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 0. "PRIV64,privileged-only access permission for peripheral 64" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." line.long 0xC "RIFSC_RISC_PRIVCFGR3,RIFSC RISFC slave privileged register 3" bitfld.long 0xC 31. "PRIV127,privileged-only access permission for peripheral 127" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 30. "PRIV126,privileged-only access permission for peripheral 126" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 29. "PRIV125,privileged-only access permission for peripheral 125" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 28. "PRIV124,privileged-only access permission for peripheral 124" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 27. "PRIV123,privileged-only access permission for peripheral 123" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 26. "PRIV122,privileged-only access permission for peripheral 122" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 25. "PRIV121,privileged-only access permission for peripheral 121" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 24. "PRIV120,privileged-only access permission for peripheral 120" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 23. "PRIV119,privileged-only access permission for peripheral 119" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 22. "PRIV118,privileged-only access permission for peripheral 118" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 21. "PRIV117,privileged-only access permission for peripheral 117" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 20. "PRIV116,privileged-only access permission for peripheral 116" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 19. "PRIV115,privileged-only access permission for peripheral 115" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 18. "PRIV114,privileged-only access permission for peripheral 114" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 17. "PRIV113,privileged-only access permission for peripheral 113" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 16. "PRIV112,privileged-only access permission for peripheral 112" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 15. "PRIV111,privileged-only access permission for peripheral 111" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 14. "PRIV110,privileged-only access permission for peripheral 110" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 13. "PRIV109,privileged-only access permission for peripheral 109" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 12. "PRIV108,privileged-only access permission for peripheral 108" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 11. "PRIV107,privileged-only access permission for peripheral 107" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 10. "PRIV106,privileged-only access permission for peripheral 106" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 9. "PRIV105,privileged-only access permission for peripheral 105" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 8. "PRIV104,privileged-only access permission for peripheral 104" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 7. "PRIV103,privileged-only access permission for peripheral 103" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 6. "PRIV102,privileged-only access permission for peripheral 102" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 5. "PRIV101,privileged-only access permission for peripheral 101" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 4. "PRIV100,privileged-only access permission for peripheral 100" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 3. "PRIV99,privileged-only access permission for peripheral 99" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 2. "PRIV98,privileged-only access permission for peripheral 98" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 1. "PRIV97,privileged-only access permission for peripheral 97" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 0. "PRIV96,privileged-only access permission for peripheral 96" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." line.long 0x10 "RIFSC_RISC_PRIVCFGR4,RIFSC RISFC slave privileged register 4" bitfld.long 0x10 31. "PRIV159,privileged-only access permission for peripheral 159" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 30. "PRIV158,privileged-only access permission for peripheral 158" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 29. "PRIV157,privileged-only access permission for peripheral 157" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 28. "PRIV156,privileged-only access permission for peripheral 156" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 27. "PRIV155,privileged-only access permission for peripheral 155" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 26. "PRIV154,privileged-only access permission for peripheral 154" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 25. "PRIV153,privileged-only access permission for peripheral 153" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 24. "PRIV152,privileged-only access permission for peripheral 152" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 23. "PRIV151,privileged-only access permission for peripheral 151" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 22. "PRIV150,privileged-only access permission for peripheral 150" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 21. "PRIV149,privileged-only access permission for peripheral 149" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 20. "PRIV148,privileged-only access permission for peripheral 148" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 19. "PRIV147,privileged-only access permission for peripheral 147" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 18. "PRIV146,privileged-only access permission for peripheral 146" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 17. "PRIV145,privileged-only access permission for peripheral 145" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 16. "PRIV144,privileged-only access permission for peripheral 144" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 15. "PRIV143,privileged-only access permission for peripheral 143" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 14. "PRIV142,privileged-only access permission for peripheral 142" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 13. "PRIV141,privileged-only access permission for peripheral 141" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 12. "PRIV140,privileged-only access permission for peripheral 140" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 11. "PRIV139,privileged-only access permission for peripheral 139" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 10. "PRIV138,privileged-only access permission for peripheral 138" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 9. "PRIV137,privileged-only access permission for peripheral 137" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 8. "PRIV136,privileged-only access permission for peripheral 136" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 7. "PRIV135,privileged-only access permission for peripheral 135" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 6. "PRIV134,privileged-only access permission for peripheral 134" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 5. "PRIV133,privileged-only access permission for peripheral 133" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 4. "PRIV132,privileged-only access permission for peripheral 132" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 3. "PRIV131,privileged-only access permission for peripheral 131" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 2. "PRIV130,privileged-only access permission for peripheral 130" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 1. "PRIV129,privileged-only access permission for peripheral 129" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 0. "PRIV128,privileged-only access permission for peripheral 128" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." line.long 0x14 "RIFSC_RISC_PRIVCFGR5,RIFSC RISFC slave privileged register 5" bitfld.long 0x14 31. "PRIV191,privileged-only access permission for peripheral 191" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 30. "PRIV190,privileged-only access permission for peripheral 190" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 29. "PRIV189,privileged-only access permission for peripheral 189" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 28. "PRIV188,privileged-only access permission for peripheral 188" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 27. "PRIV187,privileged-only access permission for peripheral 187" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 26. "PRIV186,privileged-only access permission for peripheral 186" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 25. "PRIV185,privileged-only access permission for peripheral 185" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 24. "PRIV184,privileged-only access permission for peripheral 184" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 23. "PRIV183,privileged-only access permission for peripheral 183" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 22. "PRIV182,privileged-only access permission for peripheral 182" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 21. "PRIV181,privileged-only access permission for peripheral 181" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 20. "PRIV180,privileged-only access permission for peripheral 180" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 19. "PRIV179,privileged-only access permission for peripheral 179" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 18. "PRIV178,privileged-only access permission for peripheral 178" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 17. "PRIV177,privileged-only access permission for peripheral 177" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 16. "PRIV176,privileged-only access permission for peripheral 176" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 15. "PRIV175,privileged-only access permission for peripheral 175" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 14. "PRIV174,privileged-only access permission for peripheral 174" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 13. "PRIV173,privileged-only access permission for peripheral 173" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 12. "PRIV172,privileged-only access permission for peripheral 172" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 11. "PRIV171,privileged-only access permission for peripheral 171" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 10. "PRIV170,privileged-only access permission for peripheral 170" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 9. "PRIV169,privileged-only access permission for peripheral 169" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 8. "PRIV168,privileged-only access permission for peripheral 168" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 7. "PRIV167,privileged-only access permission for peripheral 167" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 6. "PRIV166,privileged-only access permission for peripheral 166" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 5. "PRIV165,privileged-only access permission for peripheral 165" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 4. "PRIV164,privileged-only access permission for peripheral 164" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 3. "PRIV163,privileged-only access permission for peripheral 163" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 2. "PRIV162,privileged-only access permission for peripheral 162" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 1. "PRIV161,privileged-only access permission for peripheral 161" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 0. "PRIV160,privileged-only access permission for peripheral 160" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." group.long 0x50++0x17 line.long 0x0 "RIFSC_RISC_RCFGLOCKR0,RIFSC RISC slave resource configuration lock register 0" bitfld.long 0x0 31. "RLOCK31,resource lock for peripheral 31" "0: SEC31 in RIFSC_RISC_SECCFGRx and PRIV31 in..,1: Writes to SEC31 and PRIV31 are ignored." bitfld.long 0x0 30. "RLOCK30,resource lock for peripheral 30" "0: SEC30 in RIFSC_RISC_SECCFGRx and PRIV30 in..,1: Writes to SEC30 and PRIV30 are ignored." newline bitfld.long 0x0 29. "RLOCK29,resource lock for peripheral 29" "0: SEC29 in RIFSC_RISC_SECCFGRx and PRIV29 in..,1: Writes to SEC29 and PRIV29 are ignored." bitfld.long 0x0 28. "RLOCK28,resource lock for peripheral 28" "0: SEC28 in RIFSC_RISC_SECCFGRx and PRIV28 in..,1: Writes to SEC28 and PRIV28 are ignored." newline bitfld.long 0x0 27. "RLOCK27,resource lock for peripheral 27" "0: SEC27 in RIFSC_RISC_SECCFGRx and PRIV27 in..,1: Writes to SEC27 and PRIV27 are ignored." bitfld.long 0x0 26. "RLOCK26,resource lock for peripheral 26" "0: SEC26 in RIFSC_RISC_SECCFGRx and PRIV26 in..,1: Writes to SEC26 and PRIV26 are ignored." newline bitfld.long 0x0 25. "RLOCK25,resource lock for peripheral 25" "0: SEC25 in RIFSC_RISC_SECCFGRx and PRIV25 in..,1: Writes to SEC25 and PRIV25 are ignored." bitfld.long 0x0 24. "RLOCK24,resource lock for peripheral 24" "0: SEC24 in RIFSC_RISC_SECCFGRx and PRIV24 in..,1: Writes to SEC24 and PRIV24 are ignored." newline bitfld.long 0x0 23. "RLOCK23,resource lock for peripheral 23" "0: SEC23 in RIFSC_RISC_SECCFGRx and PRIV23 in..,1: Writes to SEC23 and PRIV23 are ignored." bitfld.long 0x0 22. "RLOCK22,resource lock for peripheral 22" "0: SEC22 in RIFSC_RISC_SECCFGRx and PRIV22 in..,1: Writes to SEC22 and PRIV22 are ignored." newline bitfld.long 0x0 21. "RLOCK21,resource lock for peripheral 21" "0: SEC21 in RIFSC_RISC_SECCFGRx and PRIV21 in..,1: Writes to SEC21 and PRIV21 are ignored." bitfld.long 0x0 20. "RLOCK20,resource lock for peripheral 20" "0: SEC20 in RIFSC_RISC_SECCFGRx and PRIV20 in..,1: Writes to SEC20 and PRIV20 are ignored." newline bitfld.long 0x0 19. "RLOCK19,resource lock for peripheral 19" "0: SEC19 in RIFSC_RISC_SECCFGRx and PRIV19 in..,1: Writes to SEC19 and PRIV19 are ignored." bitfld.long 0x0 18. "RLOCK18,resource lock for peripheral 18" "0: SEC18 in RIFSC_RISC_SECCFGRx and PRIV18 in..,1: Writes to SEC18 and PRIV18 are ignored." newline bitfld.long 0x0 17. "RLOCK17,resource lock for peripheral 17" "0: SEC17 in RIFSC_RISC_SECCFGRx and PRIV17 in..,1: Writes to SEC17 and PRIV17 are ignored." bitfld.long 0x0 16. "RLOCK16,resource lock for peripheral 16" "0: SEC16 in RIFSC_RISC_SECCFGRx and PRIV16 in..,1: Writes to SEC16 and PRIV16 are ignored." newline bitfld.long 0x0 15. "RLOCK15,resource lock for peripheral 15" "0: SEC15 in RIFSC_RISC_SECCFGRx and PRIV15 in..,1: Writes to SEC15 and PRIV15 are ignored." bitfld.long 0x0 14. "RLOCK14,resource lock for peripheral 14" "0: SEC14 in RIFSC_RISC_SECCFGRx and PRIV14 in..,1: Writes to SEC14 and PRIV14 are ignored." newline bitfld.long 0x0 13. "RLOCK13,resource lock for peripheral 13" "0: SEC13 in RIFSC_RISC_SECCFGRx and PRIV13 in..,1: Writes to SEC13 and PRIV13 are ignored." bitfld.long 0x0 12. "RLOCK12,resource lock for peripheral 12" "0: SEC12 in RIFSC_RISC_SECCFGRx and PRIV12 in..,1: Writes to SEC12 and PRIV12 are ignored." newline bitfld.long 0x0 11. "RLOCK11,resource lock for peripheral 11" "0: SEC11 in RIFSC_RISC_SECCFGRx and PRIV11 in..,1: Writes to SEC11 and PRIV11 are ignored." bitfld.long 0x0 10. "RLOCK10,resource lock for peripheral 10" "0: SEC10 in RIFSC_RISC_SECCFGRx and PRIV10 in..,1: Writes to SEC10 and PRIV10 are ignored." newline bitfld.long 0x0 9. "RLOCK9,resource lock for peripheral 9" "0: SEC9 in RIFSC_RISC_SECCFGRx and PRIV9 in..,1: Writes to SEC9 and PRIV9 are ignored." bitfld.long 0x0 8. "RLOCK8,resource lock for peripheral 8" "0: SEC8 in RIFSC_RISC_SECCFGRx and PRIV8 in..,1: Writes to SEC8 and PRIV8 are ignored." newline bitfld.long 0x0 7. "RLOCK7,resource lock for peripheral 7" "0: SEC7 in RIFSC_RISC_SECCFGRx and PRIV7 in..,1: Writes to SEC7 and PRIV7 are ignored." bitfld.long 0x0 6. "RLOCK6,resource lock for peripheral 6" "0: SEC6 in RIFSC_RISC_SECCFGRx and PRIV6 in..,1: Writes to SEC6 and PRIV6 are ignored." newline bitfld.long 0x0 5. "RLOCK5,resource lock for peripheral 5" "0: SEC5 in RIFSC_RISC_SECCFGRx and PRIV5 in..,1: Writes to SEC5 and PRIV5 are ignored." bitfld.long 0x0 4. "RLOCK4,resource lock for peripheral 4" "0: SEC4 in RIFSC_RISC_SECCFGRx and PRIV4 in..,1: Writes to SEC4 and PRIV4 are ignored." newline bitfld.long 0x0 3. "RLOCK3,resource lock for peripheral 3" "0: SEC3 in RIFSC_RISC_SECCFGRx and PRIV3 in..,1: Writes to SEC3 and PRIV3 are ignored." bitfld.long 0x0 2. "RLOCK2,resource lock for peripheral 2" "0: SEC2 in RIFSC_RISC_SECCFGRx and PRIV2 in..,1: Writes to SEC2 and PRIV2 are ignored." newline bitfld.long 0x0 1. "RLOCK1,resource lock for peripheral 1" "0: SEC1 in RIFSC_RISC_SECCFGRx and PRIV1 in..,1: Writes to SEC1 and PRIV1 are ignored." bitfld.long 0x0 0. "RLOCK0,resource lock for peripheral 0" "0: SEC0 in RIFSC_RISC_SECCFGRx and PRIV0 in..,1: Writes to SEC0 and PRIV0 are ignored." line.long 0x4 "RIFSC_RISC_RCFGLOCKR1,RIFSC RISC slave resource configuration lock register 1" bitfld.long 0x4 31. "RLOCK63,resource lock for peripheral 63" "0: SEC63 in RIFSC_RISC_SECCFGRx and PRIV63 in..,1: Writes to SEC63 and PRIV63 are ignored." bitfld.long 0x4 30. "RLOCK62,resource lock for peripheral 62" "0: SEC62 in RIFSC_RISC_SECCFGRx and PRIV62 in..,1: Writes to SEC62 and PRIV62 are ignored." newline bitfld.long 0x4 29. "RLOCK61,resource lock for peripheral 61" "0: SEC61 in RIFSC_RISC_SECCFGRx and PRIV61 in..,1: Writes to SEC61 and PRIV61 are ignored." bitfld.long 0x4 28. "RLOCK60,resource lock for peripheral 60" "0: SEC60 in RIFSC_RISC_SECCFGRx and PRIV60 in..,1: Writes to SEC60 and PRIV60 are ignored." newline bitfld.long 0x4 27. "RLOCK59,resource lock for peripheral 59" "0: SEC59 in RIFSC_RISC_SECCFGRx and PRIV59 in..,1: Writes to SEC59 and PRIV59 are ignored." bitfld.long 0x4 26. "RLOCK58,resource lock for peripheral 58" "0: SEC58 in RIFSC_RISC_SECCFGRx and PRIV58 in..,1: Writes to SEC58 and PRIV58 are ignored." newline bitfld.long 0x4 25. "RLOCK57,resource lock for peripheral 57" "0: SEC57 in RIFSC_RISC_SECCFGRx and PRIV57 in..,1: Writes to SEC57 and PRIV57 are ignored." bitfld.long 0x4 24. "RLOCK56,resource lock for peripheral 56" "0: SEC56 in RIFSC_RISC_SECCFGRx and PRIV56 in..,1: Writes to SEC56 and PRIV56 are ignored." newline bitfld.long 0x4 23. "RLOCK55,resource lock for peripheral 55" "0: SEC55 in RIFSC_RISC_SECCFGRx and PRIV55 in..,1: Writes to SEC55 and PRIV55 are ignored." bitfld.long 0x4 22. "RLOCK54,resource lock for peripheral 54" "0: SEC54 in RIFSC_RISC_SECCFGRx and PRIV54 in..,1: Writes to SEC54 and PRIV54 are ignored." newline bitfld.long 0x4 21. "RLOCK53,resource lock for peripheral 53" "0: SEC53 in RIFSC_RISC_SECCFGRx and PRIV53 in..,1: Writes to SEC53 and PRIV53 are ignored." bitfld.long 0x4 20. "RLOCK52,resource lock for peripheral 52" "0: SEC52 in RIFSC_RISC_SECCFGRx and PRIV52 in..,1: Writes to SEC52 and PRIV52 are ignored." newline bitfld.long 0x4 19. "RLOCK51,resource lock for peripheral 51" "0: SEC51 in RIFSC_RISC_SECCFGRx and PRIV51 in..,1: Writes to SEC51 and PRIV51 are ignored." bitfld.long 0x4 18. "RLOCK50,resource lock for peripheral 50" "0: SEC50 in RIFSC_RISC_SECCFGRx and PRIV50 in..,1: Writes to SEC50 and PRIV50 are ignored." newline bitfld.long 0x4 17. "RLOCK49,resource lock for peripheral 49" "0: SEC49 in RIFSC_RISC_SECCFGRx and PRIV49 in..,1: Writes to SEC49 and PRIV49 are ignored." bitfld.long 0x4 16. "RLOCK48,resource lock for peripheral 48" "0: SEC48 in RIFSC_RISC_SECCFGRx and PRIV48 in..,1: Writes to SEC48 and PRIV48 are ignored." newline bitfld.long 0x4 15. "RLOCK47,resource lock for peripheral 47" "0: SEC47 in RIFSC_RISC_SECCFGRx and PRIV47 in..,1: Writes to SEC47 and PRIV47 are ignored." bitfld.long 0x4 14. "RLOCK46,resource lock for peripheral 46" "0: SEC46 in RIFSC_RISC_SECCFGRx and PRIV46 in..,1: Writes to SEC46 and PRIV46 are ignored." newline bitfld.long 0x4 13. "RLOCK45,resource lock for peripheral 45" "0: SEC45 in RIFSC_RISC_SECCFGRx and PRIV45 in..,1: Writes to SEC45 and PRIV45 are ignored." bitfld.long 0x4 12. "RLOCK44,resource lock for peripheral 44" "0: SEC44 in RIFSC_RISC_SECCFGRx and PRIV44 in..,1: Writes to SEC44 and PRIV44 are ignored." newline bitfld.long 0x4 11. "RLOCK43,resource lock for peripheral 43" "0: SEC43 in RIFSC_RISC_SECCFGRx and PRIV43 in..,1: Writes to SEC43 and PRIV43 are ignored." bitfld.long 0x4 10. "RLOCK42,resource lock for peripheral 42" "0: SEC42 in RIFSC_RISC_SECCFGRx and PRIV42 in..,1: Writes to SEC42 and PRIV42 are ignored." newline bitfld.long 0x4 9. "RLOCK41,resource lock for peripheral 41" "0: SEC41 in RIFSC_RISC_SECCFGRx and PRIV41 in..,1: Writes to SEC41 and PRIV41 are ignored." bitfld.long 0x4 8. "RLOCK40,resource lock for peripheral 40" "0: SEC40 in RIFSC_RISC_SECCFGRx and PRIV40 in..,1: Writes to SEC40 and PRIV40 are ignored." newline bitfld.long 0x4 7. "RLOCK39,resource lock for peripheral 39" "0: SEC39 in RIFSC_RISC_SECCFGRx and PRIV39 in..,1: Writes to SEC39 and PRIV39 are ignored." bitfld.long 0x4 6. "RLOCK38,resource lock for peripheral 38" "0: SEC38 in RIFSC_RISC_SECCFGRx and PRIV38 in..,1: Writes to SEC38 and PRIV38 are ignored." newline bitfld.long 0x4 5. "RLOCK37,resource lock for peripheral 37" "0: SEC37 in RIFSC_RISC_SECCFGRx and PRIV37 in..,1: Writes to SEC37 and PRIV37 are ignored." bitfld.long 0x4 4. "RLOCK36,resource lock for peripheral 36" "0: SEC36 in RIFSC_RISC_SECCFGRx and PRIV36 in..,1: Writes to SEC36 and PRIV36 are ignored." newline bitfld.long 0x4 3. "RLOCK35,resource lock for peripheral 35" "0: SEC35 in RIFSC_RISC_SECCFGRx and PRIV35 in..,1: Writes to SEC35 and PRIV35 are ignored." bitfld.long 0x4 2. "RLOCK34,resource lock for peripheral 34" "0: SEC34 in RIFSC_RISC_SECCFGRx and PRIV34 in..,1: Writes to SEC34 and PRIV34 are ignored." newline bitfld.long 0x4 1. "RLOCK33,resource lock for peripheral 33" "0: SEC33 in RIFSC_RISC_SECCFGRx and PRIV33 in..,1: Writes to SEC33 and PRIV33 are ignored." bitfld.long 0x4 0. "RLOCK32,resource lock for peripheral 32" "0: SEC32 in RIFSC_RISC_SECCFGRx and PRIV32 in..,1: Writes to SEC32 and PRIV32 are ignored." line.long 0x8 "RIFSC_RISC_RCFGLOCKR2,RIFSC RISC slave resource configuration lock register 2" bitfld.long 0x8 31. "RLOCK95,resource lock for peripheral 95" "0: SEC95 in RIFSC_RISC_SECCFGRx and PRIV95 in..,1: Writes to SEC95 and PRIV95 are ignored." bitfld.long 0x8 30. "RLOCK94,resource lock for peripheral 94" "0: SEC94 in RIFSC_RISC_SECCFGRx and PRIV94 in..,1: Writes to SEC94 and PRIV94 are ignored." newline bitfld.long 0x8 29. "RLOCK93,resource lock for peripheral 93" "0: SEC93 in RIFSC_RISC_SECCFGRx and PRIV93 in..,1: Writes to SEC93 and PRIV93 are ignored." bitfld.long 0x8 28. "RLOCK92,resource lock for peripheral 92" "0: SEC92 in RIFSC_RISC_SECCFGRx and PRIV92 in..,1: Writes to SEC92 and PRIV92 are ignored." newline bitfld.long 0x8 27. "RLOCK91,resource lock for peripheral 91" "0: SEC91 in RIFSC_RISC_SECCFGRx and PRIV91 in..,1: Writes to SEC91 and PRIV91 are ignored." bitfld.long 0x8 26. "RLOCK90,resource lock for peripheral 90" "0: SEC90 in RIFSC_RISC_SECCFGRx and PRIV90 in..,1: Writes to SEC90 and PRIV90 are ignored." newline bitfld.long 0x8 25. "RLOCK89,resource lock for peripheral 89" "0: SEC89 in RIFSC_RISC_SECCFGRx and PRIV89 in..,1: Writes to SEC89 and PRIV89 are ignored." bitfld.long 0x8 24. "RLOCK88,resource lock for peripheral 88" "0: SEC88 in RIFSC_RISC_SECCFGRx and PRIV88 in..,1: Writes to SEC88 and PRIV88 are ignored." newline bitfld.long 0x8 23. "RLOCK87,resource lock for peripheral 87" "0: SEC87 in RIFSC_RISC_SECCFGRx and PRIV87 in..,1: Writes to SEC87 and PRIV87 are ignored." bitfld.long 0x8 22. "RLOCK86,resource lock for peripheral 86" "0: SEC86 in RIFSC_RISC_SECCFGRx and PRIV86 in..,1: Writes to SEC86 and PRIV86 are ignored." newline bitfld.long 0x8 21. "RLOCK85,resource lock for peripheral 85" "0: SEC85 in RIFSC_RISC_SECCFGRx and PRIV85 in..,1: Writes to SEC85 and PRIV85 are ignored." bitfld.long 0x8 20. "RLOCK84,resource lock for peripheral 84" "0: SEC84 in RIFSC_RISC_SECCFGRx and PRIV84 in..,1: Writes to SEC84 and PRIV84 are ignored." newline bitfld.long 0x8 19. "RLOCK83,resource lock for peripheral 83" "0: SEC83 in RIFSC_RISC_SECCFGRx and PRIV83 in..,1: Writes to SEC83 and PRIV83 are ignored." bitfld.long 0x8 18. "RLOCK82,resource lock for peripheral 82" "0: SEC82 in RIFSC_RISC_SECCFGRx and PRIV82 in..,1: Writes to SEC82 and PRIV82 are ignored." newline bitfld.long 0x8 17. "RLOCK81,resource lock for peripheral 81" "0: SEC81 in RIFSC_RISC_SECCFGRx and PRIV81 in..,1: Writes to SEC81 and PRIV81 are ignored." bitfld.long 0x8 16. "RLOCK80,resource lock for peripheral 80" "0: SEC80 in RIFSC_RISC_SECCFGRx and PRIV80 in..,1: Writes to SEC80 and PRIV80 are ignored." newline bitfld.long 0x8 15. "RLOCK79,resource lock for peripheral 79" "0: SEC79 in RIFSC_RISC_SECCFGRx and PRIV79 in..,1: Writes to SEC79 and PRIV79 are ignored." bitfld.long 0x8 14. "RLOCK78,resource lock for peripheral 78" "0: SEC78 in RIFSC_RISC_SECCFGRx and PRIV78 in..,1: Writes to SEC78 and PRIV78 are ignored." newline bitfld.long 0x8 13. "RLOCK77,resource lock for peripheral 77" "0: SEC77 in RIFSC_RISC_SECCFGRx and PRIV77 in..,1: Writes to SEC77 and PRIV77 are ignored." bitfld.long 0x8 12. "RLOCK76,resource lock for peripheral 76" "0: SEC76 in RIFSC_RISC_SECCFGRx and PRIV76 in..,1: Writes to SEC76 and PRIV76 are ignored." newline bitfld.long 0x8 11. "RLOCK75,resource lock for peripheral 75" "0: SEC75 in RIFSC_RISC_SECCFGRx and PRIV75 in..,1: Writes to SEC75 and PRIV75 are ignored." bitfld.long 0x8 10. "RLOCK74,resource lock for peripheral 74" "0: SEC74 in RIFSC_RISC_SECCFGRx and PRIV74 in..,1: Writes to SEC74 and PRIV74 are ignored." newline bitfld.long 0x8 9. "RLOCK73,resource lock for peripheral 73" "0: SEC73 in RIFSC_RISC_SECCFGRx and PRIV73 in..,1: Writes to SEC73 and PRIV73 are ignored." bitfld.long 0x8 8. "RLOCK72,resource lock for peripheral 72" "0: SEC72 in RIFSC_RISC_SECCFGRx and PRIV72 in..,1: Writes to SEC72 and PRIV72 are ignored." newline bitfld.long 0x8 7. "RLOCK71,resource lock for peripheral 71" "0: SEC71 in RIFSC_RISC_SECCFGRx and PRIV71 in..,1: Writes to SEC71 and PRIV71 are ignored." bitfld.long 0x8 6. "RLOCK70,resource lock for peripheral 70" "0: SEC70 in RIFSC_RISC_SECCFGRx and PRIV70 in..,1: Writes to SEC70 and PRIV70 are ignored." newline bitfld.long 0x8 5. "RLOCK69,resource lock for peripheral 69" "0: SEC69 in RIFSC_RISC_SECCFGRx and PRIV69 in..,1: Writes to SEC69 and PRIV69 are ignored." bitfld.long 0x8 4. "RLOCK68,resource lock for peripheral 68" "0: SEC68 in RIFSC_RISC_SECCFGRx and PRIV68 in..,1: Writes to SEC68 and PRIV68 are ignored." newline bitfld.long 0x8 3. "RLOCK67,resource lock for peripheral 67" "0: SEC67 in RIFSC_RISC_SECCFGRx and PRIV67 in..,1: Writes to SEC67 and PRIV67 are ignored." bitfld.long 0x8 2. "RLOCK66,resource lock for peripheral 66" "0: SEC66 in RIFSC_RISC_SECCFGRx and PRIV66 in..,1: Writes to SEC66 and PRIV66 are ignored." newline bitfld.long 0x8 1. "RLOCK65,resource lock for peripheral 65" "0: SEC65 in RIFSC_RISC_SECCFGRx and PRIV65 in..,1: Writes to SEC65 and PRIV65 are ignored." bitfld.long 0x8 0. "RLOCK64,resource lock for peripheral 64" "0: SEC64 in RIFSC_RISC_SECCFGRx and PRIV64 in..,1: Writes to SEC64 and PRIV64 are ignored." line.long 0xC "RIFSC_RISC_RCFGLOCKR3,RIFSC RISC slave resource configuration lock register 3" bitfld.long 0xC 31. "RLOCK127,resource lock for peripheral 127" "0: SEC127 in RIFSC_RISC_SECCFGRx and PRIV127 in..,1: Writes to SEC127 and PRIV127 are ignored." bitfld.long 0xC 30. "RLOCK126,resource lock for peripheral 126" "0: SEC126 in RIFSC_RISC_SECCFGRx and PRIV126 in..,1: Writes to SEC126 and PRIV126 are ignored." newline bitfld.long 0xC 29. "RLOCK125,resource lock for peripheral 125" "0: SEC125 in RIFSC_RISC_SECCFGRx and PRIV125 in..,1: Writes to SEC125 and PRIV125 are ignored." bitfld.long 0xC 28. "RLOCK124,resource lock for peripheral 124" "0: SEC124 in RIFSC_RISC_SECCFGRx and PRIV124 in..,1: Writes to SEC124 and PRIV124 are ignored." newline bitfld.long 0xC 27. "RLOCK123,resource lock for peripheral 123" "0: SEC123 in RIFSC_RISC_SECCFGRx and PRIV123 in..,1: Writes to SEC123 and PRIV123 are ignored." bitfld.long 0xC 26. "RLOCK122,resource lock for peripheral 122" "0: SEC122 in RIFSC_RISC_SECCFGRx and PRIV122 in..,1: Writes to SEC122 and PRIV122 are ignored." newline bitfld.long 0xC 25. "RLOCK121,resource lock for peripheral 121" "0: SEC121 in RIFSC_RISC_SECCFGRx and PRIV121 in..,1: Writes to SEC121 and PRIV121 are ignored." bitfld.long 0xC 24. "RLOCK120,resource lock for peripheral 120" "0: SEC120 in RIFSC_RISC_SECCFGRx and PRIV120 in..,1: Writes to SEC120 and PRIV120 are ignored." newline bitfld.long 0xC 23. "RLOCK119,resource lock for peripheral 119" "0: SEC119 in RIFSC_RISC_SECCFGRx and PRIV119 in..,1: Writes to SEC119 and PRIV119 are ignored." bitfld.long 0xC 22. "RLOCK118,resource lock for peripheral 118" "0: SEC118 in RIFSC_RISC_SECCFGRx and PRIV118 in..,1: Writes to SEC118 and PRIV118 are ignored." newline bitfld.long 0xC 21. "RLOCK117,resource lock for peripheral 117" "0: SEC117 in RIFSC_RISC_SECCFGRx and PRIV117 in..,1: Writes to SEC117 and PRIV117 are ignored." bitfld.long 0xC 20. "RLOCK116,resource lock for peripheral 116" "0: SEC116 in RIFSC_RISC_SECCFGRx and PRIV116 in..,1: Writes to SEC116 and PRIV116 are ignored." newline bitfld.long 0xC 19. "RLOCK115,resource lock for peripheral 115" "0: SEC115 in RIFSC_RISC_SECCFGRx and PRIV115 in..,1: Writes to SEC115 and PRIV115 are ignored." bitfld.long 0xC 18. "RLOCK114,resource lock for peripheral 114" "0: SEC114 in RIFSC_RISC_SECCFGRx and PRIV114 in..,1: Writes to SEC114 and PRIV114 are ignored." newline bitfld.long 0xC 17. "RLOCK113,resource lock for peripheral 113" "0: SEC113 in RIFSC_RISC_SECCFGRx and PRIV113 in..,1: Writes to SEC113 and PRIV113 are ignored." bitfld.long 0xC 16. "RLOCK112,resource lock for peripheral 112" "0: SEC112 in RIFSC_RISC_SECCFGRx and PRIV112 in..,1: Writes to SEC112 and PRIV112 are ignored." newline bitfld.long 0xC 15. "RLOCK111,resource lock for peripheral 111" "0: SEC111 in RIFSC_RISC_SECCFGRx and PRIV111 in..,1: Writes to SEC111 and PRIV111 are ignored." bitfld.long 0xC 14. "RLOCK110,resource lock for peripheral 110" "0: SEC110 in RIFSC_RISC_SECCFGRx and PRIV110 in..,1: Writes to SEC110 and PRIV110 are ignored." newline bitfld.long 0xC 13. "RLOCK109,resource lock for peripheral 109" "0: SEC109 in RIFSC_RISC_SECCFGRx and PRIV109 in..,1: Writes to SEC109 and PRIV109 are ignored." bitfld.long 0xC 12. "RLOCK108,resource lock for peripheral 108" "0: SEC108 in RIFSC_RISC_SECCFGRx and PRIV108 in..,1: Writes to SEC108 and PRIV108 are ignored." newline bitfld.long 0xC 11. "RLOCK107,resource lock for peripheral 107" "0: SEC107 in RIFSC_RISC_SECCFGRx and PRIV107 in..,1: Writes to SEC107 and PRIV107 are ignored." bitfld.long 0xC 10. "RLOCK106,resource lock for peripheral 106" "0: SEC106 in RIFSC_RISC_SECCFGRx and PRIV106 in..,1: Writes to SEC106 and PRIV106 are ignored." newline bitfld.long 0xC 9. "RLOCK105,resource lock for peripheral 105" "0: SEC105 in RIFSC_RISC_SECCFGRx and PRIV105 in..,1: Writes to SEC105 and PRIV105 are ignored." bitfld.long 0xC 8. "RLOCK104,resource lock for peripheral 104" "0: SEC104 in RIFSC_RISC_SECCFGRx and PRIV104 in..,1: Writes to SEC104 and PRIV104 are ignored." newline bitfld.long 0xC 7. "RLOCK103,resource lock for peripheral 103" "0: SEC103 in RIFSC_RISC_SECCFGRx and PRIV103 in..,1: Writes to SEC103 and PRIV103 are ignored." bitfld.long 0xC 6. "RLOCK102,resource lock for peripheral 102" "0: SEC102 in RIFSC_RISC_SECCFGRx and PRIV102 in..,1: Writes to SEC102 and PRIV102 are ignored." newline bitfld.long 0xC 5. "RLOCK101,resource lock for peripheral 101" "0: SEC101 in RIFSC_RISC_SECCFGRx and PRIV101 in..,1: Writes to SEC101 and PRIV101 are ignored." bitfld.long 0xC 4. "RLOCK100,resource lock for peripheral 100" "0: SEC100 in RIFSC_RISC_SECCFGRx and PRIV100 in..,1: Writes to SEC100 and PRIV100 are ignored." newline bitfld.long 0xC 3. "RLOCK99,resource lock for peripheral 99" "0: SEC99 in RIFSC_RISC_SECCFGRx and PRIV99 in..,1: Writes to SEC99 and PRIV99 are ignored." bitfld.long 0xC 2. "RLOCK98,resource lock for peripheral 98" "0: SEC98 in RIFSC_RISC_SECCFGRx and PRIV98 in..,1: Writes to SEC98 and PRIV98 are ignored." newline bitfld.long 0xC 1. "RLOCK97,resource lock for peripheral 97" "0: SEC97 in RIFSC_RISC_SECCFGRx and PRIV97 in..,1: Writes to SEC97 and PRIV97 are ignored." bitfld.long 0xC 0. "RLOCK96,resource lock for peripheral 96" "0: SEC96 in RIFSC_RISC_SECCFGRx and PRIV96 in..,1: Writes to SEC96 and PRIV96 are ignored." line.long 0x10 "RIFSC_RISC_RCFGLOCKR4,RIFSC RISC slave resource configuration lock register 4" bitfld.long 0x10 31. "RLOCK159,resource lock for peripheral 159" "0: SEC159 in RIFSC_RISC_SECCFGRx and PRIV159 in..,1: Writes to SEC159 and PRIV159 are ignored." bitfld.long 0x10 30. "RLOCK158,resource lock for peripheral 158" "0: SEC158 in RIFSC_RISC_SECCFGRx and PRIV158 in..,1: Writes to SEC158 and PRIV158 are ignored." newline bitfld.long 0x10 29. "RLOCK157,resource lock for peripheral 157" "0: SEC157 in RIFSC_RISC_SECCFGRx and PRIV157 in..,1: Writes to SEC157 and PRIV157 are ignored." bitfld.long 0x10 28. "RLOCK156,resource lock for peripheral 156" "0: SEC156 in RIFSC_RISC_SECCFGRx and PRIV156 in..,1: Writes to SEC156 and PRIV156 are ignored." newline bitfld.long 0x10 27. "RLOCK155,resource lock for peripheral 155" "0: SEC155 in RIFSC_RISC_SECCFGRx and PRIV155 in..,1: Writes to SEC155 and PRIV155 are ignored." bitfld.long 0x10 26. "RLOCK154,resource lock for peripheral 154" "0: SEC154 in RIFSC_RISC_SECCFGRx and PRIV154 in..,1: Writes to SEC154 and PRIV154 are ignored." newline bitfld.long 0x10 25. "RLOCK153,resource lock for peripheral 153" "0: SEC153 in RIFSC_RISC_SECCFGRx and PRIV153 in..,1: Writes to SEC153 and PRIV153 are ignored." bitfld.long 0x10 24. "RLOCK152,resource lock for peripheral 152" "0: SEC152 in RIFSC_RISC_SECCFGRx and PRIV152 in..,1: Writes to SEC152 and PRIV152 are ignored." newline bitfld.long 0x10 23. "RLOCK151,resource lock for peripheral 151" "0: SEC151 in RIFSC_RISC_SECCFGRx and PRIV151 in..,1: Writes to SEC151 and PRIV151 are ignored." bitfld.long 0x10 22. "RLOCK150,resource lock for peripheral 150" "0: SEC150 in RIFSC_RISC_SECCFGRx and PRIV150 in..,1: Writes to SEC150 and PRIV150 are ignored." newline bitfld.long 0x10 21. "RLOCK149,resource lock for peripheral 149" "0: SEC149 in RIFSC_RISC_SECCFGRx and PRIV149 in..,1: Writes to SEC149 and PRIV149 are ignored." bitfld.long 0x10 20. "RLOCK148,resource lock for peripheral 148" "0: SEC148 in RIFSC_RISC_SECCFGRx and PRIV148 in..,1: Writes to SEC148 and PRIV148 are ignored." newline bitfld.long 0x10 19. "RLOCK147,resource lock for peripheral 147" "0: SEC147 in RIFSC_RISC_SECCFGRx and PRIV147 in..,1: Writes to SEC147 and PRIV147 are ignored." bitfld.long 0x10 18. "RLOCK146,resource lock for peripheral 146" "0: SEC146 in RIFSC_RISC_SECCFGRx and PRIV146 in..,1: Writes to SEC146 and PRIV146 are ignored." newline bitfld.long 0x10 17. "RLOCK145,resource lock for peripheral 145" "0: SEC145 in RIFSC_RISC_SECCFGRx and PRIV145 in..,1: Writes to SEC145 and PRIV145 are ignored." bitfld.long 0x10 16. "RLOCK144,resource lock for peripheral 144" "0: SEC144 in RIFSC_RISC_SECCFGRx and PRIV144 in..,1: Writes to SEC144 and PRIV144 are ignored." newline bitfld.long 0x10 15. "RLOCK143,resource lock for peripheral 143" "0: SEC143 in RIFSC_RISC_SECCFGRx and PRIV143 in..,1: Writes to SEC143 and PRIV143 are ignored." bitfld.long 0x10 14. "RLOCK142,resource lock for peripheral 142" "0: SEC142 in RIFSC_RISC_SECCFGRx and PRIV142 in..,1: Writes to SEC142 and PRIV142 are ignored." newline bitfld.long 0x10 13. "RLOCK141,resource lock for peripheral 141" "0: SEC141 in RIFSC_RISC_SECCFGRx and PRIV141 in..,1: Writes to SEC141 and PRIV141 are ignored." bitfld.long 0x10 12. "RLOCK140,resource lock for peripheral 140" "0: SEC140 in RIFSC_RISC_SECCFGRx and PRIV140 in..,1: Writes to SEC140 and PRIV140 are ignored." newline bitfld.long 0x10 11. "RLOCK139,resource lock for peripheral 139" "0: SEC139 in RIFSC_RISC_SECCFGRx and PRIV139 in..,1: Writes to SEC139 and PRIV139 are ignored." bitfld.long 0x10 10. "RLOCK138,resource lock for peripheral 138" "0: SEC138 in RIFSC_RISC_SECCFGRx and PRIV138 in..,1: Writes to SEC138 and PRIV138 are ignored." newline bitfld.long 0x10 9. "RLOCK137,resource lock for peripheral 137" "0: SEC137 in RIFSC_RISC_SECCFGRx and PRIV137 in..,1: Writes to SEC137 and PRIV137 are ignored." bitfld.long 0x10 8. "RLOCK136,resource lock for peripheral 136" "0: SEC136 in RIFSC_RISC_SECCFGRx and PRIV136 in..,1: Writes to SEC136 and PRIV136 are ignored." newline bitfld.long 0x10 7. "RLOCK135,resource lock for peripheral 135" "0: SEC135 in RIFSC_RISC_SECCFGRx and PRIV135 in..,1: Writes to SEC135 and PRIV135 are ignored." bitfld.long 0x10 6. "RLOCK134,resource lock for peripheral 134" "0: SEC134 in RIFSC_RISC_SECCFGRx and PRIV134 in..,1: Writes to SEC134 and PRIV134 are ignored." newline bitfld.long 0x10 5. "RLOCK133,resource lock for peripheral 133" "0: SEC133 in RIFSC_RISC_SECCFGRx and PRIV133 in..,1: Writes to SEC133 and PRIV133 are ignored." bitfld.long 0x10 4. "RLOCK132,resource lock for peripheral 132" "0: SEC132 in RIFSC_RISC_SECCFGRx and PRIV132 in..,1: Writes to SEC132 and PRIV132 are ignored." newline bitfld.long 0x10 3. "RLOCK131,resource lock for peripheral 131" "0: SEC131 in RIFSC_RISC_SECCFGRx and PRIV131 in..,1: Writes to SEC131 and PRIV131 are ignored." bitfld.long 0x10 2. "RLOCK130,resource lock for peripheral 130" "0: SEC130 in RIFSC_RISC_SECCFGRx and PRIV130 in..,1: Writes to SEC130 and PRIV130 are ignored." newline bitfld.long 0x10 1. "RLOCK129,resource lock for peripheral 129" "0: SEC129 in RIFSC_RISC_SECCFGRx and PRIV129 in..,1: Writes to SEC129 and PRIV129 are ignored." bitfld.long 0x10 0. "RLOCK128,resource lock for peripheral 128" "0: SEC128 in RIFSC_RISC_SECCFGRx and PRIV128 in..,1: Writes to SEC128 and PRIV128 are ignored." line.long 0x14 "RIFSC_RISC_RCFGLOCKR5,RIFSC RISC slave resource configuration lock register 5" bitfld.long 0x14 31. "RLOCK191,resource lock for peripheral 191" "0: SEC191 in RIFSC_RISC_SECCFGRx and PRIV191 in..,1: Writes to SEC191 and PRIV191 are ignored." bitfld.long 0x14 30. "RLOCK190,resource lock for peripheral 190" "0: SEC190 in RIFSC_RISC_SECCFGRx and PRIV190 in..,1: Writes to SEC190 and PRIV190 are ignored." newline bitfld.long 0x14 29. "RLOCK189,resource lock for peripheral 189" "0: SEC189 in RIFSC_RISC_SECCFGRx and PRIV189 in..,1: Writes to SEC189 and PRIV189 are ignored." bitfld.long 0x14 28. "RLOCK188,resource lock for peripheral 188" "0: SEC188 in RIFSC_RISC_SECCFGRx and PRIV188 in..,1: Writes to SEC188 and PRIV188 are ignored." newline bitfld.long 0x14 27. "RLOCK187,resource lock for peripheral 187" "0: SEC187 in RIFSC_RISC_SECCFGRx and PRIV187 in..,1: Writes to SEC187 and PRIV187 are ignored." bitfld.long 0x14 26. "RLOCK186,resource lock for peripheral 186" "0: SEC186 in RIFSC_RISC_SECCFGRx and PRIV186 in..,1: Writes to SEC186 and PRIV186 are ignored." newline bitfld.long 0x14 25. "RLOCK185,resource lock for peripheral 185" "0: SEC185 in RIFSC_RISC_SECCFGRx and PRIV185 in..,1: Writes to SEC185 and PRIV185 are ignored." bitfld.long 0x14 24. "RLOCK184,resource lock for peripheral 184" "0: SEC184 in RIFSC_RISC_SECCFGRx and PRIV184 in..,1: Writes to SEC184 and PRIV184 are ignored." newline bitfld.long 0x14 23. "RLOCK183,resource lock for peripheral 183" "0: SEC183 in RIFSC_RISC_SECCFGRx and PRIV183 in..,1: Writes to SEC183 and PRIV183 are ignored." bitfld.long 0x14 22. "RLOCK182,resource lock for peripheral 182" "0: SEC182 in RIFSC_RISC_SECCFGRx and PRIV182 in..,1: Writes to SEC182 and PRIV182 are ignored." newline bitfld.long 0x14 21. "RLOCK181,resource lock for peripheral 181" "0: SEC181 in RIFSC_RISC_SECCFGRx and PRIV181 in..,1: Writes to SEC181 and PRIV181 are ignored." bitfld.long 0x14 20. "RLOCK180,resource lock for peripheral 180" "0: SEC180 in RIFSC_RISC_SECCFGRx and PRIV180 in..,1: Writes to SEC180 and PRIV180 are ignored." newline bitfld.long 0x14 19. "RLOCK179,resource lock for peripheral 179" "0: SEC179 in RIFSC_RISC_SECCFGRx and PRIV179 in..,1: Writes to SEC179 and PRIV179 are ignored." bitfld.long 0x14 18. "RLOCK178,resource lock for peripheral 178" "0: SEC178 in RIFSC_RISC_SECCFGRx and PRIV178 in..,1: Writes to SEC178 and PRIV178 are ignored." newline bitfld.long 0x14 17. "RLOCK177,resource lock for peripheral 177" "0: SEC177 in RIFSC_RISC_SECCFGRx and PRIV177 in..,1: Writes to SEC177 and PRIV177 are ignored." bitfld.long 0x14 16. "RLOCK176,resource lock for peripheral 176" "0: SEC176 in RIFSC_RISC_SECCFGRx and PRIV176 in..,1: Writes to SEC176 and PRIV176 are ignored." newline bitfld.long 0x14 15. "RLOCK175,resource lock for peripheral 175" "0: SEC175 in RIFSC_RISC_SECCFGRx and PRIV175 in..,1: Writes to SEC175 and PRIV175 are ignored." bitfld.long 0x14 14. "RLOCK174,resource lock for peripheral 174" "0: SEC174 in RIFSC_RISC_SECCFGRx and PRIV174 in..,1: Writes to SEC174 and PRIV174 are ignored." newline bitfld.long 0x14 13. "RLOCK173,resource lock for peripheral 173" "0: SEC173 in RIFSC_RISC_SECCFGRx and PRIV173 in..,1: Writes to SEC173 and PRIV173 are ignored." bitfld.long 0x14 12. "RLOCK172,resource lock for peripheral 172" "0: SEC172 in RIFSC_RISC_SECCFGRx and PRIV172 in..,1: Writes to SEC172 and PRIV172 are ignored." newline bitfld.long 0x14 11. "RLOCK171,resource lock for peripheral 171" "0: SEC171 in RIFSC_RISC_SECCFGRx and PRIV171 in..,1: Writes to SEC171 and PRIV171 are ignored." bitfld.long 0x14 10. "RLOCK170,resource lock for peripheral 170" "0: SEC170 in RIFSC_RISC_SECCFGRx and PRIV170 in..,1: Writes to SEC170 and PRIV170 are ignored." newline bitfld.long 0x14 9. "RLOCK169,resource lock for peripheral 169" "0: SEC169 in RIFSC_RISC_SECCFGRx and PRIV169 in..,1: Writes to SEC169 and PRIV169 are ignored." bitfld.long 0x14 8. "RLOCK168,resource lock for peripheral 168" "0: SEC168 in RIFSC_RISC_SECCFGRx and PRIV168 in..,1: Writes to SEC168 and PRIV168 are ignored." newline bitfld.long 0x14 7. "RLOCK167,resource lock for peripheral 167" "0: SEC167 in RIFSC_RISC_SECCFGRx and PRIV167 in..,1: Writes to SEC167 and PRIV167 are ignored." bitfld.long 0x14 6. "RLOCK166,resource lock for peripheral 166" "0: SEC166 in RIFSC_RISC_SECCFGRx and PRIV166 in..,1: Writes to SEC166 and PRIV166 are ignored." newline bitfld.long 0x14 5. "RLOCK165,resource lock for peripheral 165" "0: SEC165 in RIFSC_RISC_SECCFGRx and PRIV165 in..,1: Writes to SEC165 and PRIV165 are ignored." bitfld.long 0x14 4. "RLOCK164,resource lock for peripheral 164" "0: SEC164 in RIFSC_RISC_SECCFGRx and PRIV164 in..,1: Writes to SEC164 and PRIV164 are ignored." newline bitfld.long 0x14 3. "RLOCK163,resource lock for peripheral 163" "0: SEC163 in RIFSC_RISC_SECCFGRx and PRIV163 in..,1: Writes to SEC163 and PRIV163 are ignored." bitfld.long 0x14 2. "RLOCK162,resource lock for peripheral 162" "0: SEC162 in RIFSC_RISC_SECCFGRx and PRIV162 in..,1: Writes to SEC162 and PRIV162 are ignored." newline bitfld.long 0x14 1. "RLOCK161,resource lock for peripheral 161" "0: SEC161 in RIFSC_RISC_SECCFGRx and PRIV161 in..,1: Writes to SEC161 and PRIV161 are ignored." bitfld.long 0x14 0. "RLOCK160,resource lock for peripheral 160" "0: SEC160 in RIFSC_RISC_SECCFGRx and PRIV160 in..,1: Writes to SEC160 and PRIV160 are ignored." group.long 0xC00++0x3 line.long 0x0 "RIFSC_RIMC_CR,RIFSC RIMC master configuration register" bitfld.long 0x0 8.--10. "DAPCID,debug access port compartment ID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "GLOCK,global lock" "0: RIFSC RIMC registers are writable.,1: All writes to RIFSC RIMC registers are ignored." group.long 0xC10++0x2F line.long 0x0 "RIFSC_RIMC_ATTR0,RIFSC RIMC master attribute register 0" bitfld.long 0x0 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x0 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x0 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x4 "RIFSC_RIMC_ATTR1,RIFSC RIMC master attribute register 1" bitfld.long 0x4 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x4 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x4 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x8 "RIFSC_RIMC_ATTR2,RIFSC RIMC master attribute register 2" bitfld.long 0x8 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x8 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x8 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0xC "RIFSC_RIMC_ATTR3,RIFSC RIMC master attribute register 3" bitfld.long 0xC 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0xC 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0xC 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x10 "RIFSC_RIMC_ATTR4,RIFSC RIMC master attribute register 4" bitfld.long 0x10 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x10 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x10 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x14 "RIFSC_RIMC_ATTR5,RIFSC RIMC master attribute register 5" bitfld.long 0x14 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x14 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x14 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x18 "RIFSC_RIMC_ATTR6,RIFSC RIMC master attribute register 6" bitfld.long 0x18 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x18 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x18 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x1C "RIFSC_RIMC_ATTR7,RIFSC RIMC master attribute register 7" bitfld.long 0x1C 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x1C 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x1C 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x20 "RIFSC_RIMC_ATTR8,RIFSC RIMC master attribute register 8" bitfld.long 0x20 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x20 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x20 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x24 "RIFSC_RIMC_ATTR9,RIFSC RIMC master attribute register 9" bitfld.long 0x24 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x24 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x24 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x28 "RIFSC_RIMC_ATTR10,RIFSC RIMC master attribute register 10" bitfld.long 0x28 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x28 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x28 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x2C "RIFSC_RIMC_ATTR11,RIFSC RIMC master attribute register 11" bitfld.long 0x2C 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x2C 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x2C 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" rgroup.long 0xFB0++0x17 line.long 0x0 "RIFSC_PPSR0,RIFSC peripheral protection status register 0" bitfld.long 0x0 31. "PPEN31,peripheral protection enable 31" "0: SEC31 PRIV31 and RLOCK31 register bit not present.,1: SEC31 PRIV31 and RLOCK31 register bit present." bitfld.long 0x0 30. "PPEN30,peripheral protection enable 30" "0: SEC30 PRIV30 and RLOCK30 register bit not present.,1: SEC30 PRIV30 and RLOCK30 register bit present." newline bitfld.long 0x0 29. "PPEN29,peripheral protection enable 29" "0: SEC29 PRIV29 and RLOCK29 register bit not present.,1: SEC29 PRIV29 and RLOCK29 register bit present." bitfld.long 0x0 28. "PPEN28,peripheral protection enable 28" "0: SEC28 PRIV28 and RLOCK28 register bit not present.,1: SEC28 PRIV28 and RLOCK28 register bit present." newline bitfld.long 0x0 27. "PPEN27,peripheral protection enable 27" "0: SEC27 PRIV27 and RLOCK27 register bit not present.,1: SEC27 PRIV27 and RLOCK27 register bit present." bitfld.long 0x0 26. "PPEN26,peripheral protection enable 26" "0: SEC26 PRIV26 and RLOCK26 register bit not present.,1: SEC26 PRIV26 and RLOCK26 register bit present." newline bitfld.long 0x0 25. "PPEN25,peripheral protection enable 25" "0: SEC25 PRIV25 and RLOCK25 register bit not present.,1: SEC25 PRIV25 and RLOCK25 register bit present." bitfld.long 0x0 24. "PPEN24,peripheral protection enable 24" "0: SEC24 PRIV24 and RLOCK24 register bit not present.,1: SEC24 PRIV24 and RLOCK24 register bit present." newline bitfld.long 0x0 23. "PPEN23,peripheral protection enable 23" "0: SEC23 PRIV23 and RLOCK23 register bit not present.,1: SEC23 PRIV23 and RLOCK23 register bit present." bitfld.long 0x0 22. "PPEN22,peripheral protection enable 22" "0: SEC22 PRIV22 and RLOCK22 register bit not present.,1: SEC22 PRIV22 and RLOCK22 register bit present." newline bitfld.long 0x0 21. "PPEN21,peripheral protection enable 21" "0: SEC21 PRIV21 and RLOCK21 register bit not present.,1: SEC21 PRIV21 and RLOCK21 register bit present." bitfld.long 0x0 20. "PPEN20,peripheral protection enable 20" "0: SEC20 PRIV20 and RLOCK20 register bit not present.,1: SEC20 PRIV20 and RLOCK20 register bit present." newline bitfld.long 0x0 19. "PPEN19,peripheral protection enable 19" "0: SEC19 PRIV19 and RLOCK19 register bit not present.,1: SEC19 PRIV19 and RLOCK19 register bit present." bitfld.long 0x0 18. "PPEN18,peripheral protection enable 18" "0: SEC18 PRIV18 and RLOCK18 register bit not present.,1: SEC18 PRIV18 and RLOCK18 register bit present." newline bitfld.long 0x0 17. "PPEN17,peripheral protection enable 17" "0: SEC17 PRIV17 and RLOCK17 register bit not present.,1: SEC17 PRIV17 and RLOCK17 register bit present." bitfld.long 0x0 16. "PPEN16,peripheral protection enable 16" "0: SEC16 PRIV16 and RLOCK16 register bit not present.,1: SEC16 PRIV16 and RLOCK16 register bit present." newline bitfld.long 0x0 15. "PPEN15,peripheral protection enable 15" "0: SEC15 PRIV15 and RLOCK15 register bit not present.,1: SEC15 PRIV15 and RLOCK15 register bit present." bitfld.long 0x0 14. "PPEN14,peripheral protection enable 14" "0: SEC14 PRIV14 and RLOCK14 register bit not present.,1: SEC14 PRIV14 and RLOCK14 register bit present." newline bitfld.long 0x0 13. "PPEN13,peripheral protection enable 13" "0: SEC13 PRIV13 and RLOCK13 register bit not present.,1: SEC13 PRIV13 and RLOCK13 register bit present." bitfld.long 0x0 12. "PPEN12,peripheral protection enable 12" "0: SEC12 PRIV12 and RLOCK12 register bit not present.,1: SEC12 PRIV12 and RLOCK12 register bit present." newline bitfld.long 0x0 11. "PPEN11,peripheral protection enable 11" "0: SEC11 PRIV11 and RLOCK11 register bit not present.,1: SEC11 PRIV11 and RLOCK11 register bit present." bitfld.long 0x0 10. "PPEN10,peripheral protection enable 10" "0: SEC10 PRIV10 and RLOCK10 register bit not present.,1: SEC10 PRIV10 and RLOCK10 register bit present." newline bitfld.long 0x0 9. "PPEN9,peripheral protection enable 9" "0: SEC9 PRIV9 and RLOCK9 register bit not present.,1: SEC9 PRIV9 and RLOCK9 register bit present." bitfld.long 0x0 8. "PPEN8,peripheral protection enable 8" "0: SEC8 PRIV8 and RLOCK8 register bit not present.,1: SEC8 PRIV8 and RLOCK8 register bit present." newline bitfld.long 0x0 7. "PPEN7,peripheral protection enable 7" "0: SEC7 PRIV7 and RLOCK7 register bit not present.,1: SEC7 PRIV7 and RLOCK7 register bit present." bitfld.long 0x0 6. "PPEN6,peripheral protection enable 6" "0: SEC6 PRIV6 and RLOCK6 register bit not present.,1: SEC6 PRIV6 and RLOCK6 register bit present." newline bitfld.long 0x0 5. "PPEN5,peripheral protection enable 5" "0: SEC5 PRIV5 and RLOCK5 register bit not present.,1: SEC5 PRIV5 and RLOCK5 register bit present." bitfld.long 0x0 4. "PPEN4,peripheral protection enable 4" "0: SEC4 PRIV4 and RLOCK4 register bit not present.,1: SEC4 PRIV4 and RLOCK4 register bit present." newline bitfld.long 0x0 3. "PPEN3,peripheral protection enable 3" "0: SEC3 PRIV3 and RLOCK3 register bit not present.,1: SEC3 PRIV3 and RLOCK3 register bit present." bitfld.long 0x0 2. "PPEN2,peripheral protection enable 2" "0: SEC2 PRIV2 and RLOCK2 register bit not present.,1: SEC2 PRIV2 and RLOCK2 register bit present." newline bitfld.long 0x0 1. "PPEN1,peripheral protection enable 1" "0: SEC1 PRIV1 and RLOCK1 register bit not present.,1: SEC1 PRIV1 and RLOCK1 register bit present." bitfld.long 0x0 0. "PPEN0,peripheral protection enable 0" "0: SEC0 PRIV0 and RLOCK0 register bit not present.,1: SEC0 PRIV0 and RLOCK0 register bit present." line.long 0x4 "RIFSC_PPSR1,RIFSC peripheral protection status register 1" bitfld.long 0x4 31. "PPEN63,peripheral protection enable 63" "0: SEC63 PRIV63 and RLOCK63 register bit not present.,1: SEC63 PRIV63 and RLOCK63 register bit present." bitfld.long 0x4 30. "PPEN62,peripheral protection enable 62" "0: SEC62 PRIV62 and RLOCK62 register bit not present.,1: SEC62 PRIV62 and RLOCK62 register bit present." newline bitfld.long 0x4 29. "PPEN61,peripheral protection enable 61" "0: SEC61 PRIV61 and RLOCK61 register bit not present.,1: SEC61 PRIV61 and RLOCK61 register bit present." bitfld.long 0x4 28. "PPEN60,peripheral protection enable 60" "0: SEC60 PRIV60 and RLOCK60 register bit not present.,1: SEC60 PRIV60 and RLOCK60 register bit present." newline bitfld.long 0x4 27. "PPEN59,peripheral protection enable 59" "0: SEC59 PRIV59 and RLOCK59 register bit not present.,1: SEC59 PRIV59 and RLOCK59 register bit present." bitfld.long 0x4 26. "PPEN58,peripheral protection enable 58" "0: SEC58 PRIV58 and RLOCK58 register bit not present.,1: SEC58 PRIV58 and RLOCK58 register bit present." newline bitfld.long 0x4 25. "PPEN57,peripheral protection enable 57" "0: SEC57 PRIV57 and RLOCK57 register bit not present.,1: SEC57 PRIV57 and RLOCK57 register bit present." bitfld.long 0x4 24. "PPEN56,peripheral protection enable 56" "0: SEC56 PRIV56 and RLOCK56 register bit not present.,1: SEC56 PRIV56 and RLOCK56 register bit present." newline bitfld.long 0x4 23. "PPEN55,peripheral protection enable 55" "0: SEC55 PRIV55 and RLOCK55 register bit not present.,1: SEC55 PRIV55 and RLOCK55 register bit present." bitfld.long 0x4 22. "PPEN54,peripheral protection enable 54" "0: SEC54 PRIV54 and RLOCK54 register bit not present.,1: SEC54 PRIV54 and RLOCK54 register bit present." newline bitfld.long 0x4 21. "PPEN53,peripheral protection enable 53" "0: SEC53 PRIV53 and RLOCK53 register bit not present.,1: SEC53 PRIV53 and RLOCK53 register bit present." bitfld.long 0x4 20. "PPEN52,peripheral protection enable 52" "0: SEC52 PRIV52 and RLOCK52 register bit not present.,1: SEC52 PRIV52 and RLOCK52 register bit present." newline bitfld.long 0x4 19. "PPEN51,peripheral protection enable 51" "0: SEC51 PRIV51 and RLOCK51 register bit not present.,1: SEC51 PRIV51 and RLOCK51 register bit present." bitfld.long 0x4 18. "PPEN50,peripheral protection enable 50" "0: SEC50 PRIV50 and RLOCK50 register bit not present.,1: SEC50 PRIV50 and RLOCK50 register bit present." newline bitfld.long 0x4 17. "PPEN49,peripheral protection enable 49" "0: SEC49 PRIV49 and RLOCK49 register bit not present.,1: SEC49 PRIV49 and RLOCK49 register bit present." bitfld.long 0x4 16. "PPEN48,peripheral protection enable 48" "0: SEC48 PRIV48 and RLOCK48 register bit not present.,1: SEC48 PRIV48 and RLOCK48 register bit present." newline bitfld.long 0x4 15. "PPEN47,peripheral protection enable 47" "0: SEC47 PRIV47 and RLOCK47 register bit not present.,1: SEC47 PRIV47 and RLOCK47 register bit present." bitfld.long 0x4 14. "PPEN46,peripheral protection enable 46" "0: SEC46 PRIV46 and RLOCK46 register bit not present.,1: SEC46 PRIV46 and RLOCK46 register bit present." newline bitfld.long 0x4 13. "PPEN45,peripheral protection enable 45" "0: SEC45 PRIV45 and RLOCK45 register bit not present.,1: SEC45 PRIV45 and RLOCK45 register bit present." bitfld.long 0x4 12. "PPEN44,peripheral protection enable 44" "0: SEC44 PRIV44 and RLOCK44 register bit not present.,1: SEC44 PRIV44 and RLOCK44 register bit present." newline bitfld.long 0x4 11. "PPEN43,peripheral protection enable 43" "0: SEC43 PRIV43 and RLOCK43 register bit not present.,1: SEC43 PRIV43 and RLOCK43 register bit present." bitfld.long 0x4 10. "PPEN42,peripheral protection enable 42" "0: SEC42 PRIV42 and RLOCK42 register bit not present.,1: SEC42 PRIV42 and RLOCK42 register bit present." newline bitfld.long 0x4 9. "PPEN41,peripheral protection enable 41" "0: SEC41 PRIV41 and RLOCK41 register bit not present.,1: SEC41 PRIV41 and RLOCK41 register bit present." bitfld.long 0x4 8. "PPEN40,peripheral protection enable 40" "0: SEC40 PRIV40 and RLOCK40 register bit not present.,1: SEC40 PRIV40 and RLOCK40 register bit present." newline bitfld.long 0x4 7. "PPEN39,peripheral protection enable 39" "0: SEC39 PRIV39 and RLOCK39 register bit not present.,1: SEC39 PRIV39 and RLOCK39 register bit present." bitfld.long 0x4 6. "PPEN38,peripheral protection enable 38" "0: SEC38 PRIV38 and RLOCK38 register bit not present.,1: SEC38 PRIV38 and RLOCK38 register bit present." newline bitfld.long 0x4 5. "PPEN37,peripheral protection enable 37" "0: SEC37 PRIV37 and RLOCK37 register bit not present.,1: SEC37 PRIV37 and RLOCK37 register bit present." bitfld.long 0x4 4. "PPEN36,peripheral protection enable 36" "0: SEC36 PRIV36 and RLOCK36 register bit not present.,1: SEC36 PRIV36 and RLOCK36 register bit present." newline bitfld.long 0x4 3. "PPEN35,peripheral protection enable 35" "0: SEC35 PRIV35 and RLOCK35 register bit not present.,1: SEC35 PRIV35 and RLOCK35 register bit present." bitfld.long 0x4 2. "PPEN34,peripheral protection enable 34" "0: SEC34 PRIV34 and RLOCK34 register bit not present.,1: SEC34 PRIV34 and RLOCK34 register bit present." newline bitfld.long 0x4 1. "PPEN33,peripheral protection enable 33" "0: SEC33 PRIV33 and RLOCK33 register bit not present.,1: SEC33 PRIV33 and RLOCK33 register bit present." bitfld.long 0x4 0. "PPEN32,peripheral protection enable 32" "0: SEC32 PRIV32 and RLOCK32 register bit not present.,1: SEC32 PRIV32 and RLOCK32 register bit present." line.long 0x8 "RIFSC_PPSR2,RIFSC peripheral protection status register 2" bitfld.long 0x8 31. "PPEN95,peripheral protection enable 95" "0: SEC95 PRIV95 and RLOCK95 register bit not present.,1: SEC95 PRIV95 and RLOCK95 register bit present." bitfld.long 0x8 30. "PPEN94,peripheral protection enable 94" "0: SEC94 PRIV94 and RLOCK94 register bit not present.,1: SEC94 PRIV94 and RLOCK94 register bit present." newline bitfld.long 0x8 29. "PPEN93,peripheral protection enable 93" "0: SEC93 PRIV93 and RLOCK93 register bit not present.,1: SEC93 PRIV93 and RLOCK93 register bit present." bitfld.long 0x8 28. "PPEN92,peripheral protection enable 92" "0: SEC92 PRIV92 and RLOCK92 register bit not present.,1: SEC92 PRIV92 and RLOCK92 register bit present." newline bitfld.long 0x8 27. "PPEN91,peripheral protection enable 91" "0: SEC91 PRIV91 and RLOCK91 register bit not present.,1: SEC91 PRIV91 and RLOCK91 register bit present." bitfld.long 0x8 26. "PPEN90,peripheral protection enable 90" "0: SEC90 PRIV90 and RLOCK90 register bit not present.,1: SEC90 PRIV90 and RLOCK90 register bit present." newline bitfld.long 0x8 25. "PPEN89,peripheral protection enable 89" "0: SEC89 PRIV89 and RLOCK89 register bit not present.,1: SEC89 PRIV89 and RLOCK89 register bit present." bitfld.long 0x8 24. "PPEN88,peripheral protection enable 88" "0: SEC88 PRIV88 and RLOCK88 register bit not present.,1: SEC88 PRIV88 and RLOCK88 register bit present." newline bitfld.long 0x8 23. "PPEN87,peripheral protection enable 87" "0: SEC87 PRIV87 and RLOCK87 register bit not present.,1: SEC87 PRIV87 and RLOCK87 register bit present." bitfld.long 0x8 22. "PPEN86,peripheral protection enable 86" "0: SEC86 PRIV86 and RLOCK86 register bit not present.,1: SEC86 PRIV86 and RLOCK86 register bit present." newline bitfld.long 0x8 21. "PPEN85,peripheral protection enable 85" "0: SEC85 PRIV85 and RLOCK85 register bit not present.,1: SEC85 PRIV85 and RLOCK85 register bit present." bitfld.long 0x8 20. "PPEN84,peripheral protection enable 84" "0: SEC84 PRIV84 and RLOCK84 register bit not present.,1: SEC84 PRIV84 and RLOCK84 register bit present." newline bitfld.long 0x8 19. "PPEN83,peripheral protection enable 83" "0: SEC83 PRIV83 and RLOCK83 register bit not present.,1: SEC83 PRIV83 and RLOCK83 register bit present." bitfld.long 0x8 18. "PPEN82,peripheral protection enable 82" "0: SEC82 PRIV82 and RLOCK82 register bit not present.,1: SEC82 PRIV82 and RLOCK82 register bit present." newline bitfld.long 0x8 17. "PPEN81,peripheral protection enable 81" "0: SEC81 PRIV81 and RLOCK81 register bit not present.,1: SEC81 PRIV81 and RLOCK81 register bit present." bitfld.long 0x8 16. "PPEN80,peripheral protection enable 80" "0: SEC80 PRIV80 and RLOCK80 register bit not present.,1: SEC80 PRIV80 and RLOCK80 register bit present." newline bitfld.long 0x8 15. "PPEN79,peripheral protection enable 79" "0: SEC79 PRIV79 and RLOCK79 register bit not present.,1: SEC79 PRIV79 and RLOCK79 register bit present." bitfld.long 0x8 14. "PPEN78,peripheral protection enable 78" "0: SEC78 PRIV78 and RLOCK78 register bit not present.,1: SEC78 PRIV78 and RLOCK78 register bit present." newline bitfld.long 0x8 13. "PPEN77,peripheral protection enable 77" "0: SEC77 PRIV77 and RLOCK77 register bit not present.,1: SEC77 PRIV77 and RLOCK77 register bit present." bitfld.long 0x8 12. "PPEN76,peripheral protection enable 76" "0: SEC76 PRIV76 and RLOCK76 register bit not present.,1: SEC76 PRIV76 and RLOCK76 register bit present." newline bitfld.long 0x8 11. "PPEN75,peripheral protection enable 75" "0: SEC75 PRIV75 and RLOCK75 register bit not present.,1: SEC75 PRIV75 and RLOCK75 register bit present." bitfld.long 0x8 10. "PPEN74,peripheral protection enable 74" "0: SEC74 PRIV74 and RLOCK74 register bit not present.,1: SEC74 PRIV74 and RLOCK74 register bit present." newline bitfld.long 0x8 9. "PPEN73,peripheral protection enable 73" "0: SEC73 PRIV73 and RLOCK73 register bit not present.,1: SEC73 PRIV73 and RLOCK73 register bit present." bitfld.long 0x8 8. "PPEN72,peripheral protection enable 72" "0: SEC72 PRIV72 and RLOCK72 register bit not present.,1: SEC72 PRIV72 and RLOCK72 register bit present." newline bitfld.long 0x8 7. "PPEN71,peripheral protection enable 71" "0: SEC71 PRIV71 and RLOCK71 register bit not present.,1: SEC71 PRIV71 and RLOCK71 register bit present." bitfld.long 0x8 6. "PPEN70,peripheral protection enable 70" "0: SEC70 PRIV70 and RLOCK70 register bit not present.,1: SEC70 PRIV70 and RLOCK70 register bit present." newline bitfld.long 0x8 5. "PPEN69,peripheral protection enable 69" "0: SEC69 PRIV69 and RLOCK69 register bit not present.,1: SEC69 PRIV69 and RLOCK69 register bit present." bitfld.long 0x8 4. "PPEN68,peripheral protection enable 68" "0: SEC68 PRIV68 and RLOCK68 register bit not present.,1: SEC68 PRIV68 and RLOCK68 register bit present." newline bitfld.long 0x8 3. "PPEN67,peripheral protection enable 67" "0: SEC67 PRIV67 and RLOCK67 register bit not present.,1: SEC67 PRIV67 and RLOCK67 register bit present." bitfld.long 0x8 2. "PPEN66,peripheral protection enable 66" "0: SEC66 PRIV66 and RLOCK66 register bit not present.,1: SEC66 PRIV66 and RLOCK66 register bit present." newline bitfld.long 0x8 1. "PPEN65,peripheral protection enable 65" "0: SEC65 PRIV65 and RLOCK65 register bit not present.,1: SEC65 PRIV65 and RLOCK65 register bit present." bitfld.long 0x8 0. "PPEN64,peripheral protection enable 64" "0: SEC64 PRIV64 and RLOCK64 register bit not present.,1: SEC64 PRIV64 and RLOCK64 register bit present." line.long 0xC "RIFSC_PPSR3,RIFSC peripheral protection status register 3" bitfld.long 0xC 31. "PPEN127,peripheral protection enable 127" "0: SEC127 PRIV127 and RLOCK127 register bit not..,1: SEC127 PRIV127 and RLOCK127 register bit present." bitfld.long 0xC 30. "PPEN126,peripheral protection enable 126" "0: SEC126 PRIV126 and RLOCK126 register bit not..,1: SEC126 PRIV126 and RLOCK126 register bit present." newline bitfld.long 0xC 29. "PPEN125,peripheral protection enable 125" "0: SEC125 PRIV125 and RLOCK125 register bit not..,1: SEC125 PRIV125 and RLOCK125 register bit present." bitfld.long 0xC 28. "PPEN124,peripheral protection enable 124" "0: SEC124 PRIV124 and RLOCK124 register bit not..,1: SEC124 PRIV124 and RLOCK124 register bit present." newline bitfld.long 0xC 27. "PPEN123,peripheral protection enable 123" "0: SEC123 PRIV123 and RLOCK123 register bit not..,1: SEC123 PRIV123 and RLOCK123 register bit present." bitfld.long 0xC 26. "PPEN122,peripheral protection enable 122" "0: SEC122 PRIV122 and RLOCK122 register bit not..,1: SEC122 PRIV122 and RLOCK122 register bit present." newline bitfld.long 0xC 25. "PPEN121,peripheral protection enable 121" "0: SEC121 PRIV121 and RLOCK121 register bit not..,1: SEC121 PRIV121 and RLOCK121 register bit present." bitfld.long 0xC 24. "PPEN120,peripheral protection enable 120" "0: SEC120 PRIV120 and RLOCK120 register bit not..,1: SEC120 PRIV120 and RLOCK120 register bit present." newline bitfld.long 0xC 23. "PPEN119,peripheral protection enable 119" "0: SEC119 PRIV119 and RLOCK119 register bit not..,1: SEC119 PRIV119 and RLOCK119 register bit present." bitfld.long 0xC 22. "PPEN118,peripheral protection enable 118" "0: SEC118 PRIV118 and RLOCK118 register bit not..,1: SEC118 PRIV118 and RLOCK118 register bit present." newline bitfld.long 0xC 21. "PPEN117,peripheral protection enable 117" "0: SEC117 PRIV117 and RLOCK117 register bit not..,1: SEC117 PRIV117 and RLOCK117 register bit present." bitfld.long 0xC 20. "PPEN116,peripheral protection enable 116" "0: SEC116 PRIV116 and RLOCK116 register bit not..,1: SEC116 PRIV116 and RLOCK116 register bit present." newline bitfld.long 0xC 19. "PPEN115,peripheral protection enable 115" "0: SEC115 PRIV115 and RLOCK115 register bit not..,1: SEC115 PRIV115 and RLOCK115 register bit present." bitfld.long 0xC 18. "PPEN114,peripheral protection enable 114" "0: SEC114 PRIV114 and RLOCK114 register bit not..,1: SEC114 PRIV114 and RLOCK114 register bit present." newline bitfld.long 0xC 17. "PPEN113,peripheral protection enable 113" "0: SEC113 PRIV113 and RLOCK113 register bit not..,1: SEC113 PRIV113 and RLOCK113 register bit present." bitfld.long 0xC 16. "PPEN112,peripheral protection enable 112" "0: SEC112 PRIV112 and RLOCK112 register bit not..,1: SEC112 PRIV112 and RLOCK112 register bit present." newline bitfld.long 0xC 15. "PPEN111,peripheral protection enable 111" "0: SEC111 PRIV111 and RLOCK111 register bit not..,1: SEC111 PRIV111 and RLOCK111 register bit present." bitfld.long 0xC 14. "PPEN110,peripheral protection enable 110" "0: SEC110 PRIV110 and RLOCK110 register bit not..,1: SEC110 PRIV110 and RLOCK110 register bit present." newline bitfld.long 0xC 13. "PPEN109,peripheral protection enable 109" "0: SEC109 PRIV109 and RLOCK109 register bit not..,1: SEC109 PRIV109 and RLOCK109 register bit present." bitfld.long 0xC 12. "PPEN108,peripheral protection enable 108" "0: SEC108 PRIV108 and RLOCK108 register bit not..,1: SEC108 PRIV108 and RLOCK108 register bit present." newline bitfld.long 0xC 11. "PPEN107,peripheral protection enable 107" "0: SEC107 PRIV107 and RLOCK107 register bit not..,1: SEC107 PRIV107 and RLOCK107 register bit present." bitfld.long 0xC 10. "PPEN106,peripheral protection enable 106" "0: SEC106 PRIV106 and RLOCK106 register bit not..,1: SEC106 PRIV106 and RLOCK106 register bit present." newline bitfld.long 0xC 9. "PPEN105,peripheral protection enable 105" "0: SEC105 PRIV105 and RLOCK105 register bit not..,1: SEC105 PRIV105 and RLOCK105 register bit present." bitfld.long 0xC 8. "PPEN104,peripheral protection enable 104" "0: SEC104 PRIV104 and RLOCK104 register bit not..,1: SEC104 PRIV104 and RLOCK104 register bit present." newline bitfld.long 0xC 7. "PPEN103,peripheral protection enable 103" "0: SEC103 PRIV103 and RLOCK103 register bit not..,1: SEC103 PRIV103 and RLOCK103 register bit present." bitfld.long 0xC 6. "PPEN102,peripheral protection enable 102" "0: SEC102 PRIV102 and RLOCK102 register bit not..,1: SEC102 PRIV102 and RLOCK102 register bit present." newline bitfld.long 0xC 5. "PPEN101,peripheral protection enable 101" "0: SEC101 PRIV101 and RLOCK101 register bit not..,1: SEC101 PRIV101 and RLOCK101 register bit present." bitfld.long 0xC 4. "PPEN100,peripheral protection enable 100" "0: SEC100 PRIV100 and RLOCK100 register bit not..,1: SEC100 PRIV100 and RLOCK100 register bit present." newline bitfld.long 0xC 3. "PPEN99,peripheral protection enable 99" "0: SEC99 PRIV99 and RLOCK99 register bit not present.,1: SEC99 PRIV99 and RLOCK99 register bit present." bitfld.long 0xC 2. "PPEN98,peripheral protection enable 98" "0: SEC98 PRIV98 and RLOCK98 register bit not present.,1: SEC98 PRIV98 and RLOCK98 register bit present." newline bitfld.long 0xC 1. "PPEN97,peripheral protection enable 97" "0: SEC97 PRIV97 and RLOCK97 register bit not present.,1: SEC97 PRIV97 and RLOCK97 register bit present." bitfld.long 0xC 0. "PPEN96,peripheral protection enable 96" "0: SEC96 PRIV96 and RLOCK96 register bit not present.,1: SEC96 PRIV96 and RLOCK96 register bit present." line.long 0x10 "RIFSC_PPSR4,RIFSC peripheral protection status register 4" bitfld.long 0x10 31. "PPEN159,peripheral protection enable 159" "0: SEC159 PRIV159 and RLOCK159 register bit not..,1: SEC159 PRIV159 and RLOCK159 register bit present." bitfld.long 0x10 30. "PPEN158,peripheral protection enable 158" "0: SEC158 PRIV158 and RLOCK158 register bit not..,1: SEC158 PRIV158 and RLOCK158 register bit present." newline bitfld.long 0x10 29. "PPEN157,peripheral protection enable 157" "0: SEC157 PRIV157 and RLOCK157 register bit not..,1: SEC157 PRIV157 and RLOCK157 register bit present." bitfld.long 0x10 28. "PPEN156,peripheral protection enable 156" "0: SEC156 PRIV156 and RLOCK156 register bit not..,1: SEC156 PRIV156 and RLOCK156 register bit present." newline bitfld.long 0x10 27. "PPEN155,peripheral protection enable 155" "0: SEC155 PRIV155 and RLOCK155 register bit not..,1: SEC155 PRIV155 and RLOCK155 register bit present." bitfld.long 0x10 26. "PPEN154,peripheral protection enable 154" "0: SEC154 PRIV154 and RLOCK154 register bit not..,1: SEC154 PRIV154 and RLOCK154 register bit present." newline bitfld.long 0x10 25. "PPEN153,peripheral protection enable 153" "0: SEC153 PRIV153 and RLOCK153 register bit not..,1: SEC153 PRIV153 and RLOCK153 register bit present." bitfld.long 0x10 24. "PPEN152,peripheral protection enable 152" "0: SEC152 PRIV152 and RLOCK152 register bit not..,1: SEC152 PRIV152 and RLOCK152 register bit present." newline bitfld.long 0x10 23. "PPEN151,peripheral protection enable 151" "0: SEC151 PRIV151 and RLOCK151 register bit not..,1: SEC151 PRIV151 and RLOCK151 register bit present." bitfld.long 0x10 22. "PPEN150,peripheral protection enable 150" "0: SEC150 PRIV150 and RLOCK150 register bit not..,1: SEC150 PRIV150 and RLOCK150 register bit present." newline bitfld.long 0x10 21. "PPEN149,peripheral protection enable 149" "0: SEC149 PRIV149 and RLOCK149 register bit not..,1: SEC149 PRIV149 and RLOCK149 register bit present." bitfld.long 0x10 20. "PPEN148,peripheral protection enable 148" "0: SEC148 PRIV148 and RLOCK148 register bit not..,1: SEC148 PRIV148 and RLOCK148 register bit present." newline bitfld.long 0x10 19. "PPEN147,peripheral protection enable 147" "0: SEC147 PRIV147 and RLOCK147 register bit not..,1: SEC147 PRIV147 and RLOCK147 register bit present." bitfld.long 0x10 18. "PPEN146,peripheral protection enable 146" "0: SEC146 PRIV146 and RLOCK146 register bit not..,1: SEC146 PRIV146 and RLOCK146 register bit present." newline bitfld.long 0x10 17. "PPEN145,peripheral protection enable 145" "0: SEC145 PRIV145 and RLOCK145 register bit not..,1: SEC145 PRIV145 and RLOCK145 register bit present." bitfld.long 0x10 16. "PPEN144,peripheral protection enable 144" "0: SEC144 PRIV144 and RLOCK144 register bit not..,1: SEC144 PRIV144 and RLOCK144 register bit present." newline bitfld.long 0x10 15. "PPEN143,peripheral protection enable 143" "0: SEC143 PRIV143 and RLOCK143 register bit not..,1: SEC143 PRIV143 and RLOCK143 register bit present." bitfld.long 0x10 14. "PPEN142,peripheral protection enable 142" "0: SEC142 PRIV142 and RLOCK142 register bit not..,1: SEC142 PRIV142 and RLOCK142 register bit present." newline bitfld.long 0x10 13. "PPEN141,peripheral protection enable 141" "0: SEC141 PRIV141 and RLOCK141 register bit not..,1: SEC141 PRIV141 and RLOCK141 register bit present." bitfld.long 0x10 12. "PPEN140,peripheral protection enable 140" "0: SEC140 PRIV140 and RLOCK140 register bit not..,1: SEC140 PRIV140 and RLOCK140 register bit present." newline bitfld.long 0x10 11. "PPEN139,peripheral protection enable 139" "0: SEC139 PRIV139 and RLOCK139 register bit not..,1: SEC139 PRIV139 and RLOCK139 register bit present." bitfld.long 0x10 10. "PPEN138,peripheral protection enable 138" "0: SEC138 PRIV138 and RLOCK138 register bit not..,1: SEC138 PRIV138 and RLOCK138 register bit present." newline bitfld.long 0x10 9. "PPEN137,peripheral protection enable 137" "0: SEC137 PRIV137 and RLOCK137 register bit not..,1: SEC137 PRIV137 and RLOCK137 register bit present." bitfld.long 0x10 8. "PPEN136,peripheral protection enable 136" "0: SEC136 PRIV136 and RLOCK136 register bit not..,1: SEC136 PRIV136 and RLOCK136 register bit present." newline bitfld.long 0x10 7. "PPEN135,peripheral protection enable 135" "0: SEC135 PRIV135 and RLOCK135 register bit not..,1: SEC135 PRIV135 and RLOCK135 register bit present." bitfld.long 0x10 6. "PPEN134,peripheral protection enable 134" "0: SEC134 PRIV134 and RLOCK134 register bit not..,1: SEC134 PRIV134 and RLOCK134 register bit present." newline bitfld.long 0x10 5. "PPEN133,peripheral protection enable 133" "0: SEC133 PRIV133 and RLOCK133 register bit not..,1: SEC133 PRIV133 and RLOCK133 register bit present." bitfld.long 0x10 4. "PPEN132,peripheral protection enable 132" "0: SEC132 PRIV132 and RLOCK132 register bit not..,1: SEC132 PRIV132 and RLOCK132 register bit present." newline bitfld.long 0x10 3. "PPEN131,peripheral protection enable 131" "0: SEC131 PRIV131 and RLOCK131 register bit not..,1: SEC131 PRIV131 and RLOCK131 register bit present." bitfld.long 0x10 2. "PPEN130,peripheral protection enable 130" "0: SEC130 PRIV130 and RLOCK130 register bit not..,1: SEC130 PRIV130 and RLOCK130 register bit present." newline bitfld.long 0x10 1. "PPEN129,peripheral protection enable 129" "0: SEC129 PRIV129 and RLOCK129 register bit not..,1: SEC129 PRIV129 and RLOCK129 register bit present." bitfld.long 0x10 0. "PPEN128,peripheral protection enable 128" "0: SEC128 PRIV128 and RLOCK128 register bit not..,1: SEC128 PRIV128 and RLOCK128 register bit present." line.long 0x14 "RIFSC_PPSR5,RIFSC peripheral protection status register 5" bitfld.long 0x14 31. "PPEN191,peripheral protection enable 191" "0: SEC191 PRIV191 and RLOCK191 register bit not..,1: SEC191 PRIV191 and RLOCK191 register bit present." bitfld.long 0x14 30. "PPEN190,peripheral protection enable 190" "0: SEC190 PRIV190 and RLOCK190 register bit not..,1: SEC190 PRIV190 and RLOCK190 register bit present." newline bitfld.long 0x14 29. "PPEN189,peripheral protection enable 189" "0: SEC189 PRIV189 and RLOCK189 register bit not..,1: SEC189 PRIV189 and RLOCK189 register bit present." bitfld.long 0x14 28. "PPEN188,peripheral protection enable 188" "0: SEC188 PRIV188 and RLOCK188 register bit not..,1: SEC188 PRIV188 and RLOCK188 register bit present." newline bitfld.long 0x14 27. "PPEN187,peripheral protection enable 187" "0: SEC187 PRIV187 and RLOCK187 register bit not..,1: SEC187 PRIV187 and RLOCK187 register bit present." bitfld.long 0x14 26. "PPEN186,peripheral protection enable 186" "0: SEC186 PRIV186 and RLOCK186 register bit not..,1: SEC186 PRIV186 and RLOCK186 register bit present." newline bitfld.long 0x14 25. "PPEN185,peripheral protection enable 185" "0: SEC185 PRIV185 and RLOCK185 register bit not..,1: SEC185 PRIV185 and RLOCK185 register bit present." bitfld.long 0x14 24. "PPEN184,peripheral protection enable 184" "0: SEC184 PRIV184 and RLOCK184 register bit not..,1: SEC184 PRIV184 and RLOCK184 register bit present." newline bitfld.long 0x14 23. "PPEN183,peripheral protection enable 183" "0: SEC183 PRIV183 and RLOCK183 register bit not..,1: SEC183 PRIV183 and RLOCK183 register bit present." bitfld.long 0x14 22. "PPEN182,peripheral protection enable 182" "0: SEC182 PRIV182 and RLOCK182 register bit not..,1: SEC182 PRIV182 and RLOCK182 register bit present." newline bitfld.long 0x14 21. "PPEN181,peripheral protection enable 181" "0: SEC181 PRIV181 and RLOCK181 register bit not..,1: SEC181 PRIV181 and RLOCK181 register bit present." bitfld.long 0x14 20. "PPEN180,peripheral protection enable 180" "0: SEC180 PRIV180 and RLOCK180 register bit not..,1: SEC180 PRIV180 and RLOCK180 register bit present." newline bitfld.long 0x14 19. "PPEN179,peripheral protection enable 179" "0: SEC179 PRIV179 and RLOCK179 register bit not..,1: SEC179 PRIV179 and RLOCK179 register bit present." bitfld.long 0x14 18. "PPEN178,peripheral protection enable 178" "0: SEC178 PRIV178 and RLOCK178 register bit not..,1: SEC178 PRIV178 and RLOCK178 register bit present." newline bitfld.long 0x14 17. "PPEN177,peripheral protection enable 177" "0: SEC177 PRIV177 and RLOCK177 register bit not..,1: SEC177 PRIV177 and RLOCK177 register bit present." bitfld.long 0x14 16. "PPEN176,peripheral protection enable 176" "0: SEC176 PRIV176 and RLOCK176 register bit not..,1: SEC176 PRIV176 and RLOCK176 register bit present." newline bitfld.long 0x14 15. "PPEN175,peripheral protection enable 175" "0: SEC175 PRIV175 and RLOCK175 register bit not..,1: SEC175 PRIV175 and RLOCK175 register bit present." bitfld.long 0x14 14. "PPEN174,peripheral protection enable 174" "0: SEC174 PRIV174 and RLOCK174 register bit not..,1: SEC174 PRIV174 and RLOCK174 register bit present." newline bitfld.long 0x14 13. "PPEN173,peripheral protection enable 173" "0: SEC173 PRIV173 and RLOCK173 register bit not..,1: SEC173 PRIV173 and RLOCK173 register bit present." bitfld.long 0x14 12. "PPEN172,peripheral protection enable 172" "0: SEC172 PRIV172 and RLOCK172 register bit not..,1: SEC172 PRIV172 and RLOCK172 register bit present." newline bitfld.long 0x14 11. "PPEN171,peripheral protection enable 171" "0: SEC171 PRIV171 and RLOCK171 register bit not..,1: SEC171 PRIV171 and RLOCK171 register bit present." bitfld.long 0x14 10. "PPEN170,peripheral protection enable 170" "0: SEC170 PRIV170 and RLOCK170 register bit not..,1: SEC170 PRIV170 and RLOCK170 register bit present." newline bitfld.long 0x14 9. "PPEN169,peripheral protection enable 169" "0: SEC169 PRIV169 and RLOCK169 register bit not..,1: SEC169 PRIV169 and RLOCK169 register bit present." bitfld.long 0x14 8. "PPEN168,peripheral protection enable 168" "0: SEC168 PRIV168 and RLOCK168 register bit not..,1: SEC168 PRIV168 and RLOCK168 register bit present." newline bitfld.long 0x14 7. "PPEN167,peripheral protection enable 167" "0: SEC167 PRIV167 and RLOCK167 register bit not..,1: SEC167 PRIV167 and RLOCK167 register bit present." bitfld.long 0x14 6. "PPEN166,peripheral protection enable 166" "0: SEC166 PRIV166 and RLOCK166 register bit not..,1: SEC166 PRIV166 and RLOCK166 register bit present." newline bitfld.long 0x14 5. "PPEN165,peripheral protection enable 165" "0: SEC165 PRIV165 and RLOCK165 register bit not..,1: SEC165 PRIV165 and RLOCK165 register bit present." bitfld.long 0x14 4. "PPEN164,peripheral protection enable 164" "0: SEC164 PRIV164 and RLOCK164 register bit not..,1: SEC164 PRIV164 and RLOCK164 register bit present." newline bitfld.long 0x14 3. "PPEN163,peripheral protection enable 163" "0: SEC163 PRIV163 and RLOCK163 register bit not..,1: SEC163 PRIV163 and RLOCK163 register bit present." bitfld.long 0x14 2. "PPEN162,peripheral protection enable 162" "0: SEC162 PRIV162 and RLOCK162 register bit not..,1: SEC162 PRIV162 and RLOCK162 register bit present." newline bitfld.long 0x14 1. "PPEN161,peripheral protection enable 161" "0: SEC161 PRIV161 and RLOCK161 register bit not..,1: SEC161 PRIV161 and RLOCK161 register bit present." bitfld.long 0x14 0. "PPEN160,peripheral protection enable 160" "0: SEC160 PRIV160 and RLOCK160 register bit not..,1: SEC160 PRIV160 and RLOCK160 register bit present." tree.end tree "RIFSC_S" base ad:0x54024000 group.long 0x0++0x3 line.long 0x0 "RIFSC_RISC_CR,RIFSC RISC slave configuration register x" bitfld.long 0x0 0. "GLOCK,Global lock" "0: RIFSC RISC registers are writable.,1: All writes to RIFSC RISC registers are ignored." group.long 0x10++0x17 line.long 0x0 "RIFSC_RISC_SECCFGR0,RIFSC RISC slave security configuration register 0" bitfld.long 0x0 31. "SEC31,security configuration for peripheral 31" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 30. "SEC30,security configuration for peripheral 30" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 29. "SEC29,security configuration for peripheral 29" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 28. "SEC28,security configuration for peripheral 28" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 27. "SEC27,security configuration for peripheral 27" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 26. "SEC26,security configuration for peripheral 26" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 25. "SEC25,security configuration for peripheral 25" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 24. "SEC24,security configuration for peripheral 24" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 23. "SEC23,security configuration for peripheral 23" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 22. "SEC22,security configuration for peripheral 22" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 21. "SEC21,security configuration for peripheral 21" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 20. "SEC20,security configuration for peripheral 20" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 19. "SEC19,security configuration for peripheral 19" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 18. "SEC18,security configuration for peripheral 18" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 17. "SEC17,security configuration for peripheral 17" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 16. "SEC16,security configuration for peripheral 16" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 15. "SEC15,security configuration for peripheral 15" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 14. "SEC14,security configuration for peripheral 14" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 13. "SEC13,security configuration for peripheral 13" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 12. "SEC12,security configuration for peripheral 12" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 11. "SEC11,security configuration for peripheral 11" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 10. "SEC10,security configuration for peripheral 10" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 9. "SEC9,security configuration for peripheral 9" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 8. "SEC8,security configuration for peripheral 8" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 7. "SEC7,security configuration for peripheral 7" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 6. "SEC6,security configuration for peripheral 6" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 5. "SEC5,security configuration for peripheral 5" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 4. "SEC4,security configuration for peripheral 4" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 3. "SEC3,security configuration for peripheral 3" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 2. "SEC2,security configuration for peripheral 2" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x0 1. "SEC1,security configuration for peripheral 1" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x0 0. "SEC0,security configuration for peripheral 0" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." line.long 0x4 "RIFSC_RISC_SECCFGR1,RIFSC RISC slave security configuration register 1" bitfld.long 0x4 31. "SEC63,security configuration for peripheral 63" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 30. "SEC62,security configuration for peripheral 62" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 29. "SEC61,security configuration for peripheral 61" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 28. "SEC60,security configuration for peripheral 60" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 27. "SEC59,security configuration for peripheral 59" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 26. "SEC58,security configuration for peripheral 58" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 25. "SEC57,security configuration for peripheral 57" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 24. "SEC56,security configuration for peripheral 56" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 23. "SEC55,security configuration for peripheral 55" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 22. "SEC54,security configuration for peripheral 54" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 21. "SEC53,security configuration for peripheral 53" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 20. "SEC52,security configuration for peripheral 52" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 19. "SEC51,security configuration for peripheral 51" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 18. "SEC50,security configuration for peripheral 50" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 17. "SEC49,security configuration for peripheral 49" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 16. "SEC48,security configuration for peripheral 48" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 15. "SEC47,security configuration for peripheral 47" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 14. "SEC46,security configuration for peripheral 46" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 13. "SEC45,security configuration for peripheral 45" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 12. "SEC44,security configuration for peripheral 44" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 11. "SEC43,security configuration for peripheral 43" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 10. "SEC42,security configuration for peripheral 42" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 9. "SEC41,security configuration for peripheral 41" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 8. "SEC40,security configuration for peripheral 40" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 7. "SEC39,security configuration for peripheral 39" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 6. "SEC38,security configuration for peripheral 38" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 5. "SEC37,security configuration for peripheral 37" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 4. "SEC36,security configuration for peripheral 36" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 3. "SEC35,security configuration for peripheral 35" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 2. "SEC34,security configuration for peripheral 34" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x4 1. "SEC33,security configuration for peripheral 33" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x4 0. "SEC32,security configuration for peripheral 32" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." line.long 0x8 "RIFSC_RISC_SECCFGR2,RIFSC RISC slave security configuration register 2" bitfld.long 0x8 31. "SEC95,security configuration for peripheral 95" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 30. "SEC94,security configuration for peripheral 94" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 29. "SEC93,security configuration for peripheral 93" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 28. "SEC92,security configuration for peripheral 92" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 27. "SEC91,security configuration for peripheral 91" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 26. "SEC90,security configuration for peripheral 90" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 25. "SEC89,security configuration for peripheral 89" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 24. "SEC88,security configuration for peripheral 88" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 23. "SEC87,security configuration for peripheral 87" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 22. "SEC86,security configuration for peripheral 86" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 21. "SEC85,security configuration for peripheral 85" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 20. "SEC84,security configuration for peripheral 84" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 19. "SEC83,security configuration for peripheral 83" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 18. "SEC82,security configuration for peripheral 82" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 17. "SEC81,security configuration for peripheral 81" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 16. "SEC80,security configuration for peripheral 80" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 15. "SEC79,security configuration for peripheral 79" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 14. "SEC78,security configuration for peripheral 78" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 13. "SEC77,security configuration for peripheral 77" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 12. "SEC76,security configuration for peripheral 76" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 11. "SEC75,security configuration for peripheral 75" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 10. "SEC74,security configuration for peripheral 74" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 9. "SEC73,security configuration for peripheral 73" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 8. "SEC72,security configuration for peripheral 72" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 7. "SEC71,security configuration for peripheral 71" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 6. "SEC70,security configuration for peripheral 70" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 5. "SEC69,security configuration for peripheral 69" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 4. "SEC68,security configuration for peripheral 68" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 3. "SEC67,security configuration for peripheral 67" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 2. "SEC66,security configuration for peripheral 66" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x8 1. "SEC65,security configuration for peripheral 65" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x8 0. "SEC64,security configuration for peripheral 64" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." line.long 0xC "RIFSC_RISC_SECCFGR3,RIFSC RISC slave security configuration register 3" bitfld.long 0xC 31. "SEC127,security configuration for peripheral 127" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 30. "SEC126,security configuration for peripheral 126" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 29. "SEC125,security configuration for peripheral 125" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 28. "SEC124,security configuration for peripheral 124" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 27. "SEC123,security configuration for peripheral 123" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 26. "SEC122,security configuration for peripheral 122" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 25. "SEC121,security configuration for peripheral 121" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 24. "SEC120,security configuration for peripheral 120" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 23. "SEC119,security configuration for peripheral 119" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 22. "SEC118,security configuration for peripheral 118" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 21. "SEC117,security configuration for peripheral 117" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 20. "SEC116,security configuration for peripheral 116" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 19. "SEC115,security configuration for peripheral 115" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 18. "SEC114,security configuration for peripheral 114" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 17. "SEC113,security configuration for peripheral 113" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 16. "SEC112,security configuration for peripheral 112" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 15. "SEC111,security configuration for peripheral 111" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 14. "SEC110,security configuration for peripheral 110" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 13. "SEC109,security configuration for peripheral 109" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 12. "SEC108,security configuration for peripheral 108" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 11. "SEC107,security configuration for peripheral 107" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 10. "SEC106,security configuration for peripheral 106" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 9. "SEC105,security configuration for peripheral 105" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 8. "SEC104,security configuration for peripheral 104" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 7. "SEC103,security configuration for peripheral 103" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 6. "SEC102,security configuration for peripheral 102" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 5. "SEC101,security configuration for peripheral 101" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 4. "SEC100,security configuration for peripheral 100" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 3. "SEC99,security configuration for peripheral 99" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 2. "SEC98,security configuration for peripheral 98" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0xC 1. "SEC97,security configuration for peripheral 97" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0xC 0. "SEC96,security configuration for peripheral 96" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." line.long 0x10 "RIFSC_RISC_SECCFGR4,RIFSC RISC slave security configuration register 4" bitfld.long 0x10 31. "SEC159,security configuration for peripheral 159" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 30. "SEC158,security configuration for peripheral 158" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 29. "SEC157,security configuration for peripheral 157" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 28. "SEC156,security configuration for peripheral 156" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 27. "SEC155,security configuration for peripheral 155" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 26. "SEC154,security configuration for peripheral 154" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 25. "SEC153,security configuration for peripheral 153" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 24. "SEC152,security configuration for peripheral 152" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 23. "SEC151,security configuration for peripheral 151" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 22. "SEC150,security configuration for peripheral 150" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 21. "SEC149,security configuration for peripheral 149" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 20. "SEC148,security configuration for peripheral 148" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 19. "SEC147,security configuration for peripheral 147" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 18. "SEC146,security configuration for peripheral 146" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 17. "SEC145,security configuration for peripheral 145" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 16. "SEC144,security configuration for peripheral 144" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 15. "SEC143,security configuration for peripheral 143" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 14. "SEC142,security configuration for peripheral 142" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 13. "SEC141,security configuration for peripheral 141" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 12. "SEC140,security configuration for peripheral 140" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 11. "SEC139,security configuration for peripheral 139" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 10. "SEC138,security configuration for peripheral 138" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 9. "SEC137,security configuration for peripheral 137" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 8. "SEC136,security configuration for peripheral 136" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 7. "SEC135,security configuration for peripheral 135" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 6. "SEC134,security configuration for peripheral 134" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 5. "SEC133,security configuration for peripheral 133" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 4. "SEC132,security configuration for peripheral 132" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 3. "SEC131,security configuration for peripheral 131" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 2. "SEC130,security configuration for peripheral 130" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x10 1. "SEC129,security configuration for peripheral 129" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x10 0. "SEC128,security configuration for peripheral 128" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." line.long 0x14 "RIFSC_RISC_SECCFGR5,RIFSC RISC slave security configuration register 5" bitfld.long 0x14 31. "SEC191,security configuration for peripheral 191" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 30. "SEC190,security configuration for peripheral 190" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 29. "SEC189,security configuration for peripheral 189" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 28. "SEC188,security configuration for peripheral 188" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 27. "SEC187,security configuration for peripheral 187" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 26. "SEC186,security configuration for peripheral 186" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 25. "SEC185,security configuration for peripheral 185" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 24. "SEC184,security configuration for peripheral 184" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 23. "SEC183,security configuration for peripheral 183" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 22. "SEC182,security configuration for peripheral 182" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 21. "SEC181,security configuration for peripheral 181" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 20. "SEC180,security configuration for peripheral 180" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 19. "SEC179,security configuration for peripheral 179" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 18. "SEC178,security configuration for peripheral 178" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 17. "SEC177,security configuration for peripheral 177" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 16. "SEC176,security configuration for peripheral 176" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 15. "SEC175,security configuration for peripheral 175" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 14. "SEC174,security configuration for peripheral 174" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 13. "SEC173,security configuration for peripheral 173" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 12. "SEC172,security configuration for peripheral 172" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 11. "SEC171,security configuration for peripheral 171" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 10. "SEC170,security configuration for peripheral 170" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 9. "SEC169,security configuration for peripheral 169" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 8. "SEC168,security configuration for peripheral 168" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 7. "SEC167,security configuration for peripheral 167" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 6. "SEC166,security configuration for peripheral 166" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 5. "SEC165,security configuration for peripheral 165" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 4. "SEC164,security configuration for peripheral 164" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 3. "SEC163,security configuration for peripheral 163" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 2. "SEC162,security configuration for peripheral 162" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." newline bitfld.long 0x14 1. "SEC161,security configuration for peripheral 161" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." bitfld.long 0x14 0. "SEC160,security configuration for peripheral 160" "0: Secure and non-secure data access are granted to..,1: Secure data access only are granted to the.." group.long 0x30++0x17 line.long 0x0 "RIFSC_RISC_PRIVCFGR0,RIFSC RISFC slave privileged register 0" bitfld.long 0x0 31. "PRIV31,privileged-only access permission for peripheral 31" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 30. "PRIV30,privileged-only access permission for peripheral 30" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 29. "PRIV29,privileged-only access permission for peripheral 29" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 28. "PRIV28,privileged-only access permission for peripheral 28" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 27. "PRIV27,privileged-only access permission for peripheral 27" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 26. "PRIV26,privileged-only access permission for peripheral 26" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 25. "PRIV25,privileged-only access permission for peripheral 25" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 24. "PRIV24,privileged-only access permission for peripheral 24" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 23. "PRIV23,privileged-only access permission for peripheral 23" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 22. "PRIV22,privileged-only access permission for peripheral 22" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 21. "PRIV21,privileged-only access permission for peripheral 21" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 20. "PRIV20,privileged-only access permission for peripheral 20" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 19. "PRIV19,privileged-only access permission for peripheral 19" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 18. "PRIV18,privileged-only access permission for peripheral 18" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 17. "PRIV17,privileged-only access permission for peripheral 17" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 16. "PRIV16,privileged-only access permission for peripheral 16" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 15. "PRIV15,privileged-only access permission for peripheral 15" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 14. "PRIV14,privileged-only access permission for peripheral 14" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 13. "PRIV13,privileged-only access permission for peripheral 13" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 12. "PRIV12,privileged-only access permission for peripheral 12" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 11. "PRIV11,privileged-only access permission for peripheral 11" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 10. "PRIV10,privileged-only access permission for peripheral 10" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 9. "PRIV9,privileged-only access permission for peripheral 9" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 8. "PRIV8,privileged-only access permission for peripheral 8" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 7. "PRIV7,privileged-only access permission for peripheral 7" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 6. "PRIV6,privileged-only access permission for peripheral 6" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 5. "PRIV5,privileged-only access permission for peripheral 5" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 4. "PRIV4,privileged-only access permission for peripheral 4" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 3. "PRIV3,privileged-only access permission for peripheral 3" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 2. "PRIV2,privileged-only access permission for peripheral 2" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x0 1. "PRIV1,privileged-only access permission for peripheral 1" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x0 0. "PRIV0,privileged-only access permission for peripheral 0" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." line.long 0x4 "RIFSC_RISC_PRIVCFGR1,RIFSC RISFC slave privileged register 1" bitfld.long 0x4 31. "PRIV63,privileged-only access permission for peripheral 63" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 30. "PRIV62,privileged-only access permission for peripheral 62" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 29. "PRIV61,privileged-only access permission for peripheral 61" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 28. "PRIV60,privileged-only access permission for peripheral 60" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 27. "PRIV59,privileged-only access permission for peripheral 59" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 26. "PRIV58,privileged-only access permission for peripheral 58" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 25. "PRIV57,privileged-only access permission for peripheral 57" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 24. "PRIV56,privileged-only access permission for peripheral 56" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 23. "PRIV55,privileged-only access permission for peripheral 55" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 22. "PRIV54,privileged-only access permission for peripheral 54" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 21. "PRIV53,privileged-only access permission for peripheral 53" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 20. "PRIV52,privileged-only access permission for peripheral 52" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 19. "PRIV51,privileged-only access permission for peripheral 51" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 18. "PRIV50,privileged-only access permission for peripheral 50" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 17. "PRIV49,privileged-only access permission for peripheral 49" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 16. "PRIV48,privileged-only access permission for peripheral 48" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 15. "PRIV47,privileged-only access permission for peripheral 47" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 14. "PRIV46,privileged-only access permission for peripheral 46" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 13. "PRIV45,privileged-only access permission for peripheral 45" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 12. "PRIV44,privileged-only access permission for peripheral 44" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 11. "PRIV43,privileged-only access permission for peripheral 43" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 10. "PRIV42,privileged-only access permission for peripheral 42" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 9. "PRIV41,privileged-only access permission for peripheral 41" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 8. "PRIV40,privileged-only access permission for peripheral 40" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 7. "PRIV39,privileged-only access permission for peripheral 39" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 6. "PRIV38,privileged-only access permission for peripheral 38" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 5. "PRIV37,privileged-only access permission for peripheral 37" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 4. "PRIV36,privileged-only access permission for peripheral 36" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 3. "PRIV35,privileged-only access permission for peripheral 35" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 2. "PRIV34,privileged-only access permission for peripheral 34" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x4 1. "PRIV33,privileged-only access permission for peripheral 33" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x4 0. "PRIV32,privileged-only access permission for peripheral 32" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." line.long 0x8 "RIFSC_RISC_PRIVCFGR2,RIFSC RISFC slave privileged register 2" bitfld.long 0x8 31. "PRIV95,privileged-only access permission for peripheral 95" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 30. "PRIV94,privileged-only access permission for peripheral 94" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 29. "PRIV93,privileged-only access permission for peripheral 93" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 28. "PRIV92,privileged-only access permission for peripheral 92" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 27. "PRIV91,privileged-only access permission for peripheral 91" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 26. "PRIV90,privileged-only access permission for peripheral 90" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 25. "PRIV89,privileged-only access permission for peripheral 89" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 24. "PRIV88,privileged-only access permission for peripheral 88" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 23. "PRIV87,privileged-only access permission for peripheral 87" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 22. "PRIV86,privileged-only access permission for peripheral 86" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 21. "PRIV85,privileged-only access permission for peripheral 85" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 20. "PRIV84,privileged-only access permission for peripheral 84" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 19. "PRIV83,privileged-only access permission for peripheral 83" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 18. "PRIV82,privileged-only access permission for peripheral 82" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 17. "PRIV81,privileged-only access permission for peripheral 81" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 16. "PRIV80,privileged-only access permission for peripheral 80" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 15. "PRIV79,privileged-only access permission for peripheral 79" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 14. "PRIV78,privileged-only access permission for peripheral 78" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 13. "PRIV77,privileged-only access permission for peripheral 77" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 12. "PRIV76,privileged-only access permission for peripheral 76" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 11. "PRIV75,privileged-only access permission for peripheral 75" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 10. "PRIV74,privileged-only access permission for peripheral 74" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 9. "PRIV73,privileged-only access permission for peripheral 73" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 8. "PRIV72,privileged-only access permission for peripheral 72" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 7. "PRIV71,privileged-only access permission for peripheral 71" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 6. "PRIV70,privileged-only access permission for peripheral 70" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 5. "PRIV69,privileged-only access permission for peripheral 69" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 4. "PRIV68,privileged-only access permission for peripheral 68" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 3. "PRIV67,privileged-only access permission for peripheral 67" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 2. "PRIV66,privileged-only access permission for peripheral 66" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x8 1. "PRIV65,privileged-only access permission for peripheral 65" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x8 0. "PRIV64,privileged-only access permission for peripheral 64" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." line.long 0xC "RIFSC_RISC_PRIVCFGR3,RIFSC RISFC slave privileged register 3" bitfld.long 0xC 31. "PRIV127,privileged-only access permission for peripheral 127" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 30. "PRIV126,privileged-only access permission for peripheral 126" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 29. "PRIV125,privileged-only access permission for peripheral 125" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 28. "PRIV124,privileged-only access permission for peripheral 124" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 27. "PRIV123,privileged-only access permission for peripheral 123" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 26. "PRIV122,privileged-only access permission for peripheral 122" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 25. "PRIV121,privileged-only access permission for peripheral 121" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 24. "PRIV120,privileged-only access permission for peripheral 120" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 23. "PRIV119,privileged-only access permission for peripheral 119" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 22. "PRIV118,privileged-only access permission for peripheral 118" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 21. "PRIV117,privileged-only access permission for peripheral 117" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 20. "PRIV116,privileged-only access permission for peripheral 116" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 19. "PRIV115,privileged-only access permission for peripheral 115" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 18. "PRIV114,privileged-only access permission for peripheral 114" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 17. "PRIV113,privileged-only access permission for peripheral 113" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 16. "PRIV112,privileged-only access permission for peripheral 112" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 15. "PRIV111,privileged-only access permission for peripheral 111" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 14. "PRIV110,privileged-only access permission for peripheral 110" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 13. "PRIV109,privileged-only access permission for peripheral 109" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 12. "PRIV108,privileged-only access permission for peripheral 108" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 11. "PRIV107,privileged-only access permission for peripheral 107" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 10. "PRIV106,privileged-only access permission for peripheral 106" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 9. "PRIV105,privileged-only access permission for peripheral 105" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 8. "PRIV104,privileged-only access permission for peripheral 104" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 7. "PRIV103,privileged-only access permission for peripheral 103" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 6. "PRIV102,privileged-only access permission for peripheral 102" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 5. "PRIV101,privileged-only access permission for peripheral 101" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 4. "PRIV100,privileged-only access permission for peripheral 100" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 3. "PRIV99,privileged-only access permission for peripheral 99" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 2. "PRIV98,privileged-only access permission for peripheral 98" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0xC 1. "PRIV97,privileged-only access permission for peripheral 97" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0xC 0. "PRIV96,privileged-only access permission for peripheral 96" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." line.long 0x10 "RIFSC_RISC_PRIVCFGR4,RIFSC RISFC slave privileged register 4" bitfld.long 0x10 31. "PRIV159,privileged-only access permission for peripheral 159" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 30. "PRIV158,privileged-only access permission for peripheral 158" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 29. "PRIV157,privileged-only access permission for peripheral 157" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 28. "PRIV156,privileged-only access permission for peripheral 156" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 27. "PRIV155,privileged-only access permission for peripheral 155" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 26. "PRIV154,privileged-only access permission for peripheral 154" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 25. "PRIV153,privileged-only access permission for peripheral 153" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 24. "PRIV152,privileged-only access permission for peripheral 152" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 23. "PRIV151,privileged-only access permission for peripheral 151" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 22. "PRIV150,privileged-only access permission for peripheral 150" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 21. "PRIV149,privileged-only access permission for peripheral 149" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 20. "PRIV148,privileged-only access permission for peripheral 148" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 19. "PRIV147,privileged-only access permission for peripheral 147" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 18. "PRIV146,privileged-only access permission for peripheral 146" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 17. "PRIV145,privileged-only access permission for peripheral 145" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 16. "PRIV144,privileged-only access permission for peripheral 144" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 15. "PRIV143,privileged-only access permission for peripheral 143" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 14. "PRIV142,privileged-only access permission for peripheral 142" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 13. "PRIV141,privileged-only access permission for peripheral 141" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 12. "PRIV140,privileged-only access permission for peripheral 140" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 11. "PRIV139,privileged-only access permission for peripheral 139" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 10. "PRIV138,privileged-only access permission for peripheral 138" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 9. "PRIV137,privileged-only access permission for peripheral 137" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 8. "PRIV136,privileged-only access permission for peripheral 136" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 7. "PRIV135,privileged-only access permission for peripheral 135" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 6. "PRIV134,privileged-only access permission for peripheral 134" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 5. "PRIV133,privileged-only access permission for peripheral 133" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 4. "PRIV132,privileged-only access permission for peripheral 132" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 3. "PRIV131,privileged-only access permission for peripheral 131" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 2. "PRIV130,privileged-only access permission for peripheral 130" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x10 1. "PRIV129,privileged-only access permission for peripheral 129" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x10 0. "PRIV128,privileged-only access permission for peripheral 128" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." line.long 0x14 "RIFSC_RISC_PRIVCFGR5,RIFSC RISFC slave privileged register 5" bitfld.long 0x14 31. "PRIV191,privileged-only access permission for peripheral 191" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 30. "PRIV190,privileged-only access permission for peripheral 190" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 29. "PRIV189,privileged-only access permission for peripheral 189" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 28. "PRIV188,privileged-only access permission for peripheral 188" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 27. "PRIV187,privileged-only access permission for peripheral 187" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 26. "PRIV186,privileged-only access permission for peripheral 186" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 25. "PRIV185,privileged-only access permission for peripheral 185" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 24. "PRIV184,privileged-only access permission for peripheral 184" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 23. "PRIV183,privileged-only access permission for peripheral 183" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 22. "PRIV182,privileged-only access permission for peripheral 182" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 21. "PRIV181,privileged-only access permission for peripheral 181" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 20. "PRIV180,privileged-only access permission for peripheral 180" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 19. "PRIV179,privileged-only access permission for peripheral 179" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 18. "PRIV178,privileged-only access permission for peripheral 178" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 17. "PRIV177,privileged-only access permission for peripheral 177" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 16. "PRIV176,privileged-only access permission for peripheral 176" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 15. "PRIV175,privileged-only access permission for peripheral 175" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 14. "PRIV174,privileged-only access permission for peripheral 174" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 13. "PRIV173,privileged-only access permission for peripheral 173" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 12. "PRIV172,privileged-only access permission for peripheral 172" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 11. "PRIV171,privileged-only access permission for peripheral 171" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 10. "PRIV170,privileged-only access permission for peripheral 170" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 9. "PRIV169,privileged-only access permission for peripheral 169" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 8. "PRIV168,privileged-only access permission for peripheral 168" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 7. "PRIV167,privileged-only access permission for peripheral 167" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 6. "PRIV166,privileged-only access permission for peripheral 166" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 5. "PRIV165,privileged-only access permission for peripheral 165" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 4. "PRIV164,privileged-only access permission for peripheral 164" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 3. "PRIV163,privileged-only access permission for peripheral 163" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 2. "PRIV162,privileged-only access permission for peripheral 162" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." newline bitfld.long 0x14 1. "PRIV161,privileged-only access permission for peripheral 161" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." bitfld.long 0x14 0. "PRIV160,privileged-only access permission for peripheral 160" "0: Privileged and unprivileged data access are..,1: Privileged data access only are granted to the.." group.long 0x50++0x17 line.long 0x0 "RIFSC_RISC_RCFGLOCKR0,RIFSC RISC slave resource configuration lock register 0" bitfld.long 0x0 31. "RLOCK31,resource lock for peripheral 31" "0: SEC31 in RIFSC_RISC_SECCFGRx and PRIV31 in..,1: Writes to SEC31 and PRIV31 are ignored." bitfld.long 0x0 30. "RLOCK30,resource lock for peripheral 30" "0: SEC30 in RIFSC_RISC_SECCFGRx and PRIV30 in..,1: Writes to SEC30 and PRIV30 are ignored." newline bitfld.long 0x0 29. "RLOCK29,resource lock for peripheral 29" "0: SEC29 in RIFSC_RISC_SECCFGRx and PRIV29 in..,1: Writes to SEC29 and PRIV29 are ignored." bitfld.long 0x0 28. "RLOCK28,resource lock for peripheral 28" "0: SEC28 in RIFSC_RISC_SECCFGRx and PRIV28 in..,1: Writes to SEC28 and PRIV28 are ignored." newline bitfld.long 0x0 27. "RLOCK27,resource lock for peripheral 27" "0: SEC27 in RIFSC_RISC_SECCFGRx and PRIV27 in..,1: Writes to SEC27 and PRIV27 are ignored." bitfld.long 0x0 26. "RLOCK26,resource lock for peripheral 26" "0: SEC26 in RIFSC_RISC_SECCFGRx and PRIV26 in..,1: Writes to SEC26 and PRIV26 are ignored." newline bitfld.long 0x0 25. "RLOCK25,resource lock for peripheral 25" "0: SEC25 in RIFSC_RISC_SECCFGRx and PRIV25 in..,1: Writes to SEC25 and PRIV25 are ignored." bitfld.long 0x0 24. "RLOCK24,resource lock for peripheral 24" "0: SEC24 in RIFSC_RISC_SECCFGRx and PRIV24 in..,1: Writes to SEC24 and PRIV24 are ignored." newline bitfld.long 0x0 23. "RLOCK23,resource lock for peripheral 23" "0: SEC23 in RIFSC_RISC_SECCFGRx and PRIV23 in..,1: Writes to SEC23 and PRIV23 are ignored." bitfld.long 0x0 22. "RLOCK22,resource lock for peripheral 22" "0: SEC22 in RIFSC_RISC_SECCFGRx and PRIV22 in..,1: Writes to SEC22 and PRIV22 are ignored." newline bitfld.long 0x0 21. "RLOCK21,resource lock for peripheral 21" "0: SEC21 in RIFSC_RISC_SECCFGRx and PRIV21 in..,1: Writes to SEC21 and PRIV21 are ignored." bitfld.long 0x0 20. "RLOCK20,resource lock for peripheral 20" "0: SEC20 in RIFSC_RISC_SECCFGRx and PRIV20 in..,1: Writes to SEC20 and PRIV20 are ignored." newline bitfld.long 0x0 19. "RLOCK19,resource lock for peripheral 19" "0: SEC19 in RIFSC_RISC_SECCFGRx and PRIV19 in..,1: Writes to SEC19 and PRIV19 are ignored." bitfld.long 0x0 18. "RLOCK18,resource lock for peripheral 18" "0: SEC18 in RIFSC_RISC_SECCFGRx and PRIV18 in..,1: Writes to SEC18 and PRIV18 are ignored." newline bitfld.long 0x0 17. "RLOCK17,resource lock for peripheral 17" "0: SEC17 in RIFSC_RISC_SECCFGRx and PRIV17 in..,1: Writes to SEC17 and PRIV17 are ignored." bitfld.long 0x0 16. "RLOCK16,resource lock for peripheral 16" "0: SEC16 in RIFSC_RISC_SECCFGRx and PRIV16 in..,1: Writes to SEC16 and PRIV16 are ignored." newline bitfld.long 0x0 15. "RLOCK15,resource lock for peripheral 15" "0: SEC15 in RIFSC_RISC_SECCFGRx and PRIV15 in..,1: Writes to SEC15 and PRIV15 are ignored." bitfld.long 0x0 14. "RLOCK14,resource lock for peripheral 14" "0: SEC14 in RIFSC_RISC_SECCFGRx and PRIV14 in..,1: Writes to SEC14 and PRIV14 are ignored." newline bitfld.long 0x0 13. "RLOCK13,resource lock for peripheral 13" "0: SEC13 in RIFSC_RISC_SECCFGRx and PRIV13 in..,1: Writes to SEC13 and PRIV13 are ignored." bitfld.long 0x0 12. "RLOCK12,resource lock for peripheral 12" "0: SEC12 in RIFSC_RISC_SECCFGRx and PRIV12 in..,1: Writes to SEC12 and PRIV12 are ignored." newline bitfld.long 0x0 11. "RLOCK11,resource lock for peripheral 11" "0: SEC11 in RIFSC_RISC_SECCFGRx and PRIV11 in..,1: Writes to SEC11 and PRIV11 are ignored." bitfld.long 0x0 10. "RLOCK10,resource lock for peripheral 10" "0: SEC10 in RIFSC_RISC_SECCFGRx and PRIV10 in..,1: Writes to SEC10 and PRIV10 are ignored." newline bitfld.long 0x0 9. "RLOCK9,resource lock for peripheral 9" "0: SEC9 in RIFSC_RISC_SECCFGRx and PRIV9 in..,1: Writes to SEC9 and PRIV9 are ignored." bitfld.long 0x0 8. "RLOCK8,resource lock for peripheral 8" "0: SEC8 in RIFSC_RISC_SECCFGRx and PRIV8 in..,1: Writes to SEC8 and PRIV8 are ignored." newline bitfld.long 0x0 7. "RLOCK7,resource lock for peripheral 7" "0: SEC7 in RIFSC_RISC_SECCFGRx and PRIV7 in..,1: Writes to SEC7 and PRIV7 are ignored." bitfld.long 0x0 6. "RLOCK6,resource lock for peripheral 6" "0: SEC6 in RIFSC_RISC_SECCFGRx and PRIV6 in..,1: Writes to SEC6 and PRIV6 are ignored." newline bitfld.long 0x0 5. "RLOCK5,resource lock for peripheral 5" "0: SEC5 in RIFSC_RISC_SECCFGRx and PRIV5 in..,1: Writes to SEC5 and PRIV5 are ignored." bitfld.long 0x0 4. "RLOCK4,resource lock for peripheral 4" "0: SEC4 in RIFSC_RISC_SECCFGRx and PRIV4 in..,1: Writes to SEC4 and PRIV4 are ignored." newline bitfld.long 0x0 3. "RLOCK3,resource lock for peripheral 3" "0: SEC3 in RIFSC_RISC_SECCFGRx and PRIV3 in..,1: Writes to SEC3 and PRIV3 are ignored." bitfld.long 0x0 2. "RLOCK2,resource lock for peripheral 2" "0: SEC2 in RIFSC_RISC_SECCFGRx and PRIV2 in..,1: Writes to SEC2 and PRIV2 are ignored." newline bitfld.long 0x0 1. "RLOCK1,resource lock for peripheral 1" "0: SEC1 in RIFSC_RISC_SECCFGRx and PRIV1 in..,1: Writes to SEC1 and PRIV1 are ignored." bitfld.long 0x0 0. "RLOCK0,resource lock for peripheral 0" "0: SEC0 in RIFSC_RISC_SECCFGRx and PRIV0 in..,1: Writes to SEC0 and PRIV0 are ignored." line.long 0x4 "RIFSC_RISC_RCFGLOCKR1,RIFSC RISC slave resource configuration lock register 1" bitfld.long 0x4 31. "RLOCK63,resource lock for peripheral 63" "0: SEC63 in RIFSC_RISC_SECCFGRx and PRIV63 in..,1: Writes to SEC63 and PRIV63 are ignored." bitfld.long 0x4 30. "RLOCK62,resource lock for peripheral 62" "0: SEC62 in RIFSC_RISC_SECCFGRx and PRIV62 in..,1: Writes to SEC62 and PRIV62 are ignored." newline bitfld.long 0x4 29. "RLOCK61,resource lock for peripheral 61" "0: SEC61 in RIFSC_RISC_SECCFGRx and PRIV61 in..,1: Writes to SEC61 and PRIV61 are ignored." bitfld.long 0x4 28. "RLOCK60,resource lock for peripheral 60" "0: SEC60 in RIFSC_RISC_SECCFGRx and PRIV60 in..,1: Writes to SEC60 and PRIV60 are ignored." newline bitfld.long 0x4 27. "RLOCK59,resource lock for peripheral 59" "0: SEC59 in RIFSC_RISC_SECCFGRx and PRIV59 in..,1: Writes to SEC59 and PRIV59 are ignored." bitfld.long 0x4 26. "RLOCK58,resource lock for peripheral 58" "0: SEC58 in RIFSC_RISC_SECCFGRx and PRIV58 in..,1: Writes to SEC58 and PRIV58 are ignored." newline bitfld.long 0x4 25. "RLOCK57,resource lock for peripheral 57" "0: SEC57 in RIFSC_RISC_SECCFGRx and PRIV57 in..,1: Writes to SEC57 and PRIV57 are ignored." bitfld.long 0x4 24. "RLOCK56,resource lock for peripheral 56" "0: SEC56 in RIFSC_RISC_SECCFGRx and PRIV56 in..,1: Writes to SEC56 and PRIV56 are ignored." newline bitfld.long 0x4 23. "RLOCK55,resource lock for peripheral 55" "0: SEC55 in RIFSC_RISC_SECCFGRx and PRIV55 in..,1: Writes to SEC55 and PRIV55 are ignored." bitfld.long 0x4 22. "RLOCK54,resource lock for peripheral 54" "0: SEC54 in RIFSC_RISC_SECCFGRx and PRIV54 in..,1: Writes to SEC54 and PRIV54 are ignored." newline bitfld.long 0x4 21. "RLOCK53,resource lock for peripheral 53" "0: SEC53 in RIFSC_RISC_SECCFGRx and PRIV53 in..,1: Writes to SEC53 and PRIV53 are ignored." bitfld.long 0x4 20. "RLOCK52,resource lock for peripheral 52" "0: SEC52 in RIFSC_RISC_SECCFGRx and PRIV52 in..,1: Writes to SEC52 and PRIV52 are ignored." newline bitfld.long 0x4 19. "RLOCK51,resource lock for peripheral 51" "0: SEC51 in RIFSC_RISC_SECCFGRx and PRIV51 in..,1: Writes to SEC51 and PRIV51 are ignored." bitfld.long 0x4 18. "RLOCK50,resource lock for peripheral 50" "0: SEC50 in RIFSC_RISC_SECCFGRx and PRIV50 in..,1: Writes to SEC50 and PRIV50 are ignored." newline bitfld.long 0x4 17. "RLOCK49,resource lock for peripheral 49" "0: SEC49 in RIFSC_RISC_SECCFGRx and PRIV49 in..,1: Writes to SEC49 and PRIV49 are ignored." bitfld.long 0x4 16. "RLOCK48,resource lock for peripheral 48" "0: SEC48 in RIFSC_RISC_SECCFGRx and PRIV48 in..,1: Writes to SEC48 and PRIV48 are ignored." newline bitfld.long 0x4 15. "RLOCK47,resource lock for peripheral 47" "0: SEC47 in RIFSC_RISC_SECCFGRx and PRIV47 in..,1: Writes to SEC47 and PRIV47 are ignored." bitfld.long 0x4 14. "RLOCK46,resource lock for peripheral 46" "0: SEC46 in RIFSC_RISC_SECCFGRx and PRIV46 in..,1: Writes to SEC46 and PRIV46 are ignored." newline bitfld.long 0x4 13. "RLOCK45,resource lock for peripheral 45" "0: SEC45 in RIFSC_RISC_SECCFGRx and PRIV45 in..,1: Writes to SEC45 and PRIV45 are ignored." bitfld.long 0x4 12. "RLOCK44,resource lock for peripheral 44" "0: SEC44 in RIFSC_RISC_SECCFGRx and PRIV44 in..,1: Writes to SEC44 and PRIV44 are ignored." newline bitfld.long 0x4 11. "RLOCK43,resource lock for peripheral 43" "0: SEC43 in RIFSC_RISC_SECCFGRx and PRIV43 in..,1: Writes to SEC43 and PRIV43 are ignored." bitfld.long 0x4 10. "RLOCK42,resource lock for peripheral 42" "0: SEC42 in RIFSC_RISC_SECCFGRx and PRIV42 in..,1: Writes to SEC42 and PRIV42 are ignored." newline bitfld.long 0x4 9. "RLOCK41,resource lock for peripheral 41" "0: SEC41 in RIFSC_RISC_SECCFGRx and PRIV41 in..,1: Writes to SEC41 and PRIV41 are ignored." bitfld.long 0x4 8. "RLOCK40,resource lock for peripheral 40" "0: SEC40 in RIFSC_RISC_SECCFGRx and PRIV40 in..,1: Writes to SEC40 and PRIV40 are ignored." newline bitfld.long 0x4 7. "RLOCK39,resource lock for peripheral 39" "0: SEC39 in RIFSC_RISC_SECCFGRx and PRIV39 in..,1: Writes to SEC39 and PRIV39 are ignored." bitfld.long 0x4 6. "RLOCK38,resource lock for peripheral 38" "0: SEC38 in RIFSC_RISC_SECCFGRx and PRIV38 in..,1: Writes to SEC38 and PRIV38 are ignored." newline bitfld.long 0x4 5. "RLOCK37,resource lock for peripheral 37" "0: SEC37 in RIFSC_RISC_SECCFGRx and PRIV37 in..,1: Writes to SEC37 and PRIV37 are ignored." bitfld.long 0x4 4. "RLOCK36,resource lock for peripheral 36" "0: SEC36 in RIFSC_RISC_SECCFGRx and PRIV36 in..,1: Writes to SEC36 and PRIV36 are ignored." newline bitfld.long 0x4 3. "RLOCK35,resource lock for peripheral 35" "0: SEC35 in RIFSC_RISC_SECCFGRx and PRIV35 in..,1: Writes to SEC35 and PRIV35 are ignored." bitfld.long 0x4 2. "RLOCK34,resource lock for peripheral 34" "0: SEC34 in RIFSC_RISC_SECCFGRx and PRIV34 in..,1: Writes to SEC34 and PRIV34 are ignored." newline bitfld.long 0x4 1. "RLOCK33,resource lock for peripheral 33" "0: SEC33 in RIFSC_RISC_SECCFGRx and PRIV33 in..,1: Writes to SEC33 and PRIV33 are ignored." bitfld.long 0x4 0. "RLOCK32,resource lock for peripheral 32" "0: SEC32 in RIFSC_RISC_SECCFGRx and PRIV32 in..,1: Writes to SEC32 and PRIV32 are ignored." line.long 0x8 "RIFSC_RISC_RCFGLOCKR2,RIFSC RISC slave resource configuration lock register 2" bitfld.long 0x8 31. "RLOCK95,resource lock for peripheral 95" "0: SEC95 in RIFSC_RISC_SECCFGRx and PRIV95 in..,1: Writes to SEC95 and PRIV95 are ignored." bitfld.long 0x8 30. "RLOCK94,resource lock for peripheral 94" "0: SEC94 in RIFSC_RISC_SECCFGRx and PRIV94 in..,1: Writes to SEC94 and PRIV94 are ignored." newline bitfld.long 0x8 29. "RLOCK93,resource lock for peripheral 93" "0: SEC93 in RIFSC_RISC_SECCFGRx and PRIV93 in..,1: Writes to SEC93 and PRIV93 are ignored." bitfld.long 0x8 28. "RLOCK92,resource lock for peripheral 92" "0: SEC92 in RIFSC_RISC_SECCFGRx and PRIV92 in..,1: Writes to SEC92 and PRIV92 are ignored." newline bitfld.long 0x8 27. "RLOCK91,resource lock for peripheral 91" "0: SEC91 in RIFSC_RISC_SECCFGRx and PRIV91 in..,1: Writes to SEC91 and PRIV91 are ignored." bitfld.long 0x8 26. "RLOCK90,resource lock for peripheral 90" "0: SEC90 in RIFSC_RISC_SECCFGRx and PRIV90 in..,1: Writes to SEC90 and PRIV90 are ignored." newline bitfld.long 0x8 25. "RLOCK89,resource lock for peripheral 89" "0: SEC89 in RIFSC_RISC_SECCFGRx and PRIV89 in..,1: Writes to SEC89 and PRIV89 are ignored." bitfld.long 0x8 24. "RLOCK88,resource lock for peripheral 88" "0: SEC88 in RIFSC_RISC_SECCFGRx and PRIV88 in..,1: Writes to SEC88 and PRIV88 are ignored." newline bitfld.long 0x8 23. "RLOCK87,resource lock for peripheral 87" "0: SEC87 in RIFSC_RISC_SECCFGRx and PRIV87 in..,1: Writes to SEC87 and PRIV87 are ignored." bitfld.long 0x8 22. "RLOCK86,resource lock for peripheral 86" "0: SEC86 in RIFSC_RISC_SECCFGRx and PRIV86 in..,1: Writes to SEC86 and PRIV86 are ignored." newline bitfld.long 0x8 21. "RLOCK85,resource lock for peripheral 85" "0: SEC85 in RIFSC_RISC_SECCFGRx and PRIV85 in..,1: Writes to SEC85 and PRIV85 are ignored." bitfld.long 0x8 20. "RLOCK84,resource lock for peripheral 84" "0: SEC84 in RIFSC_RISC_SECCFGRx and PRIV84 in..,1: Writes to SEC84 and PRIV84 are ignored." newline bitfld.long 0x8 19. "RLOCK83,resource lock for peripheral 83" "0: SEC83 in RIFSC_RISC_SECCFGRx and PRIV83 in..,1: Writes to SEC83 and PRIV83 are ignored." bitfld.long 0x8 18. "RLOCK82,resource lock for peripheral 82" "0: SEC82 in RIFSC_RISC_SECCFGRx and PRIV82 in..,1: Writes to SEC82 and PRIV82 are ignored." newline bitfld.long 0x8 17. "RLOCK81,resource lock for peripheral 81" "0: SEC81 in RIFSC_RISC_SECCFGRx and PRIV81 in..,1: Writes to SEC81 and PRIV81 are ignored." bitfld.long 0x8 16. "RLOCK80,resource lock for peripheral 80" "0: SEC80 in RIFSC_RISC_SECCFGRx and PRIV80 in..,1: Writes to SEC80 and PRIV80 are ignored." newline bitfld.long 0x8 15. "RLOCK79,resource lock for peripheral 79" "0: SEC79 in RIFSC_RISC_SECCFGRx and PRIV79 in..,1: Writes to SEC79 and PRIV79 are ignored." bitfld.long 0x8 14. "RLOCK78,resource lock for peripheral 78" "0: SEC78 in RIFSC_RISC_SECCFGRx and PRIV78 in..,1: Writes to SEC78 and PRIV78 are ignored." newline bitfld.long 0x8 13. "RLOCK77,resource lock for peripheral 77" "0: SEC77 in RIFSC_RISC_SECCFGRx and PRIV77 in..,1: Writes to SEC77 and PRIV77 are ignored." bitfld.long 0x8 12. "RLOCK76,resource lock for peripheral 76" "0: SEC76 in RIFSC_RISC_SECCFGRx and PRIV76 in..,1: Writes to SEC76 and PRIV76 are ignored." newline bitfld.long 0x8 11. "RLOCK75,resource lock for peripheral 75" "0: SEC75 in RIFSC_RISC_SECCFGRx and PRIV75 in..,1: Writes to SEC75 and PRIV75 are ignored." bitfld.long 0x8 10. "RLOCK74,resource lock for peripheral 74" "0: SEC74 in RIFSC_RISC_SECCFGRx and PRIV74 in..,1: Writes to SEC74 and PRIV74 are ignored." newline bitfld.long 0x8 9. "RLOCK73,resource lock for peripheral 73" "0: SEC73 in RIFSC_RISC_SECCFGRx and PRIV73 in..,1: Writes to SEC73 and PRIV73 are ignored." bitfld.long 0x8 8. "RLOCK72,resource lock for peripheral 72" "0: SEC72 in RIFSC_RISC_SECCFGRx and PRIV72 in..,1: Writes to SEC72 and PRIV72 are ignored." newline bitfld.long 0x8 7. "RLOCK71,resource lock for peripheral 71" "0: SEC71 in RIFSC_RISC_SECCFGRx and PRIV71 in..,1: Writes to SEC71 and PRIV71 are ignored." bitfld.long 0x8 6. "RLOCK70,resource lock for peripheral 70" "0: SEC70 in RIFSC_RISC_SECCFGRx and PRIV70 in..,1: Writes to SEC70 and PRIV70 are ignored." newline bitfld.long 0x8 5. "RLOCK69,resource lock for peripheral 69" "0: SEC69 in RIFSC_RISC_SECCFGRx and PRIV69 in..,1: Writes to SEC69 and PRIV69 are ignored." bitfld.long 0x8 4. "RLOCK68,resource lock for peripheral 68" "0: SEC68 in RIFSC_RISC_SECCFGRx and PRIV68 in..,1: Writes to SEC68 and PRIV68 are ignored." newline bitfld.long 0x8 3. "RLOCK67,resource lock for peripheral 67" "0: SEC67 in RIFSC_RISC_SECCFGRx and PRIV67 in..,1: Writes to SEC67 and PRIV67 are ignored." bitfld.long 0x8 2. "RLOCK66,resource lock for peripheral 66" "0: SEC66 in RIFSC_RISC_SECCFGRx and PRIV66 in..,1: Writes to SEC66 and PRIV66 are ignored." newline bitfld.long 0x8 1. "RLOCK65,resource lock for peripheral 65" "0: SEC65 in RIFSC_RISC_SECCFGRx and PRIV65 in..,1: Writes to SEC65 and PRIV65 are ignored." bitfld.long 0x8 0. "RLOCK64,resource lock for peripheral 64" "0: SEC64 in RIFSC_RISC_SECCFGRx and PRIV64 in..,1: Writes to SEC64 and PRIV64 are ignored." line.long 0xC "RIFSC_RISC_RCFGLOCKR3,RIFSC RISC slave resource configuration lock register 3" bitfld.long 0xC 31. "RLOCK127,resource lock for peripheral 127" "0: SEC127 in RIFSC_RISC_SECCFGRx and PRIV127 in..,1: Writes to SEC127 and PRIV127 are ignored." bitfld.long 0xC 30. "RLOCK126,resource lock for peripheral 126" "0: SEC126 in RIFSC_RISC_SECCFGRx and PRIV126 in..,1: Writes to SEC126 and PRIV126 are ignored." newline bitfld.long 0xC 29. "RLOCK125,resource lock for peripheral 125" "0: SEC125 in RIFSC_RISC_SECCFGRx and PRIV125 in..,1: Writes to SEC125 and PRIV125 are ignored." bitfld.long 0xC 28. "RLOCK124,resource lock for peripheral 124" "0: SEC124 in RIFSC_RISC_SECCFGRx and PRIV124 in..,1: Writes to SEC124 and PRIV124 are ignored." newline bitfld.long 0xC 27. "RLOCK123,resource lock for peripheral 123" "0: SEC123 in RIFSC_RISC_SECCFGRx and PRIV123 in..,1: Writes to SEC123 and PRIV123 are ignored." bitfld.long 0xC 26. "RLOCK122,resource lock for peripheral 122" "0: SEC122 in RIFSC_RISC_SECCFGRx and PRIV122 in..,1: Writes to SEC122 and PRIV122 are ignored." newline bitfld.long 0xC 25. "RLOCK121,resource lock for peripheral 121" "0: SEC121 in RIFSC_RISC_SECCFGRx and PRIV121 in..,1: Writes to SEC121 and PRIV121 are ignored." bitfld.long 0xC 24. "RLOCK120,resource lock for peripheral 120" "0: SEC120 in RIFSC_RISC_SECCFGRx and PRIV120 in..,1: Writes to SEC120 and PRIV120 are ignored." newline bitfld.long 0xC 23. "RLOCK119,resource lock for peripheral 119" "0: SEC119 in RIFSC_RISC_SECCFGRx and PRIV119 in..,1: Writes to SEC119 and PRIV119 are ignored." bitfld.long 0xC 22. "RLOCK118,resource lock for peripheral 118" "0: SEC118 in RIFSC_RISC_SECCFGRx and PRIV118 in..,1: Writes to SEC118 and PRIV118 are ignored." newline bitfld.long 0xC 21. "RLOCK117,resource lock for peripheral 117" "0: SEC117 in RIFSC_RISC_SECCFGRx and PRIV117 in..,1: Writes to SEC117 and PRIV117 are ignored." bitfld.long 0xC 20. "RLOCK116,resource lock for peripheral 116" "0: SEC116 in RIFSC_RISC_SECCFGRx and PRIV116 in..,1: Writes to SEC116 and PRIV116 are ignored." newline bitfld.long 0xC 19. "RLOCK115,resource lock for peripheral 115" "0: SEC115 in RIFSC_RISC_SECCFGRx and PRIV115 in..,1: Writes to SEC115 and PRIV115 are ignored." bitfld.long 0xC 18. "RLOCK114,resource lock for peripheral 114" "0: SEC114 in RIFSC_RISC_SECCFGRx and PRIV114 in..,1: Writes to SEC114 and PRIV114 are ignored." newline bitfld.long 0xC 17. "RLOCK113,resource lock for peripheral 113" "0: SEC113 in RIFSC_RISC_SECCFGRx and PRIV113 in..,1: Writes to SEC113 and PRIV113 are ignored." bitfld.long 0xC 16. "RLOCK112,resource lock for peripheral 112" "0: SEC112 in RIFSC_RISC_SECCFGRx and PRIV112 in..,1: Writes to SEC112 and PRIV112 are ignored." newline bitfld.long 0xC 15. "RLOCK111,resource lock for peripheral 111" "0: SEC111 in RIFSC_RISC_SECCFGRx and PRIV111 in..,1: Writes to SEC111 and PRIV111 are ignored." bitfld.long 0xC 14. "RLOCK110,resource lock for peripheral 110" "0: SEC110 in RIFSC_RISC_SECCFGRx and PRIV110 in..,1: Writes to SEC110 and PRIV110 are ignored." newline bitfld.long 0xC 13. "RLOCK109,resource lock for peripheral 109" "0: SEC109 in RIFSC_RISC_SECCFGRx and PRIV109 in..,1: Writes to SEC109 and PRIV109 are ignored." bitfld.long 0xC 12. "RLOCK108,resource lock for peripheral 108" "0: SEC108 in RIFSC_RISC_SECCFGRx and PRIV108 in..,1: Writes to SEC108 and PRIV108 are ignored." newline bitfld.long 0xC 11. "RLOCK107,resource lock for peripheral 107" "0: SEC107 in RIFSC_RISC_SECCFGRx and PRIV107 in..,1: Writes to SEC107 and PRIV107 are ignored." bitfld.long 0xC 10. "RLOCK106,resource lock for peripheral 106" "0: SEC106 in RIFSC_RISC_SECCFGRx and PRIV106 in..,1: Writes to SEC106 and PRIV106 are ignored." newline bitfld.long 0xC 9. "RLOCK105,resource lock for peripheral 105" "0: SEC105 in RIFSC_RISC_SECCFGRx and PRIV105 in..,1: Writes to SEC105 and PRIV105 are ignored." bitfld.long 0xC 8. "RLOCK104,resource lock for peripheral 104" "0: SEC104 in RIFSC_RISC_SECCFGRx and PRIV104 in..,1: Writes to SEC104 and PRIV104 are ignored." newline bitfld.long 0xC 7. "RLOCK103,resource lock for peripheral 103" "0: SEC103 in RIFSC_RISC_SECCFGRx and PRIV103 in..,1: Writes to SEC103 and PRIV103 are ignored." bitfld.long 0xC 6. "RLOCK102,resource lock for peripheral 102" "0: SEC102 in RIFSC_RISC_SECCFGRx and PRIV102 in..,1: Writes to SEC102 and PRIV102 are ignored." newline bitfld.long 0xC 5. "RLOCK101,resource lock for peripheral 101" "0: SEC101 in RIFSC_RISC_SECCFGRx and PRIV101 in..,1: Writes to SEC101 and PRIV101 are ignored." bitfld.long 0xC 4. "RLOCK100,resource lock for peripheral 100" "0: SEC100 in RIFSC_RISC_SECCFGRx and PRIV100 in..,1: Writes to SEC100 and PRIV100 are ignored." newline bitfld.long 0xC 3. "RLOCK99,resource lock for peripheral 99" "0: SEC99 in RIFSC_RISC_SECCFGRx and PRIV99 in..,1: Writes to SEC99 and PRIV99 are ignored." bitfld.long 0xC 2. "RLOCK98,resource lock for peripheral 98" "0: SEC98 in RIFSC_RISC_SECCFGRx and PRIV98 in..,1: Writes to SEC98 and PRIV98 are ignored." newline bitfld.long 0xC 1. "RLOCK97,resource lock for peripheral 97" "0: SEC97 in RIFSC_RISC_SECCFGRx and PRIV97 in..,1: Writes to SEC97 and PRIV97 are ignored." bitfld.long 0xC 0. "RLOCK96,resource lock for peripheral 96" "0: SEC96 in RIFSC_RISC_SECCFGRx and PRIV96 in..,1: Writes to SEC96 and PRIV96 are ignored." line.long 0x10 "RIFSC_RISC_RCFGLOCKR4,RIFSC RISC slave resource configuration lock register 4" bitfld.long 0x10 31. "RLOCK159,resource lock for peripheral 159" "0: SEC159 in RIFSC_RISC_SECCFGRx and PRIV159 in..,1: Writes to SEC159 and PRIV159 are ignored." bitfld.long 0x10 30. "RLOCK158,resource lock for peripheral 158" "0: SEC158 in RIFSC_RISC_SECCFGRx and PRIV158 in..,1: Writes to SEC158 and PRIV158 are ignored." newline bitfld.long 0x10 29. "RLOCK157,resource lock for peripheral 157" "0: SEC157 in RIFSC_RISC_SECCFGRx and PRIV157 in..,1: Writes to SEC157 and PRIV157 are ignored." bitfld.long 0x10 28. "RLOCK156,resource lock for peripheral 156" "0: SEC156 in RIFSC_RISC_SECCFGRx and PRIV156 in..,1: Writes to SEC156 and PRIV156 are ignored." newline bitfld.long 0x10 27. "RLOCK155,resource lock for peripheral 155" "0: SEC155 in RIFSC_RISC_SECCFGRx and PRIV155 in..,1: Writes to SEC155 and PRIV155 are ignored." bitfld.long 0x10 26. "RLOCK154,resource lock for peripheral 154" "0: SEC154 in RIFSC_RISC_SECCFGRx and PRIV154 in..,1: Writes to SEC154 and PRIV154 are ignored." newline bitfld.long 0x10 25. "RLOCK153,resource lock for peripheral 153" "0: SEC153 in RIFSC_RISC_SECCFGRx and PRIV153 in..,1: Writes to SEC153 and PRIV153 are ignored." bitfld.long 0x10 24. "RLOCK152,resource lock for peripheral 152" "0: SEC152 in RIFSC_RISC_SECCFGRx and PRIV152 in..,1: Writes to SEC152 and PRIV152 are ignored." newline bitfld.long 0x10 23. "RLOCK151,resource lock for peripheral 151" "0: SEC151 in RIFSC_RISC_SECCFGRx and PRIV151 in..,1: Writes to SEC151 and PRIV151 are ignored." bitfld.long 0x10 22. "RLOCK150,resource lock for peripheral 150" "0: SEC150 in RIFSC_RISC_SECCFGRx and PRIV150 in..,1: Writes to SEC150 and PRIV150 are ignored." newline bitfld.long 0x10 21. "RLOCK149,resource lock for peripheral 149" "0: SEC149 in RIFSC_RISC_SECCFGRx and PRIV149 in..,1: Writes to SEC149 and PRIV149 are ignored." bitfld.long 0x10 20. "RLOCK148,resource lock for peripheral 148" "0: SEC148 in RIFSC_RISC_SECCFGRx and PRIV148 in..,1: Writes to SEC148 and PRIV148 are ignored." newline bitfld.long 0x10 19. "RLOCK147,resource lock for peripheral 147" "0: SEC147 in RIFSC_RISC_SECCFGRx and PRIV147 in..,1: Writes to SEC147 and PRIV147 are ignored." bitfld.long 0x10 18. "RLOCK146,resource lock for peripheral 146" "0: SEC146 in RIFSC_RISC_SECCFGRx and PRIV146 in..,1: Writes to SEC146 and PRIV146 are ignored." newline bitfld.long 0x10 17. "RLOCK145,resource lock for peripheral 145" "0: SEC145 in RIFSC_RISC_SECCFGRx and PRIV145 in..,1: Writes to SEC145 and PRIV145 are ignored." bitfld.long 0x10 16. "RLOCK144,resource lock for peripheral 144" "0: SEC144 in RIFSC_RISC_SECCFGRx and PRIV144 in..,1: Writes to SEC144 and PRIV144 are ignored." newline bitfld.long 0x10 15. "RLOCK143,resource lock for peripheral 143" "0: SEC143 in RIFSC_RISC_SECCFGRx and PRIV143 in..,1: Writes to SEC143 and PRIV143 are ignored." bitfld.long 0x10 14. "RLOCK142,resource lock for peripheral 142" "0: SEC142 in RIFSC_RISC_SECCFGRx and PRIV142 in..,1: Writes to SEC142 and PRIV142 are ignored." newline bitfld.long 0x10 13. "RLOCK141,resource lock for peripheral 141" "0: SEC141 in RIFSC_RISC_SECCFGRx and PRIV141 in..,1: Writes to SEC141 and PRIV141 are ignored." bitfld.long 0x10 12. "RLOCK140,resource lock for peripheral 140" "0: SEC140 in RIFSC_RISC_SECCFGRx and PRIV140 in..,1: Writes to SEC140 and PRIV140 are ignored." newline bitfld.long 0x10 11. "RLOCK139,resource lock for peripheral 139" "0: SEC139 in RIFSC_RISC_SECCFGRx and PRIV139 in..,1: Writes to SEC139 and PRIV139 are ignored." bitfld.long 0x10 10. "RLOCK138,resource lock for peripheral 138" "0: SEC138 in RIFSC_RISC_SECCFGRx and PRIV138 in..,1: Writes to SEC138 and PRIV138 are ignored." newline bitfld.long 0x10 9. "RLOCK137,resource lock for peripheral 137" "0: SEC137 in RIFSC_RISC_SECCFGRx and PRIV137 in..,1: Writes to SEC137 and PRIV137 are ignored." bitfld.long 0x10 8. "RLOCK136,resource lock for peripheral 136" "0: SEC136 in RIFSC_RISC_SECCFGRx and PRIV136 in..,1: Writes to SEC136 and PRIV136 are ignored." newline bitfld.long 0x10 7. "RLOCK135,resource lock for peripheral 135" "0: SEC135 in RIFSC_RISC_SECCFGRx and PRIV135 in..,1: Writes to SEC135 and PRIV135 are ignored." bitfld.long 0x10 6. "RLOCK134,resource lock for peripheral 134" "0: SEC134 in RIFSC_RISC_SECCFGRx and PRIV134 in..,1: Writes to SEC134 and PRIV134 are ignored." newline bitfld.long 0x10 5. "RLOCK133,resource lock for peripheral 133" "0: SEC133 in RIFSC_RISC_SECCFGRx and PRIV133 in..,1: Writes to SEC133 and PRIV133 are ignored." bitfld.long 0x10 4. "RLOCK132,resource lock for peripheral 132" "0: SEC132 in RIFSC_RISC_SECCFGRx and PRIV132 in..,1: Writes to SEC132 and PRIV132 are ignored." newline bitfld.long 0x10 3. "RLOCK131,resource lock for peripheral 131" "0: SEC131 in RIFSC_RISC_SECCFGRx and PRIV131 in..,1: Writes to SEC131 and PRIV131 are ignored." bitfld.long 0x10 2. "RLOCK130,resource lock for peripheral 130" "0: SEC130 in RIFSC_RISC_SECCFGRx and PRIV130 in..,1: Writes to SEC130 and PRIV130 are ignored." newline bitfld.long 0x10 1. "RLOCK129,resource lock for peripheral 129" "0: SEC129 in RIFSC_RISC_SECCFGRx and PRIV129 in..,1: Writes to SEC129 and PRIV129 are ignored." bitfld.long 0x10 0. "RLOCK128,resource lock for peripheral 128" "0: SEC128 in RIFSC_RISC_SECCFGRx and PRIV128 in..,1: Writes to SEC128 and PRIV128 are ignored." line.long 0x14 "RIFSC_RISC_RCFGLOCKR5,RIFSC RISC slave resource configuration lock register 5" bitfld.long 0x14 31. "RLOCK191,resource lock for peripheral 191" "0: SEC191 in RIFSC_RISC_SECCFGRx and PRIV191 in..,1: Writes to SEC191 and PRIV191 are ignored." bitfld.long 0x14 30. "RLOCK190,resource lock for peripheral 190" "0: SEC190 in RIFSC_RISC_SECCFGRx and PRIV190 in..,1: Writes to SEC190 and PRIV190 are ignored." newline bitfld.long 0x14 29. "RLOCK189,resource lock for peripheral 189" "0: SEC189 in RIFSC_RISC_SECCFGRx and PRIV189 in..,1: Writes to SEC189 and PRIV189 are ignored." bitfld.long 0x14 28. "RLOCK188,resource lock for peripheral 188" "0: SEC188 in RIFSC_RISC_SECCFGRx and PRIV188 in..,1: Writes to SEC188 and PRIV188 are ignored." newline bitfld.long 0x14 27. "RLOCK187,resource lock for peripheral 187" "0: SEC187 in RIFSC_RISC_SECCFGRx and PRIV187 in..,1: Writes to SEC187 and PRIV187 are ignored." bitfld.long 0x14 26. "RLOCK186,resource lock for peripheral 186" "0: SEC186 in RIFSC_RISC_SECCFGRx and PRIV186 in..,1: Writes to SEC186 and PRIV186 are ignored." newline bitfld.long 0x14 25. "RLOCK185,resource lock for peripheral 185" "0: SEC185 in RIFSC_RISC_SECCFGRx and PRIV185 in..,1: Writes to SEC185 and PRIV185 are ignored." bitfld.long 0x14 24. "RLOCK184,resource lock for peripheral 184" "0: SEC184 in RIFSC_RISC_SECCFGRx and PRIV184 in..,1: Writes to SEC184 and PRIV184 are ignored." newline bitfld.long 0x14 23. "RLOCK183,resource lock for peripheral 183" "0: SEC183 in RIFSC_RISC_SECCFGRx and PRIV183 in..,1: Writes to SEC183 and PRIV183 are ignored." bitfld.long 0x14 22. "RLOCK182,resource lock for peripheral 182" "0: SEC182 in RIFSC_RISC_SECCFGRx and PRIV182 in..,1: Writes to SEC182 and PRIV182 are ignored." newline bitfld.long 0x14 21. "RLOCK181,resource lock for peripheral 181" "0: SEC181 in RIFSC_RISC_SECCFGRx and PRIV181 in..,1: Writes to SEC181 and PRIV181 are ignored." bitfld.long 0x14 20. "RLOCK180,resource lock for peripheral 180" "0: SEC180 in RIFSC_RISC_SECCFGRx and PRIV180 in..,1: Writes to SEC180 and PRIV180 are ignored." newline bitfld.long 0x14 19. "RLOCK179,resource lock for peripheral 179" "0: SEC179 in RIFSC_RISC_SECCFGRx and PRIV179 in..,1: Writes to SEC179 and PRIV179 are ignored." bitfld.long 0x14 18. "RLOCK178,resource lock for peripheral 178" "0: SEC178 in RIFSC_RISC_SECCFGRx and PRIV178 in..,1: Writes to SEC178 and PRIV178 are ignored." newline bitfld.long 0x14 17. "RLOCK177,resource lock for peripheral 177" "0: SEC177 in RIFSC_RISC_SECCFGRx and PRIV177 in..,1: Writes to SEC177 and PRIV177 are ignored." bitfld.long 0x14 16. "RLOCK176,resource lock for peripheral 176" "0: SEC176 in RIFSC_RISC_SECCFGRx and PRIV176 in..,1: Writes to SEC176 and PRIV176 are ignored." newline bitfld.long 0x14 15. "RLOCK175,resource lock for peripheral 175" "0: SEC175 in RIFSC_RISC_SECCFGRx and PRIV175 in..,1: Writes to SEC175 and PRIV175 are ignored." bitfld.long 0x14 14. "RLOCK174,resource lock for peripheral 174" "0: SEC174 in RIFSC_RISC_SECCFGRx and PRIV174 in..,1: Writes to SEC174 and PRIV174 are ignored." newline bitfld.long 0x14 13. "RLOCK173,resource lock for peripheral 173" "0: SEC173 in RIFSC_RISC_SECCFGRx and PRIV173 in..,1: Writes to SEC173 and PRIV173 are ignored." bitfld.long 0x14 12. "RLOCK172,resource lock for peripheral 172" "0: SEC172 in RIFSC_RISC_SECCFGRx and PRIV172 in..,1: Writes to SEC172 and PRIV172 are ignored." newline bitfld.long 0x14 11. "RLOCK171,resource lock for peripheral 171" "0: SEC171 in RIFSC_RISC_SECCFGRx and PRIV171 in..,1: Writes to SEC171 and PRIV171 are ignored." bitfld.long 0x14 10. "RLOCK170,resource lock for peripheral 170" "0: SEC170 in RIFSC_RISC_SECCFGRx and PRIV170 in..,1: Writes to SEC170 and PRIV170 are ignored." newline bitfld.long 0x14 9. "RLOCK169,resource lock for peripheral 169" "0: SEC169 in RIFSC_RISC_SECCFGRx and PRIV169 in..,1: Writes to SEC169 and PRIV169 are ignored." bitfld.long 0x14 8. "RLOCK168,resource lock for peripheral 168" "0: SEC168 in RIFSC_RISC_SECCFGRx and PRIV168 in..,1: Writes to SEC168 and PRIV168 are ignored." newline bitfld.long 0x14 7. "RLOCK167,resource lock for peripheral 167" "0: SEC167 in RIFSC_RISC_SECCFGRx and PRIV167 in..,1: Writes to SEC167 and PRIV167 are ignored." bitfld.long 0x14 6. "RLOCK166,resource lock for peripheral 166" "0: SEC166 in RIFSC_RISC_SECCFGRx and PRIV166 in..,1: Writes to SEC166 and PRIV166 are ignored." newline bitfld.long 0x14 5. "RLOCK165,resource lock for peripheral 165" "0: SEC165 in RIFSC_RISC_SECCFGRx and PRIV165 in..,1: Writes to SEC165 and PRIV165 are ignored." bitfld.long 0x14 4. "RLOCK164,resource lock for peripheral 164" "0: SEC164 in RIFSC_RISC_SECCFGRx and PRIV164 in..,1: Writes to SEC164 and PRIV164 are ignored." newline bitfld.long 0x14 3. "RLOCK163,resource lock for peripheral 163" "0: SEC163 in RIFSC_RISC_SECCFGRx and PRIV163 in..,1: Writes to SEC163 and PRIV163 are ignored." bitfld.long 0x14 2. "RLOCK162,resource lock for peripheral 162" "0: SEC162 in RIFSC_RISC_SECCFGRx and PRIV162 in..,1: Writes to SEC162 and PRIV162 are ignored." newline bitfld.long 0x14 1. "RLOCK161,resource lock for peripheral 161" "0: SEC161 in RIFSC_RISC_SECCFGRx and PRIV161 in..,1: Writes to SEC161 and PRIV161 are ignored." bitfld.long 0x14 0. "RLOCK160,resource lock for peripheral 160" "0: SEC160 in RIFSC_RISC_SECCFGRx and PRIV160 in..,1: Writes to SEC160 and PRIV160 are ignored." group.long 0xC00++0x3 line.long 0x0 "RIFSC_RIMC_CR,RIFSC RIMC master configuration register" bitfld.long 0x0 8.--10. "DAPCID,debug access port compartment ID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "GLOCK,global lock" "0: RIFSC RIMC registers are writable.,1: All writes to RIFSC RIMC registers are ignored." group.long 0xC10++0x2F line.long 0x0 "RIFSC_RIMC_ATTR0,RIFSC RIMC master attribute register 0" bitfld.long 0x0 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x0 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x0 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x4 "RIFSC_RIMC_ATTR1,RIFSC RIMC master attribute register 1" bitfld.long 0x4 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x4 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x4 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x8 "RIFSC_RIMC_ATTR2,RIFSC RIMC master attribute register 2" bitfld.long 0x8 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x8 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x8 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0xC "RIFSC_RIMC_ATTR3,RIFSC RIMC master attribute register 3" bitfld.long 0xC 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0xC 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0xC 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x10 "RIFSC_RIMC_ATTR4,RIFSC RIMC master attribute register 4" bitfld.long 0x10 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x10 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x10 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x14 "RIFSC_RIMC_ATTR5,RIFSC RIMC master attribute register 5" bitfld.long 0x14 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x14 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x14 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x18 "RIFSC_RIMC_ATTR6,RIFSC RIMC master attribute register 6" bitfld.long 0x18 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x18 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x18 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x1C "RIFSC_RIMC_ATTR7,RIFSC RIMC master attribute register 7" bitfld.long 0x1C 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x1C 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x1C 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x20 "RIFSC_RIMC_ATTR8,RIFSC RIMC master attribute register 8" bitfld.long 0x20 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x20 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x20 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x24 "RIFSC_RIMC_ATTR9,RIFSC RIMC master attribute register 9" bitfld.long 0x24 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x24 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x24 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x28 "RIFSC_RIMC_ATTR10,RIFSC RIMC master attribute register 10" bitfld.long 0x28 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x28 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x28 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" line.long 0x2C "RIFSC_RIMC_ATTR11,RIFSC RIMC master attribute register 11" bitfld.long 0x2C 9. "MPRIV,master privileged" "0: This master is unprivileged.,1: This master is privileged." bitfld.long 0x2C 8. "MSEC,master secure" "0: This master is non-secure.,1: This master is secure." newline bitfld.long 0x2C 4.--6. "MCID,master CID" "0,1,2,3,4,5,6,7" rgroup.long 0xFB0++0x17 line.long 0x0 "RIFSC_PPSR0,RIFSC peripheral protection status register 0" bitfld.long 0x0 31. "PPEN31,peripheral protection enable 31" "0: SEC31 PRIV31 and RLOCK31 register bit not present.,1: SEC31 PRIV31 and RLOCK31 register bit present." bitfld.long 0x0 30. "PPEN30,peripheral protection enable 30" "0: SEC30 PRIV30 and RLOCK30 register bit not present.,1: SEC30 PRIV30 and RLOCK30 register bit present." newline bitfld.long 0x0 29. "PPEN29,peripheral protection enable 29" "0: SEC29 PRIV29 and RLOCK29 register bit not present.,1: SEC29 PRIV29 and RLOCK29 register bit present." bitfld.long 0x0 28. "PPEN28,peripheral protection enable 28" "0: SEC28 PRIV28 and RLOCK28 register bit not present.,1: SEC28 PRIV28 and RLOCK28 register bit present." newline bitfld.long 0x0 27. "PPEN27,peripheral protection enable 27" "0: SEC27 PRIV27 and RLOCK27 register bit not present.,1: SEC27 PRIV27 and RLOCK27 register bit present." bitfld.long 0x0 26. "PPEN26,peripheral protection enable 26" "0: SEC26 PRIV26 and RLOCK26 register bit not present.,1: SEC26 PRIV26 and RLOCK26 register bit present." newline bitfld.long 0x0 25. "PPEN25,peripheral protection enable 25" "0: SEC25 PRIV25 and RLOCK25 register bit not present.,1: SEC25 PRIV25 and RLOCK25 register bit present." bitfld.long 0x0 24. "PPEN24,peripheral protection enable 24" "0: SEC24 PRIV24 and RLOCK24 register bit not present.,1: SEC24 PRIV24 and RLOCK24 register bit present." newline bitfld.long 0x0 23. "PPEN23,peripheral protection enable 23" "0: SEC23 PRIV23 and RLOCK23 register bit not present.,1: SEC23 PRIV23 and RLOCK23 register bit present." bitfld.long 0x0 22. "PPEN22,peripheral protection enable 22" "0: SEC22 PRIV22 and RLOCK22 register bit not present.,1: SEC22 PRIV22 and RLOCK22 register bit present." newline bitfld.long 0x0 21. "PPEN21,peripheral protection enable 21" "0: SEC21 PRIV21 and RLOCK21 register bit not present.,1: SEC21 PRIV21 and RLOCK21 register bit present." bitfld.long 0x0 20. "PPEN20,peripheral protection enable 20" "0: SEC20 PRIV20 and RLOCK20 register bit not present.,1: SEC20 PRIV20 and RLOCK20 register bit present." newline bitfld.long 0x0 19. "PPEN19,peripheral protection enable 19" "0: SEC19 PRIV19 and RLOCK19 register bit not present.,1: SEC19 PRIV19 and RLOCK19 register bit present." bitfld.long 0x0 18. "PPEN18,peripheral protection enable 18" "0: SEC18 PRIV18 and RLOCK18 register bit not present.,1: SEC18 PRIV18 and RLOCK18 register bit present." newline bitfld.long 0x0 17. "PPEN17,peripheral protection enable 17" "0: SEC17 PRIV17 and RLOCK17 register bit not present.,1: SEC17 PRIV17 and RLOCK17 register bit present." bitfld.long 0x0 16. "PPEN16,peripheral protection enable 16" "0: SEC16 PRIV16 and RLOCK16 register bit not present.,1: SEC16 PRIV16 and RLOCK16 register bit present." newline bitfld.long 0x0 15. "PPEN15,peripheral protection enable 15" "0: SEC15 PRIV15 and RLOCK15 register bit not present.,1: SEC15 PRIV15 and RLOCK15 register bit present." bitfld.long 0x0 14. "PPEN14,peripheral protection enable 14" "0: SEC14 PRIV14 and RLOCK14 register bit not present.,1: SEC14 PRIV14 and RLOCK14 register bit present." newline bitfld.long 0x0 13. "PPEN13,peripheral protection enable 13" "0: SEC13 PRIV13 and RLOCK13 register bit not present.,1: SEC13 PRIV13 and RLOCK13 register bit present." bitfld.long 0x0 12. "PPEN12,peripheral protection enable 12" "0: SEC12 PRIV12 and RLOCK12 register bit not present.,1: SEC12 PRIV12 and RLOCK12 register bit present." newline bitfld.long 0x0 11. "PPEN11,peripheral protection enable 11" "0: SEC11 PRIV11 and RLOCK11 register bit not present.,1: SEC11 PRIV11 and RLOCK11 register bit present." bitfld.long 0x0 10. "PPEN10,peripheral protection enable 10" "0: SEC10 PRIV10 and RLOCK10 register bit not present.,1: SEC10 PRIV10 and RLOCK10 register bit present." newline bitfld.long 0x0 9. "PPEN9,peripheral protection enable 9" "0: SEC9 PRIV9 and RLOCK9 register bit not present.,1: SEC9 PRIV9 and RLOCK9 register bit present." bitfld.long 0x0 8. "PPEN8,peripheral protection enable 8" "0: SEC8 PRIV8 and RLOCK8 register bit not present.,1: SEC8 PRIV8 and RLOCK8 register bit present." newline bitfld.long 0x0 7. "PPEN7,peripheral protection enable 7" "0: SEC7 PRIV7 and RLOCK7 register bit not present.,1: SEC7 PRIV7 and RLOCK7 register bit present." bitfld.long 0x0 6. "PPEN6,peripheral protection enable 6" "0: SEC6 PRIV6 and RLOCK6 register bit not present.,1: SEC6 PRIV6 and RLOCK6 register bit present." newline bitfld.long 0x0 5. "PPEN5,peripheral protection enable 5" "0: SEC5 PRIV5 and RLOCK5 register bit not present.,1: SEC5 PRIV5 and RLOCK5 register bit present." bitfld.long 0x0 4. "PPEN4,peripheral protection enable 4" "0: SEC4 PRIV4 and RLOCK4 register bit not present.,1: SEC4 PRIV4 and RLOCK4 register bit present." newline bitfld.long 0x0 3. "PPEN3,peripheral protection enable 3" "0: SEC3 PRIV3 and RLOCK3 register bit not present.,1: SEC3 PRIV3 and RLOCK3 register bit present." bitfld.long 0x0 2. "PPEN2,peripheral protection enable 2" "0: SEC2 PRIV2 and RLOCK2 register bit not present.,1: SEC2 PRIV2 and RLOCK2 register bit present." newline bitfld.long 0x0 1. "PPEN1,peripheral protection enable 1" "0: SEC1 PRIV1 and RLOCK1 register bit not present.,1: SEC1 PRIV1 and RLOCK1 register bit present." bitfld.long 0x0 0. "PPEN0,peripheral protection enable 0" "0: SEC0 PRIV0 and RLOCK0 register bit not present.,1: SEC0 PRIV0 and RLOCK0 register bit present." line.long 0x4 "RIFSC_PPSR1,RIFSC peripheral protection status register 1" bitfld.long 0x4 31. "PPEN63,peripheral protection enable 63" "0: SEC63 PRIV63 and RLOCK63 register bit not present.,1: SEC63 PRIV63 and RLOCK63 register bit present." bitfld.long 0x4 30. "PPEN62,peripheral protection enable 62" "0: SEC62 PRIV62 and RLOCK62 register bit not present.,1: SEC62 PRIV62 and RLOCK62 register bit present." newline bitfld.long 0x4 29. "PPEN61,peripheral protection enable 61" "0: SEC61 PRIV61 and RLOCK61 register bit not present.,1: SEC61 PRIV61 and RLOCK61 register bit present." bitfld.long 0x4 28. "PPEN60,peripheral protection enable 60" "0: SEC60 PRIV60 and RLOCK60 register bit not present.,1: SEC60 PRIV60 and RLOCK60 register bit present." newline bitfld.long 0x4 27. "PPEN59,peripheral protection enable 59" "0: SEC59 PRIV59 and RLOCK59 register bit not present.,1: SEC59 PRIV59 and RLOCK59 register bit present." bitfld.long 0x4 26. "PPEN58,peripheral protection enable 58" "0: SEC58 PRIV58 and RLOCK58 register bit not present.,1: SEC58 PRIV58 and RLOCK58 register bit present." newline bitfld.long 0x4 25. "PPEN57,peripheral protection enable 57" "0: SEC57 PRIV57 and RLOCK57 register bit not present.,1: SEC57 PRIV57 and RLOCK57 register bit present." bitfld.long 0x4 24. "PPEN56,peripheral protection enable 56" "0: SEC56 PRIV56 and RLOCK56 register bit not present.,1: SEC56 PRIV56 and RLOCK56 register bit present." newline bitfld.long 0x4 23. "PPEN55,peripheral protection enable 55" "0: SEC55 PRIV55 and RLOCK55 register bit not present.,1: SEC55 PRIV55 and RLOCK55 register bit present." bitfld.long 0x4 22. "PPEN54,peripheral protection enable 54" "0: SEC54 PRIV54 and RLOCK54 register bit not present.,1: SEC54 PRIV54 and RLOCK54 register bit present." newline bitfld.long 0x4 21. "PPEN53,peripheral protection enable 53" "0: SEC53 PRIV53 and RLOCK53 register bit not present.,1: SEC53 PRIV53 and RLOCK53 register bit present." bitfld.long 0x4 20. "PPEN52,peripheral protection enable 52" "0: SEC52 PRIV52 and RLOCK52 register bit not present.,1: SEC52 PRIV52 and RLOCK52 register bit present." newline bitfld.long 0x4 19. "PPEN51,peripheral protection enable 51" "0: SEC51 PRIV51 and RLOCK51 register bit not present.,1: SEC51 PRIV51 and RLOCK51 register bit present." bitfld.long 0x4 18. "PPEN50,peripheral protection enable 50" "0: SEC50 PRIV50 and RLOCK50 register bit not present.,1: SEC50 PRIV50 and RLOCK50 register bit present." newline bitfld.long 0x4 17. "PPEN49,peripheral protection enable 49" "0: SEC49 PRIV49 and RLOCK49 register bit not present.,1: SEC49 PRIV49 and RLOCK49 register bit present." bitfld.long 0x4 16. "PPEN48,peripheral protection enable 48" "0: SEC48 PRIV48 and RLOCK48 register bit not present.,1: SEC48 PRIV48 and RLOCK48 register bit present." newline bitfld.long 0x4 15. "PPEN47,peripheral protection enable 47" "0: SEC47 PRIV47 and RLOCK47 register bit not present.,1: SEC47 PRIV47 and RLOCK47 register bit present." bitfld.long 0x4 14. "PPEN46,peripheral protection enable 46" "0: SEC46 PRIV46 and RLOCK46 register bit not present.,1: SEC46 PRIV46 and RLOCK46 register bit present." newline bitfld.long 0x4 13. "PPEN45,peripheral protection enable 45" "0: SEC45 PRIV45 and RLOCK45 register bit not present.,1: SEC45 PRIV45 and RLOCK45 register bit present." bitfld.long 0x4 12. "PPEN44,peripheral protection enable 44" "0: SEC44 PRIV44 and RLOCK44 register bit not present.,1: SEC44 PRIV44 and RLOCK44 register bit present." newline bitfld.long 0x4 11. "PPEN43,peripheral protection enable 43" "0: SEC43 PRIV43 and RLOCK43 register bit not present.,1: SEC43 PRIV43 and RLOCK43 register bit present." bitfld.long 0x4 10. "PPEN42,peripheral protection enable 42" "0: SEC42 PRIV42 and RLOCK42 register bit not present.,1: SEC42 PRIV42 and RLOCK42 register bit present." newline bitfld.long 0x4 9. "PPEN41,peripheral protection enable 41" "0: SEC41 PRIV41 and RLOCK41 register bit not present.,1: SEC41 PRIV41 and RLOCK41 register bit present." bitfld.long 0x4 8. "PPEN40,peripheral protection enable 40" "0: SEC40 PRIV40 and RLOCK40 register bit not present.,1: SEC40 PRIV40 and RLOCK40 register bit present." newline bitfld.long 0x4 7. "PPEN39,peripheral protection enable 39" "0: SEC39 PRIV39 and RLOCK39 register bit not present.,1: SEC39 PRIV39 and RLOCK39 register bit present." bitfld.long 0x4 6. "PPEN38,peripheral protection enable 38" "0: SEC38 PRIV38 and RLOCK38 register bit not present.,1: SEC38 PRIV38 and RLOCK38 register bit present." newline bitfld.long 0x4 5. "PPEN37,peripheral protection enable 37" "0: SEC37 PRIV37 and RLOCK37 register bit not present.,1: SEC37 PRIV37 and RLOCK37 register bit present." bitfld.long 0x4 4. "PPEN36,peripheral protection enable 36" "0: SEC36 PRIV36 and RLOCK36 register bit not present.,1: SEC36 PRIV36 and RLOCK36 register bit present." newline bitfld.long 0x4 3. "PPEN35,peripheral protection enable 35" "0: SEC35 PRIV35 and RLOCK35 register bit not present.,1: SEC35 PRIV35 and RLOCK35 register bit present." bitfld.long 0x4 2. "PPEN34,peripheral protection enable 34" "0: SEC34 PRIV34 and RLOCK34 register bit not present.,1: SEC34 PRIV34 and RLOCK34 register bit present." newline bitfld.long 0x4 1. "PPEN33,peripheral protection enable 33" "0: SEC33 PRIV33 and RLOCK33 register bit not present.,1: SEC33 PRIV33 and RLOCK33 register bit present." bitfld.long 0x4 0. "PPEN32,peripheral protection enable 32" "0: SEC32 PRIV32 and RLOCK32 register bit not present.,1: SEC32 PRIV32 and RLOCK32 register bit present." line.long 0x8 "RIFSC_PPSR2,RIFSC peripheral protection status register 2" bitfld.long 0x8 31. "PPEN95,peripheral protection enable 95" "0: SEC95 PRIV95 and RLOCK95 register bit not present.,1: SEC95 PRIV95 and RLOCK95 register bit present." bitfld.long 0x8 30. "PPEN94,peripheral protection enable 94" "0: SEC94 PRIV94 and RLOCK94 register bit not present.,1: SEC94 PRIV94 and RLOCK94 register bit present." newline bitfld.long 0x8 29. "PPEN93,peripheral protection enable 93" "0: SEC93 PRIV93 and RLOCK93 register bit not present.,1: SEC93 PRIV93 and RLOCK93 register bit present." bitfld.long 0x8 28. "PPEN92,peripheral protection enable 92" "0: SEC92 PRIV92 and RLOCK92 register bit not present.,1: SEC92 PRIV92 and RLOCK92 register bit present." newline bitfld.long 0x8 27. "PPEN91,peripheral protection enable 91" "0: SEC91 PRIV91 and RLOCK91 register bit not present.,1: SEC91 PRIV91 and RLOCK91 register bit present." bitfld.long 0x8 26. "PPEN90,peripheral protection enable 90" "0: SEC90 PRIV90 and RLOCK90 register bit not present.,1: SEC90 PRIV90 and RLOCK90 register bit present." newline bitfld.long 0x8 25. "PPEN89,peripheral protection enable 89" "0: SEC89 PRIV89 and RLOCK89 register bit not present.,1: SEC89 PRIV89 and RLOCK89 register bit present." bitfld.long 0x8 24. "PPEN88,peripheral protection enable 88" "0: SEC88 PRIV88 and RLOCK88 register bit not present.,1: SEC88 PRIV88 and RLOCK88 register bit present." newline bitfld.long 0x8 23. "PPEN87,peripheral protection enable 87" "0: SEC87 PRIV87 and RLOCK87 register bit not present.,1: SEC87 PRIV87 and RLOCK87 register bit present." bitfld.long 0x8 22. "PPEN86,peripheral protection enable 86" "0: SEC86 PRIV86 and RLOCK86 register bit not present.,1: SEC86 PRIV86 and RLOCK86 register bit present." newline bitfld.long 0x8 21. "PPEN85,peripheral protection enable 85" "0: SEC85 PRIV85 and RLOCK85 register bit not present.,1: SEC85 PRIV85 and RLOCK85 register bit present." bitfld.long 0x8 20. "PPEN84,peripheral protection enable 84" "0: SEC84 PRIV84 and RLOCK84 register bit not present.,1: SEC84 PRIV84 and RLOCK84 register bit present." newline bitfld.long 0x8 19. "PPEN83,peripheral protection enable 83" "0: SEC83 PRIV83 and RLOCK83 register bit not present.,1: SEC83 PRIV83 and RLOCK83 register bit present." bitfld.long 0x8 18. "PPEN82,peripheral protection enable 82" "0: SEC82 PRIV82 and RLOCK82 register bit not present.,1: SEC82 PRIV82 and RLOCK82 register bit present." newline bitfld.long 0x8 17. "PPEN81,peripheral protection enable 81" "0: SEC81 PRIV81 and RLOCK81 register bit not present.,1: SEC81 PRIV81 and RLOCK81 register bit present." bitfld.long 0x8 16. "PPEN80,peripheral protection enable 80" "0: SEC80 PRIV80 and RLOCK80 register bit not present.,1: SEC80 PRIV80 and RLOCK80 register bit present." newline bitfld.long 0x8 15. "PPEN79,peripheral protection enable 79" "0: SEC79 PRIV79 and RLOCK79 register bit not present.,1: SEC79 PRIV79 and RLOCK79 register bit present." bitfld.long 0x8 14. "PPEN78,peripheral protection enable 78" "0: SEC78 PRIV78 and RLOCK78 register bit not present.,1: SEC78 PRIV78 and RLOCK78 register bit present." newline bitfld.long 0x8 13. "PPEN77,peripheral protection enable 77" "0: SEC77 PRIV77 and RLOCK77 register bit not present.,1: SEC77 PRIV77 and RLOCK77 register bit present." bitfld.long 0x8 12. "PPEN76,peripheral protection enable 76" "0: SEC76 PRIV76 and RLOCK76 register bit not present.,1: SEC76 PRIV76 and RLOCK76 register bit present." newline bitfld.long 0x8 11. "PPEN75,peripheral protection enable 75" "0: SEC75 PRIV75 and RLOCK75 register bit not present.,1: SEC75 PRIV75 and RLOCK75 register bit present." bitfld.long 0x8 10. "PPEN74,peripheral protection enable 74" "0: SEC74 PRIV74 and RLOCK74 register bit not present.,1: SEC74 PRIV74 and RLOCK74 register bit present." newline bitfld.long 0x8 9. "PPEN73,peripheral protection enable 73" "0: SEC73 PRIV73 and RLOCK73 register bit not present.,1: SEC73 PRIV73 and RLOCK73 register bit present." bitfld.long 0x8 8. "PPEN72,peripheral protection enable 72" "0: SEC72 PRIV72 and RLOCK72 register bit not present.,1: SEC72 PRIV72 and RLOCK72 register bit present." newline bitfld.long 0x8 7. "PPEN71,peripheral protection enable 71" "0: SEC71 PRIV71 and RLOCK71 register bit not present.,1: SEC71 PRIV71 and RLOCK71 register bit present." bitfld.long 0x8 6. "PPEN70,peripheral protection enable 70" "0: SEC70 PRIV70 and RLOCK70 register bit not present.,1: SEC70 PRIV70 and RLOCK70 register bit present." newline bitfld.long 0x8 5. "PPEN69,peripheral protection enable 69" "0: SEC69 PRIV69 and RLOCK69 register bit not present.,1: SEC69 PRIV69 and RLOCK69 register bit present." bitfld.long 0x8 4. "PPEN68,peripheral protection enable 68" "0: SEC68 PRIV68 and RLOCK68 register bit not present.,1: SEC68 PRIV68 and RLOCK68 register bit present." newline bitfld.long 0x8 3. "PPEN67,peripheral protection enable 67" "0: SEC67 PRIV67 and RLOCK67 register bit not present.,1: SEC67 PRIV67 and RLOCK67 register bit present." bitfld.long 0x8 2. "PPEN66,peripheral protection enable 66" "0: SEC66 PRIV66 and RLOCK66 register bit not present.,1: SEC66 PRIV66 and RLOCK66 register bit present." newline bitfld.long 0x8 1. "PPEN65,peripheral protection enable 65" "0: SEC65 PRIV65 and RLOCK65 register bit not present.,1: SEC65 PRIV65 and RLOCK65 register bit present." bitfld.long 0x8 0. "PPEN64,peripheral protection enable 64" "0: SEC64 PRIV64 and RLOCK64 register bit not present.,1: SEC64 PRIV64 and RLOCK64 register bit present." line.long 0xC "RIFSC_PPSR3,RIFSC peripheral protection status register 3" bitfld.long 0xC 31. "PPEN127,peripheral protection enable 127" "0: SEC127 PRIV127 and RLOCK127 register bit not..,1: SEC127 PRIV127 and RLOCK127 register bit present." bitfld.long 0xC 30. "PPEN126,peripheral protection enable 126" "0: SEC126 PRIV126 and RLOCK126 register bit not..,1: SEC126 PRIV126 and RLOCK126 register bit present." newline bitfld.long 0xC 29. "PPEN125,peripheral protection enable 125" "0: SEC125 PRIV125 and RLOCK125 register bit not..,1: SEC125 PRIV125 and RLOCK125 register bit present." bitfld.long 0xC 28. "PPEN124,peripheral protection enable 124" "0: SEC124 PRIV124 and RLOCK124 register bit not..,1: SEC124 PRIV124 and RLOCK124 register bit present." newline bitfld.long 0xC 27. "PPEN123,peripheral protection enable 123" "0: SEC123 PRIV123 and RLOCK123 register bit not..,1: SEC123 PRIV123 and RLOCK123 register bit present." bitfld.long 0xC 26. "PPEN122,peripheral protection enable 122" "0: SEC122 PRIV122 and RLOCK122 register bit not..,1: SEC122 PRIV122 and RLOCK122 register bit present." newline bitfld.long 0xC 25. "PPEN121,peripheral protection enable 121" "0: SEC121 PRIV121 and RLOCK121 register bit not..,1: SEC121 PRIV121 and RLOCK121 register bit present." bitfld.long 0xC 24. "PPEN120,peripheral protection enable 120" "0: SEC120 PRIV120 and RLOCK120 register bit not..,1: SEC120 PRIV120 and RLOCK120 register bit present." newline bitfld.long 0xC 23. "PPEN119,peripheral protection enable 119" "0: SEC119 PRIV119 and RLOCK119 register bit not..,1: SEC119 PRIV119 and RLOCK119 register bit present." bitfld.long 0xC 22. "PPEN118,peripheral protection enable 118" "0: SEC118 PRIV118 and RLOCK118 register bit not..,1: SEC118 PRIV118 and RLOCK118 register bit present." newline bitfld.long 0xC 21. "PPEN117,peripheral protection enable 117" "0: SEC117 PRIV117 and RLOCK117 register bit not..,1: SEC117 PRIV117 and RLOCK117 register bit present." bitfld.long 0xC 20. "PPEN116,peripheral protection enable 116" "0: SEC116 PRIV116 and RLOCK116 register bit not..,1: SEC116 PRIV116 and RLOCK116 register bit present." newline bitfld.long 0xC 19. "PPEN115,peripheral protection enable 115" "0: SEC115 PRIV115 and RLOCK115 register bit not..,1: SEC115 PRIV115 and RLOCK115 register bit present." bitfld.long 0xC 18. "PPEN114,peripheral protection enable 114" "0: SEC114 PRIV114 and RLOCK114 register bit not..,1: SEC114 PRIV114 and RLOCK114 register bit present." newline bitfld.long 0xC 17. "PPEN113,peripheral protection enable 113" "0: SEC113 PRIV113 and RLOCK113 register bit not..,1: SEC113 PRIV113 and RLOCK113 register bit present." bitfld.long 0xC 16. "PPEN112,peripheral protection enable 112" "0: SEC112 PRIV112 and RLOCK112 register bit not..,1: SEC112 PRIV112 and RLOCK112 register bit present." newline bitfld.long 0xC 15. "PPEN111,peripheral protection enable 111" "0: SEC111 PRIV111 and RLOCK111 register bit not..,1: SEC111 PRIV111 and RLOCK111 register bit present." bitfld.long 0xC 14. "PPEN110,peripheral protection enable 110" "0: SEC110 PRIV110 and RLOCK110 register bit not..,1: SEC110 PRIV110 and RLOCK110 register bit present." newline bitfld.long 0xC 13. "PPEN109,peripheral protection enable 109" "0: SEC109 PRIV109 and RLOCK109 register bit not..,1: SEC109 PRIV109 and RLOCK109 register bit present." bitfld.long 0xC 12. "PPEN108,peripheral protection enable 108" "0: SEC108 PRIV108 and RLOCK108 register bit not..,1: SEC108 PRIV108 and RLOCK108 register bit present." newline bitfld.long 0xC 11. "PPEN107,peripheral protection enable 107" "0: SEC107 PRIV107 and RLOCK107 register bit not..,1: SEC107 PRIV107 and RLOCK107 register bit present." bitfld.long 0xC 10. "PPEN106,peripheral protection enable 106" "0: SEC106 PRIV106 and RLOCK106 register bit not..,1: SEC106 PRIV106 and RLOCK106 register bit present." newline bitfld.long 0xC 9. "PPEN105,peripheral protection enable 105" "0: SEC105 PRIV105 and RLOCK105 register bit not..,1: SEC105 PRIV105 and RLOCK105 register bit present." bitfld.long 0xC 8. "PPEN104,peripheral protection enable 104" "0: SEC104 PRIV104 and RLOCK104 register bit not..,1: SEC104 PRIV104 and RLOCK104 register bit present." newline bitfld.long 0xC 7. "PPEN103,peripheral protection enable 103" "0: SEC103 PRIV103 and RLOCK103 register bit not..,1: SEC103 PRIV103 and RLOCK103 register bit present." bitfld.long 0xC 6. "PPEN102,peripheral protection enable 102" "0: SEC102 PRIV102 and RLOCK102 register bit not..,1: SEC102 PRIV102 and RLOCK102 register bit present." newline bitfld.long 0xC 5. "PPEN101,peripheral protection enable 101" "0: SEC101 PRIV101 and RLOCK101 register bit not..,1: SEC101 PRIV101 and RLOCK101 register bit present." bitfld.long 0xC 4. "PPEN100,peripheral protection enable 100" "0: SEC100 PRIV100 and RLOCK100 register bit not..,1: SEC100 PRIV100 and RLOCK100 register bit present." newline bitfld.long 0xC 3. "PPEN99,peripheral protection enable 99" "0: SEC99 PRIV99 and RLOCK99 register bit not present.,1: SEC99 PRIV99 and RLOCK99 register bit present." bitfld.long 0xC 2. "PPEN98,peripheral protection enable 98" "0: SEC98 PRIV98 and RLOCK98 register bit not present.,1: SEC98 PRIV98 and RLOCK98 register bit present." newline bitfld.long 0xC 1. "PPEN97,peripheral protection enable 97" "0: SEC97 PRIV97 and RLOCK97 register bit not present.,1: SEC97 PRIV97 and RLOCK97 register bit present." bitfld.long 0xC 0. "PPEN96,peripheral protection enable 96" "0: SEC96 PRIV96 and RLOCK96 register bit not present.,1: SEC96 PRIV96 and RLOCK96 register bit present." line.long 0x10 "RIFSC_PPSR4,RIFSC peripheral protection status register 4" bitfld.long 0x10 31. "PPEN159,peripheral protection enable 159" "0: SEC159 PRIV159 and RLOCK159 register bit not..,1: SEC159 PRIV159 and RLOCK159 register bit present." bitfld.long 0x10 30. "PPEN158,peripheral protection enable 158" "0: SEC158 PRIV158 and RLOCK158 register bit not..,1: SEC158 PRIV158 and RLOCK158 register bit present." newline bitfld.long 0x10 29. "PPEN157,peripheral protection enable 157" "0: SEC157 PRIV157 and RLOCK157 register bit not..,1: SEC157 PRIV157 and RLOCK157 register bit present." bitfld.long 0x10 28. "PPEN156,peripheral protection enable 156" "0: SEC156 PRIV156 and RLOCK156 register bit not..,1: SEC156 PRIV156 and RLOCK156 register bit present." newline bitfld.long 0x10 27. "PPEN155,peripheral protection enable 155" "0: SEC155 PRIV155 and RLOCK155 register bit not..,1: SEC155 PRIV155 and RLOCK155 register bit present." bitfld.long 0x10 26. "PPEN154,peripheral protection enable 154" "0: SEC154 PRIV154 and RLOCK154 register bit not..,1: SEC154 PRIV154 and RLOCK154 register bit present." newline bitfld.long 0x10 25. "PPEN153,peripheral protection enable 153" "0: SEC153 PRIV153 and RLOCK153 register bit not..,1: SEC153 PRIV153 and RLOCK153 register bit present." bitfld.long 0x10 24. "PPEN152,peripheral protection enable 152" "0: SEC152 PRIV152 and RLOCK152 register bit not..,1: SEC152 PRIV152 and RLOCK152 register bit present." newline bitfld.long 0x10 23. "PPEN151,peripheral protection enable 151" "0: SEC151 PRIV151 and RLOCK151 register bit not..,1: SEC151 PRIV151 and RLOCK151 register bit present." bitfld.long 0x10 22. "PPEN150,peripheral protection enable 150" "0: SEC150 PRIV150 and RLOCK150 register bit not..,1: SEC150 PRIV150 and RLOCK150 register bit present." newline bitfld.long 0x10 21. "PPEN149,peripheral protection enable 149" "0: SEC149 PRIV149 and RLOCK149 register bit not..,1: SEC149 PRIV149 and RLOCK149 register bit present." bitfld.long 0x10 20. "PPEN148,peripheral protection enable 148" "0: SEC148 PRIV148 and RLOCK148 register bit not..,1: SEC148 PRIV148 and RLOCK148 register bit present." newline bitfld.long 0x10 19. "PPEN147,peripheral protection enable 147" "0: SEC147 PRIV147 and RLOCK147 register bit not..,1: SEC147 PRIV147 and RLOCK147 register bit present." bitfld.long 0x10 18. "PPEN146,peripheral protection enable 146" "0: SEC146 PRIV146 and RLOCK146 register bit not..,1: SEC146 PRIV146 and RLOCK146 register bit present." newline bitfld.long 0x10 17. "PPEN145,peripheral protection enable 145" "0: SEC145 PRIV145 and RLOCK145 register bit not..,1: SEC145 PRIV145 and RLOCK145 register bit present." bitfld.long 0x10 16. "PPEN144,peripheral protection enable 144" "0: SEC144 PRIV144 and RLOCK144 register bit not..,1: SEC144 PRIV144 and RLOCK144 register bit present." newline bitfld.long 0x10 15. "PPEN143,peripheral protection enable 143" "0: SEC143 PRIV143 and RLOCK143 register bit not..,1: SEC143 PRIV143 and RLOCK143 register bit present." bitfld.long 0x10 14. "PPEN142,peripheral protection enable 142" "0: SEC142 PRIV142 and RLOCK142 register bit not..,1: SEC142 PRIV142 and RLOCK142 register bit present." newline bitfld.long 0x10 13. "PPEN141,peripheral protection enable 141" "0: SEC141 PRIV141 and RLOCK141 register bit not..,1: SEC141 PRIV141 and RLOCK141 register bit present." bitfld.long 0x10 12. "PPEN140,peripheral protection enable 140" "0: SEC140 PRIV140 and RLOCK140 register bit not..,1: SEC140 PRIV140 and RLOCK140 register bit present." newline bitfld.long 0x10 11. "PPEN139,peripheral protection enable 139" "0: SEC139 PRIV139 and RLOCK139 register bit not..,1: SEC139 PRIV139 and RLOCK139 register bit present." bitfld.long 0x10 10. "PPEN138,peripheral protection enable 138" "0: SEC138 PRIV138 and RLOCK138 register bit not..,1: SEC138 PRIV138 and RLOCK138 register bit present." newline bitfld.long 0x10 9. "PPEN137,peripheral protection enable 137" "0: SEC137 PRIV137 and RLOCK137 register bit not..,1: SEC137 PRIV137 and RLOCK137 register bit present." bitfld.long 0x10 8. "PPEN136,peripheral protection enable 136" "0: SEC136 PRIV136 and RLOCK136 register bit not..,1: SEC136 PRIV136 and RLOCK136 register bit present." newline bitfld.long 0x10 7. "PPEN135,peripheral protection enable 135" "0: SEC135 PRIV135 and RLOCK135 register bit not..,1: SEC135 PRIV135 and RLOCK135 register bit present." bitfld.long 0x10 6. "PPEN134,peripheral protection enable 134" "0: SEC134 PRIV134 and RLOCK134 register bit not..,1: SEC134 PRIV134 and RLOCK134 register bit present." newline bitfld.long 0x10 5. "PPEN133,peripheral protection enable 133" "0: SEC133 PRIV133 and RLOCK133 register bit not..,1: SEC133 PRIV133 and RLOCK133 register bit present." bitfld.long 0x10 4. "PPEN132,peripheral protection enable 132" "0: SEC132 PRIV132 and RLOCK132 register bit not..,1: SEC132 PRIV132 and RLOCK132 register bit present." newline bitfld.long 0x10 3. "PPEN131,peripheral protection enable 131" "0: SEC131 PRIV131 and RLOCK131 register bit not..,1: SEC131 PRIV131 and RLOCK131 register bit present." bitfld.long 0x10 2. "PPEN130,peripheral protection enable 130" "0: SEC130 PRIV130 and RLOCK130 register bit not..,1: SEC130 PRIV130 and RLOCK130 register bit present." newline bitfld.long 0x10 1. "PPEN129,peripheral protection enable 129" "0: SEC129 PRIV129 and RLOCK129 register bit not..,1: SEC129 PRIV129 and RLOCK129 register bit present." bitfld.long 0x10 0. "PPEN128,peripheral protection enable 128" "0: SEC128 PRIV128 and RLOCK128 register bit not..,1: SEC128 PRIV128 and RLOCK128 register bit present." line.long 0x14 "RIFSC_PPSR5,RIFSC peripheral protection status register 5" bitfld.long 0x14 31. "PPEN191,peripheral protection enable 191" "0: SEC191 PRIV191 and RLOCK191 register bit not..,1: SEC191 PRIV191 and RLOCK191 register bit present." bitfld.long 0x14 30. "PPEN190,peripheral protection enable 190" "0: SEC190 PRIV190 and RLOCK190 register bit not..,1: SEC190 PRIV190 and RLOCK190 register bit present." newline bitfld.long 0x14 29. "PPEN189,peripheral protection enable 189" "0: SEC189 PRIV189 and RLOCK189 register bit not..,1: SEC189 PRIV189 and RLOCK189 register bit present." bitfld.long 0x14 28. "PPEN188,peripheral protection enable 188" "0: SEC188 PRIV188 and RLOCK188 register bit not..,1: SEC188 PRIV188 and RLOCK188 register bit present." newline bitfld.long 0x14 27. "PPEN187,peripheral protection enable 187" "0: SEC187 PRIV187 and RLOCK187 register bit not..,1: SEC187 PRIV187 and RLOCK187 register bit present." bitfld.long 0x14 26. "PPEN186,peripheral protection enable 186" "0: SEC186 PRIV186 and RLOCK186 register bit not..,1: SEC186 PRIV186 and RLOCK186 register bit present." newline bitfld.long 0x14 25. "PPEN185,peripheral protection enable 185" "0: SEC185 PRIV185 and RLOCK185 register bit not..,1: SEC185 PRIV185 and RLOCK185 register bit present." bitfld.long 0x14 24. "PPEN184,peripheral protection enable 184" "0: SEC184 PRIV184 and RLOCK184 register bit not..,1: SEC184 PRIV184 and RLOCK184 register bit present." newline bitfld.long 0x14 23. "PPEN183,peripheral protection enable 183" "0: SEC183 PRIV183 and RLOCK183 register bit not..,1: SEC183 PRIV183 and RLOCK183 register bit present." bitfld.long 0x14 22. "PPEN182,peripheral protection enable 182" "0: SEC182 PRIV182 and RLOCK182 register bit not..,1: SEC182 PRIV182 and RLOCK182 register bit present." newline bitfld.long 0x14 21. "PPEN181,peripheral protection enable 181" "0: SEC181 PRIV181 and RLOCK181 register bit not..,1: SEC181 PRIV181 and RLOCK181 register bit present." bitfld.long 0x14 20. "PPEN180,peripheral protection enable 180" "0: SEC180 PRIV180 and RLOCK180 register bit not..,1: SEC180 PRIV180 and RLOCK180 register bit present." newline bitfld.long 0x14 19. "PPEN179,peripheral protection enable 179" "0: SEC179 PRIV179 and RLOCK179 register bit not..,1: SEC179 PRIV179 and RLOCK179 register bit present." bitfld.long 0x14 18. "PPEN178,peripheral protection enable 178" "0: SEC178 PRIV178 and RLOCK178 register bit not..,1: SEC178 PRIV178 and RLOCK178 register bit present." newline bitfld.long 0x14 17. "PPEN177,peripheral protection enable 177" "0: SEC177 PRIV177 and RLOCK177 register bit not..,1: SEC177 PRIV177 and RLOCK177 register bit present." bitfld.long 0x14 16. "PPEN176,peripheral protection enable 176" "0: SEC176 PRIV176 and RLOCK176 register bit not..,1: SEC176 PRIV176 and RLOCK176 register bit present." newline bitfld.long 0x14 15. "PPEN175,peripheral protection enable 175" "0: SEC175 PRIV175 and RLOCK175 register bit not..,1: SEC175 PRIV175 and RLOCK175 register bit present." bitfld.long 0x14 14. "PPEN174,peripheral protection enable 174" "0: SEC174 PRIV174 and RLOCK174 register bit not..,1: SEC174 PRIV174 and RLOCK174 register bit present." newline bitfld.long 0x14 13. "PPEN173,peripheral protection enable 173" "0: SEC173 PRIV173 and RLOCK173 register bit not..,1: SEC173 PRIV173 and RLOCK173 register bit present." bitfld.long 0x14 12. "PPEN172,peripheral protection enable 172" "0: SEC172 PRIV172 and RLOCK172 register bit not..,1: SEC172 PRIV172 and RLOCK172 register bit present." newline bitfld.long 0x14 11. "PPEN171,peripheral protection enable 171" "0: SEC171 PRIV171 and RLOCK171 register bit not..,1: SEC171 PRIV171 and RLOCK171 register bit present." bitfld.long 0x14 10. "PPEN170,peripheral protection enable 170" "0: SEC170 PRIV170 and RLOCK170 register bit not..,1: SEC170 PRIV170 and RLOCK170 register bit present." newline bitfld.long 0x14 9. "PPEN169,peripheral protection enable 169" "0: SEC169 PRIV169 and RLOCK169 register bit not..,1: SEC169 PRIV169 and RLOCK169 register bit present." bitfld.long 0x14 8. "PPEN168,peripheral protection enable 168" "0: SEC168 PRIV168 and RLOCK168 register bit not..,1: SEC168 PRIV168 and RLOCK168 register bit present." newline bitfld.long 0x14 7. "PPEN167,peripheral protection enable 167" "0: SEC167 PRIV167 and RLOCK167 register bit not..,1: SEC167 PRIV167 and RLOCK167 register bit present." bitfld.long 0x14 6. "PPEN166,peripheral protection enable 166" "0: SEC166 PRIV166 and RLOCK166 register bit not..,1: SEC166 PRIV166 and RLOCK166 register bit present." newline bitfld.long 0x14 5. "PPEN165,peripheral protection enable 165" "0: SEC165 PRIV165 and RLOCK165 register bit not..,1: SEC165 PRIV165 and RLOCK165 register bit present." bitfld.long 0x14 4. "PPEN164,peripheral protection enable 164" "0: SEC164 PRIV164 and RLOCK164 register bit not..,1: SEC164 PRIV164 and RLOCK164 register bit present." newline bitfld.long 0x14 3. "PPEN163,peripheral protection enable 163" "0: SEC163 PRIV163 and RLOCK163 register bit not..,1: SEC163 PRIV163 and RLOCK163 register bit present." bitfld.long 0x14 2. "PPEN162,peripheral protection enable 162" "0: SEC162 PRIV162 and RLOCK162 register bit not..,1: SEC162 PRIV162 and RLOCK162 register bit present." newline bitfld.long 0x14 1. "PPEN161,peripheral protection enable 161" "0: SEC161 PRIV161 and RLOCK161 register bit not..,1: SEC161 PRIV161 and RLOCK161 register bit present." bitfld.long 0x14 0. "PPEN160,peripheral protection enable 160" "0: SEC160 PRIV160 and RLOCK160 register bit not..,1: SEC160 PRIV160 and RLOCK160 register bit present." tree.end tree.end tree "RISAF (Resource Isolation Slave Unit)" base ad:0x0 tree "RISAF" base ad:0x44026000 group.long 0x0++0x3 line.long 0x0 "RISAF_CR,RISAF configuration register" bitfld.long 0x0 0. "GLOCK,global lock" "0: RISAF registers are writable.,1: All writes to RISAF registers are ignored except.." rgroup.long 0x8++0x3 line.long 0x0 "RISAF_IASR,RISAF illegal access status register" bitfld.long 0x0 1. "IAEF,illegal access error flag" "0,1" bitfld.long 0x0 0. "CAEF,configuration access error flag" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "RISAF_IACR,RISAF illegal access clear register" bitfld.long 0x0 1. "IAEF,illegal access error flag" "0,1" bitfld.long 0x0 0. "CAEF,configuration access error flag" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "RISAF_IAESR,RISAF illegal access error status register" bitfld.long 0x0 7. "IANRW,illegal access read/write" "0: Illegal access was a data read or an instruction..,1: Illegal access was a data write." bitfld.long 0x0 5. "IASEC,illegal access security" "0: Illegal access was non-secure.,1: Illegal access was secure." newline bitfld.long 0x0 4. "IAPRIV,illegal access privileged" "0: Illegal access was unprivileged.,1: Illegal access was privileged." bitfld.long 0x0 0.--2. "IACID,illegal access compartment ID" "0,1,2,3,4,5,6,7" line.long 0x4 "RISAF_IADDR,RISAF illegal address register" hexmask.long 0x4 0.--31. 1. "IADD,illegal address" group.long 0x40++0xF line.long 0x0 "RISAF_REG1_CFGR,RISAF region 1 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG1_STARTR,RISAF region 1 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG1_ENDR,RISAF region 1 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG1_CIDCFGR,RISAF region 1 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x80++0xF line.long 0x0 "RISAF_REG2_CFGR,RISAF region 2 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG2_STARTR,RISAF region 2 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG2_ENDR,RISAF region 2 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG2_CIDCFGR,RISAF region 2 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0xC0++0xF line.long 0x0 "RISAF_REG3_CFGR,RISAF region 3 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG3_STARTR,RISAF region 3 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG3_ENDR,RISAF region 3 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG3_CIDCFGR,RISAF region 3 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x100++0xF line.long 0x0 "RISAF_REG4_CFGR,RISAF region 4 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG4_STARTR,RISAF region 4 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG4_ENDR,RISAF region 4 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG4_CIDCFGR,RISAF region 4 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x140++0xF line.long 0x0 "RISAF_REG5_CFGR,RISAF region 5 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG5_STARTR,RISAF region 5 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG5_ENDR,RISAF region 5 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG5_CIDCFGR,RISAF region 5 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x180++0xF line.long 0x0 "RISAF_REG6_CFGR,RISAF region 6 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG6_STARTR,RISAF region 6 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG6_ENDR,RISAF region 6 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG6_CIDCFGR,RISAF region 6 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x1C0++0xF line.long 0x0 "RISAF_REG7_CFGR,RISAF region 7 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG7_STARTR,RISAF region 7 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG7_ENDR,RISAF region 7 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG7_CIDCFGR,RISAF region 7 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x200++0xF line.long 0x0 "RISAF_REG8_CFGR,RISAF region 8 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG8_STARTR,RISAF region 8 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG8_ENDR,RISAF region 8 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG8_CIDCFGR,RISAF region 8 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x240++0xF line.long 0x0 "RISAF_REG9_CFGR,RISAF region 9 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG9_STARTR,RISAF region 9 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG9_ENDR,RISAF region 9 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG9_CIDCFGR,RISAF region 9 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x280++0xF line.long 0x0 "RISAF_REG10_CFGR,RISAF region 10 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG10_STARTR,RISAF region 10 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG10_ENDR,RISAF region 10 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG10_CIDCFGR,RISAF region 10 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x2C0++0xF line.long 0x0 "RISAF_REG11_CFGR,RISAF region 11 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG11_STARTR,RISAF region 11 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG11_ENDR,RISAF region 11 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG11_CIDCFGR,RISAF region 11 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x300++0xF line.long 0x0 "RISAF_REG12_CFGR,RISAF region 12 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG12_STARTR,RISAF region 12 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG12_ENDR,RISAF region 12 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG12_CIDCFGR,RISAF region 12 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x340++0xF line.long 0x0 "RISAF_REG13_CFGR,RISAF region 13 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG13_STARTR,RISAF region 13 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG13_ENDR,RISAF region 13 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG13_CIDCFGR,RISAF region 13 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x380++0xF line.long 0x0 "RISAF_REG14_CFGR,RISAF region 14 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG14_STARTR,RISAF region 14 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG14_ENDR,RISAF region 14 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG14_CIDCFGR,RISAF region 14 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x3C0++0xF line.long 0x0 "RISAF_REG15_CFGR,RISAF region 15 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG15_STARTR,RISAF region 15 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG15_ENDR,RISAF region 15 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG15_CIDCFGR,RISAF region 15 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x50++0xF line.long 0x0 "RISAF_REG1_ACFGR,RISAF region 1 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG1_ASTARTR,RISAF region 1 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG1_AENDR,RISAF region 1 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG1_ANESTR,RISAF region 1 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x90++0xF line.long 0x0 "RISAF_REG2_ACFGR,RISAF region 2 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG2_ASTARTR,RISAF region 2 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG2_AENDR,RISAF region 2 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG2_ANESTR,RISAF region 2 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0xD0++0xF line.long 0x0 "RISAF_REG3_ACFGR,RISAF region 3 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG3_ASTARTR,RISAF region 3 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG3_AENDR,RISAF region 3 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG3_ANESTR,RISAF region 3 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x110++0xF line.long 0x0 "RISAF_REG4_ACFGR,RISAF region 4 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG4_ASTARTR,RISAF region 4 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG4_AENDR,RISAF region 4 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG4_ANESTR,RISAF region 4 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x150++0xF line.long 0x0 "RISAF_REG5_ACFGR,RISAF region 5 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG5_ASTARTR,RISAF region 5 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG5_AENDR,RISAF region 5 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG5_ANESTR,RISAF region 5 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x190++0xF line.long 0x0 "RISAF_REG6_ACFGR,RISAF region 6 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG6_ASTARTR,RISAF region 6 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG6_AENDR,RISAF region 6 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG6_ANESTR,RISAF region 6 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x1D0++0xF line.long 0x0 "RISAF_REG7_ACFGR,RISAF region 7 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG7_ASTARTR,RISAF region 7 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG7_AENDR,RISAF region 7 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG7_ANESTR,RISAF region 7 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x210++0xF line.long 0x0 "RISAF_REG8_ACFGR,RISAF region 8 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG8_ASTARTR,RISAF region 8 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG8_AENDR,RISAF region 8 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG8_ANESTR,RISAF region 8 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x250++0xF line.long 0x0 "RISAF_REG9_ACFGR,RISAF region 9 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG9_ASTARTR,RISAF region 9 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG9_AENDR,RISAF region 9 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG9_ANESTR,RISAF region 9 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x290++0xF line.long 0x0 "RISAF_REG10_ACFGR,RISAF region 10 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG10_ASTARTR,RISAF region 10 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG10_AENDR,RISAF region 10 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG10_ANESTR,RISAF region 10 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x2D0++0xF line.long 0x0 "RISAF_REG11_ACFGR,RISAF region 11 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG11_ASTARTR,RISAF region 11 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG11_AENDR,RISAF region 11 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG11_ANESTR,RISAF region 11 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x310++0xF line.long 0x0 "RISAF_REG12_ACFGR,RISAF region 12 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG12_ASTARTR,RISAF region 12 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG12_AENDR,RISAF region 12 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG12_ANESTR,RISAF region 12 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x350++0xF line.long 0x0 "RISAF_REG13_ACFGR,RISAF region 13 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG13_ASTARTR,RISAF region 13 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG13_AENDR,RISAF region 13 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG13_ANESTR,RISAF region 13 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x390++0xF line.long 0x0 "RISAF_REG14_ACFGR,RISAF region 14 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG14_ASTARTR,RISAF region 14 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG14_AENDR,RISAF region 14 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG14_ANESTR,RISAF region 14 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x3D0++0xF line.long 0x0 "RISAF_REG15_ACFGR,RISAF region 15 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG15_ASTARTR,RISAF region 15 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG15_AENDR,RISAF region 15 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG15_ANESTR,RISAF region 15 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x60++0xF line.long 0x0 "RISAF_REG1_BCFGR,RISAF region 1 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG1_BSTARTR,RISAF region 1 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG1_BENDR,RISAF region 1 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG1_BNESTR,RISAF region 1 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0xA0++0xF line.long 0x0 "RISAF_REG2_BCFGR,RISAF region 2 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG2_BSTARTR,RISAF region 2 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG2_BENDR,RISAF region 2 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG2_BNESTR,RISAF region 2 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0xE0++0xF line.long 0x0 "RISAF_REG3_BCFGR,RISAF region 3 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG3_BSTARTR,RISAF region 3 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG3_BENDR,RISAF region 3 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG3_BNESTR,RISAF region 3 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x120++0xF line.long 0x0 "RISAF_REG4_BCFGR,RISAF region 4 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG4_BSTARTR,RISAF region 4 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG4_BENDR,RISAF region 4 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG4_BNESTR,RISAF region 4 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x160++0xF line.long 0x0 "RISAF_REG5_BCFGR,RISAF region 5 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG5_BSTARTR,RISAF region 5 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG5_BENDR,RISAF region 5 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG5_BNESTR,RISAF region 5 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x1A0++0xF line.long 0x0 "RISAF_REG6_BCFGR,RISAF region 6 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG6_BSTARTR,RISAF region 6 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG6_BENDR,RISAF region 6 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG6_BNESTR,RISAF region 6 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x1E0++0xF line.long 0x0 "RISAF_REG7_BCFGR,RISAF region 7 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG7_BSTARTR,RISAF region 7 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG7_BENDR,RISAF region 7 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG7_BNESTR,RISAF region 7 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x220++0xF line.long 0x0 "RISAF_REG8_BCFGR,RISAF region 8 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG8_BSTARTR,RISAF region 8 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG8_BENDR,RISAF region 8 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG8_BNESTR,RISAF region 8 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x260++0xF line.long 0x0 "RISAF_REG9_BCFGR,RISAF region 9 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG9_BSTARTR,RISAF region 9 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG9_BENDR,RISAF region 9 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG9_BNESTR,RISAF region 9 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x2A0++0xF line.long 0x0 "RISAF_REG10_BCFGR,RISAF region 10 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG10_BSTARTR,RISAF region 10 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG10_BENDR,RISAF region 10 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG10_BNESTR,RISAF region 10 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x2E0++0xF line.long 0x0 "RISAF_REG11_BCFGR,RISAF region 11 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG11_BSTARTR,RISAF region 11 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG11_BENDR,RISAF region 11 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG11_BNESTR,RISAF region 11 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x320++0xF line.long 0x0 "RISAF_REG12_BCFGR,RISAF region 12 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG12_BSTARTR,RISAF region 12 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG12_BENDR,RISAF region 12 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG12_BNESTR,RISAF region 12 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x360++0xF line.long 0x0 "RISAF_REG13_BCFGR,RISAF region 13 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG13_BSTARTR,RISAF region 13 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG13_BENDR,RISAF region 13 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG13_BNESTR,RISAF region 13 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x3A0++0xF line.long 0x0 "RISAF_REG14_BCFGR,RISAF region 14 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG14_BSTARTR,RISAF region 14 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG14_BENDR,RISAF region 14 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG14_BNESTR,RISAF region 14 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x3E0++0xF line.long 0x0 "RISAF_REG15_BCFGR,RISAF region 15 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG15_BSTARTR,RISAF region 15 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG15_BENDR,RISAF region 15 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG15_BNESTR,RISAF region 15 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." tree.end tree "RISAF_S" base ad:0x54026000 group.long 0x0++0x3 line.long 0x0 "RISAF_CR,RISAF configuration register" bitfld.long 0x0 0. "GLOCK,global lock" "0: RISAF registers are writable.,1: All writes to RISAF registers are ignored except.." rgroup.long 0x8++0x3 line.long 0x0 "RISAF_IASR,RISAF illegal access status register" bitfld.long 0x0 1. "IAEF,illegal access error flag" "0,1" bitfld.long 0x0 0. "CAEF,configuration access error flag" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "RISAF_IACR,RISAF illegal access clear register" bitfld.long 0x0 1. "IAEF,illegal access error flag" "0,1" bitfld.long 0x0 0. "CAEF,configuration access error flag" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "RISAF_IAESR,RISAF illegal access error status register" bitfld.long 0x0 7. "IANRW,illegal access read/write" "0: Illegal access was a data read or an instruction..,1: Illegal access was a data write." bitfld.long 0x0 5. "IASEC,illegal access security" "0: Illegal access was non-secure.,1: Illegal access was secure." newline bitfld.long 0x0 4. "IAPRIV,illegal access privileged" "0: Illegal access was unprivileged.,1: Illegal access was privileged." bitfld.long 0x0 0.--2. "IACID,illegal access compartment ID" "0,1,2,3,4,5,6,7" line.long 0x4 "RISAF_IADDR,RISAF illegal address register" hexmask.long 0x4 0.--31. 1. "IADD,illegal address" group.long 0x40++0xF line.long 0x0 "RISAF_REG1_CFGR,RISAF region 1 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG1_STARTR,RISAF region 1 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG1_ENDR,RISAF region 1 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG1_CIDCFGR,RISAF region 1 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x80++0xF line.long 0x0 "RISAF_REG2_CFGR,RISAF region 2 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG2_STARTR,RISAF region 2 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG2_ENDR,RISAF region 2 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG2_CIDCFGR,RISAF region 2 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0xC0++0xF line.long 0x0 "RISAF_REG3_CFGR,RISAF region 3 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG3_STARTR,RISAF region 3 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG3_ENDR,RISAF region 3 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG3_CIDCFGR,RISAF region 3 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x100++0xF line.long 0x0 "RISAF_REG4_CFGR,RISAF region 4 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG4_STARTR,RISAF region 4 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG4_ENDR,RISAF region 4 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG4_CIDCFGR,RISAF region 4 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x140++0xF line.long 0x0 "RISAF_REG5_CFGR,RISAF region 5 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG5_STARTR,RISAF region 5 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG5_ENDR,RISAF region 5 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG5_CIDCFGR,RISAF region 5 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x180++0xF line.long 0x0 "RISAF_REG6_CFGR,RISAF region 6 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG6_STARTR,RISAF region 6 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG6_ENDR,RISAF region 6 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG6_CIDCFGR,RISAF region 6 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x1C0++0xF line.long 0x0 "RISAF_REG7_CFGR,RISAF region 7 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG7_STARTR,RISAF region 7 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG7_ENDR,RISAF region 7 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG7_CIDCFGR,RISAF region 7 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x200++0xF line.long 0x0 "RISAF_REG8_CFGR,RISAF region 8 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG8_STARTR,RISAF region 8 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG8_ENDR,RISAF region 8 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG8_CIDCFGR,RISAF region 8 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x240++0xF line.long 0x0 "RISAF_REG9_CFGR,RISAF region 9 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG9_STARTR,RISAF region 9 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG9_ENDR,RISAF region 9 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG9_CIDCFGR,RISAF region 9 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x280++0xF line.long 0x0 "RISAF_REG10_CFGR,RISAF region 10 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG10_STARTR,RISAF region 10 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG10_ENDR,RISAF region 10 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG10_CIDCFGR,RISAF region 10 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x2C0++0xF line.long 0x0 "RISAF_REG11_CFGR,RISAF region 11 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG11_STARTR,RISAF region 11 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG11_ENDR,RISAF region 11 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG11_CIDCFGR,RISAF region 11 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x300++0xF line.long 0x0 "RISAF_REG12_CFGR,RISAF region 12 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG12_STARTR,RISAF region 12 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG12_ENDR,RISAF region 12 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG12_CIDCFGR,RISAF region 12 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x340++0xF line.long 0x0 "RISAF_REG13_CFGR,RISAF region 13 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG13_STARTR,RISAF region 13 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG13_ENDR,RISAF region 13 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG13_CIDCFGR,RISAF region 13 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x380++0xF line.long 0x0 "RISAF_REG14_CFGR,RISAF region 14 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG14_STARTR,RISAF region 14 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG14_ENDR,RISAF region 14 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG14_CIDCFGR,RISAF region 14 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x3C0++0xF line.long 0x0 "RISAF_REG15_CFGR,RISAF region 15 configuration register" bitfld.long 0x0 23. "PRIVC7,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 22. "PRIVC6,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 21. "PRIVC5,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 20. "PRIVC4,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 19. "PRIVC3,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 18. "PRIVC2,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 17. "PRIVC1,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." bitfld.long 0x0 16. "PRIVC0,privileged access for compartment y" "0: Application running in compartment y can access..,1: Application running in compartment y can access.." newline bitfld.long 0x0 8. "SEC,secure region" "0: Only non-secure requests can access region x.,1: Only secure requests can access region x and.." bitfld.long 0x0 0. "BREN,base region enable" "0: Base region x is disabled. Access control of..,1: Base region x is enabled. Access controls.." line.long 0x4 "RISAF_REG15_STARTR,RISAF region 15 start-address register" hexmask.long 0x4 0.--31. 1. "BADDSTART,Base region address start" line.long 0x8 "RISAF_REG15_ENDR,RISAF region 15 end-address register" hexmask.long 0x8 0.--31. 1. "BADDEND,Base region address end" line.long 0xC "RISAF_REG15_CIDCFGR,RISAF region 15 CID configuration register" bitfld.long 0xC 23. "WRENC7,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 22. "WRENC6,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 21. "WRENC5,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 20. "WRENC4,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 19. "WRENC3,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 18. "WRENC2,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 17. "WRENC1,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." bitfld.long 0xC 16. "WRENC0,write enable for compartment y" "0: Application running in compartment y cannot..,1: Application running in compartment y can write.." newline bitfld.long 0xC 7. "RDENC7,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 6. "RDENC6,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 5. "RDENC5,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 4. "RDENC4,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 3. "RDENC3,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 2. "RDENC2,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." newline bitfld.long 0xC 1. "RDENC1,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." bitfld.long 0xC 0. "RDENC0,read enable for compartment y" "0: Application running in compartment y cannot read..,1: Application running in compartment y can read.." group.long 0x50++0xF line.long 0x0 "RISAF_REG1_ACFGR,RISAF region 1 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG1_ASTARTR,RISAF region 1 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG1_AENDR,RISAF region 1 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG1_ANESTR,RISAF region 1 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x90++0xF line.long 0x0 "RISAF_REG2_ACFGR,RISAF region 2 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG2_ASTARTR,RISAF region 2 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG2_AENDR,RISAF region 2 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG2_ANESTR,RISAF region 2 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0xD0++0xF line.long 0x0 "RISAF_REG3_ACFGR,RISAF region 3 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG3_ASTARTR,RISAF region 3 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG3_AENDR,RISAF region 3 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG3_ANESTR,RISAF region 3 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x110++0xF line.long 0x0 "RISAF_REG4_ACFGR,RISAF region 4 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG4_ASTARTR,RISAF region 4 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG4_AENDR,RISAF region 4 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG4_ANESTR,RISAF region 4 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x150++0xF line.long 0x0 "RISAF_REG5_ACFGR,RISAF region 5 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG5_ASTARTR,RISAF region 5 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG5_AENDR,RISAF region 5 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG5_ANESTR,RISAF region 5 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x190++0xF line.long 0x0 "RISAF_REG6_ACFGR,RISAF region 6 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG6_ASTARTR,RISAF region 6 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG6_AENDR,RISAF region 6 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG6_ANESTR,RISAF region 6 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x1D0++0xF line.long 0x0 "RISAF_REG7_ACFGR,RISAF region 7 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG7_ASTARTR,RISAF region 7 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG7_AENDR,RISAF region 7 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG7_ANESTR,RISAF region 7 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x210++0xF line.long 0x0 "RISAF_REG8_ACFGR,RISAF region 8 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG8_ASTARTR,RISAF region 8 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG8_AENDR,RISAF region 8 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG8_ANESTR,RISAF region 8 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x250++0xF line.long 0x0 "RISAF_REG9_ACFGR,RISAF region 9 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG9_ASTARTR,RISAF region 9 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG9_AENDR,RISAF region 9 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG9_ANESTR,RISAF region 9 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x290++0xF line.long 0x0 "RISAF_REG10_ACFGR,RISAF region 10 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG10_ASTARTR,RISAF region 10 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG10_AENDR,RISAF region 10 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG10_ANESTR,RISAF region 10 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x2D0++0xF line.long 0x0 "RISAF_REG11_ACFGR,RISAF region 11 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG11_ASTARTR,RISAF region 11 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG11_AENDR,RISAF region 11 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG11_ANESTR,RISAF region 11 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x310++0xF line.long 0x0 "RISAF_REG12_ACFGR,RISAF region 12 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG12_ASTARTR,RISAF region 12 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG12_AENDR,RISAF region 12 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG12_ANESTR,RISAF region 12 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x350++0xF line.long 0x0 "RISAF_REG13_ACFGR,RISAF region 13 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG13_ASTARTR,RISAF region 13 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG13_AENDR,RISAF region 13 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG13_ANESTR,RISAF region 13 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x390++0xF line.long 0x0 "RISAF_REG14_ACFGR,RISAF region 14 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG14_ASTARTR,RISAF region 14 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG14_AENDR,RISAF region 14 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG14_ANESTR,RISAF region 14 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x3D0++0xF line.long 0x0 "RISAF_REG15_ACFGR,RISAF region 15 subregion A configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG15_ASTARTR,RISAF region 15 subregion A start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG15_AENDR,RISAF region 15 subregion A end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG15_ANESTR,RISAF region 15 subregion A nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x60++0xF line.long 0x0 "RISAF_REG1_BCFGR,RISAF region 1 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG1_BSTARTR,RISAF region 1 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG1_BENDR,RISAF region 1 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG1_BNESTR,RISAF region 1 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0xA0++0xF line.long 0x0 "RISAF_REG2_BCFGR,RISAF region 2 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG2_BSTARTR,RISAF region 2 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG2_BENDR,RISAF region 2 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG2_BNESTR,RISAF region 2 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0xE0++0xF line.long 0x0 "RISAF_REG3_BCFGR,RISAF region 3 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG3_BSTARTR,RISAF region 3 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG3_BENDR,RISAF region 3 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG3_BNESTR,RISAF region 3 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x120++0xF line.long 0x0 "RISAF_REG4_BCFGR,RISAF region 4 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG4_BSTARTR,RISAF region 4 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG4_BENDR,RISAF region 4 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG4_BNESTR,RISAF region 4 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x160++0xF line.long 0x0 "RISAF_REG5_BCFGR,RISAF region 5 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG5_BSTARTR,RISAF region 5 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG5_BENDR,RISAF region 5 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG5_BNESTR,RISAF region 5 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x1A0++0xF line.long 0x0 "RISAF_REG6_BCFGR,RISAF region 6 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG6_BSTARTR,RISAF region 6 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG6_BENDR,RISAF region 6 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG6_BNESTR,RISAF region 6 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x1E0++0xF line.long 0x0 "RISAF_REG7_BCFGR,RISAF region 7 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG7_BSTARTR,RISAF region 7 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG7_BENDR,RISAF region 7 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG7_BNESTR,RISAF region 7 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x220++0xF line.long 0x0 "RISAF_REG8_BCFGR,RISAF region 8 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG8_BSTARTR,RISAF region 8 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG8_BENDR,RISAF region 8 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG8_BNESTR,RISAF region 8 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x260++0xF line.long 0x0 "RISAF_REG9_BCFGR,RISAF region 9 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG9_BSTARTR,RISAF region 9 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG9_BENDR,RISAF region 9 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG9_BNESTR,RISAF region 9 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x2A0++0xF line.long 0x0 "RISAF_REG10_BCFGR,RISAF region 10 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG10_BSTARTR,RISAF region 10 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG10_BENDR,RISAF region 10 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG10_BNESTR,RISAF region 10 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x2E0++0xF line.long 0x0 "RISAF_REG11_BCFGR,RISAF region 11 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG11_BSTARTR,RISAF region 11 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG11_BENDR,RISAF region 11 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG11_BNESTR,RISAF region 11 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x320++0xF line.long 0x0 "RISAF_REG12_BCFGR,RISAF region 12 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG12_BSTARTR,RISAF region 12 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG12_BENDR,RISAF region 12 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG12_BNESTR,RISAF region 12 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x360++0xF line.long 0x0 "RISAF_REG13_BCFGR,RISAF region 13 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG13_BSTARTR,RISAF region 13 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG13_BENDR,RISAF region 13 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG13_BNESTR,RISAF region 13 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x3A0++0xF line.long 0x0 "RISAF_REG14_BCFGR,RISAF region 14 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG14_BSTARTR,RISAF region 14 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG14_BENDR,RISAF region 14 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG14_BNESTR,RISAF region 14 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." group.long 0x3E0++0xF line.long 0x0 "RISAF_REG15_BCFGR,RISAF region 15 subregion B configuration register" bitfld.long 0x0 13. "WREN,write enable" "0: Any writes to subregion z of region x are ignored.,1: Subregion z of region x can be written to." bitfld.long 0x0 12. "RDEN,read enable" "0: Any read to subregion z of region x returns zero.,1: Subregion z of region x can be read." newline bitfld.long 0x0 9. "PRIV,privileged subregion" "0: Privileged and unprivileged accesses are granted..,1: Only privileged accesses are granted in.." bitfld.long 0x0 8. "SEC,secure subregion" "0: Only non-secure requests can access subregion z..,1: Only secure requests can access subregion z of.." newline bitfld.long 0x0 4.--6. "SRCID,subregion CID" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "RLOCK,resource lock" "0: RISAF_REGx_zCFGR RISAF_REGx_zSTARTR and..,1: Writes to RISAF_REGx_zCFGR RISAF_REGx_zSTARTR.." newline bitfld.long 0x0 0. "SREN,subregion enable" "0: Subregion z is disabled. Access control of base..,1: Subregion z of region x is enable. Access.." line.long 0x4 "RISAF_REG15_BSTARTR,RISAF region 15 subregion B start-address register" hexmask.long 0x4 0.--31. 1. "SADDSTART,subregion address start" line.long 0x8 "RISAF_REG15_BENDR,RISAF region 15 subregion B end-address register" hexmask.long 0x8 0.--31. 1. "SADDEND,subregion address end" line.long 0xC "RISAF_REG15_BNESTR,RISAF region 15 subregion B nested mode register" bitfld.long 0xC 2. "DCEN,delegated configuration enable" "0: RIF configuration for subregion z can be written..,1: RIF configuration for subregion z can be written.." tree.end tree.end tree "RNG (Random Number Generator)" base ad:0x0 tree "RNG" base ad:0x44020000 group.long 0x0++0x7 line.long 0x0 "RNG_CR,RNG control register" bitfld.long 0x0 31. "CONFIGLOCK,RNG Config lock" "0: Writes to the RNG_NSCR RNG_HTCR and RNG_CR..,1: Writes to the RNG_NSCR RNG_HTCR and RNG_CR.." bitfld.long 0x0 30. "CONDRST,Conditioning soft reset" "0,1" newline hexmask.long.byte 0x0 20.--25. 1. "RNG_CONFIG1,RNG configuration 1" hexmask.long.byte 0x0 16.--19. 1. "CLKDIV,Clock divider factor" newline bitfld.long 0x0 13.--15. "RNG_CONFIG2,RNG configuration 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "NISTC,NIST custom" "0: Hardware default values for NIST compliant RNG.,1: Custom values for NIST compliant RNG. See.." newline hexmask.long.byte 0x0 8.--11. 1. "RNG_CONFIG3,RNG configuration 3" bitfld.long 0x0 7. "ARDIS,Auto reset disable" "0: When a noise source error occurs RNG performs an..,1: When a noise source error occurs the application.." newline bitfld.long 0x0 5. "CED,Clock error detection" "0: Clock error detection enabled,1: Clock error detection is disabled" bitfld.long 0x0 3. "IE,Interrupt enable" "0: RNG interrupt is disabled,1: RNG interrupt is enabled. An interrupt is.." newline bitfld.long 0x0 2. "RNGEN,True random number generator enable" "0: True random number generator is disabled. Analog..,1: True random number generator is enabled." line.long 0x4 "RNG_SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status" "0: No faulty sequence detected,1: At least one faulty sequence is detected. See.." bitfld.long 0x4 5. "CEIS,Clock error interrupt status" "0: The RNG clock is correct (f less than sub>RNGCLK..,1: The RNG clock before the internal divider is.." newline rbitfld.long 0x4 2. "SECS,Seed error current status" "0: No faulty sequence has currently been detected.,1: At least one of the following faulty sequences.." rbitfld.long 0x4 1. "CECS,Clock error current status" "0: The RNG clock is correct (f less than sub>RNGCLK..,1: The RNG clock is too slow (f less than.." newline rbitfld.long 0x4 0. "DRDY,Data ready" "0: The RNG_DR register is not yet valid no random..,1: The RNG_DR register contains valid random data." rgroup.long 0x8++0x3 line.long 0x0 "RNG_DR,RNG data register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data" group.long 0xC++0x7 line.long 0x0 "RNG_NSCR,RNG noise source control register" bitfld.long 0x0 15.--17. "EN_OSC6,Each bit drives one oscillator enable signal input of instance number 6 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "EN_OSC5,Each bit drives one oscillator enable signal input of instance number 5 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "EN_OSC4,Each bit drives one oscillator enable signal input of instance number 4 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "EN_OSC3,Each bit drives one oscillator enable signal input of instance number 3 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "EN_OSC2,Each bit drives one oscillator enable signal input of instance number 2 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "EN_OSC1,Each bit drives one oscillator enable signal input of instance number 1 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" line.long 0x4 "RNG_HTCR,RNG health test control register" hexmask.long 0x4 0.--31. 1. "HTCFG,health test configuration" tree.end tree "RNG_S" base ad:0x54020000 group.long 0x0++0x7 line.long 0x0 "RNG_CR,RNG control register" bitfld.long 0x0 31. "CONFIGLOCK,RNG Config lock" "0: Writes to the RNG_NSCR RNG_HTCR and RNG_CR..,1: Writes to the RNG_NSCR RNG_HTCR and RNG_CR.." bitfld.long 0x0 30. "CONDRST,Conditioning soft reset" "0,1" newline hexmask.long.byte 0x0 20.--25. 1. "RNG_CONFIG1,RNG configuration 1" hexmask.long.byte 0x0 16.--19. 1. "CLKDIV,Clock divider factor" newline bitfld.long 0x0 13.--15. "RNG_CONFIG2,RNG configuration 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "NISTC,NIST custom" "0: Hardware default values for NIST compliant RNG.,1: Custom values for NIST compliant RNG. See.." newline hexmask.long.byte 0x0 8.--11. 1. "RNG_CONFIG3,RNG configuration 3" bitfld.long 0x0 7. "ARDIS,Auto reset disable" "0: When a noise source error occurs RNG performs an..,1: When a noise source error occurs the application.." newline bitfld.long 0x0 5. "CED,Clock error detection" "0: Clock error detection enabled,1: Clock error detection is disabled" bitfld.long 0x0 3. "IE,Interrupt enable" "0: RNG interrupt is disabled,1: RNG interrupt is enabled. An interrupt is.." newline bitfld.long 0x0 2. "RNGEN,True random number generator enable" "0: True random number generator is disabled. Analog..,1: True random number generator is enabled." line.long 0x4 "RNG_SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status" "0: No faulty sequence detected,1: At least one faulty sequence is detected. See.." bitfld.long 0x4 5. "CEIS,Clock error interrupt status" "0: The RNG clock is correct (f less than sub>RNGCLK..,1: The RNG clock before the internal divider is.." newline rbitfld.long 0x4 2. "SECS,Seed error current status" "0: No faulty sequence has currently been detected.,1: At least one of the following faulty sequences.." rbitfld.long 0x4 1. "CECS,Clock error current status" "0: The RNG clock is correct (f less than sub>RNGCLK..,1: The RNG clock is too slow (f less than.." newline rbitfld.long 0x4 0. "DRDY,Data ready" "0: The RNG_DR register is not yet valid no random..,1: The RNG_DR register contains valid random data." rgroup.long 0x8++0x3 line.long 0x0 "RNG_DR,RNG data register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data" group.long 0xC++0x7 line.long 0x0 "RNG_NSCR,RNG noise source control register" bitfld.long 0x0 15.--17. "EN_OSC6,Each bit drives one oscillator enable signal input of instance number 6 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "EN_OSC5,Each bit drives one oscillator enable signal input of instance number 5 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "EN_OSC4,Each bit drives one oscillator enable signal input of instance number 4 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "EN_OSC3,Each bit drives one oscillator enable signal input of instance number 3 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "EN_OSC2,Each bit drives one oscillator enable signal input of instance number 2 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "EN_OSC1,Each bit drives one oscillator enable signal input of instance number 1 gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." "0,1,2,3,4,5,6,7" line.long 0x4 "RNG_HTCR,RNG health test control register" hexmask.long 0x4 0.--31. 1. "HTCFG,health test configuration" tree.end tree.end tree "RTC (Real-Time Clock)" base ad:0x0 tree "RTC" base ad:0x46004000 group.long 0x0++0x7 line.long 0x0 "RTC_TR,RTC time register" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" newline hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "RTC_DR,RTC date register" hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format" hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format" newline bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday" bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" rgroup.long 0x8++0x3 line.long 0x0 "RTC_SSR,RTC subsecond register" hexmask.long 0x0 0.--31. 1. "SS,Synchronous binary counter" group.long 0xC++0x17 line.long 0x0 "RTC_ICSR,RTC initialization control and status register" rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1" bitfld.long 0x0 10.--12. "BCDU,BCD update (BIN = 10 or 11)" "0: 1s calendar increment is generated each time..,1: 1s calendar increment is generated each time..,2: 1s calendar increment is generated each time..,3: 1s calendar increment is generated each time..,4: 1s calendar increment is generated each time..,5: 1s calendar increment is generated each time..,6: 1s calendar increment is generated each time..,7: 1s calendar increment is generated each time.." newline bitfld.long 0x0 8.--9. "BIN,Binary mode" "0: Free running BCD calendar mode (Binary mode..,1: Free running Binary mode (BCD mode disabled),2: Free running BCD calendar and Binary modes,3: Free running BCD calendar and Binary modes" bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.." newline rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed" bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized" newline rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized" rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending" newline rbitfld.long 0x0 2. "WUTWF,Wake-up timer write flag" "0: Wake-up timer configuration update not allowed..,1: Wake-up timer configuration update allowed" line.long 0x4 "RTC_PRER,RTC prescaler register" hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor" hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor" line.long 0x8 "RTC_WUTR,RTC wake-up timer register" hexmask.long.word 0x8 16.--31. 1. "WUTOCLR,Wake-up auto-reload output clear value" hexmask.long.word 0x8 0.--15. 1. "WUT,Wake-up auto-reload value bits" line.long 0xC "RTC_CR,RTC control register" bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0,1" bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output" newline bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output" bitfld.long 0xC 28. "ALRBFCLR,Alarm B flag automatic clear" "0: Alarm B event generates a trigger event and..,1: Alarm B event generates a trigger event. ALRBF.." newline bitfld.long 0xC 27. "ALRAFCLR,Alarm A flag automatic clear" "0: Alarm A event generates a trigger event and..,1: Alarm A event generates a trigger event. ALRAF.." bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.." newline bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event" bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled" newline bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled" bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wake-up output enabled" newline bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.." bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz" newline bitfld.long 0xC 18. "BKP,Backup" "0,1" bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.." newline bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.." bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable" newline bitfld.long 0xC 14. "WUTIE,Wake-up timer interrupt enable" "0: Wake-up timer interrupt disabled,1: Wake-up timer interrupt enabled" bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable" newline bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled" bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable" newline bitfld.long 0xC 10. "WUTE,Wake-up timer enable" "0: Wake-up timer disabled,1: Wake-up timer enabled" bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled" newline bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled" bitfld.long 0xC 7. "SSRUIE,SSR underflow interrupt enable" "0: SSR underflow interrupt disabled,1: SSR underflow interrupt enabled" newline bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format" bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.." newline bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled" bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.." newline bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wake-up clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?" line.long 0x10 "RTC_PRIVCFGR,RTC privilege mode control register" bitfld.long 0x10 15. "PRIV,RTC privilege protection" "0: All RTC registers can be written when the APB..,1: All RTC registers can be written only when the.." bitfld.long 0x10 14. "INITPRIV,Initialization privilege protection" "0: RTC Initialization mode calendar and prescalers..,1: RTC Initialization mode calendar and prescalers.." newline bitfld.long 0x10 13. "CALPRIV,Shift register Delight saving calibration and reference clock privilege protection" "0: Shift register Delight saving calibration and..,1: Shift register Delight saving calibration and.." bitfld.long 0x10 3. "TSPRIV,Timestamp privilege protection" "0: RTC Timestamp configuration and interrupt clear..,1: RTC Timestamp configuration and interrupt clear.." newline bitfld.long 0x10 2. "WUTPRIV,Wake-up timer privilege protection" "0: RTC wake-up timer configuration and interrupt..,1: RTC wake-up timer configuration and interrupt.." bitfld.long 0x10 1. "ALRBPRIV,Alarm B privilege protection" "0: RTC Alarm B configuration and interrupt clear..,1: RTC Alarm B configuration and interrupt clear.." newline bitfld.long 0x10 0. "ALRAPRIV,Alarm A and SSR underflow privilege protection" "0: RTC Alarm A and SSR underflow configuration and..,1: RTC Alarm A and SSR underflow configuration and.." line.long 0x14 "RTC_SECCFGR,RTC secure configuration register" bitfld.long 0x14 15. "SEC,RTC global protection" "0: All RTC registers can be written when the APB..,1: All RTC registers can be written only when the.." bitfld.long 0x14 14. "INITSEC,Initialization protection" "0: RTC Initialization mode calendar and prescalers..,1: RTC Initialization mode calendar and prescalers.." newline bitfld.long 0x14 13. "CALSEC,Shift register daylight saving calibration and reference clock protection" "0: Shift register daylight saving calibration and..,1: Shift register daylight saving calibration and.." bitfld.long 0x14 3. "TSSEC,Timestamp protection" "0: RTC timestamp configuration and interrupt clear..,1: RTC timestamp configuration and interrupt clear.." newline bitfld.long 0x14 2. "WUTSEC,Wake-up timer protection" "0: RTC wake-up timer configuration and interrupt..,1: RTC wake-up timer configuration and interrupt.." bitfld.long 0x14 1. "ALRBSEC,Alarm B protection" "0: RTC alarm B configuration and interrupt clear..,1: RTC alarm B configuration and interrupt clear.." newline bitfld.long 0x14 0. "ALRASEC,Alarm A and SSR underflow protection" "0: RTC alarm A and SSR underflow configuration and..,1: RTC alarm A and SSR underflow configuration and.." wgroup.long 0x24++0x3 line.long 0x0 "RTC_WPR,RTC write protection register" hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key" group.long 0x28++0x3 line.long 0x0 "RTC_CALR,RTC calibration register" bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5 ppm" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every 2.." bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1" newline bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1" bitfld.long 0x0 12. "LPCAL,RTC low-power mode" "0: Calibration window is 2 less than sup>20 less..,1: Calibration window is 2 less than sup>20 less.." newline hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus" wgroup.long 0x2C++0x3 line.long 0x0 "RTC_SHIFTR,RTC shift control register" bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar" hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second" rgroup.long 0x30++0xB line.long 0x0 "RTC_TSTR,RTC timestamp time register" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3" newline hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format." bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format." bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format." line.long 0x4 "RTC_TSDR,RTC timestamp date register" bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" line.long 0x8 "RTC_TSSSR,RTC timestamp subsecond register" hexmask.long 0x8 0.--31. 1. "SS,Subsecond value/synchronous binary counter values" group.long 0x40++0xF line.long 0x0 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison" bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.." newline bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format" newline bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" newline bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison" newline bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format." line.long 0x4 "RTC_ALRMASSR,RTC alarm A subsecond register" bitfld.long 0x4 31. "SSCLR,Clear synchronous counter on alarm (Binary mode only)" "0: The synchronous binary counter (SS[31:0] in..,1: The synchronous binary counter (SS[31:0] in.." hexmask.long.byte 0x4 24.--29. 1. "MASKSS,Mask the most-significant bits starting at this bit" newline hexmask.long.word 0x4 0.--14. 1. "SS,Subseconds value" line.long 0x8 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison" bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.." newline bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format" newline bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison" bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format" newline bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison" bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison" newline bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format" line.long 0xC "RTC_ALRMBSSR,RTC alarm B subsecond register" bitfld.long 0xC 31. "SSCLR,Clear synchronous counter on alarm (Binary mode only)" "0: The synchronous binary counter (SS[31:0] in..,1: The synchronous binary counter (SS[31:0] in.." hexmask.long.byte 0xC 24.--29. 1. "MASKSS,Mask the most-significant bits starting at this bit" newline hexmask.long.word 0xC 0.--14. 1. "SS,Subseconds value" rgroup.long 0x50++0xB line.long 0x0 "RTC_SR,RTC status register" bitfld.long 0x0 6. "SSRUF,SSR underflow flag" "0,1" bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1" newline bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1" bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1" newline bitfld.long 0x0 2. "WUTF,Wake-up timer flag" "0,1" bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1" newline bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1" line.long 0x4 "RTC_MISR,RTC non-secure masked interrupt status register" bitfld.long 0x4 6. "SSRUMF,SSR underflow non-secure masked flag" "0,1" bitfld.long 0x4 5. "ITSMF,Internal timestamp non-secure masked flag" "0,1" newline bitfld.long 0x4 4. "TSOVMF,Timestamp overflow non-secure masked flag" "0,1" bitfld.long 0x4 3. "TSMF,Timestamp non-secure masked flag" "0,1" newline bitfld.long 0x4 2. "WUTMF,Wake-up timer non-secure masked flag" "0,1" bitfld.long 0x4 1. "ALRBMF,Alarm B non-secure masked flag" "0,1" newline bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1" line.long 0x8 "RTC_SMISR,RTC secure masked interrupt status register" bitfld.long 0x8 6. "SSRUMF,SSR underflow secure masked flag" "0,1" bitfld.long 0x8 5. "ITSMF,Internal timestamp interrupt secure masked flag" "0,1" newline bitfld.long 0x8 4. "TSOVMF,Timestamp overflow interrupt secure masked flag" "0,1" bitfld.long 0x8 3. "TSMF,Timestamp interrupt secure masked flag" "0,1" newline bitfld.long 0x8 2. "WUTMF,Wake-up timer interrupt secure masked flag" "0,1" bitfld.long 0x8 1. "ALRBMF,Alarm B interrupt secure masked flag" "0,1" newline bitfld.long 0x8 0. "ALRAMF,Alarm A interrupt secure masked flag" "0,1" wgroup.long 0x5C++0x3 line.long 0x0 "RTC_SCR,RTC status clear register" bitfld.long 0x0 6. "CSSRUF,Clear SSR underflow flag" "0,1" bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1" newline bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1" bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1" newline bitfld.long 0x0 2. "CWUTF,Clear wake-up timer flag" "0,1" bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1" newline bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1" group.long 0x70++0x7 line.long 0x0 "RTC_ALRABINR,RTC alarm A binary mode register" hexmask.long 0x0 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode" line.long 0x4 "RTC_ALRBBINR,RTC alarm B binary mode register" hexmask.long 0x4 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode" tree.end tree "RTC_S" base ad:0x56004000 group.long 0x0++0x7 line.long 0x0 "RTC_TR,RTC time register" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" newline hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "RTC_DR,RTC date register" hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format" hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format" newline bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday" bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" rgroup.long 0x8++0x3 line.long 0x0 "RTC_SSR,RTC subsecond register" hexmask.long 0x0 0.--31. 1. "SS,Synchronous binary counter" group.long 0xC++0x17 line.long 0x0 "RTC_ICSR,RTC initialization control and status register" rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1" bitfld.long 0x0 10.--12. "BCDU,BCD update (BIN = 10 or 11)" "0: 1s calendar increment is generated each time..,1: 1s calendar increment is generated each time..,2: 1s calendar increment is generated each time..,3: 1s calendar increment is generated each time..,4: 1s calendar increment is generated each time..,5: 1s calendar increment is generated each time..,6: 1s calendar increment is generated each time..,7: 1s calendar increment is generated each time.." newline bitfld.long 0x0 8.--9. "BIN,Binary mode" "0: Free running BCD calendar mode (Binary mode..,1: Free running Binary mode (BCD mode disabled),2: Free running BCD calendar and Binary modes,3: Free running BCD calendar and Binary modes" bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.." newline rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed" bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized" newline rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized" rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending" newline rbitfld.long 0x0 2. "WUTWF,Wake-up timer write flag" "0: Wake-up timer configuration update not allowed..,1: Wake-up timer configuration update allowed" line.long 0x4 "RTC_PRER,RTC prescaler register" hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor" hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor" line.long 0x8 "RTC_WUTR,RTC wake-up timer register" hexmask.long.word 0x8 16.--31. 1. "WUTOCLR,Wake-up auto-reload output clear value" hexmask.long.word 0x8 0.--15. 1. "WUT,Wake-up auto-reload value bits" line.long 0xC "RTC_CR,RTC control register" bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0,1" bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output" newline bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output" bitfld.long 0xC 28. "ALRBFCLR,Alarm B flag automatic clear" "0: Alarm B event generates a trigger event and..,1: Alarm B event generates a trigger event. ALRBF.." newline bitfld.long 0xC 27. "ALRAFCLR,Alarm A flag automatic clear" "0: Alarm A event generates a trigger event and..,1: Alarm A event generates a trigger event. ALRAF.." bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.." newline bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event" bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled" newline bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled" bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wake-up output enabled" newline bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.." bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz" newline bitfld.long 0xC 18. "BKP,Backup" "0,1" bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.." newline bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.." bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable" newline bitfld.long 0xC 14. "WUTIE,Wake-up timer interrupt enable" "0: Wake-up timer interrupt disabled,1: Wake-up timer interrupt enabled" bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable" newline bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled" bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable" newline bitfld.long 0xC 10. "WUTE,Wake-up timer enable" "0: Wake-up timer disabled,1: Wake-up timer enabled" bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled" newline bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled" bitfld.long 0xC 7. "SSRUIE,SSR underflow interrupt enable" "0: SSR underflow interrupt disabled,1: SSR underflow interrupt enabled" newline bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format" bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.." newline bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled" bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.." newline bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wake-up clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?" line.long 0x10 "RTC_PRIVCFGR,RTC privilege mode control register" bitfld.long 0x10 15. "PRIV,RTC privilege protection" "0: All RTC registers can be written when the APB..,1: All RTC registers can be written only when the.." bitfld.long 0x10 14. "INITPRIV,Initialization privilege protection" "0: RTC Initialization mode calendar and prescalers..,1: RTC Initialization mode calendar and prescalers.." newline bitfld.long 0x10 13. "CALPRIV,Shift register Delight saving calibration and reference clock privilege protection" "0: Shift register Delight saving calibration and..,1: Shift register Delight saving calibration and.." bitfld.long 0x10 3. "TSPRIV,Timestamp privilege protection" "0: RTC Timestamp configuration and interrupt clear..,1: RTC Timestamp configuration and interrupt clear.." newline bitfld.long 0x10 2. "WUTPRIV,Wake-up timer privilege protection" "0: RTC wake-up timer configuration and interrupt..,1: RTC wake-up timer configuration and interrupt.." bitfld.long 0x10 1. "ALRBPRIV,Alarm B privilege protection" "0: RTC Alarm B configuration and interrupt clear..,1: RTC Alarm B configuration and interrupt clear.." newline bitfld.long 0x10 0. "ALRAPRIV,Alarm A and SSR underflow privilege protection" "0: RTC Alarm A and SSR underflow configuration and..,1: RTC Alarm A and SSR underflow configuration and.." line.long 0x14 "RTC_SECCFGR,RTC secure configuration register" bitfld.long 0x14 15. "SEC,RTC global protection" "0: All RTC registers can be written when the APB..,1: All RTC registers can be written only when the.." bitfld.long 0x14 14. "INITSEC,Initialization protection" "0: RTC Initialization mode calendar and prescalers..,1: RTC Initialization mode calendar and prescalers.." newline bitfld.long 0x14 13. "CALSEC,Shift register daylight saving calibration and reference clock protection" "0: Shift register daylight saving calibration and..,1: Shift register daylight saving calibration and.." bitfld.long 0x14 3. "TSSEC,Timestamp protection" "0: RTC timestamp configuration and interrupt clear..,1: RTC timestamp configuration and interrupt clear.." newline bitfld.long 0x14 2. "WUTSEC,Wake-up timer protection" "0: RTC wake-up timer configuration and interrupt..,1: RTC wake-up timer configuration and interrupt.." bitfld.long 0x14 1. "ALRBSEC,Alarm B protection" "0: RTC alarm B configuration and interrupt clear..,1: RTC alarm B configuration and interrupt clear.." newline bitfld.long 0x14 0. "ALRASEC,Alarm A and SSR underflow protection" "0: RTC alarm A and SSR underflow configuration and..,1: RTC alarm A and SSR underflow configuration and.." wgroup.long 0x24++0x3 line.long 0x0 "RTC_WPR,RTC write protection register" hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key" group.long 0x28++0x3 line.long 0x0 "RTC_CALR,RTC calibration register" bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5 ppm" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every 2.." bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1" newline bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1" bitfld.long 0x0 12. "LPCAL,RTC low-power mode" "0: Calibration window is 2 less than sup>20 less..,1: Calibration window is 2 less than sup>20 less.." newline hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus" wgroup.long 0x2C++0x3 line.long 0x0 "RTC_SHIFTR,RTC shift control register" bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar" hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second" rgroup.long 0x30++0xB line.long 0x0 "RTC_TSTR,RTC timestamp time register" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3" newline hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format." bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format." bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format." line.long 0x4 "RTC_TSDR,RTC timestamp date register" bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" line.long 0x8 "RTC_TSSSR,RTC timestamp subsecond register" hexmask.long 0x8 0.--31. 1. "SS,Subsecond value/synchronous binary counter values" group.long 0x40++0xF line.long 0x0 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison" bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.." newline bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format" newline bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" newline bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison" newline bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format." line.long 0x4 "RTC_ALRMASSR,RTC alarm A subsecond register" bitfld.long 0x4 31. "SSCLR,Clear synchronous counter on alarm (Binary mode only)" "0: The synchronous binary counter (SS[31:0] in..,1: The synchronous binary counter (SS[31:0] in.." hexmask.long.byte 0x4 24.--29. 1. "MASKSS,Mask the most-significant bits starting at this bit" newline hexmask.long.word 0x4 0.--14. 1. "SS,Subseconds value" line.long 0x8 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison" bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.." newline bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format" newline bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison" bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format" newline bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison" bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison" newline bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format" line.long 0xC "RTC_ALRMBSSR,RTC alarm B subsecond register" bitfld.long 0xC 31. "SSCLR,Clear synchronous counter on alarm (Binary mode only)" "0: The synchronous binary counter (SS[31:0] in..,1: The synchronous binary counter (SS[31:0] in.." hexmask.long.byte 0xC 24.--29. 1. "MASKSS,Mask the most-significant bits starting at this bit" newline hexmask.long.word 0xC 0.--14. 1. "SS,Subseconds value" rgroup.long 0x50++0xB line.long 0x0 "RTC_SR,RTC status register" bitfld.long 0x0 6. "SSRUF,SSR underflow flag" "0,1" bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1" newline bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1" bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1" newline bitfld.long 0x0 2. "WUTF,Wake-up timer flag" "0,1" bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1" newline bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1" line.long 0x4 "RTC_MISR,RTC non-secure masked interrupt status register" bitfld.long 0x4 6. "SSRUMF,SSR underflow non-secure masked flag" "0,1" bitfld.long 0x4 5. "ITSMF,Internal timestamp non-secure masked flag" "0,1" newline bitfld.long 0x4 4. "TSOVMF,Timestamp overflow non-secure masked flag" "0,1" bitfld.long 0x4 3. "TSMF,Timestamp non-secure masked flag" "0,1" newline bitfld.long 0x4 2. "WUTMF,Wake-up timer non-secure masked flag" "0,1" bitfld.long 0x4 1. "ALRBMF,Alarm B non-secure masked flag" "0,1" newline bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1" line.long 0x8 "RTC_SMISR,RTC secure masked interrupt status register" bitfld.long 0x8 6. "SSRUMF,SSR underflow secure masked flag" "0,1" bitfld.long 0x8 5. "ITSMF,Internal timestamp interrupt secure masked flag" "0,1" newline bitfld.long 0x8 4. "TSOVMF,Timestamp overflow interrupt secure masked flag" "0,1" bitfld.long 0x8 3. "TSMF,Timestamp interrupt secure masked flag" "0,1" newline bitfld.long 0x8 2. "WUTMF,Wake-up timer interrupt secure masked flag" "0,1" bitfld.long 0x8 1. "ALRBMF,Alarm B interrupt secure masked flag" "0,1" newline bitfld.long 0x8 0. "ALRAMF,Alarm A interrupt secure masked flag" "0,1" wgroup.long 0x5C++0x3 line.long 0x0 "RTC_SCR,RTC status clear register" bitfld.long 0x0 6. "CSSRUF,Clear SSR underflow flag" "0,1" bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1" newline bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1" bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1" newline bitfld.long 0x0 2. "CWUTF,Clear wake-up timer flag" "0,1" bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1" newline bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1" group.long 0x70++0x7 line.long 0x0 "RTC_ALRABINR,RTC alarm A binary mode register" hexmask.long 0x0 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode" line.long 0x4 "RTC_ALRBBINR,RTC alarm B binary mode register" hexmask.long 0x4 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode" tree.end tree.end sif (cpuis("STM32N655*")||cpuis("STM32N657*")) tree "SAES (Secure AES Coprocessor)" base ad:0x0 tree "SAES" base ad:0x44021000 group.long 0x0++0x3 line.long 0x0 "SAES_CR,SAES control register" bitfld.long 0x0 31. "IPRST,SAES peripheral software reset" "0,1" bitfld.long 0x0 28.--30. "KEYSEL,Key selection" "0: Software key loaded in key registers SAES_KEYx,1: Derived hardware unique key (DHUK),2: Boot hardware key (BHK),?,4: XOR of DHUK and BHK,?,?,7: Test mode key (256-bit hardware constant.." newline bitfld.long 0x0 26.--27. "KSHAREID,Key share identification" "0: CRYP peripheral,?,?,?" bitfld.long 0x0 24.--25. "KMOD,Key mode selection" "0: Normal key mode. Key registers are freely usable..,1: Wrapped key mode. Key loaded in key registers..,2: Shared key mode. After a successful decryption..,?" newline hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block" bitfld.long 0x0 19. "KEYPROT,Key protection" "0: When KEYVALID is set and KEYSEL[2:0] = 0..,1: When KEYVALID is set key error flag (KEIF) is.." newline bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0: 128-bit,1: 256-bit" bitfld.long 0x0 16. "CHMOD_1,CHMOD[2]" "0,1" newline bitfld.long 0x0 13.--14. "GCMPH,GCM or CCM phase selection" "0: Initialization phase,1: Header phase,2: Payload phase,3: Final phase" bitfld.long 0x0 12. "DMAOUTEN,DMA output enable" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "DMAINEN,DMA input enable" "0: Disable,1: Enable" bitfld.long 0x0 5.--6. "CHMOD,CHMOD[1:0]: Chaining mode" "0: Electronic codebook (ECB),1: Cipher-block chaining (CBC),2: Counter mode (CTR),3: Galois counter mode (GCM) and Galois message.." newline bitfld.long 0x0 3.--4. "MODE,Operating mode" "0: Encryption,1: Key derivation (or key preparation) for ECB/CBC..,2: Decryption,?" bitfld.long 0x0 1.--2. "DATATYPE,Data type" "0: No swapping (32-bit data).,1: Half-word swapping (16-bit data),2: Byte swapping (8-bit data),3: Bit-level swapping" newline bitfld.long 0x0 0. "EN,Enable" "0: Disable,1: Enable" rgroup.long 0x4++0x3 line.long 0x0 "SAES_SR,SAES status register" bitfld.long 0x0 7. "KEYVALID,Key valid flag" "0: Key not valid,1: Key valid" bitfld.long 0x0 3. "BUSY,Busy" "0: Idle,1: Busy" newline bitfld.long 0x0 2. "WRERRF,Write error flag" "0: No error,1: Unexpected write to SAES_DINR register occurred.." bitfld.long 0x0 1. "RDERRF,Read error flag" "0: No error,1: Unexpected read to SAES_DOUTR register occurred.." wgroup.long 0x8++0x3 line.long 0x0 "SAES_DINR,SAES data input register" hexmask.long 0x0 0.--31. 1. "DIN,Data input" rgroup.long 0xC++0x3 line.long 0x0 "SAES_DOUTR,SAES data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Data output" wgroup.long 0x10++0xF line.long 0x0 "SAES_KEYR0,SAES key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "SAES_KEYR1,SAES key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "SAES_KEYR2,SAES key register 2" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [95:64]" line.long 0xC "SAES_KEYR3,SAES key register 3" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "SAES_IVR0,SAES initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "SAES_IVR1,SAES initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "SAES_IVR2,SAES initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "SAES_IVR3,SAES initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0xF line.long 0x0 "SAES_KEYR4,SAES key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "SAES_KEYR5,SAES key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "SAES_KEYR6,SAES key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "SAES_KEYR7,SAES key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" group.long 0x40++0x1F line.long 0x0 "SAES_SUSPR0,SAES suspend registers" hexmask.long 0x0 0.--31. 1. "SUSP,Suspend data" line.long 0x4 "SAES_SUSPR1,SAES suspend registers" hexmask.long 0x4 0.--31. 1. "SUSP,Suspend data" line.long 0x8 "SAES_SUSPR2,SAES suspend registers" hexmask.long 0x8 0.--31. 1. "SUSP,Suspend data" line.long 0xC "SAES_SUSPR3,SAES suspend registers" hexmask.long 0xC 0.--31. 1. "SUSP,Suspend data" line.long 0x10 "SAES_SUSPR4,SAES suspend registers" hexmask.long 0x10 0.--31. 1. "SUSP,Suspend data" line.long 0x14 "SAES_SUSPR5,SAES suspend registers" hexmask.long 0x14 0.--31. 1. "SUSP,Suspend data" line.long 0x18 "SAES_SUSPR6,SAES suspend registers" hexmask.long 0x18 0.--31. 1. "SUSP,Suspend data" line.long 0x1C "SAES_SUSPR7,SAES suspend registers" hexmask.long 0x1C 0.--31. 1. "SUSP,Suspend data" group.long 0x300++0x3 line.long 0x0 "SAES_IER,SAES interrupt enable register" bitfld.long 0x0 3. "RNGEIE,RNG error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" bitfld.long 0x0 2. "KEIE,Key error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" newline bitfld.long 0x0 1. "RWEIE,Read or write error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" bitfld.long 0x0 0. "CCFIE,Computation complete flag interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" rgroup.long 0x304++0x3 line.long 0x0 "SAES_ISR,SAES interrupt status register" bitfld.long 0x0 3. "RNGEIF,RNG error interrupt flag" "0: RNG bus is functional,1: Error detected on RNG bus interface (random seed.." bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0: No key error detected,1: Key information failed to load into key.." newline bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0: No read or write error detected,1: Read or write error detected" bitfld.long 0x0 0. "CCF,Computation complete flag" "0: Not completed,1: Completed" wgroup.long 0x308++0x3 line.long 0x0 "SAES_ICR,SAES interrupt clear register" bitfld.long 0x0 3. "RNGEIF,RNG error interrupt flag clear" "0,1" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" newline bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end tree "SAES_S" base ad:0x54021000 group.long 0x0++0x3 line.long 0x0 "SAES_CR,SAES control register" bitfld.long 0x0 31. "IPRST,SAES peripheral software reset" "0,1" bitfld.long 0x0 28.--30. "KEYSEL,Key selection" "0: Software key loaded in key registers SAES_KEYx,1: Derived hardware unique key (DHUK),2: Boot hardware key (BHK),?,4: XOR of DHUK and BHK,?,?,7: Test mode key (256-bit hardware constant.." newline bitfld.long 0x0 26.--27. "KSHAREID,Key share identification" "0: CRYP peripheral,?,?,?" bitfld.long 0x0 24.--25. "KMOD,Key mode selection" "0: Normal key mode. Key registers are freely usable..,1: Wrapped key mode. Key loaded in key registers..,2: Shared key mode. After a successful decryption..,?" newline hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block" bitfld.long 0x0 19. "KEYPROT,Key protection" "0: When KEYVALID is set and KEYSEL[2:0] = 0..,1: When KEYVALID is set key error flag (KEIF) is.." newline bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0: 128-bit,1: 256-bit" bitfld.long 0x0 16. "CHMOD_1,CHMOD[2]" "0,1" newline bitfld.long 0x0 13.--14. "GCMPH,GCM or CCM phase selection" "0: Initialization phase,1: Header phase,2: Payload phase,3: Final phase" bitfld.long 0x0 12. "DMAOUTEN,DMA output enable" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "DMAINEN,DMA input enable" "0: Disable,1: Enable" bitfld.long 0x0 5.--6. "CHMOD,CHMOD[1:0]: Chaining mode" "0: Electronic codebook (ECB),1: Cipher-block chaining (CBC),2: Counter mode (CTR),3: Galois counter mode (GCM) and Galois message.." newline bitfld.long 0x0 3.--4. "MODE,Operating mode" "0: Encryption,1: Key derivation (or key preparation) for ECB/CBC..,2: Decryption,?" bitfld.long 0x0 1.--2. "DATATYPE,Data type" "0: No swapping (32-bit data).,1: Half-word swapping (16-bit data),2: Byte swapping (8-bit data),3: Bit-level swapping" newline bitfld.long 0x0 0. "EN,Enable" "0: Disable,1: Enable" rgroup.long 0x4++0x3 line.long 0x0 "SAES_SR,SAES status register" bitfld.long 0x0 7. "KEYVALID,Key valid flag" "0: Key not valid,1: Key valid" bitfld.long 0x0 3. "BUSY,Busy" "0: Idle,1: Busy" newline bitfld.long 0x0 2. "WRERRF,Write error flag" "0: No error,1: Unexpected write to SAES_DINR register occurred.." bitfld.long 0x0 1. "RDERRF,Read error flag" "0: No error,1: Unexpected read to SAES_DOUTR register occurred.." wgroup.long 0x8++0x3 line.long 0x0 "SAES_DINR,SAES data input register" hexmask.long 0x0 0.--31. 1. "DIN,Data input" rgroup.long 0xC++0x3 line.long 0x0 "SAES_DOUTR,SAES data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Data output" wgroup.long 0x10++0xF line.long 0x0 "SAES_KEYR0,SAES key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "SAES_KEYR1,SAES key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "SAES_KEYR2,SAES key register 2" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [95:64]" line.long 0xC "SAES_KEYR3,SAES key register 3" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "SAES_IVR0,SAES initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "SAES_IVR1,SAES initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "SAES_IVR2,SAES initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "SAES_IVR3,SAES initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0xF line.long 0x0 "SAES_KEYR4,SAES key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "SAES_KEYR5,SAES key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "SAES_KEYR6,SAES key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "SAES_KEYR7,SAES key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" group.long 0x40++0x1F line.long 0x0 "SAES_SUSPR0,SAES suspend registers" hexmask.long 0x0 0.--31. 1. "SUSP,Suspend data" line.long 0x4 "SAES_SUSPR1,SAES suspend registers" hexmask.long 0x4 0.--31. 1. "SUSP,Suspend data" line.long 0x8 "SAES_SUSPR2,SAES suspend registers" hexmask.long 0x8 0.--31. 1. "SUSP,Suspend data" line.long 0xC "SAES_SUSPR3,SAES suspend registers" hexmask.long 0xC 0.--31. 1. "SUSP,Suspend data" line.long 0x10 "SAES_SUSPR4,SAES suspend registers" hexmask.long 0x10 0.--31. 1. "SUSP,Suspend data" line.long 0x14 "SAES_SUSPR5,SAES suspend registers" hexmask.long 0x14 0.--31. 1. "SUSP,Suspend data" line.long 0x18 "SAES_SUSPR6,SAES suspend registers" hexmask.long 0x18 0.--31. 1. "SUSP,Suspend data" line.long 0x1C "SAES_SUSPR7,SAES suspend registers" hexmask.long 0x1C 0.--31. 1. "SUSP,Suspend data" group.long 0x300++0x3 line.long 0x0 "SAES_IER,SAES interrupt enable register" bitfld.long 0x0 3. "RNGEIE,RNG error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" bitfld.long 0x0 2. "KEIE,Key error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" newline bitfld.long 0x0 1. "RWEIE,Read or write error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" bitfld.long 0x0 0. "CCFIE,Computation complete flag interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" rgroup.long 0x304++0x3 line.long 0x0 "SAES_ISR,SAES interrupt status register" bitfld.long 0x0 3. "RNGEIF,RNG error interrupt flag" "0: RNG bus is functional,1: Error detected on RNG bus interface (random seed.." bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0: No key error detected,1: Key information failed to load into key.." newline bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0: No read or write error detected,1: Read or write error detected" bitfld.long 0x0 0. "CCF,Computation complete flag" "0: Not completed,1: Completed" wgroup.long 0x308++0x3 line.long 0x0 "SAES_ICR,SAES interrupt clear register" bitfld.long 0x0 3. "RNGEIF,RNG error interrupt flag clear" "0,1" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" newline bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" tree.end tree.end endif tree "SAI (Serial Audio Interface)" base ad:0x0 tree "SAI1" base ad:0x42005800 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,SAI global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0: No synchronization output signals. SYNCOUT[1:0]..,1: Block A used for further synchronization for..,2: Block B used for further synchronization for..,?" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization outputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,SAI configuration register 1" bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.." bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F less than sub>FS less..,1: Master clock frequency = F less than sub>FS less.." newline hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.." newline bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled" bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled." newline bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.." bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode." newline bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,?" bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.." newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first" bitfld.long 0x4 5.--7. "DS,Data size" "?,?,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits" newline bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC'97 protocol,?" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver" line.long 0x8 "SAI_ACR2,SAI configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,?,2: -Law algorithm,3: A-Law algorithm" bitfld.long 0x8 13. "CPL,Complement bit." "0: 1's complement representation.,1: 2's complement representation." newline hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter." bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode." newline bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled." bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.." newline bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.." bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,?,?,?" line.long 0xC "SAI_AFRCR,SAI frame configuration register" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.." bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)" newline rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.." hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length." newline hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length." line.long 0x10 "SAI_ASLOTR,SAI slot register" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable." hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame." newline bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,?" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset" line.long 0x14 "SAI_AIM,SAI interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC'97)." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,SAI status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO less than or equal 1/4 but not empty..,2: 1/4 less than FIFO less than or equal half..,3: half less than FIFO less than or equal 3/4..,4: 3/4 less than FIFO but not full (transmitter..,5: FIFO full (transmitter and receiver modes),?,?" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.." newline bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.." bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC'97 Codec is ready,1: External AC'97 Codec is not ready" newline bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR." bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.." newline bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.." bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection." wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,SAI clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1" newline bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" newline bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,SAI data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "SAI_BCR1,SAI configuration register 1" bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.." bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F less than sub>FS less..,1: Master clock frequency = F less than sub>FS less.." newline hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.." newline bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled" bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled." newline bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.." bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode." newline bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,?" bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.." newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first" bitfld.long 0x4 5.--7. "DS,Data size" "?,?,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits" newline bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC'97 protocol,?" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver" line.long 0x8 "SAI_BCR2,SAI configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,?,2: -Law algorithm,3: A-Law algorithm" bitfld.long 0x8 13. "CPL,Complement bit." "0: 1's complement representation.,1: 2's complement representation." newline hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter." bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode." newline bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled." bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.." newline bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.." bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,?,?,?" line.long 0xC "SAI_BFRCR,SAI frame configuration register" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.." bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)" newline rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.." hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length." newline hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length." line.long 0x10 "SAI_BSLOTR,SAI slot register" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable." hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame." newline bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,?" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset" line.long 0x14 "SAI_BIM,SAI interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC'97)." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,SAI status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO less than or equal 1/4 but not empty..,2: 1/4 less than FIFO less than or equal half..,3: half less than FIFO less than or equal 3/4..,4: 3/4 less than FIFO but not full (transmitter..,5: FIFO full (transmitter and receiver modes),?,?" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.." newline bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.." bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC'97 Codec is ready,1: External AC'97 Codec is not ready" newline bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR." bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.." newline bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.." bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection." wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,SAI clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1" newline bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" newline bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,SAI data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "SAI_PDMCR,SAI PDM control register" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number 2" "0: SAI_CK2 clock disabled,1: SAI_CK2 clock enabled" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number 1" "0: SAI_CK1 clock disabled,1: SAI_CK1 clock enabled" newline bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0: Configuration with 2 microphones,1: Configuration with 4 microphones,2: Configuration with 6 microphones,3: Configuration with 8 microphones" bitfld.long 0x4 0. "PDMEN,PDM enable" "0: PDM interface disabled,1: PDM interface enabled" line.long 0x8 "SAI_PDMDLY,SAI PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair 4" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair 4" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 of T less than sub>SAI_CK less than.." newline bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair 3" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair 3" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." newline bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair 2" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair 2" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." newline bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone of pair 1" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone of pair 1" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." tree.end tree "SAI1_S" base ad:0x52005800 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,SAI global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0: No synchronization output signals. SYNCOUT[1:0]..,1: Block A used for further synchronization for..,2: Block B used for further synchronization for..,?" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization outputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,SAI configuration register 1" bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.." bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F less than sub>FS less..,1: Master clock frequency = F less than sub>FS less.." newline hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.." newline bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled" bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled." newline bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.." bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode." newline bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,?" bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.." newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first" bitfld.long 0x4 5.--7. "DS,Data size" "?,?,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits" newline bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC'97 protocol,?" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver" line.long 0x8 "SAI_ACR2,SAI configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,?,2: -Law algorithm,3: A-Law algorithm" bitfld.long 0x8 13. "CPL,Complement bit." "0: 1's complement representation.,1: 2's complement representation." newline hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter." bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode." newline bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled." bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.." newline bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.." bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,?,?,?" line.long 0xC "SAI_AFRCR,SAI frame configuration register" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.." bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)" newline rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.." hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length." newline hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length." line.long 0x10 "SAI_ASLOTR,SAI slot register" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable." hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame." newline bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,?" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset" line.long 0x14 "SAI_AIM,SAI interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC'97)." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,SAI status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO less than or equal 1/4 but not empty..,2: 1/4 less than FIFO less than or equal half..,3: half less than FIFO less than or equal 3/4..,4: 3/4 less than FIFO but not full (transmitter..,5: FIFO full (transmitter and receiver modes),?,?" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.." newline bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.." bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC'97 Codec is ready,1: External AC'97 Codec is not ready" newline bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR." bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.." newline bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.." bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection." wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,SAI clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1" newline bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" newline bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,SAI data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "SAI_BCR1,SAI configuration register 1" bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.." bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F less than sub>FS less..,1: Master clock frequency = F less than sub>FS less.." newline hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.." newline bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled" bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled." newline bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.." bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode." newline bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,?" bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.." newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first" bitfld.long 0x4 5.--7. "DS,Data size" "?,?,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits" newline bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC'97 protocol,?" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver" line.long 0x8 "SAI_BCR2,SAI configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,?,2: -Law algorithm,3: A-Law algorithm" bitfld.long 0x8 13. "CPL,Complement bit." "0: 1's complement representation.,1: 2's complement representation." newline hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter." bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode." newline bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled." bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.." newline bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.." bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,?,?,?" line.long 0xC "SAI_BFRCR,SAI frame configuration register" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.." bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)" newline rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.." hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length." newline hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length." line.long 0x10 "SAI_BSLOTR,SAI slot register" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable." hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame." newline bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,?" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset" line.long 0x14 "SAI_BIM,SAI interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC'97)." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,SAI status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO less than or equal 1/4 but not empty..,2: 1/4 less than FIFO less than or equal half..,3: half less than FIFO less than or equal 3/4..,4: 3/4 less than FIFO but not full (transmitter..,5: FIFO full (transmitter and receiver modes),?,?" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.." newline bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.." bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC'97 Codec is ready,1: External AC'97 Codec is not ready" newline bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR." bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.." newline bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.." bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection." wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,SAI clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1" newline bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" newline bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,SAI data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "SAI_PDMCR,SAI PDM control register" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number 2" "0: SAI_CK2 clock disabled,1: SAI_CK2 clock enabled" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number 1" "0: SAI_CK1 clock disabled,1: SAI_CK1 clock enabled" newline bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0: Configuration with 2 microphones,1: Configuration with 4 microphones,2: Configuration with 6 microphones,3: Configuration with 8 microphones" bitfld.long 0x4 0. "PDMEN,PDM enable" "0: PDM interface disabled,1: PDM interface enabled" line.long 0x8 "SAI_PDMDLY,SAI PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair 4" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair 4" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 of T less than sub>SAI_CK less than.." newline bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair 3" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair 3" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." newline bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair 2" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair 2" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." newline bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone of pair 1" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone of pair 1" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." tree.end tree "SAI2" base ad:0x42005C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,SAI global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0: No synchronization output signals. SYNCOUT[1:0]..,1: Block A used for further synchronization for..,2: Block B used for further synchronization for..,?" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization outputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,SAI configuration register 1" bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.." bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F less than sub>FS less..,1: Master clock frequency = F less than sub>FS less.." newline hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.." newline bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled" bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled." newline bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.." bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode." newline bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,?" bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.." newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first" bitfld.long 0x4 5.--7. "DS,Data size" "?,?,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits" newline bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC'97 protocol,?" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver" line.long 0x8 "SAI_ACR2,SAI configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,?,2: -Law algorithm,3: A-Law algorithm" bitfld.long 0x8 13. "CPL,Complement bit." "0: 1's complement representation.,1: 2's complement representation." newline hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter." bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode." newline bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled." bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.." newline bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.." bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,?,?,?" line.long 0xC "SAI_AFRCR,SAI frame configuration register" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.." bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)" newline rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.." hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length." newline hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length." line.long 0x10 "SAI_ASLOTR,SAI slot register" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable." hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame." newline bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,?" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset" line.long 0x14 "SAI_AIM,SAI interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC'97)." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,SAI status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO less than or equal 1/4 but not empty..,2: 1/4 less than FIFO less than or equal half..,3: half less than FIFO less than or equal 3/4..,4: 3/4 less than FIFO but not full (transmitter..,5: FIFO full (transmitter and receiver modes),?,?" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.." newline bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.." bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC'97 Codec is ready,1: External AC'97 Codec is not ready" newline bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR." bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.." newline bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.." bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection." wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,SAI clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1" newline bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" newline bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,SAI data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "SAI_BCR1,SAI configuration register 1" bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.." bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F less than sub>FS less..,1: Master clock frequency = F less than sub>FS less.." newline hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.." newline bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled" bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled." newline bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.." bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode." newline bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,?" bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.." newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first" bitfld.long 0x4 5.--7. "DS,Data size" "?,?,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits" newline bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC'97 protocol,?" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver" line.long 0x8 "SAI_BCR2,SAI configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,?,2: -Law algorithm,3: A-Law algorithm" bitfld.long 0x8 13. "CPL,Complement bit." "0: 1's complement representation.,1: 2's complement representation." newline hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter." bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode." newline bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled." bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.." newline bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.." bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,?,?,?" line.long 0xC "SAI_BFRCR,SAI frame configuration register" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.." bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)" newline rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.." hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length." newline hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length." line.long 0x10 "SAI_BSLOTR,SAI slot register" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable." hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame." newline bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,?" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset" line.long 0x14 "SAI_BIM,SAI interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC'97)." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,SAI status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO less than or equal 1/4 but not empty..,2: 1/4 less than FIFO less than or equal half..,3: half less than FIFO less than or equal 3/4..,4: 3/4 less than FIFO but not full (transmitter..,5: FIFO full (transmitter and receiver modes),?,?" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.." newline bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.." bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC'97 Codec is ready,1: External AC'97 Codec is not ready" newline bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR." bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.." newline bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.." bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection." wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,SAI clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1" newline bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" newline bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,SAI data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "SAI_PDMCR,SAI PDM control register" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number 2" "0: SAI_CK2 clock disabled,1: SAI_CK2 clock enabled" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number 1" "0: SAI_CK1 clock disabled,1: SAI_CK1 clock enabled" newline bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0: Configuration with 2 microphones,1: Configuration with 4 microphones,2: Configuration with 6 microphones,3: Configuration with 8 microphones" bitfld.long 0x4 0. "PDMEN,PDM enable" "0: PDM interface disabled,1: PDM interface enabled" line.long 0x8 "SAI_PDMDLY,SAI PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair 4" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair 4" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 of T less than sub>SAI_CK less than.." newline bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair 3" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair 3" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." newline bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair 2" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair 2" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." newline bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone of pair 1" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone of pair 1" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." tree.end tree "SAI2_S" base ad:0x52005C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,SAI global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0: No synchronization output signals. SYNCOUT[1:0]..,1: Block A used for further synchronization for..,2: Block B used for further synchronization for..,?" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization outputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,SAI configuration register 1" bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.." bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F less than sub>FS less..,1: Master clock frequency = F less than sub>FS less.." newline hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.." newline bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled" bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled." newline bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.." bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode." newline bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,?" bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.." newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first" bitfld.long 0x4 5.--7. "DS,Data size" "?,?,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits" newline bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC'97 protocol,?" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver" line.long 0x8 "SAI_ACR2,SAI configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,?,2: -Law algorithm,3: A-Law algorithm" bitfld.long 0x8 13. "CPL,Complement bit." "0: 1's complement representation.,1: 2's complement representation." newline hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter." bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode." newline bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled." bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.." newline bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.." bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,?,?,?" line.long 0xC "SAI_AFRCR,SAI frame configuration register" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.." bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)" newline rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.." hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length." newline hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length." line.long 0x10 "SAI_ASLOTR,SAI slot register" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable." hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame." newline bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,?" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset" line.long 0x14 "SAI_AIM,SAI interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC'97)." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,SAI status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO less than or equal 1/4 but not empty..,2: 1/4 less than FIFO less than or equal half..,3: half less than FIFO less than or equal 3/4..,4: 3/4 less than FIFO but not full (transmitter..,5: FIFO full (transmitter and receiver modes),?,?" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.." newline bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.." bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC'97 Codec is ready,1: External AC'97 Codec is not ready" newline bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR." bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.." newline bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.." bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection." wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,SAI clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1" newline bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" newline bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,SAI data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "SAI_BCR1,SAI configuration register 1" bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.." bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F less than sub>FS less..,1: Master clock frequency = F less than sub>FS less.." newline hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider" bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.." newline bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled" bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled." newline bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.." bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode." newline bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,?" bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.." newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first" bitfld.long 0x4 5.--7. "DS,Data size" "?,?,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits" newline bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC'97 protocol,?" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver" line.long 0x8 "SAI_BCR2,SAI configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,?,2: -Law algorithm,3: A-Law algorithm" bitfld.long 0x8 13. "CPL,Complement bit." "0: 1's complement representation.,1: 2's complement representation." newline hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter." bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode." newline bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled." bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.." newline bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.." bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,?,?,?" line.long 0xC "SAI_BFRCR,SAI frame configuration register" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.." bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)" newline rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.." hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length." newline hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length." line.long 0x10 "SAI_BSLOTR,SAI slot register" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable." hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame." newline bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,?" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset" line.long 0x14 "SAI_BIM,SAI interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC'97)." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,SAI status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO less than or equal 1/4 but not empty..,2: 1/4 less than FIFO less than or equal half..,3: half less than FIFO less than or equal 3/4..,4: 3/4 less than FIFO but not full (transmitter..,5: FIFO full (transmitter and receiver modes),?,?" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.." newline bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.." bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC'97 Codec is ready,1: External AC'97 Codec is not ready" newline bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR." bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.." newline bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.." bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection." wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,SAI clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1" newline bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" newline bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,SAI data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" line.long 0x4 "SAI_PDMCR,SAI PDM control register" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number 2" "0: SAI_CK2 clock disabled,1: SAI_CK2 clock enabled" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number 1" "0: SAI_CK1 clock disabled,1: SAI_CK1 clock enabled" newline bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0: Configuration with 2 microphones,1: Configuration with 4 microphones,2: Configuration with 6 microphones,3: Configuration with 8 microphones" bitfld.long 0x4 0. "PDMEN,PDM enable" "0: PDM interface disabled,1: PDM interface enabled" line.long 0x8 "SAI_PDMDLY,SAI PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair 4" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair 4" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 of T less than sub>SAI_CK less than.." newline bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair 3" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair 3" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." newline bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair 2" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair 2" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." newline bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone of pair 1" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone of pair 1" "0: No delay,1: Delay of 1 T less than sub>SAI_CK less than..,2: Delay of 2 T less than sub>SAI_CK less than..,?,?,?,?,7: Delay of 7 T less than sub>SAI_CK less than.." tree.end tree.end tree "SDMMC (Secure Digital Input/Output MultiMediaCard Interface)" base ad:0x0 tree "SDMMC1" base ad:0x48027000 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0: Voltage transceiver IOs driven as output when..,1: Voltage transceiver IOs driven as output when.." bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0: SDMMC_CK clock kept unchanged after successfully..,1: SDMMC_CK clock stopped after successfully.." newline bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0: Voltage switch sequence not started and not..,1: Voltage switch sequence started or active." bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0: After reset Reset: the SDMMC is disabled and the..,?,2: Power-cycle the SDMMC is disabled and the clock..,3: Power-on: the card is clocked The first 74.." line.long 0x4 "SDMMC_CLKCR,SDMMC clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0: sdmmc_io_in_ck selected as receive clock,1: SDMMC_CKIN feedback clock selected as receive..,2: sdmmc_fb_ck tuned feedback clock selected as..,?" bitfld.long 0x4 19. "BUSSPEED,Bus speed for selection of SDMMC operating modes" "0: DS HS SDR12 SDR25 Legacy compatible High speed..,1: SDR50 DDR50 SDR104 HS200 bus speed mode selected." newline bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0: SDR Single data rate signaling,1: DDR double data rate signaling" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable" "0: Hardware flow control is disabled,1: Hardware flow control is enabled" newline bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for data and command" "0: When clock division >1 (CLKDIV > 0) and DDR = 0:,1: When clock division >1 (CLKDIV > 0) and DDR = 0:" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0: Default 1-bit wide bus mode: SDMMC_D0 used (Does..,1: 4-bit wide bus mode: SDMMC_D[3:0] used,2: 8-bit wide bus mode: SDMMC_D[7:0] used,?" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0: SDMMC_CK clock is always enabled,1: SDMMC_CK is only enabled when the bus is active" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "SDMMC_ARGR,SDMMC argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "SDMMC_CMDR,SDMMC command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0: Boot mode procedure disabled,1: Boot mode procedure enabled" newline bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0: Normal boot mode procedure selected,1: Alternative boot mode procedure selected." bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" newline bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM waits for end of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0: No response expect CMDSENT flag,1: Short response expect CMDREND or CCRCFAIL flag,2: Short response expect CMDREND flag (No CRC),3: Long response expect CMDREND or CCRCFAIL flag" newline bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "SDMMC_RESP1R,SDMMC response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0x8 "SDMMC_RESP2R,SDMMC response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0xC "SDMMC_RESP3R,SDMMC response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0x10 "SDMMC_RESP4R,SDMMC response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS,Card status according table below" group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,SDMMC data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "SDMMC_DLENR,SDMMC data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "SDMMC_DCTRL,SDMMC data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset flushes any remaining data" "0: FIFO not affected.,1: Flush any remaining data and reset the FIFO.." bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0: Boot acknowledgment disabled not expected to be..,1: Boot acknowledgment enabled expected to be.." newline bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read Wait mode" "0: Read Wait control using SDMMC_D2,1: Read Wait control stopping SDMMC_CK" newline bitfld.long 0x8 9. "RWSTOP,Read Wait stop" "0: No Read Wait stop.,1: Enable for Read Wait stop when DPSM is in the.." bitfld.long 0x8 8. "RWSTART,Read Wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0: Block data transfer ending on block count.,1: SDIO multibyte data transfer.,2: e MMC Stream data transfer. (WIDBUS must select..,3: Block data transfer ending with.." newline bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0: From host to card.,1: From card to host." bitfld.long 0x8 0. "DTEN,Data transfer enable bit" "0: Do not start data transfer without CPSM data..,1: Start data transfer without CPSM data transfer.." rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,SDMMC data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "SDMMC_STAR,SDMMC status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" newline bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" newline bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0: card SDMMC_D0 signal does NOT signal change from..,1: card SDMMC_D0 signal changed from busy to NOT.." newline bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0: card signals not busy on SDMMC_D0.,1: card signals busy on SDMMC_D0." bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" newline bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" newline bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" newline bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" newline bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" newline bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" newline bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" newline bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xF line.long 0x0 "SDMMC_ICR,SDMMC interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0: IDMABTC not cleared,1: IDMABTC cleared" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0: IDMATE not cleared,1: IDMATE cleared" newline bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0: CKSTOP not cleared,1: CKSTOP cleared" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0: VSWEND not cleared,1: VSWEND cleared" newline bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0: ACKTIMEOUT not cleared,1: ACKTIMEOUT cleared" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0: ACKFAIL not cleared,1: ACKFAIL cleared" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0: SDIOIT not cleared,1: SDIOIT cleared" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0: BUSYD0END not cleared,1: BUSYD0END cleared" newline bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0: DABORT not cleared,1: DABORT cleared" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0: DBCKEND not cleared,1: DBCKEND cleared" newline bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0: DHOLD not cleared,1: DHOLD cleared" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0: DATAEND not cleared,1: DATAEND cleared" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0: CMDSENT not cleared,1: CMDSENT cleared" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0: CMDREND not cleared,1: CMDREND cleared" newline bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0: RXOVERR not cleared,1: RXOVERR cleared" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0: TXUNDERR not cleared,1: TXUNDERR cleared" newline bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0: DTIMEOUT not cleared,1: DTIMEOUT cleared" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0: CTIMEOUT not cleared,1: CTIMEOUT cleared" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0: DCRCFAIL not cleared,1: DCRCFAIL cleared" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0: CCRCFAIL not cleared,1: CCRCFAIL cleared" line.long 0x4 "SDMMC_MASKR,SDMMC mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0: IDMA buffer transfer complete interrupt disabled,1: IDMA buffer transfer complete interrupt enabled" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0: Voltage Switch clock stopped interrupt disabled,1: Voltage Switch clock stopped interrupt enabled" newline bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0: Voltage switch critical timing section..,1: Voltage switch critical timing section.." bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0: Acknowledgment timeout interrupt disabled,1: Acknowledgment timeout interrupt enabled" newline bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0: Acknowledgment Fail interrupt disabled,1: Acknowledgment Fail interrupt enabled" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0: SDIO Mode interrupt received interrupt disabled,1: SDIO Mode interrupt received interrupt enabled" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0: BUSYD0END interrupt disabled,1: BUSYD0END interrupt enabled" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0: Tx FIFO empty interrupt disabled,1: Tx FIFO empty interrupt enabled" newline bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0: Rx FIFO full interrupt disabled,1: Rx FIFO full interrupt enabled" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0: Rx FIFO half full interrupt disabled,1: Rx FIFO half full interrupt enabled" newline bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0: Tx FIFO half empty interrupt disabled,1: Tx FIFO half empty interrupt enabled" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0: Data transfer abort interrupt disabled,1: Data transfer abort interrupt enabled" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0: Data block end interrupt disabled,1: Data block end interrupt enabled" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0: Data hold interrupt disabled,1: Data hold interrupt enabled" newline bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0: Data end interrupt disabled,1: Data end interrupt enabled" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0: Command sent interrupt disabled,1: Command sent interrupt enabled" newline bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0: Command response received interrupt disabled,1: command Response received interrupt enabled" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0: Rx FIFO overrun error interrupt disabled,1: Rx FIFO overrun error interrupt enabled" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0: Tx FIFO underrun error interrupt disabled,1: Tx FIFO underrun error interrupt enabled" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0: Data timeout interrupt disabled,1: Data timeout interrupt enabled" newline bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0: Command timeout interrupt disabled,1: Command timeout interrupt enabled" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0: Data CRC fail interrupt disabled,1: Data CRC fail interrupt enabled" newline bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0: Command CRC fail interrupt disabled,1: Command CRC fail interrupt enabled" line.long 0x8 "SDMMC_ACKTIMER,SDMMC acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" line.long 0xC "SDMMC_FIFOTHRR,SDMMC data FIFO threshold register" hexmask.long.byte 0xC 0.--3. 1. "THR,FIFO threshold" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,SDMMC DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection" "0: Single buffer mode.,1: Linked list mode." bitfld.long 0x0 0. "IDMAEN,IDMA enable" "0: IDMA disabled,1: IDMA enabled" line.long 0x4 "SDMMC_IDMABSIZER,SDMMC IDMA buffer size register" hexmask.long.word 0x4 6.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,SDMMC IDMA buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] must be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,SDMMC IDMA linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0: SDMMC_IDMALAR is not to be updated last linked..,1: SDMMC_IDMALAR is to be updated from linked list.." bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0: SDMMC_IDMABSIZER is not to be updated from next..,1: SDMMC_IDMABSIZER is to be updated from next.." newline bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0: Loaded linked list buffer is not ready (this..,1: Loaded linked list buffer ready acknowledge." hexmask.long.word 0x0 2.--15. 1. "IDMALA,Word aligned linked list item address offset" line.long 0x4 "SDMMC_IDMABAR,SDMMC IDMA linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" group.long 0x80++0x3F line.long 0x0 "SDMMC_FIFOR0,SDMMC data FIFO registers 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "SDMMC_FIFOR1,SDMMC data FIFO registers 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "SDMMC_FIFOR2,SDMMC data FIFO registers 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "SDMMC_FIFOR3,SDMMC data FIFO registers 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "SDMMC_FIFOR4,SDMMC data FIFO registers 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "SDMMC_FIFOR5,SDMMC data FIFO registers 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "SDMMC_FIFOR6,SDMMC data FIFO registers 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "SDMMC_FIFOR7,SDMMC data FIFO registers 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "SDMMC_FIFOR8,SDMMC data FIFO registers 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "SDMMC_FIFOR9,SDMMC data FIFO registers 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "SDMMC_FIFOR10,SDMMC data FIFO registers 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "SDMMC_FIFOR11,SDMMC data FIFO registers 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "SDMMC_FIFOR12,SDMMC data FIFO registers 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "SDMMC_FIFOR13,SDMMC data FIFO registers 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "SDMMC_FIFOR14,SDMMC data FIFO registers 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "SDMMC_FIFOR15,SDMMC data FIFO registers 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" tree.end tree "SDMMC1_S" base ad:0x58027000 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0: Voltage transceiver IOs driven as output when..,1: Voltage transceiver IOs driven as output when.." bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0: SDMMC_CK clock kept unchanged after successfully..,1: SDMMC_CK clock stopped after successfully.." newline bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0: Voltage switch sequence not started and not..,1: Voltage switch sequence started or active." bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0: After reset Reset: the SDMMC is disabled and the..,?,2: Power-cycle the SDMMC is disabled and the clock..,3: Power-on: the card is clocked The first 74.." line.long 0x4 "SDMMC_CLKCR,SDMMC clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0: sdmmc_io_in_ck selected as receive clock,1: SDMMC_CKIN feedback clock selected as receive..,2: sdmmc_fb_ck tuned feedback clock selected as..,?" bitfld.long 0x4 19. "BUSSPEED,Bus speed for selection of SDMMC operating modes" "0: DS HS SDR12 SDR25 Legacy compatible High speed..,1: SDR50 DDR50 SDR104 HS200 bus speed mode selected." newline bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0: SDR Single data rate signaling,1: DDR double data rate signaling" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable" "0: Hardware flow control is disabled,1: Hardware flow control is enabled" newline bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for data and command" "0: When clock division >1 (CLKDIV > 0) and DDR = 0:,1: When clock division >1 (CLKDIV > 0) and DDR = 0:" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0: Default 1-bit wide bus mode: SDMMC_D0 used (Does..,1: 4-bit wide bus mode: SDMMC_D[3:0] used,2: 8-bit wide bus mode: SDMMC_D[7:0] used,?" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0: SDMMC_CK clock is always enabled,1: SDMMC_CK is only enabled when the bus is active" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "SDMMC_ARGR,SDMMC argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "SDMMC_CMDR,SDMMC command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0: Boot mode procedure disabled,1: Boot mode procedure enabled" newline bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0: Normal boot mode procedure selected,1: Alternative boot mode procedure selected." bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" newline bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM waits for end of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0: No response expect CMDSENT flag,1: Short response expect CMDREND or CCRCFAIL flag,2: Short response expect CMDREND flag (No CRC),3: Long response expect CMDREND or CCRCFAIL flag" newline bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "SDMMC_RESP1R,SDMMC response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0x8 "SDMMC_RESP2R,SDMMC response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0xC "SDMMC_RESP3R,SDMMC response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0x10 "SDMMC_RESP4R,SDMMC response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS,Card status according table below" group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,SDMMC data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "SDMMC_DLENR,SDMMC data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "SDMMC_DCTRL,SDMMC data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset flushes any remaining data" "0: FIFO not affected.,1: Flush any remaining data and reset the FIFO.." bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0: Boot acknowledgment disabled not expected to be..,1: Boot acknowledgment enabled expected to be.." newline bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read Wait mode" "0: Read Wait control using SDMMC_D2,1: Read Wait control stopping SDMMC_CK" newline bitfld.long 0x8 9. "RWSTOP,Read Wait stop" "0: No Read Wait stop.,1: Enable for Read Wait stop when DPSM is in the.." bitfld.long 0x8 8. "RWSTART,Read Wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0: Block data transfer ending on block count.,1: SDIO multibyte data transfer.,2: e MMC Stream data transfer. (WIDBUS must select..,3: Block data transfer ending with.." newline bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0: From host to card.,1: From card to host." bitfld.long 0x8 0. "DTEN,Data transfer enable bit" "0: Do not start data transfer without CPSM data..,1: Start data transfer without CPSM data transfer.." rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,SDMMC data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "SDMMC_STAR,SDMMC status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" newline bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" newline bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0: card SDMMC_D0 signal does NOT signal change from..,1: card SDMMC_D0 signal changed from busy to NOT.." newline bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0: card signals not busy on SDMMC_D0.,1: card signals busy on SDMMC_D0." bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" newline bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" newline bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" newline bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" newline bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" newline bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" newline bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" newline bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xF line.long 0x0 "SDMMC_ICR,SDMMC interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0: IDMABTC not cleared,1: IDMABTC cleared" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0: IDMATE not cleared,1: IDMATE cleared" newline bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0: CKSTOP not cleared,1: CKSTOP cleared" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0: VSWEND not cleared,1: VSWEND cleared" newline bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0: ACKTIMEOUT not cleared,1: ACKTIMEOUT cleared" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0: ACKFAIL not cleared,1: ACKFAIL cleared" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0: SDIOIT not cleared,1: SDIOIT cleared" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0: BUSYD0END not cleared,1: BUSYD0END cleared" newline bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0: DABORT not cleared,1: DABORT cleared" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0: DBCKEND not cleared,1: DBCKEND cleared" newline bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0: DHOLD not cleared,1: DHOLD cleared" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0: DATAEND not cleared,1: DATAEND cleared" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0: CMDSENT not cleared,1: CMDSENT cleared" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0: CMDREND not cleared,1: CMDREND cleared" newline bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0: RXOVERR not cleared,1: RXOVERR cleared" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0: TXUNDERR not cleared,1: TXUNDERR cleared" newline bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0: DTIMEOUT not cleared,1: DTIMEOUT cleared" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0: CTIMEOUT not cleared,1: CTIMEOUT cleared" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0: DCRCFAIL not cleared,1: DCRCFAIL cleared" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0: CCRCFAIL not cleared,1: CCRCFAIL cleared" line.long 0x4 "SDMMC_MASKR,SDMMC mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0: IDMA buffer transfer complete interrupt disabled,1: IDMA buffer transfer complete interrupt enabled" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0: Voltage Switch clock stopped interrupt disabled,1: Voltage Switch clock stopped interrupt enabled" newline bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0: Voltage switch critical timing section..,1: Voltage switch critical timing section.." bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0: Acknowledgment timeout interrupt disabled,1: Acknowledgment timeout interrupt enabled" newline bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0: Acknowledgment Fail interrupt disabled,1: Acknowledgment Fail interrupt enabled" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0: SDIO Mode interrupt received interrupt disabled,1: SDIO Mode interrupt received interrupt enabled" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0: BUSYD0END interrupt disabled,1: BUSYD0END interrupt enabled" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0: Tx FIFO empty interrupt disabled,1: Tx FIFO empty interrupt enabled" newline bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0: Rx FIFO full interrupt disabled,1: Rx FIFO full interrupt enabled" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0: Rx FIFO half full interrupt disabled,1: Rx FIFO half full interrupt enabled" newline bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0: Tx FIFO half empty interrupt disabled,1: Tx FIFO half empty interrupt enabled" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0: Data transfer abort interrupt disabled,1: Data transfer abort interrupt enabled" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0: Data block end interrupt disabled,1: Data block end interrupt enabled" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0: Data hold interrupt disabled,1: Data hold interrupt enabled" newline bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0: Data end interrupt disabled,1: Data end interrupt enabled" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0: Command sent interrupt disabled,1: Command sent interrupt enabled" newline bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0: Command response received interrupt disabled,1: command Response received interrupt enabled" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0: Rx FIFO overrun error interrupt disabled,1: Rx FIFO overrun error interrupt enabled" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0: Tx FIFO underrun error interrupt disabled,1: Tx FIFO underrun error interrupt enabled" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0: Data timeout interrupt disabled,1: Data timeout interrupt enabled" newline bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0: Command timeout interrupt disabled,1: Command timeout interrupt enabled" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0: Data CRC fail interrupt disabled,1: Data CRC fail interrupt enabled" newline bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0: Command CRC fail interrupt disabled,1: Command CRC fail interrupt enabled" line.long 0x8 "SDMMC_ACKTIMER,SDMMC acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" line.long 0xC "SDMMC_FIFOTHRR,SDMMC data FIFO threshold register" hexmask.long.byte 0xC 0.--3. 1. "THR,FIFO threshold" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,SDMMC DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection" "0: Single buffer mode.,1: Linked list mode." bitfld.long 0x0 0. "IDMAEN,IDMA enable" "0: IDMA disabled,1: IDMA enabled" line.long 0x4 "SDMMC_IDMABSIZER,SDMMC IDMA buffer size register" hexmask.long.word 0x4 6.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,SDMMC IDMA buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] must be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,SDMMC IDMA linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0: SDMMC_IDMALAR is not to be updated last linked..,1: SDMMC_IDMALAR is to be updated from linked list.." bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0: SDMMC_IDMABSIZER is not to be updated from next..,1: SDMMC_IDMABSIZER is to be updated from next.." newline bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0: Loaded linked list buffer is not ready (this..,1: Loaded linked list buffer ready acknowledge." hexmask.long.word 0x0 2.--15. 1. "IDMALA,Word aligned linked list item address offset" line.long 0x4 "SDMMC_IDMABAR,SDMMC IDMA linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" group.long 0x80++0x3F line.long 0x0 "SDMMC_FIFOR0,SDMMC data FIFO registers 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "SDMMC_FIFOR1,SDMMC data FIFO registers 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "SDMMC_FIFOR2,SDMMC data FIFO registers 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "SDMMC_FIFOR3,SDMMC data FIFO registers 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "SDMMC_FIFOR4,SDMMC data FIFO registers 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "SDMMC_FIFOR5,SDMMC data FIFO registers 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "SDMMC_FIFOR6,SDMMC data FIFO registers 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "SDMMC_FIFOR7,SDMMC data FIFO registers 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "SDMMC_FIFOR8,SDMMC data FIFO registers 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "SDMMC_FIFOR9,SDMMC data FIFO registers 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "SDMMC_FIFOR10,SDMMC data FIFO registers 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "SDMMC_FIFOR11,SDMMC data FIFO registers 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "SDMMC_FIFOR12,SDMMC data FIFO registers 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "SDMMC_FIFOR13,SDMMC data FIFO registers 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "SDMMC_FIFOR14,SDMMC data FIFO registers 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "SDMMC_FIFOR15,SDMMC data FIFO registers 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" tree.end tree "SDMMC2" base ad:0x48026800 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0: Voltage transceiver IOs driven as output when..,1: Voltage transceiver IOs driven as output when.." bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0: SDMMC_CK clock kept unchanged after successfully..,1: SDMMC_CK clock stopped after successfully.." newline bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0: Voltage switch sequence not started and not..,1: Voltage switch sequence started or active." bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0: After reset Reset: the SDMMC is disabled and the..,?,2: Power-cycle the SDMMC is disabled and the clock..,3: Power-on: the card is clocked The first 74.." line.long 0x4 "SDMMC_CLKCR,SDMMC clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0: sdmmc_io_in_ck selected as receive clock,1: SDMMC_CKIN feedback clock selected as receive..,2: sdmmc_fb_ck tuned feedback clock selected as..,?" bitfld.long 0x4 19. "BUSSPEED,Bus speed for selection of SDMMC operating modes" "0: DS HS SDR12 SDR25 Legacy compatible High speed..,1: SDR50 DDR50 SDR104 HS200 bus speed mode selected." newline bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0: SDR Single data rate signaling,1: DDR double data rate signaling" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable" "0: Hardware flow control is disabled,1: Hardware flow control is enabled" newline bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for data and command" "0: When clock division >1 (CLKDIV > 0) and DDR = 0:,1: When clock division >1 (CLKDIV > 0) and DDR = 0:" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0: Default 1-bit wide bus mode: SDMMC_D0 used (Does..,1: 4-bit wide bus mode: SDMMC_D[3:0] used,2: 8-bit wide bus mode: SDMMC_D[7:0] used,?" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0: SDMMC_CK clock is always enabled,1: SDMMC_CK is only enabled when the bus is active" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "SDMMC_ARGR,SDMMC argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "SDMMC_CMDR,SDMMC command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0: Boot mode procedure disabled,1: Boot mode procedure enabled" newline bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0: Normal boot mode procedure selected,1: Alternative boot mode procedure selected." bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" newline bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM waits for end of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0: No response expect CMDSENT flag,1: Short response expect CMDREND or CCRCFAIL flag,2: Short response expect CMDREND flag (No CRC),3: Long response expect CMDREND or CCRCFAIL flag" newline bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "SDMMC_RESP1R,SDMMC response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0x8 "SDMMC_RESP2R,SDMMC response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0xC "SDMMC_RESP3R,SDMMC response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0x10 "SDMMC_RESP4R,SDMMC response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS,Card status according table below" group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,SDMMC data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "SDMMC_DLENR,SDMMC data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "SDMMC_DCTRL,SDMMC data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset flushes any remaining data" "0: FIFO not affected.,1: Flush any remaining data and reset the FIFO.." bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0: Boot acknowledgment disabled not expected to be..,1: Boot acknowledgment enabled expected to be.." newline bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read Wait mode" "0: Read Wait control using SDMMC_D2,1: Read Wait control stopping SDMMC_CK" newline bitfld.long 0x8 9. "RWSTOP,Read Wait stop" "0: No Read Wait stop.,1: Enable for Read Wait stop when DPSM is in the.." bitfld.long 0x8 8. "RWSTART,Read Wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0: Block data transfer ending on block count.,1: SDIO multibyte data transfer.,2: e MMC Stream data transfer. (WIDBUS must select..,3: Block data transfer ending with.." newline bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0: From host to card.,1: From card to host." bitfld.long 0x8 0. "DTEN,Data transfer enable bit" "0: Do not start data transfer without CPSM data..,1: Start data transfer without CPSM data transfer.." rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,SDMMC data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "SDMMC_STAR,SDMMC status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" newline bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" newline bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0: card SDMMC_D0 signal does NOT signal change from..,1: card SDMMC_D0 signal changed from busy to NOT.." newline bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0: card signals not busy on SDMMC_D0.,1: card signals busy on SDMMC_D0." bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" newline bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" newline bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" newline bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" newline bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" newline bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" newline bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" newline bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xF line.long 0x0 "SDMMC_ICR,SDMMC interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0: IDMABTC not cleared,1: IDMABTC cleared" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0: IDMATE not cleared,1: IDMATE cleared" newline bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0: CKSTOP not cleared,1: CKSTOP cleared" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0: VSWEND not cleared,1: VSWEND cleared" newline bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0: ACKTIMEOUT not cleared,1: ACKTIMEOUT cleared" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0: ACKFAIL not cleared,1: ACKFAIL cleared" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0: SDIOIT not cleared,1: SDIOIT cleared" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0: BUSYD0END not cleared,1: BUSYD0END cleared" newline bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0: DABORT not cleared,1: DABORT cleared" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0: DBCKEND not cleared,1: DBCKEND cleared" newline bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0: DHOLD not cleared,1: DHOLD cleared" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0: DATAEND not cleared,1: DATAEND cleared" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0: CMDSENT not cleared,1: CMDSENT cleared" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0: CMDREND not cleared,1: CMDREND cleared" newline bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0: RXOVERR not cleared,1: RXOVERR cleared" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0: TXUNDERR not cleared,1: TXUNDERR cleared" newline bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0: DTIMEOUT not cleared,1: DTIMEOUT cleared" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0: CTIMEOUT not cleared,1: CTIMEOUT cleared" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0: DCRCFAIL not cleared,1: DCRCFAIL cleared" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0: CCRCFAIL not cleared,1: CCRCFAIL cleared" line.long 0x4 "SDMMC_MASKR,SDMMC mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0: IDMA buffer transfer complete interrupt disabled,1: IDMA buffer transfer complete interrupt enabled" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0: Voltage Switch clock stopped interrupt disabled,1: Voltage Switch clock stopped interrupt enabled" newline bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0: Voltage switch critical timing section..,1: Voltage switch critical timing section.." bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0: Acknowledgment timeout interrupt disabled,1: Acknowledgment timeout interrupt enabled" newline bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0: Acknowledgment Fail interrupt disabled,1: Acknowledgment Fail interrupt enabled" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0: SDIO Mode interrupt received interrupt disabled,1: SDIO Mode interrupt received interrupt enabled" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0: BUSYD0END interrupt disabled,1: BUSYD0END interrupt enabled" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0: Tx FIFO empty interrupt disabled,1: Tx FIFO empty interrupt enabled" newline bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0: Rx FIFO full interrupt disabled,1: Rx FIFO full interrupt enabled" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0: Rx FIFO half full interrupt disabled,1: Rx FIFO half full interrupt enabled" newline bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0: Tx FIFO half empty interrupt disabled,1: Tx FIFO half empty interrupt enabled" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0: Data transfer abort interrupt disabled,1: Data transfer abort interrupt enabled" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0: Data block end interrupt disabled,1: Data block end interrupt enabled" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0: Data hold interrupt disabled,1: Data hold interrupt enabled" newline bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0: Data end interrupt disabled,1: Data end interrupt enabled" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0: Command sent interrupt disabled,1: Command sent interrupt enabled" newline bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0: Command response received interrupt disabled,1: command Response received interrupt enabled" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0: Rx FIFO overrun error interrupt disabled,1: Rx FIFO overrun error interrupt enabled" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0: Tx FIFO underrun error interrupt disabled,1: Tx FIFO underrun error interrupt enabled" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0: Data timeout interrupt disabled,1: Data timeout interrupt enabled" newline bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0: Command timeout interrupt disabled,1: Command timeout interrupt enabled" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0: Data CRC fail interrupt disabled,1: Data CRC fail interrupt enabled" newline bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0: Command CRC fail interrupt disabled,1: Command CRC fail interrupt enabled" line.long 0x8 "SDMMC_ACKTIMER,SDMMC acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" line.long 0xC "SDMMC_FIFOTHRR,SDMMC data FIFO threshold register" hexmask.long.byte 0xC 0.--3. 1. "THR,FIFO threshold" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,SDMMC DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection" "0: Single buffer mode.,1: Linked list mode." bitfld.long 0x0 0. "IDMAEN,IDMA enable" "0: IDMA disabled,1: IDMA enabled" line.long 0x4 "SDMMC_IDMABSIZER,SDMMC IDMA buffer size register" hexmask.long.word 0x4 6.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,SDMMC IDMA buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] must be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,SDMMC IDMA linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0: SDMMC_IDMALAR is not to be updated last linked..,1: SDMMC_IDMALAR is to be updated from linked list.." bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0: SDMMC_IDMABSIZER is not to be updated from next..,1: SDMMC_IDMABSIZER is to be updated from next.." newline bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0: Loaded linked list buffer is not ready (this..,1: Loaded linked list buffer ready acknowledge." hexmask.long.word 0x0 2.--15. 1. "IDMALA,Word aligned linked list item address offset" line.long 0x4 "SDMMC_IDMABAR,SDMMC IDMA linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" group.long 0x80++0x3F line.long 0x0 "SDMMC_FIFOR0,SDMMC data FIFO registers 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "SDMMC_FIFOR1,SDMMC data FIFO registers 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "SDMMC_FIFOR2,SDMMC data FIFO registers 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "SDMMC_FIFOR3,SDMMC data FIFO registers 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "SDMMC_FIFOR4,SDMMC data FIFO registers 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "SDMMC_FIFOR5,SDMMC data FIFO registers 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "SDMMC_FIFOR6,SDMMC data FIFO registers 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "SDMMC_FIFOR7,SDMMC data FIFO registers 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "SDMMC_FIFOR8,SDMMC data FIFO registers 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "SDMMC_FIFOR9,SDMMC data FIFO registers 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "SDMMC_FIFOR10,SDMMC data FIFO registers 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "SDMMC_FIFOR11,SDMMC data FIFO registers 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "SDMMC_FIFOR12,SDMMC data FIFO registers 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "SDMMC_FIFOR13,SDMMC data FIFO registers 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "SDMMC_FIFOR14,SDMMC data FIFO registers 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "SDMMC_FIFOR15,SDMMC data FIFO registers 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" tree.end tree "SDMMC2_S" base ad:0x58026800 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0: Voltage transceiver IOs driven as output when..,1: Voltage transceiver IOs driven as output when.." bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0: SDMMC_CK clock kept unchanged after successfully..,1: SDMMC_CK clock stopped after successfully.." newline bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0: Voltage switch sequence not started and not..,1: Voltage switch sequence started or active." bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0: After reset Reset: the SDMMC is disabled and the..,?,2: Power-cycle the SDMMC is disabled and the clock..,3: Power-on: the card is clocked The first 74.." line.long 0x4 "SDMMC_CLKCR,SDMMC clock control register" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0: sdmmc_io_in_ck selected as receive clock,1: SDMMC_CKIN feedback clock selected as receive..,2: sdmmc_fb_ck tuned feedback clock selected as..,?" bitfld.long 0x4 19. "BUSSPEED,Bus speed for selection of SDMMC operating modes" "0: DS HS SDR12 SDR25 Legacy compatible High speed..,1: SDR50 DDR50 SDR104 HS200 bus speed mode selected." newline bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0: SDR Single data rate signaling,1: DDR double data rate signaling" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable" "0: Hardware flow control is disabled,1: Hardware flow control is enabled" newline bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for data and command" "0: When clock division >1 (CLKDIV > 0) and DDR = 0:,1: When clock division >1 (CLKDIV > 0) and DDR = 0:" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0: Default 1-bit wide bus mode: SDMMC_D0 used (Does..,1: 4-bit wide bus mode: SDMMC_D[3:0] used,2: 8-bit wide bus mode: SDMMC_D[7:0] used,?" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0: SDMMC_CK clock is always enabled,1: SDMMC_CK is only enabled when the bus is active" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor" line.long 0x8 "SDMMC_ARGR,SDMMC argument register" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "SDMMC_CMDR,SDMMC command register" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0: Boot mode procedure disabled,1: Boot mode procedure enabled" newline bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0: Normal boot mode procedure selected,1: Alternative boot mode procedure selected." bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1" newline bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) enable bit" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM waits for end of data transfer (CmdPend internal signal) from DPSM" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0: No response expect CMDSENT flag,1: Short response expect CMDREND or CCRCFAIL flag,2: Short response expect CMDREND flag (No CRC),3: Long response expect CMDREND or CCRCFAIL flag" newline bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index" rgroup.long 0x10++0x13 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response register" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" line.long 0x4 "SDMMC_RESP1R,SDMMC response 1 register" hexmask.long 0x4 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0x8 "SDMMC_RESP2R,SDMMC response 2 register" hexmask.long 0x8 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0xC "SDMMC_RESP3R,SDMMC response 3 register" hexmask.long 0xC 0.--31. 1. "CARDSTATUS,Card status according table below" line.long 0x10 "SDMMC_RESP4R,SDMMC response 4 register" hexmask.long 0x10 0.--31. 1. "CARDSTATUS,Card status according table below" group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,SDMMC data timer register" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period" line.long 0x4 "SDMMC_DLENR,SDMMC data length register" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value" line.long 0x8 "SDMMC_DCTRL,SDMMC data control register" bitfld.long 0x8 13. "FIFORST,FIFO reset flushes any remaining data" "0: FIFO not affected.,1: Flush any remaining data and reset the FIFO.." bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0: Boot acknowledgment disabled not expected to be..,1: Boot acknowledgment enabled expected to be.." newline bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions" "0,1" bitfld.long 0x8 10. "RWMOD,Read Wait mode" "0: Read Wait control using SDMMC_D2,1: Read Wait control stopping SDMMC_CK" newline bitfld.long 0x8 9. "RWSTOP,Read Wait stop" "0: No Read Wait stop.,1: Enable for Read Wait stop when DPSM is in the.." bitfld.long 0x8 8. "RWSTART,Read Wait start" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0: Block data transfer ending on block count.,1: SDIO multibyte data transfer.,2: e MMC Stream data transfer. (WIDBUS must select..,3: Block data transfer ending with.." newline bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0: From host to card.,1: From card to host." bitfld.long 0x8 0. "DTEN,Data transfer enable bit" "0: Do not start data transfer without CPSM data..,1: Start data transfer without CPSM data transfer.." rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,SDMMC data counter register" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value" line.long 0x4 "SDMMC_STAR,SDMMC status register" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1" newline bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1" newline bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0: card SDMMC_D0 signal does NOT signal change from..,1: card SDMMC_D0 signal changed from busy to NOT.." newline bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0: card signals not busy on SDMMC_D0.,1: card signals busy on SDMMC_D0." bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1" newline bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1" newline bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1" newline bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1" newline bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1" newline bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1" newline bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1" newline bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1" group.long 0x38++0xF line.long 0x0 "SDMMC_ICR,SDMMC interrupt clear register" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0: IDMABTC not cleared,1: IDMABTC cleared" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0: IDMATE not cleared,1: IDMATE cleared" newline bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0: CKSTOP not cleared,1: CKSTOP cleared" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0: VSWEND not cleared,1: VSWEND cleared" newline bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0: ACKTIMEOUT not cleared,1: ACKTIMEOUT cleared" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0: ACKFAIL not cleared,1: ACKFAIL cleared" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0: SDIOIT not cleared,1: SDIOIT cleared" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0: BUSYD0END not cleared,1: BUSYD0END cleared" newline bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0: DABORT not cleared,1: DABORT cleared" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0: DBCKEND not cleared,1: DBCKEND cleared" newline bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0: DHOLD not cleared,1: DHOLD cleared" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0: DATAEND not cleared,1: DATAEND cleared" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0: CMDSENT not cleared,1: CMDSENT cleared" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0: CMDREND not cleared,1: CMDREND cleared" newline bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0: RXOVERR not cleared,1: RXOVERR cleared" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0: TXUNDERR not cleared,1: TXUNDERR cleared" newline bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0: DTIMEOUT not cleared,1: DTIMEOUT cleared" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0: CTIMEOUT not cleared,1: CTIMEOUT cleared" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0: DCRCFAIL not cleared,1: DCRCFAIL cleared" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0: CCRCFAIL not cleared,1: CCRCFAIL cleared" line.long 0x4 "SDMMC_MASKR,SDMMC mask register" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0: IDMA buffer transfer complete interrupt disabled,1: IDMA buffer transfer complete interrupt enabled" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0: Voltage Switch clock stopped interrupt disabled,1: Voltage Switch clock stopped interrupt enabled" newline bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0: Voltage switch critical timing section..,1: Voltage switch critical timing section.." bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0: Acknowledgment timeout interrupt disabled,1: Acknowledgment timeout interrupt enabled" newline bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0: Acknowledgment Fail interrupt disabled,1: Acknowledgment Fail interrupt enabled" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0: SDIO Mode interrupt received interrupt disabled,1: SDIO Mode interrupt received interrupt enabled" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0: BUSYD0END interrupt disabled,1: BUSYD0END interrupt enabled" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0: Tx FIFO empty interrupt disabled,1: Tx FIFO empty interrupt enabled" newline bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0: Rx FIFO full interrupt disabled,1: Rx FIFO full interrupt enabled" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0: Rx FIFO half full interrupt disabled,1: Rx FIFO half full interrupt enabled" newline bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0: Tx FIFO half empty interrupt disabled,1: Tx FIFO half empty interrupt enabled" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0: Data transfer abort interrupt disabled,1: Data transfer abort interrupt enabled" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0: Data block end interrupt disabled,1: Data block end interrupt enabled" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0: Data hold interrupt disabled,1: Data hold interrupt enabled" newline bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0: Data end interrupt disabled,1: Data end interrupt enabled" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0: Command sent interrupt disabled,1: Command sent interrupt enabled" newline bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0: Command response received interrupt disabled,1: command Response received interrupt enabled" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0: Rx FIFO overrun error interrupt disabled,1: Rx FIFO overrun error interrupt enabled" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0: Tx FIFO underrun error interrupt disabled,1: Tx FIFO underrun error interrupt enabled" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0: Data timeout interrupt disabled,1: Data timeout interrupt enabled" newline bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0: Command timeout interrupt disabled,1: Command timeout interrupt enabled" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0: Data CRC fail interrupt disabled,1: Data CRC fail interrupt enabled" newline bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0: Command CRC fail interrupt disabled,1: Command CRC fail interrupt enabled" line.long 0x8 "SDMMC_ACKTIMER,SDMMC acknowledgment timer register" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period" line.long 0xC "SDMMC_FIFOTHRR,SDMMC data FIFO threshold register" hexmask.long.byte 0xC 0.--3. 1. "THR,FIFO threshold" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,SDMMC DMA control register" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection" "0: Single buffer mode.,1: Linked list mode." bitfld.long 0x0 0. "IDMAEN,IDMA enable" "0: IDMA disabled,1: IDMA enabled" line.long 0x4 "SDMMC_IDMABSIZER,SDMMC IDMA buffer size register" hexmask.long.word 0x4 6.--16. 1. "IDMABNDT,Number of bytes per buffer" line.long 0x8 "SDMMC_IDMABASER,SDMMC IDMA buffer base address register" hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] must be word aligned (bit [1:0] are always 0 and read only)" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,SDMMC IDMA linked list address register" bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0: SDMMC_IDMALAR is not to be updated last linked..,1: SDMMC_IDMALAR is to be updated from linked list.." bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0: SDMMC_IDMABSIZER is not to be updated from next..,1: SDMMC_IDMABSIZER is to be updated from next.." newline bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0: Loaded linked list buffer is not ready (this..,1: Loaded linked list buffer ready acknowledge." hexmask.long.word 0x0 2.--15. 1. "IDMALA,Word aligned linked list item address offset" line.long 0x4 "SDMMC_IDMABAR,SDMMC IDMA linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address" group.long 0x80++0x3F line.long 0x0 "SDMMC_FIFOR0,SDMMC data FIFO registers 0" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x4 "SDMMC_FIFOR1,SDMMC data FIFO registers 1" hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x8 "SDMMC_FIFOR2,SDMMC data FIFO registers 2" hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0xC "SDMMC_FIFOR3,SDMMC data FIFO registers 3" hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x10 "SDMMC_FIFOR4,SDMMC data FIFO registers 4" hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x14 "SDMMC_FIFOR5,SDMMC data FIFO registers 5" hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x18 "SDMMC_FIFOR6,SDMMC data FIFO registers 6" hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x1C "SDMMC_FIFOR7,SDMMC data FIFO registers 7" hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x20 "SDMMC_FIFOR8,SDMMC data FIFO registers 8" hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x24 "SDMMC_FIFOR9,SDMMC data FIFO registers 9" hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x28 "SDMMC_FIFOR10,SDMMC data FIFO registers 10" hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x2C "SDMMC_FIFOR11,SDMMC data FIFO registers 11" hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x30 "SDMMC_FIFOR12,SDMMC data FIFO registers 12" hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x34 "SDMMC_FIFOR13,SDMMC data FIFO registers 13" hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x38 "SDMMC_FIFOR14,SDMMC data FIFO registers 14" hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" line.long 0x3C "SDMMC_FIFOR15,SDMMC data FIFO registers 15" hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data" tree.end tree.end tree "SPDIFRX (SPDIF Receiver Interface)" base ad:0x0 tree "SPDIFRX" base ad:0x40004000 group.long 0x0++0x7 line.long 0x0 "SPDIFRX_CR,SPDIFRX control register" bitfld.long 0x0 21. "CKSBKPEN,Backup symbol clock enable" "0: The SPDIFRX does not generate a backup symbol..,1: The SPDIFRX generates a backup symbol clock if.." bitfld.long 0x0 20. "CKSEN,Symbol clock enable" "0: The SPDIFRX does not generate a symbol clock.,1: The SPDIFRX generates a symbol clock." newline bitfld.long 0x0 16.--18. "INSEL,SPDIFRX input selection" "0: SPDIFRX_IN0 selected,1: SPDIFRX_IN1 selected,2: SPDIFRX_IN2 selected,3: SPDIFRX_IN3 selected,?,?,?,?" bitfld.long 0x0 14. "WFA,Wait for activity less than sup>(1) less than /sup>" "0: The SPDIFRX does not wait for activity on..,1: The SPDIFRX waits for activity on SPDIFRX_IN.." newline bitfld.long 0x0 12.--13. "NBTR,Maximum allowed re-tries during synchronization phase less than sup>(1) less than /sup>" "0: No re-try is allowed (only one attempt),1: 3 re-tries allowed,2: 15 re-tries allowed,3: 63 re-tries allowed" bitfld.long 0x0 11. "CHSEL,Channel selection less than sup>(1) less than /sup>" "0: The control flow takes the channel status from..,1: The control flow takes the channel status from.." newline bitfld.long 0x0 10. "CBDMAEN,Control buffer DMA enable for control flow less than sup>(1) less than /sup>" "0: DMA mode is disabled for reception of channel..,1: DMA mode is enabled for reception of channel.." bitfld.long 0x0 9. "PTMSK,Mask of preamble type bits less than sup>(1) less than /sup>" "0: The preamble type bits are copied into the..,1: The preamble type bits are not copied into the.." newline bitfld.long 0x0 8. "CUMSK,Mask of channel status and user bits less than sup>(1) less than /sup>" "0: The channel status and user bits are copied into..,1: The channel status and user bits are not copied.." bitfld.long 0x0 7. "VMSK,Mask of validity bit less than sup>(1) less than /sup>" "0: The validity bit is copied into the..,1: The validity bit is not copied into the.." newline bitfld.long 0x0 6. "PMSK,Mask parity error bit less than sup>(1) less than /sup>" "0: The parity error bit is copied into the..,1: The parity error bit is not copied into the.." bitfld.long 0x0 4.--5. "DRFMT,RX data format less than sup>(1) less than /sup>" "0: Data samples are aligned in the right (LSB).,1: Data samples are aligned in the left (MSB),2: Data sample are packed by setting two 16-bit..,?" newline bitfld.long 0x0 3. "RXSTEO,Stereo mode less than sup>(1) less than /sup>" "0: The peripheral is in mono mode.,1: The peripheral is in stereo mode." bitfld.long 0x0 2. "RXDMAEN,Receiver DMA enable for data flow less than sup>(1) less than /sup>" "0: DMA mode is disabled for reception.,1: DMA mode is enabled for reception." newline bitfld.long 0x0 0.--1. "SPDIFRXEN,Peripheral block enable less than sup>(1) less than /sup>" "0: Disable SPDIFRX (STATE_IDLE).,1: Enable SPDIFRX synchronization only.,?,3: Enable SPDIF receiver." line.long 0x4 "SPDIFRX_IMR,SPDIFRX interrupt mask register" bitfld.long 0x4 6. "IFEIE,Serial interface error interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." bitfld.long 0x4 5. "SYNCDIE,Synchronization done" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." newline bitfld.long 0x4 4. "SBLKIE,Synchronization block detected interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." bitfld.long 0x4 3. "OVRIE,Overrun error interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." newline bitfld.long 0x4 2. "PERRIE,Parity error interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." bitfld.long 0x4 1. "CSRNEIE,Control buffer ready interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." newline bitfld.long 0x4 0. "RXNEIE,RXNE interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." rgroup.long 0x8++0x3 line.long 0x0 "SPDIFRX_SR,SPDIFRX status register" hexmask.long.word 0x0 16.--30. 1. "WIDTH5,duration of 5 symbols counted with spdifrx_ker_ck" bitfld.long 0x0 8. "TERR,Time-out error" "0: No sequence error is detected.,1: Sequence error is detected." newline bitfld.long 0x0 7. "SERR,Synchronization error" "0: No synchronization error is detected.,1: Synchronization error is detected." bitfld.long 0x0 6. "FERR,Framing error" "0: No Manchester violation detected,1: Manchester violation detected" newline bitfld.long 0x0 5. "SYNCD,Synchronization done" "0: Synchronization is pending.,1: Synchronization is completed." bitfld.long 0x0 4. "SBD,Synchronization block detected" "0: No B preamble is detected.,1: B preamble is detected." newline bitfld.long 0x0 3. "OVR,Overrun error" "0: No overrun error,1: Overrun error is detected." bitfld.long 0x0 2. "PERR,Parity error" "0: No parity error,1: Parity error" newline bitfld.long 0x0 1. "CSRNE,Control buffer register not empty" "0: No control word available on SPDIFRX_CSR register,1: A control word is available on SPDIFRX_CSR.." bitfld.long 0x0 0. "RXNE,Read data register not empty" "0: Data is not received.,1: Received data is ready to be read." wgroup.long 0xC++0x3 line.long 0x0 "SPDIFRX_IFCR,SPDIFRX interrupt flag clear register" bitfld.long 0x0 5. "SYNCDCF,clears the synchronization done flag" "0,1" bitfld.long 0x0 4. "SBDCF,clears the synchronization block detected flag" "0,1" newline bitfld.long 0x0 3. "OVRCF,clears the overrun error flag" "0,1" bitfld.long 0x0 2. "PERRCF,clears the parity error flag" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "SPDIFRX_FMT0_DR,SPDIFRX data input register" bitfld.long 0x0 28.--29. "PT,preamble type" "0: not used,1: Preamble B received,2: Preamble M received,3: Preamble W received" bitfld.long 0x0 27. "C,channel status bit" "0,1" newline bitfld.long 0x0 26. "U,user bit" "0,1" bitfld.long 0x0 25. "V,validity bit" "0,1" newline bitfld.long 0x0 24. "PE,parity error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,data value" rgroup.long 0x10++0x3 line.long 0x0 "SPDIFRX_FMT1_DR,SPDIFRX data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,data value" bitfld.long 0x0 4.--5. "PT,preamble type" "0: not used,1: preamble B received,2: preamble M received,3: preamble W received" newline bitfld.long 0x0 3. "C,channel Status bit" "0,1" bitfld.long 0x0 2. "U,user bit" "0,1" newline bitfld.long 0x0 1. "V,validity bit" "0,1" bitfld.long 0x0 0. "PE,parity error bit" "0,1" rgroup.long 0x10++0xB line.long 0x0 "SPDIFRX_FMT2_DR,SPDIFRX data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,data value" line.long 0x4 "SPDIFRX_CSR,SPDIFRX channel status register" bitfld.long 0x4 24. "SOB,start of block" "0: CS[0] is not the first bit of a new block,1: CS[0] is the first bit of a new block" hexmask.long.byte 0x4 16.--23. 1. "CS,channel A status information" newline hexmask.long.word 0x4 0.--15. 1. "USR,user data information" line.long 0x8 "SPDIFRX_DIR,SPDIFRX debug information register" hexmask.long.word 0x8 16.--28. 1. "TLO,threshold LOW (TLO = 1.5 x UI / T less than sub>spdifrx_ker_ck less than /sub>)" hexmask.long.word 0x8 0.--12. 1. "THI,threshold HIGH (THI = 2.5 x UI / T less than sub>spdifrx_ker_ck less than /sub>)" tree.end tree "SPDIFRX_S" base ad:0x50004000 group.long 0x0++0x7 line.long 0x0 "SPDIFRX_CR,SPDIFRX control register" bitfld.long 0x0 21. "CKSBKPEN,Backup symbol clock enable" "0: The SPDIFRX does not generate a backup symbol..,1: The SPDIFRX generates a backup symbol clock if.." bitfld.long 0x0 20. "CKSEN,Symbol clock enable" "0: The SPDIFRX does not generate a symbol clock.,1: The SPDIFRX generates a symbol clock." newline bitfld.long 0x0 16.--18. "INSEL,SPDIFRX input selection" "0: SPDIFRX_IN0 selected,1: SPDIFRX_IN1 selected,2: SPDIFRX_IN2 selected,3: SPDIFRX_IN3 selected,?,?,?,?" bitfld.long 0x0 14. "WFA,Wait for activity less than sup>(1) less than /sup>" "0: The SPDIFRX does not wait for activity on..,1: The SPDIFRX waits for activity on SPDIFRX_IN.." newline bitfld.long 0x0 12.--13. "NBTR,Maximum allowed re-tries during synchronization phase less than sup>(1) less than /sup>" "0: No re-try is allowed (only one attempt),1: 3 re-tries allowed,2: 15 re-tries allowed,3: 63 re-tries allowed" bitfld.long 0x0 11. "CHSEL,Channel selection less than sup>(1) less than /sup>" "0: The control flow takes the channel status from..,1: The control flow takes the channel status from.." newline bitfld.long 0x0 10. "CBDMAEN,Control buffer DMA enable for control flow less than sup>(1) less than /sup>" "0: DMA mode is disabled for reception of channel..,1: DMA mode is enabled for reception of channel.." bitfld.long 0x0 9. "PTMSK,Mask of preamble type bits less than sup>(1) less than /sup>" "0: The preamble type bits are copied into the..,1: The preamble type bits are not copied into the.." newline bitfld.long 0x0 8. "CUMSK,Mask of channel status and user bits less than sup>(1) less than /sup>" "0: The channel status and user bits are copied into..,1: The channel status and user bits are not copied.." bitfld.long 0x0 7. "VMSK,Mask of validity bit less than sup>(1) less than /sup>" "0: The validity bit is copied into the..,1: The validity bit is not copied into the.." newline bitfld.long 0x0 6. "PMSK,Mask parity error bit less than sup>(1) less than /sup>" "0: The parity error bit is copied into the..,1: The parity error bit is not copied into the.." bitfld.long 0x0 4.--5. "DRFMT,RX data format less than sup>(1) less than /sup>" "0: Data samples are aligned in the right (LSB).,1: Data samples are aligned in the left (MSB),2: Data sample are packed by setting two 16-bit..,?" newline bitfld.long 0x0 3. "RXSTEO,Stereo mode less than sup>(1) less than /sup>" "0: The peripheral is in mono mode.,1: The peripheral is in stereo mode." bitfld.long 0x0 2. "RXDMAEN,Receiver DMA enable for data flow less than sup>(1) less than /sup>" "0: DMA mode is disabled for reception.,1: DMA mode is enabled for reception." newline bitfld.long 0x0 0.--1. "SPDIFRXEN,Peripheral block enable less than sup>(1) less than /sup>" "0: Disable SPDIFRX (STATE_IDLE).,1: Enable SPDIFRX synchronization only.,?,3: Enable SPDIF receiver." line.long 0x4 "SPDIFRX_IMR,SPDIFRX interrupt mask register" bitfld.long 0x4 6. "IFEIE,Serial interface error interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." bitfld.long 0x4 5. "SYNCDIE,Synchronization done" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." newline bitfld.long 0x4 4. "SBLKIE,Synchronization block detected interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." bitfld.long 0x4 3. "OVRIE,Overrun error interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." newline bitfld.long 0x4 2. "PERRIE,Parity error interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." bitfld.long 0x4 1. "CSRNEIE,Control buffer ready interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." newline bitfld.long 0x4 0. "RXNEIE,RXNE interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.." rgroup.long 0x8++0x3 line.long 0x0 "SPDIFRX_SR,SPDIFRX status register" hexmask.long.word 0x0 16.--30. 1. "WIDTH5,duration of 5 symbols counted with spdifrx_ker_ck" bitfld.long 0x0 8. "TERR,Time-out error" "0: No sequence error is detected.,1: Sequence error is detected." newline bitfld.long 0x0 7. "SERR,Synchronization error" "0: No synchronization error is detected.,1: Synchronization error is detected." bitfld.long 0x0 6. "FERR,Framing error" "0: No Manchester violation detected,1: Manchester violation detected" newline bitfld.long 0x0 5. "SYNCD,Synchronization done" "0: Synchronization is pending.,1: Synchronization is completed." bitfld.long 0x0 4. "SBD,Synchronization block detected" "0: No B preamble is detected.,1: B preamble is detected." newline bitfld.long 0x0 3. "OVR,Overrun error" "0: No overrun error,1: Overrun error is detected." bitfld.long 0x0 2. "PERR,Parity error" "0: No parity error,1: Parity error" newline bitfld.long 0x0 1. "CSRNE,Control buffer register not empty" "0: No control word available on SPDIFRX_CSR register,1: A control word is available on SPDIFRX_CSR.." bitfld.long 0x0 0. "RXNE,Read data register not empty" "0: Data is not received.,1: Received data is ready to be read." wgroup.long 0xC++0x3 line.long 0x0 "SPDIFRX_IFCR,SPDIFRX interrupt flag clear register" bitfld.long 0x0 5. "SYNCDCF,clears the synchronization done flag" "0,1" bitfld.long 0x0 4. "SBDCF,clears the synchronization block detected flag" "0,1" newline bitfld.long 0x0 3. "OVRCF,clears the overrun error flag" "0,1" bitfld.long 0x0 2. "PERRCF,clears the parity error flag" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "SPDIFRX_FMT0_DR,SPDIFRX data input register" bitfld.long 0x0 28.--29. "PT,preamble type" "0: not used,1: Preamble B received,2: Preamble M received,3: Preamble W received" bitfld.long 0x0 27. "C,channel status bit" "0,1" newline bitfld.long 0x0 26. "U,user bit" "0,1" bitfld.long 0x0 25. "V,validity bit" "0,1" newline bitfld.long 0x0 24. "PE,parity error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,data value" rgroup.long 0x10++0x3 line.long 0x0 "SPDIFRX_FMT1_DR,SPDIFRX data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,data value" bitfld.long 0x0 4.--5. "PT,preamble type" "0: not used,1: preamble B received,2: preamble M received,3: preamble W received" newline bitfld.long 0x0 3. "C,channel Status bit" "0,1" bitfld.long 0x0 2. "U,user bit" "0,1" newline bitfld.long 0x0 1. "V,validity bit" "0,1" bitfld.long 0x0 0. "PE,parity error bit" "0,1" rgroup.long 0x10++0xB line.long 0x0 "SPDIFRX_FMT2_DR,SPDIFRX data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,data value" line.long 0x4 "SPDIFRX_CSR,SPDIFRX channel status register" bitfld.long 0x4 24. "SOB,start of block" "0: CS[0] is not the first bit of a new block,1: CS[0] is the first bit of a new block" hexmask.long.byte 0x4 16.--23. 1. "CS,channel A status information" newline hexmask.long.word 0x4 0.--15. 1. "USR,user data information" line.long 0x8 "SPDIFRX_DIR,SPDIFRX debug information register" hexmask.long.word 0x8 16.--28. 1. "TLO,threshold LOW (TLO = 1.5 x UI / T less than sub>spdifrx_ker_ck less than /sub>)" hexmask.long.word 0x8 0.--12. 1. "THI,threshold HIGH (THI = 2.5 x UI / T less than sub>spdifrx_ker_ck less than /sub>)" tree.end tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x0 tree "SPI1" base ad:0x42003000 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree "SPI1_S" base ad:0x52003000 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree "SPI2_S" base ad:0x50003800 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree "SPI3_S" base ad:0x50003C00 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree "SPI4" base ad:0x42003400 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree "SPI4_S" base ad:0x52003400 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree "SPI5" base ad:0x42005000 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree "SPI5_S" base ad:0x52005000 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree "SPI6" base ad:0x46001400 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree "SPI6_S" base ad:0x56001400 group.long 0x0++0x13 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled" line.long 0x4 "SPI_CR2,SPI/I2S control register 2" hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1" bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled" bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" newline bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" newline bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" newline bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master." hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2" bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.." bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master" bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.." bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.." newline hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" newline bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" newline bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" newline bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" newline bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected." newline bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected" bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" newline bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected" newline bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished" bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete" newline bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.." bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.." newline bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1" bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" newline bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" newline bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" newline bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1" bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter" line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register" bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I less than sup>2 less than /sup>S linear prescaler" bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.." newline bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.." bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.." newline bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" newline bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 58.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.." bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" newline bitfld.long 0x4 4.--5. "I2SSTD,I less than sup>2 less than /sup>S standard selection" "0: I less than sup>2 less than /sup>S Philips..,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?" newline bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" tree.end tree.end tree "SYSCFG (System Configuration Controller)" base ad:0x0 tree "SYSCFG" base ad:0x46008000 group.long 0x0++0x27 line.long 0x0 "SYSCFG_BOOTCR,SYSCFG boot pin control register" bitfld.long 0x0 1. "BOOT1_PD,BOOT1 pin pull-down disable" "0: Pull-down enabled. The BOOT1 pin can be left..,1: Pull-down disabled. The BOOT1 pin must not be.." newline bitfld.long 0x0 0. "BOOT0_PD,BOOT0 pin pull-down disable" "0: Pull-down enabled. The BOOT0 pin can be left..,1: Pull-down disabled. The BOOT0 pin must not be.." line.long 0x4 "SYSCFG_CM55CR,SYSCFG Cortex-M55 control register" bitfld.long 0x4 21. "LOCKDCAIC,Disable access to the instruction cache direct cache access registers DCAICLR and DCAICRR." "0,1" newline bitfld.long 0x4 20. "LOCKSAU,Prevent changes to secure SAU memory regions already programmed." "0,1" newline bitfld.long 0x4 19. "LOCKNSMPU,Prevent changes to non-secure MPU memory regions already programmed." "0,1" newline bitfld.long 0x4 18. "LOCKSMPU,Prevent changes to programmed secure MPU memory regions." "0,1" newline bitfld.long 0x4 17. "LOCKNSVTOR,Prevent changes to the non-secure vector table base address." "0,1" newline bitfld.long 0x4 16. "LOCKSVTAIRCR,Prevent changes to:" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FPU_IT_EN,Enable FPU exception" line.long 0x8 "SYSCFG_CM55TCMCR,SYSCFG Cortex-M55 TCM control register" bitfld.long 0x8 24. "DTCMWSDISABLE,Disable wait-state applied by default on extended DTCM memory." "0,1" newline bitfld.long 0x8 23. "ITCMWSDISABLE,Disable wait-state applied by default on extended ITCM memory." "0,1" newline bitfld.long 0x8 18. "LOCKDTGU,Disable writes to registers associated with the DTCM interface security gating." "0,1" newline bitfld.long 0x8 17. "LOCKITGU,Disable writes to registers associated with the ITCM interface security gating." "0,1" newline bitfld.long 0x8 16. "LOCKTCM,Disable writes to registers associated with the TCM region" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "CFGDTCMSZ,Select DTCM memory size" newline hexmask.long.byte 0x8 0.--3. 1. "CFGITCMSZ,Select ITCM memory size" line.long 0xC "SYSCFG_CM55RWMCR,SYSCFG Cortex-CM55 memory RW margin register" bitfld.long 0xC 13. "BC2_CACHE,Biasing level adjust input recommended for Vnom + 10%" "0,1" newline bitfld.long 0xC 12. "BC1_CACHE,Biasing level adjust input recommended for Vnom." "0,1" newline hexmask.long.byte 0xC 8.--11. 1. "RM_CACHE,External read/write (RW) margin inputs for caches memories" newline bitfld.long 0xC 7. "RME_CACHE,RW margin enable input for caches memories" "0: Default RW margin settings,1: Use external pin RW margin setting" newline bitfld.long 0xC 6. "BC2_TCM,Biasing level adjust input recommended for Vnom + 10%" "0,1" newline bitfld.long 0xC 5. "BC1_TCM,Biasing level adjust input recommended for Vnom" "0,1" newline hexmask.long.byte 0xC 1.--4. 1. "RM_TCM,External RW margin inputs for TCM memories" newline bitfld.long 0xC 0. "RME_TCM,RW margin enable input for TCM memories" "0: Default RW margin settings,1: Use external pin RW margin setting" line.long 0x10 "SYSCFG_INITSVTORCR,SYSCFG Cortex-M55 SVTOR control register" hexmask.long 0x10 7.--31. 1. "SVTOR_ADDR,Secure vector table base address" line.long 0x14 "SYSCFG_INITNSVTORCR,SYSCFG Cortex-M55 NSVTOR control register" hexmask.long 0x14 7.--31. 1. "NSVTOR_ADDR,Non-secure vector table base address" line.long 0x18 "SYSCFG_CM55RSTCR,SYSCFG Cortex-M55 reset type control register" bitfld.long 0x18 2. "LOCKUP_NMI_EN,Select action to perform on a lockup state on the core" "0: Lockup state must be recovered from NVIC..,1: Lockup generates a NMI on the core." newline bitfld.long 0x18 1. "LOCKUP_RST_EN,Select action to perform on a lockup state on the core" "0: Lockup state shall be recovered from interrupt..,1: Lockup requests a warm reset to the RCC." newline bitfld.long 0x18 0. "CORE_RESET_TYPE,Select reset to apply on core upon SYSRESETREQ" "0: Warm reset (default value),1: Power-on reset" line.long 0x1C "SYSCFG_CM55PAHBWPR,SYSCFG Cortex-M55 P-AHB write posting control register" bitfld.long 0x1C 0. "PAHB_ERROR_ACK,Error capture in write posting buffer" "0: Error capture,1: Clean error" line.long 0x20 "SYSCFG_VENCRAMCR,SYSCFG VENCRAM control register" bitfld.long 0x20 0. "VENCRAM_EN,VENCRAM allocation VENC if active or to system (if VENC inactive)" "0: VENCRAM reserved for the VENC,1: VENCRAM available for the system (VENC inactive)" line.long 0x24 "SYSCFG_POTTAMPRSTCR,SYSCFG potential tamper reset register" bitfld.long 0x24 0. "POTTAMPERSETMASK,This bit can be set by software to mask PKA SAES CRYP1/2 and HASH reset in case of potential tamper." "0: PKA SAES CRYP1/2 and HASH reset in case of..,1: PKA SAES CRYP1/2 and HASH not reset in case of.." group.long 0x34++0x13 line.long 0x0 "SYSCFG_ICNEWRCR,SYSCFG AHB-AXI bridge early write response control register" bitfld.long 0x0 3. "USB2_EARLY_WR_RSP_ENABLE,None" "0: Early-write response disabled. The last AHB..,1: Early-write response enabled. AHB-Lite write.." newline bitfld.long 0x0 2. "USB1_EARLY_WR_RSP_ENABLE,None" "0: Early-write response disabled. The last AHB..,1: Early-write response enabled. AHB-Lite write.." newline bitfld.long 0x0 1. "SDMMC2_EARLY_WR_RSP_ENABLE,None" "0: Early-write response disabled. The last AHB..,1: Early-write response enabled. AHB-Lite write.." newline bitfld.long 0x0 0. "SDMMC1_EARLY_WR_RSP_ENABLE,None" "0: Early-write response disabled. The last AHB..,1: Early-write response enabled. AHB-Lite write.." line.long 0x4 "SYSCFG_ICNCGCR,SYSCFG ICN clock gating control register" hexmask.long 0x4 0.--31. 1. "ICNCGCR,When bit[i] is set to 1 ICN clock gating[i] is OFF." line.long 0x8 "SYSCFG_ICNBWRCR,SYSCFG ICN bandwidth regulator control register" hexmask.long 0x8 0.--31. 1. "ICNBWRCR,Bandwidth regulator control bits" line.long 0xC "SYSCFG_IOCR,SYSCFG /O control register" hexmask.long 0xC 0.--31. 1. "IOCR,Digital or analog pins" line.long 0x10 "SYSCFG_VDDIO1CCCR,SYSCFG VDDIO1 compensation cell control register" bitfld.long 0x10 9. "CS,Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O code from the cell (available in the..,1: VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0].." newline bitfld.long 0x10 8. "EN,Enables the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O compensation cell disabled,1: VDDIOx I/O compensation cell enabled" newline hexmask.long.byte 0x10 4.--7. 1. "RAPSRC,These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." newline hexmask.long.byte 0x10 0.--3. 1. "RANSRC,These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." rgroup.long 0x48++0x3 line.long 0x0 "SYSCFG_VDDIO1CCSR,SYSCFG VDDIO1 compensation cell status register" bitfld.long 0x0 8. "READY,Provides the compensation cell status of I/Os supplied by VDDIOx" "0: VDDIOx I/O compensation cell not ready,1: VDDIOx I/O compensation cell ready" newline hexmask.long.byte 0x0 4.--7. 1. "APSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." newline hexmask.long.byte 0x0 0.--3. 1. "ANSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." group.long 0x4C++0x3 line.long 0x0 "SYSCFG_VDDIO2CCCR,SYSCFG VDDIO2 compensation cell control register" bitfld.long 0x0 9. "CS,Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O code from the cell (available in the..,1: VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0].." newline bitfld.long 0x0 8. "EN,Enables the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O compensation cell disabled,1: VDDIOx I/O compensation cell enabled" newline hexmask.long.byte 0x0 4.--7. 1. "RAPSRC,These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." newline hexmask.long.byte 0x0 0.--3. 1. "RANSRC,These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." rgroup.long 0x50++0x3 line.long 0x0 "SYSCFG_VDDIO2CCSR,SYSCFG VDDIO2 compensation cell status register" bitfld.long 0x0 8. "READY,Provides the compensation cell status of I/Os supplied by VDDIOx" "0: VDDIOx I/O compensation cell not ready,1: VDDIOx I/O compensation cell ready" newline hexmask.long.byte 0x0 4.--7. 1. "APSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." newline hexmask.long.byte 0x0 0.--3. 1. "ANSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." group.long 0x54++0x3 line.long 0x0 "SYSCFG_VDDIO3CCCR,SYSCFG VDDIO3 compensation cell control register" bitfld.long 0x0 9. "CS,Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O code from the cell (available in the..,1: VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0].." newline bitfld.long 0x0 8. "EN,Enables the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O compensation cell disabled,1: VDDIOx I/O compensation cell enabled" newline hexmask.long.byte 0x0 4.--7. 1. "RAPSRC,These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." newline hexmask.long.byte 0x0 0.--3. 1. "RANSRC,These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." rgroup.long 0x58++0x3 line.long 0x0 "SYSCFG_VDDIO3CCSR,SYSCFG VDDIO3 compensation cell status register" bitfld.long 0x0 8. "READY,Provides the compensation cell status of I/Os supplied by VDDIOx" "0: VDDIOx I/O compensation cell not ready,1: VDDIOx I/O compensation cell ready" newline hexmask.long.byte 0x0 4.--7. 1. "APSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." newline hexmask.long.byte 0x0 0.--3. 1. "ANSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." group.long 0x5C++0x3 line.long 0x0 "SYSCFG_VDDIO4CCCR,SYSCFG VDDIO4 compensation cell control register" bitfld.long 0x0 9. "CS,Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O code from the cell (available in the..,1: VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0].." newline bitfld.long 0x0 8. "EN,Enables the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O compensation cell disabled,1: VDDIOx I/O compensation cell enabled" newline hexmask.long.byte 0x0 4.--7. 1. "RAPSRC,These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." newline hexmask.long.byte 0x0 0.--3. 1. "RANSRC,These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." rgroup.long 0x60++0x3 line.long 0x0 "SYSCFG_VDDIO4CCSR,SYSCFG VDDIO4 compensation cell status register" bitfld.long 0x0 8. "READY,Provides the compensation cell status of I/Os supplied by VDDIOx" "0: VDDIOx I/O compensation cell not ready,1: VDDIOx I/O compensation cell ready" newline hexmask.long.byte 0x0 4.--7. 1. "APSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." newline hexmask.long.byte 0x0 0.--3. 1. "ANSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." group.long 0x64++0x3 line.long 0x0 "SYSCFG_VDDIOCCCR,SYSCFG VDDIO compensation cell control register" bitfld.long 0x0 9. "CS,Selects the code to be applied for the compensation cell of I/Os supplied by VDDIO." "0: VDDIO I/O code from the cell (available in the..,1: VDDIO I/O code from RANSRC[3:0] and RAPSRC[3:0]" newline bitfld.long 0x0 8. "EN,Enables the compensation cell of I/Os supplied by VDDIO." "0: VDDIO I/O compensation cell disabled,1: VDDIO I/O compensation cell enabled" newline hexmask.long.byte 0x0 4.--7. 1. "RAPSRC,These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." newline hexmask.long.byte 0x0 0.--3. 1. "RANSRC,These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when CS = 1." rgroup.long 0x68++0x3 line.long 0x0 "SYSCFG_VDDIOCCSR,SYSCFG VDDIO compensation cell status register" bitfld.long 0x0 8. "READY,Provides the compensation cell status of I/Os supplied by VDDIO" "0: VDDIO I/O compensation cell not ready,1: VDDIO I/O compensation cell ready" newline hexmask.long.byte 0x0 4.--7. 1. "APSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." newline hexmask.long.byte 0x0 0.--3. 1. "ANSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." group.long 0x6C++0xF line.long 0x0 "SYSCFG_CBR,SYSCFG control timer break register" bitfld.long 0x0 6. "CM55TCML,CM55 TCM double ECC error lock" "0: Cortex-M55 TCM double ECC error signal..,1: Cortex-M55 TCM double ECC error signal connected.." newline bitfld.long 0x0 5. "CM55CACHEL,CM55 cache double ECC error lock" "0: Cortex-M55 cache double ECC error signal..,1: Cortex-M55 cache double ECC error signal.." newline bitfld.long 0x0 3. "BKPRAML,Backup SRAM double ECC error lock" "0: Backup SRAM double ECC error signal disconnected..,1: Backup SRAM double ECC error signal connected to.." newline bitfld.long 0x0 2. "PVDL_LOCK,PVD lock enable" "0: PVD interrupt disconnected from TIM1/8/15/16/17..,1: PVD interrupt connected to TIM1/8/15/16/17 break.." newline bitfld.long 0x0 0. "CM55L,CM55 lockup lock enable" "0: Cortex-M55 lockup output disconnected from..,1: Cortex-M55 lockup output disconnected from.." line.long 0x4 "SYSCFG_SEC_AIDCR,SYSCFG DMA CID secure control register" bitfld.long 0x4 0.--2. "DMACID_SEC,Secure OS allocates specific CID to DMA channel through these bits." "0,1,2,3,4,5,6,7" line.long 0x8 "SYSCFG_FMC_RETIMECR,SYSCFG FMC retiming logic control register" bitfld.long 0x8 2. "SDFBCLK_180,Delay on feedback clock" "0: No delay on the feedback clock,1: Half a cycle delay on the feedback clock" newline bitfld.long 0x8 1. "CFG_RETIME_TX,Retiming on Tx path" "0: No retiming on Tx path,1: Retiming on Tx path" newline bitfld.long 0x8 0. "CFG_RETIME_RX,Retiming on Rx path" "0: No retiming on Rx path,1: Retiming on Rx path" line.long 0xC "SYSCFG_NPU_ICNCR,SYSCFG NPU RAM interleaving control register" bitfld.long 0xC 0. "INTERLEAVING_ACTIVE,Control interleaving on NPU RAMs" "0: Interleaving disabled,1: Interleaving enabled" rgroup.long 0x100++0x7 line.long 0x0 "SYSCFG_BOOTSR,SYSCFG boot pin status register" bitfld.long 0x0 1. "BOOT1,BOOT1 pin value" "0: BOOT1 pin connected to VSS (or left open if..,1: BOOT1 pin connected to VDD" newline bitfld.long 0x0 0. "BOOT0,BOOT0 pin value" "0: BOOT0 pin connected to VSS (or left open if..,1: BOOT0 pin connected to VDD" line.long 0x4 "SYSCFG_AHBWP_ERROR_SR,SYSCFG AHB write posting address error register" hexmask.long 0x4 0.--31. 1. "PAHB_ERROR_ADDR,Reports address of the first error in P-AHB write-posting buffer" group.long 0x400++0x3 line.long 0x0 "SYSCFG_SMPSHDPCR,SYSCFG SMPS observable signals through HDP selection configuration register" hexmask.long.byte 0x0 0.--3. 1. "SMPSHDPSEL,Others: Reserved" group.long 0x800++0x3 line.long 0x0 "SYSCFG_NONSEC_AIDCR,SYSCFG DMA CID non-secure control register" bitfld.long 0x0 0.--2. "DMACID_NONSEC,Non-secure OS allocates specific CID to DMA channel through these bits" "0,1,2,3,4,5,6,7" tree.end tree "SYSCFG_S" base ad:0x56008000 group.long 0x0++0x27 line.long 0x0 "SYSCFG_BOOTCR,SYSCFG boot pin control register" bitfld.long 0x0 1. "BOOT1_PD,BOOT1 pin pull-down disable" "0: Pull-down enabled. The BOOT1 pin can be left..,1: Pull-down disabled. The BOOT1 pin must not be.." newline bitfld.long 0x0 0. "BOOT0_PD,BOOT0 pin pull-down disable" "0: Pull-down enabled. The BOOT0 pin can be left..,1: Pull-down disabled. The BOOT0 pin must not be.." line.long 0x4 "SYSCFG_CM55CR,SYSCFG Cortex-M55 control register" bitfld.long 0x4 21. "LOCKDCAIC,Disable access to the instruction cache direct cache access registers DCAICLR and DCAICRR." "0,1" newline bitfld.long 0x4 20. "LOCKSAU,Prevent changes to secure SAU memory regions already programmed." "0,1" newline bitfld.long 0x4 19. "LOCKNSMPU,Prevent changes to non-secure MPU memory regions already programmed." "0,1" newline bitfld.long 0x4 18. "LOCKSMPU,Prevent changes to programmed secure MPU memory regions." "0,1" newline bitfld.long 0x4 17. "LOCKNSVTOR,Prevent changes to the non-secure vector table base address." "0,1" newline bitfld.long 0x4 16. "LOCKSVTAIRCR,Prevent changes to:" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FPU_IT_EN,Enable FPU exception" line.long 0x8 "SYSCFG_CM55TCMCR,SYSCFG Cortex-M55 TCM control register" bitfld.long 0x8 24. "DTCMWSDISABLE,Disable wait-state applied by default on extended DTCM memory." "0,1" newline bitfld.long 0x8 23. "ITCMWSDISABLE,Disable wait-state applied by default on extended ITCM memory." "0,1" newline bitfld.long 0x8 18. "LOCKDTGU,Disable writes to registers associated with the DTCM interface security gating." "0,1" newline bitfld.long 0x8 17. "LOCKITGU,Disable writes to registers associated with the ITCM interface security gating." "0,1" newline bitfld.long 0x8 16. "LOCKTCM,Disable writes to registers associated with the TCM region" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "CFGDTCMSZ,Select DTCM memory size" newline hexmask.long.byte 0x8 0.--3. 1. "CFGITCMSZ,Select ITCM memory size" line.long 0xC "SYSCFG_CM55RWMCR,SYSCFG Cortex-CM55 memory RW margin register" bitfld.long 0xC 13. "BC2_CACHE,Biasing level adjust input recommended for Vnom + 10%" "0,1" newline bitfld.long 0xC 12. "BC1_CACHE,Biasing level adjust input recommended for Vnom." "0,1" newline hexmask.long.byte 0xC 8.--11. 1. "RM_CACHE,External read/write (RW) margin inputs for caches memories" newline bitfld.long 0xC 7. "RME_CACHE,RW margin enable input for caches memories" "0: Default RW margin settings,1: Use external pin RW margin setting" newline bitfld.long 0xC 6. "BC2_TCM,Biasing level adjust input recommended for Vnom + 10%" "0,1" newline bitfld.long 0xC 5. "BC1_TCM,Biasing level adjust input recommended for Vnom" "0,1" newline hexmask.long.byte 0xC 1.--4. 1. "RM_TCM,External RW margin inputs for TCM memories" newline bitfld.long 0xC 0. "RME_TCM,RW margin enable input for TCM memories" "0: Default RW margin settings,1: Use external pin RW margin setting" line.long 0x10 "SYSCFG_INITSVTORCR,SYSCFG Cortex-M55 SVTOR control register" hexmask.long 0x10 7.--31. 1. "SVTOR_ADDR,Secure vector table base address" line.long 0x14 "SYSCFG_INITNSVTORCR,SYSCFG Cortex-M55 NSVTOR control register" hexmask.long 0x14 7.--31. 1. "NSVTOR_ADDR,Non-secure vector table base address" line.long 0x18 "SYSCFG_CM55RSTCR,SYSCFG Cortex-M55 reset type control register" bitfld.long 0x18 2. "LOCKUP_NMI_EN,Select action to perform on a lockup state on the core" "0: Lockup state must be recovered from NVIC..,1: Lockup generates a NMI on the core." newline bitfld.long 0x18 1. "LOCKUP_RST_EN,Select action to perform on a lockup state on the core" "0: Lockup state shall be recovered from interrupt..,1: Lockup requests a warm reset to the RCC." newline bitfld.long 0x18 0. "CORE_RESET_TYPE,Select reset to apply on core upon SYSRESETREQ" "0: Warm reset (default value),1: Power-on reset" line.long 0x1C "SYSCFG_CM55PAHBWPR,SYSCFG Cortex-M55 P-AHB write posting control register" bitfld.long 0x1C 0. "PAHB_ERROR_ACK,Error capture in write posting buffer" "0: Error capture,1: Clean error" line.long 0x20 "SYSCFG_VENCRAMCR,SYSCFG VENCRAM control register" bitfld.long 0x20 0. "VENCRAM_EN,VENCRAM allocation VENC if active or to system (if VENC inactive)" "0: VENCRAM reserved for the VENC,1: VENCRAM available for the system (VENC inactive)" line.long 0x24 "SYSCFG_POTTAMPRSTCR,SYSCFG potential tamper reset register" bitfld.long 0x24 0. "POTTAMPERSETMASK,This bit can be set by software to mask PKA SAES CRYP1/2 and HASH reset in case of potential tamper." "0: PKA SAES CRYP1/2 and HASH reset in case of..,1: PKA SAES CRYP1/2 and HASH not reset in case of.." group.long 0x34++0x13 line.long 0x0 "SYSCFG_ICNEWRCR,SYSCFG AHB-AXI bridge early write response control register" bitfld.long 0x0 3. "USB2_EARLY_WR_RSP_ENABLE,None" "0: Early-write response disabled. The last AHB..,1: Early-write response enabled. AHB-Lite write.." newline bitfld.long 0x0 2. "USB1_EARLY_WR_RSP_ENABLE,None" "0: Early-write response disabled. The last AHB..,1: Early-write response enabled. AHB-Lite write.." newline bitfld.long 0x0 1. "SDMMC2_EARLY_WR_RSP_ENABLE,None" "0: Early-write response disabled. The last AHB..,1: Early-write response enabled. AHB-Lite write.." newline bitfld.long 0x0 0. "SDMMC1_EARLY_WR_RSP_ENABLE,None" "0: Early-write response disabled. The last AHB..,1: Early-write response enabled. AHB-Lite write.." line.long 0x4 "SYSCFG_ICNCGCR,SYSCFG ICN clock gating control register" hexmask.long 0x4 0.--31. 1. "ICNCGCR,When bit[i] is set to 1 ICN clock gating[i] is OFF." line.long 0x8 "SYSCFG_ICNBWRCR,SYSCFG ICN bandwidth regulator control register" hexmask.long 0x8 0.--31. 1. "ICNBWRCR,Bandwidth regulator control bits" line.long 0xC "SYSCFG_IOCR,SYSCFG /O control register" hexmask.long 0xC 0.--31. 1. "IOCR,Digital or analog pins" line.long 0x10 "SYSCFG_VDDIO1CCCR,SYSCFG VDDIO1 compensation cell control register" bitfld.long 0x10 9. "CS,Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O code from the cell (available in the..,1: VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0].." newline bitfld.long 0x10 8. "EN,Enables the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O compensation cell disabled,1: VDDIOx I/O compensation cell enabled" newline hexmask.long.byte 0x10 4.--7. 1. "RAPSRC,These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." newline hexmask.long.byte 0x10 0.--3. 1. "RANSRC,These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." rgroup.long 0x48++0x3 line.long 0x0 "SYSCFG_VDDIO1CCSR,SYSCFG VDDIO1 compensation cell status register" bitfld.long 0x0 8. "READY,Provides the compensation cell status of I/Os supplied by VDDIOx" "0: VDDIOx I/O compensation cell not ready,1: VDDIOx I/O compensation cell ready" newline hexmask.long.byte 0x0 4.--7. 1. "APSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." newline hexmask.long.byte 0x0 0.--3. 1. "ANSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." group.long 0x4C++0x3 line.long 0x0 "SYSCFG_VDDIO2CCCR,SYSCFG VDDIO2 compensation cell control register" bitfld.long 0x0 9. "CS,Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O code from the cell (available in the..,1: VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0].." newline bitfld.long 0x0 8. "EN,Enables the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O compensation cell disabled,1: VDDIOx I/O compensation cell enabled" newline hexmask.long.byte 0x0 4.--7. 1. "RAPSRC,These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." newline hexmask.long.byte 0x0 0.--3. 1. "RANSRC,These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." rgroup.long 0x50++0x3 line.long 0x0 "SYSCFG_VDDIO2CCSR,SYSCFG VDDIO2 compensation cell status register" bitfld.long 0x0 8. "READY,Provides the compensation cell status of I/Os supplied by VDDIOx" "0: VDDIOx I/O compensation cell not ready,1: VDDIOx I/O compensation cell ready" newline hexmask.long.byte 0x0 4.--7. 1. "APSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." newline hexmask.long.byte 0x0 0.--3. 1. "ANSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." group.long 0x54++0x3 line.long 0x0 "SYSCFG_VDDIO3CCCR,SYSCFG VDDIO3 compensation cell control register" bitfld.long 0x0 9. "CS,Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O code from the cell (available in the..,1: VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0].." newline bitfld.long 0x0 8. "EN,Enables the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O compensation cell disabled,1: VDDIOx I/O compensation cell enabled" newline hexmask.long.byte 0x0 4.--7. 1. "RAPSRC,These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." newline hexmask.long.byte 0x0 0.--3. 1. "RANSRC,These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." rgroup.long 0x58++0x3 line.long 0x0 "SYSCFG_VDDIO3CCSR,SYSCFG VDDIO3 compensation cell status register" bitfld.long 0x0 8. "READY,Provides the compensation cell status of I/Os supplied by VDDIOx" "0: VDDIOx I/O compensation cell not ready,1: VDDIOx I/O compensation cell ready" newline hexmask.long.byte 0x0 4.--7. 1. "APSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." newline hexmask.long.byte 0x0 0.--3. 1. "ANSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." group.long 0x5C++0x3 line.long 0x0 "SYSCFG_VDDIO4CCCR,SYSCFG VDDIO4 compensation cell control register" bitfld.long 0x0 9. "CS,Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O code from the cell (available in the..,1: VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0].." newline bitfld.long 0x0 8. "EN,Enables the compensation cell of I/Os supplied by VDDIOx." "0: VDDIOx I/O compensation cell disabled,1: VDDIOx I/O compensation cell enabled" newline hexmask.long.byte 0x0 4.--7. 1. "RAPSRC,These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." newline hexmask.long.byte 0x0 0.--3. 1. "RANSRC,These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." rgroup.long 0x60++0x3 line.long 0x0 "SYSCFG_VDDIO4CCSR,SYSCFG VDDIO4 compensation cell status register" bitfld.long 0x0 8. "READY,Provides the compensation cell status of I/Os supplied by VDDIOx" "0: VDDIOx I/O compensation cell not ready,1: VDDIOx I/O compensation cell ready" newline hexmask.long.byte 0x0 4.--7. 1. "APSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." newline hexmask.long.byte 0x0 0.--3. 1. "ANSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." group.long 0x64++0x3 line.long 0x0 "SYSCFG_VDDIOCCCR,SYSCFG VDDIO compensation cell control register" bitfld.long 0x0 9. "CS,Selects the code to be applied for the compensation cell of I/Os supplied by VDDIO." "0: VDDIO I/O code from the cell (available in the..,1: VDDIO I/O code from RANSRC[3:0] and RAPSRC[3:0]" newline bitfld.long 0x0 8. "EN,Enables the compensation cell of I/Os supplied by VDDIO." "0: VDDIO I/O compensation cell disabled,1: VDDIO I/O compensation cell enabled" newline hexmask.long.byte 0x0 4.--7. 1. "RAPSRC,These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." newline hexmask.long.byte 0x0 0.--3. 1. "RANSRC,These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when CS = 1." rgroup.long 0x68++0x3 line.long 0x0 "SYSCFG_VDDIOCCSR,SYSCFG VDDIO compensation cell status register" bitfld.long 0x0 8. "READY,Provides the compensation cell status of I/Os supplied by VDDIO" "0: VDDIO I/O compensation cell not ready,1: VDDIO I/O compensation cell ready" newline hexmask.long.byte 0x0 4.--7. 1. "APSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." newline hexmask.long.byte 0x0 0.--3. 1. "ANSRC,This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." group.long 0x6C++0xF line.long 0x0 "SYSCFG_CBR,SYSCFG control timer break register" bitfld.long 0x0 6. "CM55TCML,CM55 TCM double ECC error lock" "0: Cortex-M55 TCM double ECC error signal..,1: Cortex-M55 TCM double ECC error signal connected.." newline bitfld.long 0x0 5. "CM55CACHEL,CM55 cache double ECC error lock" "0: Cortex-M55 cache double ECC error signal..,1: Cortex-M55 cache double ECC error signal.." newline bitfld.long 0x0 3. "BKPRAML,Backup SRAM double ECC error lock" "0: Backup SRAM double ECC error signal disconnected..,1: Backup SRAM double ECC error signal connected to.." newline bitfld.long 0x0 2. "PVDL_LOCK,PVD lock enable" "0: PVD interrupt disconnected from TIM1/8/15/16/17..,1: PVD interrupt connected to TIM1/8/15/16/17 break.." newline bitfld.long 0x0 0. "CM55L,CM55 lockup lock enable" "0: Cortex-M55 lockup output disconnected from..,1: Cortex-M55 lockup output disconnected from.." line.long 0x4 "SYSCFG_SEC_AIDCR,SYSCFG DMA CID secure control register" bitfld.long 0x4 0.--2. "DMACID_SEC,Secure OS allocates specific CID to DMA channel through these bits." "0,1,2,3,4,5,6,7" line.long 0x8 "SYSCFG_FMC_RETIMECR,SYSCFG FMC retiming logic control register" bitfld.long 0x8 2. "SDFBCLK_180,Delay on feedback clock" "0: No delay on the feedback clock,1: Half a cycle delay on the feedback clock" newline bitfld.long 0x8 1. "CFG_RETIME_TX,Retiming on Tx path" "0: No retiming on Tx path,1: Retiming on Tx path" newline bitfld.long 0x8 0. "CFG_RETIME_RX,Retiming on Rx path" "0: No retiming on Rx path,1: Retiming on Rx path" line.long 0xC "SYSCFG_NPU_ICNCR,SYSCFG NPU RAM interleaving control register" bitfld.long 0xC 0. "INTERLEAVING_ACTIVE,Control interleaving on NPU RAMs" "0: Interleaving disabled,1: Interleaving enabled" rgroup.long 0x100++0x7 line.long 0x0 "SYSCFG_BOOTSR,SYSCFG boot pin status register" bitfld.long 0x0 1. "BOOT1,BOOT1 pin value" "0: BOOT1 pin connected to VSS (or left open if..,1: BOOT1 pin connected to VDD" newline bitfld.long 0x0 0. "BOOT0,BOOT0 pin value" "0: BOOT0 pin connected to VSS (or left open if..,1: BOOT0 pin connected to VDD" line.long 0x4 "SYSCFG_AHBWP_ERROR_SR,SYSCFG AHB write posting address error register" hexmask.long 0x4 0.--31. 1. "PAHB_ERROR_ADDR,Reports address of the first error in P-AHB write-posting buffer" group.long 0x400++0x3 line.long 0x0 "SYSCFG_SMPSHDPCR,SYSCFG SMPS observable signals through HDP selection configuration register" hexmask.long.byte 0x0 0.--3. 1. "SMPSHDPSEL,Others: Reserved" group.long 0x800++0x3 line.long 0x0 "SYSCFG_NONSEC_AIDCR,SYSCFG DMA CID non-secure control register" bitfld.long 0x0 0.--2. "DMACID_NONSEC,Non-secure OS allocates specific CID to DMA channel through these bits" "0,1,2,3,4,5,6,7" tree.end tree.end tree "TAMP (Tamper and Backup)" base ad:0x0 tree "TAMP" base ad:0x46004400 group.long 0x0++0x13 line.long 0x0 "TAMP_CR1,TAMP control register 1" bitfld.long 0x0 26. "ITAMP11E,Internal tamper 11 enable" "0: Internal tamper 11 disabled.,1: Internal tamper 11 enabled." bitfld.long 0x0 24. "ITAMP9E,Internal tamper 9 enable" "0: Internal tamper 9 disabled.,1: Internal tamper 9 enabled." newline bitfld.long 0x0 23. "ITAMP8E,Internal tamper 8 enable" "0: Internal tamper 8 disabled.,1: Internal tamper 8 enabled." bitfld.long 0x0 22. "ITAMP7E,Internal tamper 7 enable" "0: Internal tamper 7 disabled.,1: Internal tamper 7 enabled" newline bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled." bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled." newline bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled." bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled." newline bitfld.long 0x0 17. "ITAMP2E,Internal tamper 2 enable" "0: Internal tamper 2 disabled.,1: Internal tamper 2 enabled." bitfld.long 0x0 16. "ITAMP1E,Internal tamper 1 enable" "0: Internal tamper 1 disabled.,1: Internal tamper 1 enabled." newline bitfld.long 0x0 6. "TAMP7E,Tamper detection on TAMP_IN7 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN7 is disabled.,1: Tamper detection on TAMP_IN7 is enabled." bitfld.long 0x0 5. "TAMP6E,Tamper detection on TAMP_IN6 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN6 is disabled.,1: Tamper detection on TAMP_IN6 is enabled." newline bitfld.long 0x0 4. "TAMP5E,Tamper detection on TAMP_IN5 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN5 is disabled.,1: Tamper detection on TAMP_IN5 is enabled." bitfld.long 0x0 3. "TAMP4E,Tamper detection on TAMP_IN4 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN4 is disabled.,1: Tamper detection on TAMP_IN4 is enabled." newline bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled." bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled." newline bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled." line.long 0x4 "TAMP_CR2,TAMP control register 2" bitfld.long 0x4 30. "TAMP7TRG,Active level for tamper 7 input (active mode disabled)" "0: If TAMPFLT different 00 tamper 7 input staying..,1: If TAMPFLT different 00 tamper 7 input staying.." bitfld.long 0x4 29. "TAMP6TRG,Active level for tamper 6 input (active mode disabled)" "0: If TAMPFLT different 00 tamper 6 input staying..,1: If TAMPFLT different 00 tamper 6 input staying.." newline bitfld.long 0x4 28. "TAMP5TRG,Active level for tamper 5 input (active mode disabled)" "0: If TAMPFLT different 00 tamper 5 input staying..,1: If TAMPFLT different 00 tamper 5 input staying.." bitfld.long 0x4 27. "TAMP4TRG,Active level for tamper 4 input (active mode disabled)" "0: If TAMPFLT different 00 tamper 4 input staying..,1: If TAMPFLT different 00 tamper 4 input staying.." newline bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input" "0: If TAMPFLT different 00 tamper 3 input staying..,1: If TAMPFLT different 00 tamper 3 input staying.." bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input" "0: If TAMPFLT different 00 tamper 2 input staying..,1: If TAMPFLT different 00 tamper 2 input staying.." newline bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input" "0: If TAMPFLT different 00 tamper 1 input staying..,1: If TAMPFLT different 00 tamper 1 input staying.." bitfld.long 0x4 23. "BKERASE,Backup registers and device secrets less than sup>(1) less than /sup> erase" "0,1" newline bitfld.long 0x4 22. "BKBLOCK,Backup registers and device secrets less than sup>(1) less than /sup> access blocked" "0: backup registers and device secrets less than..,1: backup registers and device secrets less than.." bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.." newline bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.." bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.." newline bitfld.long 0x4 6. "TAMP7POM,Tamper 7 potential mode" "0: Tamper 7 event detection is in confirmed mode..,1: Tamper 7 event detection is in potential mode.." bitfld.long 0x4 5. "TAMP6POM,Tamper 6 potential mode" "0: Tamper 6 event detection is in confirmed mode..,1: Tamper 6 event detection is in potential mode.." newline bitfld.long 0x4 4. "TAMP5POM,Tamper 5 potential mode" "0: Tamper 5 event detection is in confirmed mode..,1: Tamper 5 event detection is in potential mode.." bitfld.long 0x4 3. "TAMP4POM,Tamper 4 potential mode" "0: Tamper 4 event detection is in confirmed mode..,1: Tamper 4 event detection is in potential mode.." newline bitfld.long 0x4 2. "TAMP3POM,Tamper 3 potential mode" "0: Tamper 3 event detection is in confirmed mode..,1: Tamper 3 event detection is in potential mode.." bitfld.long 0x4 1. "TAMP2POM,Tamper 2 potential mode" "0: Tamper 2 event detection is in confirmed mode..,1: Tamper 2 event detection is in potential mode.." newline bitfld.long 0x4 0. "TAMP1POM,Tamper 1 potential mode" "0: Tamper 1 event detection is in confirmed mode.,1: Tamper 1 event detection is in potential mode." line.long 0x8 "TAMP_CR3,TAMP control register 3" bitfld.long 0x8 10. "ITAMP11POM,Internal tamper 11 potential mode" "0: Internal tamper 11 event detection is in..,1: Internal tamper 11 event detection is in.." bitfld.long 0x8 8. "ITAMP9POM,Internal tamper 9 potential mode" "0: Internal tamper 9 event detection is in..,1: Internal tamper 9 event detection is in.." newline bitfld.long 0x8 7. "ITAMP8POM,Internal tamper 8 potential mode" "0: Internal tamper 8 event detection is in..,1: Internal tamper 8 event detection is in.." bitfld.long 0x8 6. "ITAMP7POM,Internal tamper 7 potential mode" "0: Internal tamper 7 event detection is in..,1: Internal tamper 7 event detection is in.." newline bitfld.long 0x8 5. "ITAMP6POM,Internal tamper 6 potential mode" "0: Internal tamper 6 event detection is in..,1: Internal tamper 6 event detection is in.." bitfld.long 0x8 4. "ITAMP5POM,Internal tamper 5 potential mode" "0: Internal tamper 5 event detection is in..,1: Internal tamper 5 event detection is in.." newline bitfld.long 0x8 3. "ITAMP4POM,Internal tamper 4 potential mode" "0: Internal tamper 4 event detection is in..,1: Internal tamper 4 event detection is in.." bitfld.long 0x8 2. "ITAMP3POM,Internal tamper 3 potential mode" "0: Internal tamper 3 event detection is in..,1: Internal tamper 3 event detection is in.." newline bitfld.long 0x8 1. "ITAMP2POM,Internal tamper 2 potential mode" "0: Internal tamper 2 event detection is in..,1: Internal tamper 2 event detection is in.." bitfld.long 0x8 0. "ITAMP1POM,Internal tamper 1 potential mode" "0: Internal tamper 1 event detection is in..,1: Internal tamper 1 event detection is in.." line.long 0xC "TAMP_FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins." bitfld.long 0xC 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles" newline bitfld.long 0xC 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.." bitfld.long 0xC 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)" line.long 0x10 "TAMP_ATCR1,TAMP active tamper control register 1" bitfld.long 0x10 31. "FLTEN,Active tamper filter enable" "0: Active tamper filtering disable,1: Active tamper filtering enable: a tamper event.." bitfld.long 0x10 30. "ATOSHARE,Active tamper output sharing" "0: Each active tamper input TAMP_INi is compared..,1: Each active tamper input TAMP_INi is compared.." newline bitfld.long 0x10 24.--26. "ATPER,Active tamper output change period" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 16.--19. 1. "ATCKSEL,Active tamper RTC asynchronous prescaler clock selection" newline bitfld.long 0x10 14.--15. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4" bitfld.long 0x10 12.--13. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4" newline bitfld.long 0x10 10.--11. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4" bitfld.long 0x10 8.--9. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4" newline bitfld.long 0x10 6. "TAMP7AM,Tamper 7 active mode" "0: Tamper 7 detection mode is passive.,1: Tamper 7 detection mode is active." bitfld.long 0x10 5. "TAMP6AM,Tamper 6 active mode" "0: Tamper 6 detection mode is passive.,1: Tamper 6 detection mode is active." newline bitfld.long 0x10 4. "TAMP5AM,Tamper 5 active mode" "0: Tamper 5 detection mode is passive.,1: Tamper 5 detection mode is active." bitfld.long 0x10 3. "TAMP4AM,Tamper 4 active mode" "0: Tamper 4 detection mode is passive.,1: Tamper 4 detection mode is active." newline bitfld.long 0x10 2. "TAMP3AM,Tamper 3 active mode" "0: Tamper 3 detection mode is passive.,1: Tamper 3 detection mode is active." bitfld.long 0x10 1. "TAMP2AM,Tamper 2 active mode" "0: Tamper 2 detection mode is passive.,1: Tamper 2 detection mode is active." newline bitfld.long 0x10 0. "TAMP1AM,Tamper 1 active mode" "0: Tamper 1 detection mode is passive.,1: Tamper 1 detection mode is active." wgroup.long 0x14++0x3 line.long 0x0 "TAMP_ATSEEDR,TAMP active tamper seed register" hexmask.long 0x0 0.--31. 1. "SEED,Pseudo-random generator seed value" rgroup.long 0x18++0x3 line.long 0x0 "TAMP_ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,Active tamper initialization status" "0,1" bitfld.long 0x0 14. "SEEDF,Seed running flag" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PRNG,Pseudo-random generator value" group.long 0x1C++0xB line.long 0x0 "TAMP_ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 26.--28. "ATOSEL7,Active tamper shared output 7 selection" "0: TAMPOUTSEL7 = TAMP_OUT1,1: TAMPOUTSEL7 = TAMP_OUT2,2: TAMPOUTSEL7 = TAMP_OUT3,3: TAMPOUTSEL7 = TAMP_OUT4,4: TAMPOUTSEL7 = TAMP_OUT5,5: TAMPOUTSEL7 = TAMP_OUT6,6: TAMPOUTSEL7 = TAMP_OUT7,7: TAMPOUTSEL7 = TAMP_OUT8" bitfld.long 0x0 23.--25. "ATOSEL6,Active tamper shared output 6 selection" "0: TAMPOUTSEL6 = TAMP_OUT1,1: TAMPOUTSEL6 = TAMP_OUT2,2: TAMPOUTSEL6 = TAMP_OUT3,3: TAMPOUTSEL6 = TAMP_OUT4,4: TAMPOUTSEL6 = TAMP_OUT5,5: TAMPOUTSEL6 = TAMP_OUT6,6: TAMPOUTSEL6 = TAMP_OUT7,7: TAMPOUTSEL6 = TAMP_OUT8" newline bitfld.long 0x0 20.--22. "ATOSEL5,Active tamper shared output 5 selection" "0: TAMPOUTSEL5 = TAMP_OUT1,1: TAMPOUTSEL5 = TAMP_OUT2,2: TAMPOUTSEL5 = TAMP_OUT3,3: TAMPOUTSEL5 = TAMP_OUT4,4: TAMPOUTSEL5 = TAMP_OUT5,5: TAMPOUTSEL5 = TAMP_OUT6,6: TAMPOUTSEL5 = TAMP_OUT7,7: TAMPOUTSEL5 = TAMP_OUT8" bitfld.long 0x0 17.--19. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4,4: TAMPOUTSEL4 = TAMP_OUT5,5: TAMPOUTSEL4 = TAMP_OUT6,6: TAMPOUTSEL4 = TAMP_OUT7,7: TAMPOUTSEL4 = TAMP_OUT8" newline bitfld.long 0x0 14.--16. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4,4: TAMPOUTSEL3 = TAMP_OUT5,5: TAMPOUTSEL3 = TAMP_OUT6,6: TAMPOUTSEL3 = TAMP_OUT7,7: TAMPOUTSEL3 = TAMP_OUT8" bitfld.long 0x0 11.--13. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4,4: TAMPOUTSEL2 = TAMP_OUT5,5: TAMPOUTSEL2 = TAMP_OUT6,6: TAMPOUTSEL2 = TAMP_OUT7,7: TAMPOUTSEL2 = TAMP_OUT8" newline bitfld.long 0x0 8.--10. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4,4: TAMPOUTSEL1 = TAMP_OUT5,5: TAMPOUTSEL1 = TAMP_OUT6,6: TAMPOUTSEL1 = TAMP_OUT7,7: TAMPOUTSEL1 = TAMP_OUT8" line.long 0x4 "TAMP_SECCFGR,TAMP secure configuration register" bitfld.long 0x4 31. "TAMPSEC,Tamper protection (excluding monotonic counters and backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x4 30. "BHKLOCK,Boot hardware key lock" "0: The Backup registers from TAMP_BKP0R to..,1: The backup registers from TAMP_BKP0R to.." newline hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,Backup registers write protection offset" bitfld.long 0x4 15. "CNT1SEC,Monotonic counter 1 secure protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." newline hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,Backup registers read/write protection offset" line.long 0x8 "TAMP_PRIVCFGR,TAMP privilege configuration register" bitfld.long 0x8 31. "TAMPPRIV,Tamper privilege protection (excluding backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x8 30. "BKPWPRIV,Backup registers zone 2 privilege protection" "0: Backup registers zone 2 can be written with..,1: Backup registers zone 2 can be written only with.." newline bitfld.long 0x8 29. "BKPRWPRIV,Backup registers zone 1 privilege protection" "0: Backup registers zone 1 can be read and written..,1: Backup registers zone 1 can be read and written.." bitfld.long 0x8 15. "CNT1PRIV,Monotonic counter 1 privilege protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." group.long 0x2C++0x3 line.long 0x0 "TAMP_IER,TAMP interrupt enable register" bitfld.long 0x0 26. "ITAMP11IE,Internal tamper 11 interrupt enable" "0: Internal tamper 11 interrupt disabled.,1: Internal tamper 11 interrupt enabled." bitfld.long 0x0 24. "ITAMP9IE,Internal tamper 9 interrupt enable" "0: Internal tamper 9 interrupt disabled.,1: Internal tamper 9 interrupt enabled." newline bitfld.long 0x0 23. "ITAMP8IE,Internal tamper 8 interrupt enable" "0: Internal tamper 8 interrupt disabled.,1: Internal tamper 8 interrupt enabled." bitfld.long 0x0 22. "ITAMP7IE,Internal tamper 7 interrupt enable" "0: Internal tamper 7 interrupt disabled.,1: Internal tamper 7 interrupt enabled." newline bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled." bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled." newline bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled." bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled." newline bitfld.long 0x0 17. "ITAMP2IE,Internal tamper 2 interrupt enable" "0: Internal tamper 2 interrupt disabled.,1: Internal tamper 2 interrupt enabled." bitfld.long 0x0 16. "ITAMP1IE,Internal tamper 1 interrupt enable" "0: Internal tamper 1 interrupt disabled.,1: Internal tamper 1 interrupt enabled" newline bitfld.long 0x0 6. "TAMP7IE,Tamper 7interrupt enable" "0: Tamper 7 interrupt disabled.,1: Tamper 7interrupt enabled." bitfld.long 0x0 5. "TAMP6IE,Tamper 6 interrupt enable" "0: Tamper 6 interrupt disabled.,1: Tamper 6 interrupt enabled." newline bitfld.long 0x0 4. "TAMP5IE,Tamper 5 interrupt enable" "0: Tamper 5 interrupt disabled.,1: Tamper 5 interrupt enabled." bitfld.long 0x0 3. "TAMP4IE,Tamper 4 interrupt enable" "0: Tamper 4 interrupt disabled.,1: Tamper 4 interrupt enabled." newline bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.." bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled." newline bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled." rgroup.long 0x30++0xB line.long 0x0 "TAMP_SR,TAMP status register" bitfld.long 0x0 26. "ITAMP11F,Internal tamper 11 flag" "0,1" bitfld.long 0x0 24. "ITAMP9F,Internal tamper 9 flag" "0,1" newline bitfld.long 0x0 23. "ITAMP8F,Internal tamper 8 flag" "0,1" bitfld.long 0x0 22. "ITAMP7F,Internal tamper 7 flag" "0,1" newline bitfld.long 0x0 21. "ITAMP6F,Internal tamper 6 flag" "0,1" bitfld.long 0x0 20. "ITAMP5F,Internal tamper 5 flag" "0,1" newline bitfld.long 0x0 19. "ITAMP4F,Internal tamper 4 flag" "0,1" bitfld.long 0x0 18. "ITAMP3F,Internal tamper 3 flag" "0,1" newline bitfld.long 0x0 17. "ITAMP2F,Internal tamper 2 flag" "0,1" bitfld.long 0x0 16. "ITAMP1F,Internal tamper 1 flag" "0,1" newline bitfld.long 0x0 6. "TAMP7F,TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1" line.long 0x4 "TAMP_MISR,TAMP non-secure masked interrupt status register" bitfld.long 0x4 26. "ITAMP11MF,internal tamper 11 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 24. "ITAMP9MF,internal tamper 9 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 23. "ITAMP8MF,Internal tamper 8 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 22. "ITAMP7MF,Internal tamper 7 tamper non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 21. "ITAMP6MF,Internal tamper 6 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 20. "ITAMP5MF,Internal tamper 5 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 19. "ITAMP4MF,Internal tamper 4 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 18. "ITAMP3MF,Internal tamper 3 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 17. "ITAMP2MF,Internal tamper 2 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 16. "ITAMP1MF,Internal tamper 1 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 6. "TAMP7MF,TAMP7 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 2. "TAMP3MF,TAMP3 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 0. "TAMP1MF,TAMP1 non-secure interrupt masked flag" "0,1" line.long 0x8 "TAMP_SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 26. "ITAMP11MF,internal tamper 11 secure interrupt masked flag" "0,1" bitfld.long 0x8 24. "ITAMP9MF,internal tamper 9 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 23. "ITAMP8MF,Internal tamper 8 secure interrupt masked flag" "0,1" bitfld.long 0x8 22. "ITAMP7MF,Internal tamper 7 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 21. "ITAMP6MF,Internal tamper 6 secure interrupt masked flag" "0,1" bitfld.long 0x8 20. "ITAMP5MF,Internal tamper 5 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 19. "ITAMP4MF,Internal tamper 4 secure interrupt masked flag" "0,1" bitfld.long 0x8 18. "ITAMP3MF,Internal tamper 3 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 17. "ITAMP2MF,Internal tamper 2 secure interrupt masked flag" "0,1" bitfld.long 0x8 16. "ITAMP1MF,Internal tamper 1 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 6. "TAMP7MF,TAMP7 secure interrupt masked flag" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5 secure interrupt masked flag" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 2. "TAMP3MF,TAMP3 secure interrupt masked flag" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 0. "TAMP1MF,TAMP1 secure interrupt masked flag" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "TAMP_SCR,TAMP status clear register" bitfld.long 0x0 26. "CITAMP11F,Clear ITAMP11 detection flag" "0,1" bitfld.long 0x0 24. "CITAMP9F,Clear ITAMP9 detection flag" "0,1" newline bitfld.long 0x0 23. "CITAMP8F,Clear ITAMP8 detection flag" "0,1" bitfld.long 0x0 22. "CITAMP7F,Clear ITAMP7 detection flag" "0,1" newline bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1" bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1" newline bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1" bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1" newline bitfld.long 0x0 17. "CITAMP2F,Clear ITAMP2 detection flag" "0,1" bitfld.long 0x0 16. "CITAMP1F,Clear ITAMP1 detection flag" "0,1" newline bitfld.long 0x0 6. "CTAMP7F,Clear TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "CTAMP6F,Clear TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,Clear TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "CTAMP4F,Clear TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "TAMP_COUNT1R,TAMP monotonic counter 1 register" hexmask.long 0x0 0.--31. 1. "COUNT,This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value." group.long 0x50++0x7 line.long 0x0 "TAMP_OR,TAMP option register" bitfld.long 0x0 1. "BSEN,Boundary scan enable" "0: Boundary scan is disabled,1: Boundary scan is enabled" bitfld.long 0x0 0. "VCOREMEN,V less than sub>CORE less than /sub> monitoring" "0: V less than sub>CORE less than /sub> monitoring..,1: V less than sub>CORE less than /sub> monitoring.." line.long 0x4 "TAMP_RPCFGR,TAMP resources protection configuration register" bitfld.long 0x4 0. "RPCFG0,Configurable resource 0 protection" "0: Resource 0 is not included in the device secrets..,1: Resource 0 is included in the device secrets.." group.long 0x100++0x7F line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register" hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register" hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register" hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0xC "TAMP_BKP3R,TAMP backup 3 register" hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register" hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x14 "TAMP_BKP5R,TAMP backup 5 register" hexmask.long 0x14 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x18 "TAMP_BKP6R,TAMP backup 6 register" hexmask.long 0x18 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x1C "TAMP_BKP7R,TAMP backup 7 register" hexmask.long 0x1C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x20 "TAMP_BKP8R,TAMP backup 8 register" hexmask.long 0x20 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x24 "TAMP_BKP9R,TAMP backup 9 register" hexmask.long 0x24 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x28 "TAMP_BKP10R,TAMP backup 10 register" hexmask.long 0x28 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x2C "TAMP_BKP11R,TAMP backup 11 register" hexmask.long 0x2C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x30 "TAMP_BKP12R,TAMP backup 12 register" hexmask.long 0x30 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x34 "TAMP_BKP13R,TAMP backup 13 register" hexmask.long 0x34 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x38 "TAMP_BKP14R,TAMP backup 14 register" hexmask.long 0x38 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x3C "TAMP_BKP15R,TAMP backup 15 register" hexmask.long 0x3C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x40 "TAMP_BKP16R,TAMP backup 16 register" hexmask.long 0x40 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x44 "TAMP_BKP17R,TAMP backup 17 register" hexmask.long 0x44 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x48 "TAMP_BKP18R,TAMP backup 18 register" hexmask.long 0x48 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4C "TAMP_BKP19R,TAMP backup 19 register" hexmask.long 0x4C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x50 "TAMP_BKP20R,TAMP backup 20 register" hexmask.long 0x50 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x54 "TAMP_BKP21R,TAMP backup 21 register" hexmask.long 0x54 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x58 "TAMP_BKP22R,TAMP backup 22 register" hexmask.long 0x58 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x5C "TAMP_BKP23R,TAMP backup 23 register" hexmask.long 0x5C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x60 "TAMP_BKP24R,TAMP backup 24 register" hexmask.long 0x60 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x64 "TAMP_BKP25R,TAMP backup 25 register" hexmask.long 0x64 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x68 "TAMP_BKP26R,TAMP backup 26 register" hexmask.long 0x68 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x6C "TAMP_BKP27R,TAMP backup 27 register" hexmask.long 0x6C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x70 "TAMP_BKP28R,TAMP backup 28 register" hexmask.long 0x70 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x74 "TAMP_BKP29R,TAMP backup 29 register" hexmask.long 0x74 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x78 "TAMP_BKP30R,TAMP backup 30 register" hexmask.long 0x78 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x7C "TAMP_BKP31R,TAMP backup 31 register" hexmask.long 0x7C 0.--31. 1. "BKP,The application can write or read data to and from these registers." tree.end tree "TAMP_S" base ad:0x56004400 group.long 0x0++0x13 line.long 0x0 "TAMP_CR1,TAMP control register 1" bitfld.long 0x0 26. "ITAMP11E,Internal tamper 11 enable" "0: Internal tamper 11 disabled.,1: Internal tamper 11 enabled." bitfld.long 0x0 24. "ITAMP9E,Internal tamper 9 enable" "0: Internal tamper 9 disabled.,1: Internal tamper 9 enabled." newline bitfld.long 0x0 23. "ITAMP8E,Internal tamper 8 enable" "0: Internal tamper 8 disabled.,1: Internal tamper 8 enabled." bitfld.long 0x0 22. "ITAMP7E,Internal tamper 7 enable" "0: Internal tamper 7 disabled.,1: Internal tamper 7 enabled" newline bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled." bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled." newline bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled." bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled." newline bitfld.long 0x0 17. "ITAMP2E,Internal tamper 2 enable" "0: Internal tamper 2 disabled.,1: Internal tamper 2 enabled." bitfld.long 0x0 16. "ITAMP1E,Internal tamper 1 enable" "0: Internal tamper 1 disabled.,1: Internal tamper 1 enabled." newline bitfld.long 0x0 6. "TAMP7E,Tamper detection on TAMP_IN7 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN7 is disabled.,1: Tamper detection on TAMP_IN7 is enabled." bitfld.long 0x0 5. "TAMP6E,Tamper detection on TAMP_IN6 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN6 is disabled.,1: Tamper detection on TAMP_IN6 is enabled." newline bitfld.long 0x0 4. "TAMP5E,Tamper detection on TAMP_IN5 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN5 is disabled.,1: Tamper detection on TAMP_IN5 is enabled." bitfld.long 0x0 3. "TAMP4E,Tamper detection on TAMP_IN4 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN4 is disabled.,1: Tamper detection on TAMP_IN4 is enabled." newline bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled." bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable less than sup>(1) less than /sup>" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled." newline bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled." line.long 0x4 "TAMP_CR2,TAMP control register 2" bitfld.long 0x4 30. "TAMP7TRG,Active level for tamper 7 input (active mode disabled)" "0: If TAMPFLT different 00 tamper 7 input staying..,1: If TAMPFLT different 00 tamper 7 input staying.." bitfld.long 0x4 29. "TAMP6TRG,Active level for tamper 6 input (active mode disabled)" "0: If TAMPFLT different 00 tamper 6 input staying..,1: If TAMPFLT different 00 tamper 6 input staying.." newline bitfld.long 0x4 28. "TAMP5TRG,Active level for tamper 5 input (active mode disabled)" "0: If TAMPFLT different 00 tamper 5 input staying..,1: If TAMPFLT different 00 tamper 5 input staying.." bitfld.long 0x4 27. "TAMP4TRG,Active level for tamper 4 input (active mode disabled)" "0: If TAMPFLT different 00 tamper 4 input staying..,1: If TAMPFLT different 00 tamper 4 input staying.." newline bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input" "0: If TAMPFLT different 00 tamper 3 input staying..,1: If TAMPFLT different 00 tamper 3 input staying.." bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input" "0: If TAMPFLT different 00 tamper 2 input staying..,1: If TAMPFLT different 00 tamper 2 input staying.." newline bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input" "0: If TAMPFLT different 00 tamper 1 input staying..,1: If TAMPFLT different 00 tamper 1 input staying.." bitfld.long 0x4 23. "BKERASE,Backup registers and device secrets less than sup>(1) less than /sup> erase" "0,1" newline bitfld.long 0x4 22. "BKBLOCK,Backup registers and device secrets less than sup>(1) less than /sup> access blocked" "0: backup registers and device secrets less than..,1: backup registers and device secrets less than.." bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.." newline bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.." bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.." newline bitfld.long 0x4 6. "TAMP7POM,Tamper 7 potential mode" "0: Tamper 7 event detection is in confirmed mode..,1: Tamper 7 event detection is in potential mode.." bitfld.long 0x4 5. "TAMP6POM,Tamper 6 potential mode" "0: Tamper 6 event detection is in confirmed mode..,1: Tamper 6 event detection is in potential mode.." newline bitfld.long 0x4 4. "TAMP5POM,Tamper 5 potential mode" "0: Tamper 5 event detection is in confirmed mode..,1: Tamper 5 event detection is in potential mode.." bitfld.long 0x4 3. "TAMP4POM,Tamper 4 potential mode" "0: Tamper 4 event detection is in confirmed mode..,1: Tamper 4 event detection is in potential mode.." newline bitfld.long 0x4 2. "TAMP3POM,Tamper 3 potential mode" "0: Tamper 3 event detection is in confirmed mode..,1: Tamper 3 event detection is in potential mode.." bitfld.long 0x4 1. "TAMP2POM,Tamper 2 potential mode" "0: Tamper 2 event detection is in confirmed mode..,1: Tamper 2 event detection is in potential mode.." newline bitfld.long 0x4 0. "TAMP1POM,Tamper 1 potential mode" "0: Tamper 1 event detection is in confirmed mode.,1: Tamper 1 event detection is in potential mode." line.long 0x8 "TAMP_CR3,TAMP control register 3" bitfld.long 0x8 10. "ITAMP11POM,Internal tamper 11 potential mode" "0: Internal tamper 11 event detection is in..,1: Internal tamper 11 event detection is in.." bitfld.long 0x8 8. "ITAMP9POM,Internal tamper 9 potential mode" "0: Internal tamper 9 event detection is in..,1: Internal tamper 9 event detection is in.." newline bitfld.long 0x8 7. "ITAMP8POM,Internal tamper 8 potential mode" "0: Internal tamper 8 event detection is in..,1: Internal tamper 8 event detection is in.." bitfld.long 0x8 6. "ITAMP7POM,Internal tamper 7 potential mode" "0: Internal tamper 7 event detection is in..,1: Internal tamper 7 event detection is in.." newline bitfld.long 0x8 5. "ITAMP6POM,Internal tamper 6 potential mode" "0: Internal tamper 6 event detection is in..,1: Internal tamper 6 event detection is in.." bitfld.long 0x8 4. "ITAMP5POM,Internal tamper 5 potential mode" "0: Internal tamper 5 event detection is in..,1: Internal tamper 5 event detection is in.." newline bitfld.long 0x8 3. "ITAMP4POM,Internal tamper 4 potential mode" "0: Internal tamper 4 event detection is in..,1: Internal tamper 4 event detection is in.." bitfld.long 0x8 2. "ITAMP3POM,Internal tamper 3 potential mode" "0: Internal tamper 3 event detection is in..,1: Internal tamper 3 event detection is in.." newline bitfld.long 0x8 1. "ITAMP2POM,Internal tamper 2 potential mode" "0: Internal tamper 2 event detection is in..,1: Internal tamper 2 event detection is in.." bitfld.long 0x8 0. "ITAMP1POM,Internal tamper 1 potential mode" "0: Internal tamper 1 event detection is in..,1: Internal tamper 1 event detection is in.." line.long 0xC "TAMP_FLTCR,TAMP filter control register" bitfld.long 0xC 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins." bitfld.long 0xC 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles" newline bitfld.long 0xC 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.." bitfld.long 0xC 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)" line.long 0x10 "TAMP_ATCR1,TAMP active tamper control register 1" bitfld.long 0x10 31. "FLTEN,Active tamper filter enable" "0: Active tamper filtering disable,1: Active tamper filtering enable: a tamper event.." bitfld.long 0x10 30. "ATOSHARE,Active tamper output sharing" "0: Each active tamper input TAMP_INi is compared..,1: Each active tamper input TAMP_INi is compared.." newline bitfld.long 0x10 24.--26. "ATPER,Active tamper output change period" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 16.--19. 1. "ATCKSEL,Active tamper RTC asynchronous prescaler clock selection" newline bitfld.long 0x10 14.--15. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4" bitfld.long 0x10 12.--13. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4" newline bitfld.long 0x10 10.--11. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4" bitfld.long 0x10 8.--9. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4" newline bitfld.long 0x10 6. "TAMP7AM,Tamper 7 active mode" "0: Tamper 7 detection mode is passive.,1: Tamper 7 detection mode is active." bitfld.long 0x10 5. "TAMP6AM,Tamper 6 active mode" "0: Tamper 6 detection mode is passive.,1: Tamper 6 detection mode is active." newline bitfld.long 0x10 4. "TAMP5AM,Tamper 5 active mode" "0: Tamper 5 detection mode is passive.,1: Tamper 5 detection mode is active." bitfld.long 0x10 3. "TAMP4AM,Tamper 4 active mode" "0: Tamper 4 detection mode is passive.,1: Tamper 4 detection mode is active." newline bitfld.long 0x10 2. "TAMP3AM,Tamper 3 active mode" "0: Tamper 3 detection mode is passive.,1: Tamper 3 detection mode is active." bitfld.long 0x10 1. "TAMP2AM,Tamper 2 active mode" "0: Tamper 2 detection mode is passive.,1: Tamper 2 detection mode is active." newline bitfld.long 0x10 0. "TAMP1AM,Tamper 1 active mode" "0: Tamper 1 detection mode is passive.,1: Tamper 1 detection mode is active." wgroup.long 0x14++0x3 line.long 0x0 "TAMP_ATSEEDR,TAMP active tamper seed register" hexmask.long 0x0 0.--31. 1. "SEED,Pseudo-random generator seed value" rgroup.long 0x18++0x3 line.long 0x0 "TAMP_ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,Active tamper initialization status" "0,1" bitfld.long 0x0 14. "SEEDF,Seed running flag" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PRNG,Pseudo-random generator value" group.long 0x1C++0xB line.long 0x0 "TAMP_ATCR2,TAMP active tamper control register 2" bitfld.long 0x0 26.--28. "ATOSEL7,Active tamper shared output 7 selection" "0: TAMPOUTSEL7 = TAMP_OUT1,1: TAMPOUTSEL7 = TAMP_OUT2,2: TAMPOUTSEL7 = TAMP_OUT3,3: TAMPOUTSEL7 = TAMP_OUT4,4: TAMPOUTSEL7 = TAMP_OUT5,5: TAMPOUTSEL7 = TAMP_OUT6,6: TAMPOUTSEL7 = TAMP_OUT7,7: TAMPOUTSEL7 = TAMP_OUT8" bitfld.long 0x0 23.--25. "ATOSEL6,Active tamper shared output 6 selection" "0: TAMPOUTSEL6 = TAMP_OUT1,1: TAMPOUTSEL6 = TAMP_OUT2,2: TAMPOUTSEL6 = TAMP_OUT3,3: TAMPOUTSEL6 = TAMP_OUT4,4: TAMPOUTSEL6 = TAMP_OUT5,5: TAMPOUTSEL6 = TAMP_OUT6,6: TAMPOUTSEL6 = TAMP_OUT7,7: TAMPOUTSEL6 = TAMP_OUT8" newline bitfld.long 0x0 20.--22. "ATOSEL5,Active tamper shared output 5 selection" "0: TAMPOUTSEL5 = TAMP_OUT1,1: TAMPOUTSEL5 = TAMP_OUT2,2: TAMPOUTSEL5 = TAMP_OUT3,3: TAMPOUTSEL5 = TAMP_OUT4,4: TAMPOUTSEL5 = TAMP_OUT5,5: TAMPOUTSEL5 = TAMP_OUT6,6: TAMPOUTSEL5 = TAMP_OUT7,7: TAMPOUTSEL5 = TAMP_OUT8" bitfld.long 0x0 17.--19. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4,4: TAMPOUTSEL4 = TAMP_OUT5,5: TAMPOUTSEL4 = TAMP_OUT6,6: TAMPOUTSEL4 = TAMP_OUT7,7: TAMPOUTSEL4 = TAMP_OUT8" newline bitfld.long 0x0 14.--16. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4,4: TAMPOUTSEL3 = TAMP_OUT5,5: TAMPOUTSEL3 = TAMP_OUT6,6: TAMPOUTSEL3 = TAMP_OUT7,7: TAMPOUTSEL3 = TAMP_OUT8" bitfld.long 0x0 11.--13. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4,4: TAMPOUTSEL2 = TAMP_OUT5,5: TAMPOUTSEL2 = TAMP_OUT6,6: TAMPOUTSEL2 = TAMP_OUT7,7: TAMPOUTSEL2 = TAMP_OUT8" newline bitfld.long 0x0 8.--10. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4,4: TAMPOUTSEL1 = TAMP_OUT5,5: TAMPOUTSEL1 = TAMP_OUT6,6: TAMPOUTSEL1 = TAMP_OUT7,7: TAMPOUTSEL1 = TAMP_OUT8" line.long 0x4 "TAMP_SECCFGR,TAMP secure configuration register" bitfld.long 0x4 31. "TAMPSEC,Tamper protection (excluding monotonic counters and backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x4 30. "BHKLOCK,Boot hardware key lock" "0: The Backup registers from TAMP_BKP0R to..,1: The backup registers from TAMP_BKP0R to.." newline hexmask.long.byte 0x4 16.--23. 1. "BKPWSEC,Backup registers write protection offset" bitfld.long 0x4 15. "CNT1SEC,Monotonic counter 1 secure protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." newline hexmask.long.byte 0x4 0.--7. 1. "BKPRWSEC,Backup registers read/write protection offset" line.long 0x8 "TAMP_PRIVCFGR,TAMP privilege configuration register" bitfld.long 0x8 31. "TAMPPRIV,Tamper privilege protection (excluding backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.." bitfld.long 0x8 30. "BKPWPRIV,Backup registers zone 2 privilege protection" "0: Backup registers zone 2 can be written with..,1: Backup registers zone 2 can be written only with.." newline bitfld.long 0x8 29. "BKPRWPRIV,Backup registers zone 1 privilege protection" "0: Backup registers zone 1 can be read and written..,1: Backup registers zone 1 can be read and written.." bitfld.long 0x8 15. "CNT1PRIV,Monotonic counter 1 privilege protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.." group.long 0x2C++0x3 line.long 0x0 "TAMP_IER,TAMP interrupt enable register" bitfld.long 0x0 26. "ITAMP11IE,Internal tamper 11 interrupt enable" "0: Internal tamper 11 interrupt disabled.,1: Internal tamper 11 interrupt enabled." bitfld.long 0x0 24. "ITAMP9IE,Internal tamper 9 interrupt enable" "0: Internal tamper 9 interrupt disabled.,1: Internal tamper 9 interrupt enabled." newline bitfld.long 0x0 23. "ITAMP8IE,Internal tamper 8 interrupt enable" "0: Internal tamper 8 interrupt disabled.,1: Internal tamper 8 interrupt enabled." bitfld.long 0x0 22. "ITAMP7IE,Internal tamper 7 interrupt enable" "0: Internal tamper 7 interrupt disabled.,1: Internal tamper 7 interrupt enabled." newline bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled." bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled." newline bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled." bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled." newline bitfld.long 0x0 17. "ITAMP2IE,Internal tamper 2 interrupt enable" "0: Internal tamper 2 interrupt disabled.,1: Internal tamper 2 interrupt enabled." bitfld.long 0x0 16. "ITAMP1IE,Internal tamper 1 interrupt enable" "0: Internal tamper 1 interrupt disabled.,1: Internal tamper 1 interrupt enabled" newline bitfld.long 0x0 6. "TAMP7IE,Tamper 7interrupt enable" "0: Tamper 7 interrupt disabled.,1: Tamper 7interrupt enabled." bitfld.long 0x0 5. "TAMP6IE,Tamper 6 interrupt enable" "0: Tamper 6 interrupt disabled.,1: Tamper 6 interrupt enabled." newline bitfld.long 0x0 4. "TAMP5IE,Tamper 5 interrupt enable" "0: Tamper 5 interrupt disabled.,1: Tamper 5 interrupt enabled." bitfld.long 0x0 3. "TAMP4IE,Tamper 4 interrupt enable" "0: Tamper 4 interrupt disabled.,1: Tamper 4 interrupt enabled." newline bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.." bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled." newline bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled." rgroup.long 0x30++0xB line.long 0x0 "TAMP_SR,TAMP status register" bitfld.long 0x0 26. "ITAMP11F,Internal tamper 11 flag" "0,1" bitfld.long 0x0 24. "ITAMP9F,Internal tamper 9 flag" "0,1" newline bitfld.long 0x0 23. "ITAMP8F,Internal tamper 8 flag" "0,1" bitfld.long 0x0 22. "ITAMP7F,Internal tamper 7 flag" "0,1" newline bitfld.long 0x0 21. "ITAMP6F,Internal tamper 6 flag" "0,1" bitfld.long 0x0 20. "ITAMP5F,Internal tamper 5 flag" "0,1" newline bitfld.long 0x0 19. "ITAMP4F,Internal tamper 4 flag" "0,1" bitfld.long 0x0 18. "ITAMP3F,Internal tamper 3 flag" "0,1" newline bitfld.long 0x0 17. "ITAMP2F,Internal tamper 2 flag" "0,1" bitfld.long 0x0 16. "ITAMP1F,Internal tamper 1 flag" "0,1" newline bitfld.long 0x0 6. "TAMP7F,TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "TAMP6F,TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "TAMP5F,TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "TAMP4F,TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1" line.long 0x4 "TAMP_MISR,TAMP non-secure masked interrupt status register" bitfld.long 0x4 26. "ITAMP11MF,internal tamper 11 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 24. "ITAMP9MF,internal tamper 9 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 23. "ITAMP8MF,Internal tamper 8 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 22. "ITAMP7MF,Internal tamper 7 tamper non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 21. "ITAMP6MF,Internal tamper 6 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 20. "ITAMP5MF,Internal tamper 5 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 19. "ITAMP4MF,Internal tamper 4 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 18. "ITAMP3MF,Internal tamper 3 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 17. "ITAMP2MF,Internal tamper 2 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 16. "ITAMP1MF,Internal tamper 1 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 6. "TAMP7MF,TAMP7 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 5. "TAMP6MF,TAMP6 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 4. "TAMP5MF,TAMP5 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 3. "TAMP4MF,TAMP4 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 2. "TAMP3MF,TAMP3 non-secure interrupt masked flag" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2 non-secure interrupt masked flag" "0,1" newline bitfld.long 0x4 0. "TAMP1MF,TAMP1 non-secure interrupt masked flag" "0,1" line.long 0x8 "TAMP_SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 26. "ITAMP11MF,internal tamper 11 secure interrupt masked flag" "0,1" bitfld.long 0x8 24. "ITAMP9MF,internal tamper 9 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 23. "ITAMP8MF,Internal tamper 8 secure interrupt masked flag" "0,1" bitfld.long 0x8 22. "ITAMP7MF,Internal tamper 7 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 21. "ITAMP6MF,Internal tamper 6 secure interrupt masked flag" "0,1" bitfld.long 0x8 20. "ITAMP5MF,Internal tamper 5 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 19. "ITAMP4MF,Internal tamper 4 secure interrupt masked flag" "0,1" bitfld.long 0x8 18. "ITAMP3MF,Internal tamper 3 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 17. "ITAMP2MF,Internal tamper 2 secure interrupt masked flag" "0,1" bitfld.long 0x8 16. "ITAMP1MF,Internal tamper 1 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 6. "TAMP7MF,TAMP7 secure interrupt masked flag" "0,1" bitfld.long 0x8 5. "TAMP6MF,TAMP6 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 4. "TAMP5MF,TAMP5 secure interrupt masked flag" "0,1" bitfld.long 0x8 3. "TAMP4MF,TAMP4 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 2. "TAMP3MF,TAMP3 secure interrupt masked flag" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2 secure interrupt masked flag" "0,1" newline bitfld.long 0x8 0. "TAMP1MF,TAMP1 secure interrupt masked flag" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "TAMP_SCR,TAMP status clear register" bitfld.long 0x0 26. "CITAMP11F,Clear ITAMP11 detection flag" "0,1" bitfld.long 0x0 24. "CITAMP9F,Clear ITAMP9 detection flag" "0,1" newline bitfld.long 0x0 23. "CITAMP8F,Clear ITAMP8 detection flag" "0,1" bitfld.long 0x0 22. "CITAMP7F,Clear ITAMP7 detection flag" "0,1" newline bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1" bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1" newline bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1" bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1" newline bitfld.long 0x0 17. "CITAMP2F,Clear ITAMP2 detection flag" "0,1" bitfld.long 0x0 16. "CITAMP1F,Clear ITAMP1 detection flag" "0,1" newline bitfld.long 0x0 6. "CTAMP7F,Clear TAMP7 detection flag" "0,1" bitfld.long 0x0 5. "CTAMP6F,Clear TAMP6 detection flag" "0,1" newline bitfld.long 0x0 4. "CTAMP5F,Clear TAMP5 detection flag" "0,1" bitfld.long 0x0 3. "CTAMP4F,Clear TAMP4 detection flag" "0,1" newline bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1" bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1" newline bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "TAMP_COUNT1R,TAMP monotonic counter 1 register" hexmask.long 0x0 0.--31. 1. "COUNT,This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value." group.long 0x50++0x7 line.long 0x0 "TAMP_OR,TAMP option register" bitfld.long 0x0 1. "BSEN,Boundary scan enable" "0: Boundary scan is disabled,1: Boundary scan is enabled" bitfld.long 0x0 0. "VCOREMEN,V less than sub>CORE less than /sub> monitoring" "0: V less than sub>CORE less than /sub> monitoring..,1: V less than sub>CORE less than /sub> monitoring.." line.long 0x4 "TAMP_RPCFGR,TAMP resources protection configuration register" bitfld.long 0x4 0. "RPCFG0,Configurable resource 0 protection" "0: Resource 0 is not included in the device secrets..,1: Resource 0 is included in the device secrets.." group.long 0x100++0x7F line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register" hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register" hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register" hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0xC "TAMP_BKP3R,TAMP backup 3 register" hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register" hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x14 "TAMP_BKP5R,TAMP backup 5 register" hexmask.long 0x14 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x18 "TAMP_BKP6R,TAMP backup 6 register" hexmask.long 0x18 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x1C "TAMP_BKP7R,TAMP backup 7 register" hexmask.long 0x1C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x20 "TAMP_BKP8R,TAMP backup 8 register" hexmask.long 0x20 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x24 "TAMP_BKP9R,TAMP backup 9 register" hexmask.long 0x24 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x28 "TAMP_BKP10R,TAMP backup 10 register" hexmask.long 0x28 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x2C "TAMP_BKP11R,TAMP backup 11 register" hexmask.long 0x2C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x30 "TAMP_BKP12R,TAMP backup 12 register" hexmask.long 0x30 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x34 "TAMP_BKP13R,TAMP backup 13 register" hexmask.long 0x34 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x38 "TAMP_BKP14R,TAMP backup 14 register" hexmask.long 0x38 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x3C "TAMP_BKP15R,TAMP backup 15 register" hexmask.long 0x3C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x40 "TAMP_BKP16R,TAMP backup 16 register" hexmask.long 0x40 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x44 "TAMP_BKP17R,TAMP backup 17 register" hexmask.long 0x44 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x48 "TAMP_BKP18R,TAMP backup 18 register" hexmask.long 0x48 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4C "TAMP_BKP19R,TAMP backup 19 register" hexmask.long 0x4C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x50 "TAMP_BKP20R,TAMP backup 20 register" hexmask.long 0x50 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x54 "TAMP_BKP21R,TAMP backup 21 register" hexmask.long 0x54 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x58 "TAMP_BKP22R,TAMP backup 22 register" hexmask.long 0x58 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x5C "TAMP_BKP23R,TAMP backup 23 register" hexmask.long 0x5C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x60 "TAMP_BKP24R,TAMP backup 24 register" hexmask.long 0x60 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x64 "TAMP_BKP25R,TAMP backup 25 register" hexmask.long 0x64 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x68 "TAMP_BKP26R,TAMP backup 26 register" hexmask.long 0x68 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x6C "TAMP_BKP27R,TAMP backup 27 register" hexmask.long 0x6C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x70 "TAMP_BKP28R,TAMP backup 28 register" hexmask.long 0x70 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x74 "TAMP_BKP29R,TAMP backup 29 register" hexmask.long 0x74 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x78 "TAMP_BKP30R,TAMP backup 30 register" hexmask.long 0x78 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x7C "TAMP_BKP31R,TAMP backup 31 register" hexmask.long 0x7C 0.--31. 1. "BKP,The application can write or read data to and from these registers." tree.end tree.end tree "TIM (Timers)" base ad:0x0 tree "TIM1" base ad:0x42000000 group.word 0x0++0x1 line.word 0x0 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub>=t less than..,1: t less than sub>DTS less than /sub>=2*t less..,2: t less than sub>DTS less than /sub>=4*t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM1_CR2,TIM1 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x0 18. "OIS6,Output idle state 6 (tim_oc6 output)" "0,1" newline bitfld.long 0x0 16. "OIS5,Output idle state 5 (tim_oc5 output)" "0,1" bitfld.long 0x0 15. "OIS4N,Output idle state 4 (tim_oc4n output)" "0,1" newline bitfld.long 0x0 14. "OIS4,Output idle state 4 (tim_oc4 output)" "0,1" bitfld.long 0x0 13. "OIS3N,Output idle state 3 (tim_oc3n output)" "0,1" newline bitfld.long 0x0 12. "OIS3,Output idle state 3 (tim_oc3n output)" "0,1" bitfld.long 0x0 11. "OIS2N,Output idle state 2 (tim_oc2n output)" "0,1" newline bitfld.long 0x0 10. "OIS2,Output idle state 2 (tim_oc2 output)" "0,1" bitfld.long 0x0 9. "OIS1N,Output idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0" newline bitfld.long 0x0 8. "OIS1,Output idle state 1 (tim_oc1 output)" "0: tim_oc1=0 (after a dead-time) when MOE=0,1: tim_oc1=1 (after a dead-time) when MOE=0" bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: tim_ti1_in[15:0] tim_ti2_in[15:0] and.." newline bitfld.long 0x0 4.--6. "MMS,MMS[2:0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" newline bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM1_SR,TIM1 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: CCxE CCxNE and OCxM bits update (providing CCPC.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM1_CCMR1_Input,TIM1 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM1_CCMR1_Output,TIM1 capture/compare mode register 1 [alternate]" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM1_CCMR2_Input,TIM1 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0xB line.long 0x0 "TIM1_CCMR2_Output,TIM1 capture/compare mode register 2 [alternate]" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0: Frozen - The comparison between the output..,1: Set channel 3 to active level on match.,2: Set channel 3 to inactive level on match.,3: Toggle - tim_oc3ref toggles when..,4: Force inactive level - tim_oc3ref is forced low.,5: Force active level - tim_oc3ref is forced high.,6: PWM mode 1 - In upcounting channel 3 is active..,7: PWM mode 2 - In upcounting channel 3 is inactive.." bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM1_CNT,TIM1 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC,TIM1 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM1_ARR,TIM1 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR,TIM1 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM1_CCR1,TIM1 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM1_CCR2,TIM1 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM1_CCR3,TIM1 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM1_CCR4,TIM1 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: In response to a break 2 event. OC and OCN..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM1_CCR6,TIM1 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M_1,OC6M[3]" "0,1" bitfld.long 0x1C 16. "OC5M_1,OC5M[3]" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M,OC6M[2:0]: Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M,OC5M[2:0]: Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM1_DTR2,TIM1 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM1_ECR,TIM1 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled when tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM1_TISEL,TIM1 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x2C "TIM1_AF1,TIM1 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM1_AF2,TIM1 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM1_DCR,TIM1 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM1_DMAR,TIM1 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM1_S" base ad:0x52000000 group.word 0x0++0x1 line.word 0x0 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub>=t less than..,1: t less than sub>DTS less than /sub>=2*t less..,2: t less than sub>DTS less than /sub>=4*t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM1_CR2,TIM1 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x0 18. "OIS6,Output idle state 6 (tim_oc6 output)" "0,1" newline bitfld.long 0x0 16. "OIS5,Output idle state 5 (tim_oc5 output)" "0,1" bitfld.long 0x0 15. "OIS4N,Output idle state 4 (tim_oc4n output)" "0,1" newline bitfld.long 0x0 14. "OIS4,Output idle state 4 (tim_oc4 output)" "0,1" bitfld.long 0x0 13. "OIS3N,Output idle state 3 (tim_oc3n output)" "0,1" newline bitfld.long 0x0 12. "OIS3,Output idle state 3 (tim_oc3n output)" "0,1" bitfld.long 0x0 11. "OIS2N,Output idle state 2 (tim_oc2n output)" "0,1" newline bitfld.long 0x0 10. "OIS2,Output idle state 2 (tim_oc2 output)" "0,1" bitfld.long 0x0 9. "OIS1N,Output idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0" newline bitfld.long 0x0 8. "OIS1,Output idle state 1 (tim_oc1 output)" "0: tim_oc1=0 (after a dead-time) when MOE=0,1: tim_oc1=1 (after a dead-time) when MOE=0" bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: tim_ti1_in[15:0] tim_ti2_in[15:0] and.." newline bitfld.long 0x0 4.--6. "MMS,MMS[2:0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" newline bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM1_SR,TIM1 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: CCxE CCxNE and OCxM bits update (providing CCPC.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM1_CCMR1_Input,TIM1 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM1_CCMR1_Output,TIM1 capture/compare mode register 1 [alternate]" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM1_CCMR2_Input,TIM1 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0xB line.long 0x0 "TIM1_CCMR2_Output,TIM1 capture/compare mode register 2 [alternate]" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0: Frozen - The comparison between the output..,1: Set channel 3 to active level on match.,2: Set channel 3 to inactive level on match.,3: Toggle - tim_oc3ref toggles when..,4: Force inactive level - tim_oc3ref is forced low.,5: Force active level - tim_oc3ref is forced high.,6: PWM mode 1 - In upcounting channel 3 is active..,7: PWM mode 2 - In upcounting channel 3 is inactive.." bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM1_CNT,TIM1 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC,TIM1 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM1_ARR,TIM1 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR,TIM1 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM1_CCR1,TIM1 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM1_CCR2,TIM1 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM1_CCR3,TIM1 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM1_CCR4,TIM1 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: In response to a break 2 event. OC and OCN..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM1_CCR6,TIM1 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M_1,OC6M[3]" "0,1" bitfld.long 0x1C 16. "OC5M_1,OC5M[3]" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M,OC6M[2:0]: Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M,OC5M[2:0]: Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM1_DTR2,TIM1 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM1_ECR,TIM1 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled when tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM1_TISEL,TIM1 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x2C "TIM1_AF1,TIM1 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM1_AF2,TIM1 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM1_DCR,TIM1 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM1_DMAR,TIM1 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM2" base ad:0x40000000 group.word 0x0++0x1 line.word 0x0 "TIM2_CR1,TIM2 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM2_CR2,TIM2 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.." bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" line.long 0x4 "TIM2_SMCR,TIM2 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: Internal trigger 2 (tim_itr2),3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM2_DIER,TIM2 DMA/Interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled." bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled." newline bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled." bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled." newline bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled." bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled." newline bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled." bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." line.long 0xC "TIM2_SR,TIM2 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1" newline bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM2_EGR,TIM2 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" newline bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM2_CCMR1_INPUT,TIM2 capture/compare mode register 1" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM2_CCMR1_OUTPUT,TIM2 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM2_CCMR2_INPUT,TIM2 capture/compare mode register 2" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0x3 line.long 0x0 "TIM2_CCMR2_OUTPUT,TIM2 capture/compare mode register 2" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.word 0x20++0x1 line.word 0x0 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1" bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1" newline bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1" bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1" newline bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1" bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1" newline bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM2_CNT,TIM2 counter" bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1" hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value" group.word 0x28++0x1 line.word 0x0 "TIM2_PSC,TIM2 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM2_ARR,TIM2 auto-reload register" hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "TIM2_CCR1,TIM2 capture/compare register 1" hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM2_CCR2,TIM2 capture/compare register 2" hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM2_CCR3,TIM2 capture/compare register 3" hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value" line.long 0xC "TIM2_CCR4,TIM2 capture/compare register 4" hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value" group.long 0x58++0xF line.long 0x0 "TIM2_ECR,TIM2 timer encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x4 "TIM2_TISEL,TIM2 timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x8 "TIM2_AF1,TIM2 alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "TIM2_AF2,TIM2 alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM2_DCR,TIM2 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM2_DMAR,TIM2 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM2_S" base ad:0x50000000 group.word 0x0++0x1 line.word 0x0 "TIM2_CR1,TIM2 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM2_CR2,TIM2 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.." bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" line.long 0x4 "TIM2_SMCR,TIM2 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: Internal trigger 2 (tim_itr2),3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM2_DIER,TIM2 DMA/Interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled." bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled." newline bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled." bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled." newline bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled." bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled." newline bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled." bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." line.long 0xC "TIM2_SR,TIM2 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1" newline bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM2_EGR,TIM2 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" newline bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM2_CCMR1_INPUT,TIM2 capture/compare mode register 1" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM2_CCMR1_OUTPUT,TIM2 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM2_CCMR2_INPUT,TIM2 capture/compare mode register 2" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0x3 line.long 0x0 "TIM2_CCMR2_OUTPUT,TIM2 capture/compare mode register 2" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.word 0x20++0x1 line.word 0x0 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1" bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1" newline bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1" bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1" newline bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1" bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1" newline bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM2_CNT,TIM2 counter" bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1" hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value" group.word 0x28++0x1 line.word 0x0 "TIM2_PSC,TIM2 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM2_ARR,TIM2 auto-reload register" hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "TIM2_CCR1,TIM2 capture/compare register 1" hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM2_CCR2,TIM2 capture/compare register 2" hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM2_CCR3,TIM2 capture/compare register 3" hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value" line.long 0xC "TIM2_CCR4,TIM2 capture/compare register 4" hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value" group.long 0x58++0xF line.long 0x0 "TIM2_ECR,TIM2 timer encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x4 "TIM2_TISEL,TIM2 timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x8 "TIM2_AF1,TIM2 alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "TIM2_AF2,TIM2 alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM2_DCR,TIM2 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM2_DMAR,TIM2 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM3" base ad:0x40000400 group.word 0x0++0x1 line.word 0x0 "TIM3_CR1,TIM3 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM3_CR2,TIM3 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.." bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" line.long 0x4 "TIM3_SMCR,TIM3 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: Internal trigger 2 (tim_itr2),3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM3_DIER,TIM3 DMA/Interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled." bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled." newline bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled." bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled." newline bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled." bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled." newline bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled." bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." line.long 0xC "TIM3_SR,TIM3 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1" newline bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM3_EGR,TIM3 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" newline bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM3_CCMR1_INPUT,TIM3 capture/compare mode register 1" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM3_CCMR1_OUTPUT,TIM3 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM3_CCMR2_INPUT,TIM3 capture/compare mode register 2" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0x3 line.long 0x0 "TIM3_CCMR2_OUTPUT,TIM3 capture/compare mode register 2" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.word 0x20++0x1 line.word 0x0 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1" bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1" newline bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1" bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1" newline bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1" bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1" newline bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM3_CNT,TIM3 counter" bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1" hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value" group.word 0x28++0x1 line.word 0x0 "TIM3_PSC,TIM3 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM3_ARR,TIM3 auto-reload register" hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "TIM3_CCR1,TIM3 capture/compare register 1" hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM3_CCR2,TIM3 capture/compare register 2" hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM3_CCR3,TIM3 capture/compare register 3" hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value" line.long 0xC "TIM3_CCR4,TIM3 capture/compare register 4" hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value" group.long 0x58++0xF line.long 0x0 "TIM3_ECR,TIM3 timer encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x4 "TIM3_TISEL,TIM3 timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x8 "TIM3_AF1,TIM3 alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "TIM3_AF2,TIM3 alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM3_DCR,TIM3 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM3_DMAR,TIM3 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM3_S" base ad:0x50000400 group.word 0x0++0x1 line.word 0x0 "TIM3_CR1,TIM3 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM3_CR2,TIM3 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.." bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" line.long 0x4 "TIM3_SMCR,TIM3 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: Internal trigger 2 (tim_itr2),3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM3_DIER,TIM3 DMA/Interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled." bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled." newline bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled." bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled." newline bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled." bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled." newline bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled." bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." line.long 0xC "TIM3_SR,TIM3 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1" newline bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM3_EGR,TIM3 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" newline bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM3_CCMR1_INPUT,TIM3 capture/compare mode register 1" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM3_CCMR1_OUTPUT,TIM3 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM3_CCMR2_INPUT,TIM3 capture/compare mode register 2" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0x3 line.long 0x0 "TIM3_CCMR2_OUTPUT,TIM3 capture/compare mode register 2" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.word 0x20++0x1 line.word 0x0 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1" bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1" newline bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1" bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1" newline bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1" bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1" newline bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM3_CNT,TIM3 counter" bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1" hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value" group.word 0x28++0x1 line.word 0x0 "TIM3_PSC,TIM3 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM3_ARR,TIM3 auto-reload register" hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "TIM3_CCR1,TIM3 capture/compare register 1" hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM3_CCR2,TIM3 capture/compare register 2" hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM3_CCR3,TIM3 capture/compare register 3" hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value" line.long 0xC "TIM3_CCR4,TIM3 capture/compare register 4" hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value" group.long 0x58++0xF line.long 0x0 "TIM3_ECR,TIM3 timer encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x4 "TIM3_TISEL,TIM3 timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x8 "TIM3_AF1,TIM3 alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "TIM3_AF2,TIM3 alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM3_DCR,TIM3 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM3_DMAR,TIM3 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM4" base ad:0x40000800 group.word 0x0++0x1 line.word 0x0 "TIM4_CR1,TIM4 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM4_CR2,TIM4 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.." bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" line.long 0x4 "TIM4_SMCR,TIM4 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: Internal trigger 2 (tim_itr2),3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM4_DIER,TIM4 DMA/Interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled." bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled." newline bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled." bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled." newline bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled." bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled." newline bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled." bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." line.long 0xC "TIM4_SR,TIM4 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1" newline bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM4_EGR,TIM4 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" newline bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM4_CCMR1_INPUT,TIM4 capture/compare mode register 1" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM4_CCMR1_OUTPUT,TIM4 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM4_CCMR2_INPUT,TIM4 capture/compare mode register 2" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0x3 line.long 0x0 "TIM4_CCMR2_OUTPUT,TIM4 capture/compare mode register 2" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.word 0x20++0x1 line.word 0x0 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1" bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1" newline bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1" bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1" newline bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1" bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1" newline bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM4_CNT,TIM4 counter" bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1" hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value" group.word 0x28++0x1 line.word 0x0 "TIM4_PSC,TIM4 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM4_ARR,TIM4 auto-reload register" hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "TIM4_CCR1,TIM4 capture/compare register 1" hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM4_CCR2,TIM4 capture/compare register 2" hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM4_CCR3,TIM4 capture/compare register 3" hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value" line.long 0xC "TIM4_CCR4,TIM4 capture/compare register 4" hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value" group.long 0x58++0xF line.long 0x0 "TIM4_ECR,TIM4 timer encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x4 "TIM4_TISEL,TIM4 timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x8 "TIM4_AF1,TIM4 alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "TIM4_AF2,TIM4 alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM4_DCR,TIM4 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM4_DMAR,TIM4 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM4_S" base ad:0x50000800 group.word 0x0++0x1 line.word 0x0 "TIM4_CR1,TIM4 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM4_CR2,TIM4 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.." bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" line.long 0x4 "TIM4_SMCR,TIM4 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: Internal trigger 2 (tim_itr2),3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM4_DIER,TIM4 DMA/Interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled." bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled." newline bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled." bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled." newline bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled." bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled." newline bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled." bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." line.long 0xC "TIM4_SR,TIM4 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1" newline bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM4_EGR,TIM4 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" newline bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM4_CCMR1_INPUT,TIM4 capture/compare mode register 1" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM4_CCMR1_OUTPUT,TIM4 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM4_CCMR2_INPUT,TIM4 capture/compare mode register 2" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0x3 line.long 0x0 "TIM4_CCMR2_OUTPUT,TIM4 capture/compare mode register 2" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.word 0x20++0x1 line.word 0x0 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1" bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1" newline bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1" bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1" newline bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1" bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1" newline bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM4_CNT,TIM4 counter" bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1" hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value" group.word 0x28++0x1 line.word 0x0 "TIM4_PSC,TIM4 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM4_ARR,TIM4 auto-reload register" hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "TIM4_CCR1,TIM4 capture/compare register 1" hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM4_CCR2,TIM4 capture/compare register 2" hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM4_CCR3,TIM4 capture/compare register 3" hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value" line.long 0xC "TIM4_CCR4,TIM4 capture/compare register 4" hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value" group.long 0x58++0xF line.long 0x0 "TIM4_ECR,TIM4 timer encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x4 "TIM4_TISEL,TIM4 timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x8 "TIM4_AF1,TIM4 alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "TIM4_AF2,TIM4 alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM4_DCR,TIM4 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM4_DMAR,TIM4 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM5" base ad:0x40000C00 group.word 0x0++0x1 line.word 0x0 "TIM5_CR1,TIM5 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM5_CR2,TIM5 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.." bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" line.long 0x4 "TIM5_SMCR,TIM5 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: Internal trigger 2 (tim_itr2),3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM5_DIER,TIM5 DMA/Interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled." bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled." newline bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled." bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled." newline bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled." bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled." newline bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled." bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." line.long 0xC "TIM5_SR,TIM5 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1" newline bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM5_EGR,TIM5 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" newline bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM5_CCMR1_INPUT,TIM5 capture/compare mode register 1" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM5_CCMR1_OUTPUT,TIM5 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM5_CCMR2_INPUT,TIM5 capture/compare mode register 2" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0x3 line.long 0x0 "TIM5_CCMR2_OUTPUT,TIM5 capture/compare mode register 2" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.word 0x20++0x1 line.word 0x0 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1" bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1" newline bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1" bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1" newline bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1" bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1" newline bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM5_CNT,TIM5 counter" bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1" hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value" group.word 0x28++0x1 line.word 0x0 "TIM5_PSC,TIM5 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM5_ARR,TIM5 auto-reload register" hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "TIM5_CCR1,TIM5 capture/compare register 1" hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM5_CCR2,TIM5 capture/compare register 2" hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM5_CCR3,TIM5 capture/compare register 3" hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value" line.long 0xC "TIM5_CCR4,TIM5 capture/compare register 4" hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value" group.long 0x58++0xF line.long 0x0 "TIM5_ECR,TIM5 timer encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x4 "TIM5_TISEL,TIM5 timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x8 "TIM5_AF1,TIM5 alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "TIM5_AF2,TIM5 alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM5_DCR,TIM5 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM5_DMAR,TIM5 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM5_S" base ad:0x50000C00 group.word 0x0++0x1 line.word 0x0 "TIM5_CR1,TIM5 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM5_CR2,TIM5 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.." bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" line.long 0x4 "TIM5_SMCR,TIM5 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: Internal trigger 2 (tim_itr2),3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)" newline bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf" bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM5_DIER,TIM5 DMA/Interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled." bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled." newline bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled." bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled." newline bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled." bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled." newline bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled." bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." line.long 0xC "TIM5_SR,TIM5 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1" newline bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM5_EGR,TIM5 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" newline bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM5_CCMR1_INPUT,TIM5 capture/compare mode register 1" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM5_CCMR1_OUTPUT,TIM5 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM5_CCMR2_INPUT,TIM5 capture/compare mode register 2" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0x3 line.long 0x0 "TIM5_CCMR2_OUTPUT,TIM5 capture/compare mode register 2" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.word 0x20++0x1 line.word 0x0 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1" bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1" newline bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1" bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1" newline bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1" bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1" newline bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM5_CNT,TIM5 counter" bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1" hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value" group.word 0x28++0x1 line.word 0x0 "TIM5_PSC,TIM5 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM5_ARR,TIM5 auto-reload register" hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "TIM5_CCR1,TIM5 capture/compare register 1" hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM5_CCR2,TIM5 capture/compare register 2" hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM5_CCR3,TIM5 capture/compare register 3" hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value" line.long 0xC "TIM5_CCR4,TIM5 capture/compare register 4" hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value" group.long 0x58++0xF line.long 0x0 "TIM5_ECR,TIM5 timer encoder control register" bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x4 "TIM5_TISEL,TIM5 timer input selection register" hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x8 "TIM5_AF1,TIM5 alternate function register 1" hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection" line.long 0xC "TIM5_AF2,TIM5 alternate function register 2" bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM5_DCR,TIM5 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM5_DMAR,TIM5 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM6" base ad:0x40001000 group.word 0x0++0x1 line.word 0x0 "TIM6_CR1,TIM6 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x3 line.long 0x0 "TIM6_CR2,TIM6 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal tim_cnt_en is..,2: Update - The update event is selected as a..,?,?,?,?,?" group.word 0xC++0x1 line.word 0x0 "TIM6_DIER,TIM6 DMA/Interrupt enable register" bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM6_SR,TIM6 status register" bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM6_EGR,TIM6 event generation register" bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.." group.long 0x24++0x3 line.long 0x0 "TIM6_CNT,TIM6 counter" rbitfld.long 0x0 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM6_PSC,TIM6 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM6_ARR,TIM6 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" tree.end tree "TIM6_S" base ad:0x50001000 group.word 0x0++0x1 line.word 0x0 "TIM6_CR1,TIM6 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x3 line.long 0x0 "TIM6_CR2,TIM6 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal tim_cnt_en is..,2: Update - The update event is selected as a..,?,?,?,?,?" group.word 0xC++0x1 line.word 0x0 "TIM6_DIER,TIM6 DMA/Interrupt enable register" bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM6_SR,TIM6 status register" bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM6_EGR,TIM6 event generation register" bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.." group.long 0x24++0x3 line.long 0x0 "TIM6_CNT,TIM6 counter" rbitfld.long 0x0 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM6_PSC,TIM6 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM6_ARR,TIM6 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" tree.end tree "TIM7" base ad:0x40001400 group.word 0x0++0x1 line.word 0x0 "TIM7_CR1,TIM7 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x3 line.long 0x0 "TIM7_CR2,TIM7 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal tim_cnt_en is..,2: Update - The update event is selected as a..,?,?,?,?,?" group.word 0xC++0x1 line.word 0x0 "TIM7_DIER,TIM7 DMA/Interrupt enable register" bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM7_SR,TIM7 status register" bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM7_EGR,TIM7 event generation register" bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.." group.long 0x24++0x3 line.long 0x0 "TIM7_CNT,TIM7 counter" rbitfld.long 0x0 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM7_PSC,TIM7 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM7_ARR,TIM7 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" tree.end tree "TIM8" base ad:0x42000400 group.word 0x0++0x1 line.word 0x0 "TIM8_CR1,TIM8 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub>=t less than..,1: t less than sub>DTS less than /sub>=2*t less..,2: t less than sub>DTS less than /sub>=4*t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM8_CR2,TIM8 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x0 18. "OIS6,Output idle state 6 (tim_oc6 output)" "0,1" newline bitfld.long 0x0 16. "OIS5,Output idle state 5 (tim_oc5 output)" "0,1" bitfld.long 0x0 15. "OIS4N,Output idle state 4 (tim_oc4n output)" "0,1" newline bitfld.long 0x0 14. "OIS4,Output idle state 4 (tim_oc4 output)" "0,1" bitfld.long 0x0 13. "OIS3N,Output idle state 3 (tim_oc3n output)" "0,1" newline bitfld.long 0x0 12. "OIS3,Output idle state 3 (tim_oc3n output)" "0,1" bitfld.long 0x0 11. "OIS2N,Output idle state 2 (tim_oc2n output)" "0,1" newline bitfld.long 0x0 10. "OIS2,Output idle state 2 (tim_oc2 output)" "0,1" bitfld.long 0x0 9. "OIS1N,Output idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0" newline bitfld.long 0x0 8. "OIS1,Output idle state 1 (tim_oc1 output)" "0: tim_oc1=0 (after a dead-time) when MOE=0,1: tim_oc1=1 (after a dead-time) when MOE=0" bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: tim_ti1_in[15:0] tim_ti2_in[15:0] and.." newline bitfld.long 0x0 4.--6. "MMS,MMS[2:0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" newline bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." line.long 0x4 "TIM8_SMCR,TIM8 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM8_DIER,TIM8 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM8_SR,TIM8 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM8_EGR,TIM8 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: CCxE CCxNE and OCxM bits update (providing CCPC.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM8_CCMR1_Input,TIM8 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM8_CCMR1_Output,TIM8 capture/compare mode register 1 [alternate]" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM8_CCMR2_Input,TIM8 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0xB line.long 0x0 "TIM8_CCMR2_Output,TIM8 capture/compare mode register 2 [alternate]" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0: Frozen - The comparison between the output..,1: Set channel 3 to active level on match.,2: Set channel 3 to inactive level on match.,3: Toggle - tim_oc3ref toggles when..,4: Force inactive level - tim_oc3ref is forced low.,5: Force active level - tim_oc3ref is forced high.,6: PWM mode 1 - In upcounting channel 3 is active..,7: PWM mode 2 - In upcounting channel 3 is inactive.." bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM8_CNT,TIM8 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM8_PSC,TIM8 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM8_ARR,TIM8 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM8_RCR,TIM8 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM8_CCR1,TIM8 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM8_CCR2,TIM8 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM8_CCR3,TIM8 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM8_CCR4,TIM8 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM8_BDTR,TIM8 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: In response to a break 2 event. OC and OCN..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM8_CCR5,TIM8 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM8_CCR6,TIM8 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM8_CCMR3,TIM8 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M_1,OC6M[3]" "0,1" bitfld.long 0x1C 16. "OC5M_1,OC5M[3]" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M,OC6M[2:0]: Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M,OC5M[2:0]: Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM8_DTR2,TIM8 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM8_ECR,TIM8 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled when tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM8_TISEL,TIM8 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x2C "TIM8_AF1,TIM8 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM8_AF2,TIM8 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM8_DCR,TIM8 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM8_DMAR,TIM8 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM8_S" base ad:0x52000400 group.word 0x0++0x1 line.word 0x0 "TIM8_CR1,TIM8 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub>=t less than..,1: t less than sub>DTS less than /sub>=2*t less..,2: t less than sub>DTS less than /sub>=4*t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0xF line.long 0x0 "TIM8_CR2,TIM8 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x0 18. "OIS6,Output idle state 6 (tim_oc6 output)" "0,1" newline bitfld.long 0x0 16. "OIS5,Output idle state 5 (tim_oc5 output)" "0,1" bitfld.long 0x0 15. "OIS4N,Output idle state 4 (tim_oc4n output)" "0,1" newline bitfld.long 0x0 14. "OIS4,Output idle state 4 (tim_oc4 output)" "0,1" bitfld.long 0x0 13. "OIS3N,Output idle state 3 (tim_oc3n output)" "0,1" newline bitfld.long 0x0 12. "OIS3,Output idle state 3 (tim_oc3n output)" "0,1" bitfld.long 0x0 11. "OIS2N,Output idle state 2 (tim_oc2n output)" "0,1" newline bitfld.long 0x0 10. "OIS2,Output idle state 2 (tim_oc2 output)" "0,1" bitfld.long 0x0 9. "OIS1N,Output idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0" newline bitfld.long 0x0 8. "OIS1,Output idle state 1 (tim_oc1 output)" "0: tim_oc1=0 (after a dead-time) when MOE=0,1: tim_oc1=1 (after a dead-time) when MOE=0" bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: tim_ti1_in[15:0] tim_ti2_in[15:0] and.." newline bitfld.long 0x0 4.--6. "MMS,MMS[2:0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.." bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" newline bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." line.long 0x4 "TIM8_SMCR,TIM8 slave mode control register" bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timer's Update..,1: The transfer is triggered by the Index event" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" newline bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),7: External Trigger input (tim_etrf)" newline bitfld.long 0x4 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." line.long 0x8 "TIM8_DIER,TIM8 DMA/interrupt enable register" bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled" bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled" newline bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled" bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled" newline bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" line.long 0xC "TIM8_SR,TIM8 status register" bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected" bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected" newline bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change" bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred" newline bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1" newline bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1" bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" newline bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1" newline bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1" bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1" newline bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM8_EGR,TIM8 event generation register" bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: CCxE CCxNE and OCxM bits update (providing CCPC.." newline bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM8_CCMR1_Input,TIM8 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x7 line.long 0x0 "TIM8_CCMR1_Output,TIM8 capture/compare mode register 1 [alternate]" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." line.long 0x4 "TIM8_CCMR2_Input,TIM8 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." group.long 0x1C++0xB line.long 0x0 "TIM8_CCMR2_Output,TIM8 capture/compare mode register 2 [alternate]" bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1" bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0: Frozen - The comparison between the output..,1: Set channel 3 to active level on match.,2: Set channel 3 to inactive level on match.,3: Toggle - tim_oc3ref toggles when..,4: Force inactive level - tim_oc3ref is forced low.,5: Force active level - tim_oc3ref is forced high.,6: PWM mode 1 - In upcounting channel 3 is active..,7: PWM mode 2 - In upcounting channel 3 is inactive.." bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.." line.long 0x4 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1" bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1" newline bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1" bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1" newline bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1" bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1" newline bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1" bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1" newline bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1" newline bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1" bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low." bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM8_CNT,TIM8 counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM8_PSC,TIM8 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM8_ARR,TIM8 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM8_RCR,TIM8 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value" group.long 0x34++0x33 line.long 0x0 "TIM8_CCR1,TIM8 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM8_CCR2,TIM8 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" line.long 0x8 "TIM8_CCR3,TIM8 capture/compare register 3" hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value" line.long 0xC "TIM8_CCR4,TIM8 capture/compare register 4" hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value" line.long 0x10 "TIM8_BDTR,TIM8 break and dead-time register" bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" newline bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1" bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high" bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x10 15. "MOE,Main output enable" "0: In response to a break 2 event. OC and OCN..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x14 "TIM8_CCR5,TIM8 capture/compare register 5" bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.." bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.." newline bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref" hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value" line.long 0x18 "TIM8_CCR6,TIM8 capture/compare register 6" hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value" line.long 0x1C "TIM8_CCMR3,TIM8 capture/compare mode register 3" bitfld.long 0x1C 24. "OC6M_1,OC6M[3]" "0,1" bitfld.long 0x1C 16. "OC5M_1,OC5M[3]" "0,1" newline bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x1C 12.--14. "OC6M,OC6M[2:0]: Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x1C 4.--6. "OC5M,OC5M[2:0]: Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x20 "TIM8_DTR2,TIM8 timer deadtime register 2" bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup" line.long 0x24 "TIM8_ECR,TIM8 timer encoder control register" bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width" newline bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11" bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter" newline bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled when tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,?" bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,?" newline bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled" line.long 0x28 "TIM8_TISEL,TIM8 timer input selection register" hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input" hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input" newline hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input" hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input" line.long 0x2C "TIM8_AF1,TIM8 alternate function option register 1" hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection" bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.." newline bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.." bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.." newline bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.." bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.." newline bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" newline bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" newline bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" newline bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" newline bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x30 "TIM8_AF2,TIM8 alternate function register 2" bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,?,?,?,?,?,7: tim_ocref_clr7" bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.." newline bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.." bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.." newline bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.." bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.." newline bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled" bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled" newline bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled" bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled" newline bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled" bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled" newline bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled" bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled" newline bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled" group.long 0x3DC++0x7 line.long 0x0 "TIM8_DCR,TIM8 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM8_DMAR,TIM8 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM9" base ad:0x42004C00 group.word 0x0++0x1 line.word 0x0 "TIM9_CR1,TIM9 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow generates an update.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x7 line.long 0x0 "TIM9_CR2,TIM12 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: The tim_ti1_in[15:0] and tim_ti2_in[15:0].." newline bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,?,?" line.long 0x4 "TIM9_SMCR,TIM9 slave mode control register" bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),?" newline bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." group.word 0xC++0x1 line.word 0x0 "TIM9_DIER,TIM9 Interrupt enable register" bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM9_SR,TIM9 status register" bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM9_EGR,TIM9 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in the TIMx_SR register." bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initializes the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM9_CCMR1_Input,TIM9 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x3 line.long 0x0 "TIM9_CCMR1_Output,TIM9 capture/compare mode register 1 [alternate]" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" newline bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. The..,2: Set channel 1 to inactive level on match. The..,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low,5: Force active level - tim_oc1ref is forced high,6: PWM mode 1 - channel 1 is active as long as..,7: PWM mode 2 - channel 1 is inactive as long as.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on the counter..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.word 0x20++0x1 line.word 0x0 "TIM9_CCER,TIM9 capture/compare enable register" bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity" "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity" "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM9_CNT,TIM9 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM9_PSC,TIM9 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM9_ARR,TIM9 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x7 line.long 0x0 "TIM9_CCR1,TIM9 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM9_CCR2,TIM9 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" group.word 0x5C++0x1 line.word 0x0 "TIM9_TISEL,TIM9 timer input selection register" hexmask.word.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[15:0] input" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end tree "TIM9_S" base ad:0x52004C00 group.word 0x0++0x1 line.word 0x0 "TIM9_CR1,TIM9 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow generates an update.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x7 line.long 0x0 "TIM9_CR2,TIM12 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: The tim_ti1_in[15:0] and tim_ti2_in[15:0].." newline bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,?,?" line.long 0x4 "TIM9_SMCR,TIM9 slave mode control register" bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),?" newline bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." group.word 0xC++0x1 line.word 0x0 "TIM9_DIER,TIM9 Interrupt enable register" bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM9_SR,TIM9 status register" bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM9_EGR,TIM9 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in the TIMx_SR register." bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initializes the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM9_CCMR1_Input,TIM9 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x3 line.long 0x0 "TIM9_CCMR1_Output,TIM9 capture/compare mode register 1 [alternate]" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" newline bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. The..,2: Set channel 1 to inactive level on match. The..,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low,5: Force active level - tim_oc1ref is forced high,6: PWM mode 1 - channel 1 is active as long as..,7: PWM mode 2 - channel 1 is inactive as long as.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on the counter..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.word 0x20++0x1 line.word 0x0 "TIM9_CCER,TIM9 capture/compare enable register" bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity" "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity" "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM9_CNT,TIM9 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM9_PSC,TIM9 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM9_ARR,TIM9 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x7 line.long 0x0 "TIM9_CCR1,TIM9 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM9_CCR2,TIM9 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" group.word 0x5C++0x1 line.word 0x0 "TIM9_TISEL,TIM9 timer input selection register" hexmask.word.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[15:0] input" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end tree "TIM10" base ad:0x40003000 group.word 0x0++0x1 line.word 0x0 "TIM10_CR1,TIM10 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0xC++0x1 line.word 0x0 "TIM10_DIER,TIM10 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM10_SR,TIM10 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM10_EGR,TIM10 event generation register" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM10_CCMR1_Input,TIM10 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM10_CCMR1_Output,TIM10 capture/compare mode register 1 [alternate]" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when TIMx_CNT =..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM10_CCER,TIM10 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1" bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM10_CNT,TIM10 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM10_PSC,TIM10 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM10_ARR,TIM10 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x3 line.long 0x0 "TIM10_CCR1,TIM10 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" group.word 0x5C++0x1 line.word 0x0 "TIM10_TISEL,TIM10 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end tree "TIM10_S" base ad:0x50003000 group.word 0x0++0x1 line.word 0x0 "TIM10_CR1,TIM10 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0xC++0x1 line.word 0x0 "TIM10_DIER,TIM10 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM10_SR,TIM10 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM10_EGR,TIM10 event generation register" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM10_CCMR1_Input,TIM10 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM10_CCMR1_Output,TIM10 capture/compare mode register 1 [alternate]" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when TIMx_CNT =..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM10_CCER,TIM10 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1" bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM10_CNT,TIM10 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM10_PSC,TIM10 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM10_ARR,TIM10 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x3 line.long 0x0 "TIM10_CCR1,TIM10 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" group.word 0x5C++0x1 line.word 0x0 "TIM10_TISEL,TIM10 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end tree "TIM11" base ad:0x40003400 group.word 0x0++0x1 line.word 0x0 "TIM11_CR1,TIM11 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0xC++0x1 line.word 0x0 "TIM11_DIER,TIM11 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM11_SR,TIM11 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM11_EGR,TIM11 event generation register" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM11_CCMR1_Input,TIM11 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM11_CCMR1_Output,TIM11 capture/compare mode register 1 [alternate]" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when TIMx_CNT =..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM11_CCER,TIM11 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1" bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM11_CNT,TIM11 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM11_PSC,TIM11 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM11_ARR,TIM11 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x3 line.long 0x0 "TIM11_CCR1,TIM11 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" group.word 0x5C++0x1 line.word 0x0 "TIM11_TISEL,TIM11 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end tree "TIM11_S" base ad:0x50003400 group.word 0x0++0x1 line.word 0x0 "TIM11_CR1,TIM11 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0xC++0x1 line.word 0x0 "TIM11_DIER,TIM11 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM11_SR,TIM11 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM11_EGR,TIM11 event generation register" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM11_CCMR1_Input,TIM11 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM11_CCMR1_Output,TIM11 capture/compare mode register 1 [alternate]" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when TIMx_CNT =..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM11_CCER,TIM11 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1" bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM11_CNT,TIM11 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM11_PSC,TIM11 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM11_ARR,TIM11 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x3 line.long 0x0 "TIM11_CCR1,TIM11 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" group.word 0x5C++0x1 line.word 0x0 "TIM11_TISEL,TIM11 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end tree "TIM12" base ad:0x40001800 group.word 0x0++0x1 line.word 0x0 "TIM12_CR1,TIM12 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow generates an update.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x7 line.long 0x0 "TIM12_CR2,TIM12 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: The tim_ti1_in[15:0] and tim_ti2_in[15:0].." newline bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,?,?" line.long 0x4 "TIM12_SMCR,TIM12 slave mode control register" bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),?" newline bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." group.word 0xC++0x1 line.word 0x0 "TIM12_DIER,TIM12 Interrupt enable register" bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM12_SR,TIM12 status register" bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM12_EGR,TIM12 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in the TIMx_SR register." bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initializes the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM12_CCMR1_Input,TIM12 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x3 line.long 0x0 "TIM12_CCMR1_Output,TIM12 capture/compare mode register 1 [alternate]" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" newline bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. The..,2: Set channel 1 to inactive level on match. The..,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low,5: Force active level - tim_oc1ref is forced high,6: PWM mode 1 - channel 1 is active as long as..,7: PWM mode 2 - channel 1 is inactive as long as.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on the counter..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.word 0x20++0x1 line.word 0x0 "TIM12_CCER,TIM12 capture/compare enable register" bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity" "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity" "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM12_CNT,TIM12 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM12_PSC,TIM12 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM12_ARR,TIM12 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x7 line.long 0x0 "TIM12_CCR1,TIM12 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM12_CCR2,TIM12 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" group.word 0x5C++0x1 line.word 0x0 "TIM12_TISEL,TIM12 timer input selection register" hexmask.word.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[15:0] input" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end tree "TIM12_S" base ad:0x50001800 group.word 0x0++0x1 line.word 0x0 "TIM12_CR1,TIM12 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow generates an update.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x7 line.long 0x0 "TIM12_CR2,TIM12 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: The tim_ti1_in[15:0] and tim_ti2_in[15:0].." newline bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,?,?" line.long 0x4 "TIM12_SMCR,TIM12 slave mode control register" bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" newline bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),?" newline bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." group.word 0xC++0x1 line.word 0x0 "TIM12_DIER,TIM12 Interrupt enable register" bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM12_SR,TIM12 status register" bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM12_EGR,TIM12 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in the TIMx_SR register." bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initializes the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM12_CCMR1_Input,TIM12 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x3 line.long 0x0 "TIM12_CCMR1_Output,TIM12 capture/compare mode register 1 [alternate]" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" newline bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. The..,2: Set channel 1 to inactive level on match. The..,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low,5: Force active level - tim_oc1ref is forced high,6: PWM mode 1 - channel 1 is active as long as..,7: PWM mode 2 - channel 1 is inactive as long as.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on the counter..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.word 0x20++0x1 line.word 0x0 "TIM12_CCER,TIM12 capture/compare enable register" bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity" "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity" "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM12_CNT,TIM12 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM12_PSC,TIM12 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM12_ARR,TIM12 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x7 line.long 0x0 "TIM12_CCR1,TIM12 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM12_CCR2,TIM12 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" group.word 0x5C++0x1 line.word 0x0 "TIM12_TISEL,TIM12 timer input selection register" hexmask.word.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[15:0] input" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end tree "TIM13" base ad:0x40001C00 group.word 0x0++0x1 line.word 0x0 "TIM13_CR1,TIM13 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0xC++0x1 line.word 0x0 "TIM13_DIER,TIM13 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM13_SR,TIM13 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM13_EGR,TIM13 event generation register" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM13_CCMR1_Input,TIM13 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM13_CCMR1_Output,TIM13 capture/compare mode register 1 [alternate]" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when TIMx_CNT =..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM13_CCER,TIM13 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1" bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM13_CNT,TIM13 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM13_PSC,TIM13 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM13_ARR,TIM13 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x3 line.long 0x0 "TIM13_CCR1,TIM13 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" group.word 0x5C++0x1 line.word 0x0 "TIM13_TISEL,TIM13 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end tree "TIM13_S" base ad:0x50001C00 group.word 0x0++0x1 line.word 0x0 "TIM13_CR1,TIM13 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0xC++0x1 line.word 0x0 "TIM13_DIER,TIM13 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM13_SR,TIM13 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM13_EGR,TIM13 event generation register" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM13_CCMR1_Input,TIM13 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM13_CCMR1_Output,TIM13 capture/compare mode register 1 [alternate]" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when TIMx_CNT =..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM13_CCER,TIM13 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1" bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM13_CNT,TIM13 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM13_PSC,TIM13 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM13_ARR,TIM13 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x3 line.long 0x0 "TIM13_CCR1,TIM13 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" group.word 0x5C++0x1 line.word 0x0 "TIM13_TISEL,TIM13 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end tree "TIM14" base ad:0x40002000 group.word 0x0++0x1 line.word 0x0 "TIM14_CR1,TIM14 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0xC++0x1 line.word 0x0 "TIM14_DIER,TIM14 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM14_SR,TIM14 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM14_EGR,TIM14 event generation register" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM14_CCMR1_Input,TIM14 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM14_CCMR1_Output,TIM14 capture/compare mode register 1 [alternate]" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when TIMx_CNT =..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM14_CCER,TIM14 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1" bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM14_CNT,TIM14 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM14_PSC,TIM14 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM14_ARR,TIM14 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x3 line.long 0x0 "TIM14_CCR1,TIM14 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" group.word 0x5C++0x1 line.word 0x0 "TIM14_TISEL,TIM14 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end tree "TIM14_S" base ad:0x50002000 group.word 0x0++0x1 line.word 0x0 "TIM14_CR1,TIM14 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub> = t less..,1: t less than sub>DTS less than /sub> = 2 t less..,2: t less than sub>DTS less than /sub> = 4 t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0xC++0x1 line.word 0x0 "TIM14_DIER,TIM14 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM14_SR,TIM14 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM14_EGR,TIM14 event generation register" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM14_CCMR1_Input,TIM14 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM14_CCMR1_Output,TIM14 capture/compare mode register 1 [alternate]" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when TIMx_CNT =..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM14_CCER,TIM14 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1" bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: tim_oc1 active high (output mode) / Edge..,1: tim_oc1 active low (output mode) / Edge.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.." group.long 0x24++0x3 line.long 0x0 "TIM14_CNT,TIM14 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM14_PSC,TIM14 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM14_ARR,TIM14 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.long 0x34++0x3 line.long 0x0 "TIM14_CCR1,TIM14 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" group.word 0x5C++0x1 line.word 0x0 "TIM14_TISEL,TIM14 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" tree.end sif (cpuis("STM32N645*")||cpuis("STM32N655*")) tree "TIM7_S" base ad:0x50001400 group.word 0x0++0x1 line.word 0x0 "TIM7_CR1,TIM7 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x3 line.long 0x0 "TIM7_CR2,TIM7 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal tim_cnt_en is..,2: Update - The update event is selected as a..,?,?,?,?,?" group.word 0xC++0x1 line.word 0x0 "TIM7_DIER,TIM7 DMA/Interrupt enable register" bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM7_SR,TIM7 status register" bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM7_EGR,TIM7 event generation register" bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.." group.long 0x24++0x3 line.long 0x0 "TIM7_CNT,TIM7 counter" rbitfld.long 0x0 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM7_PSC,TIM7 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM7_ARR,TIM7 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" tree.end endif tree "TIM15" base ad:0x42004000 group.word 0x0++0x1 line.word 0x0 "TIM15_CR1,TIM15 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub>= t less than..,1: t less than sub>DTS less than /sub> = 2*t less..,2: t less than sub>DTS less than /sub> = 4*t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIM15_ARR register is not buffered,1: TIM15_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x7 line.long 0x0 "TIM15_CR2,TIM15 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 10. "OIS2,Output idle state 2 (tim_oc2 output)" "0: tim_oc2=0 when MOE=0,1: tim_oc2=1 when MOE=0" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0" bitfld.long 0x0 8. "OIS1,Output Idle state 1 (tim_oc1 output)" "0: tim_oc1=0 after a dead-time when MOE=0,1: tim_oc1=1 after a dead-time when MOE=0" newline bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: The tim_ti1_in[15:0] and tim_ti2_in[15:0].." bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIM15_EGR register..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,?,?" newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." line.long 0x4 "TIM15_SMCR,TIM15 slave mode control register" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" newline bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." newline bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),?" bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." group.word 0xC++0x1 line.word 0x0 "TIM15_DIER,TIM15 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.word 0x0 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM15_SR,TIM15 status register" bitfld.word 0x0 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in.." newline bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.." bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending" newline bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending" bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." group.word 0x14++0x1 line.word 0x0 "TIM15_EGR,TIM15 event generation register" bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIM15_SR register." newline bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.." bitfld.word 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,?" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM15_CCMR1_INPUT,TIM15 capture/compare mode register 1" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x3 line.long 0x0 "TIM15_CCMR1_OUTPUT,TIM15 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: C2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIM15_CCR1 disabled.,1: Preload register on TIM15_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.word 0x20++0x1 line.word 0x0 "TIM15_CCER,TIM15 capture/compare enable register" bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: tim_oc1n active high,1: tim_oc1n active low" newline bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM15_CNT,TIM15 counter" rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM15_PSC,TIM15 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM15_ARR,TIM15 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM15_RCR,TIM15 repetition counter register" hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter reload value" group.long 0x34++0x7 line.long 0x0 "TIM15_CCR1,TIM15 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM15_CCR2,TIM15 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" group.long 0x44++0x3 line.long 0x0 "TIM15_BDTR,TIM15 break and dead-time register" bitfld.long 0x0 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" bitfld.long 0x0 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0: tim_ocx and tim_ocxn outputs are disabled or..,1: tim_ocx and tim_ocxn outputs are enabled if.." newline bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" newline bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (tim_brk and tim_sys_brk clock..,?" bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive tim_ocx/tim_ocxn outputs are..,1: When inactive tim_ocx/tim_ocxn outputs are.." newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive tim_ocx/tim_ocxn outputs are..,1: When inactive tim_ocx/tim_ocxn outputs are.." bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIM15_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: OCK Level 3 = LOCK Level 2 + CC Control bits.." newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "TIM15_DTR2,TIM15 timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TIM15_TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[15:0] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" line.long 0x4 "TIM15_AF1,TIM15 alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input is active high,1: tim_brk_cmp4 input is active low" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input is active high,1: tim_brk_cmp3 input is active low" newline bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input is active high,1: tim_brk_cmp2 input is active low" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input is active high,1: tim_brk_cmp1 input is active low" newline bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input is active high,1: TIMx_BKIN input is active low" bitfld.long 0x4 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" newline bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" newline bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" newline bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x8 "TIM15_AF2,TIM15 alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: tim_ocref_clr2,3: tim_ocref_clr3,4: tim_ocref_clr4,5: tim_ocref_clr5,6: tim_ocref_clr6,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM15_DCR,TIM15 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM15_DMAR,TIM15 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM15_S" base ad:0x52004000 group.word 0x0++0x1 line.word 0x0 "TIM15_CR1,TIM15 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub>= t less than..,1: t less than sub>DTS less than /sub> = 2*t less..,2: t less than sub>DTS less than /sub> = 4*t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIM15_ARR register is not buffered,1: TIM15_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x7 line.long 0x0 "TIM15_CR2,TIM15 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 10. "OIS2,Output idle state 2 (tim_oc2 output)" "0: tim_oc2=0 when MOE=0,1: tim_oc2=1 when MOE=0" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0" bitfld.long 0x0 8. "OIS1,Output Idle state 1 (tim_oc1 output)" "0: tim_oc1=0 after a dead-time when MOE=0,1: tim_oc1=1 after a dead-time when MOE=0" newline bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: The tim_ti1_in[15:0] and tim_ti2_in[15:0].." bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIM15_EGR register..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,?,?" newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." line.long 0x4 "TIM15_SMCR,TIM15 slave mode control register" bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled" bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3" newline bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1" bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." newline bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),?" bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." group.word 0xC++0x1 line.word 0x0 "TIM15_DIER,TIM15 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.word 0x0 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM15_SR,TIM15 status register" bitfld.word 0x0 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in.." newline bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.." bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending" newline bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending" bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." group.word 0x14++0x1 line.word 0x0 "TIM15_EGR,TIM15 event generation register" bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIM15_SR register." newline bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.." bitfld.word 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,?" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM15_CCMR1_INPUT,TIM15 capture/compare mode register 1" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.long 0x18++0x3 line.long 0x0 "TIM15_CCMR1_OUTPUT,TIM15 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: C2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIM15_CCR1 disabled.,1: Preload register on TIM15_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.." group.word 0x20++0x1 line.word 0x0 "TIM15_CCER,TIM15 capture/compare enable register" bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: tim_oc1n active high,1: tim_oc1n active low" newline bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM15_CNT,TIM15 counter" rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM15_PSC,TIM15 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM15_ARR,TIM15 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM15_RCR,TIM15 repetition counter register" hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter reload value" group.long 0x34++0x7 line.long 0x0 "TIM15_CCR1,TIM15 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value" line.long 0x4 "TIM15_CCR2,TIM15 capture/compare register 2" hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value" group.long 0x44++0x3 line.long 0x0 "TIM15_BDTR,TIM15 break and dead-time register" bitfld.long 0x0 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" bitfld.long 0x0 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0: tim_ocx and tim_ocxn outputs are disabled or..,1: tim_ocx and tim_ocxn outputs are enabled if.." newline bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" newline bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (tim_brk and tim_sys_brk clock..,?" bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive tim_ocx/tim_ocxn outputs are..,1: When inactive tim_ocx/tim_ocxn outputs are.." newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive tim_ocx/tim_ocxn outputs are..,1: When inactive tim_ocx/tim_ocxn outputs are.." bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIM15_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: OCK Level 3 = LOCK Level 2 + CC Control bits.." newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "TIM15_DTR2,TIM15 timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TIM15_TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[15:0] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" line.long 0x4 "TIM15_AF1,TIM15 alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input is active high,1: tim_brk_cmp4 input is active low" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input is active high,1: tim_brk_cmp3 input is active low" newline bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input is active high,1: tim_brk_cmp2 input is active low" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input is active high,1: tim_brk_cmp1 input is active low" newline bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input is active high,1: TIMx_BKIN input is active low" bitfld.long 0x4 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" newline bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" newline bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" newline bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x8 "TIM15_AF2,TIM15 alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: tim_ocref_clr2,3: tim_ocref_clr3,4: tim_ocref_clr4,5: tim_ocref_clr5,6: tim_ocref_clr6,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM15_DCR,TIM15 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM15_DMAR,TIM15 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM16" base ad:0x42004400 group.word 0x0++0x1 line.word 0x0 "TIM16_CR1,TIM16 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub>=t less than..,1: t less than sub>DTS less than /sub>=2*t less..,2: t less than sub>DTS less than /sub>=4*t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: nly counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0x4++0x1 line.word 0x0 "TIM16_CR2,TIM16 control register 2" bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0" bitfld.word 0x0 8. "OIS1,Output Idle state 1 (tim_oc1 output)" "0: tim_oc1=0 after a dead-time when MOE=0,1: tim_oc1=1 after a dead-time when MOE=0" newline bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." newline bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." group.word 0xC++0x1 line.word 0x0 "TIM16_DIER,TIM16 DMA/interrupt enable register" bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" newline bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM16_SR,TIM16 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.." newline bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending" bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM16_EGR,TIM16 event generation register" bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.." bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.." newline bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM16_CCMR1_INPUT,TIM16 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM16_CCMR1_OUTPUT,TIM16 capture/compare mode register 1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: tim_oc1ref is not affected by the tim_ocref_clr..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM16_CCER,TIM16 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: tim_oc1n active high,1: tim_oc1n active low" bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM16_CNT,TIM16 counter" rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM16_PSC,TIM16 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM16_ARR,TIM16 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM16_RCR,TIM16 repetition counter register" hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter reload value" group.long 0x34++0x3 line.long 0x0 "TIM16_CCR1,TIM16 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "TIM16_BDTR,TIM16 break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0: tim_oc1 and tim_oc1n outputs are disabled or..,1: tim_oc1 and tim_oc1n outputs are enabled if.." newline bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" newline bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (tim_brk and tim_sys_brk event)..,?" bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.." newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.." bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "TIM16_DTR2,TIM16 timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" line.long 0x4 "TIM16_AF1,TIM16 alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input is active high,1: tim_brk_cmp4 input is active low" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input is active high,1: tim_brk_cmp3 input is active low" newline bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input is active high,1: tim_brk_cmp2 input is active low" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input is active high,1: tim_brk_cmp1 input is active low" newline bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input is active high,1: TIMx_BKIN input is active low" bitfld.long 0x4 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" newline bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" newline bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" newline bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x8 "TIM16_AF2,TIM16 alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: tim_ocref_clr2,3: tim_ocref_clr3,4: tim_ocref_clr4,5: tim_ocref_clr5,6: tim_ocref_clr6,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM16_DCR,TIM16 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM16_DMAR,TIM16/TIM17 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM16_S" base ad:0x52004400 group.word 0x0++0x1 line.word 0x0 "TIM16_CR1,TIM16 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub>=t less than..,1: t less than sub>DTS less than /sub>=2*t less..,2: t less than sub>DTS less than /sub>=4*t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: nly counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0x4++0x1 line.word 0x0 "TIM16_CR2,TIM16 control register 2" bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0" bitfld.word 0x0 8. "OIS1,Output Idle state 1 (tim_oc1 output)" "0: tim_oc1=0 after a dead-time when MOE=0,1: tim_oc1=1 after a dead-time when MOE=0" newline bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." newline bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." group.word 0xC++0x1 line.word 0x0 "TIM16_DIER,TIM16 DMA/interrupt enable register" bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" newline bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM16_SR,TIM16 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.." newline bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending" bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM16_EGR,TIM16 event generation register" bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.." bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.." newline bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM16_CCMR1_INPUT,TIM16 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM16_CCMR1_OUTPUT,TIM16 capture/compare mode register 1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: tim_oc1ref is not affected by the tim_ocref_clr..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM16_CCER,TIM16 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: tim_oc1n active high,1: tim_oc1n active low" bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM16_CNT,TIM16 counter" rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM16_PSC,TIM16 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM16_ARR,TIM16 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM16_RCR,TIM16 repetition counter register" hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter reload value" group.long 0x34++0x3 line.long 0x0 "TIM16_CCR1,TIM16 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "TIM16_BDTR,TIM16 break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0: tim_oc1 and tim_oc1n outputs are disabled or..,1: tim_oc1 and tim_oc1n outputs are enabled if.." newline bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" newline bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (tim_brk and tim_sys_brk event)..,?" bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.." newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.." bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "TIM16_DTR2,TIM16 timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" line.long 0x4 "TIM16_AF1,TIM16 alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input is active high,1: tim_brk_cmp4 input is active low" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input is active high,1: tim_brk_cmp3 input is active low" newline bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input is active high,1: tim_brk_cmp2 input is active low" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input is active high,1: tim_brk_cmp1 input is active low" newline bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input is active high,1: TIMx_BKIN input is active low" bitfld.long 0x4 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" newline bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" newline bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" newline bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x8 "TIM16_AF2,TIM16 alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: tim_ocref_clr2,3: tim_ocref_clr3,4: tim_ocref_clr4,5: tim_ocref_clr5,6: tim_ocref_clr6,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM16_DCR,TIM16 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM16_DMAR,TIM16/TIM17 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM17" base ad:0x42004800 group.word 0x0++0x1 line.word 0x0 "TIM17_CR1,TIM17 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub>=t less than..,1: t less than sub>DTS less than /sub>=2*t less..,2: t less than sub>DTS less than /sub>=4*t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: nly counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0x4++0x1 line.word 0x0 "TIM17_CR2,TIM17 control register 2" bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0" bitfld.word 0x0 8. "OIS1,Output Idle state 1 (tim_oc1 output)" "0: tim_oc1=0 after a dead-time when MOE=0,1: tim_oc1=1 after a dead-time when MOE=0" newline bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." newline bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." group.word 0xC++0x1 line.word 0x0 "TIM17_DIER,TIM17 DMA/interrupt enable register" bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" newline bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM17_SR,TIM17 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.." newline bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending" bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM17_EGR,TIM17 event generation register" bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.." bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.." newline bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM17_CCMR1_INPUT,TIM17 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM17_CCMR1_OUTPUT,TIM17 capture/compare mode register 1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: tim_oc1ref is not affected by the tim_ocref_clr..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM17_CCER,TIM17 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: tim_oc1n active high,1: tim_oc1n active low" bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM17_CNT,TIM17 counter" rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM17_PSC,TIM17 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM17_ARR,TIM17 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM17_RCR,TIM17 repetition counter register" hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter reload value" group.long 0x34++0x3 line.long 0x0 "TIM17_CCR1,TIM17 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "TIM17_BDTR,TIM17 break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0: tim_oc1 and tim_oc1n outputs are disabled or..,1: tim_oc1 and tim_oc1n outputs are enabled if.." newline bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" newline bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (tim_brk and tim_sys_brk event)..,?" bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.." newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.." bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "TIM17_DTR2,TIM17 timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" line.long 0x4 "TIM17_AF1,TIM17 alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input is active high,1: tim_brk_cmp4 input is active low" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input is active high,1: tim_brk_cmp3 input is active low" newline bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input is active high,1: tim_brk_cmp2 input is active low" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input is active high,1: tim_brk_cmp1 input is active low" newline bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input is active high,1: TIMx_BKIN input is active low" bitfld.long 0x4 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" newline bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" newline bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" newline bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x8 "TIM17_AF2,TIM17 alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: tim_ocref_clr2,3: tim_ocref_clr3,4: tim_ocref_clr4,5: tim_ocref_clr5,6: tim_ocref_clr6,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM17_DCR,TIM17 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM17_DMAR,TIM16/TIM17 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM17_S" base ad:0x52004800 group.word 0x0++0x1 line.word 0x0 "TIM17_CR1,TIM17 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t less than sub>DTS less than /sub>=t less than..,1: t less than sub>DTS less than /sub>=2*t less..,2: t less than sub>DTS less than /sub>=4*t less..,?" bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" newline bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: nly counter overflow/underflow generates an.." newline bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0x4++0x1 line.word 0x0 "TIM17_CR2,TIM17 control register 2" bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0" bitfld.word 0x0 8. "OIS1,Output Idle state 1 (tim_oc1 output)" "0: tim_oc1=0 after a dead-time when MOE=0,1: tim_oc1=1 after a dead-time when MOE=0" newline bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." newline bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." group.word 0xC++0x1 line.word 0x0 "TIM17_DIER,TIM17 DMA/interrupt enable register" bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" newline bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM17_SR,TIM17 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.." newline bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending" bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred" newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM17_EGR,TIM17 event generation register" bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.." bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.." newline bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM17_CCMR1_INPUT,TIM17 capture/compare mode register 1" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM17_CCMR1_OUTPUT,TIM17 capture/compare mode register 1" bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: tim_oc1ref is not affected by the tim_ocref_clr..,1: tim_oc1ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM17_CCER,TIM17 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: tim_oc1n active high,1: tim_oc1n active low" bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.." newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM17_CNT,TIM17 counter" rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM17_PSC,TIM17 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM17_ARR,TIM17 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM17_RCR,TIM17 repetition counter register" hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter reload value" group.long 0x34++0x3 line.long 0x0 "TIM17_CCR1,TIM17 capture/compare register 1" hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0x3 line.long 0x0 "TIM17_BDTR,TIM17 break and dead-time register" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed" newline hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0: tim_oc1 and tim_oc1n outputs are disabled or..,1: tim_oc1 and tim_oc1n outputs are enabled if.." newline bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high" newline bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (tim_brk and tim_sys_brk event)..,?" bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.." newline bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.." bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." newline hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x3 line.long 0x0 "TIM17_DTR2,TIM17 timer deadtime register 2" bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled" bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].." newline hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup" group.long 0x5C++0xB line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input" line.long 0x4 "TIM17_AF1,TIM17 alternate function register 1" bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input is active high,1: tim_brk_cmp4 input is active low" bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input is active high,1: tim_brk_cmp3 input is active low" newline bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input is active high,1: tim_brk_cmp2 input is active low" bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input is active high,1: tim_brk_cmp1 input is active low" newline bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input is active high,1: TIMx_BKIN input is active low" bitfld.long 0x4 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled" newline bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled" bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled" newline bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled" bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled" newline bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled" bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled" newline bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled" bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled" line.long 0x8 "TIM17_AF2,TIM17 alternate function register 2" bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: tim_ocref_clr2,3: tim_ocref_clr3,4: tim_ocref_clr4,5: tim_ocref_clr5,6: tim_ocref_clr6,7: tim_ocref_clr7" group.long 0x3DC++0x7 line.long 0x0 "TIM17_DCR,TIM17 DMA control register" hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" newline hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "TIM17_DMAR,TIM16/TIM17 DMA address for full transfer" hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses" tree.end tree "TIM18" base ad:0x42003C00 group.word 0x0++0x1 line.word 0x0 "TIM18_CR1,TIM18 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x3 line.long 0x0 "TIM18_CR2,TIM18 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal tim_cnt_en is..,2: Update - The update event is selected as a..,?,?,?,?,?" group.word 0xC++0x1 line.word 0x0 "TIM18_DIER,TIM18 DMA/Interrupt enable register" bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM18_SR,TIM18 status register" bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM18_EGR,TIM18 event generation register" bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.." group.long 0x24++0x3 line.long 0x0 "TIM18_CNT,TIM18 counter" rbitfld.long 0x0 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM18_PSC,TIM18 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM18_ARR,TIM18 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" tree.end tree "TIM18_S" base ad:0x52003C00 group.word 0x0++0x1 line.word 0x0 "TIM18_CR1,TIM18 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x3 line.long 0x0 "TIM18_CR2,TIM18 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal tim_cnt_en is..,2: Update - The update event is selected as a..,?,?,?,?,?" group.word 0xC++0x1 line.word 0x0 "TIM18_DIER,TIM18 DMA/Interrupt enable register" bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM18_SR,TIM18 status register" bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM18_EGR,TIM18 event generation register" bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.." group.long 0x24++0x3 line.long 0x0 "TIM18_CNT,TIM18 counter" rbitfld.long 0x0 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM18_PSC,TIM18 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM18_ARR,TIM18 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" tree.end sif (cpuis("STM32N647*")||cpuis("STM32N657*")) tree "TIM7_S" base ad:0x50001400 group.word 0x0++0x1 line.word 0x0 "TIM6_CR1,TIM6 control register 1" bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x3 line.long 0x0 "TIM6_CR2,TIM6 control register 2" bitfld.long 0x0 28. "ADSYNC,ADC synchronization" "0: The timer operates independently from the ADC,1: The timer operation is synchronized with the ADC.." bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal tim_cnt_en is..,2: Update - The update event is selected as a..,?,?,?,?,?" group.word 0xC++0x1 line.word 0x0 "TIM6_DIER,TIM6 DMA/Interrupt enable register" bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM6_SR,TIM6 status register" bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM6_EGR,TIM6 event generation register" bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.." group.long 0x24++0x3 line.long 0x0 "TIM6_CNT,TIM6 counter" rbitfld.long 0x0 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM6_PSC,TIM6 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.long 0x2C++0x3 line.long 0x0 "TIM6_ARR,TIM6 auto-reload register" hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value" tree.end endif tree.end tree "UCPD (USB Type-C/USB Power Delivery Interface)" base ad:0x0 tree "UCPD" base ad:0x4000FC00 group.long 0x0++0x7 line.long 0x0 "UCPD_CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPD peripheral enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "RXDMAEN,Reception DMA mode enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "TXDMAEN,Transmission DMA mode enable" "0: Disable,1: Enable" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,Receiver ordered set enable" newline bitfld.long 0x0 17.--19. "PSC_USBPDCLK,Pre-scaler division ratio for generating ucpd_clk" "0: 1 (bypass),1: 2,2: 4,3: 8,4: 16,?,?,?" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,Transition window duration" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,Division ratio for producing inter-frame gap timer clock" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,Division ratio for producing half-bit clock" line.long 0x4 "UCPD_CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,Wakeup from Stop mode enable" "0: Disable,1: Enable" bitfld.long 0x4 2. "FORCECLK,Force ClkReq clock request" "0: Do not force clock request,1: Force clock request" newline bitfld.long 0x4 1. "RXFILT2N3,BMC decoder Rx pre-filter sampling method" "0: 3 samples,1: 2 samples" bitfld.long 0x4 0. "RXFILTDIS,BMC decoder Rx pre-filter enable" "0: Enable,1: Disable" group.long 0xC++0x7 line.long 0x0 "UCPD_CR,UCPD control register" bitfld.long 0x0 21. "CC2TCDIS,CC2 Type-C detector disable" "0: Enable,1: Disable" bitfld.long 0x0 20. "CC1TCDIS,CC1 Type-C detector disable" "0: Enable,1: Disable" newline bitfld.long 0x0 18. "RDCH,Rdch condition drive" "0: No effect,1: Rdch condition drive" bitfld.long 0x0 17. "FRSTX,FRS Tx signaling enable." "0: No effect,1: Enable" newline bitfld.long 0x0 16. "FRSRXEN,FRS event detection enable" "?,1: Enable" bitfld.long 0x0 10.--11. "CCENABLE,CC line enable" "0: Disable both PHYs,1: Enable CC1 PHY,2: Enable CC2 PHY,3: Enable CC1 and CC2 PHY" newline bitfld.long 0x0 9. "ANAMODE,Analog PHY operating mode" "0: Source,1: Sink" bitfld.long 0x0 7.--8. "ANASUBMODE,Analog PHY sub-mode" "0,1,2,3" newline bitfld.long 0x0 6. "PHYCCSEL,CC1/CC2 line selector for USB Power Delivery signaling" "0: Use CC1 IO for Power Delivery communication,1: Use CC2 IO for Power Delivery communication" bitfld.long 0x0 5. "PHYRXEN,USB Power Delivery receiver enable" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "RXMODE,Receiver mode" "0: Normal receive mode,1: BIST receive mode (BIST test data mode)" bitfld.long 0x0 3. "TXHRST,Command to send a Tx Hard Reset" "0: No effect,1: Start Tx Hard Reset message" newline bitfld.long 0x0 2. "TXSEND,Command to send a Tx packet" "0: No effect,1: Start Tx packet transmission" bitfld.long 0x0 0.--1. "TXMODE,Type of Tx packet" "0: Transmission of Tx packet previously defined in..,1: Cable Reset sequence,2: BIST test sequence (BIST Carrier Mode 2),?" line.long 0x4 "UCPD_IMR,UCPD interrupt mask register" rbitfld.long 0x4 20. "FRSEVTIE,FRSEVT interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 15. "TYPECEVT2IE,TYPECEVT2 interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 14. "TYPECEVT1IE,TYPECEVT1 interrupt enable" "0,1" bitfld.long 0x4 12. "RXMSGENDIE,RXMSGEND interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 11. "RXOVRIE,RXOVR interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 10. "RXHRSTDETIE,RXHRSTDET interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 9. "RXORDDETIE,RXORDDET interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 8. "RXNEIE,RXNE interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 6. "TXUNDIE,TXUND interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 5. "HRSTSENTIE,HRSTSENT interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 4. "HRSTDISCIE,HRSTDISC interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 3. "TXMSGABTIE,TXMSGABT interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 2. "TXMSGSENTIE,TXMSGSENT interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 1. "TXMSGDISCIE,TXMSGDISC interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 0. "TXISIE,TXIS interrupt enable" "0: Disable,1: Enable" rgroup.long 0x14++0x3 line.long 0x0 "UCPD_SR,UCPD status register" bitfld.long 0x0 20. "FRSEVT,FRS detection event" "0: No new event,1: New FRS receive event occurred" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,CC2 line voltage level" "0: Lowest,1: Low,2: High,3: Highest" newline bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,The status bitfield indicates the voltage level on the CC1 line in its steady state." "0: Lowest,1: Low,2: High,3: Highest" bitfld.long 0x0 15. "TYPECEVT2,Type-C voltage level event on CC2 line" "0: No new event,1: A new Type-C event" newline bitfld.long 0x0 14. "TYPECEVT1,Type-C voltage level event on CC1 line" "0: No new event,1: A new Type-C event" bitfld.long 0x0 13. "RXERR,Receive message error" "0: No error detected,1: Error(s) detected" newline bitfld.long 0x0 12. "RXMSGEND,Rx message received" "0: No new Rx message received,1: A new Rx message received" bitfld.long 0x0 11. "RXOVR,Rx data overflow detection" "0: No overflow,1: Overflow" newline bitfld.long 0x0 10. "RXHRSTDET,Rx Hard Reset receipt detection" "0: Hard Reset not received,1: Hard Reset received" bitfld.long 0x0 9. "RXORDDET,Rx ordered set (4 K-codes) detection" "0: No ordered set detected,1: A new ordered set detected" newline bitfld.long 0x0 8. "RXNE,Receive data register not empty detection" "0: Rx data register empty,1: Rx data register not empty" bitfld.long 0x0 6. "TXUND,Tx data underrun detection" "0: No Tx data underrun detected,1: Tx data underrun detected" newline bitfld.long 0x0 5. "HRSTSENT,Hard Reset message sent" "0: No Hard Reset message sent,1: Hard Reset message sent" bitfld.long 0x0 4. "HRSTDISC,Hard Reset discarded" "0: No Hard Reset discarded,1: Hard Reset discarded" newline bitfld.long 0x0 3. "TXMSGABT,Transmit message abort" "0: No transmit message abort,1: Transmit message abort" bitfld.long 0x0 2. "TXMSGSENT,Message transmission completed" "0: No Tx message completed,1: Tx message completed" newline bitfld.long 0x0 1. "TXMSGDISC,Message transmission discarded" "0: No Tx message discarded,1: Tx message discarded" bitfld.long 0x0 0. "TXIS,Transmit interrupt status" "0: New Tx data write not required,1: New Tx data write required" wgroup.long 0x18++0x3 line.long 0x0 "UCPD_ICR,UCPD interrupt clear register" bitfld.long 0x0 20. "FRSEVTCF,FRS event flag (FRSEVT) clear" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,Type-C CC2 line event flag (TYPECEVT2) clear" "0,1" newline bitfld.long 0x0 14. "TYPECEVT1CF,Type-C CC1 event flag (TYPECEVT1) clear" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,Rx message received flag (RXMSGEND) clear" "0,1" newline bitfld.long 0x0 11. "RXOVRCF,Rx overflow flag (RXOVR) clear" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,Rx Hard Reset detect flag (RXHRSTDET) clear" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,Rx ordered set detect flag (RXORDDET) clear" "0,1" bitfld.long 0x0 6. "TXUNDCF,Tx underflow flag (TXUND) clear" "0,1" newline bitfld.long 0x0 5. "HRSTSENTCF,Hard reset send flag (HRSTSENT) clear" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,Hard reset discard flag (HRSTDISC) clear" "0,1" newline bitfld.long 0x0 3. "TXMSGABTCF,Tx message abort flag (TXMSGABT) clear" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,Tx message send flag (TXMSGSENT) clear" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,Tx message discard flag (TXMSGDISC) clear" "0,1" group.long 0x1C++0xB line.long 0x0 "UCPD_TX_ORDSETR,UCPD Tx ordered set type register" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,Ordered set to transmit" line.long 0x4 "UCPD_TX_PAYSZR,UCPD Tx payload size register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,Payload size yet to transmit" line.long 0x8 "UCPD_TXDR,UCPD Tx data register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,Data byte to transmit" rgroup.long 0x28++0xB line.long 0x0 "UCPD_RX_ORDSETR,UCPD Rx ordered set register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,The bitfield is for debug purposes only." "0: No K-code corrupted,1: First K-code corrupted,2: Second K-code corrupted,3: Third K-code corrupted,4: Fourth K-code corrupted,?,?,?" bitfld.long 0x0 3. "RXSOP3OF4,The bit indicates the number of correct K-codes. For debug purposes only." "0: 4 correct K-codes out of 4,1: 3 correct K-codes out of 4" newline bitfld.long 0x0 0.--2. "RXORDSET,Rx ordered set code detected" "0: SOP code detected in receiver,1: SOP' code detected in receiver,2: SOP'' code detected in receiver,3: SOP'_Debug detected in receiver,4: SOP''_Debug detected in receiver,5: Cable Reset detected in receiver,6: SOP extension#1 detected in receiver,7: SOP extension#2 detected in receiver" line.long 0x4 "UCPD_RX_PAYSZR,UCPD Rx payload size register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,Rx payload size received" line.long 0x8 "UCPD_RXDR,UCPD receive data register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,Data byte received" group.long 0x34++0x7 line.long 0x0 "UCPD_RX_ORDEXTR1,UCPD Rx ordered set extension register 1" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,Ordered set 1 received" line.long 0x4 "UCPD_RX_ORDEXTR2,UCPD Rx ordered set extension register 2" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,Ordered set 2 received" tree.end tree "UCPD_S" base ad:0x5000FC00 group.long 0x0++0x7 line.long 0x0 "UCPD_CFGR1,UCPD configuration register 1" bitfld.long 0x0 31. "UCPDEN,UCPD peripheral enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "RXDMAEN,Reception DMA mode enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "TXDMAEN,Transmission DMA mode enable" "0: Disable,1: Enable" hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,Receiver ordered set enable" newline bitfld.long 0x0 17.--19. "PSC_USBPDCLK,Pre-scaler division ratio for generating ucpd_clk" "0: 1 (bypass),1: 2,2: 4,3: 8,4: 16,?,?,?" hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,Transition window duration" newline hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,Division ratio for producing inter-frame gap timer clock" hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,Division ratio for producing half-bit clock" line.long 0x4 "UCPD_CFGR2,UCPD configuration register 2" bitfld.long 0x4 3. "WUPEN,Wakeup from Stop mode enable" "0: Disable,1: Enable" bitfld.long 0x4 2. "FORCECLK,Force ClkReq clock request" "0: Do not force clock request,1: Force clock request" newline bitfld.long 0x4 1. "RXFILT2N3,BMC decoder Rx pre-filter sampling method" "0: 3 samples,1: 2 samples" bitfld.long 0x4 0. "RXFILTDIS,BMC decoder Rx pre-filter enable" "0: Enable,1: Disable" group.long 0xC++0x7 line.long 0x0 "UCPD_CR,UCPD control register" bitfld.long 0x0 21. "CC2TCDIS,CC2 Type-C detector disable" "0: Enable,1: Disable" bitfld.long 0x0 20. "CC1TCDIS,CC1 Type-C detector disable" "0: Enable,1: Disable" newline bitfld.long 0x0 18. "RDCH,Rdch condition drive" "0: No effect,1: Rdch condition drive" bitfld.long 0x0 17. "FRSTX,FRS Tx signaling enable." "0: No effect,1: Enable" newline bitfld.long 0x0 16. "FRSRXEN,FRS event detection enable" "?,1: Enable" bitfld.long 0x0 10.--11. "CCENABLE,CC line enable" "0: Disable both PHYs,1: Enable CC1 PHY,2: Enable CC2 PHY,3: Enable CC1 and CC2 PHY" newline bitfld.long 0x0 9. "ANAMODE,Analog PHY operating mode" "0: Source,1: Sink" bitfld.long 0x0 7.--8. "ANASUBMODE,Analog PHY sub-mode" "0,1,2,3" newline bitfld.long 0x0 6. "PHYCCSEL,CC1/CC2 line selector for USB Power Delivery signaling" "0: Use CC1 IO for Power Delivery communication,1: Use CC2 IO for Power Delivery communication" bitfld.long 0x0 5. "PHYRXEN,USB Power Delivery receiver enable" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "RXMODE,Receiver mode" "0: Normal receive mode,1: BIST receive mode (BIST test data mode)" bitfld.long 0x0 3. "TXHRST,Command to send a Tx Hard Reset" "0: No effect,1: Start Tx Hard Reset message" newline bitfld.long 0x0 2. "TXSEND,Command to send a Tx packet" "0: No effect,1: Start Tx packet transmission" bitfld.long 0x0 0.--1. "TXMODE,Type of Tx packet" "0: Transmission of Tx packet previously defined in..,1: Cable Reset sequence,2: BIST test sequence (BIST Carrier Mode 2),?" line.long 0x4 "UCPD_IMR,UCPD interrupt mask register" rbitfld.long 0x4 20. "FRSEVTIE,FRSEVT interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 15. "TYPECEVT2IE,TYPECEVT2 interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 14. "TYPECEVT1IE,TYPECEVT1 interrupt enable" "0,1" bitfld.long 0x4 12. "RXMSGENDIE,RXMSGEND interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 11. "RXOVRIE,RXOVR interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 10. "RXHRSTDETIE,RXHRSTDET interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 9. "RXORDDETIE,RXORDDET interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 8. "RXNEIE,RXNE interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 6. "TXUNDIE,TXUND interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 5. "HRSTSENTIE,HRSTSENT interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 4. "HRSTDISCIE,HRSTDISC interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 3. "TXMSGABTIE,TXMSGABT interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 2. "TXMSGSENTIE,TXMSGSENT interrupt enable" "0: Disable,1: Enable" bitfld.long 0x4 1. "TXMSGDISCIE,TXMSGDISC interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x4 0. "TXISIE,TXIS interrupt enable" "0: Disable,1: Enable" rgroup.long 0x14++0x3 line.long 0x0 "UCPD_SR,UCPD status register" bitfld.long 0x0 20. "FRSEVT,FRS detection event" "0: No new event,1: New FRS receive event occurred" bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,CC2 line voltage level" "0: Lowest,1: Low,2: High,3: Highest" newline bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,The status bitfield indicates the voltage level on the CC1 line in its steady state." "0: Lowest,1: Low,2: High,3: Highest" bitfld.long 0x0 15. "TYPECEVT2,Type-C voltage level event on CC2 line" "0: No new event,1: A new Type-C event" newline bitfld.long 0x0 14. "TYPECEVT1,Type-C voltage level event on CC1 line" "0: No new event,1: A new Type-C event" bitfld.long 0x0 13. "RXERR,Receive message error" "0: No error detected,1: Error(s) detected" newline bitfld.long 0x0 12. "RXMSGEND,Rx message received" "0: No new Rx message received,1: A new Rx message received" bitfld.long 0x0 11. "RXOVR,Rx data overflow detection" "0: No overflow,1: Overflow" newline bitfld.long 0x0 10. "RXHRSTDET,Rx Hard Reset receipt detection" "0: Hard Reset not received,1: Hard Reset received" bitfld.long 0x0 9. "RXORDDET,Rx ordered set (4 K-codes) detection" "0: No ordered set detected,1: A new ordered set detected" newline bitfld.long 0x0 8. "RXNE,Receive data register not empty detection" "0: Rx data register empty,1: Rx data register not empty" bitfld.long 0x0 6. "TXUND,Tx data underrun detection" "0: No Tx data underrun detected,1: Tx data underrun detected" newline bitfld.long 0x0 5. "HRSTSENT,Hard Reset message sent" "0: No Hard Reset message sent,1: Hard Reset message sent" bitfld.long 0x0 4. "HRSTDISC,Hard Reset discarded" "0: No Hard Reset discarded,1: Hard Reset discarded" newline bitfld.long 0x0 3. "TXMSGABT,Transmit message abort" "0: No transmit message abort,1: Transmit message abort" bitfld.long 0x0 2. "TXMSGSENT,Message transmission completed" "0: No Tx message completed,1: Tx message completed" newline bitfld.long 0x0 1. "TXMSGDISC,Message transmission discarded" "0: No Tx message discarded,1: Tx message discarded" bitfld.long 0x0 0. "TXIS,Transmit interrupt status" "0: New Tx data write not required,1: New Tx data write required" wgroup.long 0x18++0x3 line.long 0x0 "UCPD_ICR,UCPD interrupt clear register" bitfld.long 0x0 20. "FRSEVTCF,FRS event flag (FRSEVT) clear" "0,1" bitfld.long 0x0 15. "TYPECEVT2CF,Type-C CC2 line event flag (TYPECEVT2) clear" "0,1" newline bitfld.long 0x0 14. "TYPECEVT1CF,Type-C CC1 event flag (TYPECEVT1) clear" "0,1" bitfld.long 0x0 12. "RXMSGENDCF,Rx message received flag (RXMSGEND) clear" "0,1" newline bitfld.long 0x0 11. "RXOVRCF,Rx overflow flag (RXOVR) clear" "0,1" bitfld.long 0x0 10. "RXHRSTDETCF,Rx Hard Reset detect flag (RXHRSTDET) clear" "0,1" newline bitfld.long 0x0 9. "RXORDDETCF,Rx ordered set detect flag (RXORDDET) clear" "0,1" bitfld.long 0x0 6. "TXUNDCF,Tx underflow flag (TXUND) clear" "0,1" newline bitfld.long 0x0 5. "HRSTSENTCF,Hard reset send flag (HRSTSENT) clear" "0,1" bitfld.long 0x0 4. "HRSTDISCCF,Hard reset discard flag (HRSTDISC) clear" "0,1" newline bitfld.long 0x0 3. "TXMSGABTCF,Tx message abort flag (TXMSGABT) clear" "0,1" bitfld.long 0x0 2. "TXMSGSENTCF,Tx message send flag (TXMSGSENT) clear" "0,1" newline bitfld.long 0x0 1. "TXMSGDISCCF,Tx message discard flag (TXMSGDISC) clear" "0,1" group.long 0x1C++0xB line.long 0x0 "UCPD_TX_ORDSETR,UCPD Tx ordered set type register" hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,Ordered set to transmit" line.long 0x4 "UCPD_TX_PAYSZR,UCPD Tx payload size register" hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,Payload size yet to transmit" line.long 0x8 "UCPD_TXDR,UCPD Tx data register" hexmask.long.byte 0x8 0.--7. 1. "TXDATA,Data byte to transmit" rgroup.long 0x28++0xB line.long 0x0 "UCPD_RX_ORDSETR,UCPD Rx ordered set register" bitfld.long 0x0 4.--6. "RXSOPKINVALID,The bitfield is for debug purposes only." "0: No K-code corrupted,1: First K-code corrupted,2: Second K-code corrupted,3: Third K-code corrupted,4: Fourth K-code corrupted,?,?,?" bitfld.long 0x0 3. "RXSOP3OF4,The bit indicates the number of correct K-codes. For debug purposes only." "0: 4 correct K-codes out of 4,1: 3 correct K-codes out of 4" newline bitfld.long 0x0 0.--2. "RXORDSET,Rx ordered set code detected" "0: SOP code detected in receiver,1: SOP' code detected in receiver,2: SOP'' code detected in receiver,3: SOP'_Debug detected in receiver,4: SOP''_Debug detected in receiver,5: Cable Reset detected in receiver,6: SOP extension#1 detected in receiver,7: SOP extension#2 detected in receiver" line.long 0x4 "UCPD_RX_PAYSZR,UCPD Rx payload size register" hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,Rx payload size received" line.long 0x8 "UCPD_RXDR,UCPD receive data register" hexmask.long.byte 0x8 0.--7. 1. "RXDATA,Data byte received" group.long 0x34++0x7 line.long 0x0 "UCPD_RX_ORDEXTR1,UCPD Rx ordered set extension register 1" hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,Ordered set 1 received" line.long 0x4 "UCPD_RX_ORDEXTR2,UCPD Rx ordered set extension register 2" hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,Ordered set 2 received" tree.end tree.end tree "USART (Universal Synchronous Asynchronous Receiver)" base ad:0x0 sif (cpuis("STM32N655*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "USART3" base ad:0x40004800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "USART3" base ad:0x40004800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "UART4" base ad:0x40004C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "UART4" base ad:0x40004C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "UART5" base ad:0x40005000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "UART5" base ad:0x40005000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "UART7" base ad:0x40007800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "UART7" base ad:0x40007800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "UART8" base ad:0x40007C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "UART8" base ad:0x40007C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "USART1" base ad:0x42001000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "USART1" base ad:0x42001000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "USART1" base ad:0x42001000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "USART6" base ad:0x42001400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "USART6" base ad:0x42001400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "UART9" base ad:0x42001800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "UART9" base ad:0x42001800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "USART10" base ad:0x42001C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "USART10" base ad:0x42001C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "USART2_S" base ad:0x50004400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "USART2_S" base ad:0x50004400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "USART3_S" base ad:0x50004800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "USART3_S" base ad:0x50004800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "UART4_S" base ad:0x50004C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "UART4_S" base ad:0x50004C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "UART5_S" base ad:0x50005000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "UART5_S" base ad:0x50005000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "UART7_S" base ad:0x50007800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "UART7_S" base ad:0x50007800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "UART8_S" base ad:0x50007C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "UART8_S" base ad:0x50007C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "USART1_S" base ad:0x52001000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "USART2_S" base ad:0x50004400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "USART3" base ad:0x40004800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "USART3_S" base ad:0x50004800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "UART4" base ad:0x40004C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "UART4_S" base ad:0x50004C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "UART5" base ad:0x40005000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "UART5_S" base ad:0x50005000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "USART6" base ad:0x42001400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "USART1_S" base ad:0x52001000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "USART1_S" base ad:0x52001000 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "USART6_S" base ad:0x52001400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "UART7" base ad:0x40007800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "UART7_S" base ad:0x50007800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "UART8" base ad:0x40007C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "UART8_S" base ad:0x50007C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "UART9" base ad:0x42001800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "USART6_S" base ad:0x52001400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "USART6_S" base ad:0x52001400 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "UART9_S" base ad:0x52001800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "USART10" base ad:0x42001C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "UART9_S" base ad:0x52001800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "UART9_S" base ad:0x52001800 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N645*")||cpuis("STM32N647*")) tree "USART10_S" base ad:0x52001C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((V less than.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((V less than.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline sif (cpuis("STM32N645*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,?,?,?,?" endif sif (cpuis("STM32N647*")) bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" newline endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." newline bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." newline bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." newline bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." newline bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" newline bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" newline bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N655*")) tree "USART10_S" base ad:0x52001C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32N657*")) tree "USART10_S" base ad:0x52001C00 group.long 0x0++0x3 line.long 0x0 "USART_CR1_FIFO_ENABLED,USART control register 1 [alternate]" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.." bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.." newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" group.long 0x0++0x17 line.long 0x0 "USART_CR1_FIFO_DISABLED,USART control register 1 [alternate]" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled." bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.." bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.." newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.." newline bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.." bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark" bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled" newline bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.." newline bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.." bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.." newline bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.." bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.." newline bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled" bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.." newline bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode." bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled" line.long 0x4 "USART_CR2,USART control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled." newline bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled." newline bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.." bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.." newline bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted. ((Vless.." bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted. ((Vless.." newline bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.." bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled" newline bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits" bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled" newline bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.." bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.." newline bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.." bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.." newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)" newline bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.." bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled." line.long 0x8 "USART_CR3,USART control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.." newline bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.." newline bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.." bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.." newline bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?" newline bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,?,?,?,?" bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low." newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.." bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.." newline bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.." bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method" newline bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.." bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.." newline bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.." bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled" newline bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected" newline bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode" bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled" newline bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.." line.long 0xC "USART_BRR,USART baud rate register" hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate" line.long 0x10 "USART_GTPR,USART guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "USART_RTOR,USART receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "USART_RQR,USART request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" newline bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" newline bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_ENABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold." bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold." newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full." newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" rgroup.long 0x1C++0x3 line.long 0x0 "USART_ISR_FIFO_DISABLED,USART interrupt and status register [alternate]" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.." bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1" newline bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1" bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1" newline bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode" bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted" newline bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected" bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going" newline bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1" bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error" bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached" newline bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception" bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset" newline bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line" bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected" newline bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full" bitfld.long 0x0 6. "TC,Transmission complete" "0,1" newline bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read." bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected" newline bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected" bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected" newline bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected" bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error" wgroup.long 0x20++0x3 line.long 0x0 "USART_ICR,USART interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" newline bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" newline bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" newline bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" newline bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" newline bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" newline bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "USART_RDR,USART receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "USART_TDR,USART transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "USART_PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif tree.end tree "VENC (Video Encoder)" base ad:0x0 tree "VENC" base ad:0x48005000 group.long 0x0++0xF line.long 0x0 "VENC_SWREG0,VENC ID register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Interrupt register (all format mode)" line.long 0x4 "VENC_SWREG1,VENC interrupt register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,Interrupt register (all format mode)" line.long 0x8 "VENC_SWREG2,VENC bus interface configuration register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,Bus interface configuration register (all format mode)" line.long 0xC "VENC_SWREG3,VENC device configuration register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,Device configuration register (all format mode)" group.long 0x14++0xE7 line.long 0x0 "VENC_SWREG5,VENC base address for output stream data register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Base address for output stream data (all format mode)" line.long 0x4 "VENC_SWREG6,VENC base address for output control data register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,Base address for output control data (all format mode)" line.long 0x8 "VENC_SWREG7,VENC base address for reference luma register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,Base address for reference luma (all format mode)" line.long 0xC "VENC_SWREG8,VENC base address for reference chroma register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,Base address for reference chroma (all format mode)" line.long 0x10 "VENC_SWREG9,VENC base address for reconstructed luma register" hexmask.long 0x10 0.--31. 1. "SWREG_FIELD,Base address for reconstructed luma (all format mode)" line.long 0x14 "VENC_SWREG10,VENC base address for reconstructed chroma register" hexmask.long 0x14 0.--31. 1. "SWREG_FIELD,Base address for reconstructed chroma (all format mode)" line.long 0x18 "VENC_SWREG11,VENC base address for input picture luma register" hexmask.long 0x18 0.--31. 1. "SWREG_FIELD,Base address for input picture luma (all format mode)" line.long 0x1C "VENC_SWREG12,VENC base address for input picture cb register" hexmask.long 0x1C 0.--31. 1. "SWREG_FIELD,Base address for input picture cb (all format mode)" line.long 0x20 "VENC_SWREG13,VENC base address for input picture cr register" hexmask.long 0x20 0.--31. 1. "SWREG_FIELD,Base address for input picture cr (all format mode)" line.long 0x24 "VENC_SWREG14,VENC encoder control register 0" hexmask.long 0x24 0.--31. 1. "SWREG_FIELD,Encoder control register 0 (such as picture information or encoding mode) (all format mode)" line.long 0x28 "VENC_SWREG15,VENC encoder control register 1" hexmask.long 0x28 0.--31. 1. "SWREG_FIELD,Encoder control register 1 (such as preprocessing control crop rotate input format) (all format mode)" line.long 0x2C "VENC_SWREG16,VENC encoder control register 2" hexmask.long 0x2C 0.--31. 1. "SWREG_FIELD,Base address for second reference luma (H264 control) (all format mode)" line.long 0x30 "VENC_SWREG17,VENC encoder control register 3" hexmask.long 0x30 0.--31. 1. "SWREG_FIELD,Base address for second reference chroma (H264 control) (all format mode)" line.long 0x34 "VENC_SWREG18,VENC encoder control register 4" hexmask.long 0x34 0.--31. 1. "SWREG_FIELD,Encoder control register 4 (deblock filter mode H264 control) (all format mode)" line.long 0x38 "VENC_SWREG19,VENC encoder control register 5" hexmask.long 0x38 0.--31. 1. "SWREG_FIELD,Encoder control register 5 (input format motion vector etc) (all format mode)" line.long 0x3C "VENC_SWREG20,VENC encoder control register 6" hexmask.long 0x3C 0.--31. 1. "SWREG_FIELD,Control of data JPEG (all format mode)" line.long 0x40 "VENC_SWREG21,VENC encoder control register 7" hexmask.long 0x40 0.--31. 1. "SWREG_FIELD,Control of H264 (all format mode)" line.long 0x44 "VENC_SWREG22,VENC stream header remainder MSB bits register" hexmask.long 0x44 0.--31. 1. "SWREG_FIELD,Stream header remainder bits MSB (MSB aligned) (all format mode)" line.long 0x48 "VENC_SWREG23,VENC stream header remainder LSB bits register" hexmask.long 0x48 0.--31. 1. "SWREG_FIELD,Stream header remainder bits LSB (MSB aligned) (all format mode)" line.long 0x4C "VENC_SWREG24,VENC stream buffer limit/output stream size register" hexmask.long 0x4C 0.--31. 1. "SWREG_FIELD,Stream buffer limit (64-bit addresses)/output stream size (bits) (all format mode)" line.long 0x50 "VENC_SWREG25,VENC encoder control register 8" hexmask.long 0x50 0.--31. 1. "SWREG_FIELD,Control of MAD control and QP sum output (all format mode)" line.long 0x54 "VENC_SWREG26,VENC intra-slice bitmap register" hexmask.long 0x54 0.--31. 1. "SWREG_FIELD,intra-slice bitmap for probability updates (all format mode)" line.long 0x58 "VENC_SWREG27,VENC encoder control register 9" hexmask.long 0x58 0.--31. 1. "SWREG_FIELD,Control of H264 QP (all format mode)" line.long 0x5C "VENC_SWREG28,VENC encoder control register 10" hexmask.long 0x5C 0.--31. 1. "SWREG_FIELD,H264 checkpoint 1-2 (all format mode)" line.long 0x60 "VENC_SWREG29,VENC encoder control register 11" hexmask.long 0x60 0.--31. 1. "SWREG_FIELD,H.264 Checkpoint 3 -4 (all format mode)" line.long 0x64 "VENC_SWREG30,VENC encoder control register 12" hexmask.long 0x64 0.--31. 1. "SWREG_FIELD,H.264 checkpoint 5 -6 (all format mode)" line.long 0x68 "VENC_SWREG31,VENC encoder control register 13" hexmask.long 0x68 0.--31. 1. "SWREG_FIELD,H.264 checkpoint 7 -8 (all format mode)" line.long 0x6C "VENC_SWREG32,VENC encoder control register 14" hexmask.long 0x6C 0.--31. 1. "SWREG_FIELD,H.264 Checkpoint 8 -10 / Encoder control register 14 (all format mode)" line.long 0x70 "VENC_SWREG33,VENC encoder control register 15" hexmask.long 0x70 0.--31. 1. "SWREG_FIELD,H.264 Checkpoint word error 1-2 (all format mode)" line.long 0x74 "VENC_SWREG34,VENC encoder control register 16" hexmask.long 0x74 0.--31. 1. "SWREG_FIELD,H.264 checkpoint word error 3-4 and the second reference frame control (all format mode)" line.long 0x78 "VENC_SWREG35,VENC H.264 checkpoint word error 5-6/encoder control register 17" hexmask.long 0x78 0.--31. 1. "SWREG_FIELD,H.264 Checkpoint word error 5-6 / Encoder control register 17 (all format mode)" line.long 0x7C "VENC_SWREG36,VENC H.264 checkpoint delta QP 1-8/encoder control register 18" hexmask.long 0x7C 0.--31. 1. "SWREG_FIELD,H.264 Checkpoint delta QP 1-8 / Encoder control register 18 (all format mode)" line.long 0x80 "VENC_SWREG37,VENC encoder control register 19. stream start offset" hexmask.long 0x80 0.--31. 1. "SWREG_FIELD,Encoder control register 19 (all format mode)" line.long 0x84 "VENC_SWREG38,VENC macroblock count output register" hexmask.long 0x84 0.--31. 1. "SWREG_FIELD,Macroblock count output (all format mode)" line.long 0x88 "VENC_SWREG39,VENC base address for next pic luminance register" hexmask.long 0x88 0.--31. 1. "SWREG_FIELD,Base address for next pic luminance (all format mode)" line.long 0x8C "VENC_SWREG40,VENC stabilization mode control register" hexmask.long 0x8C 0.--31. 1. "SWREG_FIELD,Stabilization mode control (all format mode)" line.long 0x90 "VENC_SWREG41,VENC stabilization motion sum div8 output register" hexmask.long 0x90 0.--31. 1. "SWREG_FIELD,Stabilization motion sum div8 output (all format mode)" line.long 0x94 "VENC_SWREG42,VENC stabilization GMV output. matrix 1. up-left position output register" hexmask.long 0x94 0.--31. 1. "SWREG_FIELD,Stabilization GMV output matrix 1 (up-left position) output (all format mode)" line.long 0x98 "VENC_SWREG43,VENC stabilization GMV output. matrix 2. up position output register" hexmask.long 0x98 0.--31. 1. "SWREG_FIELD,Stabilization GMV output matrix 2 (up position) output (all format mode)" line.long 0x9C "VENC_SWREG44,VENC stabilization matrix 3. up-right position output register" hexmask.long 0x9C 0.--31. 1. "SWREG_FIELD,Stabilization matrix 3 (up-right position) output (all format mode)" line.long 0xA0 "VENC_SWREG45,VENC stabilization matrix 4. left position output register" hexmask.long 0xA0 0.--31. 1. "SWREG_FIELD,Stabilization matrix 4 (left position) output (all format mode)" line.long 0xA4 "VENC_SWREG46,VENC stabilization matrix 5. GMV position output register" hexmask.long 0xA4 0.--31. 1. "SWREG_FIELD,Stabilization matrix 5 (GMV position) output (all format mode)" line.long 0xA8 "VENC_SWREG47,VENC stabilization matrix 6. right position output register" hexmask.long 0xA8 0.--31. 1. "SWREG_FIELD,Stabilization matrix 6 (right position) output (all format mode)" line.long 0xAC "VENC_SWREG48,VENC stabilization matrix 7. down-left position output register" hexmask.long 0xAC 0.--31. 1. "SWREG_FIELD,Stabilization matrix 7 (down-left position) output (all format mode)" line.long 0xB0 "VENC_SWREG49,VENC stabilization matrix 8. down position output register" hexmask.long 0xB0 0.--31. 1. "SWREG_FIELD,Stabilization matrix 8 (down position) output (all format mode)" line.long 0xB4 "VENC_SWREG50,VENC stabilization matrix 9. down-right position output register" hexmask.long 0xB4 0.--31. 1. "SWREG_FIELD,Stabilization matrix 9 (down-right position) output (all format mode)" line.long 0xB8 "VENC_SWREG51,VENC base address for cabac context tables H264 register" hexmask.long 0xB8 0.--31. 1. "SWREG_FIELD,Base address for cabac context tables (H264) or probability tables (all format mode)" line.long 0xBC "VENC_SWREG52,VENC base address for MV output writing register" hexmask.long 0xBC 0.--31. 1. "SWREG_FIELD,Base address for MV output writing (all format mode)" line.long 0xC0 "VENC_SWREG53,VENC RGB to YUV conversion coefficient A - B register" hexmask.long 0xC0 0.--31. 1. "SWREG_FIELD,RGB to YUV conversion coefficient A - B (all format mode)" line.long 0xC4 "VENC_SWREG54,VENC RGB to YUV conversion coefficient C - E register" hexmask.long 0xC4 0.--31. 1. "SWREG_FIELD,RGB to YUV conversion coefficient C - E (all format mode)" line.long 0xC8 "VENC_SWREG55,VENC RGB to YUV conversion coefficient F. RGB mask MSB bit position register" hexmask.long 0xC8 0.--31. 1. "SWREG_FIELD,RGB to YUV conversion coefficient F RGB mask MSB bit position (all format mode)" line.long 0xCC "VENC_SWREG56,VENC intra area register" hexmask.long 0xCC 0.--31. 1. "SWREG_FIELD,intra area (all format mode)" line.long 0xD0 "VENC_SWREG57,VENC CIR intra mb position register" hexmask.long 0xD0 0.--31. 1. "SWREG_FIELD,CIR intra mb position (all format mode)" line.long 0xD4 "VENC_SWREG58,VENC intra slice bitmap for slices 0..31/base address for 1st DCT partition register" hexmask.long 0xD4 0.--31. 1. "SWREG_FIELD,intra slice bitmap for slices 0..31 / Base address for 1st DCT partition (all format mode)" line.long 0xD8 "VENC_SWREG59,VENC intra slice bitmap for slices 32..63/base address for 2nd DCT partition register" hexmask.long 0xD8 0.--31. 1. "SWREG_FIELD,intra slice bitmap for slices 32..63 / Base address for 2nd DCT partition (all format mode)" line.long 0xDC "VENC_SWREG60,VENC 1st ROI area register" hexmask.long 0xDC 0.--31. 1. "SWREG_FIELD,1st ROI area (all format mode)" line.long 0xE0 "VENC_SWREG61,VENC 2nd ROI area register" hexmask.long 0xE0 0.--31. 1. "SWREG_FIELD,2nd ROI area (all format mode)" line.long 0xE4 "VENC_SWREG62,VENC ROI area delta QP. MV register" hexmask.long 0xE4 0.--31. 1. "SWREG_FIELD,ROI area delta QP MV (all format mode)" rgroup.long 0xFC++0x3 line.long 0x0 "VENC_SWREG63,VENC synthesis configuration register encoder 0 register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Synthesis configuration register encoder 0 (read only) (all format mode)" group.long 0x100++0x7F line.long 0x0 "VENC_SWREG64,VENC JPEG luma quantization 1/intra 16x16 mode 0-1 penalty register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 1 / intra 16x16 mode 0-1 penalty (all format mode)" line.long 0x4 "VENC_SWREG65,VENC JPEG luma quantization 2/intra 16x16 mode 2-3 penalty register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 2 / intra 16x16 mode 2-3 penalty (all format mode)" line.long 0x8 "VENC_SWREG66,VENC JPEG luma quantization 3/intra 4x4 mode 0-1 penalty register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 3 / intra 4x4 mode 0-1 penalty (all format mode)" line.long 0xC "VENC_SWREG67,VENC JPEG luma quantization 4/intra 4x4 mode 2-3 penalty register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 4 / intra 4x4 mode 2-3 penalty (all format mode)" line.long 0x10 "VENC_SWREG68,VENC JPEG luma quantization 5/intra 4x4 mode 4-5 penalty register" hexmask.long 0x10 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 5 / intra 4x4 mode 4-5 penalty (all format mode)" line.long 0x14 "VENC_SWREG69,VENC JPEG luma quantization 6/intra 4x4 mode 6-7 penalty register" hexmask.long 0x14 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 6 / intra 4x4 mode 6-7 penalty (all format mode)" line.long 0x18 "VENC_SWREG70,VENC JPEG luma quantization 7/intra 4x4 mode 8-9 penalty register" hexmask.long 0x18 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 7 / intra 4x4 mode 8-9 penalty (all format mode)" line.long 0x1C "VENC_SWREG71,VENC JPEG luma quantization 8/base address for segmentation map register" hexmask.long 0x1C 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 8 / Base address for segmentation map (all format mode)" line.long 0x20 "VENC_SWREG72,VENC JPEG luma quantization 9/segment1 parameter register" hexmask.long 0x20 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 9 / segment1 parameter (all format mode)" line.long 0x24 "VENC_SWREG73,VENC JPEG luma quantization 10/segment1 parameter register" hexmask.long 0x24 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 10 / segment1 parameter (all format mode)" line.long 0x28 "VENC_SWREG74,VENC JPEG luma quantization 11/segment1 parameter register" hexmask.long 0x28 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 11 / segment1 parameter (all format mode)" line.long 0x2C "VENC_SWREG75,VENC JPEG luma quantization 12/segment1 parameter register" hexmask.long 0x2C 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 12 / segment1 parameter (all format mode)" line.long 0x30 "VENC_SWREG76,VENC JPEG luma quantization 13/segment1 parameter register" hexmask.long 0x30 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 13 / segment1 parameter (all format mode)" line.long 0x34 "VENC_SWREG77,VENC JPEG luma quantization 14/segment1 parameter register" hexmask.long 0x34 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 14 / segment1 parameter (all format mode)" line.long 0x38 "VENC_SWREG78,VENC JPEG luma quantization 15/segment1 parameter register" hexmask.long 0x38 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 15 / segment1 parameter (all format mode)" line.long 0x3C "VENC_SWREG79,VENC JPEG luma quantization 16/segment2 parameter register" hexmask.long 0x3C 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 16 / segment2 parameter (all format mode)" line.long 0x40 "VENC_SWREG80,VENC JPEG chroma quantization 1/segment2 parameter register" hexmask.long 0x40 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 1 / segment2 parameter (all format mode)" line.long 0x44 "VENC_SWREG81,VENC JPEG chroma quantization 2/segment2 parameter register" hexmask.long 0x44 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 2 / segment2 parameter (all format mode)" line.long 0x48 "VENC_SWREG82,VENC JPEG chroma quantization 3/segment2 parameter register" hexmask.long 0x48 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 3 / segment2 parameter (all format mode)" line.long 0x4C "VENC_SWREG83,VENC JPEG chroma quantization 4/segment2 parameter register" hexmask.long 0x4C 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 4 / segment2 parameter (all format mode)" line.long 0x50 "VENC_SWREG84,VENC JPEG chroma quantization 5/segment2 parameter register" hexmask.long 0x50 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 5 / segment2 parameter (all format mode)" line.long 0x54 "VENC_SWREG85,VENC JPEG chroma quantization 6/segment2 parameter register" hexmask.long 0x54 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 6 / segment2 parameter (all format mode)" line.long 0x58 "VENC_SWREG86,VENC JPEG chroma quantization 7/segment2 parameter register" hexmask.long 0x58 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 7 / segment2 parameter (all format mode)" line.long 0x5C "VENC_SWREG87,VENC JPEG chroma quantization 8/segment2 parameter register" hexmask.long 0x5C 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 8 / segment2 parameter (all format mode)" line.long 0x60 "VENC_SWREG88,VENC JPEG chroma quantization 9/segment3 parameter register" hexmask.long 0x60 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 9 / segment3 parameter (all format mode)" line.long 0x64 "VENC_SWREG89,VENC JPEG chroma quantization 10/segment3 parameter register" hexmask.long 0x64 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 10 / segment3 parameter (all format mode)" line.long 0x68 "VENC_SWREG90,VENC JPEG chroma quantization 11/segment3 parameter register" hexmask.long 0x68 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 11 / segment3 parameter (all format mode)" line.long 0x6C "VENC_SWREG91,VENC JPEG chroma quantization 12/segment3 parameter register" hexmask.long 0x6C 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 12 / segment3 parameter (all format mode)" line.long 0x70 "VENC_SWREG92,VENC JPEG chroma quantization 13/segment3 parameter register" hexmask.long 0x70 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 13 / segment3 parameter (all format mode)" line.long 0x74 "VENC_SWREG93,VENC JPEG chroma quantization 14/segment3 parameter register" hexmask.long 0x74 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 14 / segment3 parameter (all format mode)" line.long 0x78 "VENC_SWREG94,VENC JPEG chroma quantization 15/segment3 parameter register" hexmask.long 0x78 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 15 / segment3 parameter (all format mode)" line.long 0x7C "VENC_SWREG95,VENC JPEG chroma quantization 16/segment3 parameter register" hexmask.long 0x7C 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 16 / segment3 parameter (all format mode)" wgroup.long 0x180++0xFF line.long 0x0 "VENC_SWREG96,VENC DMV 4p/1p penalty values 0-3 register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values 0-3 (all format mode)" line.long 0x4 "VENC_SWREG97,VENC DMV 4p/1p penalty values 4-7 register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values 4-7 (all format mode)" line.long 0x8 "VENC_SWREG98,VENC DMV 4p/1p penalty values register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0xC "VENC_SWREG99,VENC DMV 4p/1p penalty values register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x10 "VENC_SWREG100,VENC DMV 4p/1p penalty values register" hexmask.long 0x10 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x14 "VENC_SWREG101,VENC DMV 4p/1p penalty values register" hexmask.long 0x14 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x18 "VENC_SWREG102,VENC DMV 4p/1p penalty values register" hexmask.long 0x18 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x1C "VENC_SWREG103,VENC DMV 4p/1p penalty values register" hexmask.long 0x1C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x20 "VENC_SWREG104,VENC DMV 4p/1p penalty values register" hexmask.long 0x20 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x24 "VENC_SWREG105,VENC DMV 4p/1p penalty values register" hexmask.long 0x24 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x28 "VENC_SWREG106,VENC DMV 4p/1p penalty values register" hexmask.long 0x28 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x2C "VENC_SWREG107,VENC DMV 4p/1p penalty values register" hexmask.long 0x2C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x30 "VENC_SWREG108,VENC DMV 4p/1p penalty values register" hexmask.long 0x30 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x34 "VENC_SWREG109,VENC DMV 4p/1p penalty values register" hexmask.long 0x34 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x38 "VENC_SWREG110,VENC DMV 4p/1p penalty values register" hexmask.long 0x38 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x3C "VENC_SWREG111,VENC DMV 4p/1p penalty values register" hexmask.long 0x3C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x40 "VENC_SWREG112,VENC DMV 4p/1p penalty values register" hexmask.long 0x40 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x44 "VENC_SWREG113,VENC DMV 4p/1p penalty values register" hexmask.long 0x44 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x48 "VENC_SWREG114,VENC DMV 4p/1p penalty values register" hexmask.long 0x48 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x4C "VENC_SWREG115,VENC DMV 4p/1p penalty values register" hexmask.long 0x4C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x50 "VENC_SWREG116,VENC DMV 4p/1p penalty values register" hexmask.long 0x50 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x54 "VENC_SWREG117,VENC DMV 4p/1p penalty values register" hexmask.long 0x54 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x58 "VENC_SWREG118,VENC DMV 4p/1p penalty values register" hexmask.long 0x58 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x5C "VENC_SWREG119,VENC DMV 4p/1p penalty values register" hexmask.long 0x5C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x60 "VENC_SWREG120,VENC DMV 4p/1p penalty values register" hexmask.long 0x60 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x64 "VENC_SWREG121,VENC DMV 4p/1p penalty values register" hexmask.long 0x64 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x68 "VENC_SWREG122,VENC DMV 4p/1p penalty values register" hexmask.long 0x68 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x6C "VENC_SWREG123,VENC DMV 4p/1p penalty values register" hexmask.long 0x6C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x70 "VENC_SWREG124,VENC DMV 4p/1p penalty values register" hexmask.long 0x70 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x74 "VENC_SWREG125,VENC DMV 4p/1p penalty values register" hexmask.long 0x74 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x78 "VENC_SWREG126,VENC DMV 4p/1p penalty values register" hexmask.long 0x78 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x7C "VENC_SWREG127,VENC DMV 4p/1p penalty values 124-127 register" hexmask.long 0x7C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values 124-127 (all format mode)" line.long 0x80 "VENC_SWREG128,VENC DMV qpel penalty values 0-3 register" hexmask.long 0x80 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values 0-3 (all format mode)" line.long 0x84 "VENC_SWREG129,VENC DMV qpel penalty values 4-7 register" hexmask.long 0x84 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values 4-7 (all format mode)" line.long 0x88 "VENC_SWREG130,VENC DMV qpel penalty values register" hexmask.long 0x88 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0x8C "VENC_SWREG131,VENC DMV qpel penalty values register" hexmask.long 0x8C 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0x90 "VENC_SWREG132,VENC DMV qpel penalty values register" hexmask.long 0x90 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0x94 "VENC_SWREG133,VENC DMV qpel penalty values register" hexmask.long 0x94 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0x98 "VENC_SWREG134,VENC DMV qpel penalty values register" hexmask.long 0x98 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0x9C "VENC_SWREG135,VENC DMV qpel penalty values register" hexmask.long 0x9C 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xA0 "VENC_SWREG136,VENC DMV qpel penalty values register" hexmask.long 0xA0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xA4 "VENC_SWREG137,VENC DMV qpel penalty values register" hexmask.long 0xA4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xA8 "VENC_SWREG138,VENC DMV qpel penalty values register" hexmask.long 0xA8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xAC "VENC_SWREG139,VENC DMV qpel penalty values register" hexmask.long 0xAC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xB0 "VENC_SWREG140,VENC DMV qpel penalty values register" hexmask.long 0xB0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xB4 "VENC_SWREG141,VENC DMV qpel penalty values register" hexmask.long 0xB4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xB8 "VENC_SWREG142,VENC DMV qpel penalty values register" hexmask.long 0xB8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xBC "VENC_SWREG143,VENC DMV qpel penalty values register" hexmask.long 0xBC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xC0 "VENC_SWREG144,VENC DMV qpel penalty values register" hexmask.long 0xC0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xC4 "VENC_SWREG145,VENC DMV qpel penalty values register" hexmask.long 0xC4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xC8 "VENC_SWREG146,VENC DMV qpel penalty values register" hexmask.long 0xC8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xCC "VENC_SWREG147,VENC DMV qpel penalty values register" hexmask.long 0xCC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xD0 "VENC_SWREG148,VENC DMV qpel penalty values register" hexmask.long 0xD0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xD4 "VENC_SWREG149,VENC DMV qpel penalty values register" hexmask.long 0xD4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xD8 "VENC_SWREG150,VENC DMV qpel penalty values register" hexmask.long 0xD8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xDC "VENC_SWREG151,VENC DMV qpel penalty values register" hexmask.long 0xDC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xE0 "VENC_SWREG152,VENC DMV qpel penalty values register" hexmask.long 0xE0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xE4 "VENC_SWREG153,VENC DMV qpel penalty values register" hexmask.long 0xE4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xE8 "VENC_SWREG154,VENC DMV qpel penalty values register" hexmask.long 0xE8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xEC "VENC_SWREG155,VENC DMV qpel penalty values register" hexmask.long 0xEC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xF0 "VENC_SWREG156,VENC DMV qpel penalty values register" hexmask.long 0xF0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xF4 "VENC_SWREG157,VENC DMV qpel penalty values register" hexmask.long 0xF4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xF8 "VENC_SWREG158,VENC DMV qpel penalty values register" hexmask.long 0xF8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xFC "VENC_SWREG159,VENC DMV qpel penalty values 124-127 register" hexmask.long 0xFC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values 124-127 (all format mode)" group.long 0x39C++0xB line.long 0x0 "VENC_SWREG231,VENC base address for output of down-scaled encoder image in YUYV 4:2:2 format register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Base address for output of down-scaled encoder image in YUYV 4:2:2 format (all format mode)" line.long 0x4 "VENC_SWREG232,VENC scaling control register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,Scaling control (all format mode)" line.long 0x8 "VENC_SWREG233,VENC scaling control register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,Scaling control (all format mode)" group.long 0x3B0++0xB line.long 0x0 "VENC_SWREG236,VENC squared error output calculated for 13x13 pixels per macroblock register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Squared error output calculated for 13x13 pixels per macroblock (all format mode)" line.long 0x4 "VENC_SWREG237,VENC MAD 2 control and output register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,MAD 2 control and output (all format mode)" line.long 0x8 "VENC_SWREG238,VENC MAD 3 control and output register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,MAD 3 control and output (all format mode)" group.long 0x400++0x8F line.long 0x0 "VENC_SWREG256,VENC segment 1: intra 16x16 mode 0-2 penalty register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,segment 1: intra 16x16 mode 0-2 penalty (all format mode)" line.long 0x4 "VENC_SWREG257,VENC segment 1: intra 16x16 mode 3. intra 4x4 0-1 penalty register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,segment 1: intra 16x16 mode 3 and intra 4x4 0-1 penalty (all format mode)" line.long 0x8 "VENC_SWREG258,VENC segment 1: intra 4x4 mode 2-4 penalty register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,segment 1: intra 4x4 mode 2-4 penalty (all format mode)" line.long 0xC "VENC_SWREG259,VENC segment 1: intra 4x4 mode 5-7 penalty register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,segment 1: intra 4x4 mode 5-7 penalty (all format mode)" line.long 0x10 "VENC_SWREG260,VENC segment 1: intra 4x4 mode 8-9 penalty. previous mode favor for H.264 register" hexmask.long 0x10 0.--31. 1. "SWREG_FIELD,segment 1: intra 4x4 mode 8-9 penalty previous mode favor for H.264 (all format mode)" line.long 0x14 "VENC_SWREG261,VENC segment 1: bit cost of inter type. intra 16x16 mode favor register" hexmask.long 0x14 0.--31. 1. "SWREG_FIELD,segment 1: Bit cost of inter type intra 16x16 mode favor (all format mode)" line.long 0x18 "VENC_SWREG262,VENC segment 1: inter MB mode favor. skip mode penalty. penalty value for 2nd reference frame register" hexmask.long 0x18 0.--31. 1. "SWREG_FIELD,segment 1: inter MB mode favor skip mode penalty penalty value for second reference frame (all format mode)" line.long 0x1C "VENC_SWREG263,VENC segment 1: penalty value register" hexmask.long 0x1C 0.--31. 1. "SWREG_FIELD,segment 1: penalty value (all format mode)" line.long 0x20 "VENC_SWREG264,VENC segment 1: penalty value register" hexmask.long 0x20 0.--31. 1. "SWREG_FIELD,segment 1: penalty value (all format mode)" line.long 0x24 "VENC_SWREG265,VENC segment 1: deadzone rate multiplier for plane 0-1 register" hexmask.long 0x24 0.--31. 1. "SWREG_FIELD,segment 1: Deadzone rate multiplier for plane 0-1 (all format mode)" line.long 0x28 "VENC_SWREG266,VENC segment 1: deadzone rate multiplier for plane 2-3 register" hexmask.long 0x28 0.--31. 1. "SWREG_FIELD,segment 1: Deadzone rate multiplier for plane 2-3 (all format mode)" line.long 0x2C "VENC_SWREG267,VENC segment 1: deadzone rate for macroblock skip token 0-1. dmv penalty coefficient register" hexmask.long 0x2C 0.--31. 1. "SWREG_FIELD,segment 1: Deadzone rate for macroblock skip token 0-1 dmv penalty coefficient (all format mode)" line.long 0x30 "VENC_SWREG268,VENC segment 2: intra 16x16 mode 0-2 penalty register" hexmask.long 0x30 0.--31. 1. "SWREG_FIELD,segment 2: intra 16x16 mode 0-2 penalty (all format mode)" line.long 0x34 "VENC_SWREG269,VENC segment 2: intra 16x16 mode 3 penalty. intra 4x4 mode 0-1 penalty register" hexmask.long 0x34 0.--31. 1. "SWREG_FIELD,segment 2: intra 16x16 mode 3 penalty intra 4x4 mode 0-1 penalty (all format mode)" line.long 0x38 "VENC_SWREG270,VENC segment 2: intra 4x4 mode 2-4 penalty register" hexmask.long 0x38 0.--31. 1. "SWREG_FIELD,segment 2: intra 4x4 mode 2-4 penalty (all format mode)" line.long 0x3C "VENC_SWREG271,VENC segment 2: intra 4x4 mode 5-7 penalty register" hexmask.long 0x3C 0.--31. 1. "SWREG_FIELD,segment 2: intra 4x4 mode 5-7 penalty (all format mode)" line.long 0x40 "VENC_SWREG272,VENC segment 2: intra 4x4 mode 8-9 penalty. intra 4x4 previous mode favor for H.264 register" hexmask.long 0x40 0.--31. 1. "SWREG_FIELD,segment 2: intra 4x4 mode 8-9 penalty intra 4x4 previous mode favor for H.264 (all format mode)" line.long 0x44 "VENC_SWREG273,VENC segment 2: bit cost of inter type. intra 16x16 mode favor register" hexmask.long 0x44 0.--31. 1. "SWREG_FIELD,segment 2: Bit cost of inter type intra 16x16 mode favor (all format mode)" line.long 0x48 "VENC_SWREG274,VENC segment 2: inter MB mode favor. skip mode penalty. penalty value register" hexmask.long 0x48 0.--31. 1. "SWREG_FIELD,segment 2: inter MB mode favor skip mode penalty panelty value (all format mode)" line.long 0x4C "VENC_SWREG275,VENC segment 2: penalty value register" hexmask.long 0x4C 0.--31. 1. "SWREG_FIELD,segment 2: penalty value (all format mode)" line.long 0x50 "VENC_SWREG276,VENC segment 2: penalty value register" hexmask.long 0x50 0.--31. 1. "SWREG_FIELD,segment 2: penalty value (all format mode)" line.long 0x54 "VENC_SWREG277,VENC segment 2: deadzone rate multiplier for plane 0-1 register" hexmask.long 0x54 0.--31. 1. "SWREG_FIELD,segment 2: Deadzone rate multiplier for plane 0-1 (all format mode)" line.long 0x58 "VENC_SWREG278,VENC segment 2: deadzone rate multiplier for plane 2-3 register" hexmask.long 0x58 0.--31. 1. "SWREG_FIELD,segment 2: Deadzone rate multiplier for plane 2-3 (all format mode)" line.long 0x5C "VENC_SWREG279,VENC segment 2: deadzone rate for macroblock skip token 0-1. dmv penalty coefficient register" hexmask.long 0x5C 0.--31. 1. "SWREG_FIELD,segment 2: Deadzone rate for macroblock skip token 0-1 dmv penalty coefficient (all format mode)" line.long 0x60 "VENC_SWREG280,VENC segment 3: intra 16x16 mode 0-2 penalty register" hexmask.long 0x60 0.--31. 1. "SWREG_FIELD,segment 3: intra 16x16 mode 0-2 penalty (all format mode)" line.long 0x64 "VENC_SWREG281,VENC segment 3: intra 16x16 mode 3 penalty. intra 4x4 mode 0-1 penalty register" hexmask.long 0x64 0.--31. 1. "SWREG_FIELD,segment 3: intra 16x16 mode 3 penalty intra 4x4 mode 0-1 penalty (all format mode)" line.long 0x68 "VENC_SWREG282,VENC segment 3: intra 4x4 mode 2-4 penalty register" hexmask.long 0x68 0.--31. 1. "SWREG_FIELD,segment 3: intra 4x4 mode 2-4 penalty (all format mode)" line.long 0x6C "VENC_SWREG283,VENC segment 3: intra 4x4 mode 5-7 penalty register" hexmask.long 0x6C 0.--31. 1. "SWREG_FIELD,segment 3: intra 4x4 mode 5-7 penalty (all format mode)" line.long 0x70 "VENC_SWREG284,VENC segment 3: intra 4x4 mode 8-9 penalty. intra 4x4 previous mode favor for H.264 register" hexmask.long 0x70 0.--31. 1. "SWREG_FIELD,segment 3: intra 4x4 mode 8-9 penalty intra 4x4 previous mode favor for H.264 (all format mode)" line.long 0x74 "VENC_SWREG285,VENC segment 3: bit cost of inter type. intra 16x16 mode favor register" hexmask.long 0x74 0.--31. 1. "SWREG_FIELD,segment 3: Bit cost of inter type intra 16x16 mode favor (all format mode)" line.long 0x78 "VENC_SWREG286,VENC segment 3: inter MB mode favor in intra/inter selection. inter MB mode favor. penalty value for second reference frame register" hexmask.long 0x78 0.--31. 1. "SWREG_FIELD,segment 3: inter MB mode favor in intra/inter selection inter MB mode favor penalty value for second reference frame (all format mode)" line.long 0x7C "VENC_SWREG287,VENC segment 3: penalty value register" hexmask.long 0x7C 0.--31. 1. "SWREG_FIELD,segment 3: penalty value (all format mode)" line.long 0x80 "VENC_SWREG288,VENC segment 3: penalty value register" hexmask.long 0x80 0.--31. 1. "SWREG_FIELD,segment 3: penalty value (all format mode)" line.long 0x84 "VENC_SWREG289,VENC segment 3: deadzone rate multiplier for plane 0-1 register" hexmask.long 0x84 0.--31. 1. "SWREG_FIELD,segment 3: Deadzone rate multiplier for plane 0-1 (all format mode)" line.long 0x88 "VENC_SWREG290,VENC segment 3: deadzone rate multiplier for plane 2-3 register" hexmask.long 0x88 0.--31. 1. "SWREG_FIELD,segment 3: Deadzone rate multiplier for plane 2-3 (all format mode)" line.long 0x8C "VENC_SWREG291,VENC segment 3: deadzone rate for macroblock skip token 0-1. dmv penalty coefficient register" hexmask.long 0x8C 0.--31. 1. "SWREG_FIELD,segment 3: Deadzone rate for macroblock skip token 0-1 dmv penalty coefficient (all format mode)" group.long 0x498++0x7 line.long 0x0 "VENC_SWREG294,VENC Mb boost register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Mb boost (all format mode)" line.long 0x4 "VENC_SWREG295,VENC variance control. Pskop conding mode register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,Variance control Pskop conding mode (all format mode)" rgroup.long 0x4A0++0x3 line.long 0x0 "VENC_SWREG296,VENC synthesis configuration register encoder 1 read only register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Synthesis configuration register encoder 1 (read only) (all format mode)" group.long 0x4A4++0x24F line.long 0x0 "VENC_SWREG297,VENC MBRC control register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,MBRC control (all format mode)" line.long 0x4 "VENC_SWREG298,VENC segment 4: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,segment 4: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x8 "VENC_SWREG299,VENC segment 4: skip mode penalty. inter MB mode favor register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,segment 4: skip mode penalty inter MB mode favor (all format mode)" line.long 0xC "VENC_SWREG300,VENC segment 4: penalty value register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,segment 4: penalty value (all format mode)" line.long 0x10 "VENC_SWREG301,VENC segment 4: penalty value register" hexmask.long 0x10 0.--31. 1. "SWREG_FIELD,segment 4: penalty value (all format mode)" line.long 0x14 "VENC_SWREG302,VENC segment 5: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x14 0.--31. 1. "SWREG_FIELD,segment 5: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x18 "VENC_SWREG303,VENC segment 5: skip mode penalty. inter MB mode favor register" hexmask.long 0x18 0.--31. 1. "SWREG_FIELD,segment 5: skip mode penalty inter MB mode favor (all format mode)" line.long 0x1C "VENC_SWREG304,VENC segment 5: penalty value register" hexmask.long 0x1C 0.--31. 1. "SWREG_FIELD,segment 5: penalty value (all format mode)" line.long 0x20 "VENC_SWREG305,VENC segment 5: penalty value register" hexmask.long 0x20 0.--31. 1. "SWREG_FIELD,segment 5: penalty value (all format mode)" line.long 0x24 "VENC_SWREG306,VENC segment 6: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x24 0.--31. 1. "SWREG_FIELD,segment 6: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x28 "VENC_SWREG307,VENC segment 6: skip mode penalty. inter MB mode favor register" hexmask.long 0x28 0.--31. 1. "SWREG_FIELD,segment 6: skip mode penalty inter MB mode favor (all format mode)" line.long 0x2C "VENC_SWREG308,VENC segment 6: penalty value register" hexmask.long 0x2C 0.--31. 1. "SWREG_FIELD,segment 6: penalty value (all format mode)" line.long 0x30 "VENC_SWREG309,VENC segment 6: penalty value register" hexmask.long 0x30 0.--31. 1. "SWREG_FIELD,segment 6: penalty value (all format mode)" line.long 0x34 "VENC_SWREG310,VENC segment 7: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x34 0.--31. 1. "SWREG_FIELD,segment 7: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x38 "VENC_SWREG311,VENC segment 7: skip mode penalty. inter MB mode favor register" hexmask.long 0x38 0.--31. 1. "SWREG_FIELD,segment 7: skip mode penalty inter MB mode favor (all format mode)" line.long 0x3C "VENC_SWREG312,VENC segment 7: penalty value register" hexmask.long 0x3C 0.--31. 1. "SWREG_FIELD,segment 7: penalty value (all format mode)" line.long 0x40 "VENC_SWREG313,VENC segment 7: penalty value register" hexmask.long 0x40 0.--31. 1. "SWREG_FIELD,segment 7: penalty value (all format mode)" line.long 0x44 "VENC_SWREG314,VENC segment 8: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x44 0.--31. 1. "SWREG_FIELD,segment 8: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x48 "VENC_SWREG315,VENC segment 8: skip mode penalty. inter MB mode favor register" hexmask.long 0x48 0.--31. 1. "SWREG_FIELD,segment 8: skip mode penalty inter MB mode favor (all format mode)" line.long 0x4C "VENC_SWREG316,VENC segment 8: penalty value register" hexmask.long 0x4C 0.--31. 1. "SWREG_FIELD,segment 8: penalty value (all format mode)" line.long 0x50 "VENC_SWREG317,VENC segment 8: penalty value register" hexmask.long 0x50 0.--31. 1. "SWREG_FIELD,segment 8: penalty value (all format mode)" line.long 0x54 "VENC_SWREG318,VENC segment 9: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x54 0.--31. 1. "SWREG_FIELD,segment 9: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x58 "VENC_SWREG319,VENC segment 9: skip mode penalty. inter MB mode favor register" hexmask.long 0x58 0.--31. 1. "SWREG_FIELD,segment 9: skip mode penalty inter MB mode favor (all format mode)" line.long 0x5C "VENC_SWREG320,VENC segment 9: penalty value register" hexmask.long 0x5C 0.--31. 1. "SWREG_FIELD,segment 9: penalty value (all format mode)" line.long 0x60 "VENC_SWREG321,VENC segment 9: penalty value register" hexmask.long 0x60 0.--31. 1. "SWREG_FIELD,segment 9: penalty value (all format mode)" line.long 0x64 "VENC_SWREG322,VENC segment 10: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x64 0.--31. 1. "SWREG_FIELD,segment 10: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x68 "VENC_SWREG323,VENC segment 10: skip mode penalty. inter MB mode favor register" hexmask.long 0x68 0.--31. 1. "SWREG_FIELD,segment 10: skip mode penalty inter MB mode favor (all format mode)" line.long 0x6C "VENC_SWREG324,VENC segment 10: penalty value register" hexmask.long 0x6C 0.--31. 1. "SWREG_FIELD,segment 10: penalty value (all format mode)" line.long 0x70 "VENC_SWREG325,VENC segment 10: penalty value register" hexmask.long 0x70 0.--31. 1. "SWREG_FIELD,segment 10: penalty value (all format mode)" line.long 0x74 "VENC_SWREG326,VENC segment 11: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x74 0.--31. 1. "SWREG_FIELD,segment 11: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x78 "VENC_SWREG327,VENC segment 11: skip mode penalty. inter MB mode favor register" hexmask.long 0x78 0.--31. 1. "SWREG_FIELD,segment 11: skip mode penalty inter MB mode favor (all format mode)" line.long 0x7C "VENC_SWREG328,VENC segment 11: penalty value register" hexmask.long 0x7C 0.--31. 1. "SWREG_FIELD,segment 11: penalty value (all format mode)" line.long 0x80 "VENC_SWREG329,VENC segment 11: penalty value register" hexmask.long 0x80 0.--31. 1. "SWREG_FIELD,segment 11: penalty value (all format mode)" line.long 0x84 "VENC_SWREG330,VENC segment 12: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x84 0.--31. 1. "SWREG_FIELD,segment 12: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x88 "VENC_SWREG331,VENC segment 12: skip mode penalty. inter MB mode favor register" hexmask.long 0x88 0.--31. 1. "SWREG_FIELD,segment 12: skip mode penalty inter MB mode favor (all format mode)" line.long 0x8C "VENC_SWREG332,VENC segment 12: penalty value register" hexmask.long 0x8C 0.--31. 1. "SWREG_FIELD,segment 12: penalty value (all format mode)" line.long 0x90 "VENC_SWREG333,VENC segment 12: penalty value register" hexmask.long 0x90 0.--31. 1. "SWREG_FIELD,segment 12: penalty value (all format mode)" line.long 0x94 "VENC_SWREG334,VENC segment 13: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x94 0.--31. 1. "SWREG_FIELD,segment 13: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x98 "VENC_SWREG335,VENC segment 13: skip mode penalty. inter MB mode favor register" hexmask.long 0x98 0.--31. 1. "SWREG_FIELD,segment 13: skip mode penalty inter MB mode favor (all format mode)" line.long 0x9C "VENC_SWREG336,VENC segment 13: penalty value register" hexmask.long 0x9C 0.--31. 1. "SWREG_FIELD,segment 13: penalty value (all format mode)" line.long 0xA0 "VENC_SWREG337,VENC segment 13: penalty value register" hexmask.long 0xA0 0.--31. 1. "SWREG_FIELD,segment 13: penalty value (all format mode)" line.long 0xA4 "VENC_SWREG338,VENC segment 14: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xA4 0.--31. 1. "SWREG_FIELD,segment 14: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xA8 "VENC_SWREG339,VENC segment 14: skip mode penalty. inter MB mode favor register" hexmask.long 0xA8 0.--31. 1. "SWREG_FIELD,segment 14: skip mode penalty inter MB mode favor (all format mode)" line.long 0xAC "VENC_SWREG340,VENC segment 14: penalty value register" hexmask.long 0xAC 0.--31. 1. "SWREG_FIELD,segment 14: penalty value (all format mode)" line.long 0xB0 "VENC_SWREG341,VENC segment 14: penalty value register" hexmask.long 0xB0 0.--31. 1. "SWREG_FIELD,segment 14: penalty value (all format mode)" line.long 0xB4 "VENC_SWREG342,VENC segment 15: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xB4 0.--31. 1. "SWREG_FIELD,segment 15: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xB8 "VENC_SWREG343,VENC segment 15: skip mode penalty. inter MB mode favor register" hexmask.long 0xB8 0.--31. 1. "SWREG_FIELD,segment 15: skip mode penalty inter MB mode favor (all format mode)" line.long 0xBC "VENC_SWREG344,VENC segment 15: penalty value register" hexmask.long 0xBC 0.--31. 1. "SWREG_FIELD,segment 15: penalty value (all format mode)" line.long 0xC0 "VENC_SWREG345,VENC segment 15: penalty value register" hexmask.long 0xC0 0.--31. 1. "SWREG_FIELD,segment 15: penalty value (all format mode)" line.long 0xC4 "VENC_SWREG346,VENC segment 16: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xC4 0.--31. 1. "SWREG_FIELD,segment 16: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xC8 "VENC_SWREG347,VENC segment 16: skip mode penalty. inter MB mode favor register" hexmask.long 0xC8 0.--31. 1. "SWREG_FIELD,segment 16: skip mode penalty inter MB mode favor (all format mode)" line.long 0xCC "VENC_SWREG348,VENC segment 16: penalty value register" hexmask.long 0xCC 0.--31. 1. "SWREG_FIELD,segment 16: penalty value (all format mode)" line.long 0xD0 "VENC_SWREG349,VENC segment 16: penalty value register" hexmask.long 0xD0 0.--31. 1. "SWREG_FIELD,segment 16: penalty value (all format mode)" line.long 0xD4 "VENC_SWREG350,VENC segment 17: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xD4 0.--31. 1. "SWREG_FIELD,segment 17: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xD8 "VENC_SWREG351,VENC segment 17: skip mode penalty. inter MB mode favor register" hexmask.long 0xD8 0.--31. 1. "SWREG_FIELD,segment 17: skip mode penalty inter MB mode favor (all format mode)" line.long 0xDC "VENC_SWREG352,VENC segment 17: penalty value register" hexmask.long 0xDC 0.--31. 1. "SWREG_FIELD,segment 17: penalty value (all format mode)" line.long 0xE0 "VENC_SWREG353,VENC segment 17: penalty value register" hexmask.long 0xE0 0.--31. 1. "SWREG_FIELD,segment 17: penalty value (all format mode)" line.long 0xE4 "VENC_SWREG354,VENC segment 18: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xE4 0.--31. 1. "SWREG_FIELD,segment 18: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xE8 "VENC_SWREG355,VENC segment 18: skip mode penalty. inter MB mode favor register" hexmask.long 0xE8 0.--31. 1. "SWREG_FIELD,segment 18: skip mode penalty inter MB mode favor (all format mode)" line.long 0xEC "VENC_SWREG356,VENC segment 18: penalty value register" hexmask.long 0xEC 0.--31. 1. "SWREG_FIELD,segment 18: penalty value (all format mode)" line.long 0xF0 "VENC_SWREG357,VENC segment 18: penalty value register" hexmask.long 0xF0 0.--31. 1. "SWREG_FIELD,segment 18: penalty value (all format mode)" line.long 0xF4 "VENC_SWREG358,VENC segment 19: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xF4 0.--31. 1. "SWREG_FIELD,segment 19: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xF8 "VENC_SWREG359,VENC segment 19: skip mode penalty. inter MB mode favor register" hexmask.long 0xF8 0.--31. 1. "SWREG_FIELD,segment 19: skip mode penalty inter MB mode favor (all format mode)" line.long 0xFC "VENC_SWREG360,VENC segment 19: penalty value register" hexmask.long 0xFC 0.--31. 1. "SWREG_FIELD,segment 19: penalty value (all format mode)" line.long 0x100 "VENC_SWREG361,VENC segment 19: penalty value register" hexmask.long 0x100 0.--31. 1. "SWREG_FIELD,segment 19: penalty value (all format mode)" line.long 0x104 "VENC_SWREG362,VENC segment 20: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x104 0.--31. 1. "SWREG_FIELD,segment 20: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x108 "VENC_SWREG363,VENC segment 20: skip mode penalty. inter MB mode favor register" hexmask.long 0x108 0.--31. 1. "SWREG_FIELD,segment 20: skip mode penalty inter MB mode favor (all format mode)" line.long 0x10C "VENC_SWREG364,VENC segment 20: penalty value register" hexmask.long 0x10C 0.--31. 1. "SWREG_FIELD,segment 20: penalty value (all format mode)" line.long 0x110 "VENC_SWREG365,VENC segment 20: penalty value register" hexmask.long 0x110 0.--31. 1. "SWREG_FIELD,segment 20: penalty value (all format mode)" line.long 0x114 "VENC_SWREG366,VENC segment 21: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x114 0.--31. 1. "SWREG_FIELD,segment 21: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x118 "VENC_SWREG367,VENC segment 21: skip mode penalty. inter MB mode favor register" hexmask.long 0x118 0.--31. 1. "SWREG_FIELD,segment 21: skip mode penalty inter MB mode favor (all format mode)" line.long 0x11C "VENC_SWREG368,VENC segment 21: penalty value register" hexmask.long 0x11C 0.--31. 1. "SWREG_FIELD,segment 21: penalty value (all format mode)" line.long 0x120 "VENC_SWREG369,VENC segment 21: penalty value register" hexmask.long 0x120 0.--31. 1. "SWREG_FIELD,segment 21: penalty value (all format mode)" line.long 0x124 "VENC_SWREG370,VENC segment 22: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x124 0.--31. 1. "SWREG_FIELD,segment 22: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x128 "VENC_SWREG371,VENC segment 22: skip mode penalty. inter MB mode favor register" hexmask.long 0x128 0.--31. 1. "SWREG_FIELD,segment 22: skip mode penalty inter MB mode favor (all format mode)" line.long 0x12C "VENC_SWREG372,VENC segment 22: penalty value register" hexmask.long 0x12C 0.--31. 1. "SWREG_FIELD,segment 22: penalty value (all format mode)" line.long 0x130 "VENC_SWREG373,VENC segment 22: penalty value register" hexmask.long 0x130 0.--31. 1. "SWREG_FIELD,segment 22: penalty value (all format mode)" line.long 0x134 "VENC_SWREG374,VENC segment 23: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x134 0.--31. 1. "SWREG_FIELD,segment 23: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x138 "VENC_SWREG375,VENC segment 23: skip mode penalty. inter MB mode favor register" hexmask.long 0x138 0.--31. 1. "SWREG_FIELD,segment 23: skip mode penalty inter MB mode favor (all format mode)" line.long 0x13C "VENC_SWREG376,VENC segment 23: penalty value register" hexmask.long 0x13C 0.--31. 1. "SWREG_FIELD,segment 23: penalty value (all format mode)" line.long 0x140 "VENC_SWREG377,VENC segment 23: penalty value register" hexmask.long 0x140 0.--31. 1. "SWREG_FIELD,segment 23: penalty value (all format mode)" line.long 0x144 "VENC_SWREG378,VENC segment 24: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x144 0.--31. 1. "SWREG_FIELD,segment 24: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x148 "VENC_SWREG379,VENC segment 24: skip mode penalty. inter MB mode favor register" hexmask.long 0x148 0.--31. 1. "SWREG_FIELD,segment 24: skip mode penalty inter MB mode favor (all format mode)" line.long 0x14C "VENC_SWREG380,VENC segment 24: penalty value register" hexmask.long 0x14C 0.--31. 1. "SWREG_FIELD,segment 24: penalty value (all format mode)" line.long 0x150 "VENC_SWREG381,VENC segment 24: penalty value register" hexmask.long 0x150 0.--31. 1. "SWREG_FIELD,segment 24: penalty value (all format mode)" line.long 0x154 "VENC_SWREG382,VENC segment 25: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x154 0.--31. 1. "SWREG_FIELD,segment 25: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x158 "VENC_SWREG383,VENC segment 25: skip mode penalty. inter MB mode favor register" hexmask.long 0x158 0.--31. 1. "SWREG_FIELD,segment 25: skip mode penalty inter MB mode favor (all format mode)" line.long 0x15C "VENC_SWREG384,VENC segment 25: penalty value register" hexmask.long 0x15C 0.--31. 1. "SWREG_FIELD,segment 25: penalty value (all format mode)" line.long 0x160 "VENC_SWREG385,VENC segment 25: penalty value register" hexmask.long 0x160 0.--31. 1. "SWREG_FIELD,segment 25: penalty value (all format mode)" line.long 0x164 "VENC_SWREG386,VENC segment 26: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x164 0.--31. 1. "SWREG_FIELD,segment 26: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x168 "VENC_SWREG387,VENC segment 26: skip mode penalty. inter MB mode favor register" hexmask.long 0x168 0.--31. 1. "SWREG_FIELD,segment 26: skip mode penalty inter MB mode favor (all format mode)" line.long 0x16C "VENC_SWREG388,VENC segment 26: penalty value register" hexmask.long 0x16C 0.--31. 1. "SWREG_FIELD,segment 26: penalty value (all format mode)" line.long 0x170 "VENC_SWREG389,VENC segment 26: penalty value register" hexmask.long 0x170 0.--31. 1. "SWREG_FIELD,segment 26: penalty value (all format mode)" line.long 0x174 "VENC_SWREG390,VENC segment 27: intra 4x4 previous mode favor. intra 16x16mode favor. penalty value for second reference frame register" hexmask.long 0x174 0.--31. 1. "SWREG_FIELD,segment 27: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x178 "VENC_SWREG391,VENC segment 27: skip mode penalty. inter MB mode favor register" hexmask.long 0x178 0.--31. 1. "SWREG_FIELD,segment 27: skip mode penalty inter MB mode favor (all format mode)" line.long 0x17C "VENC_SWREG392,VENC segment 27: penalty value register" hexmask.long 0x17C 0.--31. 1. "SWREG_FIELD,segment 27: penalty value (all format mode)" line.long 0x180 "VENC_SWREG393,VENC segment 27: penalty value register" hexmask.long 0x180 0.--31. 1. "SWREG_FIELD,segment 27: penalty value (all format mode)" line.long 0x184 "VENC_SWREG394,VENC segment 28: intra 4x4 previous mode favor. intra 16x16mode favor. penalty value for second reference frame register" hexmask.long 0x184 0.--31. 1. "SWREG_FIELD,segment 28: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x188 "VENC_SWREG395,VENC segment 28: skip mode penalty. inter MB mode favor register" hexmask.long 0x188 0.--31. 1. "SWREG_FIELD,segment 28: skip mode penalty inter MB mode favor (all format mode)" line.long 0x18C "VENC_SWREG396,VENC segment 28: penalty value register" hexmask.long 0x18C 0.--31. 1. "SWREG_FIELD,segment 28: penalty value (all format mode)" line.long 0x190 "VENC_SWREG397,VENC segment 28: penalty value register" hexmask.long 0x190 0.--31. 1. "SWREG_FIELD,segment 28: penalty value (all format mode)" line.long 0x194 "VENC_SWREG398,VENC segment 29: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x194 0.--31. 1. "SWREG_FIELD,segment 29: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x198 "VENC_SWREG399,VENC segment 29: skip mode penalty. inter MB mode favor register" hexmask.long 0x198 0.--31. 1. "SWREG_FIELD,segment 29: skip mode penalty inter MB mode favor (all format mode)" line.long 0x19C "VENC_SWREG400,VENC segment 29: penalty value register" hexmask.long 0x19C 0.--31. 1. "SWREG_FIELD,segment 29: penalty value (all format mode)" line.long 0x1A0 "VENC_SWREG401,VENC segment 29: penalty value register" hexmask.long 0x1A0 0.--31. 1. "SWREG_FIELD,segment 29: penalty value (all format mode)" line.long 0x1A4 "VENC_SWREG402,VENC segment 30: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x1A4 0.--31. 1. "SWREG_FIELD,segment 30: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x1A8 "VENC_SWREG403,VENC segment 30: skip mode penalty. inter MB mode favor register" hexmask.long 0x1A8 0.--31. 1. "SWREG_FIELD,segment 30: skip mode penalty inter MB mode favor (all format mode)" line.long 0x1AC "VENC_SWREG404,VENC segment 30: penalty value register" hexmask.long 0x1AC 0.--31. 1. "SWREG_FIELD,segment 30: penalty value (all format mode)" line.long 0x1B0 "VENC_SWREG405,VENC segment 30: penalty value register" hexmask.long 0x1B0 0.--31. 1. "SWREG_FIELD,segment 30: penalty value (all format mode)" line.long 0x1B4 "VENC_SWREG406,VENC segment 31: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x1B4 0.--31. 1. "SWREG_FIELD,segment 31: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x1B8 "VENC_SWREG407,VENC segment 31: skip mode penalty. inter MB mode favor register" hexmask.long 0x1B8 0.--31. 1. "SWREG_FIELD,segment 31: skip mode penalty inter MB mode favor (all format mode)" line.long 0x1BC "VENC_SWREG408,VENC segment 31: penalty value register" hexmask.long 0x1BC 0.--31. 1. "SWREG_FIELD,segment 31: penalty value (all format mode)" line.long 0x1C0 "VENC_SWREG409,VENC segment 31: penalty value register" hexmask.long 0x1C0 0.--31. 1. "SWREG_FIELD,segment 31: penalty value (all format mode)" line.long 0x1C4 "VENC_SWREG410,VENC MBRC control. QP. offset. enable register" hexmask.long 0x1C4 0.--31. 1. "SWREG_FIELD,MBRC control (QP offset enable) (all format mode)" line.long 0x1C8 "VENC_SWREG411,VENC gain of MB QP delta. 8.8 format register" hexmask.long 0x1C8 0.--31. 1. "SWREG_FIELD,gain of MB QPdelta. 8.8 format (all format mode)" line.long 0x1CC "VENC_SWREG412,VENC average of MB complexity register" hexmask.long 0x1CC 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1D0 "VENC_SWREG413,VENC reference compression control register" hexmask.long 0x1D0 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1D4 "VENC_SWREG414,VENC base address for reference luma register" hexmask.long 0x1D4 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1D8 "VENC_SWREG415,VENC base address for reference chroma register" hexmask.long 0x1D8 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1DC "VENC_SWREG416,VENC base address for reconstructed luma register" hexmask.long 0x1DC 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1E0 "VENC_SWREG417,VENC base address for reconstructed chroma register" hexmask.long 0x1E0 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1E4 "VENC_SWREG418,VENC base address for second reference luma register" hexmask.long 0x1E4 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1E8 "VENC_SWREG419,VENC base address for second reference chroma register" hexmask.long 0x1E8 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1EC "VENC_SWREG420,VENC limit of chroma RFC buffer register" hexmask.long 0x1EC 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1F0 "VENC_SWREG421,VENC reorder control register" hexmask.long 0x1F0 0.--31. 1. "SWREG_FIELD,Reorder control (all format mode)" line.long 0x1F4 "VENC_SWREG422,VENC AXI read ID register" hexmask.long 0x1F4 0.--31. 1. "SWREG_FIELD,AXI Read ID (all format mode)" line.long 0x1F8 "VENC_SWREG423,VENC base address MSB for reference luma compression table register" hexmask.long 0x1F8 0.--31. 1. "SWREG_FIELD,AXI Read ID (all format mode)" line.long 0x1FC "VENC_SWREG424,VENC base address MSB for reference chroma compression table register" hexmask.long 0x1FC 0.--31. 1. "SWREG_FIELD,AXI Read ID (all format mode)" line.long 0x200 "VENC_SWREG425,VENC base address MSB for reconstructed luma compression table register" hexmask.long 0x200 0.--31. 1. "SWREG_FIELD,AXI Read ID (all format mode)" line.long 0x204 "VENC_SWREG426,VENC base address for reconstructed chroma compression table register" hexmask.long 0x204 0.--31. 1. "SWREG_FIELD,Base address for reconstructed chroma compression table (all format mode)" line.long 0x208 "VENC_SWREG427,VENC base address MSB for second reference luma compression table register" hexmask.long 0x208 0.--31. 1. "SWREG_FIELD,Base address MSB for second reference luma compression table (all format mode)" line.long 0x20C "VENC_SWREG428,VENC base address MSB for second reference chroma compression table register" hexmask.long 0x20C 0.--31. 1. "SWREG_FIELD,Base address MSB for second reference chroma compression table (all format mode)" line.long 0x210 "VENC_SWREG429,VENC high 32 bits of base address for output stream data register" hexmask.long 0x210 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for output stream data (all format mode)" line.long 0x214 "VENC_SWREG430,VENC high 32 bits of base address for output control data register" hexmask.long 0x214 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for output control data (all format mode)" line.long 0x218 "VENC_SWREG431,VENC high 32 bits of base address for reference luma register" hexmask.long 0x218 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for reference luma (all format mode)" line.long 0x21C "VENC_SWREG432,VENC high 32 bits of base address for reference chroma register" hexmask.long 0x21C 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for reference chroma (all format mode)" line.long 0x220 "VENC_SWREG433,VENC high 32 bits of base address for reconstructed luma register" hexmask.long 0x220 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for reconstructed luma (all format mode)" line.long 0x224 "VENC_SWREG434,VENC high 32 bits of base address for reconstructed chroma register" hexmask.long 0x224 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for reconstructed chroma (all format mode)" line.long 0x228 "VENC_SWREG435,VENC high 32 bits of base address for input picture luma register" hexmask.long 0x228 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for input picture luma (all format mode)" line.long 0x22C "VENC_SWREG436,VENC high 32 bits of base address for input picture cb register" hexmask.long 0x22C 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for input picture cb (all format mode)" line.long 0x230 "VENC_SWREG437,VENC high 32 bits of base address for input picture cr register" hexmask.long 0x230 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for input picture cr (all format mode)" line.long 0x234 "VENC_SWREG438,VENC high 32 bits of base address for second reference luma register" hexmask.long 0x234 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for second reference luma (all format mode)" line.long 0x238 "VENC_SWREG439,VENC high 32 bits of base address for second reference chroma register" hexmask.long 0x238 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for second reference chroma (all format mode)" line.long 0x23C "VENC_SWREG440,VENC high 32 bits of H264 secondary ref pic base register" hexmask.long 0x23C 0.--31. 1. "SWREG_FIELD,high 32 bits of H264 secondary ref pic base (all format mode)" line.long 0x240 "VENC_SWREG441,VENC high 32 bits of H264 secondary ref pic base register" hexmask.long 0x240 0.--31. 1. "SWREG_FIELD,high 32 bits of H264 secondary ref pic base (all format mode)" line.long 0x244 "VENC_SWREG442,VENC high 32 bits of base address for next pic luminance register" hexmask.long 0x244 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for next pic luminance (all format mode)" line.long 0x248 "VENC_SWREG443,VENC high 32 bits of base address for cabac context tables H264 register" hexmask.long 0x248 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for cabac context tables (H264) or probability tables (all format mode)" line.long 0x24C "VENC_SWREG444,VENC high 32 bits of base address for MV output writing register" hexmask.long 0x24C 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for MV output writing (all format mode)" group.long 0x704++0x3 line.long 0x0 "VENC_SWREG449,VENC high 32 bits of base address for output of down-scaled encoder image in YUYV 4:2:2 format register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for output of down-scaled encoder image in YUYV 4:2:2 format (all format mode)" group.long 0x7C4++0x7 line.long 0x0 "VENC_SWREG497,VENC low-latency control register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Low latency control (all format mode)" line.long 0x4 "VENC_SWREG498,VENC encoder line buffer offset register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,Low latency control (all format mode)" tree.end tree "VENC_S" base ad:0x58005000 group.long 0x0++0xF line.long 0x0 "VENC_SWREG0,VENC ID register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Interrupt register (all format mode)" line.long 0x4 "VENC_SWREG1,VENC interrupt register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,Interrupt register (all format mode)" line.long 0x8 "VENC_SWREG2,VENC bus interface configuration register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,Bus interface configuration register (all format mode)" line.long 0xC "VENC_SWREG3,VENC device configuration register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,Device configuration register (all format mode)" group.long 0x14++0xE7 line.long 0x0 "VENC_SWREG5,VENC base address for output stream data register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Base address for output stream data (all format mode)" line.long 0x4 "VENC_SWREG6,VENC base address for output control data register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,Base address for output control data (all format mode)" line.long 0x8 "VENC_SWREG7,VENC base address for reference luma register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,Base address for reference luma (all format mode)" line.long 0xC "VENC_SWREG8,VENC base address for reference chroma register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,Base address for reference chroma (all format mode)" line.long 0x10 "VENC_SWREG9,VENC base address for reconstructed luma register" hexmask.long 0x10 0.--31. 1. "SWREG_FIELD,Base address for reconstructed luma (all format mode)" line.long 0x14 "VENC_SWREG10,VENC base address for reconstructed chroma register" hexmask.long 0x14 0.--31. 1. "SWREG_FIELD,Base address for reconstructed chroma (all format mode)" line.long 0x18 "VENC_SWREG11,VENC base address for input picture luma register" hexmask.long 0x18 0.--31. 1. "SWREG_FIELD,Base address for input picture luma (all format mode)" line.long 0x1C "VENC_SWREG12,VENC base address for input picture cb register" hexmask.long 0x1C 0.--31. 1. "SWREG_FIELD,Base address for input picture cb (all format mode)" line.long 0x20 "VENC_SWREG13,VENC base address for input picture cr register" hexmask.long 0x20 0.--31. 1. "SWREG_FIELD,Base address for input picture cr (all format mode)" line.long 0x24 "VENC_SWREG14,VENC encoder control register 0" hexmask.long 0x24 0.--31. 1. "SWREG_FIELD,Encoder control register 0 (such as picture information or encoding mode) (all format mode)" line.long 0x28 "VENC_SWREG15,VENC encoder control register 1" hexmask.long 0x28 0.--31. 1. "SWREG_FIELD,Encoder control register 1 (such as preprocessing control crop rotate input format) (all format mode)" line.long 0x2C "VENC_SWREG16,VENC encoder control register 2" hexmask.long 0x2C 0.--31. 1. "SWREG_FIELD,Base address for second reference luma (H264 control) (all format mode)" line.long 0x30 "VENC_SWREG17,VENC encoder control register 3" hexmask.long 0x30 0.--31. 1. "SWREG_FIELD,Base address for second reference chroma (H264 control) (all format mode)" line.long 0x34 "VENC_SWREG18,VENC encoder control register 4" hexmask.long 0x34 0.--31. 1. "SWREG_FIELD,Encoder control register 4 (deblock filter mode H264 control) (all format mode)" line.long 0x38 "VENC_SWREG19,VENC encoder control register 5" hexmask.long 0x38 0.--31. 1. "SWREG_FIELD,Encoder control register 5 (input format motion vector etc) (all format mode)" line.long 0x3C "VENC_SWREG20,VENC encoder control register 6" hexmask.long 0x3C 0.--31. 1. "SWREG_FIELD,Control of data JPEG (all format mode)" line.long 0x40 "VENC_SWREG21,VENC encoder control register 7" hexmask.long 0x40 0.--31. 1. "SWREG_FIELD,Control of H264 (all format mode)" line.long 0x44 "VENC_SWREG22,VENC stream header remainder MSB bits register" hexmask.long 0x44 0.--31. 1. "SWREG_FIELD,Stream header remainder bits MSB (MSB aligned) (all format mode)" line.long 0x48 "VENC_SWREG23,VENC stream header remainder LSB bits register" hexmask.long 0x48 0.--31. 1. "SWREG_FIELD,Stream header remainder bits LSB (MSB aligned) (all format mode)" line.long 0x4C "VENC_SWREG24,VENC stream buffer limit/output stream size register" hexmask.long 0x4C 0.--31. 1. "SWREG_FIELD,Stream buffer limit (64-bit addresses)/output stream size (bits) (all format mode)" line.long 0x50 "VENC_SWREG25,VENC encoder control register 8" hexmask.long 0x50 0.--31. 1. "SWREG_FIELD,Control of MAD control and QP sum output (all format mode)" line.long 0x54 "VENC_SWREG26,VENC intra-slice bitmap register" hexmask.long 0x54 0.--31. 1. "SWREG_FIELD,intra-slice bitmap for probability updates (all format mode)" line.long 0x58 "VENC_SWREG27,VENC encoder control register 9" hexmask.long 0x58 0.--31. 1. "SWREG_FIELD,Control of H264 QP (all format mode)" line.long 0x5C "VENC_SWREG28,VENC encoder control register 10" hexmask.long 0x5C 0.--31. 1. "SWREG_FIELD,H264 checkpoint 1-2 (all format mode)" line.long 0x60 "VENC_SWREG29,VENC encoder control register 11" hexmask.long 0x60 0.--31. 1. "SWREG_FIELD,H.264 Checkpoint 3 -4 (all format mode)" line.long 0x64 "VENC_SWREG30,VENC encoder control register 12" hexmask.long 0x64 0.--31. 1. "SWREG_FIELD,H.264 checkpoint 5 -6 (all format mode)" line.long 0x68 "VENC_SWREG31,VENC encoder control register 13" hexmask.long 0x68 0.--31. 1. "SWREG_FIELD,H.264 checkpoint 7 -8 (all format mode)" line.long 0x6C "VENC_SWREG32,VENC encoder control register 14" hexmask.long 0x6C 0.--31. 1. "SWREG_FIELD,H.264 Checkpoint 8 -10 / Encoder control register 14 (all format mode)" line.long 0x70 "VENC_SWREG33,VENC encoder control register 15" hexmask.long 0x70 0.--31. 1. "SWREG_FIELD,H.264 Checkpoint word error 1-2 (all format mode)" line.long 0x74 "VENC_SWREG34,VENC encoder control register 16" hexmask.long 0x74 0.--31. 1. "SWREG_FIELD,H.264 checkpoint word error 3-4 and the second reference frame control (all format mode)" line.long 0x78 "VENC_SWREG35,VENC H.264 checkpoint word error 5-6/encoder control register 17" hexmask.long 0x78 0.--31. 1. "SWREG_FIELD,H.264 Checkpoint word error 5-6 / Encoder control register 17 (all format mode)" line.long 0x7C "VENC_SWREG36,VENC H.264 checkpoint delta QP 1-8/encoder control register 18" hexmask.long 0x7C 0.--31. 1. "SWREG_FIELD,H.264 Checkpoint delta QP 1-8 / Encoder control register 18 (all format mode)" line.long 0x80 "VENC_SWREG37,VENC encoder control register 19. stream start offset" hexmask.long 0x80 0.--31. 1. "SWREG_FIELD,Encoder control register 19 (all format mode)" line.long 0x84 "VENC_SWREG38,VENC macroblock count output register" hexmask.long 0x84 0.--31. 1. "SWREG_FIELD,Macroblock count output (all format mode)" line.long 0x88 "VENC_SWREG39,VENC base address for next pic luminance register" hexmask.long 0x88 0.--31. 1. "SWREG_FIELD,Base address for next pic luminance (all format mode)" line.long 0x8C "VENC_SWREG40,VENC stabilization mode control register" hexmask.long 0x8C 0.--31. 1. "SWREG_FIELD,Stabilization mode control (all format mode)" line.long 0x90 "VENC_SWREG41,VENC stabilization motion sum div8 output register" hexmask.long 0x90 0.--31. 1. "SWREG_FIELD,Stabilization motion sum div8 output (all format mode)" line.long 0x94 "VENC_SWREG42,VENC stabilization GMV output. matrix 1. up-left position output register" hexmask.long 0x94 0.--31. 1. "SWREG_FIELD,Stabilization GMV output matrix 1 (up-left position) output (all format mode)" line.long 0x98 "VENC_SWREG43,VENC stabilization GMV output. matrix 2. up position output register" hexmask.long 0x98 0.--31. 1. "SWREG_FIELD,Stabilization GMV output matrix 2 (up position) output (all format mode)" line.long 0x9C "VENC_SWREG44,VENC stabilization matrix 3. up-right position output register" hexmask.long 0x9C 0.--31. 1. "SWREG_FIELD,Stabilization matrix 3 (up-right position) output (all format mode)" line.long 0xA0 "VENC_SWREG45,VENC stabilization matrix 4. left position output register" hexmask.long 0xA0 0.--31. 1. "SWREG_FIELD,Stabilization matrix 4 (left position) output (all format mode)" line.long 0xA4 "VENC_SWREG46,VENC stabilization matrix 5. GMV position output register" hexmask.long 0xA4 0.--31. 1. "SWREG_FIELD,Stabilization matrix 5 (GMV position) output (all format mode)" line.long 0xA8 "VENC_SWREG47,VENC stabilization matrix 6. right position output register" hexmask.long 0xA8 0.--31. 1. "SWREG_FIELD,Stabilization matrix 6 (right position) output (all format mode)" line.long 0xAC "VENC_SWREG48,VENC stabilization matrix 7. down-left position output register" hexmask.long 0xAC 0.--31. 1. "SWREG_FIELD,Stabilization matrix 7 (down-left position) output (all format mode)" line.long 0xB0 "VENC_SWREG49,VENC stabilization matrix 8. down position output register" hexmask.long 0xB0 0.--31. 1. "SWREG_FIELD,Stabilization matrix 8 (down position) output (all format mode)" line.long 0xB4 "VENC_SWREG50,VENC stabilization matrix 9. down-right position output register" hexmask.long 0xB4 0.--31. 1. "SWREG_FIELD,Stabilization matrix 9 (down-right position) output (all format mode)" line.long 0xB8 "VENC_SWREG51,VENC base address for cabac context tables H264 register" hexmask.long 0xB8 0.--31. 1. "SWREG_FIELD,Base address for cabac context tables (H264) or probability tables (all format mode)" line.long 0xBC "VENC_SWREG52,VENC base address for MV output writing register" hexmask.long 0xBC 0.--31. 1. "SWREG_FIELD,Base address for MV output writing (all format mode)" line.long 0xC0 "VENC_SWREG53,VENC RGB to YUV conversion coefficient A - B register" hexmask.long 0xC0 0.--31. 1. "SWREG_FIELD,RGB to YUV conversion coefficient A - B (all format mode)" line.long 0xC4 "VENC_SWREG54,VENC RGB to YUV conversion coefficient C - E register" hexmask.long 0xC4 0.--31. 1. "SWREG_FIELD,RGB to YUV conversion coefficient C - E (all format mode)" line.long 0xC8 "VENC_SWREG55,VENC RGB to YUV conversion coefficient F. RGB mask MSB bit position register" hexmask.long 0xC8 0.--31. 1. "SWREG_FIELD,RGB to YUV conversion coefficient F RGB mask MSB bit position (all format mode)" line.long 0xCC "VENC_SWREG56,VENC intra area register" hexmask.long 0xCC 0.--31. 1. "SWREG_FIELD,intra area (all format mode)" line.long 0xD0 "VENC_SWREG57,VENC CIR intra mb position register" hexmask.long 0xD0 0.--31. 1. "SWREG_FIELD,CIR intra mb position (all format mode)" line.long 0xD4 "VENC_SWREG58,VENC intra slice bitmap for slices 0..31/base address for 1st DCT partition register" hexmask.long 0xD4 0.--31. 1. "SWREG_FIELD,intra slice bitmap for slices 0..31 / Base address for 1st DCT partition (all format mode)" line.long 0xD8 "VENC_SWREG59,VENC intra slice bitmap for slices 32..63/base address for 2nd DCT partition register" hexmask.long 0xD8 0.--31. 1. "SWREG_FIELD,intra slice bitmap for slices 32..63 / Base address for 2nd DCT partition (all format mode)" line.long 0xDC "VENC_SWREG60,VENC 1st ROI area register" hexmask.long 0xDC 0.--31. 1. "SWREG_FIELD,1st ROI area (all format mode)" line.long 0xE0 "VENC_SWREG61,VENC 2nd ROI area register" hexmask.long 0xE0 0.--31. 1. "SWREG_FIELD,2nd ROI area (all format mode)" line.long 0xE4 "VENC_SWREG62,VENC ROI area delta QP. MV register" hexmask.long 0xE4 0.--31. 1. "SWREG_FIELD,ROI area delta QP MV (all format mode)" rgroup.long 0xFC++0x3 line.long 0x0 "VENC_SWREG63,VENC synthesis configuration register encoder 0 register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Synthesis configuration register encoder 0 (read only) (all format mode)" group.long 0x100++0x7F line.long 0x0 "VENC_SWREG64,VENC JPEG luma quantization 1/intra 16x16 mode 0-1 penalty register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 1 / intra 16x16 mode 0-1 penalty (all format mode)" line.long 0x4 "VENC_SWREG65,VENC JPEG luma quantization 2/intra 16x16 mode 2-3 penalty register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 2 / intra 16x16 mode 2-3 penalty (all format mode)" line.long 0x8 "VENC_SWREG66,VENC JPEG luma quantization 3/intra 4x4 mode 0-1 penalty register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 3 / intra 4x4 mode 0-1 penalty (all format mode)" line.long 0xC "VENC_SWREG67,VENC JPEG luma quantization 4/intra 4x4 mode 2-3 penalty register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 4 / intra 4x4 mode 2-3 penalty (all format mode)" line.long 0x10 "VENC_SWREG68,VENC JPEG luma quantization 5/intra 4x4 mode 4-5 penalty register" hexmask.long 0x10 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 5 / intra 4x4 mode 4-5 penalty (all format mode)" line.long 0x14 "VENC_SWREG69,VENC JPEG luma quantization 6/intra 4x4 mode 6-7 penalty register" hexmask.long 0x14 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 6 / intra 4x4 mode 6-7 penalty (all format mode)" line.long 0x18 "VENC_SWREG70,VENC JPEG luma quantization 7/intra 4x4 mode 8-9 penalty register" hexmask.long 0x18 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 7 / intra 4x4 mode 8-9 penalty (all format mode)" line.long 0x1C "VENC_SWREG71,VENC JPEG luma quantization 8/base address for segmentation map register" hexmask.long 0x1C 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 8 / Base address for segmentation map (all format mode)" line.long 0x20 "VENC_SWREG72,VENC JPEG luma quantization 9/segment1 parameter register" hexmask.long 0x20 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 9 / segment1 parameter (all format mode)" line.long 0x24 "VENC_SWREG73,VENC JPEG luma quantization 10/segment1 parameter register" hexmask.long 0x24 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 10 / segment1 parameter (all format mode)" line.long 0x28 "VENC_SWREG74,VENC JPEG luma quantization 11/segment1 parameter register" hexmask.long 0x28 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 11 / segment1 parameter (all format mode)" line.long 0x2C "VENC_SWREG75,VENC JPEG luma quantization 12/segment1 parameter register" hexmask.long 0x2C 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 12 / segment1 parameter (all format mode)" line.long 0x30 "VENC_SWREG76,VENC JPEG luma quantization 13/segment1 parameter register" hexmask.long 0x30 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 13 / segment1 parameter (all format mode)" line.long 0x34 "VENC_SWREG77,VENC JPEG luma quantization 14/segment1 parameter register" hexmask.long 0x34 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 14 / segment1 parameter (all format mode)" line.long 0x38 "VENC_SWREG78,VENC JPEG luma quantization 15/segment1 parameter register" hexmask.long 0x38 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 15 / segment1 parameter (all format mode)" line.long 0x3C "VENC_SWREG79,VENC JPEG luma quantization 16/segment2 parameter register" hexmask.long 0x3C 0.--31. 1. "SWREG_FIELD,JPEG luma quantization 16 / segment2 parameter (all format mode)" line.long 0x40 "VENC_SWREG80,VENC JPEG chroma quantization 1/segment2 parameter register" hexmask.long 0x40 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 1 / segment2 parameter (all format mode)" line.long 0x44 "VENC_SWREG81,VENC JPEG chroma quantization 2/segment2 parameter register" hexmask.long 0x44 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 2 / segment2 parameter (all format mode)" line.long 0x48 "VENC_SWREG82,VENC JPEG chroma quantization 3/segment2 parameter register" hexmask.long 0x48 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 3 / segment2 parameter (all format mode)" line.long 0x4C "VENC_SWREG83,VENC JPEG chroma quantization 4/segment2 parameter register" hexmask.long 0x4C 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 4 / segment2 parameter (all format mode)" line.long 0x50 "VENC_SWREG84,VENC JPEG chroma quantization 5/segment2 parameter register" hexmask.long 0x50 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 5 / segment2 parameter (all format mode)" line.long 0x54 "VENC_SWREG85,VENC JPEG chroma quantization 6/segment2 parameter register" hexmask.long 0x54 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 6 / segment2 parameter (all format mode)" line.long 0x58 "VENC_SWREG86,VENC JPEG chroma quantization 7/segment2 parameter register" hexmask.long 0x58 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 7 / segment2 parameter (all format mode)" line.long 0x5C "VENC_SWREG87,VENC JPEG chroma quantization 8/segment2 parameter register" hexmask.long 0x5C 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 8 / segment2 parameter (all format mode)" line.long 0x60 "VENC_SWREG88,VENC JPEG chroma quantization 9/segment3 parameter register" hexmask.long 0x60 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 9 / segment3 parameter (all format mode)" line.long 0x64 "VENC_SWREG89,VENC JPEG chroma quantization 10/segment3 parameter register" hexmask.long 0x64 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 10 / segment3 parameter (all format mode)" line.long 0x68 "VENC_SWREG90,VENC JPEG chroma quantization 11/segment3 parameter register" hexmask.long 0x68 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 11 / segment3 parameter (all format mode)" line.long 0x6C "VENC_SWREG91,VENC JPEG chroma quantization 12/segment3 parameter register" hexmask.long 0x6C 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 12 / segment3 parameter (all format mode)" line.long 0x70 "VENC_SWREG92,VENC JPEG chroma quantization 13/segment3 parameter register" hexmask.long 0x70 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 13 / segment3 parameter (all format mode)" line.long 0x74 "VENC_SWREG93,VENC JPEG chroma quantization 14/segment3 parameter register" hexmask.long 0x74 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 14 / segment3 parameter (all format mode)" line.long 0x78 "VENC_SWREG94,VENC JPEG chroma quantization 15/segment3 parameter register" hexmask.long 0x78 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 15 / segment3 parameter (all format mode)" line.long 0x7C "VENC_SWREG95,VENC JPEG chroma quantization 16/segment3 parameter register" hexmask.long 0x7C 0.--31. 1. "SWREG_FIELD,JPEG chroma quantization 16 / segment3 parameter (all format mode)" wgroup.long 0x180++0xFF line.long 0x0 "VENC_SWREG96,VENC DMV 4p/1p penalty values 0-3 register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values 0-3 (all format mode)" line.long 0x4 "VENC_SWREG97,VENC DMV 4p/1p penalty values 4-7 register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values 4-7 (all format mode)" line.long 0x8 "VENC_SWREG98,VENC DMV 4p/1p penalty values register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0xC "VENC_SWREG99,VENC DMV 4p/1p penalty values register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x10 "VENC_SWREG100,VENC DMV 4p/1p penalty values register" hexmask.long 0x10 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x14 "VENC_SWREG101,VENC DMV 4p/1p penalty values register" hexmask.long 0x14 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x18 "VENC_SWREG102,VENC DMV 4p/1p penalty values register" hexmask.long 0x18 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x1C "VENC_SWREG103,VENC DMV 4p/1p penalty values register" hexmask.long 0x1C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x20 "VENC_SWREG104,VENC DMV 4p/1p penalty values register" hexmask.long 0x20 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x24 "VENC_SWREG105,VENC DMV 4p/1p penalty values register" hexmask.long 0x24 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x28 "VENC_SWREG106,VENC DMV 4p/1p penalty values register" hexmask.long 0x28 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x2C "VENC_SWREG107,VENC DMV 4p/1p penalty values register" hexmask.long 0x2C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x30 "VENC_SWREG108,VENC DMV 4p/1p penalty values register" hexmask.long 0x30 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x34 "VENC_SWREG109,VENC DMV 4p/1p penalty values register" hexmask.long 0x34 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x38 "VENC_SWREG110,VENC DMV 4p/1p penalty values register" hexmask.long 0x38 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x3C "VENC_SWREG111,VENC DMV 4p/1p penalty values register" hexmask.long 0x3C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x40 "VENC_SWREG112,VENC DMV 4p/1p penalty values register" hexmask.long 0x40 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x44 "VENC_SWREG113,VENC DMV 4p/1p penalty values register" hexmask.long 0x44 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x48 "VENC_SWREG114,VENC DMV 4p/1p penalty values register" hexmask.long 0x48 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x4C "VENC_SWREG115,VENC DMV 4p/1p penalty values register" hexmask.long 0x4C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x50 "VENC_SWREG116,VENC DMV 4p/1p penalty values register" hexmask.long 0x50 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x54 "VENC_SWREG117,VENC DMV 4p/1p penalty values register" hexmask.long 0x54 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x58 "VENC_SWREG118,VENC DMV 4p/1p penalty values register" hexmask.long 0x58 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x5C "VENC_SWREG119,VENC DMV 4p/1p penalty values register" hexmask.long 0x5C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x60 "VENC_SWREG120,VENC DMV 4p/1p penalty values register" hexmask.long 0x60 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x64 "VENC_SWREG121,VENC DMV 4p/1p penalty values register" hexmask.long 0x64 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x68 "VENC_SWREG122,VENC DMV 4p/1p penalty values register" hexmask.long 0x68 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x6C "VENC_SWREG123,VENC DMV 4p/1p penalty values register" hexmask.long 0x6C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x70 "VENC_SWREG124,VENC DMV 4p/1p penalty values register" hexmask.long 0x70 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x74 "VENC_SWREG125,VENC DMV 4p/1p penalty values register" hexmask.long 0x74 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x78 "VENC_SWREG126,VENC DMV 4p/1p penalty values register" hexmask.long 0x78 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values (all format mode)" line.long 0x7C "VENC_SWREG127,VENC DMV 4p/1p penalty values 124-127 register" hexmask.long 0x7C 0.--31. 1. "SWREG_FIELD,DMV 4p/1p penalty values 124-127 (all format mode)" line.long 0x80 "VENC_SWREG128,VENC DMV qpel penalty values 0-3 register" hexmask.long 0x80 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values 0-3 (all format mode)" line.long 0x84 "VENC_SWREG129,VENC DMV qpel penalty values 4-7 register" hexmask.long 0x84 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values 4-7 (all format mode)" line.long 0x88 "VENC_SWREG130,VENC DMV qpel penalty values register" hexmask.long 0x88 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0x8C "VENC_SWREG131,VENC DMV qpel penalty values register" hexmask.long 0x8C 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0x90 "VENC_SWREG132,VENC DMV qpel penalty values register" hexmask.long 0x90 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0x94 "VENC_SWREG133,VENC DMV qpel penalty values register" hexmask.long 0x94 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0x98 "VENC_SWREG134,VENC DMV qpel penalty values register" hexmask.long 0x98 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0x9C "VENC_SWREG135,VENC DMV qpel penalty values register" hexmask.long 0x9C 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xA0 "VENC_SWREG136,VENC DMV qpel penalty values register" hexmask.long 0xA0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xA4 "VENC_SWREG137,VENC DMV qpel penalty values register" hexmask.long 0xA4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xA8 "VENC_SWREG138,VENC DMV qpel penalty values register" hexmask.long 0xA8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xAC "VENC_SWREG139,VENC DMV qpel penalty values register" hexmask.long 0xAC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xB0 "VENC_SWREG140,VENC DMV qpel penalty values register" hexmask.long 0xB0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xB4 "VENC_SWREG141,VENC DMV qpel penalty values register" hexmask.long 0xB4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xB8 "VENC_SWREG142,VENC DMV qpel penalty values register" hexmask.long 0xB8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xBC "VENC_SWREG143,VENC DMV qpel penalty values register" hexmask.long 0xBC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xC0 "VENC_SWREG144,VENC DMV qpel penalty values register" hexmask.long 0xC0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xC4 "VENC_SWREG145,VENC DMV qpel penalty values register" hexmask.long 0xC4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xC8 "VENC_SWREG146,VENC DMV qpel penalty values register" hexmask.long 0xC8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xCC "VENC_SWREG147,VENC DMV qpel penalty values register" hexmask.long 0xCC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xD0 "VENC_SWREG148,VENC DMV qpel penalty values register" hexmask.long 0xD0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xD4 "VENC_SWREG149,VENC DMV qpel penalty values register" hexmask.long 0xD4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xD8 "VENC_SWREG150,VENC DMV qpel penalty values register" hexmask.long 0xD8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xDC "VENC_SWREG151,VENC DMV qpel penalty values register" hexmask.long 0xDC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xE0 "VENC_SWREG152,VENC DMV qpel penalty values register" hexmask.long 0xE0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xE4 "VENC_SWREG153,VENC DMV qpel penalty values register" hexmask.long 0xE4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xE8 "VENC_SWREG154,VENC DMV qpel penalty values register" hexmask.long 0xE8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xEC "VENC_SWREG155,VENC DMV qpel penalty values register" hexmask.long 0xEC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xF0 "VENC_SWREG156,VENC DMV qpel penalty values register" hexmask.long 0xF0 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xF4 "VENC_SWREG157,VENC DMV qpel penalty values register" hexmask.long 0xF4 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xF8 "VENC_SWREG158,VENC DMV qpel penalty values register" hexmask.long 0xF8 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values (all format mode)" line.long 0xFC "VENC_SWREG159,VENC DMV qpel penalty values 124-127 register" hexmask.long 0xFC 0.--31. 1. "SWREG_FIELD,DMV qpel penalty values 124-127 (all format mode)" group.long 0x39C++0xB line.long 0x0 "VENC_SWREG231,VENC base address for output of down-scaled encoder image in YUYV 4:2:2 format register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Base address for output of down-scaled encoder image in YUYV 4:2:2 format (all format mode)" line.long 0x4 "VENC_SWREG232,VENC scaling control register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,Scaling control (all format mode)" line.long 0x8 "VENC_SWREG233,VENC scaling control register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,Scaling control (all format mode)" group.long 0x3B0++0xB line.long 0x0 "VENC_SWREG236,VENC squared error output calculated for 13x13 pixels per macroblock register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Squared error output calculated for 13x13 pixels per macroblock (all format mode)" line.long 0x4 "VENC_SWREG237,VENC MAD 2 control and output register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,MAD 2 control and output (all format mode)" line.long 0x8 "VENC_SWREG238,VENC MAD 3 control and output register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,MAD 3 control and output (all format mode)" group.long 0x400++0x8F line.long 0x0 "VENC_SWREG256,VENC segment 1: intra 16x16 mode 0-2 penalty register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,segment 1: intra 16x16 mode 0-2 penalty (all format mode)" line.long 0x4 "VENC_SWREG257,VENC segment 1: intra 16x16 mode 3. intra 4x4 0-1 penalty register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,segment 1: intra 16x16 mode 3 and intra 4x4 0-1 penalty (all format mode)" line.long 0x8 "VENC_SWREG258,VENC segment 1: intra 4x4 mode 2-4 penalty register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,segment 1: intra 4x4 mode 2-4 penalty (all format mode)" line.long 0xC "VENC_SWREG259,VENC segment 1: intra 4x4 mode 5-7 penalty register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,segment 1: intra 4x4 mode 5-7 penalty (all format mode)" line.long 0x10 "VENC_SWREG260,VENC segment 1: intra 4x4 mode 8-9 penalty. previous mode favor for H.264 register" hexmask.long 0x10 0.--31. 1. "SWREG_FIELD,segment 1: intra 4x4 mode 8-9 penalty previous mode favor for H.264 (all format mode)" line.long 0x14 "VENC_SWREG261,VENC segment 1: bit cost of inter type. intra 16x16 mode favor register" hexmask.long 0x14 0.--31. 1. "SWREG_FIELD,segment 1: Bit cost of inter type intra 16x16 mode favor (all format mode)" line.long 0x18 "VENC_SWREG262,VENC segment 1: inter MB mode favor. skip mode penalty. penalty value for 2nd reference frame register" hexmask.long 0x18 0.--31. 1. "SWREG_FIELD,segment 1: inter MB mode favor skip mode penalty penalty value for second reference frame (all format mode)" line.long 0x1C "VENC_SWREG263,VENC segment 1: penalty value register" hexmask.long 0x1C 0.--31. 1. "SWREG_FIELD,segment 1: penalty value (all format mode)" line.long 0x20 "VENC_SWREG264,VENC segment 1: penalty value register" hexmask.long 0x20 0.--31. 1. "SWREG_FIELD,segment 1: penalty value (all format mode)" line.long 0x24 "VENC_SWREG265,VENC segment 1: deadzone rate multiplier for plane 0-1 register" hexmask.long 0x24 0.--31. 1. "SWREG_FIELD,segment 1: Deadzone rate multiplier for plane 0-1 (all format mode)" line.long 0x28 "VENC_SWREG266,VENC segment 1: deadzone rate multiplier for plane 2-3 register" hexmask.long 0x28 0.--31. 1. "SWREG_FIELD,segment 1: Deadzone rate multiplier for plane 2-3 (all format mode)" line.long 0x2C "VENC_SWREG267,VENC segment 1: deadzone rate for macroblock skip token 0-1. dmv penalty coefficient register" hexmask.long 0x2C 0.--31. 1. "SWREG_FIELD,segment 1: Deadzone rate for macroblock skip token 0-1 dmv penalty coefficient (all format mode)" line.long 0x30 "VENC_SWREG268,VENC segment 2: intra 16x16 mode 0-2 penalty register" hexmask.long 0x30 0.--31. 1. "SWREG_FIELD,segment 2: intra 16x16 mode 0-2 penalty (all format mode)" line.long 0x34 "VENC_SWREG269,VENC segment 2: intra 16x16 mode 3 penalty. intra 4x4 mode 0-1 penalty register" hexmask.long 0x34 0.--31. 1. "SWREG_FIELD,segment 2: intra 16x16 mode 3 penalty intra 4x4 mode 0-1 penalty (all format mode)" line.long 0x38 "VENC_SWREG270,VENC segment 2: intra 4x4 mode 2-4 penalty register" hexmask.long 0x38 0.--31. 1. "SWREG_FIELD,segment 2: intra 4x4 mode 2-4 penalty (all format mode)" line.long 0x3C "VENC_SWREG271,VENC segment 2: intra 4x4 mode 5-7 penalty register" hexmask.long 0x3C 0.--31. 1. "SWREG_FIELD,segment 2: intra 4x4 mode 5-7 penalty (all format mode)" line.long 0x40 "VENC_SWREG272,VENC segment 2: intra 4x4 mode 8-9 penalty. intra 4x4 previous mode favor for H.264 register" hexmask.long 0x40 0.--31. 1. "SWREG_FIELD,segment 2: intra 4x4 mode 8-9 penalty intra 4x4 previous mode favor for H.264 (all format mode)" line.long 0x44 "VENC_SWREG273,VENC segment 2: bit cost of inter type. intra 16x16 mode favor register" hexmask.long 0x44 0.--31. 1. "SWREG_FIELD,segment 2: Bit cost of inter type intra 16x16 mode favor (all format mode)" line.long 0x48 "VENC_SWREG274,VENC segment 2: inter MB mode favor. skip mode penalty. penalty value register" hexmask.long 0x48 0.--31. 1. "SWREG_FIELD,segment 2: inter MB mode favor skip mode penalty panelty value (all format mode)" line.long 0x4C "VENC_SWREG275,VENC segment 2: penalty value register" hexmask.long 0x4C 0.--31. 1. "SWREG_FIELD,segment 2: penalty value (all format mode)" line.long 0x50 "VENC_SWREG276,VENC segment 2: penalty value register" hexmask.long 0x50 0.--31. 1. "SWREG_FIELD,segment 2: penalty value (all format mode)" line.long 0x54 "VENC_SWREG277,VENC segment 2: deadzone rate multiplier for plane 0-1 register" hexmask.long 0x54 0.--31. 1. "SWREG_FIELD,segment 2: Deadzone rate multiplier for plane 0-1 (all format mode)" line.long 0x58 "VENC_SWREG278,VENC segment 2: deadzone rate multiplier for plane 2-3 register" hexmask.long 0x58 0.--31. 1. "SWREG_FIELD,segment 2: Deadzone rate multiplier for plane 2-3 (all format mode)" line.long 0x5C "VENC_SWREG279,VENC segment 2: deadzone rate for macroblock skip token 0-1. dmv penalty coefficient register" hexmask.long 0x5C 0.--31. 1. "SWREG_FIELD,segment 2: Deadzone rate for macroblock skip token 0-1 dmv penalty coefficient (all format mode)" line.long 0x60 "VENC_SWREG280,VENC segment 3: intra 16x16 mode 0-2 penalty register" hexmask.long 0x60 0.--31. 1. "SWREG_FIELD,segment 3: intra 16x16 mode 0-2 penalty (all format mode)" line.long 0x64 "VENC_SWREG281,VENC segment 3: intra 16x16 mode 3 penalty. intra 4x4 mode 0-1 penalty register" hexmask.long 0x64 0.--31. 1. "SWREG_FIELD,segment 3: intra 16x16 mode 3 penalty intra 4x4 mode 0-1 penalty (all format mode)" line.long 0x68 "VENC_SWREG282,VENC segment 3: intra 4x4 mode 2-4 penalty register" hexmask.long 0x68 0.--31. 1. "SWREG_FIELD,segment 3: intra 4x4 mode 2-4 penalty (all format mode)" line.long 0x6C "VENC_SWREG283,VENC segment 3: intra 4x4 mode 5-7 penalty register" hexmask.long 0x6C 0.--31. 1. "SWREG_FIELD,segment 3: intra 4x4 mode 5-7 penalty (all format mode)" line.long 0x70 "VENC_SWREG284,VENC segment 3: intra 4x4 mode 8-9 penalty. intra 4x4 previous mode favor for H.264 register" hexmask.long 0x70 0.--31. 1. "SWREG_FIELD,segment 3: intra 4x4 mode 8-9 penalty intra 4x4 previous mode favor for H.264 (all format mode)" line.long 0x74 "VENC_SWREG285,VENC segment 3: bit cost of inter type. intra 16x16 mode favor register" hexmask.long 0x74 0.--31. 1. "SWREG_FIELD,segment 3: Bit cost of inter type intra 16x16 mode favor (all format mode)" line.long 0x78 "VENC_SWREG286,VENC segment 3: inter MB mode favor in intra/inter selection. inter MB mode favor. penalty value for second reference frame register" hexmask.long 0x78 0.--31. 1. "SWREG_FIELD,segment 3: inter MB mode favor in intra/inter selection inter MB mode favor penalty value for second reference frame (all format mode)" line.long 0x7C "VENC_SWREG287,VENC segment 3: penalty value register" hexmask.long 0x7C 0.--31. 1. "SWREG_FIELD,segment 3: penalty value (all format mode)" line.long 0x80 "VENC_SWREG288,VENC segment 3: penalty value register" hexmask.long 0x80 0.--31. 1. "SWREG_FIELD,segment 3: penalty value (all format mode)" line.long 0x84 "VENC_SWREG289,VENC segment 3: deadzone rate multiplier for plane 0-1 register" hexmask.long 0x84 0.--31. 1. "SWREG_FIELD,segment 3: Deadzone rate multiplier for plane 0-1 (all format mode)" line.long 0x88 "VENC_SWREG290,VENC segment 3: deadzone rate multiplier for plane 2-3 register" hexmask.long 0x88 0.--31. 1. "SWREG_FIELD,segment 3: Deadzone rate multiplier for plane 2-3 (all format mode)" line.long 0x8C "VENC_SWREG291,VENC segment 3: deadzone rate for macroblock skip token 0-1. dmv penalty coefficient register" hexmask.long 0x8C 0.--31. 1. "SWREG_FIELD,segment 3: Deadzone rate for macroblock skip token 0-1 dmv penalty coefficient (all format mode)" group.long 0x498++0x7 line.long 0x0 "VENC_SWREG294,VENC Mb boost register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Mb boost (all format mode)" line.long 0x4 "VENC_SWREG295,VENC variance control. Pskop conding mode register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,Variance control Pskop conding mode (all format mode)" rgroup.long 0x4A0++0x3 line.long 0x0 "VENC_SWREG296,VENC synthesis configuration register encoder 1 read only register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Synthesis configuration register encoder 1 (read only) (all format mode)" group.long 0x4A4++0x24F line.long 0x0 "VENC_SWREG297,VENC MBRC control register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,MBRC control (all format mode)" line.long 0x4 "VENC_SWREG298,VENC segment 4: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,segment 4: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x8 "VENC_SWREG299,VENC segment 4: skip mode penalty. inter MB mode favor register" hexmask.long 0x8 0.--31. 1. "SWREG_FIELD,segment 4: skip mode penalty inter MB mode favor (all format mode)" line.long 0xC "VENC_SWREG300,VENC segment 4: penalty value register" hexmask.long 0xC 0.--31. 1. "SWREG_FIELD,segment 4: penalty value (all format mode)" line.long 0x10 "VENC_SWREG301,VENC segment 4: penalty value register" hexmask.long 0x10 0.--31. 1. "SWREG_FIELD,segment 4: penalty value (all format mode)" line.long 0x14 "VENC_SWREG302,VENC segment 5: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x14 0.--31. 1. "SWREG_FIELD,segment 5: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x18 "VENC_SWREG303,VENC segment 5: skip mode penalty. inter MB mode favor register" hexmask.long 0x18 0.--31. 1. "SWREG_FIELD,segment 5: skip mode penalty inter MB mode favor (all format mode)" line.long 0x1C "VENC_SWREG304,VENC segment 5: penalty value register" hexmask.long 0x1C 0.--31. 1. "SWREG_FIELD,segment 5: penalty value (all format mode)" line.long 0x20 "VENC_SWREG305,VENC segment 5: penalty value register" hexmask.long 0x20 0.--31. 1. "SWREG_FIELD,segment 5: penalty value (all format mode)" line.long 0x24 "VENC_SWREG306,VENC segment 6: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x24 0.--31. 1. "SWREG_FIELD,segment 6: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x28 "VENC_SWREG307,VENC segment 6: skip mode penalty. inter MB mode favor register" hexmask.long 0x28 0.--31. 1. "SWREG_FIELD,segment 6: skip mode penalty inter MB mode favor (all format mode)" line.long 0x2C "VENC_SWREG308,VENC segment 6: penalty value register" hexmask.long 0x2C 0.--31. 1. "SWREG_FIELD,segment 6: penalty value (all format mode)" line.long 0x30 "VENC_SWREG309,VENC segment 6: penalty value register" hexmask.long 0x30 0.--31. 1. "SWREG_FIELD,segment 6: penalty value (all format mode)" line.long 0x34 "VENC_SWREG310,VENC segment 7: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x34 0.--31. 1. "SWREG_FIELD,segment 7: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x38 "VENC_SWREG311,VENC segment 7: skip mode penalty. inter MB mode favor register" hexmask.long 0x38 0.--31. 1. "SWREG_FIELD,segment 7: skip mode penalty inter MB mode favor (all format mode)" line.long 0x3C "VENC_SWREG312,VENC segment 7: penalty value register" hexmask.long 0x3C 0.--31. 1. "SWREG_FIELD,segment 7: penalty value (all format mode)" line.long 0x40 "VENC_SWREG313,VENC segment 7: penalty value register" hexmask.long 0x40 0.--31. 1. "SWREG_FIELD,segment 7: penalty value (all format mode)" line.long 0x44 "VENC_SWREG314,VENC segment 8: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x44 0.--31. 1. "SWREG_FIELD,segment 8: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x48 "VENC_SWREG315,VENC segment 8: skip mode penalty. inter MB mode favor register" hexmask.long 0x48 0.--31. 1. "SWREG_FIELD,segment 8: skip mode penalty inter MB mode favor (all format mode)" line.long 0x4C "VENC_SWREG316,VENC segment 8: penalty value register" hexmask.long 0x4C 0.--31. 1. "SWREG_FIELD,segment 8: penalty value (all format mode)" line.long 0x50 "VENC_SWREG317,VENC segment 8: penalty value register" hexmask.long 0x50 0.--31. 1. "SWREG_FIELD,segment 8: penalty value (all format mode)" line.long 0x54 "VENC_SWREG318,VENC segment 9: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x54 0.--31. 1. "SWREG_FIELD,segment 9: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x58 "VENC_SWREG319,VENC segment 9: skip mode penalty. inter MB mode favor register" hexmask.long 0x58 0.--31. 1. "SWREG_FIELD,segment 9: skip mode penalty inter MB mode favor (all format mode)" line.long 0x5C "VENC_SWREG320,VENC segment 9: penalty value register" hexmask.long 0x5C 0.--31. 1. "SWREG_FIELD,segment 9: penalty value (all format mode)" line.long 0x60 "VENC_SWREG321,VENC segment 9: penalty value register" hexmask.long 0x60 0.--31. 1. "SWREG_FIELD,segment 9: penalty value (all format mode)" line.long 0x64 "VENC_SWREG322,VENC segment 10: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x64 0.--31. 1. "SWREG_FIELD,segment 10: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x68 "VENC_SWREG323,VENC segment 10: skip mode penalty. inter MB mode favor register" hexmask.long 0x68 0.--31. 1. "SWREG_FIELD,segment 10: skip mode penalty inter MB mode favor (all format mode)" line.long 0x6C "VENC_SWREG324,VENC segment 10: penalty value register" hexmask.long 0x6C 0.--31. 1. "SWREG_FIELD,segment 10: penalty value (all format mode)" line.long 0x70 "VENC_SWREG325,VENC segment 10: penalty value register" hexmask.long 0x70 0.--31. 1. "SWREG_FIELD,segment 10: penalty value (all format mode)" line.long 0x74 "VENC_SWREG326,VENC segment 11: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x74 0.--31. 1. "SWREG_FIELD,segment 11: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x78 "VENC_SWREG327,VENC segment 11: skip mode penalty. inter MB mode favor register" hexmask.long 0x78 0.--31. 1. "SWREG_FIELD,segment 11: skip mode penalty inter MB mode favor (all format mode)" line.long 0x7C "VENC_SWREG328,VENC segment 11: penalty value register" hexmask.long 0x7C 0.--31. 1. "SWREG_FIELD,segment 11: penalty value (all format mode)" line.long 0x80 "VENC_SWREG329,VENC segment 11: penalty value register" hexmask.long 0x80 0.--31. 1. "SWREG_FIELD,segment 11: penalty value (all format mode)" line.long 0x84 "VENC_SWREG330,VENC segment 12: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x84 0.--31. 1. "SWREG_FIELD,segment 12: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x88 "VENC_SWREG331,VENC segment 12: skip mode penalty. inter MB mode favor register" hexmask.long 0x88 0.--31. 1. "SWREG_FIELD,segment 12: skip mode penalty inter MB mode favor (all format mode)" line.long 0x8C "VENC_SWREG332,VENC segment 12: penalty value register" hexmask.long 0x8C 0.--31. 1. "SWREG_FIELD,segment 12: penalty value (all format mode)" line.long 0x90 "VENC_SWREG333,VENC segment 12: penalty value register" hexmask.long 0x90 0.--31. 1. "SWREG_FIELD,segment 12: penalty value (all format mode)" line.long 0x94 "VENC_SWREG334,VENC segment 13: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x94 0.--31. 1. "SWREG_FIELD,segment 13: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x98 "VENC_SWREG335,VENC segment 13: skip mode penalty. inter MB mode favor register" hexmask.long 0x98 0.--31. 1. "SWREG_FIELD,segment 13: skip mode penalty inter MB mode favor (all format mode)" line.long 0x9C "VENC_SWREG336,VENC segment 13: penalty value register" hexmask.long 0x9C 0.--31. 1. "SWREG_FIELD,segment 13: penalty value (all format mode)" line.long 0xA0 "VENC_SWREG337,VENC segment 13: penalty value register" hexmask.long 0xA0 0.--31. 1. "SWREG_FIELD,segment 13: penalty value (all format mode)" line.long 0xA4 "VENC_SWREG338,VENC segment 14: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xA4 0.--31. 1. "SWREG_FIELD,segment 14: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xA8 "VENC_SWREG339,VENC segment 14: skip mode penalty. inter MB mode favor register" hexmask.long 0xA8 0.--31. 1. "SWREG_FIELD,segment 14: skip mode penalty inter MB mode favor (all format mode)" line.long 0xAC "VENC_SWREG340,VENC segment 14: penalty value register" hexmask.long 0xAC 0.--31. 1. "SWREG_FIELD,segment 14: penalty value (all format mode)" line.long 0xB0 "VENC_SWREG341,VENC segment 14: penalty value register" hexmask.long 0xB0 0.--31. 1. "SWREG_FIELD,segment 14: penalty value (all format mode)" line.long 0xB4 "VENC_SWREG342,VENC segment 15: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xB4 0.--31. 1. "SWREG_FIELD,segment 15: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xB8 "VENC_SWREG343,VENC segment 15: skip mode penalty. inter MB mode favor register" hexmask.long 0xB8 0.--31. 1. "SWREG_FIELD,segment 15: skip mode penalty inter MB mode favor (all format mode)" line.long 0xBC "VENC_SWREG344,VENC segment 15: penalty value register" hexmask.long 0xBC 0.--31. 1. "SWREG_FIELD,segment 15: penalty value (all format mode)" line.long 0xC0 "VENC_SWREG345,VENC segment 15: penalty value register" hexmask.long 0xC0 0.--31. 1. "SWREG_FIELD,segment 15: penalty value (all format mode)" line.long 0xC4 "VENC_SWREG346,VENC segment 16: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xC4 0.--31. 1. "SWREG_FIELD,segment 16: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xC8 "VENC_SWREG347,VENC segment 16: skip mode penalty. inter MB mode favor register" hexmask.long 0xC8 0.--31. 1. "SWREG_FIELD,segment 16: skip mode penalty inter MB mode favor (all format mode)" line.long 0xCC "VENC_SWREG348,VENC segment 16: penalty value register" hexmask.long 0xCC 0.--31. 1. "SWREG_FIELD,segment 16: penalty value (all format mode)" line.long 0xD0 "VENC_SWREG349,VENC segment 16: penalty value register" hexmask.long 0xD0 0.--31. 1. "SWREG_FIELD,segment 16: penalty value (all format mode)" line.long 0xD4 "VENC_SWREG350,VENC segment 17: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xD4 0.--31. 1. "SWREG_FIELD,segment 17: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xD8 "VENC_SWREG351,VENC segment 17: skip mode penalty. inter MB mode favor register" hexmask.long 0xD8 0.--31. 1. "SWREG_FIELD,segment 17: skip mode penalty inter MB mode favor (all format mode)" line.long 0xDC "VENC_SWREG352,VENC segment 17: penalty value register" hexmask.long 0xDC 0.--31. 1. "SWREG_FIELD,segment 17: penalty value (all format mode)" line.long 0xE0 "VENC_SWREG353,VENC segment 17: penalty value register" hexmask.long 0xE0 0.--31. 1. "SWREG_FIELD,segment 17: penalty value (all format mode)" line.long 0xE4 "VENC_SWREG354,VENC segment 18: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xE4 0.--31. 1. "SWREG_FIELD,segment 18: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xE8 "VENC_SWREG355,VENC segment 18: skip mode penalty. inter MB mode favor register" hexmask.long 0xE8 0.--31. 1. "SWREG_FIELD,segment 18: skip mode penalty inter MB mode favor (all format mode)" line.long 0xEC "VENC_SWREG356,VENC segment 18: penalty value register" hexmask.long 0xEC 0.--31. 1. "SWREG_FIELD,segment 18: penalty value (all format mode)" line.long 0xF0 "VENC_SWREG357,VENC segment 18: penalty value register" hexmask.long 0xF0 0.--31. 1. "SWREG_FIELD,segment 18: penalty value (all format mode)" line.long 0xF4 "VENC_SWREG358,VENC segment 19: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0xF4 0.--31. 1. "SWREG_FIELD,segment 19: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0xF8 "VENC_SWREG359,VENC segment 19: skip mode penalty. inter MB mode favor register" hexmask.long 0xF8 0.--31. 1. "SWREG_FIELD,segment 19: skip mode penalty inter MB mode favor (all format mode)" line.long 0xFC "VENC_SWREG360,VENC segment 19: penalty value register" hexmask.long 0xFC 0.--31. 1. "SWREG_FIELD,segment 19: penalty value (all format mode)" line.long 0x100 "VENC_SWREG361,VENC segment 19: penalty value register" hexmask.long 0x100 0.--31. 1. "SWREG_FIELD,segment 19: penalty value (all format mode)" line.long 0x104 "VENC_SWREG362,VENC segment 20: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x104 0.--31. 1. "SWREG_FIELD,segment 20: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x108 "VENC_SWREG363,VENC segment 20: skip mode penalty. inter MB mode favor register" hexmask.long 0x108 0.--31. 1. "SWREG_FIELD,segment 20: skip mode penalty inter MB mode favor (all format mode)" line.long 0x10C "VENC_SWREG364,VENC segment 20: penalty value register" hexmask.long 0x10C 0.--31. 1. "SWREG_FIELD,segment 20: penalty value (all format mode)" line.long 0x110 "VENC_SWREG365,VENC segment 20: penalty value register" hexmask.long 0x110 0.--31. 1. "SWREG_FIELD,segment 20: penalty value (all format mode)" line.long 0x114 "VENC_SWREG366,VENC segment 21: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x114 0.--31. 1. "SWREG_FIELD,segment 21: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x118 "VENC_SWREG367,VENC segment 21: skip mode penalty. inter MB mode favor register" hexmask.long 0x118 0.--31. 1. "SWREG_FIELD,segment 21: skip mode penalty inter MB mode favor (all format mode)" line.long 0x11C "VENC_SWREG368,VENC segment 21: penalty value register" hexmask.long 0x11C 0.--31. 1. "SWREG_FIELD,segment 21: penalty value (all format mode)" line.long 0x120 "VENC_SWREG369,VENC segment 21: penalty value register" hexmask.long 0x120 0.--31. 1. "SWREG_FIELD,segment 21: penalty value (all format mode)" line.long 0x124 "VENC_SWREG370,VENC segment 22: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x124 0.--31. 1. "SWREG_FIELD,segment 22: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x128 "VENC_SWREG371,VENC segment 22: skip mode penalty. inter MB mode favor register" hexmask.long 0x128 0.--31. 1. "SWREG_FIELD,segment 22: skip mode penalty inter MB mode favor (all format mode)" line.long 0x12C "VENC_SWREG372,VENC segment 22: penalty value register" hexmask.long 0x12C 0.--31. 1. "SWREG_FIELD,segment 22: penalty value (all format mode)" line.long 0x130 "VENC_SWREG373,VENC segment 22: penalty value register" hexmask.long 0x130 0.--31. 1. "SWREG_FIELD,segment 22: penalty value (all format mode)" line.long 0x134 "VENC_SWREG374,VENC segment 23: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x134 0.--31. 1. "SWREG_FIELD,segment 23: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x138 "VENC_SWREG375,VENC segment 23: skip mode penalty. inter MB mode favor register" hexmask.long 0x138 0.--31. 1. "SWREG_FIELD,segment 23: skip mode penalty inter MB mode favor (all format mode)" line.long 0x13C "VENC_SWREG376,VENC segment 23: penalty value register" hexmask.long 0x13C 0.--31. 1. "SWREG_FIELD,segment 23: penalty value (all format mode)" line.long 0x140 "VENC_SWREG377,VENC segment 23: penalty value register" hexmask.long 0x140 0.--31. 1. "SWREG_FIELD,segment 23: penalty value (all format mode)" line.long 0x144 "VENC_SWREG378,VENC segment 24: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x144 0.--31. 1. "SWREG_FIELD,segment 24: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x148 "VENC_SWREG379,VENC segment 24: skip mode penalty. inter MB mode favor register" hexmask.long 0x148 0.--31. 1. "SWREG_FIELD,segment 24: skip mode penalty inter MB mode favor (all format mode)" line.long 0x14C "VENC_SWREG380,VENC segment 24: penalty value register" hexmask.long 0x14C 0.--31. 1. "SWREG_FIELD,segment 24: penalty value (all format mode)" line.long 0x150 "VENC_SWREG381,VENC segment 24: penalty value register" hexmask.long 0x150 0.--31. 1. "SWREG_FIELD,segment 24: penalty value (all format mode)" line.long 0x154 "VENC_SWREG382,VENC segment 25: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x154 0.--31. 1. "SWREG_FIELD,segment 25: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x158 "VENC_SWREG383,VENC segment 25: skip mode penalty. inter MB mode favor register" hexmask.long 0x158 0.--31. 1. "SWREG_FIELD,segment 25: skip mode penalty inter MB mode favor (all format mode)" line.long 0x15C "VENC_SWREG384,VENC segment 25: penalty value register" hexmask.long 0x15C 0.--31. 1. "SWREG_FIELD,segment 25: penalty value (all format mode)" line.long 0x160 "VENC_SWREG385,VENC segment 25: penalty value register" hexmask.long 0x160 0.--31. 1. "SWREG_FIELD,segment 25: penalty value (all format mode)" line.long 0x164 "VENC_SWREG386,VENC segment 26: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x164 0.--31. 1. "SWREG_FIELD,segment 26: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x168 "VENC_SWREG387,VENC segment 26: skip mode penalty. inter MB mode favor register" hexmask.long 0x168 0.--31. 1. "SWREG_FIELD,segment 26: skip mode penalty inter MB mode favor (all format mode)" line.long 0x16C "VENC_SWREG388,VENC segment 26: penalty value register" hexmask.long 0x16C 0.--31. 1. "SWREG_FIELD,segment 26: penalty value (all format mode)" line.long 0x170 "VENC_SWREG389,VENC segment 26: penalty value register" hexmask.long 0x170 0.--31. 1. "SWREG_FIELD,segment 26: penalty value (all format mode)" line.long 0x174 "VENC_SWREG390,VENC segment 27: intra 4x4 previous mode favor. intra 16x16mode favor. penalty value for second reference frame register" hexmask.long 0x174 0.--31. 1. "SWREG_FIELD,segment 27: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x178 "VENC_SWREG391,VENC segment 27: skip mode penalty. inter MB mode favor register" hexmask.long 0x178 0.--31. 1. "SWREG_FIELD,segment 27: skip mode penalty inter MB mode favor (all format mode)" line.long 0x17C "VENC_SWREG392,VENC segment 27: penalty value register" hexmask.long 0x17C 0.--31. 1. "SWREG_FIELD,segment 27: penalty value (all format mode)" line.long 0x180 "VENC_SWREG393,VENC segment 27: penalty value register" hexmask.long 0x180 0.--31. 1. "SWREG_FIELD,segment 27: penalty value (all format mode)" line.long 0x184 "VENC_SWREG394,VENC segment 28: intra 4x4 previous mode favor. intra 16x16mode favor. penalty value for second reference frame register" hexmask.long 0x184 0.--31. 1. "SWREG_FIELD,segment 28: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x188 "VENC_SWREG395,VENC segment 28: skip mode penalty. inter MB mode favor register" hexmask.long 0x188 0.--31. 1. "SWREG_FIELD,segment 28: skip mode penalty inter MB mode favor (all format mode)" line.long 0x18C "VENC_SWREG396,VENC segment 28: penalty value register" hexmask.long 0x18C 0.--31. 1. "SWREG_FIELD,segment 28: penalty value (all format mode)" line.long 0x190 "VENC_SWREG397,VENC segment 28: penalty value register" hexmask.long 0x190 0.--31. 1. "SWREG_FIELD,segment 28: penalty value (all format mode)" line.long 0x194 "VENC_SWREG398,VENC segment 29: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x194 0.--31. 1. "SWREG_FIELD,segment 29: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x198 "VENC_SWREG399,VENC segment 29: skip mode penalty. inter MB mode favor register" hexmask.long 0x198 0.--31. 1. "SWREG_FIELD,segment 29: skip mode penalty inter MB mode favor (all format mode)" line.long 0x19C "VENC_SWREG400,VENC segment 29: penalty value register" hexmask.long 0x19C 0.--31. 1. "SWREG_FIELD,segment 29: penalty value (all format mode)" line.long 0x1A0 "VENC_SWREG401,VENC segment 29: penalty value register" hexmask.long 0x1A0 0.--31. 1. "SWREG_FIELD,segment 29: penalty value (all format mode)" line.long 0x1A4 "VENC_SWREG402,VENC segment 30: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x1A4 0.--31. 1. "SWREG_FIELD,segment 30: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x1A8 "VENC_SWREG403,VENC segment 30: skip mode penalty. inter MB mode favor register" hexmask.long 0x1A8 0.--31. 1. "SWREG_FIELD,segment 30: skip mode penalty inter MB mode favor (all format mode)" line.long 0x1AC "VENC_SWREG404,VENC segment 30: penalty value register" hexmask.long 0x1AC 0.--31. 1. "SWREG_FIELD,segment 30: penalty value (all format mode)" line.long 0x1B0 "VENC_SWREG405,VENC segment 30: penalty value register" hexmask.long 0x1B0 0.--31. 1. "SWREG_FIELD,segment 30: penalty value (all format mode)" line.long 0x1B4 "VENC_SWREG406,VENC segment 31: intra 4x4 previous mode favor. intra 16x16 mode favor. penalty value for second reference frame register" hexmask.long 0x1B4 0.--31. 1. "SWREG_FIELD,segment 31: intra 4x4 previous mode favor intra 16x16 mode favor penalty value for second reference frame (all format mode)" line.long 0x1B8 "VENC_SWREG407,VENC segment 31: skip mode penalty. inter MB mode favor register" hexmask.long 0x1B8 0.--31. 1. "SWREG_FIELD,segment 31: skip mode penalty inter MB mode favor (all format mode)" line.long 0x1BC "VENC_SWREG408,VENC segment 31: penalty value register" hexmask.long 0x1BC 0.--31. 1. "SWREG_FIELD,segment 31: penalty value (all format mode)" line.long 0x1C0 "VENC_SWREG409,VENC segment 31: penalty value register" hexmask.long 0x1C0 0.--31. 1. "SWREG_FIELD,segment 31: penalty value (all format mode)" line.long 0x1C4 "VENC_SWREG410,VENC MBRC control. QP. offset. enable register" hexmask.long 0x1C4 0.--31. 1. "SWREG_FIELD,MBRC control (QP offset enable) (all format mode)" line.long 0x1C8 "VENC_SWREG411,VENC gain of MB QP delta. 8.8 format register" hexmask.long 0x1C8 0.--31. 1. "SWREG_FIELD,gain of MB QPdelta. 8.8 format (all format mode)" line.long 0x1CC "VENC_SWREG412,VENC average of MB complexity register" hexmask.long 0x1CC 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1D0 "VENC_SWREG413,VENC reference compression control register" hexmask.long 0x1D0 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1D4 "VENC_SWREG414,VENC base address for reference luma register" hexmask.long 0x1D4 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1D8 "VENC_SWREG415,VENC base address for reference chroma register" hexmask.long 0x1D8 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1DC "VENC_SWREG416,VENC base address for reconstructed luma register" hexmask.long 0x1DC 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1E0 "VENC_SWREG417,VENC base address for reconstructed chroma register" hexmask.long 0x1E0 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1E4 "VENC_SWREG418,VENC base address for second reference luma register" hexmask.long 0x1E4 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1E8 "VENC_SWREG419,VENC base address for second reference chroma register" hexmask.long 0x1E8 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1EC "VENC_SWREG420,VENC limit of chroma RFC buffer register" hexmask.long 0x1EC 0.--31. 1. "SWREG_FIELD,average of MB complexity (all format mode)" line.long 0x1F0 "VENC_SWREG421,VENC reorder control register" hexmask.long 0x1F0 0.--31. 1. "SWREG_FIELD,Reorder control (all format mode)" line.long 0x1F4 "VENC_SWREG422,VENC AXI read ID register" hexmask.long 0x1F4 0.--31. 1. "SWREG_FIELD,AXI Read ID (all format mode)" line.long 0x1F8 "VENC_SWREG423,VENC base address MSB for reference luma compression table register" hexmask.long 0x1F8 0.--31. 1. "SWREG_FIELD,AXI Read ID (all format mode)" line.long 0x1FC "VENC_SWREG424,VENC base address MSB for reference chroma compression table register" hexmask.long 0x1FC 0.--31. 1. "SWREG_FIELD,AXI Read ID (all format mode)" line.long 0x200 "VENC_SWREG425,VENC base address MSB for reconstructed luma compression table register" hexmask.long 0x200 0.--31. 1. "SWREG_FIELD,AXI Read ID (all format mode)" line.long 0x204 "VENC_SWREG426,VENC base address for reconstructed chroma compression table register" hexmask.long 0x204 0.--31. 1. "SWREG_FIELD,Base address for reconstructed chroma compression table (all format mode)" line.long 0x208 "VENC_SWREG427,VENC base address MSB for second reference luma compression table register" hexmask.long 0x208 0.--31. 1. "SWREG_FIELD,Base address MSB for second reference luma compression table (all format mode)" line.long 0x20C "VENC_SWREG428,VENC base address MSB for second reference chroma compression table register" hexmask.long 0x20C 0.--31. 1. "SWREG_FIELD,Base address MSB for second reference chroma compression table (all format mode)" line.long 0x210 "VENC_SWREG429,VENC high 32 bits of base address for output stream data register" hexmask.long 0x210 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for output stream data (all format mode)" line.long 0x214 "VENC_SWREG430,VENC high 32 bits of base address for output control data register" hexmask.long 0x214 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for output control data (all format mode)" line.long 0x218 "VENC_SWREG431,VENC high 32 bits of base address for reference luma register" hexmask.long 0x218 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for reference luma (all format mode)" line.long 0x21C "VENC_SWREG432,VENC high 32 bits of base address for reference chroma register" hexmask.long 0x21C 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for reference chroma (all format mode)" line.long 0x220 "VENC_SWREG433,VENC high 32 bits of base address for reconstructed luma register" hexmask.long 0x220 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for reconstructed luma (all format mode)" line.long 0x224 "VENC_SWREG434,VENC high 32 bits of base address for reconstructed chroma register" hexmask.long 0x224 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for reconstructed chroma (all format mode)" line.long 0x228 "VENC_SWREG435,VENC high 32 bits of base address for input picture luma register" hexmask.long 0x228 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for input picture luma (all format mode)" line.long 0x22C "VENC_SWREG436,VENC high 32 bits of base address for input picture cb register" hexmask.long 0x22C 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for input picture cb (all format mode)" line.long 0x230 "VENC_SWREG437,VENC high 32 bits of base address for input picture cr register" hexmask.long 0x230 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for input picture cr (all format mode)" line.long 0x234 "VENC_SWREG438,VENC high 32 bits of base address for second reference luma register" hexmask.long 0x234 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for second reference luma (all format mode)" line.long 0x238 "VENC_SWREG439,VENC high 32 bits of base address for second reference chroma register" hexmask.long 0x238 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for second reference chroma (all format mode)" line.long 0x23C "VENC_SWREG440,VENC high 32 bits of H264 secondary ref pic base register" hexmask.long 0x23C 0.--31. 1. "SWREG_FIELD,high 32 bits of H264 secondary ref pic base (all format mode)" line.long 0x240 "VENC_SWREG441,VENC high 32 bits of H264 secondary ref pic base register" hexmask.long 0x240 0.--31. 1. "SWREG_FIELD,high 32 bits of H264 secondary ref pic base (all format mode)" line.long 0x244 "VENC_SWREG442,VENC high 32 bits of base address for next pic luminance register" hexmask.long 0x244 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for next pic luminance (all format mode)" line.long 0x248 "VENC_SWREG443,VENC high 32 bits of base address for cabac context tables H264 register" hexmask.long 0x248 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for cabac context tables (H264) or probability tables (all format mode)" line.long 0x24C "VENC_SWREG444,VENC high 32 bits of base address for MV output writing register" hexmask.long 0x24C 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for MV output writing (all format mode)" group.long 0x704++0x3 line.long 0x0 "VENC_SWREG449,VENC high 32 bits of base address for output of down-scaled encoder image in YUYV 4:2:2 format register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,high 32 bits of Base address for output of down-scaled encoder image in YUYV 4:2:2 format (all format mode)" group.long 0x7C4++0x7 line.long 0x0 "VENC_SWREG497,VENC low-latency control register" hexmask.long 0x0 0.--31. 1. "SWREG_FIELD,Low latency control (all format mode)" line.long 0x4 "VENC_SWREG498,VENC encoder line buffer offset register" hexmask.long 0x4 0.--31. 1. "SWREG_FIELD,Low latency control (all format mode)" tree.end tree.end tree "VREFBUF (Voltage Reference Buffer)" base ad:0x0 tree "VREFBUF" base ad:0x46003C00 group.long 0x0++0x7 line.long 0x0 "VREFBUF_CSR,VREFBUF control and status register" bitfld.long 0x0 4.--6. "VRS,Voltage reference scale" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.." newline bitfld.long 0x0 1. "HIZ,High impedance mode" "0: V less than sub>REF+ less than /sub> pin is..,1: V less than sub>REF+ less than /sub> pin is high.." bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.." line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control register" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code" tree.end tree "VREFBUF_S" base ad:0x56003C00 group.long 0x0++0x7 line.long 0x0 "VREFBUF_CSR,VREFBUF control and status register" bitfld.long 0x0 4.--6. "VRS,Voltage reference scale" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.." newline bitfld.long 0x0 1. "HIZ,High impedance mode" "0: V less than sub>REF+ less than /sub> pin is..,1: V less than sub>REF+ less than /sub> pin is high.." bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.." line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control register" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code" tree.end tree.end tree "WWDG (System Window Watchdog)" base ad:0x0 tree "WWDG" base ad:0x40002C00 group.long 0x0++0xB line.long 0x0 "WWDG_CR,WWDG control register" bitfld.long 0x0 7. "WDGA,Activation bit" "0: Watchdog disabled,1: Watchdog enabled" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)" line.long 0x4 "WWDG_CFR,WWDG configuration register" bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0: CK counter clock (PCLK div 4096) div 1,1: CK counter clock (PCLK div 4096) div 2,2: CK counter clock (PCLK div 4096) div 4,3: CK counter clock (PCLK div 4096) div 8,4: CK counter clock (PCLK div 4096) div 16,5: CK counter clock (PCLK div 4096) div 32,6: CK counter clock (PCLK div 4096) div 64,7: CK counter clock (PCLK div 4096) div 128" bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value" line.long 0x8 "WWDG_SR,WWDG status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag" "0,1" tree.end tree "WWDG_S" base ad:0x50002C00 group.long 0x0++0xB line.long 0x0 "WWDG_CR,WWDG control register" bitfld.long 0x0 7. "WDGA,Activation bit" "0: Watchdog disabled,1: Watchdog enabled" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)" line.long 0x4 "WWDG_CFR,WWDG configuration register" bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0: CK counter clock (PCLK div 4096) div 1,1: CK counter clock (PCLK div 4096) div 2,2: CK counter clock (PCLK div 4096) div 4,3: CK counter clock (PCLK div 4096) div 8,4: CK counter clock (PCLK div 4096) div 16,5: CK counter clock (PCLK div 4096) div 32,6: CK counter clock (PCLK div 4096) div 64,7: CK counter clock (PCLK div 4096) div 128" bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value" line.long 0x8 "WWDG_SR,WWDG status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag" "0,1" tree.end tree.end tree "XSPI (Extended-SPI Interface)" base ad:0x0 tree "XSPI1" base ad:0x48025000 group.long 0x0++0x3 line.long 0x0 "XSPI_CR,XSPI control register" bitfld.long 0x0 30.--31. "MSEL,Flash select" "0: data exchanged over IO[3:0],1: data exchanged over IO[7:4],2: data exchanged over IO[11:8],3: data exchanged over IO[15:12]" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0: indirect-write mode,1: indirect-read mode,2: automatic status-polling mode,3: memory-mapped mode" newline bitfld.long 0x0 26. "NOPREF_AXI,no prefetch for signaled AXI transactions" "0: prefetch is enabled for AXI signaled transactions.,1: prefetch is disable for AXI signaled transactions." bitfld.long 0x0 25. "NOPREF,no prefetch data" "0: automatic prefetch enabled,1: automatic prefetch disabled" newline bitfld.long 0x0 24. "CSSEL,chip select selection" "0: NCS1 active,1: NCS2 active" bitfld.long 0x0 23. "PMM,Polling match mode" "0: AND-match mode SMF is set if all the unmasked..,1: OR-match mode SMF is set if any of the unmasked.." newline bitfld.long 0x0 22. "APMS,Automatic status-polling mode stop" "0: Automatic status-polling mode is stopped only by..,1: Automatic status-polling mode stops as soon as.." bitfld.long 0x0 20. "TOIE,Timeout interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline hexmask.long.byte 0x0 8.--13. 1. "FTHRES,FIFO threshold level" bitfld.long 0x0 6. "DMM,Dual-memory configuration" "0: dual-memory configuration disabled,1: dual-memory configuration enabled" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0: timeout counter is disabled and thus the..,1: timeout counter is enabled and thus the.." bitfld.long 0x0 2. "DMAEN,DMA enable" "0: DMA disabled for indirect mode,1: DMA enabled for indirect mode" newline bitfld.long 0x0 1. "ABORT,Abort request" "0: no abort requested,1: abort requested" bitfld.long 0x0 0. "EN,Enable" "0: XSPI disabled,1: XSPI enabled" group.long 0x8++0xF line.long 0x0 "XSPI_DCR1,XSPI device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0: Micron mode D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode D1/D0 ordering in DTR 8-data-bit..,2: Standard mode,3: Macronix RAM mode D1/D0 ordering in DTR..,4: HyperBus memory mode the protocol follows the..,5: HyperBus register mode addressing register..,?,?" bitfld.long 0x0 21. "EXTENDMEM,extended memory support" "0: NCS1 and NCS2 values depend from CSSEL bit in..,1: NCS1 and NCS2 values depend from the address of.." newline hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" newline bitfld.long 0x0 1. "FRCK,Free running clock" "0: CLK is not free running.,1: CLK is free running (always provided)." rbitfld.long 0x0 0. "CKMODE,clock mode 0" "0,1" line.long 0x4 "XSPI_DCR2,XSPI device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0: wrapped reads are not supported by the memory.,?,2: external memory supports wrap size of 16 bytes.,3: external memory supports wrap size of 32 bytes.,4: external memory supports wrap size of 64 bytes.,5: external memory supports wrap size of 128 bytes.,?,?" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "XSPI_DCR3,XSPI device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,NCS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "XSPI_DCR4,XSPI device configuration register 4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "XSPI_SR,XSPI status register" hexmask.long.byte 0x0 8.--14. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "XSPI_FCR,XSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "XSPI_DLR,XSPI data length register" hexmask.long 0x0 0.--31. 1. "DL,None" group.long 0x48++0x3 line.long 0x0 "XSPI_AR,XSPIaddress register" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address" group.long 0x50++0x3 line.long 0x0 "XSPI_DR,XSPI data register" hexmask.long 0x0 0.--31. 1. "DATA,None" group.long 0x80++0x3 line.long 0x0 "XSPI_PSMKR,XSPI polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "XSPI_PSMAR,XSPI polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,None" group.long 0x90++0x3 line.long 0x0 "XSPI_PIR,XSPI polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,None" group.long 0x100++0x3 line.long 0x0 "XSPI_CCR,XSPI communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,?,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x108++0x3 line.long 0x0 "XSPI_TCR,XSPI timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no delay hold,1: 1/4 cycle hold" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "XSPI_IR,XSPI instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x120++0x3 line.long 0x0 "XSPI_ABR,XSPI alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x130++0x3 line.long 0x0 "XSPI_LPTR,XSPI low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,None" group.long 0x140++0x3 line.long 0x0 "XSPI_WPCCR,XSPI wrap communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,?,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,5: alternate bytes on 16 lines,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x148++0x3 line.long 0x0 "XSPI_WPTCR,XSPI wrap timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no quarter cycle delay,1: quarter cycle delay inserted" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "XSPI_WPIR,XSPI wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,None" group.long 0x160++0x3 line.long 0x0 "XSPI_WPABR,XSPI wrap alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x180++0x3 line.long 0x0 "XSPI_WCCR,XSPI write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: Data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double-transfer rate" "0: DTR mode disabled for alternate-bytes phase,1: DTR mode enabled for alternate-bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x188++0x3 line.long 0x0 "XSPI_WTCR,XSPI write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "XSPI_WIR,XSPI write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x1A0++0x3 line.long 0x0 "XSPI_WABR,XSPI write alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x200++0x3 line.long 0x0 "XSPI_HLCR,XSPI HyperBus latency configuration register" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,None" newline bitfld.long 0x0 1. "WZL,Write zero latency" "0: latency on write accesses,1: no latency on write accesses" bitfld.long 0x0 0. "LM,Latency mode" "0: Variable initial latency,1: Fixed latency" rgroup.long 0x210++0x3 line.long 0x0 "XSPI_CALFCR,XSPI full-cycle calibration configuration" bitfld.long 0x0 31. "CALMAX,Max value" "0,1" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" newline hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x218++0x3 line.long 0x0 "XSPI_CALMR,XSPI DLL master calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x220++0x3 line.long 0x0 "XSPI_CALSOR,XSPI DLL slave output calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x228++0x3 line.long 0x0 "XSPI_CALSIR,XSPI DLL slave input calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" tree.end tree "XSPI1_S" base ad:0x58025000 group.long 0x0++0x3 line.long 0x0 "XSPI_CR,XSPI control register" bitfld.long 0x0 30.--31. "MSEL,Flash select" "0: data exchanged over IO[3:0],1: data exchanged over IO[7:4],2: data exchanged over IO[11:8],3: data exchanged over IO[15:12]" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0: indirect-write mode,1: indirect-read mode,2: automatic status-polling mode,3: memory-mapped mode" newline bitfld.long 0x0 26. "NOPREF_AXI,no prefetch for signaled AXI transactions" "0: prefetch is enabled for AXI signaled transactions.,1: prefetch is disable for AXI signaled transactions." bitfld.long 0x0 25. "NOPREF,no prefetch data" "0: automatic prefetch enabled,1: automatic prefetch disabled" newline bitfld.long 0x0 24. "CSSEL,chip select selection" "0: NCS1 active,1: NCS2 active" bitfld.long 0x0 23. "PMM,Polling match mode" "0: AND-match mode SMF is set if all the unmasked..,1: OR-match mode SMF is set if any of the unmasked.." newline bitfld.long 0x0 22. "APMS,Automatic status-polling mode stop" "0: Automatic status-polling mode is stopped only by..,1: Automatic status-polling mode stops as soon as.." bitfld.long 0x0 20. "TOIE,Timeout interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline hexmask.long.byte 0x0 8.--13. 1. "FTHRES,FIFO threshold level" bitfld.long 0x0 6. "DMM,Dual-memory configuration" "0: dual-memory configuration disabled,1: dual-memory configuration enabled" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0: timeout counter is disabled and thus the..,1: timeout counter is enabled and thus the.." bitfld.long 0x0 2. "DMAEN,DMA enable" "0: DMA disabled for indirect mode,1: DMA enabled for indirect mode" newline bitfld.long 0x0 1. "ABORT,Abort request" "0: no abort requested,1: abort requested" bitfld.long 0x0 0. "EN,Enable" "0: XSPI disabled,1: XSPI enabled" group.long 0x8++0xF line.long 0x0 "XSPI_DCR1,XSPI device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0: Micron mode D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode D1/D0 ordering in DTR 8-data-bit..,2: Standard mode,3: Macronix RAM mode D1/D0 ordering in DTR..,4: HyperBus memory mode the protocol follows the..,5: HyperBus register mode addressing register..,?,?" bitfld.long 0x0 21. "EXTENDMEM,extended memory support" "0: NCS1 and NCS2 values depend from CSSEL bit in..,1: NCS1 and NCS2 values depend from the address of.." newline hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" newline bitfld.long 0x0 1. "FRCK,Free running clock" "0: CLK is not free running.,1: CLK is free running (always provided)." rbitfld.long 0x0 0. "CKMODE,clock mode 0" "0,1" line.long 0x4 "XSPI_DCR2,XSPI device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0: wrapped reads are not supported by the memory.,?,2: external memory supports wrap size of 16 bytes.,3: external memory supports wrap size of 32 bytes.,4: external memory supports wrap size of 64 bytes.,5: external memory supports wrap size of 128 bytes.,?,?" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "XSPI_DCR3,XSPI device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,NCS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "XSPI_DCR4,XSPI device configuration register 4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "XSPI_SR,XSPI status register" hexmask.long.byte 0x0 8.--14. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "XSPI_FCR,XSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "XSPI_DLR,XSPI data length register" hexmask.long 0x0 0.--31. 1. "DL,None" group.long 0x48++0x3 line.long 0x0 "XSPI_AR,XSPIaddress register" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address" group.long 0x50++0x3 line.long 0x0 "XSPI_DR,XSPI data register" hexmask.long 0x0 0.--31. 1. "DATA,None" group.long 0x80++0x3 line.long 0x0 "XSPI_PSMKR,XSPI polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "XSPI_PSMAR,XSPI polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,None" group.long 0x90++0x3 line.long 0x0 "XSPI_PIR,XSPI polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,None" group.long 0x100++0x3 line.long 0x0 "XSPI_CCR,XSPI communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,?,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x108++0x3 line.long 0x0 "XSPI_TCR,XSPI timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no delay hold,1: 1/4 cycle hold" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "XSPI_IR,XSPI instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x120++0x3 line.long 0x0 "XSPI_ABR,XSPI alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x130++0x3 line.long 0x0 "XSPI_LPTR,XSPI low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,None" group.long 0x140++0x3 line.long 0x0 "XSPI_WPCCR,XSPI wrap communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,?,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,5: alternate bytes on 16 lines,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x148++0x3 line.long 0x0 "XSPI_WPTCR,XSPI wrap timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no quarter cycle delay,1: quarter cycle delay inserted" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "XSPI_WPIR,XSPI wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,None" group.long 0x160++0x3 line.long 0x0 "XSPI_WPABR,XSPI wrap alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x180++0x3 line.long 0x0 "XSPI_WCCR,XSPI write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: Data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double-transfer rate" "0: DTR mode disabled for alternate-bytes phase,1: DTR mode enabled for alternate-bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x188++0x3 line.long 0x0 "XSPI_WTCR,XSPI write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "XSPI_WIR,XSPI write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x1A0++0x3 line.long 0x0 "XSPI_WABR,XSPI write alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x200++0x3 line.long 0x0 "XSPI_HLCR,XSPI HyperBus latency configuration register" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,None" newline bitfld.long 0x0 1. "WZL,Write zero latency" "0: latency on write accesses,1: no latency on write accesses" bitfld.long 0x0 0. "LM,Latency mode" "0: Variable initial latency,1: Fixed latency" rgroup.long 0x210++0x3 line.long 0x0 "XSPI_CALFCR,XSPI full-cycle calibration configuration" bitfld.long 0x0 31. "CALMAX,Max value" "0,1" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" newline hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x218++0x3 line.long 0x0 "XSPI_CALMR,XSPI DLL master calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x220++0x3 line.long 0x0 "XSPI_CALSOR,XSPI DLL slave output calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x228++0x3 line.long 0x0 "XSPI_CALSIR,XSPI DLL slave input calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" tree.end tree "XSPI2" base ad:0x4802A000 group.long 0x0++0x3 line.long 0x0 "XSPI_CR,XSPI control register" bitfld.long 0x0 30.--31. "MSEL,Flash select" "0: data exchanged over IO[3:0],1: data exchanged over IO[7:4],2: data exchanged over IO[11:8],3: data exchanged over IO[15:12]" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0: indirect-write mode,1: indirect-read mode,2: automatic status-polling mode,3: memory-mapped mode" newline bitfld.long 0x0 26. "NOPREF_AXI,no prefetch for signaled AXI transactions" "0: prefetch is enabled for AXI signaled transactions.,1: prefetch is disable for AXI signaled transactions." bitfld.long 0x0 25. "NOPREF,no prefetch data" "0: automatic prefetch enabled,1: automatic prefetch disabled" newline bitfld.long 0x0 24. "CSSEL,chip select selection" "0: NCS1 active,1: NCS2 active" bitfld.long 0x0 23. "PMM,Polling match mode" "0: AND-match mode SMF is set if all the unmasked..,1: OR-match mode SMF is set if any of the unmasked.." newline bitfld.long 0x0 22. "APMS,Automatic status-polling mode stop" "0: Automatic status-polling mode is stopped only by..,1: Automatic status-polling mode stops as soon as.." bitfld.long 0x0 20. "TOIE,Timeout interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline hexmask.long.byte 0x0 8.--13. 1. "FTHRES,FIFO threshold level" bitfld.long 0x0 6. "DMM,Dual-memory configuration" "0: dual-memory configuration disabled,1: dual-memory configuration enabled" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0: timeout counter is disabled and thus the..,1: timeout counter is enabled and thus the.." bitfld.long 0x0 2. "DMAEN,DMA enable" "0: DMA disabled for indirect mode,1: DMA enabled for indirect mode" newline bitfld.long 0x0 1. "ABORT,Abort request" "0: no abort requested,1: abort requested" bitfld.long 0x0 0. "EN,Enable" "0: XSPI disabled,1: XSPI enabled" group.long 0x8++0xF line.long 0x0 "XSPI_DCR1,XSPI device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0: Micron mode D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode D1/D0 ordering in DTR 8-data-bit..,2: Standard mode,3: Macronix RAM mode D1/D0 ordering in DTR..,4: HyperBus memory mode the protocol follows the..,5: HyperBus register mode addressing register..,?,?" bitfld.long 0x0 21. "EXTENDMEM,extended memory support" "0: NCS1 and NCS2 values depend from CSSEL bit in..,1: NCS1 and NCS2 values depend from the address of.." newline hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" newline bitfld.long 0x0 1. "FRCK,Free running clock" "0: CLK is not free running.,1: CLK is free running (always provided)." rbitfld.long 0x0 0. "CKMODE,clock mode 0" "0,1" line.long 0x4 "XSPI_DCR2,XSPI device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0: wrapped reads are not supported by the memory.,?,2: external memory supports wrap size of 16 bytes.,3: external memory supports wrap size of 32 bytes.,4: external memory supports wrap size of 64 bytes.,5: external memory supports wrap size of 128 bytes.,?,?" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "XSPI_DCR3,XSPI device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,NCS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "XSPI_DCR4,XSPI device configuration register 4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "XSPI_SR,XSPI status register" hexmask.long.byte 0x0 8.--14. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "XSPI_FCR,XSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "XSPI_DLR,XSPI data length register" hexmask.long 0x0 0.--31. 1. "DL,None" group.long 0x48++0x3 line.long 0x0 "XSPI_AR,XSPIaddress register" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address" group.long 0x50++0x3 line.long 0x0 "XSPI_DR,XSPI data register" hexmask.long 0x0 0.--31. 1. "DATA,None" group.long 0x80++0x3 line.long 0x0 "XSPI_PSMKR,XSPI polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "XSPI_PSMAR,XSPI polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,None" group.long 0x90++0x3 line.long 0x0 "XSPI_PIR,XSPI polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,None" group.long 0x100++0x3 line.long 0x0 "XSPI_CCR,XSPI communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,?,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x108++0x3 line.long 0x0 "XSPI_TCR,XSPI timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no delay hold,1: 1/4 cycle hold" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "XSPI_IR,XSPI instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x120++0x3 line.long 0x0 "XSPI_ABR,XSPI alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x130++0x3 line.long 0x0 "XSPI_LPTR,XSPI low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,None" group.long 0x140++0x3 line.long 0x0 "XSPI_WPCCR,XSPI wrap communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,?,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,5: alternate bytes on 16 lines,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x148++0x3 line.long 0x0 "XSPI_WPTCR,XSPI wrap timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no quarter cycle delay,1: quarter cycle delay inserted" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "XSPI_WPIR,XSPI wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,None" group.long 0x160++0x3 line.long 0x0 "XSPI_WPABR,XSPI wrap alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x180++0x3 line.long 0x0 "XSPI_WCCR,XSPI write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: Data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double-transfer rate" "0: DTR mode disabled for alternate-bytes phase,1: DTR mode enabled for alternate-bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x188++0x3 line.long 0x0 "XSPI_WTCR,XSPI write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "XSPI_WIR,XSPI write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x1A0++0x3 line.long 0x0 "XSPI_WABR,XSPI write alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x200++0x3 line.long 0x0 "XSPI_HLCR,XSPI HyperBus latency configuration register" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,None" newline bitfld.long 0x0 1. "WZL,Write zero latency" "0: latency on write accesses,1: no latency on write accesses" bitfld.long 0x0 0. "LM,Latency mode" "0: Variable initial latency,1: Fixed latency" rgroup.long 0x210++0x3 line.long 0x0 "XSPI_CALFCR,XSPI full-cycle calibration configuration" bitfld.long 0x0 31. "CALMAX,Max value" "0,1" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" newline hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x218++0x3 line.long 0x0 "XSPI_CALMR,XSPI DLL master calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x220++0x3 line.long 0x0 "XSPI_CALSOR,XSPI DLL slave output calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x228++0x3 line.long 0x0 "XSPI_CALSIR,XSPI DLL slave input calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" tree.end tree "XSPI2_S" base ad:0x5802A000 group.long 0x0++0x3 line.long 0x0 "XSPI_CR,XSPI control register" bitfld.long 0x0 30.--31. "MSEL,Flash select" "0: data exchanged over IO[3:0],1: data exchanged over IO[7:4],2: data exchanged over IO[11:8],3: data exchanged over IO[15:12]" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0: indirect-write mode,1: indirect-read mode,2: automatic status-polling mode,3: memory-mapped mode" newline bitfld.long 0x0 26. "NOPREF_AXI,no prefetch for signaled AXI transactions" "0: prefetch is enabled for AXI signaled transactions.,1: prefetch is disable for AXI signaled transactions." bitfld.long 0x0 25. "NOPREF,no prefetch data" "0: automatic prefetch enabled,1: automatic prefetch disabled" newline bitfld.long 0x0 24. "CSSEL,chip select selection" "0: NCS1 active,1: NCS2 active" bitfld.long 0x0 23. "PMM,Polling match mode" "0: AND-match mode SMF is set if all the unmasked..,1: OR-match mode SMF is set if any of the unmasked.." newline bitfld.long 0x0 22. "APMS,Automatic status-polling mode stop" "0: Automatic status-polling mode is stopped only by..,1: Automatic status-polling mode stops as soon as.." bitfld.long 0x0 20. "TOIE,Timeout interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline hexmask.long.byte 0x0 8.--13. 1. "FTHRES,FIFO threshold level" bitfld.long 0x0 6. "DMM,Dual-memory configuration" "0: dual-memory configuration disabled,1: dual-memory configuration enabled" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0: timeout counter is disabled and thus the..,1: timeout counter is enabled and thus the.." bitfld.long 0x0 2. "DMAEN,DMA enable" "0: DMA disabled for indirect mode,1: DMA enabled for indirect mode" newline bitfld.long 0x0 1. "ABORT,Abort request" "0: no abort requested,1: abort requested" bitfld.long 0x0 0. "EN,Enable" "0: XSPI disabled,1: XSPI enabled" group.long 0x8++0xF line.long 0x0 "XSPI_DCR1,XSPI device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0: Micron mode D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode D1/D0 ordering in DTR 8-data-bit..,2: Standard mode,3: Macronix RAM mode D1/D0 ordering in DTR..,4: HyperBus memory mode the protocol follows the..,5: HyperBus register mode addressing register..,?,?" bitfld.long 0x0 21. "EXTENDMEM,extended memory support" "0: NCS1 and NCS2 values depend from CSSEL bit in..,1: NCS1 and NCS2 values depend from the address of.." newline hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" newline bitfld.long 0x0 1. "FRCK,Free running clock" "0: CLK is not free running.,1: CLK is free running (always provided)." rbitfld.long 0x0 0. "CKMODE,clock mode 0" "0,1" line.long 0x4 "XSPI_DCR2,XSPI device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0: wrapped reads are not supported by the memory.,?,2: external memory supports wrap size of 16 bytes.,3: external memory supports wrap size of 32 bytes.,4: external memory supports wrap size of 64 bytes.,5: external memory supports wrap size of 128 bytes.,?,?" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "XSPI_DCR3,XSPI device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,NCS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "XSPI_DCR4,XSPI device configuration register 4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "XSPI_SR,XSPI status register" hexmask.long.byte 0x0 8.--14. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "XSPI_FCR,XSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "XSPI_DLR,XSPI data length register" hexmask.long 0x0 0.--31. 1. "DL,None" group.long 0x48++0x3 line.long 0x0 "XSPI_AR,XSPIaddress register" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address" group.long 0x50++0x3 line.long 0x0 "XSPI_DR,XSPI data register" hexmask.long 0x0 0.--31. 1. "DATA,None" group.long 0x80++0x3 line.long 0x0 "XSPI_PSMKR,XSPI polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "XSPI_PSMAR,XSPI polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,None" group.long 0x90++0x3 line.long 0x0 "XSPI_PIR,XSPI polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,None" group.long 0x100++0x3 line.long 0x0 "XSPI_CCR,XSPI communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,?,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x108++0x3 line.long 0x0 "XSPI_TCR,XSPI timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no delay hold,1: 1/4 cycle hold" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "XSPI_IR,XSPI instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x120++0x3 line.long 0x0 "XSPI_ABR,XSPI alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x130++0x3 line.long 0x0 "XSPI_LPTR,XSPI low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,None" group.long 0x140++0x3 line.long 0x0 "XSPI_WPCCR,XSPI wrap communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,?,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,5: alternate bytes on 16 lines,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x148++0x3 line.long 0x0 "XSPI_WPTCR,XSPI wrap timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no quarter cycle delay,1: quarter cycle delay inserted" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "XSPI_WPIR,XSPI wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,None" group.long 0x160++0x3 line.long 0x0 "XSPI_WPABR,XSPI wrap alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x180++0x3 line.long 0x0 "XSPI_WCCR,XSPI write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: Data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double-transfer rate" "0: DTR mode disabled for alternate-bytes phase,1: DTR mode enabled for alternate-bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x188++0x3 line.long 0x0 "XSPI_WTCR,XSPI write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "XSPI_WIR,XSPI write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x1A0++0x3 line.long 0x0 "XSPI_WABR,XSPI write alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x200++0x3 line.long 0x0 "XSPI_HLCR,XSPI HyperBus latency configuration register" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,None" newline bitfld.long 0x0 1. "WZL,Write zero latency" "0: latency on write accesses,1: no latency on write accesses" bitfld.long 0x0 0. "LM,Latency mode" "0: Variable initial latency,1: Fixed latency" rgroup.long 0x210++0x3 line.long 0x0 "XSPI_CALFCR,XSPI full-cycle calibration configuration" bitfld.long 0x0 31. "CALMAX,Max value" "0,1" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" newline hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x218++0x3 line.long 0x0 "XSPI_CALMR,XSPI DLL master calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x220++0x3 line.long 0x0 "XSPI_CALSOR,XSPI DLL slave output calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x228++0x3 line.long 0x0 "XSPI_CALSIR,XSPI DLL slave input calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" tree.end tree "XSPI3" base ad:0x4802D000 group.long 0x0++0x3 line.long 0x0 "XSPI_CR,XSPI control register" bitfld.long 0x0 30.--31. "MSEL,Flash select" "0: data exchanged over IO[3:0],1: data exchanged over IO[7:4],2: data exchanged over IO[11:8],3: data exchanged over IO[15:12]" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0: indirect-write mode,1: indirect-read mode,2: automatic status-polling mode,3: memory-mapped mode" newline bitfld.long 0x0 26. "NOPREF_AXI,no prefetch for signaled AXI transactions" "0: prefetch is enabled for AXI signaled transactions.,1: prefetch is disable for AXI signaled transactions." bitfld.long 0x0 25. "NOPREF,no prefetch data" "0: automatic prefetch enabled,1: automatic prefetch disabled" newline bitfld.long 0x0 24. "CSSEL,chip select selection" "0: NCS1 active,1: NCS2 active" bitfld.long 0x0 23. "PMM,Polling match mode" "0: AND-match mode SMF is set if all the unmasked..,1: OR-match mode SMF is set if any of the unmasked.." newline bitfld.long 0x0 22. "APMS,Automatic status-polling mode stop" "0: Automatic status-polling mode is stopped only by..,1: Automatic status-polling mode stops as soon as.." bitfld.long 0x0 20. "TOIE,Timeout interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline hexmask.long.byte 0x0 8.--13. 1. "FTHRES,FIFO threshold level" bitfld.long 0x0 6. "DMM,Dual-memory configuration" "0: dual-memory configuration disabled,1: dual-memory configuration enabled" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0: timeout counter is disabled and thus the..,1: timeout counter is enabled and thus the.." bitfld.long 0x0 2. "DMAEN,DMA enable" "0: DMA disabled for indirect mode,1: DMA enabled for indirect mode" newline bitfld.long 0x0 1. "ABORT,Abort request" "0: no abort requested,1: abort requested" bitfld.long 0x0 0. "EN,Enable" "0: XSPI disabled,1: XSPI enabled" group.long 0x8++0xF line.long 0x0 "XSPI_DCR1,XSPI device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0: Micron mode D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode D1/D0 ordering in DTR 8-data-bit..,2: Standard mode,3: Macronix RAM mode D1/D0 ordering in DTR..,4: HyperBus memory mode the protocol follows the..,5: HyperBus register mode addressing register..,?,?" bitfld.long 0x0 21. "EXTENDMEM,extended memory support" "0: NCS1 and NCS2 values depend from CSSEL bit in..,1: NCS1 and NCS2 values depend from the address of.." newline hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" newline bitfld.long 0x0 1. "FRCK,Free running clock" "0: CLK is not free running.,1: CLK is free running (always provided)." rbitfld.long 0x0 0. "CKMODE,clock mode 0" "0,1" line.long 0x4 "XSPI_DCR2,XSPI device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0: wrapped reads are not supported by the memory.,?,2: external memory supports wrap size of 16 bytes.,3: external memory supports wrap size of 32 bytes.,4: external memory supports wrap size of 64 bytes.,5: external memory supports wrap size of 128 bytes.,?,?" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "XSPI_DCR3,XSPI device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,NCS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "XSPI_DCR4,XSPI device configuration register 4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "XSPI_SR,XSPI status register" hexmask.long.byte 0x0 8.--14. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "XSPI_FCR,XSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "XSPI_DLR,XSPI data length register" hexmask.long 0x0 0.--31. 1. "DL,None" group.long 0x48++0x3 line.long 0x0 "XSPI_AR,XSPIaddress register" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address" group.long 0x50++0x3 line.long 0x0 "XSPI_DR,XSPI data register" hexmask.long 0x0 0.--31. 1. "DATA,None" group.long 0x80++0x3 line.long 0x0 "XSPI_PSMKR,XSPI polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "XSPI_PSMAR,XSPI polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,None" group.long 0x90++0x3 line.long 0x0 "XSPI_PIR,XSPI polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,None" group.long 0x100++0x3 line.long 0x0 "XSPI_CCR,XSPI communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,?,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x108++0x3 line.long 0x0 "XSPI_TCR,XSPI timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no delay hold,1: 1/4 cycle hold" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "XSPI_IR,XSPI instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x120++0x3 line.long 0x0 "XSPI_ABR,XSPI alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x130++0x3 line.long 0x0 "XSPI_LPTR,XSPI low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,None" group.long 0x140++0x3 line.long 0x0 "XSPI_WPCCR,XSPI wrap communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,?,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,5: alternate bytes on 16 lines,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x148++0x3 line.long 0x0 "XSPI_WPTCR,XSPI wrap timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no quarter cycle delay,1: quarter cycle delay inserted" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "XSPI_WPIR,XSPI wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,None" group.long 0x160++0x3 line.long 0x0 "XSPI_WPABR,XSPI wrap alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x180++0x3 line.long 0x0 "XSPI_WCCR,XSPI write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: Data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double-transfer rate" "0: DTR mode disabled for alternate-bytes phase,1: DTR mode enabled for alternate-bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x188++0x3 line.long 0x0 "XSPI_WTCR,XSPI write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "XSPI_WIR,XSPI write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x1A0++0x3 line.long 0x0 "XSPI_WABR,XSPI write alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x200++0x3 line.long 0x0 "XSPI_HLCR,XSPI HyperBus latency configuration register" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,None" newline bitfld.long 0x0 1. "WZL,Write zero latency" "0: latency on write accesses,1: no latency on write accesses" bitfld.long 0x0 0. "LM,Latency mode" "0: Variable initial latency,1: Fixed latency" rgroup.long 0x210++0x3 line.long 0x0 "XSPI_CALFCR,XSPI full-cycle calibration configuration" bitfld.long 0x0 31. "CALMAX,Max value" "0,1" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" newline hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x218++0x3 line.long 0x0 "XSPI_CALMR,XSPI DLL master calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x220++0x3 line.long 0x0 "XSPI_CALSOR,XSPI DLL slave output calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x228++0x3 line.long 0x0 "XSPI_CALSIR,XSPI DLL slave input calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" tree.end tree "XSPI3_S" base ad:0x5802D000 group.long 0x0++0x3 line.long 0x0 "XSPI_CR,XSPI control register" bitfld.long 0x0 30.--31. "MSEL,Flash select" "0: data exchanged over IO[3:0],1: data exchanged over IO[7:4],2: data exchanged over IO[11:8],3: data exchanged over IO[15:12]" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0: indirect-write mode,1: indirect-read mode,2: automatic status-polling mode,3: memory-mapped mode" newline bitfld.long 0x0 26. "NOPREF_AXI,no prefetch for signaled AXI transactions" "0: prefetch is enabled for AXI signaled transactions.,1: prefetch is disable for AXI signaled transactions." bitfld.long 0x0 25. "NOPREF,no prefetch data" "0: automatic prefetch enabled,1: automatic prefetch disabled" newline bitfld.long 0x0 24. "CSSEL,chip select selection" "0: NCS1 active,1: NCS2 active" bitfld.long 0x0 23. "PMM,Polling match mode" "0: AND-match mode SMF is set if all the unmasked..,1: OR-match mode SMF is set if any of the unmasked.." newline bitfld.long 0x0 22. "APMS,Automatic status-polling mode stop" "0: Automatic status-polling mode is stopped only by..,1: Automatic status-polling mode stops as soon as.." bitfld.long 0x0 20. "TOIE,Timeout interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled" newline hexmask.long.byte 0x0 8.--13. 1. "FTHRES,FIFO threshold level" bitfld.long 0x0 6. "DMM,Dual-memory configuration" "0: dual-memory configuration disabled,1: dual-memory configuration enabled" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0: timeout counter is disabled and thus the..,1: timeout counter is enabled and thus the.." bitfld.long 0x0 2. "DMAEN,DMA enable" "0: DMA disabled for indirect mode,1: DMA enabled for indirect mode" newline bitfld.long 0x0 1. "ABORT,Abort request" "0: no abort requested,1: abort requested" bitfld.long 0x0 0. "EN,Enable" "0: XSPI disabled,1: XSPI enabled" group.long 0x8++0xF line.long 0x0 "XSPI_DCR1,XSPI device configuration register 1" bitfld.long 0x0 24.--26. "MTYP,Memory type" "0: Micron mode D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode D1/D0 ordering in DTR 8-data-bit..,2: Standard mode,3: Macronix RAM mode D1/D0 ordering in DTR..,4: HyperBus memory mode the protocol follows the..,5: HyperBus register mode addressing register..,?,?" bitfld.long 0x0 21. "EXTENDMEM,extended memory support" "0: NCS1 and NCS2 values depend from CSSEL bit in..,1: NCS1 and NCS2 values depend from the address of.." newline hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" newline bitfld.long 0x0 1. "FRCK,Free running clock" "0: CLK is not free running.,1: CLK is free running (always provided)." rbitfld.long 0x0 0. "CKMODE,clock mode 0" "0,1" line.long 0x4 "XSPI_DCR2,XSPI device configuration register 2" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0: wrapped reads are not supported by the memory.,?,2: external memory supports wrap size of 16 bytes.,3: external memory supports wrap size of 32 bytes.,4: external memory supports wrap size of 64 bytes.,5: external memory supports wrap size of 128 bytes.,?,?" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "XSPI_DCR3,XSPI device configuration register 3" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,NCS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "XSPI_DCR4,XSPI device configuration register 4" hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "XSPI_SR,XSPI status register" hexmask.long.byte 0x0 8.--14. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "XSPI_FCR,XSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "XSPI_DLR,XSPI data length register" hexmask.long 0x0 0.--31. 1. "DL,None" group.long 0x48++0x3 line.long 0x0 "XSPI_AR,XSPIaddress register" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address" group.long 0x50++0x3 line.long 0x0 "XSPI_DR,XSPI data register" hexmask.long 0x0 0.--31. 1. "DATA,None" group.long 0x80++0x3 line.long 0x0 "XSPI_PSMKR,XSPI polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "XSPI_PSMAR,XSPI polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,None" group.long 0x90++0x3 line.long 0x0 "XSPI_PIR,XSPI polling interval register" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,None" group.long 0x100++0x3 line.long 0x0 "XSPI_CCR,XSPI communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,?,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x108++0x3 line.long 0x0 "XSPI_TCR,XSPI timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no delay hold,1: 1/4 cycle hold" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "XSPI_IR,XSPI instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x120++0x3 line.long 0x0 "XSPI_ABR,XSPI alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x130++0x3 line.long 0x0 "XSPI_LPTR,XSPI low-power timeout register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,None" group.long 0x140++0x3 line.long 0x0 "XSPI_WPCCR,XSPI wrap communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,?,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,5: alternate bytes on 16 lines,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x148++0x3 line.long 0x0 "XSPI_WPTCR,XSPI wrap timing configuration register" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no quarter cycle delay,1: quarter cycle delay inserted" newline hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "XSPI_WPIR,XSPI wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,None" group.long 0x160++0x3 line.long 0x0 "XSPI_WPABR,XSPI wrap alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x180++0x3 line.long 0x0 "XSPI_WCCR,XSPI write communication configuration register" bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled" bitfld.long 0x0 27. "DDTR,data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase" newline bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: Data on 16 lines,?,?" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes" newline bitfld.long 0x0 19. "ABDTR,Alternate bytes double-transfer rate" "0: DTR mode disabled for alternate-bytes phase,1: DTR mode enabled for alternate-bytes phase" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,?,?,?" newline bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address" bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction" newline bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?" group.long 0x188++0x3 line.long 0x0 "XSPI_WTCR,XSPI write timing configuration register" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x190++0x3 line.long 0x0 "XSPI_WIR,XSPI write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x1A0++0x3 line.long 0x0 "XSPI_WABR,XSPI write alternate byte register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,None" group.long 0x200++0x3 line.long 0x0 "XSPI_HLCR,XSPI HyperBus latency configuration register" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,None" newline bitfld.long 0x0 1. "WZL,Write zero latency" "0: latency on write accesses,1: no latency on write accesses" bitfld.long 0x0 0. "LM,Latency mode" "0: Variable initial latency,1: Fixed latency" rgroup.long 0x210++0x3 line.long 0x0 "XSPI_CALFCR,XSPI full-cycle calibration configuration" bitfld.long 0x0 31. "CALMAX,Max value" "0,1" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" newline hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x218++0x3 line.long 0x0 "XSPI_CALMR,XSPI DLL master calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x220++0x3 line.long 0x0 "XSPI_CALSOR,XSPI DLL slave output calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" group.long 0x228++0x3 line.long 0x0 "XSPI_CALSIR,XSPI DLL slave input calibration configuration" hexmask.long.byte 0x0 16.--20. 1. "COARSE,None" hexmask.long.byte 0x0 0.--6. 1. "FINE,None" tree.end tree.end tree "XSPIM (XSPI I/O Manager)" base ad:0x0 tree "XSPIM" base ad:0x4802B400 group.long 0x0++0x3 line.long 0x0 "XSPIM_CR,XSPIM control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 6. "CSSEL_OVR_O2,Chip select selector override setting for XSPI2" "0: XSPI2 can only use NCS1 (accesses using NCS2 are..,1: XSPI2 can only use NCS2 (accesses using NCS1 are.." newline bitfld.long 0x0 5. "CSSEL_OVR_O1,Chip select selector override setting for XSPI1" "0: XSPI1 can only use NCS1 (accesses using NCS2 are..,1: XSPI1 can only use NCS2 (accesses using NCS1 are.." bitfld.long 0x0 4. "CSSEL_OVR_EN,Chip select selector override enable" "0: CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are..,1: CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are.." newline bitfld.long 0x0 1. "MODE,XSPI multiplexing mode" "0: if MUXEN = 0 direct mode if MUXEN = 1..,1: if MUXEN = 0 swapped mode if MUXEN = 1.." bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0: No multiplexing hence no arbitration,1: XSPI1 and XSPI2 are multiplexed over the same bus." tree.end tree "XSPIM_S" base ad:0x5802B400 group.long 0x0++0x3 line.long 0x0 "XSPIM_CR,XSPIM control register" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time" bitfld.long 0x0 6. "CSSEL_OVR_O2,Chip select selector override setting for XSPI2" "0: XSPI2 can only use NCS1 (accesses using NCS2 are..,1: XSPI2 can only use NCS2 (accesses using NCS1 are.." newline bitfld.long 0x0 5. "CSSEL_OVR_O1,Chip select selector override setting for XSPI1" "0: XSPI1 can only use NCS1 (accesses using NCS2 are..,1: XSPI1 can only use NCS2 (accesses using NCS1 are.." bitfld.long 0x0 4. "CSSEL_OVR_EN,Chip select selector override enable" "0: CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are..,1: CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are.." newline bitfld.long 0x0 1. "MODE,XSPI multiplexing mode" "0: if MUXEN = 0 direct mode if MUXEN = 1..,1: if MUXEN = 0 swapped mode if MUXEN = 1.." bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0: No multiplexing hence no arbitration,1: XSPI1 and XSPI2 are multiplexed over the same bus." tree.end tree.end newline AUTOINDENT.OFF